From b76e849b5c3c30d6cc82adee6a9de1aa085e4c8c Mon Sep 17 00:00:00 2001 From: Michael McLoughlin Date: Fri, 12 Nov 2021 18:35:36 -0800 Subject: [PATCH] all: AVX-512 (#217) Extends avo to support most AVX-512 instruction sets. The instruction type is extended to support suffixes. The K family of opmask registers is added to the register package, and the operand package is updated to support the new operand types. Move instruction deduction in `Load` and `Store` is extended to support KMOV* and VMOV* forms. Internal code generation packages were overhauled. Instruction database loading required various messy changes to account for the additional complexities of the AVX-512 instruction sets. The internal/api package was added to introduce a separation between instruction forms in the database, and the functions avo provides to create them. This was required since with instruction suffixes there is no longer a one-to-one mapping between instruction constructors and opcodes. AVX-512 bloated generated source code size substantially, initially increasing compilation and CI test times to an unacceptable level. Two changes were made to address this: 1. Instruction constructors in the `x86` package moved to an optab-based approach. This compiles substantially faster than the verbose code generation we had before. 2. The most verbose code-generated tests are moved under build tags and limited to a stress test mode. Stress test builds are run on schedule but not in regular CI. An example of AVX-512 accelerated 16-lane MD5 is provided to demonstrate and test the new functionality. Updates #20 #163 #229 Co-authored-by: Vaughn Iverson --- .github/workflows/packages.yml | 1 + .github/workflows/stress.yml | 50 + .golangci.yml | 5 + README.md | 1 + build/context.go | 5 +- build/global.go | 3 + build/zinstructions.go | 79650 ++++++++++++++---- build/zinstructions_test.go | 3188 + build/zmov.go | 256 +- examples/README.md | 1 + examples/md5x16/README.md | 135 + examples/md5x16/asm.go | 132 + examples/md5x16/md5x16.go | 151 + examples/md5x16/md5x16.s | 714 + examples/md5x16/md5x16_test.go | 136 + examples/md5x16/stub.go | 9 + go.mod | 2 +- internal/api/doc.go | 2 + internal/api/function.go | 177 + internal/api/function_test.go | 50 + internal/api/signature.go | 59 + internal/api/types.go | 75 + internal/api/types_test.go | 26 + internal/cmd/avogen/main.go | 18 +- internal/gen/api.go | 257 + internal/gen/asmtest.go | 49 +- internal/gen/avotypes.go | 22 - internal/gen/build.go | 34 +- internal/gen/buildtest.go | 51 + internal/gen/ctors.go | 120 +- internal/gen/ctors_test.go | 28 - internal/gen/ctorstest.go | 213 +- internal/gen/godata.go | 21 +- internal/gen/mov.go | 61 +- internal/gen/optab.go | 288 + internal/gen/signature.go | 122 - internal/gen/testing.go | 85 + internal/gen/util.go | 19 - internal/gen/util_test.go | 46 - internal/inst/stress_test.go | 9 + internal/inst/table.go | 122 +- internal/inst/table_test.go | 158 +- internal/inst/types.go | 214 +- internal/inst/types_test.go | 82 + internal/inst/ztable.go | 111133 ++++++++++++++++++++++--- internal/inst/ztable_test.go | 18 - internal/load/load.go | 495 +- internal/load/tables.go | 48 + internal/prnt/printer.go | 5 + ir/ir.go | 10 + operand/checks.go | 31 + operand/checks_test.go | 11 + printer/goasm.go | 9 +- printer/goasm_test.go | 18 + reg/collection.go | 3 + reg/reg_test.go | 10 +- reg/x86.go | 52 + script/covermain | 2 +- tests/alloc/zeroing/asm.go | 79 + tests/alloc/zeroing/doc.go | 2 + tests/alloc/zeroing/stub.go | 6 + tests/alloc/zeroing/zeroing.s | 186 + tests/alloc/zeroing/zeroing_test.go | 29 + tests/thirdparty/packages.json | 3 +- x86/gen.go | 1 + x86/inst_test.go | 100 + x86/optab.go | 130 + x86/stress_test.go | 10 + x86/zctors.go | 60336 +++++++------- x86/zctors_test.go | 65310 ++++++++++----- x86/zoptab.go | 15641 ++++ 71 files changed, 268223 insertions(+), 72302 deletions(-) create mode 100644 .github/workflows/stress.yml create mode 100644 build/zinstructions_test.go create mode 100644 examples/md5x16/README.md create mode 100644 examples/md5x16/asm.go create mode 100644 examples/md5x16/md5x16.go create mode 100644 examples/md5x16/md5x16.s create mode 100644 examples/md5x16/md5x16_test.go create mode 100644 examples/md5x16/stub.go create mode 100644 internal/api/doc.go create mode 100644 internal/api/function.go create mode 100644 internal/api/function_test.go create mode 100644 internal/api/signature.go create mode 100644 internal/api/types.go create mode 100644 internal/api/types_test.go create mode 100644 internal/gen/api.go delete mode 100644 internal/gen/avotypes.go create mode 100644 internal/gen/buildtest.go delete mode 100644 internal/gen/ctors_test.go create mode 100644 internal/gen/optab.go delete mode 100644 internal/gen/signature.go create mode 100644 internal/gen/testing.go delete mode 100644 internal/gen/util.go delete mode 100644 internal/gen/util_test.go create mode 100644 internal/inst/stress_test.go create mode 100644 internal/inst/types_test.go delete mode 100644 internal/inst/ztable_test.go create mode 100644 tests/alloc/zeroing/asm.go create mode 100644 tests/alloc/zeroing/doc.go create mode 100644 tests/alloc/zeroing/stub.go create mode 100644 tests/alloc/zeroing/zeroing.s create mode 100644 tests/alloc/zeroing/zeroing_test.go create mode 100644 x86/inst_test.go create mode 100644 x86/optab.go create mode 100644 x86/stress_test.go create mode 100644 x86/zoptab.go diff --git a/.github/workflows/packages.yml b/.github/workflows/packages.yml index 5bddbd79..ee2673f8 100644 --- a/.github/workflows/packages.yml +++ b/.github/workflows/packages.yml @@ -561,6 +561,7 @@ jobs: run: go test ./... segmentio-asm: runs-on: ubuntu-latest + if: false # skip: https://github.com/mmcloughlin/avo/issues/229 steps: - name: Install Go uses: actions/setup-go@37335c7bb261b353407cff977110895fa0b4f7d8 # v2.1.3 diff --git a/.github/workflows/stress.yml b/.github/workflows/stress.yml new file mode 100644 index 00000000..bf5037c5 --- /dev/null +++ b/.github/workflows/stress.yml @@ -0,0 +1,50 @@ +name: stress + +permissions: + contents: read + +on: + schedule: + - cron: '33 3 * * 6' + +jobs: + test: + runs-on: ubuntu-latest + env: + GOFLAGS: -tags=stress + steps: + - name: Install Go + uses: actions/setup-go@37335c7bb261b353407cff977110895fa0b4f7d8 # v2.1.3 + with: + go-version: 1.17.x + - name: Configure Go Environment + run: | + echo GOPATH=${{ runner.workspace }} >> $GITHUB_ENV + echo ${{ runner.workspace }}/bin >> $GITHUB_PATH + - name: Go Environment + run: go env + - name: Checkout code + uses: actions/checkout@5a4ac9002d0be2fb38bd78e4b4dbde5606d7042f # v2.3.4 + with: + persist-credentials: false + - name: Bootstrap + run: ./script/bootstrap + + - name: Generate + run: ./script/generate + - name: Status + run: git status + + - name: Build + run: go build ./... + - name: Test + run: go test -bench . ./... + - name: Coverage + run: ./script/coverage + + - name: Upload Stress Unit Test Coverage + uses: codecov/codecov-action@51d810878be5422784e86451c0e7c14e5860ec47 # v2.0.2 + with: + token: ${{ secrets.CODECOV_TOKEN }} + files: unittests.coverprofile + flags: stress diff --git a/.golangci.yml b/.golangci.yml index a645a3ee..4395b4cf 100644 --- a/.golangci.yml +++ b/.golangci.yml @@ -1,3 +1,6 @@ +run: + timeout: 5m + linters: enable-all: true disable: @@ -27,3 +30,5 @@ issues: - Error return value of .((os\.)?std(out|err)\..*|.*Close|.*Flush|os\.Remove(All)?|.*printf?|os\.(Un)?Setenv). is not checked # gocritic: https://github.com/go-critic/go-critic/issues/762 - ' with `(len|cap|real|imag)`' + # We want to allow all caps in certain cases. + - "ALL_CAPS in Go names" diff --git a/README.md b/README.md index f229b8ee..502610c4 100644 --- a/README.md +++ b/README.md @@ -189,6 +189,7 @@ Implementations of full algorithms: * **[sha1](examples/sha1):** [SHA-1](https://en.wikipedia.org/wiki/SHA-1) cryptographic hash. * **[fnv1a](examples/fnv1a):** [FNV-1a](https://en.wikipedia.org/wiki/Fowler%E2%80%93Noll%E2%80%93Vo_hash_function#FNV-1a_hash) hash function. * **[dot](examples/dot):** Vector dot product. +* **[md5x16](examples/md5x16):** AVX-512 accelerated [MD5](https://en.wikipedia.org/wiki/MD5). * **[geohash](examples/geohash):** Integer [geohash](https://en.wikipedia.org/wiki/Geohash) encoding. * **[stadtx](examples/stadtx):** [`StadtX` hash](https://github.com/demerphq/BeagleHash) port from [dgryski/go-stadtx](https://github.com/dgryski/go-stadtx). diff --git a/build/context.go b/build/context.go index beb4f60f..cbfc639c 100644 --- a/build/context.go +++ b/build/context.go @@ -15,6 +15,9 @@ import ( "github.com/mmcloughlin/avo/reg" ) +//go:generate avogen -output zinstructions.go build +//go:generate avogen -output zinstructions_test.go buildtest + // Context maintains state for incrementally building an avo File. type Context struct { pkg *packages.Package @@ -175,8 +178,6 @@ func (c *Context) activefunc() *ir.Function { return c.function } -//go:generate avogen -output zinstructions.go build - // StaticGlobal adds a new static data section to the file and returns a pointer to it. func (c *Context) StaticGlobal(name string) operand.Mem { c.global = ir.NewStaticGlobal(name) diff --git a/build/global.go b/build/global.go index 39b58bfe..e23da2c7 100644 --- a/build/global.go +++ b/build/global.go @@ -98,6 +98,9 @@ func YMM() reg.VecVirtual { return ctx.YMM() } // ZMM allocates and returns a 512-bit vector register. func ZMM() reg.VecVirtual { return ctx.ZMM() } +// K allocates and returns an opmask register. +func K() reg.OpmaskVirtual { return ctx.K() } + // Param returns a the named argument of the active function. func Param(name string) gotypes.Component { return ctx.Param(name) } diff --git a/build/zinstructions.go b/build/zinstructions.go index 33c2085e..418dc2e6 100644 --- a/build/zinstructions.go +++ b/build/zinstructions.go @@ -3,27 +3,32 @@ package build import ( + "github.com/mmcloughlin/avo/ir" "github.com/mmcloughlin/avo/operand" "github.com/mmcloughlin/avo/x86" ) +func (c *Context) addinstruction(i *ir.Instruction, err error) { + if err == nil { + c.Instruction(i) + } else { + c.adderror(err) + } +} + // ADCB: Add with Carry. // // Forms: // // ADCB imm8 al +// ADCB imm8 m8 // ADCB imm8 r8 -// ADCB r8 r8 // ADCB m8 r8 -// ADCB imm8 m8 // ADCB r8 m8 +// ADCB r8 r8 // Construct and append a ADCB instruction to the active function. func (c *Context) ADCB(imr, amr operand.Op) { - if inst, err := x86.ADCB(imr, amr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.ADCB(imr, amr)) } // ADCB: Add with Carry. @@ -31,11 +36,11 @@ func (c *Context) ADCB(imr, amr operand.Op) { // Forms: // // ADCB imm8 al +// ADCB imm8 m8 // ADCB imm8 r8 -// ADCB r8 r8 // ADCB m8 r8 -// ADCB imm8 m8 // ADCB r8 m8 +// ADCB r8 r8 // Construct and append a ADCB instruction to the active function. // Operates on the global context. func ADCB(imr, amr operand.Op) { ctx.ADCB(imr, amr) } @@ -45,20 +50,16 @@ func ADCB(imr, amr operand.Op) { ctx.ADCB(imr, amr) } // Forms: // // ADCL imm32 eax -// ADCL imm8 r32 +// ADCL imm32 m32 // ADCL imm32 r32 -// ADCL r32 r32 -// ADCL m32 r32 // ADCL imm8 m32 -// ADCL imm32 m32 +// ADCL imm8 r32 +// ADCL m32 r32 // ADCL r32 m32 +// ADCL r32 r32 // Construct and append a ADCL instruction to the active function. func (c *Context) ADCL(imr, emr operand.Op) { - if inst, err := x86.ADCL(imr, emr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.ADCL(imr, emr)) } // ADCL: Add with Carry. @@ -66,13 +67,13 @@ func (c *Context) ADCL(imr, emr operand.Op) { // Forms: // // ADCL imm32 eax -// ADCL imm8 r32 +// ADCL imm32 m32 // ADCL imm32 r32 -// ADCL r32 r32 -// ADCL m32 r32 // ADCL imm8 m32 -// ADCL imm32 m32 +// ADCL imm8 r32 +// ADCL m32 r32 // ADCL r32 m32 +// ADCL r32 r32 // Construct and append a ADCL instruction to the active function. // Operates on the global context. func ADCL(imr, emr operand.Op) { ctx.ADCL(imr, emr) } @@ -81,35 +82,31 @@ func ADCL(imr, emr operand.Op) { ctx.ADCL(imr, emr) } // // Forms: // +// ADCQ imm32 m64 +// ADCQ imm32 r64 // ADCQ imm32 rax +// ADCQ imm8 m64 // ADCQ imm8 r64 -// ADCQ imm32 r64 -// ADCQ r64 r64 // ADCQ m64 r64 -// ADCQ imm8 m64 -// ADCQ imm32 m64 // ADCQ r64 m64 +// ADCQ r64 r64 // Construct and append a ADCQ instruction to the active function. func (c *Context) ADCQ(imr, mr operand.Op) { - if inst, err := x86.ADCQ(imr, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.ADCQ(imr, mr)) } // ADCQ: Add with Carry. // // Forms: // +// ADCQ imm32 m64 +// ADCQ imm32 r64 // ADCQ imm32 rax +// ADCQ imm8 m64 // ADCQ imm8 r64 -// ADCQ imm32 r64 -// ADCQ r64 r64 // ADCQ m64 r64 -// ADCQ imm8 m64 -// ADCQ imm32 m64 // ADCQ r64 m64 +// ADCQ r64 r64 // Construct and append a ADCQ instruction to the active function. // Operates on the global context. func ADCQ(imr, mr operand.Op) { ctx.ADCQ(imr, mr) } @@ -119,20 +116,16 @@ func ADCQ(imr, mr operand.Op) { ctx.ADCQ(imr, mr) } // Forms: // // ADCW imm16 ax -// ADCW imm8 r16 +// ADCW imm16 m16 // ADCW imm16 r16 -// ADCW r16 r16 -// ADCW m16 r16 // ADCW imm8 m16 -// ADCW imm16 m16 +// ADCW imm8 r16 +// ADCW m16 r16 // ADCW r16 m16 +// ADCW r16 r16 // Construct and append a ADCW instruction to the active function. func (c *Context) ADCW(imr, amr operand.Op) { - if inst, err := x86.ADCW(imr, amr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.ADCW(imr, amr)) } // ADCW: Add with Carry. @@ -140,13 +133,13 @@ func (c *Context) ADCW(imr, amr operand.Op) { // Forms: // // ADCW imm16 ax -// ADCW imm8 r16 +// ADCW imm16 m16 // ADCW imm16 r16 -// ADCW r16 r16 -// ADCW m16 r16 // ADCW imm8 m16 -// ADCW imm16 m16 +// ADCW imm8 r16 +// ADCW m16 r16 // ADCW r16 m16 +// ADCW r16 r16 // Construct and append a ADCW instruction to the active function. // Operates on the global context. func ADCW(imr, amr operand.Op) { ctx.ADCW(imr, amr) } @@ -155,23 +148,19 @@ func ADCW(imr, amr operand.Op) { ctx.ADCW(imr, amr) } // // Forms: // -// ADCXL r32 r32 // ADCXL m32 r32 +// ADCXL r32 r32 // Construct and append a ADCXL instruction to the active function. func (c *Context) ADCXL(mr, r operand.Op) { - if inst, err := x86.ADCXL(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.ADCXL(mr, r)) } // ADCXL: Unsigned Integer Addition of Two Operands with Carry Flag. // // Forms: // -// ADCXL r32 r32 // ADCXL m32 r32 +// ADCXL r32 r32 // Construct and append a ADCXL instruction to the active function. // Operates on the global context. func ADCXL(mr, r operand.Op) { ctx.ADCXL(mr, r) } @@ -180,23 +169,19 @@ func ADCXL(mr, r operand.Op) { ctx.ADCXL(mr, r) } // // Forms: // -// ADCXQ r64 r64 // ADCXQ m64 r64 +// ADCXQ r64 r64 // Construct and append a ADCXQ instruction to the active function. func (c *Context) ADCXQ(mr, r operand.Op) { - if inst, err := x86.ADCXQ(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.ADCXQ(mr, r)) } // ADCXQ: Unsigned Integer Addition of Two Operands with Carry Flag. // // Forms: // -// ADCXQ r64 r64 // ADCXQ m64 r64 +// ADCXQ r64 r64 // Construct and append a ADCXQ instruction to the active function. // Operates on the global context. func ADCXQ(mr, r operand.Op) { ctx.ADCXQ(mr, r) } @@ -206,18 +191,14 @@ func ADCXQ(mr, r operand.Op) { ctx.ADCXQ(mr, r) } // Forms: // // ADDB imm8 al +// ADDB imm8 m8 // ADDB imm8 r8 -// ADDB r8 r8 // ADDB m8 r8 -// ADDB imm8 m8 // ADDB r8 m8 +// ADDB r8 r8 // Construct and append a ADDB instruction to the active function. func (c *Context) ADDB(imr, amr operand.Op) { - if inst, err := x86.ADDB(imr, amr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.ADDB(imr, amr)) } // ADDB: Add. @@ -225,11 +206,11 @@ func (c *Context) ADDB(imr, amr operand.Op) { // Forms: // // ADDB imm8 al +// ADDB imm8 m8 // ADDB imm8 r8 -// ADDB r8 r8 // ADDB m8 r8 -// ADDB imm8 m8 // ADDB r8 m8 +// ADDB r8 r8 // Construct and append a ADDB instruction to the active function. // Operates on the global context. func ADDB(imr, amr operand.Op) { ctx.ADDB(imr, amr) } @@ -239,20 +220,16 @@ func ADDB(imr, amr operand.Op) { ctx.ADDB(imr, amr) } // Forms: // // ADDL imm32 eax -// ADDL imm8 r32 +// ADDL imm32 m32 // ADDL imm32 r32 -// ADDL r32 r32 -// ADDL m32 r32 // ADDL imm8 m32 -// ADDL imm32 m32 +// ADDL imm8 r32 +// ADDL m32 r32 // ADDL r32 m32 +// ADDL r32 r32 // Construct and append a ADDL instruction to the active function. func (c *Context) ADDL(imr, emr operand.Op) { - if inst, err := x86.ADDL(imr, emr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.ADDL(imr, emr)) } // ADDL: Add. @@ -260,13 +237,13 @@ func (c *Context) ADDL(imr, emr operand.Op) { // Forms: // // ADDL imm32 eax -// ADDL imm8 r32 +// ADDL imm32 m32 // ADDL imm32 r32 -// ADDL r32 r32 -// ADDL m32 r32 // ADDL imm8 m32 -// ADDL imm32 m32 +// ADDL imm8 r32 +// ADDL m32 r32 // ADDL r32 m32 +// ADDL r32 r32 // Construct and append a ADDL instruction to the active function. // Operates on the global context. func ADDL(imr, emr operand.Op) { ctx.ADDL(imr, emr) } @@ -275,23 +252,19 @@ func ADDL(imr, emr operand.Op) { ctx.ADDL(imr, emr) } // // Forms: // -// ADDPD xmm xmm // ADDPD m128 xmm +// ADDPD xmm xmm // Construct and append a ADDPD instruction to the active function. func (c *Context) ADDPD(mx, x operand.Op) { - if inst, err := x86.ADDPD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.ADDPD(mx, x)) } // ADDPD: Add Packed Double-Precision Floating-Point Values. // // Forms: // -// ADDPD xmm xmm // ADDPD m128 xmm +// ADDPD xmm xmm // Construct and append a ADDPD instruction to the active function. // Operates on the global context. func ADDPD(mx, x operand.Op) { ctx.ADDPD(mx, x) } @@ -300,23 +273,19 @@ func ADDPD(mx, x operand.Op) { ctx.ADDPD(mx, x) } // // Forms: // -// ADDPS xmm xmm // ADDPS m128 xmm +// ADDPS xmm xmm // Construct and append a ADDPS instruction to the active function. func (c *Context) ADDPS(mx, x operand.Op) { - if inst, err := x86.ADDPS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.ADDPS(mx, x)) } // ADDPS: Add Packed Single-Precision Floating-Point Values. // // Forms: // -// ADDPS xmm xmm // ADDPS m128 xmm +// ADDPS xmm xmm // Construct and append a ADDPS instruction to the active function. // Operates on the global context. func ADDPS(mx, x operand.Op) { ctx.ADDPS(mx, x) } @@ -325,35 +294,31 @@ func ADDPS(mx, x operand.Op) { ctx.ADDPS(mx, x) } // // Forms: // +// ADDQ imm32 m64 +// ADDQ imm32 r64 // ADDQ imm32 rax +// ADDQ imm8 m64 // ADDQ imm8 r64 -// ADDQ imm32 r64 -// ADDQ r64 r64 // ADDQ m64 r64 -// ADDQ imm8 m64 -// ADDQ imm32 m64 // ADDQ r64 m64 +// ADDQ r64 r64 // Construct and append a ADDQ instruction to the active function. func (c *Context) ADDQ(imr, mr operand.Op) { - if inst, err := x86.ADDQ(imr, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.ADDQ(imr, mr)) } // ADDQ: Add. // // Forms: // +// ADDQ imm32 m64 +// ADDQ imm32 r64 // ADDQ imm32 rax +// ADDQ imm8 m64 // ADDQ imm8 r64 -// ADDQ imm32 r64 -// ADDQ r64 r64 // ADDQ m64 r64 -// ADDQ imm8 m64 -// ADDQ imm32 m64 // ADDQ r64 m64 +// ADDQ r64 r64 // Construct and append a ADDQ instruction to the active function. // Operates on the global context. func ADDQ(imr, mr operand.Op) { ctx.ADDQ(imr, mr) } @@ -362,23 +327,19 @@ func ADDQ(imr, mr operand.Op) { ctx.ADDQ(imr, mr) } // // Forms: // -// ADDSD xmm xmm // ADDSD m64 xmm +// ADDSD xmm xmm // Construct and append a ADDSD instruction to the active function. func (c *Context) ADDSD(mx, x operand.Op) { - if inst, err := x86.ADDSD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.ADDSD(mx, x)) } // ADDSD: Add Scalar Double-Precision Floating-Point Values. // // Forms: // -// ADDSD xmm xmm // ADDSD m64 xmm +// ADDSD xmm xmm // Construct and append a ADDSD instruction to the active function. // Operates on the global context. func ADDSD(mx, x operand.Op) { ctx.ADDSD(mx, x) } @@ -387,23 +348,19 @@ func ADDSD(mx, x operand.Op) { ctx.ADDSD(mx, x) } // // Forms: // -// ADDSS xmm xmm // ADDSS m32 xmm +// ADDSS xmm xmm // Construct and append a ADDSS instruction to the active function. func (c *Context) ADDSS(mx, x operand.Op) { - if inst, err := x86.ADDSS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.ADDSS(mx, x)) } // ADDSS: Add Scalar Single-Precision Floating-Point Values. // // Forms: // -// ADDSS xmm xmm // ADDSS m32 xmm +// ADDSS xmm xmm // Construct and append a ADDSS instruction to the active function. // Operates on the global context. func ADDSS(mx, x operand.Op) { ctx.ADDSS(mx, x) } @@ -412,23 +369,19 @@ func ADDSS(mx, x operand.Op) { ctx.ADDSS(mx, x) } // // Forms: // -// ADDSUBPD xmm xmm // ADDSUBPD m128 xmm +// ADDSUBPD xmm xmm // Construct and append a ADDSUBPD instruction to the active function. func (c *Context) ADDSUBPD(mx, x operand.Op) { - if inst, err := x86.ADDSUBPD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.ADDSUBPD(mx, x)) } // ADDSUBPD: Packed Double-FP Add/Subtract. // // Forms: // -// ADDSUBPD xmm xmm // ADDSUBPD m128 xmm +// ADDSUBPD xmm xmm // Construct and append a ADDSUBPD instruction to the active function. // Operates on the global context. func ADDSUBPD(mx, x operand.Op) { ctx.ADDSUBPD(mx, x) } @@ -437,23 +390,19 @@ func ADDSUBPD(mx, x operand.Op) { ctx.ADDSUBPD(mx, x) } // // Forms: // -// ADDSUBPS xmm xmm // ADDSUBPS m128 xmm +// ADDSUBPS xmm xmm // Construct and append a ADDSUBPS instruction to the active function. func (c *Context) ADDSUBPS(mx, x operand.Op) { - if inst, err := x86.ADDSUBPS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.ADDSUBPS(mx, x)) } // ADDSUBPS: Packed Single-FP Add/Subtract. // // Forms: // -// ADDSUBPS xmm xmm // ADDSUBPS m128 xmm +// ADDSUBPS xmm xmm // Construct and append a ADDSUBPS instruction to the active function. // Operates on the global context. func ADDSUBPS(mx, x operand.Op) { ctx.ADDSUBPS(mx, x) } @@ -463,20 +412,16 @@ func ADDSUBPS(mx, x operand.Op) { ctx.ADDSUBPS(mx, x) } // Forms: // // ADDW imm16 ax -// ADDW imm8 r16 +// ADDW imm16 m16 // ADDW imm16 r16 -// ADDW r16 r16 -// ADDW m16 r16 // ADDW imm8 m16 -// ADDW imm16 m16 +// ADDW imm8 r16 +// ADDW m16 r16 // ADDW r16 m16 +// ADDW r16 r16 // Construct and append a ADDW instruction to the active function. func (c *Context) ADDW(imr, amr operand.Op) { - if inst, err := x86.ADDW(imr, amr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.ADDW(imr, amr)) } // ADDW: Add. @@ -484,13 +429,13 @@ func (c *Context) ADDW(imr, amr operand.Op) { // Forms: // // ADDW imm16 ax -// ADDW imm8 r16 +// ADDW imm16 m16 // ADDW imm16 r16 -// ADDW r16 r16 -// ADDW m16 r16 // ADDW imm8 m16 -// ADDW imm16 m16 +// ADDW imm8 r16 +// ADDW m16 r16 // ADDW r16 m16 +// ADDW r16 r16 // Construct and append a ADDW instruction to the active function. // Operates on the global context. func ADDW(imr, amr operand.Op) { ctx.ADDW(imr, amr) } @@ -499,23 +444,19 @@ func ADDW(imr, amr operand.Op) { ctx.ADDW(imr, amr) } // // Forms: // -// ADOXL r32 r32 // ADOXL m32 r32 +// ADOXL r32 r32 // Construct and append a ADOXL instruction to the active function. func (c *Context) ADOXL(mr, r operand.Op) { - if inst, err := x86.ADOXL(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.ADOXL(mr, r)) } // ADOXL: Unsigned Integer Addition of Two Operands with Overflow Flag. // // Forms: // -// ADOXL r32 r32 // ADOXL m32 r32 +// ADOXL r32 r32 // Construct and append a ADOXL instruction to the active function. // Operates on the global context. func ADOXL(mr, r operand.Op) { ctx.ADOXL(mr, r) } @@ -524,23 +465,19 @@ func ADOXL(mr, r operand.Op) { ctx.ADOXL(mr, r) } // // Forms: // -// ADOXQ r64 r64 // ADOXQ m64 r64 +// ADOXQ r64 r64 // Construct and append a ADOXQ instruction to the active function. func (c *Context) ADOXQ(mr, r operand.Op) { - if inst, err := x86.ADOXQ(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.ADOXQ(mr, r)) } // ADOXQ: Unsigned Integer Addition of Two Operands with Overflow Flag. // // Forms: // -// ADOXQ r64 r64 // ADOXQ m64 r64 +// ADOXQ r64 r64 // Construct and append a ADOXQ instruction to the active function. // Operates on the global context. func ADOXQ(mr, r operand.Op) { ctx.ADOXQ(mr, r) } @@ -549,23 +486,19 @@ func ADOXQ(mr, r operand.Op) { ctx.ADOXQ(mr, r) } // // Forms: // -// AESDEC xmm xmm // AESDEC m128 xmm +// AESDEC xmm xmm // Construct and append a AESDEC instruction to the active function. func (c *Context) AESDEC(mx, x operand.Op) { - if inst, err := x86.AESDEC(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.AESDEC(mx, x)) } // AESDEC: Perform One Round of an AES Decryption Flow. // // Forms: // -// AESDEC xmm xmm // AESDEC m128 xmm +// AESDEC xmm xmm // Construct and append a AESDEC instruction to the active function. // Operates on the global context. func AESDEC(mx, x operand.Op) { ctx.AESDEC(mx, x) } @@ -574,23 +507,19 @@ func AESDEC(mx, x operand.Op) { ctx.AESDEC(mx, x) } // // Forms: // -// AESDECLAST xmm xmm // AESDECLAST m128 xmm +// AESDECLAST xmm xmm // Construct and append a AESDECLAST instruction to the active function. func (c *Context) AESDECLAST(mx, x operand.Op) { - if inst, err := x86.AESDECLAST(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.AESDECLAST(mx, x)) } // AESDECLAST: Perform Last Round of an AES Decryption Flow. // // Forms: // -// AESDECLAST xmm xmm // AESDECLAST m128 xmm +// AESDECLAST xmm xmm // Construct and append a AESDECLAST instruction to the active function. // Operates on the global context. func AESDECLAST(mx, x operand.Op) { ctx.AESDECLAST(mx, x) } @@ -599,23 +528,19 @@ func AESDECLAST(mx, x operand.Op) { ctx.AESDECLAST(mx, x) } // // Forms: // -// AESENC xmm xmm // AESENC m128 xmm +// AESENC xmm xmm // Construct and append a AESENC instruction to the active function. func (c *Context) AESENC(mx, x operand.Op) { - if inst, err := x86.AESENC(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.AESENC(mx, x)) } // AESENC: Perform One Round of an AES Encryption Flow. // // Forms: // -// AESENC xmm xmm // AESENC m128 xmm +// AESENC xmm xmm // Construct and append a AESENC instruction to the active function. // Operates on the global context. func AESENC(mx, x operand.Op) { ctx.AESENC(mx, x) } @@ -624,23 +549,19 @@ func AESENC(mx, x operand.Op) { ctx.AESENC(mx, x) } // // Forms: // -// AESENCLAST xmm xmm // AESENCLAST m128 xmm +// AESENCLAST xmm xmm // Construct and append a AESENCLAST instruction to the active function. func (c *Context) AESENCLAST(mx, x operand.Op) { - if inst, err := x86.AESENCLAST(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.AESENCLAST(mx, x)) } // AESENCLAST: Perform Last Round of an AES Encryption Flow. // // Forms: // -// AESENCLAST xmm xmm // AESENCLAST m128 xmm +// AESENCLAST xmm xmm // Construct and append a AESENCLAST instruction to the active function. // Operates on the global context. func AESENCLAST(mx, x operand.Op) { ctx.AESENCLAST(mx, x) } @@ -649,23 +570,19 @@ func AESENCLAST(mx, x operand.Op) { ctx.AESENCLAST(mx, x) } // // Forms: // -// AESIMC xmm xmm // AESIMC m128 xmm +// AESIMC xmm xmm // Construct and append a AESIMC instruction to the active function. func (c *Context) AESIMC(mx, x operand.Op) { - if inst, err := x86.AESIMC(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.AESIMC(mx, x)) } // AESIMC: Perform the AES InvMixColumn Transformation. // // Forms: // -// AESIMC xmm xmm // AESIMC m128 xmm +// AESIMC xmm xmm // Construct and append a AESIMC instruction to the active function. // Operates on the global context. func AESIMC(mx, x operand.Op) { ctx.AESIMC(mx, x) } @@ -674,23 +591,19 @@ func AESIMC(mx, x operand.Op) { ctx.AESIMC(mx, x) } // // Forms: // -// AESKEYGENASSIST imm8 xmm xmm // AESKEYGENASSIST imm8 m128 xmm +// AESKEYGENASSIST imm8 xmm xmm // Construct and append a AESKEYGENASSIST instruction to the active function. func (c *Context) AESKEYGENASSIST(i, mx, x operand.Op) { - if inst, err := x86.AESKEYGENASSIST(i, mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.AESKEYGENASSIST(i, mx, x)) } // AESKEYGENASSIST: AES Round Key Generation Assist. // // Forms: // -// AESKEYGENASSIST imm8 xmm xmm // AESKEYGENASSIST imm8 m128 xmm +// AESKEYGENASSIST imm8 xmm xmm // Construct and append a AESKEYGENASSIST instruction to the active function. // Operates on the global context. func AESKEYGENASSIST(i, mx, x operand.Op) { ctx.AESKEYGENASSIST(i, mx, x) } @@ -700,18 +613,14 @@ func AESKEYGENASSIST(i, mx, x operand.Op) { ctx.AESKEYGENASSIST(i, mx, x) } // Forms: // // ANDB imm8 al +// ANDB imm8 m8 // ANDB imm8 r8 -// ANDB r8 r8 // ANDB m8 r8 -// ANDB imm8 m8 // ANDB r8 m8 +// ANDB r8 r8 // Construct and append a ANDB instruction to the active function. func (c *Context) ANDB(imr, amr operand.Op) { - if inst, err := x86.ANDB(imr, amr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.ANDB(imr, amr)) } // ANDB: Logical AND. @@ -719,11 +628,11 @@ func (c *Context) ANDB(imr, amr operand.Op) { // Forms: // // ANDB imm8 al +// ANDB imm8 m8 // ANDB imm8 r8 -// ANDB r8 r8 // ANDB m8 r8 -// ANDB imm8 m8 // ANDB r8 m8 +// ANDB r8 r8 // Construct and append a ANDB instruction to the active function. // Operates on the global context. func ANDB(imr, amr operand.Op) { ctx.ANDB(imr, amr) } @@ -733,20 +642,16 @@ func ANDB(imr, amr operand.Op) { ctx.ANDB(imr, amr) } // Forms: // // ANDL imm32 eax -// ANDL imm8 r32 +// ANDL imm32 m32 // ANDL imm32 r32 -// ANDL r32 r32 -// ANDL m32 r32 // ANDL imm8 m32 -// ANDL imm32 m32 +// ANDL imm8 r32 +// ANDL m32 r32 // ANDL r32 m32 +// ANDL r32 r32 // Construct and append a ANDL instruction to the active function. func (c *Context) ANDL(imr, emr operand.Op) { - if inst, err := x86.ANDL(imr, emr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.ANDL(imr, emr)) } // ANDL: Logical AND. @@ -754,13 +659,13 @@ func (c *Context) ANDL(imr, emr operand.Op) { // Forms: // // ANDL imm32 eax -// ANDL imm8 r32 +// ANDL imm32 m32 // ANDL imm32 r32 -// ANDL r32 r32 -// ANDL m32 r32 // ANDL imm8 m32 -// ANDL imm32 m32 +// ANDL imm8 r32 +// ANDL m32 r32 // ANDL r32 m32 +// ANDL r32 r32 // Construct and append a ANDL instruction to the active function. // Operates on the global context. func ANDL(imr, emr operand.Op) { ctx.ANDL(imr, emr) } @@ -769,23 +674,19 @@ func ANDL(imr, emr operand.Op) { ctx.ANDL(imr, emr) } // // Forms: // -// ANDNL r32 r32 r32 // ANDNL m32 r32 r32 +// ANDNL r32 r32 r32 // Construct and append a ANDNL instruction to the active function. func (c *Context) ANDNL(mr, r, r1 operand.Op) { - if inst, err := x86.ANDNL(mr, r, r1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.ANDNL(mr, r, r1)) } // ANDNL: Logical AND NOT. // // Forms: // -// ANDNL r32 r32 r32 // ANDNL m32 r32 r32 +// ANDNL r32 r32 r32 // Construct and append a ANDNL instruction to the active function. // Operates on the global context. func ANDNL(mr, r, r1 operand.Op) { ctx.ANDNL(mr, r, r1) } @@ -794,23 +695,19 @@ func ANDNL(mr, r, r1 operand.Op) { ctx.ANDNL(mr, r, r1) } // // Forms: // -// ANDNPD xmm xmm // ANDNPD m128 xmm +// ANDNPD xmm xmm // Construct and append a ANDNPD instruction to the active function. func (c *Context) ANDNPD(mx, x operand.Op) { - if inst, err := x86.ANDNPD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.ANDNPD(mx, x)) } // ANDNPD: Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values. // // Forms: // -// ANDNPD xmm xmm // ANDNPD m128 xmm +// ANDNPD xmm xmm // Construct and append a ANDNPD instruction to the active function. // Operates on the global context. func ANDNPD(mx, x operand.Op) { ctx.ANDNPD(mx, x) } @@ -819,23 +716,19 @@ func ANDNPD(mx, x operand.Op) { ctx.ANDNPD(mx, x) } // // Forms: // -// ANDNPS xmm xmm // ANDNPS m128 xmm +// ANDNPS xmm xmm // Construct and append a ANDNPS instruction to the active function. func (c *Context) ANDNPS(mx, x operand.Op) { - if inst, err := x86.ANDNPS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.ANDNPS(mx, x)) } // ANDNPS: Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values. // // Forms: // -// ANDNPS xmm xmm // ANDNPS m128 xmm +// ANDNPS xmm xmm // Construct and append a ANDNPS instruction to the active function. // Operates on the global context. func ANDNPS(mx, x operand.Op) { ctx.ANDNPS(mx, x) } @@ -844,23 +737,19 @@ func ANDNPS(mx, x operand.Op) { ctx.ANDNPS(mx, x) } // // Forms: // -// ANDNQ r64 r64 r64 // ANDNQ m64 r64 r64 +// ANDNQ r64 r64 r64 // Construct and append a ANDNQ instruction to the active function. func (c *Context) ANDNQ(mr, r, r1 operand.Op) { - if inst, err := x86.ANDNQ(mr, r, r1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.ANDNQ(mr, r, r1)) } // ANDNQ: Logical AND NOT. // // Forms: // -// ANDNQ r64 r64 r64 // ANDNQ m64 r64 r64 +// ANDNQ r64 r64 r64 // Construct and append a ANDNQ instruction to the active function. // Operates on the global context. func ANDNQ(mr, r, r1 operand.Op) { ctx.ANDNQ(mr, r, r1) } @@ -869,23 +758,19 @@ func ANDNQ(mr, r, r1 operand.Op) { ctx.ANDNQ(mr, r, r1) } // // Forms: // -// ANDPD xmm xmm // ANDPD m128 xmm +// ANDPD xmm xmm // Construct and append a ANDPD instruction to the active function. func (c *Context) ANDPD(mx, x operand.Op) { - if inst, err := x86.ANDPD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.ANDPD(mx, x)) } // ANDPD: Bitwise Logical AND of Packed Double-Precision Floating-Point Values. // // Forms: // -// ANDPD xmm xmm // ANDPD m128 xmm +// ANDPD xmm xmm // Construct and append a ANDPD instruction to the active function. // Operates on the global context. func ANDPD(mx, x operand.Op) { ctx.ANDPD(mx, x) } @@ -894,23 +779,19 @@ func ANDPD(mx, x operand.Op) { ctx.ANDPD(mx, x) } // // Forms: // -// ANDPS xmm xmm // ANDPS m128 xmm +// ANDPS xmm xmm // Construct and append a ANDPS instruction to the active function. func (c *Context) ANDPS(mx, x operand.Op) { - if inst, err := x86.ANDPS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.ANDPS(mx, x)) } // ANDPS: Bitwise Logical AND of Packed Single-Precision Floating-Point Values. // // Forms: // -// ANDPS xmm xmm // ANDPS m128 xmm +// ANDPS xmm xmm // Construct and append a ANDPS instruction to the active function. // Operates on the global context. func ANDPS(mx, x operand.Op) { ctx.ANDPS(mx, x) } @@ -919,35 +800,31 @@ func ANDPS(mx, x operand.Op) { ctx.ANDPS(mx, x) } // // Forms: // +// ANDQ imm32 m64 +// ANDQ imm32 r64 // ANDQ imm32 rax +// ANDQ imm8 m64 // ANDQ imm8 r64 -// ANDQ imm32 r64 -// ANDQ r64 r64 // ANDQ m64 r64 -// ANDQ imm8 m64 -// ANDQ imm32 m64 // ANDQ r64 m64 +// ANDQ r64 r64 // Construct and append a ANDQ instruction to the active function. func (c *Context) ANDQ(imr, mr operand.Op) { - if inst, err := x86.ANDQ(imr, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.ANDQ(imr, mr)) } // ANDQ: Logical AND. // // Forms: // +// ANDQ imm32 m64 +// ANDQ imm32 r64 // ANDQ imm32 rax +// ANDQ imm8 m64 // ANDQ imm8 r64 -// ANDQ imm32 r64 -// ANDQ r64 r64 // ANDQ m64 r64 -// ANDQ imm8 m64 -// ANDQ imm32 m64 // ANDQ r64 m64 +// ANDQ r64 r64 // Construct and append a ANDQ instruction to the active function. // Operates on the global context. func ANDQ(imr, mr operand.Op) { ctx.ANDQ(imr, mr) } @@ -957,20 +834,16 @@ func ANDQ(imr, mr operand.Op) { ctx.ANDQ(imr, mr) } // Forms: // // ANDW imm16 ax -// ANDW imm8 r16 +// ANDW imm16 m16 // ANDW imm16 r16 -// ANDW r16 r16 -// ANDW m16 r16 // ANDW imm8 m16 -// ANDW imm16 m16 +// ANDW imm8 r16 +// ANDW m16 r16 // ANDW r16 m16 +// ANDW r16 r16 // Construct and append a ANDW instruction to the active function. func (c *Context) ANDW(imr, amr operand.Op) { - if inst, err := x86.ANDW(imr, amr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.ANDW(imr, amr)) } // ANDW: Logical AND. @@ -978,13 +851,13 @@ func (c *Context) ANDW(imr, amr operand.Op) { // Forms: // // ANDW imm16 ax -// ANDW imm8 r16 +// ANDW imm16 m16 // ANDW imm16 r16 -// ANDW r16 r16 -// ANDW m16 r16 // ANDW imm8 m16 -// ANDW imm16 m16 +// ANDW imm8 r16 +// ANDW m16 r16 // ANDW r16 m16 +// ANDW r16 r16 // Construct and append a ANDW instruction to the active function. // Operates on the global context. func ANDW(imr, amr operand.Op) { ctx.ANDW(imr, amr) } @@ -993,23 +866,19 @@ func ANDW(imr, amr operand.Op) { ctx.ANDW(imr, amr) } // // Forms: // -// BEXTRL r32 r32 r32 // BEXTRL r32 m32 r32 +// BEXTRL r32 r32 r32 // Construct and append a BEXTRL instruction to the active function. func (c *Context) BEXTRL(r, mr, r1 operand.Op) { - if inst, err := x86.BEXTRL(r, mr, r1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BEXTRL(r, mr, r1)) } // BEXTRL: Bit Field Extract. // // Forms: // -// BEXTRL r32 r32 r32 // BEXTRL r32 m32 r32 +// BEXTRL r32 r32 r32 // Construct and append a BEXTRL instruction to the active function. // Operates on the global context. func BEXTRL(r, mr, r1 operand.Op) { ctx.BEXTRL(r, mr, r1) } @@ -1018,23 +887,19 @@ func BEXTRL(r, mr, r1 operand.Op) { ctx.BEXTRL(r, mr, r1) } // // Forms: // -// BEXTRQ r64 r64 r64 // BEXTRQ r64 m64 r64 +// BEXTRQ r64 r64 r64 // Construct and append a BEXTRQ instruction to the active function. func (c *Context) BEXTRQ(r, mr, r1 operand.Op) { - if inst, err := x86.BEXTRQ(r, mr, r1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BEXTRQ(r, mr, r1)) } // BEXTRQ: Bit Field Extract. // // Forms: // -// BEXTRQ r64 r64 r64 // BEXTRQ r64 m64 r64 +// BEXTRQ r64 r64 r64 // Construct and append a BEXTRQ instruction to the active function. // Operates on the global context. func BEXTRQ(r, mr, r1 operand.Op) { ctx.BEXTRQ(r, mr, r1) } @@ -1043,23 +908,19 @@ func BEXTRQ(r, mr, r1 operand.Op) { ctx.BEXTRQ(r, mr, r1) } // // Forms: // -// BLENDPD imm8 xmm xmm // BLENDPD imm8 m128 xmm +// BLENDPD imm8 xmm xmm // Construct and append a BLENDPD instruction to the active function. func (c *Context) BLENDPD(i, mx, x operand.Op) { - if inst, err := x86.BLENDPD(i, mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BLENDPD(i, mx, x)) } // BLENDPD: Blend Packed Double Precision Floating-Point Values. // // Forms: // -// BLENDPD imm8 xmm xmm // BLENDPD imm8 m128 xmm +// BLENDPD imm8 xmm xmm // Construct and append a BLENDPD instruction to the active function. // Operates on the global context. func BLENDPD(i, mx, x operand.Op) { ctx.BLENDPD(i, mx, x) } @@ -1068,23 +929,19 @@ func BLENDPD(i, mx, x operand.Op) { ctx.BLENDPD(i, mx, x) } // // Forms: // -// BLENDPS imm8 xmm xmm // BLENDPS imm8 m128 xmm +// BLENDPS imm8 xmm xmm // Construct and append a BLENDPS instruction to the active function. func (c *Context) BLENDPS(i, mx, x operand.Op) { - if inst, err := x86.BLENDPS(i, mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BLENDPS(i, mx, x)) } // BLENDPS: Blend Packed Single Precision Floating-Point Values. // // Forms: // -// BLENDPS imm8 xmm xmm // BLENDPS imm8 m128 xmm +// BLENDPS imm8 xmm xmm // Construct and append a BLENDPS instruction to the active function. // Operates on the global context. func BLENDPS(i, mx, x operand.Op) { ctx.BLENDPS(i, mx, x) } @@ -1093,23 +950,19 @@ func BLENDPS(i, mx, x operand.Op) { ctx.BLENDPS(i, mx, x) } // // Forms: // -// BLENDVPD xmm0 xmm xmm // BLENDVPD xmm0 m128 xmm +// BLENDVPD xmm0 xmm xmm // Construct and append a BLENDVPD instruction to the active function. func (c *Context) BLENDVPD(x, mx, x1 operand.Op) { - if inst, err := x86.BLENDVPD(x, mx, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BLENDVPD(x, mx, x1)) } // BLENDVPD: Variable Blend Packed Double Precision Floating-Point Values. // // Forms: // -// BLENDVPD xmm0 xmm xmm // BLENDVPD xmm0 m128 xmm +// BLENDVPD xmm0 xmm xmm // Construct and append a BLENDVPD instruction to the active function. // Operates on the global context. func BLENDVPD(x, mx, x1 operand.Op) { ctx.BLENDVPD(x, mx, x1) } @@ -1118,23 +971,19 @@ func BLENDVPD(x, mx, x1 operand.Op) { ctx.BLENDVPD(x, mx, x1) } // // Forms: // -// BLENDVPS xmm0 xmm xmm // BLENDVPS xmm0 m128 xmm +// BLENDVPS xmm0 xmm xmm // Construct and append a BLENDVPS instruction to the active function. func (c *Context) BLENDVPS(x, mx, x1 operand.Op) { - if inst, err := x86.BLENDVPS(x, mx, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BLENDVPS(x, mx, x1)) } // BLENDVPS: Variable Blend Packed Single Precision Floating-Point Values. // // Forms: // -// BLENDVPS xmm0 xmm xmm // BLENDVPS xmm0 m128 xmm +// BLENDVPS xmm0 xmm xmm // Construct and append a BLENDVPS instruction to the active function. // Operates on the global context. func BLENDVPS(x, mx, x1 operand.Op) { ctx.BLENDVPS(x, mx, x1) } @@ -1143,23 +992,19 @@ func BLENDVPS(x, mx, x1 operand.Op) { ctx.BLENDVPS(x, mx, x1) } // // Forms: // -// BLSIL r32 r32 // BLSIL m32 r32 +// BLSIL r32 r32 // Construct and append a BLSIL instruction to the active function. func (c *Context) BLSIL(mr, r operand.Op) { - if inst, err := x86.BLSIL(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BLSIL(mr, r)) } // BLSIL: Isolate Lowest Set Bit. // // Forms: // -// BLSIL r32 r32 // BLSIL m32 r32 +// BLSIL r32 r32 // Construct and append a BLSIL instruction to the active function. // Operates on the global context. func BLSIL(mr, r operand.Op) { ctx.BLSIL(mr, r) } @@ -1168,23 +1013,19 @@ func BLSIL(mr, r operand.Op) { ctx.BLSIL(mr, r) } // // Forms: // -// BLSIQ r64 r64 // BLSIQ m64 r64 +// BLSIQ r64 r64 // Construct and append a BLSIQ instruction to the active function. func (c *Context) BLSIQ(mr, r operand.Op) { - if inst, err := x86.BLSIQ(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BLSIQ(mr, r)) } // BLSIQ: Isolate Lowest Set Bit. // // Forms: // -// BLSIQ r64 r64 // BLSIQ m64 r64 +// BLSIQ r64 r64 // Construct and append a BLSIQ instruction to the active function. // Operates on the global context. func BLSIQ(mr, r operand.Op) { ctx.BLSIQ(mr, r) } @@ -1193,23 +1034,19 @@ func BLSIQ(mr, r operand.Op) { ctx.BLSIQ(mr, r) } // // Forms: // -// BLSMSKL r32 r32 // BLSMSKL m32 r32 +// BLSMSKL r32 r32 // Construct and append a BLSMSKL instruction to the active function. func (c *Context) BLSMSKL(mr, r operand.Op) { - if inst, err := x86.BLSMSKL(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BLSMSKL(mr, r)) } // BLSMSKL: Mask From Lowest Set Bit. // // Forms: // -// BLSMSKL r32 r32 // BLSMSKL m32 r32 +// BLSMSKL r32 r32 // Construct and append a BLSMSKL instruction to the active function. // Operates on the global context. func BLSMSKL(mr, r operand.Op) { ctx.BLSMSKL(mr, r) } @@ -1218,23 +1055,19 @@ func BLSMSKL(mr, r operand.Op) { ctx.BLSMSKL(mr, r) } // // Forms: // -// BLSMSKQ r64 r64 // BLSMSKQ m64 r64 +// BLSMSKQ r64 r64 // Construct and append a BLSMSKQ instruction to the active function. func (c *Context) BLSMSKQ(mr, r operand.Op) { - if inst, err := x86.BLSMSKQ(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BLSMSKQ(mr, r)) } // BLSMSKQ: Mask From Lowest Set Bit. // // Forms: // -// BLSMSKQ r64 r64 // BLSMSKQ m64 r64 +// BLSMSKQ r64 r64 // Construct and append a BLSMSKQ instruction to the active function. // Operates on the global context. func BLSMSKQ(mr, r operand.Op) { ctx.BLSMSKQ(mr, r) } @@ -1243,23 +1076,19 @@ func BLSMSKQ(mr, r operand.Op) { ctx.BLSMSKQ(mr, r) } // // Forms: // -// BLSRL r32 r32 // BLSRL m32 r32 +// BLSRL r32 r32 // Construct and append a BLSRL instruction to the active function. func (c *Context) BLSRL(mr, r operand.Op) { - if inst, err := x86.BLSRL(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BLSRL(mr, r)) } // BLSRL: Reset Lowest Set Bit. // // Forms: // -// BLSRL r32 r32 // BLSRL m32 r32 +// BLSRL r32 r32 // Construct and append a BLSRL instruction to the active function. // Operates on the global context. func BLSRL(mr, r operand.Op) { ctx.BLSRL(mr, r) } @@ -1268,23 +1097,19 @@ func BLSRL(mr, r operand.Op) { ctx.BLSRL(mr, r) } // // Forms: // -// BLSRQ r64 r64 // BLSRQ m64 r64 +// BLSRQ r64 r64 // Construct and append a BLSRQ instruction to the active function. func (c *Context) BLSRQ(mr, r operand.Op) { - if inst, err := x86.BLSRQ(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BLSRQ(mr, r)) } // BLSRQ: Reset Lowest Set Bit. // // Forms: // -// BLSRQ r64 r64 // BLSRQ m64 r64 +// BLSRQ r64 r64 // Construct and append a BLSRQ instruction to the active function. // Operates on the global context. func BLSRQ(mr, r operand.Op) { ctx.BLSRQ(mr, r) } @@ -1293,23 +1118,19 @@ func BLSRQ(mr, r operand.Op) { ctx.BLSRQ(mr, r) } // // Forms: // -// BSFL r32 r32 // BSFL m32 r32 +// BSFL r32 r32 // Construct and append a BSFL instruction to the active function. func (c *Context) BSFL(mr, r operand.Op) { - if inst, err := x86.BSFL(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BSFL(mr, r)) } // BSFL: Bit Scan Forward. // // Forms: // -// BSFL r32 r32 // BSFL m32 r32 +// BSFL r32 r32 // Construct and append a BSFL instruction to the active function. // Operates on the global context. func BSFL(mr, r operand.Op) { ctx.BSFL(mr, r) } @@ -1318,23 +1139,19 @@ func BSFL(mr, r operand.Op) { ctx.BSFL(mr, r) } // // Forms: // -// BSFQ r64 r64 // BSFQ m64 r64 +// BSFQ r64 r64 // Construct and append a BSFQ instruction to the active function. func (c *Context) BSFQ(mr, r operand.Op) { - if inst, err := x86.BSFQ(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BSFQ(mr, r)) } // BSFQ: Bit Scan Forward. // // Forms: // -// BSFQ r64 r64 // BSFQ m64 r64 +// BSFQ r64 r64 // Construct and append a BSFQ instruction to the active function. // Operates on the global context. func BSFQ(mr, r operand.Op) { ctx.BSFQ(mr, r) } @@ -1343,23 +1160,19 @@ func BSFQ(mr, r operand.Op) { ctx.BSFQ(mr, r) } // // Forms: // -// BSFW r16 r16 // BSFW m16 r16 +// BSFW r16 r16 // Construct and append a BSFW instruction to the active function. func (c *Context) BSFW(mr, r operand.Op) { - if inst, err := x86.BSFW(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BSFW(mr, r)) } // BSFW: Bit Scan Forward. // // Forms: // -// BSFW r16 r16 // BSFW m16 r16 +// BSFW r16 r16 // Construct and append a BSFW instruction to the active function. // Operates on the global context. func BSFW(mr, r operand.Op) { ctx.BSFW(mr, r) } @@ -1368,23 +1181,19 @@ func BSFW(mr, r operand.Op) { ctx.BSFW(mr, r) } // // Forms: // -// BSRL r32 r32 // BSRL m32 r32 +// BSRL r32 r32 // Construct and append a BSRL instruction to the active function. func (c *Context) BSRL(mr, r operand.Op) { - if inst, err := x86.BSRL(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BSRL(mr, r)) } // BSRL: Bit Scan Reverse. // // Forms: // -// BSRL r32 r32 // BSRL m32 r32 +// BSRL r32 r32 // Construct and append a BSRL instruction to the active function. // Operates on the global context. func BSRL(mr, r operand.Op) { ctx.BSRL(mr, r) } @@ -1393,23 +1202,19 @@ func BSRL(mr, r operand.Op) { ctx.BSRL(mr, r) } // // Forms: // -// BSRQ r64 r64 // BSRQ m64 r64 +// BSRQ r64 r64 // Construct and append a BSRQ instruction to the active function. func (c *Context) BSRQ(mr, r operand.Op) { - if inst, err := x86.BSRQ(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BSRQ(mr, r)) } // BSRQ: Bit Scan Reverse. // // Forms: // -// BSRQ r64 r64 // BSRQ m64 r64 +// BSRQ r64 r64 // Construct and append a BSRQ instruction to the active function. // Operates on the global context. func BSRQ(mr, r operand.Op) { ctx.BSRQ(mr, r) } @@ -1418,23 +1223,19 @@ func BSRQ(mr, r operand.Op) { ctx.BSRQ(mr, r) } // // Forms: // -// BSRW r16 r16 // BSRW m16 r16 +// BSRW r16 r16 // Construct and append a BSRW instruction to the active function. func (c *Context) BSRW(mr, r operand.Op) { - if inst, err := x86.BSRW(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BSRW(mr, r)) } // BSRW: Bit Scan Reverse. // // Forms: // -// BSRW r16 r16 // BSRW m16 r16 +// BSRW r16 r16 // Construct and append a BSRW instruction to the active function. // Operates on the global context. func BSRW(mr, r operand.Op) { ctx.BSRW(mr, r) } @@ -1446,11 +1247,7 @@ func BSRW(mr, r operand.Op) { ctx.BSRW(mr, r) } // BSWAPL r32 // Construct and append a BSWAPL instruction to the active function. func (c *Context) BSWAPL(r operand.Op) { - if inst, err := x86.BSWAPL(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BSWAPL(r)) } // BSWAPL: Byte Swap. @@ -1469,11 +1266,7 @@ func BSWAPL(r operand.Op) { ctx.BSWAPL(r) } // BSWAPQ r64 // Construct and append a BSWAPQ instruction to the active function. func (c *Context) BSWAPQ(r operand.Op) { - if inst, err := x86.BSWAPQ(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BSWAPQ(r)) } // BSWAPQ: Byte Swap. @@ -1489,27 +1282,23 @@ func BSWAPQ(r operand.Op) { ctx.BSWAPQ(r) } // // Forms: // -// BTCL imm8 r32 -// BTCL r32 r32 // BTCL imm8 m32 +// BTCL imm8 r32 // BTCL r32 m32 +// BTCL r32 r32 // Construct and append a BTCL instruction to the active function. func (c *Context) BTCL(ir, mr operand.Op) { - if inst, err := x86.BTCL(ir, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BTCL(ir, mr)) } // BTCL: Bit Test and Complement. // // Forms: // -// BTCL imm8 r32 -// BTCL r32 r32 // BTCL imm8 m32 +// BTCL imm8 r32 // BTCL r32 m32 +// BTCL r32 r32 // Construct and append a BTCL instruction to the active function. // Operates on the global context. func BTCL(ir, mr operand.Op) { ctx.BTCL(ir, mr) } @@ -1518,27 +1307,23 @@ func BTCL(ir, mr operand.Op) { ctx.BTCL(ir, mr) } // // Forms: // -// BTCQ imm8 r64 -// BTCQ r64 r64 // BTCQ imm8 m64 +// BTCQ imm8 r64 // BTCQ r64 m64 +// BTCQ r64 r64 // Construct and append a BTCQ instruction to the active function. func (c *Context) BTCQ(ir, mr operand.Op) { - if inst, err := x86.BTCQ(ir, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BTCQ(ir, mr)) } // BTCQ: Bit Test and Complement. // // Forms: // -// BTCQ imm8 r64 -// BTCQ r64 r64 // BTCQ imm8 m64 +// BTCQ imm8 r64 // BTCQ r64 m64 +// BTCQ r64 r64 // Construct and append a BTCQ instruction to the active function. // Operates on the global context. func BTCQ(ir, mr operand.Op) { ctx.BTCQ(ir, mr) } @@ -1547,27 +1332,23 @@ func BTCQ(ir, mr operand.Op) { ctx.BTCQ(ir, mr) } // // Forms: // -// BTCW imm8 r16 -// BTCW r16 r16 // BTCW imm8 m16 +// BTCW imm8 r16 // BTCW r16 m16 +// BTCW r16 r16 // Construct and append a BTCW instruction to the active function. func (c *Context) BTCW(ir, mr operand.Op) { - if inst, err := x86.BTCW(ir, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BTCW(ir, mr)) } // BTCW: Bit Test and Complement. // // Forms: // -// BTCW imm8 r16 -// BTCW r16 r16 // BTCW imm8 m16 +// BTCW imm8 r16 // BTCW r16 m16 +// BTCW r16 r16 // Construct and append a BTCW instruction to the active function. // Operates on the global context. func BTCW(ir, mr operand.Op) { ctx.BTCW(ir, mr) } @@ -1576,27 +1357,23 @@ func BTCW(ir, mr operand.Op) { ctx.BTCW(ir, mr) } // // Forms: // -// BTL imm8 r32 -// BTL r32 r32 // BTL imm8 m32 +// BTL imm8 r32 // BTL r32 m32 +// BTL r32 r32 // Construct and append a BTL instruction to the active function. func (c *Context) BTL(ir, mr operand.Op) { - if inst, err := x86.BTL(ir, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BTL(ir, mr)) } // BTL: Bit Test. // // Forms: // -// BTL imm8 r32 -// BTL r32 r32 // BTL imm8 m32 +// BTL imm8 r32 // BTL r32 m32 +// BTL r32 r32 // Construct and append a BTL instruction to the active function. // Operates on the global context. func BTL(ir, mr operand.Op) { ctx.BTL(ir, mr) } @@ -1605,27 +1382,23 @@ func BTL(ir, mr operand.Op) { ctx.BTL(ir, mr) } // // Forms: // -// BTQ imm8 r64 -// BTQ r64 r64 // BTQ imm8 m64 +// BTQ imm8 r64 // BTQ r64 m64 +// BTQ r64 r64 // Construct and append a BTQ instruction to the active function. func (c *Context) BTQ(ir, mr operand.Op) { - if inst, err := x86.BTQ(ir, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BTQ(ir, mr)) } // BTQ: Bit Test. // // Forms: // -// BTQ imm8 r64 -// BTQ r64 r64 // BTQ imm8 m64 +// BTQ imm8 r64 // BTQ r64 m64 +// BTQ r64 r64 // Construct and append a BTQ instruction to the active function. // Operates on the global context. func BTQ(ir, mr operand.Op) { ctx.BTQ(ir, mr) } @@ -1634,27 +1407,23 @@ func BTQ(ir, mr operand.Op) { ctx.BTQ(ir, mr) } // // Forms: // -// BTRL imm8 r32 -// BTRL r32 r32 // BTRL imm8 m32 +// BTRL imm8 r32 // BTRL r32 m32 +// BTRL r32 r32 // Construct and append a BTRL instruction to the active function. func (c *Context) BTRL(ir, mr operand.Op) { - if inst, err := x86.BTRL(ir, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BTRL(ir, mr)) } // BTRL: Bit Test and Reset. // // Forms: // -// BTRL imm8 r32 -// BTRL r32 r32 // BTRL imm8 m32 +// BTRL imm8 r32 // BTRL r32 m32 +// BTRL r32 r32 // Construct and append a BTRL instruction to the active function. // Operates on the global context. func BTRL(ir, mr operand.Op) { ctx.BTRL(ir, mr) } @@ -1663,27 +1432,23 @@ func BTRL(ir, mr operand.Op) { ctx.BTRL(ir, mr) } // // Forms: // -// BTRQ imm8 r64 -// BTRQ r64 r64 // BTRQ imm8 m64 +// BTRQ imm8 r64 // BTRQ r64 m64 +// BTRQ r64 r64 // Construct and append a BTRQ instruction to the active function. func (c *Context) BTRQ(ir, mr operand.Op) { - if inst, err := x86.BTRQ(ir, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BTRQ(ir, mr)) } // BTRQ: Bit Test and Reset. // // Forms: // -// BTRQ imm8 r64 -// BTRQ r64 r64 // BTRQ imm8 m64 +// BTRQ imm8 r64 // BTRQ r64 m64 +// BTRQ r64 r64 // Construct and append a BTRQ instruction to the active function. // Operates on the global context. func BTRQ(ir, mr operand.Op) { ctx.BTRQ(ir, mr) } @@ -1692,27 +1457,23 @@ func BTRQ(ir, mr operand.Op) { ctx.BTRQ(ir, mr) } // // Forms: // -// BTRW imm8 r16 -// BTRW r16 r16 // BTRW imm8 m16 +// BTRW imm8 r16 // BTRW r16 m16 +// BTRW r16 r16 // Construct and append a BTRW instruction to the active function. func (c *Context) BTRW(ir, mr operand.Op) { - if inst, err := x86.BTRW(ir, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BTRW(ir, mr)) } // BTRW: Bit Test and Reset. // // Forms: // -// BTRW imm8 r16 -// BTRW r16 r16 // BTRW imm8 m16 +// BTRW imm8 r16 // BTRW r16 m16 +// BTRW r16 r16 // Construct and append a BTRW instruction to the active function. // Operates on the global context. func BTRW(ir, mr operand.Op) { ctx.BTRW(ir, mr) } @@ -1721,27 +1482,23 @@ func BTRW(ir, mr operand.Op) { ctx.BTRW(ir, mr) } // // Forms: // -// BTSL imm8 r32 -// BTSL r32 r32 // BTSL imm8 m32 +// BTSL imm8 r32 // BTSL r32 m32 +// BTSL r32 r32 // Construct and append a BTSL instruction to the active function. func (c *Context) BTSL(ir, mr operand.Op) { - if inst, err := x86.BTSL(ir, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BTSL(ir, mr)) } // BTSL: Bit Test and Set. // // Forms: // -// BTSL imm8 r32 -// BTSL r32 r32 // BTSL imm8 m32 +// BTSL imm8 r32 // BTSL r32 m32 +// BTSL r32 r32 // Construct and append a BTSL instruction to the active function. // Operates on the global context. func BTSL(ir, mr operand.Op) { ctx.BTSL(ir, mr) } @@ -1750,27 +1507,23 @@ func BTSL(ir, mr operand.Op) { ctx.BTSL(ir, mr) } // // Forms: // -// BTSQ imm8 r64 -// BTSQ r64 r64 // BTSQ imm8 m64 +// BTSQ imm8 r64 // BTSQ r64 m64 +// BTSQ r64 r64 // Construct and append a BTSQ instruction to the active function. func (c *Context) BTSQ(ir, mr operand.Op) { - if inst, err := x86.BTSQ(ir, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BTSQ(ir, mr)) } // BTSQ: Bit Test and Set. // // Forms: // -// BTSQ imm8 r64 -// BTSQ r64 r64 // BTSQ imm8 m64 +// BTSQ imm8 r64 // BTSQ r64 m64 +// BTSQ r64 r64 // Construct and append a BTSQ instruction to the active function. // Operates on the global context. func BTSQ(ir, mr operand.Op) { ctx.BTSQ(ir, mr) } @@ -1779,27 +1532,23 @@ func BTSQ(ir, mr operand.Op) { ctx.BTSQ(ir, mr) } // // Forms: // -// BTSW imm8 r16 -// BTSW r16 r16 // BTSW imm8 m16 +// BTSW imm8 r16 // BTSW r16 m16 +// BTSW r16 r16 // Construct and append a BTSW instruction to the active function. func (c *Context) BTSW(ir, mr operand.Op) { - if inst, err := x86.BTSW(ir, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BTSW(ir, mr)) } // BTSW: Bit Test and Set. // // Forms: // -// BTSW imm8 r16 -// BTSW r16 r16 // BTSW imm8 m16 +// BTSW imm8 r16 // BTSW r16 m16 +// BTSW r16 r16 // Construct and append a BTSW instruction to the active function. // Operates on the global context. func BTSW(ir, mr operand.Op) { ctx.BTSW(ir, mr) } @@ -1808,27 +1557,23 @@ func BTSW(ir, mr operand.Op) { ctx.BTSW(ir, mr) } // // Forms: // -// BTW imm8 r16 -// BTW r16 r16 // BTW imm8 m16 +// BTW imm8 r16 // BTW r16 m16 +// BTW r16 r16 // Construct and append a BTW instruction to the active function. func (c *Context) BTW(ir, mr operand.Op) { - if inst, err := x86.BTW(ir, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BTW(ir, mr)) } // BTW: Bit Test. // // Forms: // -// BTW imm8 r16 -// BTW r16 r16 // BTW imm8 m16 +// BTW imm8 r16 // BTW r16 m16 +// BTW r16 r16 // Construct and append a BTW instruction to the active function. // Operates on the global context. func BTW(ir, mr operand.Op) { ctx.BTW(ir, mr) } @@ -1837,23 +1582,19 @@ func BTW(ir, mr operand.Op) { ctx.BTW(ir, mr) } // // Forms: // -// BZHIL r32 r32 r32 // BZHIL r32 m32 r32 +// BZHIL r32 r32 r32 // Construct and append a BZHIL instruction to the active function. func (c *Context) BZHIL(r, mr, r1 operand.Op) { - if inst, err := x86.BZHIL(r, mr, r1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BZHIL(r, mr, r1)) } // BZHIL: Zero High Bits Starting with Specified Bit Position. // // Forms: // -// BZHIL r32 r32 r32 // BZHIL r32 m32 r32 +// BZHIL r32 r32 r32 // Construct and append a BZHIL instruction to the active function. // Operates on the global context. func BZHIL(r, mr, r1 operand.Op) { ctx.BZHIL(r, mr, r1) } @@ -1862,23 +1603,19 @@ func BZHIL(r, mr, r1 operand.Op) { ctx.BZHIL(r, mr, r1) } // // Forms: // -// BZHIQ r64 r64 r64 // BZHIQ r64 m64 r64 +// BZHIQ r64 r64 r64 // Construct and append a BZHIQ instruction to the active function. func (c *Context) BZHIQ(r, mr, r1 operand.Op) { - if inst, err := x86.BZHIQ(r, mr, r1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.BZHIQ(r, mr, r1)) } // BZHIQ: Zero High Bits Starting with Specified Bit Position. // // Forms: // -// BZHIQ r64 r64 r64 // BZHIQ r64 m64 r64 +// BZHIQ r64 r64 r64 // Construct and append a BZHIQ instruction to the active function. // Operates on the global context. func BZHIQ(r, mr, r1 operand.Op) { ctx.BZHIQ(r, mr, r1) } @@ -1890,11 +1627,7 @@ func BZHIQ(r, mr, r1 operand.Op) { ctx.BZHIQ(r, mr, r1) } // CALL rel32 // Construct and append a CALL instruction to the active function. func (c *Context) CALL(r operand.Op) { - if inst, err := x86.CALL(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CALL(r)) } // CALL: Call Procedure. @@ -1913,11 +1646,7 @@ func CALL(r operand.Op) { ctx.CALL(r) } // CBW // Construct and append a CBW instruction to the active function. func (c *Context) CBW() { - if inst, err := x86.CBW(); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CBW()) } // CBW: Convert Byte to Word. @@ -1936,11 +1665,7 @@ func CBW() { ctx.CBW() } // CDQ // Construct and append a CDQ instruction to the active function. func (c *Context) CDQ() { - if inst, err := x86.CDQ(); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CDQ()) } // CDQ: Convert Doubleword to Quadword. @@ -1959,11 +1684,7 @@ func CDQ() { ctx.CDQ() } // CDQE // Construct and append a CDQE instruction to the active function. func (c *Context) CDQE() { - if inst, err := x86.CDQE(); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CDQE()) } // CDQE: Convert Doubleword to Quadword. @@ -1982,11 +1703,7 @@ func CDQE() { ctx.CDQE() } // CLC // Construct and append a CLC instruction to the active function. func (c *Context) CLC() { - if inst, err := x86.CLC(); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CLC()) } // CLC: Clear Carry Flag. @@ -2005,11 +1722,7 @@ func CLC() { ctx.CLC() } // CLD // Construct and append a CLD instruction to the active function. func (c *Context) CLD() { - if inst, err := x86.CLD(); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CLD()) } // CLD: Clear Direction Flag. @@ -2028,11 +1741,7 @@ func CLD() { ctx.CLD() } // CLFLUSH m8 // Construct and append a CLFLUSH instruction to the active function. func (c *Context) CLFLUSH(m operand.Op) { - if inst, err := x86.CLFLUSH(m); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CLFLUSH(m)) } // CLFLUSH: Flush Cache Line. @@ -2051,11 +1760,7 @@ func CLFLUSH(m operand.Op) { ctx.CLFLUSH(m) } // CLFLUSHOPT m8 // Construct and append a CLFLUSHOPT instruction to the active function. func (c *Context) CLFLUSHOPT(m operand.Op) { - if inst, err := x86.CLFLUSHOPT(m); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CLFLUSHOPT(m)) } // CLFLUSHOPT: Flush Cache Line Optimized. @@ -2074,11 +1779,7 @@ func CLFLUSHOPT(m operand.Op) { ctx.CLFLUSHOPT(m) } // CMC // Construct and append a CMC instruction to the active function. func (c *Context) CMC() { - if inst, err := x86.CMC(); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMC()) } // CMC: Complement Carry Flag. @@ -2094,23 +1795,19 @@ func CMC() { ctx.CMC() } // // Forms: // -// CMOVLCC r32 r32 // CMOVLCC m32 r32 +// CMOVLCC r32 r32 // Construct and append a CMOVLCC instruction to the active function. func (c *Context) CMOVLCC(mr, r operand.Op) { - if inst, err := x86.CMOVLCC(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVLCC(mr, r)) } // CMOVLCC: Move if above or equal (CF == 0). // // Forms: // -// CMOVLCC r32 r32 // CMOVLCC m32 r32 +// CMOVLCC r32 r32 // Construct and append a CMOVLCC instruction to the active function. // Operates on the global context. func CMOVLCC(mr, r operand.Op) { ctx.CMOVLCC(mr, r) } @@ -2119,23 +1816,19 @@ func CMOVLCC(mr, r operand.Op) { ctx.CMOVLCC(mr, r) } // // Forms: // -// CMOVLCS r32 r32 // CMOVLCS m32 r32 +// CMOVLCS r32 r32 // Construct and append a CMOVLCS instruction to the active function. func (c *Context) CMOVLCS(mr, r operand.Op) { - if inst, err := x86.CMOVLCS(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVLCS(mr, r)) } // CMOVLCS: Move if below (CF == 1). // // Forms: // -// CMOVLCS r32 r32 // CMOVLCS m32 r32 +// CMOVLCS r32 r32 // Construct and append a CMOVLCS instruction to the active function. // Operates on the global context. func CMOVLCS(mr, r operand.Op) { ctx.CMOVLCS(mr, r) } @@ -2144,23 +1837,19 @@ func CMOVLCS(mr, r operand.Op) { ctx.CMOVLCS(mr, r) } // // Forms: // -// CMOVLEQ r32 r32 // CMOVLEQ m32 r32 +// CMOVLEQ r32 r32 // Construct and append a CMOVLEQ instruction to the active function. func (c *Context) CMOVLEQ(mr, r operand.Op) { - if inst, err := x86.CMOVLEQ(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVLEQ(mr, r)) } // CMOVLEQ: Move if equal (ZF == 1). // // Forms: // -// CMOVLEQ r32 r32 // CMOVLEQ m32 r32 +// CMOVLEQ r32 r32 // Construct and append a CMOVLEQ instruction to the active function. // Operates on the global context. func CMOVLEQ(mr, r operand.Op) { ctx.CMOVLEQ(mr, r) } @@ -2169,23 +1858,19 @@ func CMOVLEQ(mr, r operand.Op) { ctx.CMOVLEQ(mr, r) } // // Forms: // -// CMOVLGE r32 r32 // CMOVLGE m32 r32 +// CMOVLGE r32 r32 // Construct and append a CMOVLGE instruction to the active function. func (c *Context) CMOVLGE(mr, r operand.Op) { - if inst, err := x86.CMOVLGE(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVLGE(mr, r)) } // CMOVLGE: Move if greater or equal (SF == OF). // // Forms: // -// CMOVLGE r32 r32 // CMOVLGE m32 r32 +// CMOVLGE r32 r32 // Construct and append a CMOVLGE instruction to the active function. // Operates on the global context. func CMOVLGE(mr, r operand.Op) { ctx.CMOVLGE(mr, r) } @@ -2194,23 +1879,19 @@ func CMOVLGE(mr, r operand.Op) { ctx.CMOVLGE(mr, r) } // // Forms: // -// CMOVLGT r32 r32 // CMOVLGT m32 r32 +// CMOVLGT r32 r32 // Construct and append a CMOVLGT instruction to the active function. func (c *Context) CMOVLGT(mr, r operand.Op) { - if inst, err := x86.CMOVLGT(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVLGT(mr, r)) } // CMOVLGT: Move if greater (ZF == 0 and SF == OF). // // Forms: // -// CMOVLGT r32 r32 // CMOVLGT m32 r32 +// CMOVLGT r32 r32 // Construct and append a CMOVLGT instruction to the active function. // Operates on the global context. func CMOVLGT(mr, r operand.Op) { ctx.CMOVLGT(mr, r) } @@ -2219,23 +1900,19 @@ func CMOVLGT(mr, r operand.Op) { ctx.CMOVLGT(mr, r) } // // Forms: // -// CMOVLHI r32 r32 // CMOVLHI m32 r32 +// CMOVLHI r32 r32 // Construct and append a CMOVLHI instruction to the active function. func (c *Context) CMOVLHI(mr, r operand.Op) { - if inst, err := x86.CMOVLHI(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVLHI(mr, r)) } // CMOVLHI: Move if above (CF == 0 and ZF == 0). // // Forms: // -// CMOVLHI r32 r32 // CMOVLHI m32 r32 +// CMOVLHI r32 r32 // Construct and append a CMOVLHI instruction to the active function. // Operates on the global context. func CMOVLHI(mr, r operand.Op) { ctx.CMOVLHI(mr, r) } @@ -2244,23 +1921,19 @@ func CMOVLHI(mr, r operand.Op) { ctx.CMOVLHI(mr, r) } // // Forms: // -// CMOVLLE r32 r32 // CMOVLLE m32 r32 +// CMOVLLE r32 r32 // Construct and append a CMOVLLE instruction to the active function. func (c *Context) CMOVLLE(mr, r operand.Op) { - if inst, err := x86.CMOVLLE(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVLLE(mr, r)) } // CMOVLLE: Move if less or equal (ZF == 1 or SF != OF). // // Forms: // -// CMOVLLE r32 r32 // CMOVLLE m32 r32 +// CMOVLLE r32 r32 // Construct and append a CMOVLLE instruction to the active function. // Operates on the global context. func CMOVLLE(mr, r operand.Op) { ctx.CMOVLLE(mr, r) } @@ -2269,23 +1942,19 @@ func CMOVLLE(mr, r operand.Op) { ctx.CMOVLLE(mr, r) } // // Forms: // -// CMOVLLS r32 r32 // CMOVLLS m32 r32 +// CMOVLLS r32 r32 // Construct and append a CMOVLLS instruction to the active function. func (c *Context) CMOVLLS(mr, r operand.Op) { - if inst, err := x86.CMOVLLS(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVLLS(mr, r)) } // CMOVLLS: Move if below or equal (CF == 1 or ZF == 1). // // Forms: // -// CMOVLLS r32 r32 // CMOVLLS m32 r32 +// CMOVLLS r32 r32 // Construct and append a CMOVLLS instruction to the active function. // Operates on the global context. func CMOVLLS(mr, r operand.Op) { ctx.CMOVLLS(mr, r) } @@ -2294,23 +1963,19 @@ func CMOVLLS(mr, r operand.Op) { ctx.CMOVLLS(mr, r) } // // Forms: // -// CMOVLLT r32 r32 // CMOVLLT m32 r32 +// CMOVLLT r32 r32 // Construct and append a CMOVLLT instruction to the active function. func (c *Context) CMOVLLT(mr, r operand.Op) { - if inst, err := x86.CMOVLLT(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVLLT(mr, r)) } // CMOVLLT: Move if less (SF != OF). // // Forms: // -// CMOVLLT r32 r32 // CMOVLLT m32 r32 +// CMOVLLT r32 r32 // Construct and append a CMOVLLT instruction to the active function. // Operates on the global context. func CMOVLLT(mr, r operand.Op) { ctx.CMOVLLT(mr, r) } @@ -2319,23 +1984,19 @@ func CMOVLLT(mr, r operand.Op) { ctx.CMOVLLT(mr, r) } // // Forms: // -// CMOVLMI r32 r32 // CMOVLMI m32 r32 +// CMOVLMI r32 r32 // Construct and append a CMOVLMI instruction to the active function. func (c *Context) CMOVLMI(mr, r operand.Op) { - if inst, err := x86.CMOVLMI(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVLMI(mr, r)) } // CMOVLMI: Move if sign (SF == 1). // // Forms: // -// CMOVLMI r32 r32 // CMOVLMI m32 r32 +// CMOVLMI r32 r32 // Construct and append a CMOVLMI instruction to the active function. // Operates on the global context. func CMOVLMI(mr, r operand.Op) { ctx.CMOVLMI(mr, r) } @@ -2344,23 +2005,19 @@ func CMOVLMI(mr, r operand.Op) { ctx.CMOVLMI(mr, r) } // // Forms: // -// CMOVLNE r32 r32 // CMOVLNE m32 r32 +// CMOVLNE r32 r32 // Construct and append a CMOVLNE instruction to the active function. func (c *Context) CMOVLNE(mr, r operand.Op) { - if inst, err := x86.CMOVLNE(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVLNE(mr, r)) } // CMOVLNE: Move if not equal (ZF == 0). // // Forms: // -// CMOVLNE r32 r32 // CMOVLNE m32 r32 +// CMOVLNE r32 r32 // Construct and append a CMOVLNE instruction to the active function. // Operates on the global context. func CMOVLNE(mr, r operand.Op) { ctx.CMOVLNE(mr, r) } @@ -2369,23 +2026,19 @@ func CMOVLNE(mr, r operand.Op) { ctx.CMOVLNE(mr, r) } // // Forms: // -// CMOVLOC r32 r32 // CMOVLOC m32 r32 +// CMOVLOC r32 r32 // Construct and append a CMOVLOC instruction to the active function. func (c *Context) CMOVLOC(mr, r operand.Op) { - if inst, err := x86.CMOVLOC(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVLOC(mr, r)) } // CMOVLOC: Move if not overflow (OF == 0). // // Forms: // -// CMOVLOC r32 r32 // CMOVLOC m32 r32 +// CMOVLOC r32 r32 // Construct and append a CMOVLOC instruction to the active function. // Operates on the global context. func CMOVLOC(mr, r operand.Op) { ctx.CMOVLOC(mr, r) } @@ -2394,23 +2047,19 @@ func CMOVLOC(mr, r operand.Op) { ctx.CMOVLOC(mr, r) } // // Forms: // -// CMOVLOS r32 r32 // CMOVLOS m32 r32 +// CMOVLOS r32 r32 // Construct and append a CMOVLOS instruction to the active function. func (c *Context) CMOVLOS(mr, r operand.Op) { - if inst, err := x86.CMOVLOS(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVLOS(mr, r)) } // CMOVLOS: Move if overflow (OF == 1). // // Forms: // -// CMOVLOS r32 r32 // CMOVLOS m32 r32 +// CMOVLOS r32 r32 // Construct and append a CMOVLOS instruction to the active function. // Operates on the global context. func CMOVLOS(mr, r operand.Op) { ctx.CMOVLOS(mr, r) } @@ -2419,23 +2068,19 @@ func CMOVLOS(mr, r operand.Op) { ctx.CMOVLOS(mr, r) } // // Forms: // -// CMOVLPC r32 r32 // CMOVLPC m32 r32 +// CMOVLPC r32 r32 // Construct and append a CMOVLPC instruction to the active function. func (c *Context) CMOVLPC(mr, r operand.Op) { - if inst, err := x86.CMOVLPC(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVLPC(mr, r)) } // CMOVLPC: Move if not parity (PF == 0). // // Forms: // -// CMOVLPC r32 r32 // CMOVLPC m32 r32 +// CMOVLPC r32 r32 // Construct and append a CMOVLPC instruction to the active function. // Operates on the global context. func CMOVLPC(mr, r operand.Op) { ctx.CMOVLPC(mr, r) } @@ -2444,23 +2089,19 @@ func CMOVLPC(mr, r operand.Op) { ctx.CMOVLPC(mr, r) } // // Forms: // -// CMOVLPL r32 r32 // CMOVLPL m32 r32 +// CMOVLPL r32 r32 // Construct and append a CMOVLPL instruction to the active function. func (c *Context) CMOVLPL(mr, r operand.Op) { - if inst, err := x86.CMOVLPL(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVLPL(mr, r)) } // CMOVLPL: Move if not sign (SF == 0). // // Forms: // -// CMOVLPL r32 r32 // CMOVLPL m32 r32 +// CMOVLPL r32 r32 // Construct and append a CMOVLPL instruction to the active function. // Operates on the global context. func CMOVLPL(mr, r operand.Op) { ctx.CMOVLPL(mr, r) } @@ -2469,23 +2110,19 @@ func CMOVLPL(mr, r operand.Op) { ctx.CMOVLPL(mr, r) } // // Forms: // -// CMOVLPS r32 r32 // CMOVLPS m32 r32 +// CMOVLPS r32 r32 // Construct and append a CMOVLPS instruction to the active function. func (c *Context) CMOVLPS(mr, r operand.Op) { - if inst, err := x86.CMOVLPS(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVLPS(mr, r)) } // CMOVLPS: Move if parity (PF == 1). // // Forms: // -// CMOVLPS r32 r32 // CMOVLPS m32 r32 +// CMOVLPS r32 r32 // Construct and append a CMOVLPS instruction to the active function. // Operates on the global context. func CMOVLPS(mr, r operand.Op) { ctx.CMOVLPS(mr, r) } @@ -2494,23 +2131,19 @@ func CMOVLPS(mr, r operand.Op) { ctx.CMOVLPS(mr, r) } // // Forms: // -// CMOVQCC r64 r64 // CMOVQCC m64 r64 +// CMOVQCC r64 r64 // Construct and append a CMOVQCC instruction to the active function. func (c *Context) CMOVQCC(mr, r operand.Op) { - if inst, err := x86.CMOVQCC(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVQCC(mr, r)) } // CMOVQCC: Move if above or equal (CF == 0). // // Forms: // -// CMOVQCC r64 r64 // CMOVQCC m64 r64 +// CMOVQCC r64 r64 // Construct and append a CMOVQCC instruction to the active function. // Operates on the global context. func CMOVQCC(mr, r operand.Op) { ctx.CMOVQCC(mr, r) } @@ -2519,23 +2152,19 @@ func CMOVQCC(mr, r operand.Op) { ctx.CMOVQCC(mr, r) } // // Forms: // -// CMOVQCS r64 r64 // CMOVQCS m64 r64 +// CMOVQCS r64 r64 // Construct and append a CMOVQCS instruction to the active function. func (c *Context) CMOVQCS(mr, r operand.Op) { - if inst, err := x86.CMOVQCS(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVQCS(mr, r)) } // CMOVQCS: Move if below (CF == 1). // // Forms: // -// CMOVQCS r64 r64 // CMOVQCS m64 r64 +// CMOVQCS r64 r64 // Construct and append a CMOVQCS instruction to the active function. // Operates on the global context. func CMOVQCS(mr, r operand.Op) { ctx.CMOVQCS(mr, r) } @@ -2544,23 +2173,19 @@ func CMOVQCS(mr, r operand.Op) { ctx.CMOVQCS(mr, r) } // // Forms: // -// CMOVQEQ r64 r64 // CMOVQEQ m64 r64 +// CMOVQEQ r64 r64 // Construct and append a CMOVQEQ instruction to the active function. func (c *Context) CMOVQEQ(mr, r operand.Op) { - if inst, err := x86.CMOVQEQ(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVQEQ(mr, r)) } // CMOVQEQ: Move if equal (ZF == 1). // // Forms: // -// CMOVQEQ r64 r64 // CMOVQEQ m64 r64 +// CMOVQEQ r64 r64 // Construct and append a CMOVQEQ instruction to the active function. // Operates on the global context. func CMOVQEQ(mr, r operand.Op) { ctx.CMOVQEQ(mr, r) } @@ -2569,23 +2194,19 @@ func CMOVQEQ(mr, r operand.Op) { ctx.CMOVQEQ(mr, r) } // // Forms: // -// CMOVQGE r64 r64 // CMOVQGE m64 r64 +// CMOVQGE r64 r64 // Construct and append a CMOVQGE instruction to the active function. func (c *Context) CMOVQGE(mr, r operand.Op) { - if inst, err := x86.CMOVQGE(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVQGE(mr, r)) } // CMOVQGE: Move if greater or equal (SF == OF). // // Forms: // -// CMOVQGE r64 r64 // CMOVQGE m64 r64 +// CMOVQGE r64 r64 // Construct and append a CMOVQGE instruction to the active function. // Operates on the global context. func CMOVQGE(mr, r operand.Op) { ctx.CMOVQGE(mr, r) } @@ -2594,23 +2215,19 @@ func CMOVQGE(mr, r operand.Op) { ctx.CMOVQGE(mr, r) } // // Forms: // -// CMOVQGT r64 r64 // CMOVQGT m64 r64 +// CMOVQGT r64 r64 // Construct and append a CMOVQGT instruction to the active function. func (c *Context) CMOVQGT(mr, r operand.Op) { - if inst, err := x86.CMOVQGT(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVQGT(mr, r)) } // CMOVQGT: Move if greater (ZF == 0 and SF == OF). // // Forms: // -// CMOVQGT r64 r64 // CMOVQGT m64 r64 +// CMOVQGT r64 r64 // Construct and append a CMOVQGT instruction to the active function. // Operates on the global context. func CMOVQGT(mr, r operand.Op) { ctx.CMOVQGT(mr, r) } @@ -2619,23 +2236,19 @@ func CMOVQGT(mr, r operand.Op) { ctx.CMOVQGT(mr, r) } // // Forms: // -// CMOVQHI r64 r64 // CMOVQHI m64 r64 +// CMOVQHI r64 r64 // Construct and append a CMOVQHI instruction to the active function. func (c *Context) CMOVQHI(mr, r operand.Op) { - if inst, err := x86.CMOVQHI(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVQHI(mr, r)) } // CMOVQHI: Move if above (CF == 0 and ZF == 0). // // Forms: // -// CMOVQHI r64 r64 // CMOVQHI m64 r64 +// CMOVQHI r64 r64 // Construct and append a CMOVQHI instruction to the active function. // Operates on the global context. func CMOVQHI(mr, r operand.Op) { ctx.CMOVQHI(mr, r) } @@ -2644,23 +2257,19 @@ func CMOVQHI(mr, r operand.Op) { ctx.CMOVQHI(mr, r) } // // Forms: // -// CMOVQLE r64 r64 // CMOVQLE m64 r64 +// CMOVQLE r64 r64 // Construct and append a CMOVQLE instruction to the active function. func (c *Context) CMOVQLE(mr, r operand.Op) { - if inst, err := x86.CMOVQLE(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVQLE(mr, r)) } // CMOVQLE: Move if less or equal (ZF == 1 or SF != OF). // // Forms: // -// CMOVQLE r64 r64 // CMOVQLE m64 r64 +// CMOVQLE r64 r64 // Construct and append a CMOVQLE instruction to the active function. // Operates on the global context. func CMOVQLE(mr, r operand.Op) { ctx.CMOVQLE(mr, r) } @@ -2669,23 +2278,19 @@ func CMOVQLE(mr, r operand.Op) { ctx.CMOVQLE(mr, r) } // // Forms: // -// CMOVQLS r64 r64 // CMOVQLS m64 r64 +// CMOVQLS r64 r64 // Construct and append a CMOVQLS instruction to the active function. func (c *Context) CMOVQLS(mr, r operand.Op) { - if inst, err := x86.CMOVQLS(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVQLS(mr, r)) } // CMOVQLS: Move if below or equal (CF == 1 or ZF == 1). // // Forms: // -// CMOVQLS r64 r64 // CMOVQLS m64 r64 +// CMOVQLS r64 r64 // Construct and append a CMOVQLS instruction to the active function. // Operates on the global context. func CMOVQLS(mr, r operand.Op) { ctx.CMOVQLS(mr, r) } @@ -2694,23 +2299,19 @@ func CMOVQLS(mr, r operand.Op) { ctx.CMOVQLS(mr, r) } // // Forms: // -// CMOVQLT r64 r64 // CMOVQLT m64 r64 +// CMOVQLT r64 r64 // Construct and append a CMOVQLT instruction to the active function. func (c *Context) CMOVQLT(mr, r operand.Op) { - if inst, err := x86.CMOVQLT(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVQLT(mr, r)) } // CMOVQLT: Move if less (SF != OF). // // Forms: // -// CMOVQLT r64 r64 // CMOVQLT m64 r64 +// CMOVQLT r64 r64 // Construct and append a CMOVQLT instruction to the active function. // Operates on the global context. func CMOVQLT(mr, r operand.Op) { ctx.CMOVQLT(mr, r) } @@ -2719,23 +2320,19 @@ func CMOVQLT(mr, r operand.Op) { ctx.CMOVQLT(mr, r) } // // Forms: // -// CMOVQMI r64 r64 // CMOVQMI m64 r64 +// CMOVQMI r64 r64 // Construct and append a CMOVQMI instruction to the active function. func (c *Context) CMOVQMI(mr, r operand.Op) { - if inst, err := x86.CMOVQMI(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVQMI(mr, r)) } // CMOVQMI: Move if sign (SF == 1). // // Forms: // -// CMOVQMI r64 r64 // CMOVQMI m64 r64 +// CMOVQMI r64 r64 // Construct and append a CMOVQMI instruction to the active function. // Operates on the global context. func CMOVQMI(mr, r operand.Op) { ctx.CMOVQMI(mr, r) } @@ -2744,23 +2341,19 @@ func CMOVQMI(mr, r operand.Op) { ctx.CMOVQMI(mr, r) } // // Forms: // -// CMOVQNE r64 r64 // CMOVQNE m64 r64 +// CMOVQNE r64 r64 // Construct and append a CMOVQNE instruction to the active function. func (c *Context) CMOVQNE(mr, r operand.Op) { - if inst, err := x86.CMOVQNE(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVQNE(mr, r)) } // CMOVQNE: Move if not equal (ZF == 0). // // Forms: // -// CMOVQNE r64 r64 // CMOVQNE m64 r64 +// CMOVQNE r64 r64 // Construct and append a CMOVQNE instruction to the active function. // Operates on the global context. func CMOVQNE(mr, r operand.Op) { ctx.CMOVQNE(mr, r) } @@ -2769,23 +2362,19 @@ func CMOVQNE(mr, r operand.Op) { ctx.CMOVQNE(mr, r) } // // Forms: // -// CMOVQOC r64 r64 // CMOVQOC m64 r64 +// CMOVQOC r64 r64 // Construct and append a CMOVQOC instruction to the active function. func (c *Context) CMOVQOC(mr, r operand.Op) { - if inst, err := x86.CMOVQOC(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVQOC(mr, r)) } // CMOVQOC: Move if not overflow (OF == 0). // // Forms: // -// CMOVQOC r64 r64 // CMOVQOC m64 r64 +// CMOVQOC r64 r64 // Construct and append a CMOVQOC instruction to the active function. // Operates on the global context. func CMOVQOC(mr, r operand.Op) { ctx.CMOVQOC(mr, r) } @@ -2794,23 +2383,19 @@ func CMOVQOC(mr, r operand.Op) { ctx.CMOVQOC(mr, r) } // // Forms: // -// CMOVQOS r64 r64 // CMOVQOS m64 r64 +// CMOVQOS r64 r64 // Construct and append a CMOVQOS instruction to the active function. func (c *Context) CMOVQOS(mr, r operand.Op) { - if inst, err := x86.CMOVQOS(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVQOS(mr, r)) } // CMOVQOS: Move if overflow (OF == 1). // // Forms: // -// CMOVQOS r64 r64 // CMOVQOS m64 r64 +// CMOVQOS r64 r64 // Construct and append a CMOVQOS instruction to the active function. // Operates on the global context. func CMOVQOS(mr, r operand.Op) { ctx.CMOVQOS(mr, r) } @@ -2819,23 +2404,19 @@ func CMOVQOS(mr, r operand.Op) { ctx.CMOVQOS(mr, r) } // // Forms: // -// CMOVQPC r64 r64 // CMOVQPC m64 r64 +// CMOVQPC r64 r64 // Construct and append a CMOVQPC instruction to the active function. func (c *Context) CMOVQPC(mr, r operand.Op) { - if inst, err := x86.CMOVQPC(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVQPC(mr, r)) } // CMOVQPC: Move if not parity (PF == 0). // // Forms: // -// CMOVQPC r64 r64 // CMOVQPC m64 r64 +// CMOVQPC r64 r64 // Construct and append a CMOVQPC instruction to the active function. // Operates on the global context. func CMOVQPC(mr, r operand.Op) { ctx.CMOVQPC(mr, r) } @@ -2844,23 +2425,19 @@ func CMOVQPC(mr, r operand.Op) { ctx.CMOVQPC(mr, r) } // // Forms: // -// CMOVQPL r64 r64 // CMOVQPL m64 r64 +// CMOVQPL r64 r64 // Construct and append a CMOVQPL instruction to the active function. func (c *Context) CMOVQPL(mr, r operand.Op) { - if inst, err := x86.CMOVQPL(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVQPL(mr, r)) } // CMOVQPL: Move if not sign (SF == 0). // // Forms: // -// CMOVQPL r64 r64 // CMOVQPL m64 r64 +// CMOVQPL r64 r64 // Construct and append a CMOVQPL instruction to the active function. // Operates on the global context. func CMOVQPL(mr, r operand.Op) { ctx.CMOVQPL(mr, r) } @@ -2869,23 +2446,19 @@ func CMOVQPL(mr, r operand.Op) { ctx.CMOVQPL(mr, r) } // // Forms: // -// CMOVQPS r64 r64 // CMOVQPS m64 r64 +// CMOVQPS r64 r64 // Construct and append a CMOVQPS instruction to the active function. func (c *Context) CMOVQPS(mr, r operand.Op) { - if inst, err := x86.CMOVQPS(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVQPS(mr, r)) } // CMOVQPS: Move if parity (PF == 1). // // Forms: // -// CMOVQPS r64 r64 // CMOVQPS m64 r64 +// CMOVQPS r64 r64 // Construct and append a CMOVQPS instruction to the active function. // Operates on the global context. func CMOVQPS(mr, r operand.Op) { ctx.CMOVQPS(mr, r) } @@ -2894,23 +2467,19 @@ func CMOVQPS(mr, r operand.Op) { ctx.CMOVQPS(mr, r) } // // Forms: // -// CMOVWCC r16 r16 // CMOVWCC m16 r16 +// CMOVWCC r16 r16 // Construct and append a CMOVWCC instruction to the active function. func (c *Context) CMOVWCC(mr, r operand.Op) { - if inst, err := x86.CMOVWCC(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVWCC(mr, r)) } // CMOVWCC: Move if above or equal (CF == 0). // // Forms: // -// CMOVWCC r16 r16 // CMOVWCC m16 r16 +// CMOVWCC r16 r16 // Construct and append a CMOVWCC instruction to the active function. // Operates on the global context. func CMOVWCC(mr, r operand.Op) { ctx.CMOVWCC(mr, r) } @@ -2919,23 +2488,19 @@ func CMOVWCC(mr, r operand.Op) { ctx.CMOVWCC(mr, r) } // // Forms: // -// CMOVWCS r16 r16 // CMOVWCS m16 r16 +// CMOVWCS r16 r16 // Construct and append a CMOVWCS instruction to the active function. func (c *Context) CMOVWCS(mr, r operand.Op) { - if inst, err := x86.CMOVWCS(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVWCS(mr, r)) } // CMOVWCS: Move if below (CF == 1). // // Forms: // -// CMOVWCS r16 r16 // CMOVWCS m16 r16 +// CMOVWCS r16 r16 // Construct and append a CMOVWCS instruction to the active function. // Operates on the global context. func CMOVWCS(mr, r operand.Op) { ctx.CMOVWCS(mr, r) } @@ -2944,23 +2509,19 @@ func CMOVWCS(mr, r operand.Op) { ctx.CMOVWCS(mr, r) } // // Forms: // -// CMOVWEQ r16 r16 // CMOVWEQ m16 r16 +// CMOVWEQ r16 r16 // Construct and append a CMOVWEQ instruction to the active function. func (c *Context) CMOVWEQ(mr, r operand.Op) { - if inst, err := x86.CMOVWEQ(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVWEQ(mr, r)) } // CMOVWEQ: Move if equal (ZF == 1). // // Forms: // -// CMOVWEQ r16 r16 // CMOVWEQ m16 r16 +// CMOVWEQ r16 r16 // Construct and append a CMOVWEQ instruction to the active function. // Operates on the global context. func CMOVWEQ(mr, r operand.Op) { ctx.CMOVWEQ(mr, r) } @@ -2969,23 +2530,19 @@ func CMOVWEQ(mr, r operand.Op) { ctx.CMOVWEQ(mr, r) } // // Forms: // -// CMOVWGE r16 r16 // CMOVWGE m16 r16 +// CMOVWGE r16 r16 // Construct and append a CMOVWGE instruction to the active function. func (c *Context) CMOVWGE(mr, r operand.Op) { - if inst, err := x86.CMOVWGE(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVWGE(mr, r)) } // CMOVWGE: Move if greater or equal (SF == OF). // // Forms: // -// CMOVWGE r16 r16 // CMOVWGE m16 r16 +// CMOVWGE r16 r16 // Construct and append a CMOVWGE instruction to the active function. // Operates on the global context. func CMOVWGE(mr, r operand.Op) { ctx.CMOVWGE(mr, r) } @@ -2994,23 +2551,19 @@ func CMOVWGE(mr, r operand.Op) { ctx.CMOVWGE(mr, r) } // // Forms: // -// CMOVWGT r16 r16 // CMOVWGT m16 r16 +// CMOVWGT r16 r16 // Construct and append a CMOVWGT instruction to the active function. func (c *Context) CMOVWGT(mr, r operand.Op) { - if inst, err := x86.CMOVWGT(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVWGT(mr, r)) } // CMOVWGT: Move if greater (ZF == 0 and SF == OF). // // Forms: // -// CMOVWGT r16 r16 // CMOVWGT m16 r16 +// CMOVWGT r16 r16 // Construct and append a CMOVWGT instruction to the active function. // Operates on the global context. func CMOVWGT(mr, r operand.Op) { ctx.CMOVWGT(mr, r) } @@ -3019,23 +2572,19 @@ func CMOVWGT(mr, r operand.Op) { ctx.CMOVWGT(mr, r) } // // Forms: // -// CMOVWHI r16 r16 // CMOVWHI m16 r16 +// CMOVWHI r16 r16 // Construct and append a CMOVWHI instruction to the active function. func (c *Context) CMOVWHI(mr, r operand.Op) { - if inst, err := x86.CMOVWHI(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVWHI(mr, r)) } // CMOVWHI: Move if above (CF == 0 and ZF == 0). // // Forms: // -// CMOVWHI r16 r16 // CMOVWHI m16 r16 +// CMOVWHI r16 r16 // Construct and append a CMOVWHI instruction to the active function. // Operates on the global context. func CMOVWHI(mr, r operand.Op) { ctx.CMOVWHI(mr, r) } @@ -3044,23 +2593,19 @@ func CMOVWHI(mr, r operand.Op) { ctx.CMOVWHI(mr, r) } // // Forms: // -// CMOVWLE r16 r16 // CMOVWLE m16 r16 +// CMOVWLE r16 r16 // Construct and append a CMOVWLE instruction to the active function. func (c *Context) CMOVWLE(mr, r operand.Op) { - if inst, err := x86.CMOVWLE(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVWLE(mr, r)) } // CMOVWLE: Move if less or equal (ZF == 1 or SF != OF). // // Forms: // -// CMOVWLE r16 r16 // CMOVWLE m16 r16 +// CMOVWLE r16 r16 // Construct and append a CMOVWLE instruction to the active function. // Operates on the global context. func CMOVWLE(mr, r operand.Op) { ctx.CMOVWLE(mr, r) } @@ -3069,23 +2614,19 @@ func CMOVWLE(mr, r operand.Op) { ctx.CMOVWLE(mr, r) } // // Forms: // -// CMOVWLS r16 r16 // CMOVWLS m16 r16 +// CMOVWLS r16 r16 // Construct and append a CMOVWLS instruction to the active function. func (c *Context) CMOVWLS(mr, r operand.Op) { - if inst, err := x86.CMOVWLS(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVWLS(mr, r)) } // CMOVWLS: Move if below or equal (CF == 1 or ZF == 1). // // Forms: // -// CMOVWLS r16 r16 // CMOVWLS m16 r16 +// CMOVWLS r16 r16 // Construct and append a CMOVWLS instruction to the active function. // Operates on the global context. func CMOVWLS(mr, r operand.Op) { ctx.CMOVWLS(mr, r) } @@ -3094,23 +2635,19 @@ func CMOVWLS(mr, r operand.Op) { ctx.CMOVWLS(mr, r) } // // Forms: // -// CMOVWLT r16 r16 // CMOVWLT m16 r16 +// CMOVWLT r16 r16 // Construct and append a CMOVWLT instruction to the active function. func (c *Context) CMOVWLT(mr, r operand.Op) { - if inst, err := x86.CMOVWLT(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVWLT(mr, r)) } // CMOVWLT: Move if less (SF != OF). // // Forms: // -// CMOVWLT r16 r16 // CMOVWLT m16 r16 +// CMOVWLT r16 r16 // Construct and append a CMOVWLT instruction to the active function. // Operates on the global context. func CMOVWLT(mr, r operand.Op) { ctx.CMOVWLT(mr, r) } @@ -3119,23 +2656,19 @@ func CMOVWLT(mr, r operand.Op) { ctx.CMOVWLT(mr, r) } // // Forms: // -// CMOVWMI r16 r16 // CMOVWMI m16 r16 +// CMOVWMI r16 r16 // Construct and append a CMOVWMI instruction to the active function. func (c *Context) CMOVWMI(mr, r operand.Op) { - if inst, err := x86.CMOVWMI(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVWMI(mr, r)) } // CMOVWMI: Move if sign (SF == 1). // // Forms: // -// CMOVWMI r16 r16 // CMOVWMI m16 r16 +// CMOVWMI r16 r16 // Construct and append a CMOVWMI instruction to the active function. // Operates on the global context. func CMOVWMI(mr, r operand.Op) { ctx.CMOVWMI(mr, r) } @@ -3144,23 +2677,19 @@ func CMOVWMI(mr, r operand.Op) { ctx.CMOVWMI(mr, r) } // // Forms: // -// CMOVWNE r16 r16 // CMOVWNE m16 r16 +// CMOVWNE r16 r16 // Construct and append a CMOVWNE instruction to the active function. func (c *Context) CMOVWNE(mr, r operand.Op) { - if inst, err := x86.CMOVWNE(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVWNE(mr, r)) } // CMOVWNE: Move if not equal (ZF == 0). // // Forms: // -// CMOVWNE r16 r16 // CMOVWNE m16 r16 +// CMOVWNE r16 r16 // Construct and append a CMOVWNE instruction to the active function. // Operates on the global context. func CMOVWNE(mr, r operand.Op) { ctx.CMOVWNE(mr, r) } @@ -3169,23 +2698,19 @@ func CMOVWNE(mr, r operand.Op) { ctx.CMOVWNE(mr, r) } // // Forms: // -// CMOVWOC r16 r16 // CMOVWOC m16 r16 +// CMOVWOC r16 r16 // Construct and append a CMOVWOC instruction to the active function. func (c *Context) CMOVWOC(mr, r operand.Op) { - if inst, err := x86.CMOVWOC(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVWOC(mr, r)) } // CMOVWOC: Move if not overflow (OF == 0). // // Forms: // -// CMOVWOC r16 r16 // CMOVWOC m16 r16 +// CMOVWOC r16 r16 // Construct and append a CMOVWOC instruction to the active function. // Operates on the global context. func CMOVWOC(mr, r operand.Op) { ctx.CMOVWOC(mr, r) } @@ -3194,23 +2719,19 @@ func CMOVWOC(mr, r operand.Op) { ctx.CMOVWOC(mr, r) } // // Forms: // -// CMOVWOS r16 r16 // CMOVWOS m16 r16 +// CMOVWOS r16 r16 // Construct and append a CMOVWOS instruction to the active function. func (c *Context) CMOVWOS(mr, r operand.Op) { - if inst, err := x86.CMOVWOS(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVWOS(mr, r)) } // CMOVWOS: Move if overflow (OF == 1). // // Forms: // -// CMOVWOS r16 r16 // CMOVWOS m16 r16 +// CMOVWOS r16 r16 // Construct and append a CMOVWOS instruction to the active function. // Operates on the global context. func CMOVWOS(mr, r operand.Op) { ctx.CMOVWOS(mr, r) } @@ -3219,23 +2740,19 @@ func CMOVWOS(mr, r operand.Op) { ctx.CMOVWOS(mr, r) } // // Forms: // -// CMOVWPC r16 r16 // CMOVWPC m16 r16 +// CMOVWPC r16 r16 // Construct and append a CMOVWPC instruction to the active function. func (c *Context) CMOVWPC(mr, r operand.Op) { - if inst, err := x86.CMOVWPC(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVWPC(mr, r)) } // CMOVWPC: Move if not parity (PF == 0). // // Forms: // -// CMOVWPC r16 r16 // CMOVWPC m16 r16 +// CMOVWPC r16 r16 // Construct and append a CMOVWPC instruction to the active function. // Operates on the global context. func CMOVWPC(mr, r operand.Op) { ctx.CMOVWPC(mr, r) } @@ -3244,23 +2761,19 @@ func CMOVWPC(mr, r operand.Op) { ctx.CMOVWPC(mr, r) } // // Forms: // -// CMOVWPL r16 r16 // CMOVWPL m16 r16 +// CMOVWPL r16 r16 // Construct and append a CMOVWPL instruction to the active function. func (c *Context) CMOVWPL(mr, r operand.Op) { - if inst, err := x86.CMOVWPL(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVWPL(mr, r)) } // CMOVWPL: Move if not sign (SF == 0). // // Forms: // -// CMOVWPL r16 r16 // CMOVWPL m16 r16 +// CMOVWPL r16 r16 // Construct and append a CMOVWPL instruction to the active function. // Operates on the global context. func CMOVWPL(mr, r operand.Op) { ctx.CMOVWPL(mr, r) } @@ -3269,23 +2782,19 @@ func CMOVWPL(mr, r operand.Op) { ctx.CMOVWPL(mr, r) } // // Forms: // -// CMOVWPS r16 r16 // CMOVWPS m16 r16 +// CMOVWPS r16 r16 // Construct and append a CMOVWPS instruction to the active function. func (c *Context) CMOVWPS(mr, r operand.Op) { - if inst, err := x86.CMOVWPS(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMOVWPS(mr, r)) } // CMOVWPS: Move if parity (PF == 1). // // Forms: // -// CMOVWPS r16 r16 // CMOVWPS m16 r16 +// CMOVWPS r16 r16 // Construct and append a CMOVWPS instruction to the active function. // Operates on the global context. func CMOVWPS(mr, r operand.Op) { ctx.CMOVWPS(mr, r) } @@ -3295,18 +2804,14 @@ func CMOVWPS(mr, r operand.Op) { ctx.CMOVWPS(mr, r) } // Forms: // // CMPB al imm8 -// CMPB r8 imm8 -// CMPB r8 r8 -// CMPB r8 m8 // CMPB m8 imm8 // CMPB m8 r8 +// CMPB r8 imm8 +// CMPB r8 m8 +// CMPB r8 r8 // Construct and append a CMPB instruction to the active function. func (c *Context) CMPB(amr, imr operand.Op) { - if inst, err := x86.CMPB(amr, imr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMPB(amr, imr)) } // CMPB: Compare Two Operands. @@ -3314,11 +2819,11 @@ func (c *Context) CMPB(amr, imr operand.Op) { // Forms: // // CMPB al imm8 -// CMPB r8 imm8 -// CMPB r8 r8 -// CMPB r8 m8 // CMPB m8 imm8 // CMPB m8 r8 +// CMPB r8 imm8 +// CMPB r8 m8 +// CMPB r8 r8 // Construct and append a CMPB instruction to the active function. // Operates on the global context. func CMPB(amr, imr operand.Op) { ctx.CMPB(amr, imr) } @@ -3328,20 +2833,16 @@ func CMPB(amr, imr operand.Op) { ctx.CMPB(amr, imr) } // Forms: // // CMPL eax imm32 -// CMPL r32 imm8 -// CMPL r32 imm32 -// CMPL r32 r32 -// CMPL r32 m32 -// CMPL m32 imm8 // CMPL m32 imm32 +// CMPL m32 imm8 // CMPL m32 r32 +// CMPL r32 imm32 +// CMPL r32 imm8 +// CMPL r32 m32 +// CMPL r32 r32 // Construct and append a CMPL instruction to the active function. func (c *Context) CMPL(emr, imr operand.Op) { - if inst, err := x86.CMPL(emr, imr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMPL(emr, imr)) } // CMPL: Compare Two Operands. @@ -3349,13 +2850,13 @@ func (c *Context) CMPL(emr, imr operand.Op) { // Forms: // // CMPL eax imm32 -// CMPL r32 imm8 -// CMPL r32 imm32 -// CMPL r32 r32 -// CMPL r32 m32 -// CMPL m32 imm8 // CMPL m32 imm32 +// CMPL m32 imm8 // CMPL m32 r32 +// CMPL r32 imm32 +// CMPL r32 imm8 +// CMPL r32 m32 +// CMPL r32 r32 // Construct and append a CMPL instruction to the active function. // Operates on the global context. func CMPL(emr, imr operand.Op) { ctx.CMPL(emr, imr) } @@ -3364,23 +2865,19 @@ func CMPL(emr, imr operand.Op) { ctx.CMPL(emr, imr) } // // Forms: // -// CMPPD xmm xmm imm8 // CMPPD m128 xmm imm8 +// CMPPD xmm xmm imm8 // Construct and append a CMPPD instruction to the active function. func (c *Context) CMPPD(mx, x, i operand.Op) { - if inst, err := x86.CMPPD(mx, x, i); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMPPD(mx, x, i)) } // CMPPD: Compare Packed Double-Precision Floating-Point Values. // // Forms: // -// CMPPD xmm xmm imm8 // CMPPD m128 xmm imm8 +// CMPPD xmm xmm imm8 // Construct and append a CMPPD instruction to the active function. // Operates on the global context. func CMPPD(mx, x, i operand.Op) { ctx.CMPPD(mx, x, i) } @@ -3389,23 +2886,19 @@ func CMPPD(mx, x, i operand.Op) { ctx.CMPPD(mx, x, i) } // // Forms: // -// CMPPS xmm xmm imm8 // CMPPS m128 xmm imm8 +// CMPPS xmm xmm imm8 // Construct and append a CMPPS instruction to the active function. func (c *Context) CMPPS(mx, x, i operand.Op) { - if inst, err := x86.CMPPS(mx, x, i); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMPPS(mx, x, i)) } // CMPPS: Compare Packed Single-Precision Floating-Point Values. // // Forms: // -// CMPPS xmm xmm imm8 // CMPPS m128 xmm imm8 +// CMPPS xmm xmm imm8 // Construct and append a CMPPS instruction to the active function. // Operates on the global context. func CMPPS(mx, x, i operand.Op) { ctx.CMPPS(mx, x, i) } @@ -3414,35 +2907,31 @@ func CMPPS(mx, x, i operand.Op) { ctx.CMPPS(mx, x, i) } // // Forms: // -// CMPQ rax imm32 -// CMPQ r64 imm8 -// CMPQ r64 imm32 -// CMPQ r64 r64 -// CMPQ r64 m64 -// CMPQ m64 imm8 // CMPQ m64 imm32 +// CMPQ m64 imm8 // CMPQ m64 r64 +// CMPQ r64 imm32 +// CMPQ r64 imm8 +// CMPQ r64 m64 +// CMPQ r64 r64 +// CMPQ rax imm32 // Construct and append a CMPQ instruction to the active function. func (c *Context) CMPQ(mr, imr operand.Op) { - if inst, err := x86.CMPQ(mr, imr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMPQ(mr, imr)) } // CMPQ: Compare Two Operands. // // Forms: // -// CMPQ rax imm32 -// CMPQ r64 imm8 -// CMPQ r64 imm32 -// CMPQ r64 r64 -// CMPQ r64 m64 -// CMPQ m64 imm8 // CMPQ m64 imm32 +// CMPQ m64 imm8 // CMPQ m64 r64 +// CMPQ r64 imm32 +// CMPQ r64 imm8 +// CMPQ r64 m64 +// CMPQ r64 r64 +// CMPQ rax imm32 // Construct and append a CMPQ instruction to the active function. // Operates on the global context. func CMPQ(mr, imr operand.Op) { ctx.CMPQ(mr, imr) } @@ -3451,23 +2940,19 @@ func CMPQ(mr, imr operand.Op) { ctx.CMPQ(mr, imr) } // // Forms: // -// CMPSD xmm xmm imm8 // CMPSD m64 xmm imm8 +// CMPSD xmm xmm imm8 // Construct and append a CMPSD instruction to the active function. func (c *Context) CMPSD(mx, x, i operand.Op) { - if inst, err := x86.CMPSD(mx, x, i); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMPSD(mx, x, i)) } // CMPSD: Compare Scalar Double-Precision Floating-Point Values. // // Forms: // -// CMPSD xmm xmm imm8 // CMPSD m64 xmm imm8 +// CMPSD xmm xmm imm8 // Construct and append a CMPSD instruction to the active function. // Operates on the global context. func CMPSD(mx, x, i operand.Op) { ctx.CMPSD(mx, x, i) } @@ -3476,23 +2961,19 @@ func CMPSD(mx, x, i operand.Op) { ctx.CMPSD(mx, x, i) } // // Forms: // -// CMPSS xmm xmm imm8 // CMPSS m32 xmm imm8 +// CMPSS xmm xmm imm8 // Construct and append a CMPSS instruction to the active function. func (c *Context) CMPSS(mx, x, i operand.Op) { - if inst, err := x86.CMPSS(mx, x, i); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMPSS(mx, x, i)) } // CMPSS: Compare Scalar Single-Precision Floating-Point Values. // // Forms: // -// CMPSS xmm xmm imm8 // CMPSS m32 xmm imm8 +// CMPSS xmm xmm imm8 // Construct and append a CMPSS instruction to the active function. // Operates on the global context. func CMPSS(mx, x, i operand.Op) { ctx.CMPSS(mx, x, i) } @@ -3502,20 +2983,16 @@ func CMPSS(mx, x, i operand.Op) { ctx.CMPSS(mx, x, i) } // Forms: // // CMPW ax imm16 -// CMPW r16 imm8 -// CMPW r16 imm16 -// CMPW r16 r16 -// CMPW r16 m16 -// CMPW m16 imm8 // CMPW m16 imm16 +// CMPW m16 imm8 // CMPW m16 r16 +// CMPW r16 imm16 +// CMPW r16 imm8 +// CMPW r16 m16 +// CMPW r16 r16 // Construct and append a CMPW instruction to the active function. func (c *Context) CMPW(amr, imr operand.Op) { - if inst, err := x86.CMPW(amr, imr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMPW(amr, imr)) } // CMPW: Compare Two Operands. @@ -3523,13 +3000,13 @@ func (c *Context) CMPW(amr, imr operand.Op) { // Forms: // // CMPW ax imm16 -// CMPW r16 imm8 -// CMPW r16 imm16 -// CMPW r16 r16 -// CMPW r16 m16 -// CMPW m16 imm8 // CMPW m16 imm16 +// CMPW m16 imm8 // CMPW m16 r16 +// CMPW r16 imm16 +// CMPW r16 imm8 +// CMPW r16 m16 +// CMPW r16 r16 // Construct and append a CMPW instruction to the active function. // Operates on the global context. func CMPW(amr, imr operand.Op) { ctx.CMPW(amr, imr) } @@ -3541,11 +3018,7 @@ func CMPW(amr, imr operand.Op) { ctx.CMPW(amr, imr) } // CMPXCHG16B m128 // Construct and append a CMPXCHG16B instruction to the active function. func (c *Context) CMPXCHG16B(m operand.Op) { - if inst, err := x86.CMPXCHG16B(m); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMPXCHG16B(m)) } // CMPXCHG16B: Compare and Exchange 16 Bytes. @@ -3564,11 +3037,7 @@ func CMPXCHG16B(m operand.Op) { ctx.CMPXCHG16B(m) } // CMPXCHG8B m64 // Construct and append a CMPXCHG8B instruction to the active function. func (c *Context) CMPXCHG8B(m operand.Op) { - if inst, err := x86.CMPXCHG8B(m); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMPXCHG8B(m)) } // CMPXCHG8B: Compare and Exchange 8 Bytes. @@ -3584,23 +3053,19 @@ func CMPXCHG8B(m operand.Op) { ctx.CMPXCHG8B(m) } // // Forms: // -// CMPXCHGB r8 r8 // CMPXCHGB r8 m8 +// CMPXCHGB r8 r8 // Construct and append a CMPXCHGB instruction to the active function. func (c *Context) CMPXCHGB(r, mr operand.Op) { - if inst, err := x86.CMPXCHGB(r, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMPXCHGB(r, mr)) } // CMPXCHGB: Compare and Exchange. // // Forms: // -// CMPXCHGB r8 r8 // CMPXCHGB r8 m8 +// CMPXCHGB r8 r8 // Construct and append a CMPXCHGB instruction to the active function. // Operates on the global context. func CMPXCHGB(r, mr operand.Op) { ctx.CMPXCHGB(r, mr) } @@ -3609,23 +3074,19 @@ func CMPXCHGB(r, mr operand.Op) { ctx.CMPXCHGB(r, mr) } // // Forms: // -// CMPXCHGL r32 r32 // CMPXCHGL r32 m32 +// CMPXCHGL r32 r32 // Construct and append a CMPXCHGL instruction to the active function. func (c *Context) CMPXCHGL(r, mr operand.Op) { - if inst, err := x86.CMPXCHGL(r, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMPXCHGL(r, mr)) } // CMPXCHGL: Compare and Exchange. // // Forms: // -// CMPXCHGL r32 r32 // CMPXCHGL r32 m32 +// CMPXCHGL r32 r32 // Construct and append a CMPXCHGL instruction to the active function. // Operates on the global context. func CMPXCHGL(r, mr operand.Op) { ctx.CMPXCHGL(r, mr) } @@ -3634,23 +3095,19 @@ func CMPXCHGL(r, mr operand.Op) { ctx.CMPXCHGL(r, mr) } // // Forms: // -// CMPXCHGQ r64 r64 // CMPXCHGQ r64 m64 +// CMPXCHGQ r64 r64 // Construct and append a CMPXCHGQ instruction to the active function. func (c *Context) CMPXCHGQ(r, mr operand.Op) { - if inst, err := x86.CMPXCHGQ(r, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMPXCHGQ(r, mr)) } // CMPXCHGQ: Compare and Exchange. // // Forms: // -// CMPXCHGQ r64 r64 // CMPXCHGQ r64 m64 +// CMPXCHGQ r64 r64 // Construct and append a CMPXCHGQ instruction to the active function. // Operates on the global context. func CMPXCHGQ(r, mr operand.Op) { ctx.CMPXCHGQ(r, mr) } @@ -3659,23 +3116,19 @@ func CMPXCHGQ(r, mr operand.Op) { ctx.CMPXCHGQ(r, mr) } // // Forms: // -// CMPXCHGW r16 r16 // CMPXCHGW r16 m16 +// CMPXCHGW r16 r16 // Construct and append a CMPXCHGW instruction to the active function. func (c *Context) CMPXCHGW(r, mr operand.Op) { - if inst, err := x86.CMPXCHGW(r, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CMPXCHGW(r, mr)) } // CMPXCHGW: Compare and Exchange. // // Forms: // -// CMPXCHGW r16 r16 // CMPXCHGW r16 m16 +// CMPXCHGW r16 r16 // Construct and append a CMPXCHGW instruction to the active function. // Operates on the global context. func CMPXCHGW(r, mr operand.Op) { ctx.CMPXCHGW(r, mr) } @@ -3684,23 +3137,19 @@ func CMPXCHGW(r, mr operand.Op) { ctx.CMPXCHGW(r, mr) } // // Forms: // -// COMISD xmm xmm // COMISD m64 xmm +// COMISD xmm xmm // Construct and append a COMISD instruction to the active function. func (c *Context) COMISD(mx, x operand.Op) { - if inst, err := x86.COMISD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.COMISD(mx, x)) } // COMISD: Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS. // // Forms: // -// COMISD xmm xmm // COMISD m64 xmm +// COMISD xmm xmm // Construct and append a COMISD instruction to the active function. // Operates on the global context. func COMISD(mx, x operand.Op) { ctx.COMISD(mx, x) } @@ -3709,23 +3158,19 @@ func COMISD(mx, x operand.Op) { ctx.COMISD(mx, x) } // // Forms: // -// COMISS xmm xmm // COMISS m32 xmm +// COMISS xmm xmm // Construct and append a COMISS instruction to the active function. func (c *Context) COMISS(mx, x operand.Op) { - if inst, err := x86.COMISS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.COMISS(mx, x)) } // COMISS: Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS. // // Forms: // -// COMISS xmm xmm // COMISS m32 xmm +// COMISS xmm xmm // Construct and append a COMISS instruction to the active function. // Operates on the global context. func COMISS(mx, x operand.Op) { ctx.COMISS(mx, x) } @@ -3737,11 +3182,7 @@ func COMISS(mx, x operand.Op) { ctx.COMISS(mx, x) } // CPUID // Construct and append a CPUID instruction to the active function. func (c *Context) CPUID() { - if inst, err := x86.CPUID(); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CPUID()) } // CPUID: CPU Identification. @@ -3760,11 +3201,7 @@ func CPUID() { ctx.CPUID() } // CQO // Construct and append a CQO instruction to the active function. func (c *Context) CQO() { - if inst, err := x86.CQO(); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CQO()) } // CQO: Convert Quadword to Octaword. @@ -3780,27 +3217,23 @@ func CQO() { ctx.CQO() } // // Forms: // -// CRC32B r8 r32 // CRC32B m8 r32 -// CRC32B r8 r64 // CRC32B m8 r64 +// CRC32B r8 r32 +// CRC32B r8 r64 // Construct and append a CRC32B instruction to the active function. func (c *Context) CRC32B(mr, r operand.Op) { - if inst, err := x86.CRC32B(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CRC32B(mr, r)) } // CRC32B: Accumulate CRC32 Value. // // Forms: // -// CRC32B r8 r32 // CRC32B m8 r32 -// CRC32B r8 r64 // CRC32B m8 r64 +// CRC32B r8 r32 +// CRC32B r8 r64 // Construct and append a CRC32B instruction to the active function. // Operates on the global context. func CRC32B(mr, r operand.Op) { ctx.CRC32B(mr, r) } @@ -3809,23 +3242,19 @@ func CRC32B(mr, r operand.Op) { ctx.CRC32B(mr, r) } // // Forms: // -// CRC32L r32 r32 // CRC32L m32 r32 +// CRC32L r32 r32 // Construct and append a CRC32L instruction to the active function. func (c *Context) CRC32L(mr, r operand.Op) { - if inst, err := x86.CRC32L(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CRC32L(mr, r)) } // CRC32L: Accumulate CRC32 Value. // // Forms: // -// CRC32L r32 r32 // CRC32L m32 r32 +// CRC32L r32 r32 // Construct and append a CRC32L instruction to the active function. // Operates on the global context. func CRC32L(mr, r operand.Op) { ctx.CRC32L(mr, r) } @@ -3834,23 +3263,19 @@ func CRC32L(mr, r operand.Op) { ctx.CRC32L(mr, r) } // // Forms: // -// CRC32Q r64 r64 // CRC32Q m64 r64 +// CRC32Q r64 r64 // Construct and append a CRC32Q instruction to the active function. func (c *Context) CRC32Q(mr, r operand.Op) { - if inst, err := x86.CRC32Q(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CRC32Q(mr, r)) } // CRC32Q: Accumulate CRC32 Value. // // Forms: // -// CRC32Q r64 r64 // CRC32Q m64 r64 +// CRC32Q r64 r64 // Construct and append a CRC32Q instruction to the active function. // Operates on the global context. func CRC32Q(mr, r operand.Op) { ctx.CRC32Q(mr, r) } @@ -3859,23 +3284,19 @@ func CRC32Q(mr, r operand.Op) { ctx.CRC32Q(mr, r) } // // Forms: // -// CRC32W r16 r32 // CRC32W m16 r32 +// CRC32W r16 r32 // Construct and append a CRC32W instruction to the active function. func (c *Context) CRC32W(mr, r operand.Op) { - if inst, err := x86.CRC32W(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CRC32W(mr, r)) } // CRC32W: Accumulate CRC32 Value. // // Forms: // -// CRC32W r16 r32 // CRC32W m16 r32 +// CRC32W r16 r32 // Construct and append a CRC32W instruction to the active function. // Operates on the global context. func CRC32W(mr, r operand.Op) { ctx.CRC32W(mr, r) } @@ -3884,23 +3305,19 @@ func CRC32W(mr, r operand.Op) { ctx.CRC32W(mr, r) } // // Forms: // -// CVTPD2PL xmm xmm // CVTPD2PL m128 xmm +// CVTPD2PL xmm xmm // Construct and append a CVTPD2PL instruction to the active function. func (c *Context) CVTPD2PL(mx, x operand.Op) { - if inst, err := x86.CVTPD2PL(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CVTPD2PL(mx, x)) } // CVTPD2PL: Convert Packed Double-Precision FP Values to Packed Dword Integers. // // Forms: // -// CVTPD2PL xmm xmm // CVTPD2PL m128 xmm +// CVTPD2PL xmm xmm // Construct and append a CVTPD2PL instruction to the active function. // Operates on the global context. func CVTPD2PL(mx, x operand.Op) { ctx.CVTPD2PL(mx, x) } @@ -3909,23 +3326,19 @@ func CVTPD2PL(mx, x operand.Op) { ctx.CVTPD2PL(mx, x) } // // Forms: // -// CVTPD2PS xmm xmm // CVTPD2PS m128 xmm +// CVTPD2PS xmm xmm // Construct and append a CVTPD2PS instruction to the active function. func (c *Context) CVTPD2PS(mx, x operand.Op) { - if inst, err := x86.CVTPD2PS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CVTPD2PS(mx, x)) } // CVTPD2PS: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values. // // Forms: // -// CVTPD2PS xmm xmm // CVTPD2PS m128 xmm +// CVTPD2PS xmm xmm // Construct and append a CVTPD2PS instruction to the active function. // Operates on the global context. func CVTPD2PS(mx, x operand.Op) { ctx.CVTPD2PS(mx, x) } @@ -3934,23 +3347,19 @@ func CVTPD2PS(mx, x operand.Op) { ctx.CVTPD2PS(mx, x) } // // Forms: // -// CVTPL2PD xmm xmm // CVTPL2PD m64 xmm +// CVTPL2PD xmm xmm // Construct and append a CVTPL2PD instruction to the active function. func (c *Context) CVTPL2PD(mx, x operand.Op) { - if inst, err := x86.CVTPL2PD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CVTPL2PD(mx, x)) } // CVTPL2PD: Convert Packed Dword Integers to Packed Double-Precision FP Values. // // Forms: // -// CVTPL2PD xmm xmm // CVTPL2PD m64 xmm +// CVTPL2PD xmm xmm // Construct and append a CVTPL2PD instruction to the active function. // Operates on the global context. func CVTPL2PD(mx, x operand.Op) { ctx.CVTPL2PD(mx, x) } @@ -3959,23 +3368,19 @@ func CVTPL2PD(mx, x operand.Op) { ctx.CVTPL2PD(mx, x) } // // Forms: // -// CVTPL2PS xmm xmm // CVTPL2PS m128 xmm +// CVTPL2PS xmm xmm // Construct and append a CVTPL2PS instruction to the active function. func (c *Context) CVTPL2PS(mx, x operand.Op) { - if inst, err := x86.CVTPL2PS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CVTPL2PS(mx, x)) } // CVTPL2PS: Convert Packed Dword Integers to Packed Single-Precision FP Values. // // Forms: // -// CVTPL2PS xmm xmm // CVTPL2PS m128 xmm +// CVTPL2PS xmm xmm // Construct and append a CVTPL2PS instruction to the active function. // Operates on the global context. func CVTPL2PS(mx, x operand.Op) { ctx.CVTPL2PS(mx, x) } @@ -3984,23 +3389,19 @@ func CVTPL2PS(mx, x operand.Op) { ctx.CVTPL2PS(mx, x) } // // Forms: // -// CVTPS2PD xmm xmm // CVTPS2PD m64 xmm +// CVTPS2PD xmm xmm // Construct and append a CVTPS2PD instruction to the active function. func (c *Context) CVTPS2PD(mx, x operand.Op) { - if inst, err := x86.CVTPS2PD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CVTPS2PD(mx, x)) } // CVTPS2PD: Convert Packed Single-Precision FP Values to Packed Double-Precision FP Values. // // Forms: // -// CVTPS2PD xmm xmm // CVTPS2PD m64 xmm +// CVTPS2PD xmm xmm // Construct and append a CVTPS2PD instruction to the active function. // Operates on the global context. func CVTPS2PD(mx, x operand.Op) { ctx.CVTPS2PD(mx, x) } @@ -4009,23 +3410,19 @@ func CVTPS2PD(mx, x operand.Op) { ctx.CVTPS2PD(mx, x) } // // Forms: // -// CVTPS2PL xmm xmm // CVTPS2PL m128 xmm +// CVTPS2PL xmm xmm // Construct and append a CVTPS2PL instruction to the active function. func (c *Context) CVTPS2PL(mx, x operand.Op) { - if inst, err := x86.CVTPS2PL(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CVTPS2PL(mx, x)) } // CVTPS2PL: Convert Packed Single-Precision FP Values to Packed Dword Integers. // // Forms: // -// CVTPS2PL xmm xmm // CVTPS2PL m128 xmm +// CVTPS2PL xmm xmm // Construct and append a CVTPS2PL instruction to the active function. // Operates on the global context. func CVTPS2PL(mx, x operand.Op) { ctx.CVTPS2PL(mx, x) } @@ -4034,27 +3431,23 @@ func CVTPS2PL(mx, x operand.Op) { ctx.CVTPS2PL(mx, x) } // // Forms: // -// CVTSD2SL xmm r32 // CVTSD2SL m64 r32 -// CVTSD2SL xmm r64 // CVTSD2SL m64 r64 +// CVTSD2SL xmm r32 +// CVTSD2SL xmm r64 // Construct and append a CVTSD2SL instruction to the active function. func (c *Context) CVTSD2SL(mx, r operand.Op) { - if inst, err := x86.CVTSD2SL(mx, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CVTSD2SL(mx, r)) } // CVTSD2SL: Convert Scalar Double-Precision FP Value to Integer. // // Forms: // -// CVTSD2SL xmm r32 // CVTSD2SL m64 r32 -// CVTSD2SL xmm r64 // CVTSD2SL m64 r64 +// CVTSD2SL xmm r32 +// CVTSD2SL xmm r64 // Construct and append a CVTSD2SL instruction to the active function. // Operates on the global context. func CVTSD2SL(mx, r operand.Op) { ctx.CVTSD2SL(mx, r) } @@ -4063,23 +3456,19 @@ func CVTSD2SL(mx, r operand.Op) { ctx.CVTSD2SL(mx, r) } // // Forms: // -// CVTSD2SS xmm xmm // CVTSD2SS m64 xmm +// CVTSD2SS xmm xmm // Construct and append a CVTSD2SS instruction to the active function. func (c *Context) CVTSD2SS(mx, x operand.Op) { - if inst, err := x86.CVTSD2SS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CVTSD2SS(mx, x)) } // CVTSD2SS: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value. // // Forms: // -// CVTSD2SS xmm xmm // CVTSD2SS m64 xmm +// CVTSD2SS xmm xmm // Construct and append a CVTSD2SS instruction to the active function. // Operates on the global context. func CVTSD2SS(mx, x operand.Op) { ctx.CVTSD2SS(mx, x) } @@ -4088,23 +3477,19 @@ func CVTSD2SS(mx, x operand.Op) { ctx.CVTSD2SS(mx, x) } // // Forms: // -// CVTSL2SD r32 xmm // CVTSL2SD m32 xmm +// CVTSL2SD r32 xmm // Construct and append a CVTSL2SD instruction to the active function. func (c *Context) CVTSL2SD(mr, x operand.Op) { - if inst, err := x86.CVTSL2SD(mr, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CVTSL2SD(mr, x)) } // CVTSL2SD: Convert Dword Integer to Scalar Double-Precision FP Value. // // Forms: // -// CVTSL2SD r32 xmm // CVTSL2SD m32 xmm +// CVTSL2SD r32 xmm // Construct and append a CVTSL2SD instruction to the active function. // Operates on the global context. func CVTSL2SD(mr, x operand.Op) { ctx.CVTSL2SD(mr, x) } @@ -4113,23 +3498,19 @@ func CVTSL2SD(mr, x operand.Op) { ctx.CVTSL2SD(mr, x) } // // Forms: // -// CVTSL2SS r32 xmm // CVTSL2SS m32 xmm +// CVTSL2SS r32 xmm // Construct and append a CVTSL2SS instruction to the active function. func (c *Context) CVTSL2SS(mr, x operand.Op) { - if inst, err := x86.CVTSL2SS(mr, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CVTSL2SS(mr, x)) } // CVTSL2SS: Convert Dword Integer to Scalar Single-Precision FP Value. // // Forms: // -// CVTSL2SS r32 xmm // CVTSL2SS m32 xmm +// CVTSL2SS r32 xmm // Construct and append a CVTSL2SS instruction to the active function. // Operates on the global context. func CVTSL2SS(mr, x operand.Op) { ctx.CVTSL2SS(mr, x) } @@ -4138,23 +3519,19 @@ func CVTSL2SS(mr, x operand.Op) { ctx.CVTSL2SS(mr, x) } // // Forms: // -// CVTSQ2SD r64 xmm // CVTSQ2SD m64 xmm +// CVTSQ2SD r64 xmm // Construct and append a CVTSQ2SD instruction to the active function. func (c *Context) CVTSQ2SD(mr, x operand.Op) { - if inst, err := x86.CVTSQ2SD(mr, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CVTSQ2SD(mr, x)) } // CVTSQ2SD: Convert Dword Integer to Scalar Double-Precision FP Value. // // Forms: // -// CVTSQ2SD r64 xmm // CVTSQ2SD m64 xmm +// CVTSQ2SD r64 xmm // Construct and append a CVTSQ2SD instruction to the active function. // Operates on the global context. func CVTSQ2SD(mr, x operand.Op) { ctx.CVTSQ2SD(mr, x) } @@ -4163,23 +3540,19 @@ func CVTSQ2SD(mr, x operand.Op) { ctx.CVTSQ2SD(mr, x) } // // Forms: // -// CVTSQ2SS r64 xmm // CVTSQ2SS m64 xmm +// CVTSQ2SS r64 xmm // Construct and append a CVTSQ2SS instruction to the active function. func (c *Context) CVTSQ2SS(mr, x operand.Op) { - if inst, err := x86.CVTSQ2SS(mr, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CVTSQ2SS(mr, x)) } // CVTSQ2SS: Convert Dword Integer to Scalar Single-Precision FP Value. // // Forms: // -// CVTSQ2SS r64 xmm // CVTSQ2SS m64 xmm +// CVTSQ2SS r64 xmm // Construct and append a CVTSQ2SS instruction to the active function. // Operates on the global context. func CVTSQ2SS(mr, x operand.Op) { ctx.CVTSQ2SS(mr, x) } @@ -4188,23 +3561,19 @@ func CVTSQ2SS(mr, x operand.Op) { ctx.CVTSQ2SS(mr, x) } // // Forms: // -// CVTSS2SD xmm xmm // CVTSS2SD m32 xmm +// CVTSS2SD xmm xmm // Construct and append a CVTSS2SD instruction to the active function. func (c *Context) CVTSS2SD(mx, x operand.Op) { - if inst, err := x86.CVTSS2SD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CVTSS2SD(mx, x)) } // CVTSS2SD: Convert Scalar Single-Precision FP Value to Scalar Double-Precision FP Value. // // Forms: // -// CVTSS2SD xmm xmm // CVTSS2SD m32 xmm +// CVTSS2SD xmm xmm // Construct and append a CVTSS2SD instruction to the active function. // Operates on the global context. func CVTSS2SD(mx, x operand.Op) { ctx.CVTSS2SD(mx, x) } @@ -4213,27 +3582,23 @@ func CVTSS2SD(mx, x operand.Op) { ctx.CVTSS2SD(mx, x) } // // Forms: // -// CVTSS2SL xmm r32 // CVTSS2SL m32 r32 -// CVTSS2SL xmm r64 // CVTSS2SL m32 r64 +// CVTSS2SL xmm r32 +// CVTSS2SL xmm r64 // Construct and append a CVTSS2SL instruction to the active function. func (c *Context) CVTSS2SL(mx, r operand.Op) { - if inst, err := x86.CVTSS2SL(mx, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CVTSS2SL(mx, r)) } // CVTSS2SL: Convert Scalar Single-Precision FP Value to Dword Integer. // // Forms: // -// CVTSS2SL xmm r32 // CVTSS2SL m32 r32 -// CVTSS2SL xmm r64 // CVTSS2SL m32 r64 +// CVTSS2SL xmm r32 +// CVTSS2SL xmm r64 // Construct and append a CVTSS2SL instruction to the active function. // Operates on the global context. func CVTSS2SL(mx, r operand.Op) { ctx.CVTSS2SL(mx, r) } @@ -4242,23 +3607,19 @@ func CVTSS2SL(mx, r operand.Op) { ctx.CVTSS2SL(mx, r) } // // Forms: // -// CVTTPD2PL xmm xmm // CVTTPD2PL m128 xmm +// CVTTPD2PL xmm xmm // Construct and append a CVTTPD2PL instruction to the active function. func (c *Context) CVTTPD2PL(mx, x operand.Op) { - if inst, err := x86.CVTTPD2PL(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CVTTPD2PL(mx, x)) } // CVTTPD2PL: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers. // // Forms: // -// CVTTPD2PL xmm xmm // CVTTPD2PL m128 xmm +// CVTTPD2PL xmm xmm // Construct and append a CVTTPD2PL instruction to the active function. // Operates on the global context. func CVTTPD2PL(mx, x operand.Op) { ctx.CVTTPD2PL(mx, x) } @@ -4267,23 +3628,19 @@ func CVTTPD2PL(mx, x operand.Op) { ctx.CVTTPD2PL(mx, x) } // // Forms: // -// CVTTPS2PL xmm xmm // CVTTPS2PL m128 xmm +// CVTTPS2PL xmm xmm // Construct and append a CVTTPS2PL instruction to the active function. func (c *Context) CVTTPS2PL(mx, x operand.Op) { - if inst, err := x86.CVTTPS2PL(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CVTTPS2PL(mx, x)) } // CVTTPS2PL: Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers. // // Forms: // -// CVTTPS2PL xmm xmm // CVTTPS2PL m128 xmm +// CVTTPS2PL xmm xmm // Construct and append a CVTTPS2PL instruction to the active function. // Operates on the global context. func CVTTPS2PL(mx, x operand.Op) { ctx.CVTTPS2PL(mx, x) } @@ -4292,23 +3649,19 @@ func CVTTPS2PL(mx, x operand.Op) { ctx.CVTTPS2PL(mx, x) } // // Forms: // -// CVTTSD2SL xmm r32 // CVTTSD2SL m64 r32 +// CVTTSD2SL xmm r32 // Construct and append a CVTTSD2SL instruction to the active function. func (c *Context) CVTTSD2SL(mx, r operand.Op) { - if inst, err := x86.CVTTSD2SL(mx, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CVTTSD2SL(mx, r)) } // CVTTSD2SL: Convert with Truncation Scalar Double-Precision FP Value to Signed Integer. // // Forms: // -// CVTTSD2SL xmm r32 // CVTTSD2SL m64 r32 +// CVTTSD2SL xmm r32 // Construct and append a CVTTSD2SL instruction to the active function. // Operates on the global context. func CVTTSD2SL(mx, r operand.Op) { ctx.CVTTSD2SL(mx, r) } @@ -4317,23 +3670,19 @@ func CVTTSD2SL(mx, r operand.Op) { ctx.CVTTSD2SL(mx, r) } // // Forms: // -// CVTTSD2SQ xmm r64 // CVTTSD2SQ m64 r64 +// CVTTSD2SQ xmm r64 // Construct and append a CVTTSD2SQ instruction to the active function. func (c *Context) CVTTSD2SQ(mx, r operand.Op) { - if inst, err := x86.CVTTSD2SQ(mx, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CVTTSD2SQ(mx, r)) } // CVTTSD2SQ: Convert with Truncation Scalar Double-Precision FP Value to Signed Integer. // // Forms: // -// CVTTSD2SQ xmm r64 // CVTTSD2SQ m64 r64 +// CVTTSD2SQ xmm r64 // Construct and append a CVTTSD2SQ instruction to the active function. // Operates on the global context. func CVTTSD2SQ(mx, r operand.Op) { ctx.CVTTSD2SQ(mx, r) } @@ -4342,27 +3691,23 @@ func CVTTSD2SQ(mx, r operand.Op) { ctx.CVTTSD2SQ(mx, r) } // // Forms: // -// CVTTSS2SL xmm r32 // CVTTSS2SL m32 r32 -// CVTTSS2SL xmm r64 // CVTTSS2SL m32 r64 +// CVTTSS2SL xmm r32 +// CVTTSS2SL xmm r64 // Construct and append a CVTTSS2SL instruction to the active function. func (c *Context) CVTTSS2SL(mx, r operand.Op) { - if inst, err := x86.CVTTSS2SL(mx, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CVTTSS2SL(mx, r)) } // CVTTSS2SL: Convert with Truncation Scalar Single-Precision FP Value to Dword Integer. // // Forms: // -// CVTTSS2SL xmm r32 // CVTTSS2SL m32 r32 -// CVTTSS2SL xmm r64 // CVTTSS2SL m32 r64 +// CVTTSS2SL xmm r32 +// CVTTSS2SL xmm r64 // Construct and append a CVTTSS2SL instruction to the active function. // Operates on the global context. func CVTTSS2SL(mx, r operand.Op) { ctx.CVTTSS2SL(mx, r) } @@ -4374,11 +3719,7 @@ func CVTTSS2SL(mx, r operand.Op) { ctx.CVTTSS2SL(mx, r) } // CWD // Construct and append a CWD instruction to the active function. func (c *Context) CWD() { - if inst, err := x86.CWD(); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CWD()) } // CWD: Convert Word to Doubleword. @@ -4397,11 +3738,7 @@ func CWD() { ctx.CWD() } // CWDE // Construct and append a CWDE instruction to the active function. func (c *Context) CWDE() { - if inst, err := x86.CWDE(); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.CWDE()) } // CWDE: Convert Word to Doubleword. @@ -4417,23 +3754,19 @@ func CWDE() { ctx.CWDE() } // // Forms: // -// DECB r8 // DECB m8 +// DECB r8 // Construct and append a DECB instruction to the active function. func (c *Context) DECB(mr operand.Op) { - if inst, err := x86.DECB(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.DECB(mr)) } // DECB: Decrement by 1. // // Forms: // -// DECB r8 // DECB m8 +// DECB r8 // Construct and append a DECB instruction to the active function. // Operates on the global context. func DECB(mr operand.Op) { ctx.DECB(mr) } @@ -4442,23 +3775,19 @@ func DECB(mr operand.Op) { ctx.DECB(mr) } // // Forms: // -// DECL r32 // DECL m32 +// DECL r32 // Construct and append a DECL instruction to the active function. func (c *Context) DECL(mr operand.Op) { - if inst, err := x86.DECL(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.DECL(mr)) } // DECL: Decrement by 1. // // Forms: // -// DECL r32 // DECL m32 +// DECL r32 // Construct and append a DECL instruction to the active function. // Operates on the global context. func DECL(mr operand.Op) { ctx.DECL(mr) } @@ -4467,23 +3796,19 @@ func DECL(mr operand.Op) { ctx.DECL(mr) } // // Forms: // -// DECQ r64 // DECQ m64 +// DECQ r64 // Construct and append a DECQ instruction to the active function. func (c *Context) DECQ(mr operand.Op) { - if inst, err := x86.DECQ(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.DECQ(mr)) } // DECQ: Decrement by 1. // // Forms: // -// DECQ r64 // DECQ m64 +// DECQ r64 // Construct and append a DECQ instruction to the active function. // Operates on the global context. func DECQ(mr operand.Op) { ctx.DECQ(mr) } @@ -4492,23 +3817,19 @@ func DECQ(mr operand.Op) { ctx.DECQ(mr) } // // Forms: // -// DECW r16 // DECW m16 +// DECW r16 // Construct and append a DECW instruction to the active function. func (c *Context) DECW(mr operand.Op) { - if inst, err := x86.DECW(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.DECW(mr)) } // DECW: Decrement by 1. // // Forms: // -// DECW r16 // DECW m16 +// DECW r16 // Construct and append a DECW instruction to the active function. // Operates on the global context. func DECW(mr operand.Op) { ctx.DECW(mr) } @@ -4517,23 +3838,19 @@ func DECW(mr operand.Op) { ctx.DECW(mr) } // // Forms: // -// DIVB r8 // DIVB m8 +// DIVB r8 // Construct and append a DIVB instruction to the active function. func (c *Context) DIVB(mr operand.Op) { - if inst, err := x86.DIVB(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.DIVB(mr)) } // DIVB: Unsigned Divide. // // Forms: // -// DIVB r8 // DIVB m8 +// DIVB r8 // Construct and append a DIVB instruction to the active function. // Operates on the global context. func DIVB(mr operand.Op) { ctx.DIVB(mr) } @@ -4542,23 +3859,19 @@ func DIVB(mr operand.Op) { ctx.DIVB(mr) } // // Forms: // -// DIVL r32 // DIVL m32 +// DIVL r32 // Construct and append a DIVL instruction to the active function. func (c *Context) DIVL(mr operand.Op) { - if inst, err := x86.DIVL(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.DIVL(mr)) } // DIVL: Unsigned Divide. // // Forms: // -// DIVL r32 // DIVL m32 +// DIVL r32 // Construct and append a DIVL instruction to the active function. // Operates on the global context. func DIVL(mr operand.Op) { ctx.DIVL(mr) } @@ -4567,23 +3880,19 @@ func DIVL(mr operand.Op) { ctx.DIVL(mr) } // // Forms: // -// DIVPD xmm xmm // DIVPD m128 xmm +// DIVPD xmm xmm // Construct and append a DIVPD instruction to the active function. func (c *Context) DIVPD(mx, x operand.Op) { - if inst, err := x86.DIVPD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.DIVPD(mx, x)) } // DIVPD: Divide Packed Double-Precision Floating-Point Values. // // Forms: // -// DIVPD xmm xmm // DIVPD m128 xmm +// DIVPD xmm xmm // Construct and append a DIVPD instruction to the active function. // Operates on the global context. func DIVPD(mx, x operand.Op) { ctx.DIVPD(mx, x) } @@ -4592,23 +3901,19 @@ func DIVPD(mx, x operand.Op) { ctx.DIVPD(mx, x) } // // Forms: // -// DIVPS xmm xmm // DIVPS m128 xmm +// DIVPS xmm xmm // Construct and append a DIVPS instruction to the active function. func (c *Context) DIVPS(mx, x operand.Op) { - if inst, err := x86.DIVPS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.DIVPS(mx, x)) } // DIVPS: Divide Packed Single-Precision Floating-Point Values. // // Forms: // -// DIVPS xmm xmm // DIVPS m128 xmm +// DIVPS xmm xmm // Construct and append a DIVPS instruction to the active function. // Operates on the global context. func DIVPS(mx, x operand.Op) { ctx.DIVPS(mx, x) } @@ -4617,23 +3922,19 @@ func DIVPS(mx, x operand.Op) { ctx.DIVPS(mx, x) } // // Forms: // -// DIVQ r64 // DIVQ m64 +// DIVQ r64 // Construct and append a DIVQ instruction to the active function. func (c *Context) DIVQ(mr operand.Op) { - if inst, err := x86.DIVQ(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.DIVQ(mr)) } // DIVQ: Unsigned Divide. // // Forms: // -// DIVQ r64 // DIVQ m64 +// DIVQ r64 // Construct and append a DIVQ instruction to the active function. // Operates on the global context. func DIVQ(mr operand.Op) { ctx.DIVQ(mr) } @@ -4642,23 +3943,19 @@ func DIVQ(mr operand.Op) { ctx.DIVQ(mr) } // // Forms: // -// DIVSD xmm xmm // DIVSD m64 xmm +// DIVSD xmm xmm // Construct and append a DIVSD instruction to the active function. func (c *Context) DIVSD(mx, x operand.Op) { - if inst, err := x86.DIVSD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.DIVSD(mx, x)) } // DIVSD: Divide Scalar Double-Precision Floating-Point Values. // // Forms: // -// DIVSD xmm xmm // DIVSD m64 xmm +// DIVSD xmm xmm // Construct and append a DIVSD instruction to the active function. // Operates on the global context. func DIVSD(mx, x operand.Op) { ctx.DIVSD(mx, x) } @@ -4667,23 +3964,19 @@ func DIVSD(mx, x operand.Op) { ctx.DIVSD(mx, x) } // // Forms: // -// DIVSS xmm xmm // DIVSS m32 xmm +// DIVSS xmm xmm // Construct and append a DIVSS instruction to the active function. func (c *Context) DIVSS(mx, x operand.Op) { - if inst, err := x86.DIVSS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.DIVSS(mx, x)) } // DIVSS: Divide Scalar Single-Precision Floating-Point Values. // // Forms: // -// DIVSS xmm xmm // DIVSS m32 xmm +// DIVSS xmm xmm // Construct and append a DIVSS instruction to the active function. // Operates on the global context. func DIVSS(mx, x operand.Op) { ctx.DIVSS(mx, x) } @@ -4692,23 +3985,19 @@ func DIVSS(mx, x operand.Op) { ctx.DIVSS(mx, x) } // // Forms: // -// DIVW r16 // DIVW m16 +// DIVW r16 // Construct and append a DIVW instruction to the active function. func (c *Context) DIVW(mr operand.Op) { - if inst, err := x86.DIVW(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.DIVW(mr)) } // DIVW: Unsigned Divide. // // Forms: // -// DIVW r16 // DIVW m16 +// DIVW r16 // Construct and append a DIVW instruction to the active function. // Operates on the global context. func DIVW(mr operand.Op) { ctx.DIVW(mr) } @@ -4717,23 +4006,19 @@ func DIVW(mr operand.Op) { ctx.DIVW(mr) } // // Forms: // -// DPPD imm8 xmm xmm // DPPD imm8 m128 xmm +// DPPD imm8 xmm xmm // Construct and append a DPPD instruction to the active function. func (c *Context) DPPD(i, mx, x operand.Op) { - if inst, err := x86.DPPD(i, mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.DPPD(i, mx, x)) } // DPPD: Dot Product of Packed Double Precision Floating-Point Values. // // Forms: // -// DPPD imm8 xmm xmm // DPPD imm8 m128 xmm +// DPPD imm8 xmm xmm // Construct and append a DPPD instruction to the active function. // Operates on the global context. func DPPD(i, mx, x operand.Op) { ctx.DPPD(i, mx, x) } @@ -4742,23 +4027,19 @@ func DPPD(i, mx, x operand.Op) { ctx.DPPD(i, mx, x) } // // Forms: // -// DPPS imm8 xmm xmm // DPPS imm8 m128 xmm +// DPPS imm8 xmm xmm // Construct and append a DPPS instruction to the active function. func (c *Context) DPPS(i, mx, x operand.Op) { - if inst, err := x86.DPPS(i, mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.DPPS(i, mx, x)) } // DPPS: Dot Product of Packed Single Precision Floating-Point Values. // // Forms: // -// DPPS imm8 xmm xmm // DPPS imm8 m128 xmm +// DPPS imm8 xmm xmm // Construct and append a DPPS instruction to the active function. // Operates on the global context. func DPPS(i, mx, x operand.Op) { ctx.DPPS(i, mx, x) } @@ -4767,23 +4048,19 @@ func DPPS(i, mx, x operand.Op) { ctx.DPPS(i, mx, x) } // // Forms: // -// EXTRACTPS imm2u xmm r32 // EXTRACTPS imm2u xmm m32 +// EXTRACTPS imm2u xmm r32 // Construct and append a EXTRACTPS instruction to the active function. func (c *Context) EXTRACTPS(i, x, mr operand.Op) { - if inst, err := x86.EXTRACTPS(i, x, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.EXTRACTPS(i, x, mr)) } // EXTRACTPS: Extract Packed Single Precision Floating-Point Value. // // Forms: // -// EXTRACTPS imm2u xmm r32 // EXTRACTPS imm2u xmm m32 +// EXTRACTPS imm2u xmm r32 // Construct and append a EXTRACTPS instruction to the active function. // Operates on the global context. func EXTRACTPS(i, x, mr operand.Op) { ctx.EXTRACTPS(i, x, mr) } @@ -4792,23 +4069,19 @@ func EXTRACTPS(i, x, mr operand.Op) { ctx.EXTRACTPS(i, x, mr) } // // Forms: // -// HADDPD xmm xmm // HADDPD m128 xmm +// HADDPD xmm xmm // Construct and append a HADDPD instruction to the active function. func (c *Context) HADDPD(mx, x operand.Op) { - if inst, err := x86.HADDPD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.HADDPD(mx, x)) } // HADDPD: Packed Double-FP Horizontal Add. // // Forms: // -// HADDPD xmm xmm // HADDPD m128 xmm +// HADDPD xmm xmm // Construct and append a HADDPD instruction to the active function. // Operates on the global context. func HADDPD(mx, x operand.Op) { ctx.HADDPD(mx, x) } @@ -4817,23 +4090,19 @@ func HADDPD(mx, x operand.Op) { ctx.HADDPD(mx, x) } // // Forms: // -// HADDPS xmm xmm // HADDPS m128 xmm +// HADDPS xmm xmm // Construct and append a HADDPS instruction to the active function. func (c *Context) HADDPS(mx, x operand.Op) { - if inst, err := x86.HADDPS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.HADDPS(mx, x)) } // HADDPS: Packed Single-FP Horizontal Add. // // Forms: // -// HADDPS xmm xmm // HADDPS m128 xmm +// HADDPS xmm xmm // Construct and append a HADDPS instruction to the active function. // Operates on the global context. func HADDPS(mx, x operand.Op) { ctx.HADDPS(mx, x) } @@ -4842,23 +4111,19 @@ func HADDPS(mx, x operand.Op) { ctx.HADDPS(mx, x) } // // Forms: // -// HSUBPD xmm xmm // HSUBPD m128 xmm +// HSUBPD xmm xmm // Construct and append a HSUBPD instruction to the active function. func (c *Context) HSUBPD(mx, x operand.Op) { - if inst, err := x86.HSUBPD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.HSUBPD(mx, x)) } // HSUBPD: Packed Double-FP Horizontal Subtract. // // Forms: // -// HSUBPD xmm xmm // HSUBPD m128 xmm +// HSUBPD xmm xmm // Construct and append a HSUBPD instruction to the active function. // Operates on the global context. func HSUBPD(mx, x operand.Op) { ctx.HSUBPD(mx, x) } @@ -4867,23 +4132,19 @@ func HSUBPD(mx, x operand.Op) { ctx.HSUBPD(mx, x) } // // Forms: // -// HSUBPS xmm xmm // HSUBPS m128 xmm +// HSUBPS xmm xmm // Construct and append a HSUBPS instruction to the active function. func (c *Context) HSUBPS(mx, x operand.Op) { - if inst, err := x86.HSUBPS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.HSUBPS(mx, x)) } // HSUBPS: Packed Single-FP Horizontal Subtract. // // Forms: // -// HSUBPS xmm xmm // HSUBPS m128 xmm +// HSUBPS xmm xmm // Construct and append a HSUBPS instruction to the active function. // Operates on the global context. func HSUBPS(mx, x operand.Op) { ctx.HSUBPS(mx, x) } @@ -4892,23 +4153,19 @@ func HSUBPS(mx, x operand.Op) { ctx.HSUBPS(mx, x) } // // Forms: // -// IDIVB r8 // IDIVB m8 +// IDIVB r8 // Construct and append a IDIVB instruction to the active function. func (c *Context) IDIVB(mr operand.Op) { - if inst, err := x86.IDIVB(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.IDIVB(mr)) } // IDIVB: Signed Divide. // // Forms: // -// IDIVB r8 // IDIVB m8 +// IDIVB r8 // Construct and append a IDIVB instruction to the active function. // Operates on the global context. func IDIVB(mr operand.Op) { ctx.IDIVB(mr) } @@ -4917,23 +4174,19 @@ func IDIVB(mr operand.Op) { ctx.IDIVB(mr) } // // Forms: // -// IDIVL r32 // IDIVL m32 +// IDIVL r32 // Construct and append a IDIVL instruction to the active function. func (c *Context) IDIVL(mr operand.Op) { - if inst, err := x86.IDIVL(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.IDIVL(mr)) } // IDIVL: Signed Divide. // // Forms: // -// IDIVL r32 // IDIVL m32 +// IDIVL r32 // Construct and append a IDIVL instruction to the active function. // Operates on the global context. func IDIVL(mr operand.Op) { ctx.IDIVL(mr) } @@ -4942,23 +4195,19 @@ func IDIVL(mr operand.Op) { ctx.IDIVL(mr) } // // Forms: // -// IDIVQ r64 // IDIVQ m64 +// IDIVQ r64 // Construct and append a IDIVQ instruction to the active function. func (c *Context) IDIVQ(mr operand.Op) { - if inst, err := x86.IDIVQ(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.IDIVQ(mr)) } // IDIVQ: Signed Divide. // // Forms: // -// IDIVQ r64 // IDIVQ m64 +// IDIVQ r64 // Construct and append a IDIVQ instruction to the active function. // Operates on the global context. func IDIVQ(mr operand.Op) { ctx.IDIVQ(mr) } @@ -4967,23 +4216,19 @@ func IDIVQ(mr operand.Op) { ctx.IDIVQ(mr) } // // Forms: // -// IDIVW r16 // IDIVW m16 +// IDIVW r16 // Construct and append a IDIVW instruction to the active function. func (c *Context) IDIVW(mr operand.Op) { - if inst, err := x86.IDIVW(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.IDIVW(mr)) } // IDIVW: Signed Divide. // // Forms: // -// IDIVW r16 // IDIVW m16 +// IDIVW r16 // Construct and append a IDIVW instruction to the active function. // Operates on the global context. func IDIVW(mr operand.Op) { ctx.IDIVW(mr) } @@ -4992,27 +4237,23 @@ func IDIVW(mr operand.Op) { ctx.IDIVW(mr) } // // Forms: // -// IMUL3L imm8 r32 r32 +// IMUL3L imm32 m32 r32 // IMUL3L imm32 r32 r32 // IMUL3L imm8 m32 r32 -// IMUL3L imm32 m32 r32 +// IMUL3L imm8 r32 r32 // Construct and append a IMUL3L instruction to the active function. func (c *Context) IMUL3L(i, mr, r operand.Op) { - if inst, err := x86.IMUL3L(i, mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.IMUL3L(i, mr, r)) } // IMUL3L: Signed Multiply. // // Forms: // -// IMUL3L imm8 r32 r32 +// IMUL3L imm32 m32 r32 // IMUL3L imm32 r32 r32 // IMUL3L imm8 m32 r32 -// IMUL3L imm32 m32 r32 +// IMUL3L imm8 r32 r32 // Construct and append a IMUL3L instruction to the active function. // Operates on the global context. func IMUL3L(i, mr, r operand.Op) { ctx.IMUL3L(i, mr, r) } @@ -5021,27 +4262,23 @@ func IMUL3L(i, mr, r operand.Op) { ctx.IMUL3L(i, mr, r) } // // Forms: // -// IMUL3Q imm8 r64 r64 +// IMUL3Q imm32 m64 r64 // IMUL3Q imm32 r64 r64 // IMUL3Q imm8 m64 r64 -// IMUL3Q imm32 m64 r64 +// IMUL3Q imm8 r64 r64 // Construct and append a IMUL3Q instruction to the active function. func (c *Context) IMUL3Q(i, mr, r operand.Op) { - if inst, err := x86.IMUL3Q(i, mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.IMUL3Q(i, mr, r)) } // IMUL3Q: Signed Multiply. // // Forms: // -// IMUL3Q imm8 r64 r64 +// IMUL3Q imm32 m64 r64 // IMUL3Q imm32 r64 r64 // IMUL3Q imm8 m64 r64 -// IMUL3Q imm32 m64 r64 +// IMUL3Q imm8 r64 r64 // Construct and append a IMUL3Q instruction to the active function. // Operates on the global context. func IMUL3Q(i, mr, r operand.Op) { ctx.IMUL3Q(i, mr, r) } @@ -5050,27 +4287,23 @@ func IMUL3Q(i, mr, r operand.Op) { ctx.IMUL3Q(i, mr, r) } // // Forms: // -// IMUL3W imm8 r16 r16 +// IMUL3W imm16 m16 r16 // IMUL3W imm16 r16 r16 // IMUL3W imm8 m16 r16 -// IMUL3W imm16 m16 r16 +// IMUL3W imm8 r16 r16 // Construct and append a IMUL3W instruction to the active function. func (c *Context) IMUL3W(i, mr, r operand.Op) { - if inst, err := x86.IMUL3W(i, mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.IMUL3W(i, mr, r)) } // IMUL3W: Signed Multiply. // // Forms: // -// IMUL3W imm8 r16 r16 +// IMUL3W imm16 m16 r16 // IMUL3W imm16 r16 r16 // IMUL3W imm8 m16 r16 -// IMUL3W imm16 m16 r16 +// IMUL3W imm8 r16 r16 // Construct and append a IMUL3W instruction to the active function. // Operates on the global context. func IMUL3W(i, mr, r operand.Op) { ctx.IMUL3W(i, mr, r) } @@ -5079,23 +4312,19 @@ func IMUL3W(i, mr, r operand.Op) { ctx.IMUL3W(i, mr, r) } // // Forms: // -// IMULB r8 // IMULB m8 +// IMULB r8 // Construct and append a IMULB instruction to the active function. func (c *Context) IMULB(mr operand.Op) { - if inst, err := x86.IMULB(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.IMULB(mr)) } // IMULB: Signed Multiply. // // Forms: // -// IMULB r8 // IMULB m8 +// IMULB r8 // Construct and append a IMULB instruction to the active function. // Operates on the global context. func IMULB(mr operand.Op) { ctx.IMULB(mr) } @@ -5104,27 +4333,23 @@ func IMULB(mr operand.Op) { ctx.IMULB(mr) } // // Forms: // -// IMULL r32 +// IMULL m32 r32 // IMULL m32 // IMULL r32 r32 -// IMULL m32 r32 +// IMULL r32 // Construct and append a IMULL instruction to the active function. func (c *Context) IMULL(ops ...operand.Op) { - if inst, err := x86.IMULL(ops...); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.IMULL(ops...)) } // IMULL: Signed Multiply. // // Forms: // -// IMULL r32 +// IMULL m32 r32 // IMULL m32 // IMULL r32 r32 -// IMULL m32 r32 +// IMULL r32 // Construct and append a IMULL instruction to the active function. // Operates on the global context. func IMULL(ops ...operand.Op) { ctx.IMULL(ops...) } @@ -5133,27 +4358,23 @@ func IMULL(ops ...operand.Op) { ctx.IMULL(ops...) } // // Forms: // -// IMULQ r64 +// IMULQ m64 r64 // IMULQ m64 // IMULQ r64 r64 -// IMULQ m64 r64 +// IMULQ r64 // Construct and append a IMULQ instruction to the active function. func (c *Context) IMULQ(ops ...operand.Op) { - if inst, err := x86.IMULQ(ops...); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.IMULQ(ops...)) } // IMULQ: Signed Multiply. // // Forms: // -// IMULQ r64 +// IMULQ m64 r64 // IMULQ m64 // IMULQ r64 r64 -// IMULQ m64 r64 +// IMULQ r64 // Construct and append a IMULQ instruction to the active function. // Operates on the global context. func IMULQ(ops ...operand.Op) { ctx.IMULQ(ops...) } @@ -5162,27 +4383,23 @@ func IMULQ(ops ...operand.Op) { ctx.IMULQ(ops...) } // // Forms: // -// IMULW r16 +// IMULW m16 r16 // IMULW m16 // IMULW r16 r16 -// IMULW m16 r16 +// IMULW r16 // Construct and append a IMULW instruction to the active function. func (c *Context) IMULW(ops ...operand.Op) { - if inst, err := x86.IMULW(ops...); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.IMULW(ops...)) } // IMULW: Signed Multiply. // // Forms: // -// IMULW r16 +// IMULW m16 r16 // IMULW m16 // IMULW r16 r16 -// IMULW m16 r16 +// IMULW r16 // Construct and append a IMULW instruction to the active function. // Operates on the global context. func IMULW(ops ...operand.Op) { ctx.IMULW(ops...) } @@ -5191,23 +4408,19 @@ func IMULW(ops ...operand.Op) { ctx.IMULW(ops...) } // // Forms: // -// INCB r8 // INCB m8 +// INCB r8 // Construct and append a INCB instruction to the active function. func (c *Context) INCB(mr operand.Op) { - if inst, err := x86.INCB(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.INCB(mr)) } // INCB: Increment by 1. // // Forms: // -// INCB r8 // INCB m8 +// INCB r8 // Construct and append a INCB instruction to the active function. // Operates on the global context. func INCB(mr operand.Op) { ctx.INCB(mr) } @@ -5216,23 +4429,19 @@ func INCB(mr operand.Op) { ctx.INCB(mr) } // // Forms: // -// INCL r32 // INCL m32 +// INCL r32 // Construct and append a INCL instruction to the active function. func (c *Context) INCL(mr operand.Op) { - if inst, err := x86.INCL(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.INCL(mr)) } // INCL: Increment by 1. // // Forms: // -// INCL r32 // INCL m32 +// INCL r32 // Construct and append a INCL instruction to the active function. // Operates on the global context. func INCL(mr operand.Op) { ctx.INCL(mr) } @@ -5241,23 +4450,19 @@ func INCL(mr operand.Op) { ctx.INCL(mr) } // // Forms: // -// INCQ r64 // INCQ m64 +// INCQ r64 // Construct and append a INCQ instruction to the active function. func (c *Context) INCQ(mr operand.Op) { - if inst, err := x86.INCQ(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.INCQ(mr)) } // INCQ: Increment by 1. // // Forms: // -// INCQ r64 // INCQ m64 +// INCQ r64 // Construct and append a INCQ instruction to the active function. // Operates on the global context. func INCQ(mr operand.Op) { ctx.INCQ(mr) } @@ -5266,23 +4471,19 @@ func INCQ(mr operand.Op) { ctx.INCQ(mr) } // // Forms: // -// INCW r16 // INCW m16 +// INCW r16 // Construct and append a INCW instruction to the active function. func (c *Context) INCW(mr operand.Op) { - if inst, err := x86.INCW(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.INCW(mr)) } // INCW: Increment by 1. // // Forms: // -// INCW r16 // INCW m16 +// INCW r16 // Construct and append a INCW instruction to the active function. // Operates on the global context. func INCW(mr operand.Op) { ctx.INCW(mr) } @@ -5291,23 +4492,19 @@ func INCW(mr operand.Op) { ctx.INCW(mr) } // // Forms: // -// INSERTPS imm8 xmm xmm // INSERTPS imm8 m32 xmm +// INSERTPS imm8 xmm xmm // Construct and append a INSERTPS instruction to the active function. func (c *Context) INSERTPS(i, mx, x operand.Op) { - if inst, err := x86.INSERTPS(i, mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.INSERTPS(i, mx, x)) } // INSERTPS: Insert Packed Single Precision Floating-Point Value. // // Forms: // -// INSERTPS imm8 xmm xmm // INSERTPS imm8 m32 xmm +// INSERTPS imm8 xmm xmm // Construct and append a INSERTPS instruction to the active function. // Operates on the global context. func INSERTPS(i, mx, x operand.Op) { ctx.INSERTPS(i, mx, x) } @@ -5320,11 +4517,7 @@ func INSERTPS(i, mx, x operand.Op) { ctx.INSERTPS(i, mx, x) } // INT imm8 // Construct and append a INT instruction to the active function. func (c *Context) INT(i operand.Op) { - if inst, err := x86.INT(i); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.INT(i)) } // INT: Call to Interrupt Procedure. @@ -5341,23 +4534,19 @@ func INT(i operand.Op) { ctx.INT(i) } // // Forms: // -// JA rel8 // JA rel32 +// JA rel8 // Construct and append a JA instruction to the active function. func (c *Context) JA(r operand.Op) { - if inst, err := x86.JA(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JA(r)) } // JA: Jump if above (CF == 0 and ZF == 0). // // Forms: // -// JA rel8 // JA rel32 +// JA rel8 // Construct and append a JA instruction to the active function. // Operates on the global context. func JA(r operand.Op) { ctx.JA(r) } @@ -5366,23 +4555,19 @@ func JA(r operand.Op) { ctx.JA(r) } // // Forms: // -// JAE rel8 // JAE rel32 +// JAE rel8 // Construct and append a JAE instruction to the active function. func (c *Context) JAE(r operand.Op) { - if inst, err := x86.JAE(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JAE(r)) } // JAE: Jump if above or equal (CF == 0). // // Forms: // -// JAE rel8 // JAE rel32 +// JAE rel8 // Construct and append a JAE instruction to the active function. // Operates on the global context. func JAE(r operand.Op) { ctx.JAE(r) } @@ -5391,23 +4576,19 @@ func JAE(r operand.Op) { ctx.JAE(r) } // // Forms: // -// JB rel8 // JB rel32 +// JB rel8 // Construct and append a JB instruction to the active function. func (c *Context) JB(r operand.Op) { - if inst, err := x86.JB(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JB(r)) } // JB: Jump if below (CF == 1). // // Forms: // -// JB rel8 // JB rel32 +// JB rel8 // Construct and append a JB instruction to the active function. // Operates on the global context. func JB(r operand.Op) { ctx.JB(r) } @@ -5416,23 +4597,19 @@ func JB(r operand.Op) { ctx.JB(r) } // // Forms: // -// JBE rel8 // JBE rel32 +// JBE rel8 // Construct and append a JBE instruction to the active function. func (c *Context) JBE(r operand.Op) { - if inst, err := x86.JBE(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JBE(r)) } // JBE: Jump if below or equal (CF == 1 or ZF == 1). // // Forms: // -// JBE rel8 // JBE rel32 +// JBE rel8 // Construct and append a JBE instruction to the active function. // Operates on the global context. func JBE(r operand.Op) { ctx.JBE(r) } @@ -5441,23 +4618,19 @@ func JBE(r operand.Op) { ctx.JBE(r) } // // Forms: // -// JC rel8 // JC rel32 +// JC rel8 // Construct and append a JC instruction to the active function. func (c *Context) JC(r operand.Op) { - if inst, err := x86.JC(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JC(r)) } // JC: Jump if below (CF == 1). // // Forms: // -// JC rel8 // JC rel32 +// JC rel8 // Construct and append a JC instruction to the active function. // Operates on the global context. func JC(r operand.Op) { ctx.JC(r) } @@ -5466,23 +4639,19 @@ func JC(r operand.Op) { ctx.JC(r) } // // Forms: // -// JCC rel8 // JCC rel32 +// JCC rel8 // Construct and append a JCC instruction to the active function. func (c *Context) JCC(r operand.Op) { - if inst, err := x86.JCC(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JCC(r)) } // JCC: Jump if above or equal (CF == 0). // // Forms: // -// JCC rel8 // JCC rel32 +// JCC rel8 // Construct and append a JCC instruction to the active function. // Operates on the global context. func JCC(r operand.Op) { ctx.JCC(r) } @@ -5491,23 +4660,19 @@ func JCC(r operand.Op) { ctx.JCC(r) } // // Forms: // -// JCS rel8 // JCS rel32 +// JCS rel8 // Construct and append a JCS instruction to the active function. func (c *Context) JCS(r operand.Op) { - if inst, err := x86.JCS(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JCS(r)) } // JCS: Jump if below (CF == 1). // // Forms: // -// JCS rel8 // JCS rel32 +// JCS rel8 // Construct and append a JCS instruction to the active function. // Operates on the global context. func JCS(r operand.Op) { ctx.JCS(r) } @@ -5519,11 +4684,7 @@ func JCS(r operand.Op) { ctx.JCS(r) } // JCXZL rel8 // Construct and append a JCXZL instruction to the active function. func (c *Context) JCXZL(r operand.Op) { - if inst, err := x86.JCXZL(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JCXZL(r)) } // JCXZL: Jump if ECX register is 0. @@ -5542,11 +4703,7 @@ func JCXZL(r operand.Op) { ctx.JCXZL(r) } // JCXZQ rel8 // Construct and append a JCXZQ instruction to the active function. func (c *Context) JCXZQ(r operand.Op) { - if inst, err := x86.JCXZQ(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JCXZQ(r)) } // JCXZQ: Jump if RCX register is 0. @@ -5562,23 +4719,19 @@ func JCXZQ(r operand.Op) { ctx.JCXZQ(r) } // // Forms: // -// JE rel8 // JE rel32 +// JE rel8 // Construct and append a JE instruction to the active function. func (c *Context) JE(r operand.Op) { - if inst, err := x86.JE(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JE(r)) } // JE: Jump if equal (ZF == 1). // // Forms: // -// JE rel8 // JE rel32 +// JE rel8 // Construct and append a JE instruction to the active function. // Operates on the global context. func JE(r operand.Op) { ctx.JE(r) } @@ -5587,23 +4740,19 @@ func JE(r operand.Op) { ctx.JE(r) } // // Forms: // -// JEQ rel8 // JEQ rel32 +// JEQ rel8 // Construct and append a JEQ instruction to the active function. func (c *Context) JEQ(r operand.Op) { - if inst, err := x86.JEQ(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JEQ(r)) } // JEQ: Jump if equal (ZF == 1). // // Forms: // -// JEQ rel8 // JEQ rel32 +// JEQ rel8 // Construct and append a JEQ instruction to the active function. // Operates on the global context. func JEQ(r operand.Op) { ctx.JEQ(r) } @@ -5612,23 +4761,19 @@ func JEQ(r operand.Op) { ctx.JEQ(r) } // // Forms: // -// JG rel8 // JG rel32 +// JG rel8 // Construct and append a JG instruction to the active function. func (c *Context) JG(r operand.Op) { - if inst, err := x86.JG(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JG(r)) } // JG: Jump if greater (ZF == 0 and SF == OF). // // Forms: // -// JG rel8 // JG rel32 +// JG rel8 // Construct and append a JG instruction to the active function. // Operates on the global context. func JG(r operand.Op) { ctx.JG(r) } @@ -5637,23 +4782,19 @@ func JG(r operand.Op) { ctx.JG(r) } // // Forms: // -// JGE rel8 // JGE rel32 +// JGE rel8 // Construct and append a JGE instruction to the active function. func (c *Context) JGE(r operand.Op) { - if inst, err := x86.JGE(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JGE(r)) } // JGE: Jump if greater or equal (SF == OF). // // Forms: // -// JGE rel8 // JGE rel32 +// JGE rel8 // Construct and append a JGE instruction to the active function. // Operates on the global context. func JGE(r operand.Op) { ctx.JGE(r) } @@ -5662,23 +4803,19 @@ func JGE(r operand.Op) { ctx.JGE(r) } // // Forms: // -// JGT rel8 // JGT rel32 +// JGT rel8 // Construct and append a JGT instruction to the active function. func (c *Context) JGT(r operand.Op) { - if inst, err := x86.JGT(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JGT(r)) } // JGT: Jump if greater (ZF == 0 and SF == OF). // // Forms: // -// JGT rel8 // JGT rel32 +// JGT rel8 // Construct and append a JGT instruction to the active function. // Operates on the global context. func JGT(r operand.Op) { ctx.JGT(r) } @@ -5687,23 +4824,19 @@ func JGT(r operand.Op) { ctx.JGT(r) } // // Forms: // -// JHI rel8 // JHI rel32 +// JHI rel8 // Construct and append a JHI instruction to the active function. func (c *Context) JHI(r operand.Op) { - if inst, err := x86.JHI(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JHI(r)) } // JHI: Jump if above (CF == 0 and ZF == 0). // // Forms: // -// JHI rel8 // JHI rel32 +// JHI rel8 // Construct and append a JHI instruction to the active function. // Operates on the global context. func JHI(r operand.Op) { ctx.JHI(r) } @@ -5712,23 +4845,19 @@ func JHI(r operand.Op) { ctx.JHI(r) } // // Forms: // -// JHS rel8 // JHS rel32 +// JHS rel8 // Construct and append a JHS instruction to the active function. func (c *Context) JHS(r operand.Op) { - if inst, err := x86.JHS(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JHS(r)) } // JHS: Jump if above or equal (CF == 0). // // Forms: // -// JHS rel8 // JHS rel32 +// JHS rel8 // Construct and append a JHS instruction to the active function. // Operates on the global context. func JHS(r operand.Op) { ctx.JHS(r) } @@ -5737,23 +4866,19 @@ func JHS(r operand.Op) { ctx.JHS(r) } // // Forms: // -// JL rel8 // JL rel32 +// JL rel8 // Construct and append a JL instruction to the active function. func (c *Context) JL(r operand.Op) { - if inst, err := x86.JL(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JL(r)) } // JL: Jump if less (SF != OF). // // Forms: // -// JL rel8 // JL rel32 +// JL rel8 // Construct and append a JL instruction to the active function. // Operates on the global context. func JL(r operand.Op) { ctx.JL(r) } @@ -5762,23 +4887,19 @@ func JL(r operand.Op) { ctx.JL(r) } // // Forms: // -// JLE rel8 // JLE rel32 +// JLE rel8 // Construct and append a JLE instruction to the active function. func (c *Context) JLE(r operand.Op) { - if inst, err := x86.JLE(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JLE(r)) } // JLE: Jump if less or equal (ZF == 1 or SF != OF). // // Forms: // -// JLE rel8 // JLE rel32 +// JLE rel8 // Construct and append a JLE instruction to the active function. // Operates on the global context. func JLE(r operand.Op) { ctx.JLE(r) } @@ -5787,23 +4908,19 @@ func JLE(r operand.Op) { ctx.JLE(r) } // // Forms: // -// JLO rel8 // JLO rel32 +// JLO rel8 // Construct and append a JLO instruction to the active function. func (c *Context) JLO(r operand.Op) { - if inst, err := x86.JLO(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JLO(r)) } // JLO: Jump if below (CF == 1). // // Forms: // -// JLO rel8 // JLO rel32 +// JLO rel8 // Construct and append a JLO instruction to the active function. // Operates on the global context. func JLO(r operand.Op) { ctx.JLO(r) } @@ -5812,23 +4929,19 @@ func JLO(r operand.Op) { ctx.JLO(r) } // // Forms: // -// JLS rel8 // JLS rel32 +// JLS rel8 // Construct and append a JLS instruction to the active function. func (c *Context) JLS(r operand.Op) { - if inst, err := x86.JLS(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JLS(r)) } // JLS: Jump if below or equal (CF == 1 or ZF == 1). // // Forms: // -// JLS rel8 // JLS rel32 +// JLS rel8 // Construct and append a JLS instruction to the active function. // Operates on the global context. func JLS(r operand.Op) { ctx.JLS(r) } @@ -5837,23 +4950,19 @@ func JLS(r operand.Op) { ctx.JLS(r) } // // Forms: // -// JLT rel8 // JLT rel32 +// JLT rel8 // Construct and append a JLT instruction to the active function. func (c *Context) JLT(r operand.Op) { - if inst, err := x86.JLT(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JLT(r)) } // JLT: Jump if less (SF != OF). // // Forms: // -// JLT rel8 // JLT rel32 +// JLT rel8 // Construct and append a JLT instruction to the active function. // Operates on the global context. func JLT(r operand.Op) { ctx.JLT(r) } @@ -5862,23 +4971,19 @@ func JLT(r operand.Op) { ctx.JLT(r) } // // Forms: // -// JMI rel8 // JMI rel32 +// JMI rel8 // Construct and append a JMI instruction to the active function. func (c *Context) JMI(r operand.Op) { - if inst, err := x86.JMI(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JMI(r)) } // JMI: Jump if sign (SF == 1). // // Forms: // -// JMI rel8 // JMI rel32 +// JMI rel8 // Construct and append a JMI instruction to the active function. // Operates on the global context. func JMI(r operand.Op) { ctx.JMI(r) } @@ -5887,27 +4992,23 @@ func JMI(r operand.Op) { ctx.JMI(r) } // // Forms: // -// JMP rel8 // JMP rel32 -// JMP r64 +// JMP rel8 // JMP m64 +// JMP r64 // Construct and append a JMP instruction to the active function. func (c *Context) JMP(mr operand.Op) { - if inst, err := x86.JMP(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JMP(mr)) } // JMP: Jump Unconditionally. // // Forms: // -// JMP rel8 // JMP rel32 -// JMP r64 +// JMP rel8 // JMP m64 +// JMP r64 // Construct and append a JMP instruction to the active function. // Operates on the global context. func JMP(mr operand.Op) { ctx.JMP(mr) } @@ -5916,23 +5017,19 @@ func JMP(mr operand.Op) { ctx.JMP(mr) } // // Forms: // -// JNA rel8 // JNA rel32 +// JNA rel8 // Construct and append a JNA instruction to the active function. func (c *Context) JNA(r operand.Op) { - if inst, err := x86.JNA(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JNA(r)) } // JNA: Jump if below or equal (CF == 1 or ZF == 1). // // Forms: // -// JNA rel8 // JNA rel32 +// JNA rel8 // Construct and append a JNA instruction to the active function. // Operates on the global context. func JNA(r operand.Op) { ctx.JNA(r) } @@ -5941,23 +5038,19 @@ func JNA(r operand.Op) { ctx.JNA(r) } // // Forms: // -// JNAE rel8 // JNAE rel32 +// JNAE rel8 // Construct and append a JNAE instruction to the active function. func (c *Context) JNAE(r operand.Op) { - if inst, err := x86.JNAE(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JNAE(r)) } // JNAE: Jump if below (CF == 1). // // Forms: // -// JNAE rel8 // JNAE rel32 +// JNAE rel8 // Construct and append a JNAE instruction to the active function. // Operates on the global context. func JNAE(r operand.Op) { ctx.JNAE(r) } @@ -5966,23 +5059,19 @@ func JNAE(r operand.Op) { ctx.JNAE(r) } // // Forms: // -// JNB rel8 // JNB rel32 +// JNB rel8 // Construct and append a JNB instruction to the active function. func (c *Context) JNB(r operand.Op) { - if inst, err := x86.JNB(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JNB(r)) } // JNB: Jump if above or equal (CF == 0). // // Forms: // -// JNB rel8 // JNB rel32 +// JNB rel8 // Construct and append a JNB instruction to the active function. // Operates on the global context. func JNB(r operand.Op) { ctx.JNB(r) } @@ -5991,23 +5080,19 @@ func JNB(r operand.Op) { ctx.JNB(r) } // // Forms: // -// JNBE rel8 // JNBE rel32 +// JNBE rel8 // Construct and append a JNBE instruction to the active function. func (c *Context) JNBE(r operand.Op) { - if inst, err := x86.JNBE(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JNBE(r)) } // JNBE: Jump if above (CF == 0 and ZF == 0). // // Forms: // -// JNBE rel8 // JNBE rel32 +// JNBE rel8 // Construct and append a JNBE instruction to the active function. // Operates on the global context. func JNBE(r operand.Op) { ctx.JNBE(r) } @@ -6016,23 +5101,19 @@ func JNBE(r operand.Op) { ctx.JNBE(r) } // // Forms: // -// JNC rel8 // JNC rel32 +// JNC rel8 // Construct and append a JNC instruction to the active function. func (c *Context) JNC(r operand.Op) { - if inst, err := x86.JNC(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JNC(r)) } // JNC: Jump if above or equal (CF == 0). // // Forms: // -// JNC rel8 // JNC rel32 +// JNC rel8 // Construct and append a JNC instruction to the active function. // Operates on the global context. func JNC(r operand.Op) { ctx.JNC(r) } @@ -6041,23 +5122,19 @@ func JNC(r operand.Op) { ctx.JNC(r) } // // Forms: // -// JNE rel8 // JNE rel32 +// JNE rel8 // Construct and append a JNE instruction to the active function. func (c *Context) JNE(r operand.Op) { - if inst, err := x86.JNE(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JNE(r)) } // JNE: Jump if not equal (ZF == 0). // // Forms: // -// JNE rel8 // JNE rel32 +// JNE rel8 // Construct and append a JNE instruction to the active function. // Operates on the global context. func JNE(r operand.Op) { ctx.JNE(r) } @@ -6066,23 +5143,19 @@ func JNE(r operand.Op) { ctx.JNE(r) } // // Forms: // -// JNG rel8 // JNG rel32 +// JNG rel8 // Construct and append a JNG instruction to the active function. func (c *Context) JNG(r operand.Op) { - if inst, err := x86.JNG(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JNG(r)) } // JNG: Jump if less or equal (ZF == 1 or SF != OF). // // Forms: // -// JNG rel8 // JNG rel32 +// JNG rel8 // Construct and append a JNG instruction to the active function. // Operates on the global context. func JNG(r operand.Op) { ctx.JNG(r) } @@ -6091,23 +5164,19 @@ func JNG(r operand.Op) { ctx.JNG(r) } // // Forms: // -// JNGE rel8 // JNGE rel32 +// JNGE rel8 // Construct and append a JNGE instruction to the active function. func (c *Context) JNGE(r operand.Op) { - if inst, err := x86.JNGE(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JNGE(r)) } // JNGE: Jump if less (SF != OF). // // Forms: // -// JNGE rel8 // JNGE rel32 +// JNGE rel8 // Construct and append a JNGE instruction to the active function. // Operates on the global context. func JNGE(r operand.Op) { ctx.JNGE(r) } @@ -6116,23 +5185,19 @@ func JNGE(r operand.Op) { ctx.JNGE(r) } // // Forms: // -// JNL rel8 // JNL rel32 +// JNL rel8 // Construct and append a JNL instruction to the active function. func (c *Context) JNL(r operand.Op) { - if inst, err := x86.JNL(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JNL(r)) } // JNL: Jump if greater or equal (SF == OF). // // Forms: // -// JNL rel8 // JNL rel32 +// JNL rel8 // Construct and append a JNL instruction to the active function. // Operates on the global context. func JNL(r operand.Op) { ctx.JNL(r) } @@ -6141,23 +5206,19 @@ func JNL(r operand.Op) { ctx.JNL(r) } // // Forms: // -// JNLE rel8 // JNLE rel32 +// JNLE rel8 // Construct and append a JNLE instruction to the active function. func (c *Context) JNLE(r operand.Op) { - if inst, err := x86.JNLE(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JNLE(r)) } // JNLE: Jump if greater (ZF == 0 and SF == OF). // // Forms: // -// JNLE rel8 // JNLE rel32 +// JNLE rel8 // Construct and append a JNLE instruction to the active function. // Operates on the global context. func JNLE(r operand.Op) { ctx.JNLE(r) } @@ -6166,23 +5227,19 @@ func JNLE(r operand.Op) { ctx.JNLE(r) } // // Forms: // -// JNO rel8 // JNO rel32 +// JNO rel8 // Construct and append a JNO instruction to the active function. func (c *Context) JNO(r operand.Op) { - if inst, err := x86.JNO(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JNO(r)) } // JNO: Jump if not overflow (OF == 0). // // Forms: // -// JNO rel8 // JNO rel32 +// JNO rel8 // Construct and append a JNO instruction to the active function. // Operates on the global context. func JNO(r operand.Op) { ctx.JNO(r) } @@ -6191,23 +5248,19 @@ func JNO(r operand.Op) { ctx.JNO(r) } // // Forms: // -// JNP rel8 // JNP rel32 +// JNP rel8 // Construct and append a JNP instruction to the active function. func (c *Context) JNP(r operand.Op) { - if inst, err := x86.JNP(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JNP(r)) } // JNP: Jump if not parity (PF == 0). // // Forms: // -// JNP rel8 // JNP rel32 +// JNP rel8 // Construct and append a JNP instruction to the active function. // Operates on the global context. func JNP(r operand.Op) { ctx.JNP(r) } @@ -6216,23 +5269,19 @@ func JNP(r operand.Op) { ctx.JNP(r) } // // Forms: // -// JNS rel8 // JNS rel32 +// JNS rel8 // Construct and append a JNS instruction to the active function. func (c *Context) JNS(r operand.Op) { - if inst, err := x86.JNS(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JNS(r)) } // JNS: Jump if not sign (SF == 0). // // Forms: // -// JNS rel8 // JNS rel32 +// JNS rel8 // Construct and append a JNS instruction to the active function. // Operates on the global context. func JNS(r operand.Op) { ctx.JNS(r) } @@ -6241,23 +5290,19 @@ func JNS(r operand.Op) { ctx.JNS(r) } // // Forms: // -// JNZ rel8 // JNZ rel32 +// JNZ rel8 // Construct and append a JNZ instruction to the active function. func (c *Context) JNZ(r operand.Op) { - if inst, err := x86.JNZ(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JNZ(r)) } // JNZ: Jump if not equal (ZF == 0). // // Forms: // -// JNZ rel8 // JNZ rel32 +// JNZ rel8 // Construct and append a JNZ instruction to the active function. // Operates on the global context. func JNZ(r operand.Op) { ctx.JNZ(r) } @@ -6266,23 +5311,19 @@ func JNZ(r operand.Op) { ctx.JNZ(r) } // // Forms: // -// JO rel8 // JO rel32 +// JO rel8 // Construct and append a JO instruction to the active function. func (c *Context) JO(r operand.Op) { - if inst, err := x86.JO(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JO(r)) } // JO: Jump if overflow (OF == 1). // // Forms: // -// JO rel8 // JO rel32 +// JO rel8 // Construct and append a JO instruction to the active function. // Operates on the global context. func JO(r operand.Op) { ctx.JO(r) } @@ -6291,23 +5332,19 @@ func JO(r operand.Op) { ctx.JO(r) } // // Forms: // -// JOC rel8 // JOC rel32 +// JOC rel8 // Construct and append a JOC instruction to the active function. func (c *Context) JOC(r operand.Op) { - if inst, err := x86.JOC(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JOC(r)) } // JOC: Jump if not overflow (OF == 0). // // Forms: // -// JOC rel8 // JOC rel32 +// JOC rel8 // Construct and append a JOC instruction to the active function. // Operates on the global context. func JOC(r operand.Op) { ctx.JOC(r) } @@ -6316,23 +5353,19 @@ func JOC(r operand.Op) { ctx.JOC(r) } // // Forms: // -// JOS rel8 // JOS rel32 +// JOS rel8 // Construct and append a JOS instruction to the active function. func (c *Context) JOS(r operand.Op) { - if inst, err := x86.JOS(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JOS(r)) } // JOS: Jump if overflow (OF == 1). // // Forms: // -// JOS rel8 // JOS rel32 +// JOS rel8 // Construct and append a JOS instruction to the active function. // Operates on the global context. func JOS(r operand.Op) { ctx.JOS(r) } @@ -6341,23 +5374,19 @@ func JOS(r operand.Op) { ctx.JOS(r) } // // Forms: // -// JP rel8 // JP rel32 +// JP rel8 // Construct and append a JP instruction to the active function. func (c *Context) JP(r operand.Op) { - if inst, err := x86.JP(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JP(r)) } // JP: Jump if parity (PF == 1). // // Forms: // -// JP rel8 // JP rel32 +// JP rel8 // Construct and append a JP instruction to the active function. // Operates on the global context. func JP(r operand.Op) { ctx.JP(r) } @@ -6366,23 +5395,19 @@ func JP(r operand.Op) { ctx.JP(r) } // // Forms: // -// JPC rel8 // JPC rel32 +// JPC rel8 // Construct and append a JPC instruction to the active function. func (c *Context) JPC(r operand.Op) { - if inst, err := x86.JPC(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JPC(r)) } // JPC: Jump if not parity (PF == 0). // // Forms: // -// JPC rel8 // JPC rel32 +// JPC rel8 // Construct and append a JPC instruction to the active function. // Operates on the global context. func JPC(r operand.Op) { ctx.JPC(r) } @@ -6391,23 +5416,19 @@ func JPC(r operand.Op) { ctx.JPC(r) } // // Forms: // -// JPE rel8 // JPE rel32 +// JPE rel8 // Construct and append a JPE instruction to the active function. func (c *Context) JPE(r operand.Op) { - if inst, err := x86.JPE(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JPE(r)) } // JPE: Jump if parity (PF == 1). // // Forms: // -// JPE rel8 // JPE rel32 +// JPE rel8 // Construct and append a JPE instruction to the active function. // Operates on the global context. func JPE(r operand.Op) { ctx.JPE(r) } @@ -6416,23 +5437,19 @@ func JPE(r operand.Op) { ctx.JPE(r) } // // Forms: // -// JPL rel8 // JPL rel32 +// JPL rel8 // Construct and append a JPL instruction to the active function. func (c *Context) JPL(r operand.Op) { - if inst, err := x86.JPL(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JPL(r)) } // JPL: Jump if not sign (SF == 0). // // Forms: // -// JPL rel8 // JPL rel32 +// JPL rel8 // Construct and append a JPL instruction to the active function. // Operates on the global context. func JPL(r operand.Op) { ctx.JPL(r) } @@ -6441,23 +5458,19 @@ func JPL(r operand.Op) { ctx.JPL(r) } // // Forms: // -// JPO rel8 // JPO rel32 +// JPO rel8 // Construct and append a JPO instruction to the active function. func (c *Context) JPO(r operand.Op) { - if inst, err := x86.JPO(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JPO(r)) } // JPO: Jump if not parity (PF == 0). // // Forms: // -// JPO rel8 // JPO rel32 +// JPO rel8 // Construct and append a JPO instruction to the active function. // Operates on the global context. func JPO(r operand.Op) { ctx.JPO(r) } @@ -6466,23 +5479,19 @@ func JPO(r operand.Op) { ctx.JPO(r) } // // Forms: // -// JPS rel8 // JPS rel32 +// JPS rel8 // Construct and append a JPS instruction to the active function. func (c *Context) JPS(r operand.Op) { - if inst, err := x86.JPS(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JPS(r)) } // JPS: Jump if parity (PF == 1). // // Forms: // -// JPS rel8 // JPS rel32 +// JPS rel8 // Construct and append a JPS instruction to the active function. // Operates on the global context. func JPS(r operand.Op) { ctx.JPS(r) } @@ -6491,23 +5500,19 @@ func JPS(r operand.Op) { ctx.JPS(r) } // // Forms: // -// JS rel8 // JS rel32 +// JS rel8 // Construct and append a JS instruction to the active function. func (c *Context) JS(r operand.Op) { - if inst, err := x86.JS(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JS(r)) } // JS: Jump if sign (SF == 1). // // Forms: // -// JS rel8 // JS rel32 +// JS rel8 // Construct and append a JS instruction to the active function. // Operates on the global context. func JS(r operand.Op) { ctx.JS(r) } @@ -6516,19041 +5521,71026 @@ func JS(r operand.Op) { ctx.JS(r) } // // Forms: // -// JZ rel8 // JZ rel32 +// JZ rel8 // Construct and append a JZ instruction to the active function. func (c *Context) JZ(r operand.Op) { - if inst, err := x86.JZ(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.JZ(r)) } // JZ: Jump if equal (ZF == 1). // // Forms: // -// JZ rel8 // JZ rel32 +// JZ rel8 // Construct and append a JZ instruction to the active function. // Operates on the global context. func JZ(r operand.Op) { ctx.JZ(r) } -// LDDQU: Load Unaligned Integer 128 Bits. +// KADDB: ADD Two 8-bit Masks. // // Forms: // -// LDDQU m128 xmm -// Construct and append a LDDQU instruction to the active function. -func (c *Context) LDDQU(m, x operand.Op) { - if inst, err := x86.LDDQU(m, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KADDB k k k +// Construct and append a KADDB instruction to the active function. +func (c *Context) KADDB(k, k1, k2 operand.Op) { + c.addinstruction(x86.KADDB(k, k1, k2)) } -// LDDQU: Load Unaligned Integer 128 Bits. +// KADDB: ADD Two 8-bit Masks. // // Forms: // -// LDDQU m128 xmm -// Construct and append a LDDQU instruction to the active function. +// KADDB k k k +// Construct and append a KADDB instruction to the active function. // Operates on the global context. -func LDDQU(m, x operand.Op) { ctx.LDDQU(m, x) } +func KADDB(k, k1, k2 operand.Op) { ctx.KADDB(k, k1, k2) } -// LDMXCSR: Load MXCSR Register. +// KADDD: ADD Two 32-bit Masks. // // Forms: // -// LDMXCSR m32 -// Construct and append a LDMXCSR instruction to the active function. -func (c *Context) LDMXCSR(m operand.Op) { - if inst, err := x86.LDMXCSR(m); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KADDD k k k +// Construct and append a KADDD instruction to the active function. +func (c *Context) KADDD(k, k1, k2 operand.Op) { + c.addinstruction(x86.KADDD(k, k1, k2)) } -// LDMXCSR: Load MXCSR Register. +// KADDD: ADD Two 32-bit Masks. // // Forms: // -// LDMXCSR m32 -// Construct and append a LDMXCSR instruction to the active function. +// KADDD k k k +// Construct and append a KADDD instruction to the active function. // Operates on the global context. -func LDMXCSR(m operand.Op) { ctx.LDMXCSR(m) } +func KADDD(k, k1, k2 operand.Op) { ctx.KADDD(k, k1, k2) } -// LEAL: Load Effective Address. +// KADDQ: ADD Two 64-bit Masks. // // Forms: // -// LEAL m r32 -// Construct and append a LEAL instruction to the active function. -func (c *Context) LEAL(m, r operand.Op) { - if inst, err := x86.LEAL(m, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KADDQ k k k +// Construct and append a KADDQ instruction to the active function. +func (c *Context) KADDQ(k, k1, k2 operand.Op) { + c.addinstruction(x86.KADDQ(k, k1, k2)) } -// LEAL: Load Effective Address. +// KADDQ: ADD Two 64-bit Masks. // // Forms: // -// LEAL m r32 -// Construct and append a LEAL instruction to the active function. +// KADDQ k k k +// Construct and append a KADDQ instruction to the active function. // Operates on the global context. -func LEAL(m, r operand.Op) { ctx.LEAL(m, r) } +func KADDQ(k, k1, k2 operand.Op) { ctx.KADDQ(k, k1, k2) } -// LEAQ: Load Effective Address. +// KADDW: ADD Two 16-bit Masks. // // Forms: // -// LEAQ m r64 -// Construct and append a LEAQ instruction to the active function. -func (c *Context) LEAQ(m, r operand.Op) { - if inst, err := x86.LEAQ(m, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KADDW k k k +// Construct and append a KADDW instruction to the active function. +func (c *Context) KADDW(k, k1, k2 operand.Op) { + c.addinstruction(x86.KADDW(k, k1, k2)) } -// LEAQ: Load Effective Address. +// KADDW: ADD Two 16-bit Masks. // // Forms: // -// LEAQ m r64 -// Construct and append a LEAQ instruction to the active function. +// KADDW k k k +// Construct and append a KADDW instruction to the active function. // Operates on the global context. -func LEAQ(m, r operand.Op) { ctx.LEAQ(m, r) } +func KADDW(k, k1, k2 operand.Op) { ctx.KADDW(k, k1, k2) } -// LEAW: Load Effective Address. +// KANDB: Bitwise Logical AND 8-bit Masks. // // Forms: // -// LEAW m r16 -// Construct and append a LEAW instruction to the active function. -func (c *Context) LEAW(m, r operand.Op) { - if inst, err := x86.LEAW(m, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KANDB k k k +// Construct and append a KANDB instruction to the active function. +func (c *Context) KANDB(k, k1, k2 operand.Op) { + c.addinstruction(x86.KANDB(k, k1, k2)) } -// LEAW: Load Effective Address. +// KANDB: Bitwise Logical AND 8-bit Masks. // // Forms: // -// LEAW m r16 -// Construct and append a LEAW instruction to the active function. +// KANDB k k k +// Construct and append a KANDB instruction to the active function. // Operates on the global context. -func LEAW(m, r operand.Op) { ctx.LEAW(m, r) } +func KANDB(k, k1, k2 operand.Op) { ctx.KANDB(k, k1, k2) } -// LFENCE: Load Fence. +// KANDD: Bitwise Logical AND 32-bit Masks. // // Forms: // -// LFENCE -// Construct and append a LFENCE instruction to the active function. -func (c *Context) LFENCE() { - if inst, err := x86.LFENCE(); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KANDD k k k +// Construct and append a KANDD instruction to the active function. +func (c *Context) KANDD(k, k1, k2 operand.Op) { + c.addinstruction(x86.KANDD(k, k1, k2)) } -// LFENCE: Load Fence. +// KANDD: Bitwise Logical AND 32-bit Masks. // // Forms: // -// LFENCE -// Construct and append a LFENCE instruction to the active function. +// KANDD k k k +// Construct and append a KANDD instruction to the active function. // Operates on the global context. -func LFENCE() { ctx.LFENCE() } +func KANDD(k, k1, k2 operand.Op) { ctx.KANDD(k, k1, k2) } -// LZCNTL: Count the Number of Leading Zero Bits. +// KANDNB: Bitwise Logical AND NOT 8-bit Masks. // // Forms: // -// LZCNTL r32 r32 -// LZCNTL m32 r32 -// Construct and append a LZCNTL instruction to the active function. -func (c *Context) LZCNTL(mr, r operand.Op) { - if inst, err := x86.LZCNTL(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KANDNB k k k +// Construct and append a KANDNB instruction to the active function. +func (c *Context) KANDNB(k, k1, k2 operand.Op) { + c.addinstruction(x86.KANDNB(k, k1, k2)) } -// LZCNTL: Count the Number of Leading Zero Bits. +// KANDNB: Bitwise Logical AND NOT 8-bit Masks. // // Forms: // -// LZCNTL r32 r32 -// LZCNTL m32 r32 -// Construct and append a LZCNTL instruction to the active function. +// KANDNB k k k +// Construct and append a KANDNB instruction to the active function. // Operates on the global context. -func LZCNTL(mr, r operand.Op) { ctx.LZCNTL(mr, r) } +func KANDNB(k, k1, k2 operand.Op) { ctx.KANDNB(k, k1, k2) } -// LZCNTQ: Count the Number of Leading Zero Bits. +// KANDND: Bitwise Logical AND NOT 32-bit Masks. // // Forms: // -// LZCNTQ r64 r64 -// LZCNTQ m64 r64 -// Construct and append a LZCNTQ instruction to the active function. -func (c *Context) LZCNTQ(mr, r operand.Op) { - if inst, err := x86.LZCNTQ(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KANDND k k k +// Construct and append a KANDND instruction to the active function. +func (c *Context) KANDND(k, k1, k2 operand.Op) { + c.addinstruction(x86.KANDND(k, k1, k2)) } -// LZCNTQ: Count the Number of Leading Zero Bits. +// KANDND: Bitwise Logical AND NOT 32-bit Masks. // // Forms: // -// LZCNTQ r64 r64 -// LZCNTQ m64 r64 -// Construct and append a LZCNTQ instruction to the active function. +// KANDND k k k +// Construct and append a KANDND instruction to the active function. // Operates on the global context. -func LZCNTQ(mr, r operand.Op) { ctx.LZCNTQ(mr, r) } +func KANDND(k, k1, k2 operand.Op) { ctx.KANDND(k, k1, k2) } -// LZCNTW: Count the Number of Leading Zero Bits. +// KANDNQ: Bitwise Logical AND NOT 64-bit Masks. // // Forms: // -// LZCNTW r16 r16 -// LZCNTW m16 r16 -// Construct and append a LZCNTW instruction to the active function. -func (c *Context) LZCNTW(mr, r operand.Op) { - if inst, err := x86.LZCNTW(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KANDNQ k k k +// Construct and append a KANDNQ instruction to the active function. +func (c *Context) KANDNQ(k, k1, k2 operand.Op) { + c.addinstruction(x86.KANDNQ(k, k1, k2)) } -// LZCNTW: Count the Number of Leading Zero Bits. +// KANDNQ: Bitwise Logical AND NOT 64-bit Masks. // // Forms: // -// LZCNTW r16 r16 -// LZCNTW m16 r16 -// Construct and append a LZCNTW instruction to the active function. +// KANDNQ k k k +// Construct and append a KANDNQ instruction to the active function. // Operates on the global context. -func LZCNTW(mr, r operand.Op) { ctx.LZCNTW(mr, r) } +func KANDNQ(k, k1, k2 operand.Op) { ctx.KANDNQ(k, k1, k2) } -// MASKMOVDQU: Store Selected Bytes of Double Quadword. +// KANDNW: Bitwise Logical AND NOT 16-bit Masks. // // Forms: // -// MASKMOVDQU xmm xmm -// Construct and append a MASKMOVDQU instruction to the active function. -func (c *Context) MASKMOVDQU(x, x1 operand.Op) { - if inst, err := x86.MASKMOVDQU(x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KANDNW k k k +// Construct and append a KANDNW instruction to the active function. +func (c *Context) KANDNW(k, k1, k2 operand.Op) { + c.addinstruction(x86.KANDNW(k, k1, k2)) } -// MASKMOVDQU: Store Selected Bytes of Double Quadword. +// KANDNW: Bitwise Logical AND NOT 16-bit Masks. // // Forms: // -// MASKMOVDQU xmm xmm -// Construct and append a MASKMOVDQU instruction to the active function. +// KANDNW k k k +// Construct and append a KANDNW instruction to the active function. // Operates on the global context. -func MASKMOVDQU(x, x1 operand.Op) { ctx.MASKMOVDQU(x, x1) } +func KANDNW(k, k1, k2 operand.Op) { ctx.KANDNW(k, k1, k2) } -// MASKMOVOU: Store Selected Bytes of Double Quadword. +// KANDQ: Bitwise Logical AND 64-bit Masks. // // Forms: // -// MASKMOVOU xmm xmm -// Construct and append a MASKMOVOU instruction to the active function. -func (c *Context) MASKMOVOU(x, x1 operand.Op) { - if inst, err := x86.MASKMOVOU(x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KANDQ k k k +// Construct and append a KANDQ instruction to the active function. +func (c *Context) KANDQ(k, k1, k2 operand.Op) { + c.addinstruction(x86.KANDQ(k, k1, k2)) } -// MASKMOVOU: Store Selected Bytes of Double Quadword. +// KANDQ: Bitwise Logical AND 64-bit Masks. // // Forms: // -// MASKMOVOU xmm xmm -// Construct and append a MASKMOVOU instruction to the active function. +// KANDQ k k k +// Construct and append a KANDQ instruction to the active function. // Operates on the global context. -func MASKMOVOU(x, x1 operand.Op) { ctx.MASKMOVOU(x, x1) } +func KANDQ(k, k1, k2 operand.Op) { ctx.KANDQ(k, k1, k2) } -// MAXPD: Return Maximum Packed Double-Precision Floating-Point Values. +// KANDW: Bitwise Logical AND 16-bit Masks. // // Forms: // -// MAXPD xmm xmm -// MAXPD m128 xmm -// Construct and append a MAXPD instruction to the active function. -func (c *Context) MAXPD(mx, x operand.Op) { - if inst, err := x86.MAXPD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KANDW k k k +// Construct and append a KANDW instruction to the active function. +func (c *Context) KANDW(k, k1, k2 operand.Op) { + c.addinstruction(x86.KANDW(k, k1, k2)) } -// MAXPD: Return Maximum Packed Double-Precision Floating-Point Values. +// KANDW: Bitwise Logical AND 16-bit Masks. // // Forms: // -// MAXPD xmm xmm -// MAXPD m128 xmm -// Construct and append a MAXPD instruction to the active function. +// KANDW k k k +// Construct and append a KANDW instruction to the active function. // Operates on the global context. -func MAXPD(mx, x operand.Op) { ctx.MAXPD(mx, x) } +func KANDW(k, k1, k2 operand.Op) { ctx.KANDW(k, k1, k2) } -// MAXPS: Return Maximum Packed Single-Precision Floating-Point Values. +// KMOVB: Move 8-bit Mask. // // Forms: // -// MAXPS xmm xmm -// MAXPS m128 xmm -// Construct and append a MAXPS instruction to the active function. -func (c *Context) MAXPS(mx, x operand.Op) { - if inst, err := x86.MAXPS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KMOVB k k +// KMOVB k m8 +// KMOVB k r32 +// KMOVB m8 k +// KMOVB r32 k +// Construct and append a KMOVB instruction to the active function. +func (c *Context) KMOVB(kmr, kmr1 operand.Op) { + c.addinstruction(x86.KMOVB(kmr, kmr1)) } -// MAXPS: Return Maximum Packed Single-Precision Floating-Point Values. +// KMOVB: Move 8-bit Mask. // // Forms: // -// MAXPS xmm xmm -// MAXPS m128 xmm -// Construct and append a MAXPS instruction to the active function. +// KMOVB k k +// KMOVB k m8 +// KMOVB k r32 +// KMOVB m8 k +// KMOVB r32 k +// Construct and append a KMOVB instruction to the active function. // Operates on the global context. -func MAXPS(mx, x operand.Op) { ctx.MAXPS(mx, x) } +func KMOVB(kmr, kmr1 operand.Op) { ctx.KMOVB(kmr, kmr1) } -// MAXSD: Return Maximum Scalar Double-Precision Floating-Point Value. +// KMOVD: Move 32-bit Mask. // // Forms: // -// MAXSD xmm xmm -// MAXSD m64 xmm -// Construct and append a MAXSD instruction to the active function. -func (c *Context) MAXSD(mx, x operand.Op) { - if inst, err := x86.MAXSD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KMOVD k k +// KMOVD k m32 +// KMOVD k r32 +// KMOVD m32 k +// KMOVD r32 k +// Construct and append a KMOVD instruction to the active function. +func (c *Context) KMOVD(kmr, kmr1 operand.Op) { + c.addinstruction(x86.KMOVD(kmr, kmr1)) } -// MAXSD: Return Maximum Scalar Double-Precision Floating-Point Value. +// KMOVD: Move 32-bit Mask. // // Forms: // -// MAXSD xmm xmm -// MAXSD m64 xmm -// Construct and append a MAXSD instruction to the active function. +// KMOVD k k +// KMOVD k m32 +// KMOVD k r32 +// KMOVD m32 k +// KMOVD r32 k +// Construct and append a KMOVD instruction to the active function. // Operates on the global context. -func MAXSD(mx, x operand.Op) { ctx.MAXSD(mx, x) } +func KMOVD(kmr, kmr1 operand.Op) { ctx.KMOVD(kmr, kmr1) } -// MAXSS: Return Maximum Scalar Single-Precision Floating-Point Value. +// KMOVQ: Move 64-bit Mask. // // Forms: // -// MAXSS xmm xmm -// MAXSS m32 xmm -// Construct and append a MAXSS instruction to the active function. -func (c *Context) MAXSS(mx, x operand.Op) { - if inst, err := x86.MAXSS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KMOVQ k k +// KMOVQ k m64 +// KMOVQ k r64 +// KMOVQ m64 k +// KMOVQ r64 k +// Construct and append a KMOVQ instruction to the active function. +func (c *Context) KMOVQ(kmr, kmr1 operand.Op) { + c.addinstruction(x86.KMOVQ(kmr, kmr1)) } -// MAXSS: Return Maximum Scalar Single-Precision Floating-Point Value. +// KMOVQ: Move 64-bit Mask. // // Forms: // -// MAXSS xmm xmm -// MAXSS m32 xmm -// Construct and append a MAXSS instruction to the active function. +// KMOVQ k k +// KMOVQ k m64 +// KMOVQ k r64 +// KMOVQ m64 k +// KMOVQ r64 k +// Construct and append a KMOVQ instruction to the active function. // Operates on the global context. -func MAXSS(mx, x operand.Op) { ctx.MAXSS(mx, x) } +func KMOVQ(kmr, kmr1 operand.Op) { ctx.KMOVQ(kmr, kmr1) } -// MFENCE: Memory Fence. +// KMOVW: Move 16-bit Mask. // // Forms: // -// MFENCE -// Construct and append a MFENCE instruction to the active function. -func (c *Context) MFENCE() { - if inst, err := x86.MFENCE(); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KMOVW k k +// KMOVW k m16 +// KMOVW k r32 +// KMOVW m16 k +// KMOVW r32 k +// Construct and append a KMOVW instruction to the active function. +func (c *Context) KMOVW(kmr, kmr1 operand.Op) { + c.addinstruction(x86.KMOVW(kmr, kmr1)) } -// MFENCE: Memory Fence. +// KMOVW: Move 16-bit Mask. // // Forms: // -// MFENCE -// Construct and append a MFENCE instruction to the active function. +// KMOVW k k +// KMOVW k m16 +// KMOVW k r32 +// KMOVW m16 k +// KMOVW r32 k +// Construct and append a KMOVW instruction to the active function. // Operates on the global context. -func MFENCE() { ctx.MFENCE() } +func KMOVW(kmr, kmr1 operand.Op) { ctx.KMOVW(kmr, kmr1) } -// MINPD: Return Minimum Packed Double-Precision Floating-Point Values. +// KNOTB: NOT 8-bit Mask Register. // // Forms: // -// MINPD xmm xmm -// MINPD m128 xmm -// Construct and append a MINPD instruction to the active function. -func (c *Context) MINPD(mx, x operand.Op) { - if inst, err := x86.MINPD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KNOTB k k +// Construct and append a KNOTB instruction to the active function. +func (c *Context) KNOTB(k, k1 operand.Op) { + c.addinstruction(x86.KNOTB(k, k1)) } -// MINPD: Return Minimum Packed Double-Precision Floating-Point Values. +// KNOTB: NOT 8-bit Mask Register. // // Forms: // -// MINPD xmm xmm -// MINPD m128 xmm -// Construct and append a MINPD instruction to the active function. +// KNOTB k k +// Construct and append a KNOTB instruction to the active function. // Operates on the global context. -func MINPD(mx, x operand.Op) { ctx.MINPD(mx, x) } +func KNOTB(k, k1 operand.Op) { ctx.KNOTB(k, k1) } -// MINPS: Return Minimum Packed Single-Precision Floating-Point Values. +// KNOTD: NOT 32-bit Mask Register. // // Forms: // -// MINPS xmm xmm -// MINPS m128 xmm -// Construct and append a MINPS instruction to the active function. -func (c *Context) MINPS(mx, x operand.Op) { - if inst, err := x86.MINPS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KNOTD k k +// Construct and append a KNOTD instruction to the active function. +func (c *Context) KNOTD(k, k1 operand.Op) { + c.addinstruction(x86.KNOTD(k, k1)) } -// MINPS: Return Minimum Packed Single-Precision Floating-Point Values. +// KNOTD: NOT 32-bit Mask Register. // // Forms: // -// MINPS xmm xmm -// MINPS m128 xmm -// Construct and append a MINPS instruction to the active function. +// KNOTD k k +// Construct and append a KNOTD instruction to the active function. // Operates on the global context. -func MINPS(mx, x operand.Op) { ctx.MINPS(mx, x) } +func KNOTD(k, k1 operand.Op) { ctx.KNOTD(k, k1) } -// MINSD: Return Minimum Scalar Double-Precision Floating-Point Value. +// KNOTQ: NOT 64-bit Mask Register. // // Forms: // -// MINSD xmm xmm -// MINSD m64 xmm -// Construct and append a MINSD instruction to the active function. -func (c *Context) MINSD(mx, x operand.Op) { - if inst, err := x86.MINSD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KNOTQ k k +// Construct and append a KNOTQ instruction to the active function. +func (c *Context) KNOTQ(k, k1 operand.Op) { + c.addinstruction(x86.KNOTQ(k, k1)) } -// MINSD: Return Minimum Scalar Double-Precision Floating-Point Value. +// KNOTQ: NOT 64-bit Mask Register. // // Forms: // -// MINSD xmm xmm -// MINSD m64 xmm -// Construct and append a MINSD instruction to the active function. +// KNOTQ k k +// Construct and append a KNOTQ instruction to the active function. // Operates on the global context. -func MINSD(mx, x operand.Op) { ctx.MINSD(mx, x) } +func KNOTQ(k, k1 operand.Op) { ctx.KNOTQ(k, k1) } -// MINSS: Return Minimum Scalar Single-Precision Floating-Point Value. +// KNOTW: NOT 16-bit Mask Register. // // Forms: // -// MINSS xmm xmm -// MINSS m32 xmm -// Construct and append a MINSS instruction to the active function. -func (c *Context) MINSS(mx, x operand.Op) { - if inst, err := x86.MINSS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KNOTW k k +// Construct and append a KNOTW instruction to the active function. +func (c *Context) KNOTW(k, k1 operand.Op) { + c.addinstruction(x86.KNOTW(k, k1)) } -// MINSS: Return Minimum Scalar Single-Precision Floating-Point Value. +// KNOTW: NOT 16-bit Mask Register. // // Forms: // -// MINSS xmm xmm -// MINSS m32 xmm -// Construct and append a MINSS instruction to the active function. +// KNOTW k k +// Construct and append a KNOTW instruction to the active function. // Operates on the global context. -func MINSS(mx, x operand.Op) { ctx.MINSS(mx, x) } +func KNOTW(k, k1 operand.Op) { ctx.KNOTW(k, k1) } -// MONITOR: Monitor a Linear Address Range. +// KORB: Bitwise Logical OR 8-bit Masks. // // Forms: // -// MONITOR -// Construct and append a MONITOR instruction to the active function. -func (c *Context) MONITOR() { - if inst, err := x86.MONITOR(); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KORB k k k +// Construct and append a KORB instruction to the active function. +func (c *Context) KORB(k, k1, k2 operand.Op) { + c.addinstruction(x86.KORB(k, k1, k2)) } -// MONITOR: Monitor a Linear Address Range. +// KORB: Bitwise Logical OR 8-bit Masks. // // Forms: // -// MONITOR -// Construct and append a MONITOR instruction to the active function. +// KORB k k k +// Construct and append a KORB instruction to the active function. // Operates on the global context. -func MONITOR() { ctx.MONITOR() } +func KORB(k, k1, k2 operand.Op) { ctx.KORB(k, k1, k2) } -// MOVAPD: Move Aligned Packed Double-Precision Floating-Point Values. +// KORD: Bitwise Logical OR 32-bit Masks. // // Forms: // -// MOVAPD xmm xmm -// MOVAPD m128 xmm -// MOVAPD xmm m128 -// Construct and append a MOVAPD instruction to the active function. -func (c *Context) MOVAPD(mx, mx1 operand.Op) { - if inst, err := x86.MOVAPD(mx, mx1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KORD k k k +// Construct and append a KORD instruction to the active function. +func (c *Context) KORD(k, k1, k2 operand.Op) { + c.addinstruction(x86.KORD(k, k1, k2)) } -// MOVAPD: Move Aligned Packed Double-Precision Floating-Point Values. +// KORD: Bitwise Logical OR 32-bit Masks. // // Forms: // -// MOVAPD xmm xmm -// MOVAPD m128 xmm -// MOVAPD xmm m128 -// Construct and append a MOVAPD instruction to the active function. +// KORD k k k +// Construct and append a KORD instruction to the active function. // Operates on the global context. -func MOVAPD(mx, mx1 operand.Op) { ctx.MOVAPD(mx, mx1) } +func KORD(k, k1, k2 operand.Op) { ctx.KORD(k, k1, k2) } -// MOVAPS: Move Aligned Packed Single-Precision Floating-Point Values. +// KORQ: Bitwise Logical OR 64-bit Masks. // // Forms: // -// MOVAPS xmm xmm -// MOVAPS m128 xmm -// MOVAPS xmm m128 -// Construct and append a MOVAPS instruction to the active function. -func (c *Context) MOVAPS(mx, mx1 operand.Op) { - if inst, err := x86.MOVAPS(mx, mx1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KORQ k k k +// Construct and append a KORQ instruction to the active function. +func (c *Context) KORQ(k, k1, k2 operand.Op) { + c.addinstruction(x86.KORQ(k, k1, k2)) } -// MOVAPS: Move Aligned Packed Single-Precision Floating-Point Values. +// KORQ: Bitwise Logical OR 64-bit Masks. // // Forms: // -// MOVAPS xmm xmm -// MOVAPS m128 xmm -// MOVAPS xmm m128 -// Construct and append a MOVAPS instruction to the active function. +// KORQ k k k +// Construct and append a KORQ instruction to the active function. // Operates on the global context. -func MOVAPS(mx, mx1 operand.Op) { ctx.MOVAPS(mx, mx1) } +func KORQ(k, k1, k2 operand.Op) { ctx.KORQ(k, k1, k2) } -// MOVB: Move. +// KORTESTB: OR 8-bit Masks and Set Flags. // // Forms: // -// MOVB imm8 r8 -// MOVB r8 r8 -// MOVB m8 r8 -// MOVB imm8 m8 -// MOVB r8 m8 -// Construct and append a MOVB instruction to the active function. -func (c *Context) MOVB(imr, mr operand.Op) { - if inst, err := x86.MOVB(imr, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KORTESTB k k +// Construct and append a KORTESTB instruction to the active function. +func (c *Context) KORTESTB(k, k1 operand.Op) { + c.addinstruction(x86.KORTESTB(k, k1)) } -// MOVB: Move. +// KORTESTB: OR 8-bit Masks and Set Flags. // // Forms: // -// MOVB imm8 r8 -// MOVB r8 r8 -// MOVB m8 r8 -// MOVB imm8 m8 -// MOVB r8 m8 -// Construct and append a MOVB instruction to the active function. +// KORTESTB k k +// Construct and append a KORTESTB instruction to the active function. // Operates on the global context. -func MOVB(imr, mr operand.Op) { ctx.MOVB(imr, mr) } +func KORTESTB(k, k1 operand.Op) { ctx.KORTESTB(k, k1) } -// MOVBELL: Move Data After Swapping Bytes. +// KORTESTD: OR 32-bit Masks and Set Flags. // // Forms: // -// MOVBELL m32 r32 -// MOVBELL r32 m32 -// Construct and append a MOVBELL instruction to the active function. -func (c *Context) MOVBELL(mr, mr1 operand.Op) { - if inst, err := x86.MOVBELL(mr, mr1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KORTESTD k k +// Construct and append a KORTESTD instruction to the active function. +func (c *Context) KORTESTD(k, k1 operand.Op) { + c.addinstruction(x86.KORTESTD(k, k1)) } -// MOVBELL: Move Data After Swapping Bytes. +// KORTESTD: OR 32-bit Masks and Set Flags. // // Forms: // -// MOVBELL m32 r32 -// MOVBELL r32 m32 -// Construct and append a MOVBELL instruction to the active function. +// KORTESTD k k +// Construct and append a KORTESTD instruction to the active function. // Operates on the global context. -func MOVBELL(mr, mr1 operand.Op) { ctx.MOVBELL(mr, mr1) } +func KORTESTD(k, k1 operand.Op) { ctx.KORTESTD(k, k1) } -// MOVBEQQ: Move Data After Swapping Bytes. +// KORTESTQ: OR 64-bit Masks and Set Flags. // // Forms: // -// MOVBEQQ m64 r64 -// MOVBEQQ r64 m64 -// Construct and append a MOVBEQQ instruction to the active function. -func (c *Context) MOVBEQQ(mr, mr1 operand.Op) { - if inst, err := x86.MOVBEQQ(mr, mr1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KORTESTQ k k +// Construct and append a KORTESTQ instruction to the active function. +func (c *Context) KORTESTQ(k, k1 operand.Op) { + c.addinstruction(x86.KORTESTQ(k, k1)) } -// MOVBEQQ: Move Data After Swapping Bytes. +// KORTESTQ: OR 64-bit Masks and Set Flags. // // Forms: // -// MOVBEQQ m64 r64 -// MOVBEQQ r64 m64 -// Construct and append a MOVBEQQ instruction to the active function. +// KORTESTQ k k +// Construct and append a KORTESTQ instruction to the active function. // Operates on the global context. -func MOVBEQQ(mr, mr1 operand.Op) { ctx.MOVBEQQ(mr, mr1) } +func KORTESTQ(k, k1 operand.Op) { ctx.KORTESTQ(k, k1) } -// MOVBEWW: Move Data After Swapping Bytes. +// KORTESTW: OR 16-bit Masks and Set Flags. // // Forms: // -// MOVBEWW m16 r16 -// MOVBEWW r16 m16 -// Construct and append a MOVBEWW instruction to the active function. -func (c *Context) MOVBEWW(mr, mr1 operand.Op) { - if inst, err := x86.MOVBEWW(mr, mr1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KORTESTW k k +// Construct and append a KORTESTW instruction to the active function. +func (c *Context) KORTESTW(k, k1 operand.Op) { + c.addinstruction(x86.KORTESTW(k, k1)) } -// MOVBEWW: Move Data After Swapping Bytes. +// KORTESTW: OR 16-bit Masks and Set Flags. // // Forms: // -// MOVBEWW m16 r16 -// MOVBEWW r16 m16 -// Construct and append a MOVBEWW instruction to the active function. +// KORTESTW k k +// Construct and append a KORTESTW instruction to the active function. // Operates on the global context. -func MOVBEWW(mr, mr1 operand.Op) { ctx.MOVBEWW(mr, mr1) } +func KORTESTW(k, k1 operand.Op) { ctx.KORTESTW(k, k1) } -// MOVBLSX: Move with Sign-Extension. +// KORW: Bitwise Logical OR 16-bit Masks. // // Forms: // -// MOVBLSX r8 r32 -// MOVBLSX m8 r32 -// Construct and append a MOVBLSX instruction to the active function. -func (c *Context) MOVBLSX(mr, r operand.Op) { - if inst, err := x86.MOVBLSX(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KORW k k k +// Construct and append a KORW instruction to the active function. +func (c *Context) KORW(k, k1, k2 operand.Op) { + c.addinstruction(x86.KORW(k, k1, k2)) } -// MOVBLSX: Move with Sign-Extension. +// KORW: Bitwise Logical OR 16-bit Masks. // // Forms: // -// MOVBLSX r8 r32 -// MOVBLSX m8 r32 -// Construct and append a MOVBLSX instruction to the active function. +// KORW k k k +// Construct and append a KORW instruction to the active function. // Operates on the global context. -func MOVBLSX(mr, r operand.Op) { ctx.MOVBLSX(mr, r) } +func KORW(k, k1, k2 operand.Op) { ctx.KORW(k, k1, k2) } -// MOVBLZX: Move with Zero-Extend. +// KSHIFTLB: Shift Left 8-bit Masks. // // Forms: // -// MOVBLZX r8 r32 -// MOVBLZX m8 r32 -// Construct and append a MOVBLZX instruction to the active function. -func (c *Context) MOVBLZX(mr, r operand.Op) { - if inst, err := x86.MOVBLZX(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KSHIFTLB imm8 k k +// Construct and append a KSHIFTLB instruction to the active function. +func (c *Context) KSHIFTLB(i, k, k1 operand.Op) { + c.addinstruction(x86.KSHIFTLB(i, k, k1)) } -// MOVBLZX: Move with Zero-Extend. +// KSHIFTLB: Shift Left 8-bit Masks. // // Forms: // -// MOVBLZX r8 r32 -// MOVBLZX m8 r32 -// Construct and append a MOVBLZX instruction to the active function. +// KSHIFTLB imm8 k k +// Construct and append a KSHIFTLB instruction to the active function. // Operates on the global context. -func MOVBLZX(mr, r operand.Op) { ctx.MOVBLZX(mr, r) } +func KSHIFTLB(i, k, k1 operand.Op) { ctx.KSHIFTLB(i, k, k1) } -// MOVBQSX: Move with Sign-Extension. +// KSHIFTLD: Shift Left 32-bit Masks. // // Forms: // -// MOVBQSX r8 r64 -// MOVBQSX m8 r64 -// Construct and append a MOVBQSX instruction to the active function. -func (c *Context) MOVBQSX(mr, r operand.Op) { - if inst, err := x86.MOVBQSX(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KSHIFTLD imm8 k k +// Construct and append a KSHIFTLD instruction to the active function. +func (c *Context) KSHIFTLD(i, k, k1 operand.Op) { + c.addinstruction(x86.KSHIFTLD(i, k, k1)) } -// MOVBQSX: Move with Sign-Extension. +// KSHIFTLD: Shift Left 32-bit Masks. // // Forms: // -// MOVBQSX r8 r64 -// MOVBQSX m8 r64 -// Construct and append a MOVBQSX instruction to the active function. +// KSHIFTLD imm8 k k +// Construct and append a KSHIFTLD instruction to the active function. // Operates on the global context. -func MOVBQSX(mr, r operand.Op) { ctx.MOVBQSX(mr, r) } +func KSHIFTLD(i, k, k1 operand.Op) { ctx.KSHIFTLD(i, k, k1) } -// MOVBQZX: Move with Zero-Extend. +// KSHIFTLQ: Shift Left 64-bit Masks. // // Forms: // -// MOVBQZX r8 r64 -// MOVBQZX m8 r64 -// Construct and append a MOVBQZX instruction to the active function. -func (c *Context) MOVBQZX(mr, r operand.Op) { - if inst, err := x86.MOVBQZX(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KSHIFTLQ imm8 k k +// Construct and append a KSHIFTLQ instruction to the active function. +func (c *Context) KSHIFTLQ(i, k, k1 operand.Op) { + c.addinstruction(x86.KSHIFTLQ(i, k, k1)) } -// MOVBQZX: Move with Zero-Extend. +// KSHIFTLQ: Shift Left 64-bit Masks. // // Forms: // -// MOVBQZX r8 r64 -// MOVBQZX m8 r64 -// Construct and append a MOVBQZX instruction to the active function. +// KSHIFTLQ imm8 k k +// Construct and append a KSHIFTLQ instruction to the active function. // Operates on the global context. -func MOVBQZX(mr, r operand.Op) { ctx.MOVBQZX(mr, r) } +func KSHIFTLQ(i, k, k1 operand.Op) { ctx.KSHIFTLQ(i, k, k1) } -// MOVBWSX: Move with Sign-Extension. +// KSHIFTLW: Shift Left 16-bit Masks. // // Forms: // -// MOVBWSX r8 r16 -// MOVBWSX m8 r16 -// Construct and append a MOVBWSX instruction to the active function. -func (c *Context) MOVBWSX(mr, r operand.Op) { - if inst, err := x86.MOVBWSX(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KSHIFTLW imm8 k k +// Construct and append a KSHIFTLW instruction to the active function. +func (c *Context) KSHIFTLW(i, k, k1 operand.Op) { + c.addinstruction(x86.KSHIFTLW(i, k, k1)) } -// MOVBWSX: Move with Sign-Extension. +// KSHIFTLW: Shift Left 16-bit Masks. // // Forms: // -// MOVBWSX r8 r16 -// MOVBWSX m8 r16 -// Construct and append a MOVBWSX instruction to the active function. +// KSHIFTLW imm8 k k +// Construct and append a KSHIFTLW instruction to the active function. // Operates on the global context. -func MOVBWSX(mr, r operand.Op) { ctx.MOVBWSX(mr, r) } +func KSHIFTLW(i, k, k1 operand.Op) { ctx.KSHIFTLW(i, k, k1) } -// MOVBWZX: Move with Zero-Extend. +// KSHIFTRB: Shift Right 8-bit Masks. // // Forms: // -// MOVBWZX r8 r16 -// MOVBWZX m8 r16 -// Construct and append a MOVBWZX instruction to the active function. -func (c *Context) MOVBWZX(mr, r operand.Op) { - if inst, err := x86.MOVBWZX(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KSHIFTRB imm8 k k +// Construct and append a KSHIFTRB instruction to the active function. +func (c *Context) KSHIFTRB(i, k, k1 operand.Op) { + c.addinstruction(x86.KSHIFTRB(i, k, k1)) } -// MOVBWZX: Move with Zero-Extend. +// KSHIFTRB: Shift Right 8-bit Masks. // // Forms: // -// MOVBWZX r8 r16 -// MOVBWZX m8 r16 -// Construct and append a MOVBWZX instruction to the active function. +// KSHIFTRB imm8 k k +// Construct and append a KSHIFTRB instruction to the active function. // Operates on the global context. -func MOVBWZX(mr, r operand.Op) { ctx.MOVBWZX(mr, r) } +func KSHIFTRB(i, k, k1 operand.Op) { ctx.KSHIFTRB(i, k, k1) } -// MOVD: Move. +// KSHIFTRD: Shift Right 32-bit Masks. // // Forms: // -// MOVD imm32 r64 -// MOVD imm64 r64 -// MOVD r64 r64 -// MOVD m64 r64 -// MOVD imm32 m64 -// MOVD r64 m64 -// MOVD xmm r64 -// MOVD r64 xmm -// MOVD xmm xmm -// MOVD m64 xmm -// MOVD xmm m64 -// MOVD xmm r32 -// MOVD r32 xmm -// MOVD m32 xmm -// MOVD xmm m32 -// Construct and append a MOVD instruction to the active function. -func (c *Context) MOVD(imrx, mrx operand.Op) { - if inst, err := x86.MOVD(imrx, mrx); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KSHIFTRD imm8 k k +// Construct and append a KSHIFTRD instruction to the active function. +func (c *Context) KSHIFTRD(i, k, k1 operand.Op) { + c.addinstruction(x86.KSHIFTRD(i, k, k1)) } -// MOVD: Move. +// KSHIFTRD: Shift Right 32-bit Masks. // // Forms: // -// MOVD imm32 r64 -// MOVD imm64 r64 -// MOVD r64 r64 -// MOVD m64 r64 -// MOVD imm32 m64 -// MOVD r64 m64 -// MOVD xmm r64 -// MOVD r64 xmm -// MOVD xmm xmm -// MOVD m64 xmm -// MOVD xmm m64 -// MOVD xmm r32 -// MOVD r32 xmm -// MOVD m32 xmm -// MOVD xmm m32 -// Construct and append a MOVD instruction to the active function. +// KSHIFTRD imm8 k k +// Construct and append a KSHIFTRD instruction to the active function. // Operates on the global context. -func MOVD(imrx, mrx operand.Op) { ctx.MOVD(imrx, mrx) } +func KSHIFTRD(i, k, k1 operand.Op) { ctx.KSHIFTRD(i, k, k1) } -// MOVDDUP: Move One Double-FP and Duplicate. +// KSHIFTRQ: Shift Right 64-bit Masks. // // Forms: // -// MOVDDUP xmm xmm -// MOVDDUP m64 xmm -// Construct and append a MOVDDUP instruction to the active function. -func (c *Context) MOVDDUP(mx, x operand.Op) { - if inst, err := x86.MOVDDUP(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KSHIFTRQ imm8 k k +// Construct and append a KSHIFTRQ instruction to the active function. +func (c *Context) KSHIFTRQ(i, k, k1 operand.Op) { + c.addinstruction(x86.KSHIFTRQ(i, k, k1)) } -// MOVDDUP: Move One Double-FP and Duplicate. +// KSHIFTRQ: Shift Right 64-bit Masks. // // Forms: // -// MOVDDUP xmm xmm -// MOVDDUP m64 xmm -// Construct and append a MOVDDUP instruction to the active function. +// KSHIFTRQ imm8 k k +// Construct and append a KSHIFTRQ instruction to the active function. // Operates on the global context. -func MOVDDUP(mx, x operand.Op) { ctx.MOVDDUP(mx, x) } +func KSHIFTRQ(i, k, k1 operand.Op) { ctx.KSHIFTRQ(i, k, k1) } -// MOVDQ2Q: Move. +// KSHIFTRW: Shift Right 16-bit Masks. // // Forms: // -// MOVDQ2Q imm32 r64 -// MOVDQ2Q imm64 r64 -// MOVDQ2Q r64 r64 -// MOVDQ2Q m64 r64 -// MOVDQ2Q imm32 m64 -// MOVDQ2Q r64 m64 -// MOVDQ2Q xmm r64 -// MOVDQ2Q r64 xmm -// MOVDQ2Q xmm xmm -// MOVDQ2Q m64 xmm -// MOVDQ2Q xmm m64 -// MOVDQ2Q xmm r32 -// MOVDQ2Q r32 xmm -// MOVDQ2Q m32 xmm -// MOVDQ2Q xmm m32 -// Construct and append a MOVDQ2Q instruction to the active function. -func (c *Context) MOVDQ2Q(imrx, mrx operand.Op) { - if inst, err := x86.MOVDQ2Q(imrx, mrx); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KSHIFTRW imm8 k k +// Construct and append a KSHIFTRW instruction to the active function. +func (c *Context) KSHIFTRW(i, k, k1 operand.Op) { + c.addinstruction(x86.KSHIFTRW(i, k, k1)) } -// MOVDQ2Q: Move. +// KSHIFTRW: Shift Right 16-bit Masks. // // Forms: // -// MOVDQ2Q imm32 r64 -// MOVDQ2Q imm64 r64 -// MOVDQ2Q r64 r64 -// MOVDQ2Q m64 r64 -// MOVDQ2Q imm32 m64 -// MOVDQ2Q r64 m64 -// MOVDQ2Q xmm r64 -// MOVDQ2Q r64 xmm -// MOVDQ2Q xmm xmm -// MOVDQ2Q m64 xmm -// MOVDQ2Q xmm m64 -// MOVDQ2Q xmm r32 -// MOVDQ2Q r32 xmm -// MOVDQ2Q m32 xmm -// MOVDQ2Q xmm m32 -// Construct and append a MOVDQ2Q instruction to the active function. +// KSHIFTRW imm8 k k +// Construct and append a KSHIFTRW instruction to the active function. // Operates on the global context. -func MOVDQ2Q(imrx, mrx operand.Op) { ctx.MOVDQ2Q(imrx, mrx) } +func KSHIFTRW(i, k, k1 operand.Op) { ctx.KSHIFTRW(i, k, k1) } -// MOVHLPS: Move Packed Single-Precision Floating-Point Values High to Low. +// KTESTB: Bit Test 8-bit Masks and Set Flags. // // Forms: // -// MOVHLPS xmm xmm -// Construct and append a MOVHLPS instruction to the active function. -func (c *Context) MOVHLPS(x, x1 operand.Op) { - if inst, err := x86.MOVHLPS(x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KTESTB k k +// Construct and append a KTESTB instruction to the active function. +func (c *Context) KTESTB(k, k1 operand.Op) { + c.addinstruction(x86.KTESTB(k, k1)) } -// MOVHLPS: Move Packed Single-Precision Floating-Point Values High to Low. +// KTESTB: Bit Test 8-bit Masks and Set Flags. // // Forms: // -// MOVHLPS xmm xmm -// Construct and append a MOVHLPS instruction to the active function. +// KTESTB k k +// Construct and append a KTESTB instruction to the active function. // Operates on the global context. -func MOVHLPS(x, x1 operand.Op) { ctx.MOVHLPS(x, x1) } +func KTESTB(k, k1 operand.Op) { ctx.KTESTB(k, k1) } -// MOVHPD: Move High Packed Double-Precision Floating-Point Value. +// KTESTD: Bit Test 32-bit Masks and Set Flags. // // Forms: // -// MOVHPD m64 xmm -// MOVHPD xmm m64 -// Construct and append a MOVHPD instruction to the active function. -func (c *Context) MOVHPD(mx, mx1 operand.Op) { - if inst, err := x86.MOVHPD(mx, mx1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KTESTD k k +// Construct and append a KTESTD instruction to the active function. +func (c *Context) KTESTD(k, k1 operand.Op) { + c.addinstruction(x86.KTESTD(k, k1)) } -// MOVHPD: Move High Packed Double-Precision Floating-Point Value. +// KTESTD: Bit Test 32-bit Masks and Set Flags. // // Forms: // -// MOVHPD m64 xmm -// MOVHPD xmm m64 -// Construct and append a MOVHPD instruction to the active function. +// KTESTD k k +// Construct and append a KTESTD instruction to the active function. // Operates on the global context. -func MOVHPD(mx, mx1 operand.Op) { ctx.MOVHPD(mx, mx1) } +func KTESTD(k, k1 operand.Op) { ctx.KTESTD(k, k1) } -// MOVHPS: Move High Packed Single-Precision Floating-Point Values. +// KTESTQ: Bit Test 64-bit Masks and Set Flags. // // Forms: // -// MOVHPS m64 xmm -// MOVHPS xmm m64 -// Construct and append a MOVHPS instruction to the active function. -func (c *Context) MOVHPS(mx, mx1 operand.Op) { - if inst, err := x86.MOVHPS(mx, mx1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KTESTQ k k +// Construct and append a KTESTQ instruction to the active function. +func (c *Context) KTESTQ(k, k1 operand.Op) { + c.addinstruction(x86.KTESTQ(k, k1)) } -// MOVHPS: Move High Packed Single-Precision Floating-Point Values. +// KTESTQ: Bit Test 64-bit Masks and Set Flags. // // Forms: // -// MOVHPS m64 xmm -// MOVHPS xmm m64 -// Construct and append a MOVHPS instruction to the active function. +// KTESTQ k k +// Construct and append a KTESTQ instruction to the active function. // Operates on the global context. -func MOVHPS(mx, mx1 operand.Op) { ctx.MOVHPS(mx, mx1) } +func KTESTQ(k, k1 operand.Op) { ctx.KTESTQ(k, k1) } -// MOVL: Move. +// KTESTW: Bit Test 16-bit Masks and Set Flags. // // Forms: // -// MOVL imm32 r32 -// MOVL r32 r32 -// MOVL m32 r32 -// MOVL imm32 m32 -// MOVL r32 m32 -// Construct and append a MOVL instruction to the active function. -func (c *Context) MOVL(imr, mr operand.Op) { - if inst, err := x86.MOVL(imr, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KTESTW k k +// Construct and append a KTESTW instruction to the active function. +func (c *Context) KTESTW(k, k1 operand.Op) { + c.addinstruction(x86.KTESTW(k, k1)) } -// MOVL: Move. +// KTESTW: Bit Test 16-bit Masks and Set Flags. // // Forms: // -// MOVL imm32 r32 -// MOVL r32 r32 -// MOVL m32 r32 -// MOVL imm32 m32 -// MOVL r32 m32 -// Construct and append a MOVL instruction to the active function. +// KTESTW k k +// Construct and append a KTESTW instruction to the active function. // Operates on the global context. -func MOVL(imr, mr operand.Op) { ctx.MOVL(imr, mr) } +func KTESTW(k, k1 operand.Op) { ctx.KTESTW(k, k1) } -// MOVLHPS: Move Packed Single-Precision Floating-Point Values Low to High. +// KUNPCKBW: Unpack and Interleave 8-bit Masks. // // Forms: // -// MOVLHPS xmm xmm -// Construct and append a MOVLHPS instruction to the active function. -func (c *Context) MOVLHPS(x, x1 operand.Op) { - if inst, err := x86.MOVLHPS(x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KUNPCKBW k k k +// Construct and append a KUNPCKBW instruction to the active function. +func (c *Context) KUNPCKBW(k, k1, k2 operand.Op) { + c.addinstruction(x86.KUNPCKBW(k, k1, k2)) } -// MOVLHPS: Move Packed Single-Precision Floating-Point Values Low to High. +// KUNPCKBW: Unpack and Interleave 8-bit Masks. // // Forms: // -// MOVLHPS xmm xmm -// Construct and append a MOVLHPS instruction to the active function. +// KUNPCKBW k k k +// Construct and append a KUNPCKBW instruction to the active function. // Operates on the global context. -func MOVLHPS(x, x1 operand.Op) { ctx.MOVLHPS(x, x1) } +func KUNPCKBW(k, k1, k2 operand.Op) { ctx.KUNPCKBW(k, k1, k2) } -// MOVLPD: Move Low Packed Double-Precision Floating-Point Value. +// KUNPCKDQ: Unpack and Interleave 32-bit Masks. // // Forms: // -// MOVLPD m64 xmm -// MOVLPD xmm m64 -// Construct and append a MOVLPD instruction to the active function. -func (c *Context) MOVLPD(mx, mx1 operand.Op) { - if inst, err := x86.MOVLPD(mx, mx1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KUNPCKDQ k k k +// Construct and append a KUNPCKDQ instruction to the active function. +func (c *Context) KUNPCKDQ(k, k1, k2 operand.Op) { + c.addinstruction(x86.KUNPCKDQ(k, k1, k2)) } -// MOVLPD: Move Low Packed Double-Precision Floating-Point Value. +// KUNPCKDQ: Unpack and Interleave 32-bit Masks. // // Forms: // -// MOVLPD m64 xmm -// MOVLPD xmm m64 -// Construct and append a MOVLPD instruction to the active function. +// KUNPCKDQ k k k +// Construct and append a KUNPCKDQ instruction to the active function. // Operates on the global context. -func MOVLPD(mx, mx1 operand.Op) { ctx.MOVLPD(mx, mx1) } +func KUNPCKDQ(k, k1, k2 operand.Op) { ctx.KUNPCKDQ(k, k1, k2) } -// MOVLPS: Move Low Packed Single-Precision Floating-Point Values. +// KUNPCKWD: Unpack and Interleave 16-bit Masks. // // Forms: // -// MOVLPS m64 xmm -// MOVLPS xmm m64 -// Construct and append a MOVLPS instruction to the active function. -func (c *Context) MOVLPS(mx, mx1 operand.Op) { - if inst, err := x86.MOVLPS(mx, mx1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KUNPCKWD k k k +// Construct and append a KUNPCKWD instruction to the active function. +func (c *Context) KUNPCKWD(k, k1, k2 operand.Op) { + c.addinstruction(x86.KUNPCKWD(k, k1, k2)) } -// MOVLPS: Move Low Packed Single-Precision Floating-Point Values. +// KUNPCKWD: Unpack and Interleave 16-bit Masks. // // Forms: // -// MOVLPS m64 xmm -// MOVLPS xmm m64 -// Construct and append a MOVLPS instruction to the active function. +// KUNPCKWD k k k +// Construct and append a KUNPCKWD instruction to the active function. // Operates on the global context. -func MOVLPS(mx, mx1 operand.Op) { ctx.MOVLPS(mx, mx1) } +func KUNPCKWD(k, k1, k2 operand.Op) { ctx.KUNPCKWD(k, k1, k2) } -// MOVLQSX: Move Doubleword to Quadword with Sign-Extension. +// KXNORB: Bitwise Logical XNOR 8-bit Masks. // // Forms: // -// MOVLQSX r32 r64 -// MOVLQSX m32 r64 -// Construct and append a MOVLQSX instruction to the active function. -func (c *Context) MOVLQSX(mr, r operand.Op) { - if inst, err := x86.MOVLQSX(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KXNORB k k k +// Construct and append a KXNORB instruction to the active function. +func (c *Context) KXNORB(k, k1, k2 operand.Op) { + c.addinstruction(x86.KXNORB(k, k1, k2)) } -// MOVLQSX: Move Doubleword to Quadword with Sign-Extension. +// KXNORB: Bitwise Logical XNOR 8-bit Masks. // // Forms: // -// MOVLQSX r32 r64 -// MOVLQSX m32 r64 -// Construct and append a MOVLQSX instruction to the active function. +// KXNORB k k k +// Construct and append a KXNORB instruction to the active function. // Operates on the global context. -func MOVLQSX(mr, r operand.Op) { ctx.MOVLQSX(mr, r) } +func KXNORB(k, k1, k2 operand.Op) { ctx.KXNORB(k, k1, k2) } -// MOVLQZX: Move with Zero-Extend. +// KXNORD: Bitwise Logical XNOR 32-bit Masks. // // Forms: // -// MOVLQZX m32 r64 -// Construct and append a MOVLQZX instruction to the active function. -func (c *Context) MOVLQZX(m, r operand.Op) { - if inst, err := x86.MOVLQZX(m, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KXNORD k k k +// Construct and append a KXNORD instruction to the active function. +func (c *Context) KXNORD(k, k1, k2 operand.Op) { + c.addinstruction(x86.KXNORD(k, k1, k2)) } -// MOVLQZX: Move with Zero-Extend. +// KXNORD: Bitwise Logical XNOR 32-bit Masks. // // Forms: // -// MOVLQZX m32 r64 -// Construct and append a MOVLQZX instruction to the active function. +// KXNORD k k k +// Construct and append a KXNORD instruction to the active function. // Operates on the global context. -func MOVLQZX(m, r operand.Op) { ctx.MOVLQZX(m, r) } +func KXNORD(k, k1, k2 operand.Op) { ctx.KXNORD(k, k1, k2) } -// MOVMSKPD: Extract Packed Double-Precision Floating-Point Sign Mask. +// KXNORQ: Bitwise Logical XNOR 64-bit Masks. // // Forms: // -// MOVMSKPD xmm r32 -// Construct and append a MOVMSKPD instruction to the active function. -func (c *Context) MOVMSKPD(x, r operand.Op) { - if inst, err := x86.MOVMSKPD(x, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KXNORQ k k k +// Construct and append a KXNORQ instruction to the active function. +func (c *Context) KXNORQ(k, k1, k2 operand.Op) { + c.addinstruction(x86.KXNORQ(k, k1, k2)) } -// MOVMSKPD: Extract Packed Double-Precision Floating-Point Sign Mask. +// KXNORQ: Bitwise Logical XNOR 64-bit Masks. // // Forms: // -// MOVMSKPD xmm r32 -// Construct and append a MOVMSKPD instruction to the active function. +// KXNORQ k k k +// Construct and append a KXNORQ instruction to the active function. // Operates on the global context. -func MOVMSKPD(x, r operand.Op) { ctx.MOVMSKPD(x, r) } +func KXNORQ(k, k1, k2 operand.Op) { ctx.KXNORQ(k, k1, k2) } -// MOVMSKPS: Extract Packed Single-Precision Floating-Point Sign Mask. +// KXNORW: Bitwise Logical XNOR 16-bit Masks. // // Forms: // -// MOVMSKPS xmm r32 -// Construct and append a MOVMSKPS instruction to the active function. -func (c *Context) MOVMSKPS(x, r operand.Op) { - if inst, err := x86.MOVMSKPS(x, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KXNORW k k k +// Construct and append a KXNORW instruction to the active function. +func (c *Context) KXNORW(k, k1, k2 operand.Op) { + c.addinstruction(x86.KXNORW(k, k1, k2)) } -// MOVMSKPS: Extract Packed Single-Precision Floating-Point Sign Mask. +// KXNORW: Bitwise Logical XNOR 16-bit Masks. // // Forms: // -// MOVMSKPS xmm r32 -// Construct and append a MOVMSKPS instruction to the active function. +// KXNORW k k k +// Construct and append a KXNORW instruction to the active function. // Operates on the global context. -func MOVMSKPS(x, r operand.Op) { ctx.MOVMSKPS(x, r) } +func KXNORW(k, k1, k2 operand.Op) { ctx.KXNORW(k, k1, k2) } -// MOVNTDQ: Store Double Quadword Using Non-Temporal Hint. +// KXORB: Bitwise Logical XOR 8-bit Masks. // // Forms: // -// MOVNTDQ xmm m128 -// Construct and append a MOVNTDQ instruction to the active function. -func (c *Context) MOVNTDQ(x, m operand.Op) { - if inst, err := x86.MOVNTDQ(x, m); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KXORB k k k +// Construct and append a KXORB instruction to the active function. +func (c *Context) KXORB(k, k1, k2 operand.Op) { + c.addinstruction(x86.KXORB(k, k1, k2)) } -// MOVNTDQ: Store Double Quadword Using Non-Temporal Hint. +// KXORB: Bitwise Logical XOR 8-bit Masks. // // Forms: // -// MOVNTDQ xmm m128 -// Construct and append a MOVNTDQ instruction to the active function. +// KXORB k k k +// Construct and append a KXORB instruction to the active function. // Operates on the global context. -func MOVNTDQ(x, m operand.Op) { ctx.MOVNTDQ(x, m) } +func KXORB(k, k1, k2 operand.Op) { ctx.KXORB(k, k1, k2) } -// MOVNTDQA: Load Double Quadword Non-Temporal Aligned Hint. +// KXORD: Bitwise Logical XOR 32-bit Masks. // // Forms: // -// MOVNTDQA m128 xmm -// Construct and append a MOVNTDQA instruction to the active function. -func (c *Context) MOVNTDQA(m, x operand.Op) { - if inst, err := x86.MOVNTDQA(m, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KXORD k k k +// Construct and append a KXORD instruction to the active function. +func (c *Context) KXORD(k, k1, k2 operand.Op) { + c.addinstruction(x86.KXORD(k, k1, k2)) } -// MOVNTDQA: Load Double Quadword Non-Temporal Aligned Hint. +// KXORD: Bitwise Logical XOR 32-bit Masks. // // Forms: // -// MOVNTDQA m128 xmm -// Construct and append a MOVNTDQA instruction to the active function. +// KXORD k k k +// Construct and append a KXORD instruction to the active function. // Operates on the global context. -func MOVNTDQA(m, x operand.Op) { ctx.MOVNTDQA(m, x) } +func KXORD(k, k1, k2 operand.Op) { ctx.KXORD(k, k1, k2) } -// MOVNTIL: Store Doubleword Using Non-Temporal Hint. +// KXORQ: Bitwise Logical XOR 64-bit Masks. // // Forms: // -// MOVNTIL r32 m32 -// Construct and append a MOVNTIL instruction to the active function. -func (c *Context) MOVNTIL(r, m operand.Op) { - if inst, err := x86.MOVNTIL(r, m); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KXORQ k k k +// Construct and append a KXORQ instruction to the active function. +func (c *Context) KXORQ(k, k1, k2 operand.Op) { + c.addinstruction(x86.KXORQ(k, k1, k2)) } -// MOVNTIL: Store Doubleword Using Non-Temporal Hint. +// KXORQ: Bitwise Logical XOR 64-bit Masks. // // Forms: // -// MOVNTIL r32 m32 -// Construct and append a MOVNTIL instruction to the active function. +// KXORQ k k k +// Construct and append a KXORQ instruction to the active function. // Operates on the global context. -func MOVNTIL(r, m operand.Op) { ctx.MOVNTIL(r, m) } +func KXORQ(k, k1, k2 operand.Op) { ctx.KXORQ(k, k1, k2) } -// MOVNTIQ: Store Doubleword Using Non-Temporal Hint. +// KXORW: Bitwise Logical XOR 16-bit Masks. // // Forms: // -// MOVNTIQ r64 m64 -// Construct and append a MOVNTIQ instruction to the active function. -func (c *Context) MOVNTIQ(r, m operand.Op) { - if inst, err := x86.MOVNTIQ(r, m); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// KXORW k k k +// Construct and append a KXORW instruction to the active function. +func (c *Context) KXORW(k, k1, k2 operand.Op) { + c.addinstruction(x86.KXORW(k, k1, k2)) } -// MOVNTIQ: Store Doubleword Using Non-Temporal Hint. +// KXORW: Bitwise Logical XOR 16-bit Masks. // // Forms: // -// MOVNTIQ r64 m64 -// Construct and append a MOVNTIQ instruction to the active function. +// KXORW k k k +// Construct and append a KXORW instruction to the active function. // Operates on the global context. -func MOVNTIQ(r, m operand.Op) { ctx.MOVNTIQ(r, m) } +func KXORW(k, k1, k2 operand.Op) { ctx.KXORW(k, k1, k2) } -// MOVNTO: Store Double Quadword Using Non-Temporal Hint. +// LDDQU: Load Unaligned Integer 128 Bits. // // Forms: // -// MOVNTO xmm m128 -// Construct and append a MOVNTO instruction to the active function. -func (c *Context) MOVNTO(x, m operand.Op) { - if inst, err := x86.MOVNTO(x, m); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// LDDQU m128 xmm +// Construct and append a LDDQU instruction to the active function. +func (c *Context) LDDQU(m, x operand.Op) { + c.addinstruction(x86.LDDQU(m, x)) } -// MOVNTO: Store Double Quadword Using Non-Temporal Hint. +// LDDQU: Load Unaligned Integer 128 Bits. // // Forms: // -// MOVNTO xmm m128 -// Construct and append a MOVNTO instruction to the active function. +// LDDQU m128 xmm +// Construct and append a LDDQU instruction to the active function. // Operates on the global context. -func MOVNTO(x, m operand.Op) { ctx.MOVNTO(x, m) } +func LDDQU(m, x operand.Op) { ctx.LDDQU(m, x) } -// MOVNTPD: Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint. +// LDMXCSR: Load MXCSR Register. // // Forms: // -// MOVNTPD xmm m128 -// Construct and append a MOVNTPD instruction to the active function. -func (c *Context) MOVNTPD(x, m operand.Op) { - if inst, err := x86.MOVNTPD(x, m); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// LDMXCSR m32 +// Construct and append a LDMXCSR instruction to the active function. +func (c *Context) LDMXCSR(m operand.Op) { + c.addinstruction(x86.LDMXCSR(m)) } -// MOVNTPD: Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint. +// LDMXCSR: Load MXCSR Register. // // Forms: // -// MOVNTPD xmm m128 -// Construct and append a MOVNTPD instruction to the active function. +// LDMXCSR m32 +// Construct and append a LDMXCSR instruction to the active function. // Operates on the global context. -func MOVNTPD(x, m operand.Op) { ctx.MOVNTPD(x, m) } +func LDMXCSR(m operand.Op) { ctx.LDMXCSR(m) } -// MOVNTPS: Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint. +// LEAL: Load Effective Address. // // Forms: // -// MOVNTPS xmm m128 -// Construct and append a MOVNTPS instruction to the active function. -func (c *Context) MOVNTPS(x, m operand.Op) { - if inst, err := x86.MOVNTPS(x, m); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// LEAL m r32 +// Construct and append a LEAL instruction to the active function. +func (c *Context) LEAL(m, r operand.Op) { + c.addinstruction(x86.LEAL(m, r)) } -// MOVNTPS: Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint. +// LEAL: Load Effective Address. // // Forms: // -// MOVNTPS xmm m128 -// Construct and append a MOVNTPS instruction to the active function. +// LEAL m r32 +// Construct and append a LEAL instruction to the active function. // Operates on the global context. -func MOVNTPS(x, m operand.Op) { ctx.MOVNTPS(x, m) } +func LEAL(m, r operand.Op) { ctx.LEAL(m, r) } -// MOVO: Move Aligned Double Quadword. +// LEAQ: Load Effective Address. // // Forms: // -// MOVO xmm xmm -// MOVO m128 xmm -// MOVO xmm m128 -// Construct and append a MOVO instruction to the active function. -func (c *Context) MOVO(mx, mx1 operand.Op) { - if inst, err := x86.MOVO(mx, mx1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// LEAQ m r64 +// Construct and append a LEAQ instruction to the active function. +func (c *Context) LEAQ(m, r operand.Op) { + c.addinstruction(x86.LEAQ(m, r)) } -// MOVO: Move Aligned Double Quadword. +// LEAQ: Load Effective Address. // // Forms: // -// MOVO xmm xmm -// MOVO m128 xmm -// MOVO xmm m128 -// Construct and append a MOVO instruction to the active function. +// LEAQ m r64 +// Construct and append a LEAQ instruction to the active function. // Operates on the global context. -func MOVO(mx, mx1 operand.Op) { ctx.MOVO(mx, mx1) } +func LEAQ(m, r operand.Op) { ctx.LEAQ(m, r) } -// MOVOA: Move Aligned Double Quadword. +// LEAW: Load Effective Address. // // Forms: // -// MOVOA xmm xmm -// MOVOA m128 xmm -// MOVOA xmm m128 -// Construct and append a MOVOA instruction to the active function. -func (c *Context) MOVOA(mx, mx1 operand.Op) { - if inst, err := x86.MOVOA(mx, mx1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// LEAW m r16 +// Construct and append a LEAW instruction to the active function. +func (c *Context) LEAW(m, r operand.Op) { + c.addinstruction(x86.LEAW(m, r)) } -// MOVOA: Move Aligned Double Quadword. +// LEAW: Load Effective Address. // // Forms: // -// MOVOA xmm xmm -// MOVOA m128 xmm -// MOVOA xmm m128 -// Construct and append a MOVOA instruction to the active function. +// LEAW m r16 +// Construct and append a LEAW instruction to the active function. // Operates on the global context. -func MOVOA(mx, mx1 operand.Op) { ctx.MOVOA(mx, mx1) } +func LEAW(m, r operand.Op) { ctx.LEAW(m, r) } -// MOVOU: Move Unaligned Double Quadword. +// LFENCE: Load Fence. // // Forms: // -// MOVOU xmm xmm -// MOVOU m128 xmm -// MOVOU xmm m128 -// Construct and append a MOVOU instruction to the active function. -func (c *Context) MOVOU(mx, mx1 operand.Op) { - if inst, err := x86.MOVOU(mx, mx1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// LFENCE +// Construct and append a LFENCE instruction to the active function. +func (c *Context) LFENCE() { + c.addinstruction(x86.LFENCE()) } -// MOVOU: Move Unaligned Double Quadword. +// LFENCE: Load Fence. // // Forms: // -// MOVOU xmm xmm -// MOVOU m128 xmm -// MOVOU xmm m128 -// Construct and append a MOVOU instruction to the active function. +// LFENCE +// Construct and append a LFENCE instruction to the active function. // Operates on the global context. -func MOVOU(mx, mx1 operand.Op) { ctx.MOVOU(mx, mx1) } +func LFENCE() { ctx.LFENCE() } -// MOVQ: Move. +// LZCNTL: Count the Number of Leading Zero Bits. // // Forms: // -// MOVQ imm32 r64 -// MOVQ imm64 r64 -// MOVQ r64 r64 -// MOVQ m64 r64 -// MOVQ imm32 m64 -// MOVQ r64 m64 -// MOVQ xmm r64 -// MOVQ r64 xmm -// MOVQ xmm xmm -// MOVQ m64 xmm -// MOVQ xmm m64 -// MOVQ xmm r32 -// MOVQ r32 xmm -// MOVQ m32 xmm -// MOVQ xmm m32 -// Construct and append a MOVQ instruction to the active function. -func (c *Context) MOVQ(imrx, mrx operand.Op) { - if inst, err := x86.MOVQ(imrx, mrx); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// LZCNTL m32 r32 +// LZCNTL r32 r32 +// Construct and append a LZCNTL instruction to the active function. +func (c *Context) LZCNTL(mr, r operand.Op) { + c.addinstruction(x86.LZCNTL(mr, r)) } -// MOVQ: Move. +// LZCNTL: Count the Number of Leading Zero Bits. // // Forms: // -// MOVQ imm32 r64 -// MOVQ imm64 r64 -// MOVQ r64 r64 -// MOVQ m64 r64 -// MOVQ imm32 m64 -// MOVQ r64 m64 -// MOVQ xmm r64 -// MOVQ r64 xmm -// MOVQ xmm xmm -// MOVQ m64 xmm -// MOVQ xmm m64 -// MOVQ xmm r32 -// MOVQ r32 xmm -// MOVQ m32 xmm -// MOVQ xmm m32 -// Construct and append a MOVQ instruction to the active function. +// LZCNTL m32 r32 +// LZCNTL r32 r32 +// Construct and append a LZCNTL instruction to the active function. // Operates on the global context. -func MOVQ(imrx, mrx operand.Op) { ctx.MOVQ(imrx, mrx) } +func LZCNTL(mr, r operand.Op) { ctx.LZCNTL(mr, r) } -// MOVSD: Move Scalar Double-Precision Floating-Point Value. +// LZCNTQ: Count the Number of Leading Zero Bits. // // Forms: // -// MOVSD xmm xmm -// MOVSD m64 xmm -// MOVSD xmm m64 -// Construct and append a MOVSD instruction to the active function. -func (c *Context) MOVSD(mx, mx1 operand.Op) { - if inst, err := x86.MOVSD(mx, mx1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// LZCNTQ m64 r64 +// LZCNTQ r64 r64 +// Construct and append a LZCNTQ instruction to the active function. +func (c *Context) LZCNTQ(mr, r operand.Op) { + c.addinstruction(x86.LZCNTQ(mr, r)) } -// MOVSD: Move Scalar Double-Precision Floating-Point Value. +// LZCNTQ: Count the Number of Leading Zero Bits. // // Forms: // -// MOVSD xmm xmm -// MOVSD m64 xmm -// MOVSD xmm m64 -// Construct and append a MOVSD instruction to the active function. +// LZCNTQ m64 r64 +// LZCNTQ r64 r64 +// Construct and append a LZCNTQ instruction to the active function. // Operates on the global context. -func MOVSD(mx, mx1 operand.Op) { ctx.MOVSD(mx, mx1) } +func LZCNTQ(mr, r operand.Op) { ctx.LZCNTQ(mr, r) } -// MOVSHDUP: Move Packed Single-FP High and Duplicate. +// LZCNTW: Count the Number of Leading Zero Bits. // // Forms: // -// MOVSHDUP xmm xmm -// MOVSHDUP m128 xmm -// Construct and append a MOVSHDUP instruction to the active function. -func (c *Context) MOVSHDUP(mx, x operand.Op) { - if inst, err := x86.MOVSHDUP(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// LZCNTW m16 r16 +// LZCNTW r16 r16 +// Construct and append a LZCNTW instruction to the active function. +func (c *Context) LZCNTW(mr, r operand.Op) { + c.addinstruction(x86.LZCNTW(mr, r)) } -// MOVSHDUP: Move Packed Single-FP High and Duplicate. +// LZCNTW: Count the Number of Leading Zero Bits. // // Forms: // -// MOVSHDUP xmm xmm -// MOVSHDUP m128 xmm -// Construct and append a MOVSHDUP instruction to the active function. +// LZCNTW m16 r16 +// LZCNTW r16 r16 +// Construct and append a LZCNTW instruction to the active function. // Operates on the global context. -func MOVSHDUP(mx, x operand.Op) { ctx.MOVSHDUP(mx, x) } +func LZCNTW(mr, r operand.Op) { ctx.LZCNTW(mr, r) } -// MOVSLDUP: Move Packed Single-FP Low and Duplicate. +// MASKMOVDQU: Store Selected Bytes of Double Quadword. // // Forms: // -// MOVSLDUP xmm xmm -// MOVSLDUP m128 xmm -// Construct and append a MOVSLDUP instruction to the active function. -func (c *Context) MOVSLDUP(mx, x operand.Op) { - if inst, err := x86.MOVSLDUP(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// MASKMOVDQU xmm xmm +// Construct and append a MASKMOVDQU instruction to the active function. +func (c *Context) MASKMOVDQU(x, x1 operand.Op) { + c.addinstruction(x86.MASKMOVDQU(x, x1)) } -// MOVSLDUP: Move Packed Single-FP Low and Duplicate. +// MASKMOVDQU: Store Selected Bytes of Double Quadword. // // Forms: // -// MOVSLDUP xmm xmm -// MOVSLDUP m128 xmm -// Construct and append a MOVSLDUP instruction to the active function. +// MASKMOVDQU xmm xmm +// Construct and append a MASKMOVDQU instruction to the active function. // Operates on the global context. -func MOVSLDUP(mx, x operand.Op) { ctx.MOVSLDUP(mx, x) } +func MASKMOVDQU(x, x1 operand.Op) { ctx.MASKMOVDQU(x, x1) } -// MOVSS: Move Scalar Single-Precision Floating-Point Values. +// MASKMOVOU: Store Selected Bytes of Double Quadword. // // Forms: // -// MOVSS xmm xmm -// MOVSS m32 xmm -// MOVSS xmm m32 -// Construct and append a MOVSS instruction to the active function. -func (c *Context) MOVSS(mx, mx1 operand.Op) { - if inst, err := x86.MOVSS(mx, mx1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// MASKMOVOU xmm xmm +// Construct and append a MASKMOVOU instruction to the active function. +func (c *Context) MASKMOVOU(x, x1 operand.Op) { + c.addinstruction(x86.MASKMOVOU(x, x1)) } -// MOVSS: Move Scalar Single-Precision Floating-Point Values. +// MASKMOVOU: Store Selected Bytes of Double Quadword. // // Forms: // -// MOVSS xmm xmm -// MOVSS m32 xmm -// MOVSS xmm m32 -// Construct and append a MOVSS instruction to the active function. +// MASKMOVOU xmm xmm +// Construct and append a MASKMOVOU instruction to the active function. // Operates on the global context. -func MOVSS(mx, mx1 operand.Op) { ctx.MOVSS(mx, mx1) } +func MASKMOVOU(x, x1 operand.Op) { ctx.MASKMOVOU(x, x1) } -// MOVUPD: Move Unaligned Packed Double-Precision Floating-Point Values. +// MAXPD: Return Maximum Packed Double-Precision Floating-Point Values. // // Forms: // -// MOVUPD xmm xmm -// MOVUPD m128 xmm -// MOVUPD xmm m128 -// Construct and append a MOVUPD instruction to the active function. -func (c *Context) MOVUPD(mx, mx1 operand.Op) { - if inst, err := x86.MOVUPD(mx, mx1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// MAXPD m128 xmm +// MAXPD xmm xmm +// Construct and append a MAXPD instruction to the active function. +func (c *Context) MAXPD(mx, x operand.Op) { + c.addinstruction(x86.MAXPD(mx, x)) } -// MOVUPD: Move Unaligned Packed Double-Precision Floating-Point Values. +// MAXPD: Return Maximum Packed Double-Precision Floating-Point Values. // // Forms: // -// MOVUPD xmm xmm -// MOVUPD m128 xmm -// MOVUPD xmm m128 -// Construct and append a MOVUPD instruction to the active function. +// MAXPD m128 xmm +// MAXPD xmm xmm +// Construct and append a MAXPD instruction to the active function. // Operates on the global context. -func MOVUPD(mx, mx1 operand.Op) { ctx.MOVUPD(mx, mx1) } +func MAXPD(mx, x operand.Op) { ctx.MAXPD(mx, x) } -// MOVUPS: Move Unaligned Packed Single-Precision Floating-Point Values. +// MAXPS: Return Maximum Packed Single-Precision Floating-Point Values. // // Forms: // -// MOVUPS xmm xmm -// MOVUPS m128 xmm -// MOVUPS xmm m128 -// Construct and append a MOVUPS instruction to the active function. -func (c *Context) MOVUPS(mx, mx1 operand.Op) { - if inst, err := x86.MOVUPS(mx, mx1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// MAXPS m128 xmm +// MAXPS xmm xmm +// Construct and append a MAXPS instruction to the active function. +func (c *Context) MAXPS(mx, x operand.Op) { + c.addinstruction(x86.MAXPS(mx, x)) } -// MOVUPS: Move Unaligned Packed Single-Precision Floating-Point Values. +// MAXPS: Return Maximum Packed Single-Precision Floating-Point Values. // // Forms: // -// MOVUPS xmm xmm -// MOVUPS m128 xmm -// MOVUPS xmm m128 -// Construct and append a MOVUPS instruction to the active function. +// MAXPS m128 xmm +// MAXPS xmm xmm +// Construct and append a MAXPS instruction to the active function. // Operates on the global context. -func MOVUPS(mx, mx1 operand.Op) { ctx.MOVUPS(mx, mx1) } +func MAXPS(mx, x operand.Op) { ctx.MAXPS(mx, x) } -// MOVW: Move. +// MAXSD: Return Maximum Scalar Double-Precision Floating-Point Value. // // Forms: // -// MOVW imm16 r16 -// MOVW r16 r16 -// MOVW m16 r16 -// MOVW imm16 m16 -// MOVW r16 m16 -// Construct and append a MOVW instruction to the active function. -func (c *Context) MOVW(imr, mr operand.Op) { - if inst, err := x86.MOVW(imr, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// MAXSD m64 xmm +// MAXSD xmm xmm +// Construct and append a MAXSD instruction to the active function. +func (c *Context) MAXSD(mx, x operand.Op) { + c.addinstruction(x86.MAXSD(mx, x)) } -// MOVW: Move. +// MAXSD: Return Maximum Scalar Double-Precision Floating-Point Value. // // Forms: // -// MOVW imm16 r16 -// MOVW r16 r16 -// MOVW m16 r16 -// MOVW imm16 m16 -// MOVW r16 m16 -// Construct and append a MOVW instruction to the active function. +// MAXSD m64 xmm +// MAXSD xmm xmm +// Construct and append a MAXSD instruction to the active function. // Operates on the global context. -func MOVW(imr, mr operand.Op) { ctx.MOVW(imr, mr) } +func MAXSD(mx, x operand.Op) { ctx.MAXSD(mx, x) } -// MOVWLSX: Move with Sign-Extension. +// MAXSS: Return Maximum Scalar Single-Precision Floating-Point Value. // // Forms: // -// MOVWLSX r16 r32 -// MOVWLSX m16 r32 -// Construct and append a MOVWLSX instruction to the active function. -func (c *Context) MOVWLSX(mr, r operand.Op) { - if inst, err := x86.MOVWLSX(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// MAXSS m32 xmm +// MAXSS xmm xmm +// Construct and append a MAXSS instruction to the active function. +func (c *Context) MAXSS(mx, x operand.Op) { + c.addinstruction(x86.MAXSS(mx, x)) } -// MOVWLSX: Move with Sign-Extension. +// MAXSS: Return Maximum Scalar Single-Precision Floating-Point Value. // // Forms: // -// MOVWLSX r16 r32 -// MOVWLSX m16 r32 -// Construct and append a MOVWLSX instruction to the active function. +// MAXSS m32 xmm +// MAXSS xmm xmm +// Construct and append a MAXSS instruction to the active function. // Operates on the global context. -func MOVWLSX(mr, r operand.Op) { ctx.MOVWLSX(mr, r) } +func MAXSS(mx, x operand.Op) { ctx.MAXSS(mx, x) } -// MOVWLZX: Move with Zero-Extend. +// MFENCE: Memory Fence. // // Forms: // -// MOVWLZX r16 r32 -// MOVWLZX m16 r32 -// Construct and append a MOVWLZX instruction to the active function. -func (c *Context) MOVWLZX(mr, r operand.Op) { - if inst, err := x86.MOVWLZX(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// MFENCE +// Construct and append a MFENCE instruction to the active function. +func (c *Context) MFENCE() { + c.addinstruction(x86.MFENCE()) } -// MOVWLZX: Move with Zero-Extend. +// MFENCE: Memory Fence. // // Forms: // -// MOVWLZX r16 r32 -// MOVWLZX m16 r32 -// Construct and append a MOVWLZX instruction to the active function. +// MFENCE +// Construct and append a MFENCE instruction to the active function. // Operates on the global context. -func MOVWLZX(mr, r operand.Op) { ctx.MOVWLZX(mr, r) } +func MFENCE() { ctx.MFENCE() } -// MOVWQSX: Move with Sign-Extension. +// MINPD: Return Minimum Packed Double-Precision Floating-Point Values. // // Forms: // -// MOVWQSX r16 r64 -// MOVWQSX m16 r64 -// Construct and append a MOVWQSX instruction to the active function. -func (c *Context) MOVWQSX(mr, r operand.Op) { - if inst, err := x86.MOVWQSX(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// MINPD m128 xmm +// MINPD xmm xmm +// Construct and append a MINPD instruction to the active function. +func (c *Context) MINPD(mx, x operand.Op) { + c.addinstruction(x86.MINPD(mx, x)) } -// MOVWQSX: Move with Sign-Extension. +// MINPD: Return Minimum Packed Double-Precision Floating-Point Values. // // Forms: // -// MOVWQSX r16 r64 -// MOVWQSX m16 r64 -// Construct and append a MOVWQSX instruction to the active function. +// MINPD m128 xmm +// MINPD xmm xmm +// Construct and append a MINPD instruction to the active function. // Operates on the global context. -func MOVWQSX(mr, r operand.Op) { ctx.MOVWQSX(mr, r) } +func MINPD(mx, x operand.Op) { ctx.MINPD(mx, x) } -// MOVWQZX: Move with Zero-Extend. +// MINPS: Return Minimum Packed Single-Precision Floating-Point Values. // // Forms: // -// MOVWQZX r16 r64 -// MOVWQZX m16 r64 -// Construct and append a MOVWQZX instruction to the active function. +// MINPS m128 xmm +// MINPS xmm xmm +// Construct and append a MINPS instruction to the active function. +func (c *Context) MINPS(mx, x operand.Op) { + c.addinstruction(x86.MINPS(mx, x)) +} + +// MINPS: Return Minimum Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// MINPS m128 xmm +// MINPS xmm xmm +// Construct and append a MINPS instruction to the active function. +// Operates on the global context. +func MINPS(mx, x operand.Op) { ctx.MINPS(mx, x) } + +// MINSD: Return Minimum Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// MINSD m64 xmm +// MINSD xmm xmm +// Construct and append a MINSD instruction to the active function. +func (c *Context) MINSD(mx, x operand.Op) { + c.addinstruction(x86.MINSD(mx, x)) +} + +// MINSD: Return Minimum Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// MINSD m64 xmm +// MINSD xmm xmm +// Construct and append a MINSD instruction to the active function. +// Operates on the global context. +func MINSD(mx, x operand.Op) { ctx.MINSD(mx, x) } + +// MINSS: Return Minimum Scalar Single-Precision Floating-Point Value. +// +// Forms: +// +// MINSS m32 xmm +// MINSS xmm xmm +// Construct and append a MINSS instruction to the active function. +func (c *Context) MINSS(mx, x operand.Op) { + c.addinstruction(x86.MINSS(mx, x)) +} + +// MINSS: Return Minimum Scalar Single-Precision Floating-Point Value. +// +// Forms: +// +// MINSS m32 xmm +// MINSS xmm xmm +// Construct and append a MINSS instruction to the active function. +// Operates on the global context. +func MINSS(mx, x operand.Op) { ctx.MINSS(mx, x) } + +// MONITOR: Monitor a Linear Address Range. +// +// Forms: +// +// MONITOR +// Construct and append a MONITOR instruction to the active function. +func (c *Context) MONITOR() { + c.addinstruction(x86.MONITOR()) +} + +// MONITOR: Monitor a Linear Address Range. +// +// Forms: +// +// MONITOR +// Construct and append a MONITOR instruction to the active function. +// Operates on the global context. +func MONITOR() { ctx.MONITOR() } + +// MOVAPD: Move Aligned Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// MOVAPD m128 xmm +// MOVAPD xmm m128 +// MOVAPD xmm xmm +// Construct and append a MOVAPD instruction to the active function. +func (c *Context) MOVAPD(mx, mx1 operand.Op) { + c.addinstruction(x86.MOVAPD(mx, mx1)) +} + +// MOVAPD: Move Aligned Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// MOVAPD m128 xmm +// MOVAPD xmm m128 +// MOVAPD xmm xmm +// Construct and append a MOVAPD instruction to the active function. +// Operates on the global context. +func MOVAPD(mx, mx1 operand.Op) { ctx.MOVAPD(mx, mx1) } + +// MOVAPS: Move Aligned Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// MOVAPS m128 xmm +// MOVAPS xmm m128 +// MOVAPS xmm xmm +// Construct and append a MOVAPS instruction to the active function. +func (c *Context) MOVAPS(mx, mx1 operand.Op) { + c.addinstruction(x86.MOVAPS(mx, mx1)) +} + +// MOVAPS: Move Aligned Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// MOVAPS m128 xmm +// MOVAPS xmm m128 +// MOVAPS xmm xmm +// Construct and append a MOVAPS instruction to the active function. +// Operates on the global context. +func MOVAPS(mx, mx1 operand.Op) { ctx.MOVAPS(mx, mx1) } + +// MOVB: Move. +// +// Forms: +// +// MOVB imm8 m8 +// MOVB imm8 r8 +// MOVB m8 r8 +// MOVB r8 m8 +// MOVB r8 r8 +// Construct and append a MOVB instruction to the active function. +func (c *Context) MOVB(imr, mr operand.Op) { + c.addinstruction(x86.MOVB(imr, mr)) +} + +// MOVB: Move. +// +// Forms: +// +// MOVB imm8 m8 +// MOVB imm8 r8 +// MOVB m8 r8 +// MOVB r8 m8 +// MOVB r8 r8 +// Construct and append a MOVB instruction to the active function. +// Operates on the global context. +func MOVB(imr, mr operand.Op) { ctx.MOVB(imr, mr) } + +// MOVBELL: Move Data After Swapping Bytes. +// +// Forms: +// +// MOVBELL m32 r32 +// MOVBELL r32 m32 +// Construct and append a MOVBELL instruction to the active function. +func (c *Context) MOVBELL(mr, mr1 operand.Op) { + c.addinstruction(x86.MOVBELL(mr, mr1)) +} + +// MOVBELL: Move Data After Swapping Bytes. +// +// Forms: +// +// MOVBELL m32 r32 +// MOVBELL r32 m32 +// Construct and append a MOVBELL instruction to the active function. +// Operates on the global context. +func MOVBELL(mr, mr1 operand.Op) { ctx.MOVBELL(mr, mr1) } + +// MOVBEQQ: Move Data After Swapping Bytes. +// +// Forms: +// +// MOVBEQQ m64 r64 +// MOVBEQQ r64 m64 +// Construct and append a MOVBEQQ instruction to the active function. +func (c *Context) MOVBEQQ(mr, mr1 operand.Op) { + c.addinstruction(x86.MOVBEQQ(mr, mr1)) +} + +// MOVBEQQ: Move Data After Swapping Bytes. +// +// Forms: +// +// MOVBEQQ m64 r64 +// MOVBEQQ r64 m64 +// Construct and append a MOVBEQQ instruction to the active function. +// Operates on the global context. +func MOVBEQQ(mr, mr1 operand.Op) { ctx.MOVBEQQ(mr, mr1) } + +// MOVBEWW: Move Data After Swapping Bytes. +// +// Forms: +// +// MOVBEWW m16 r16 +// MOVBEWW r16 m16 +// Construct and append a MOVBEWW instruction to the active function. +func (c *Context) MOVBEWW(mr, mr1 operand.Op) { + c.addinstruction(x86.MOVBEWW(mr, mr1)) +} + +// MOVBEWW: Move Data After Swapping Bytes. +// +// Forms: +// +// MOVBEWW m16 r16 +// MOVBEWW r16 m16 +// Construct and append a MOVBEWW instruction to the active function. +// Operates on the global context. +func MOVBEWW(mr, mr1 operand.Op) { ctx.MOVBEWW(mr, mr1) } + +// MOVBLSX: Move with Sign-Extension. +// +// Forms: +// +// MOVBLSX m8 r32 +// MOVBLSX r8 r32 +// Construct and append a MOVBLSX instruction to the active function. +func (c *Context) MOVBLSX(mr, r operand.Op) { + c.addinstruction(x86.MOVBLSX(mr, r)) +} + +// MOVBLSX: Move with Sign-Extension. +// +// Forms: +// +// MOVBLSX m8 r32 +// MOVBLSX r8 r32 +// Construct and append a MOVBLSX instruction to the active function. +// Operates on the global context. +func MOVBLSX(mr, r operand.Op) { ctx.MOVBLSX(mr, r) } + +// MOVBLZX: Move with Zero-Extend. +// +// Forms: +// +// MOVBLZX m8 r32 +// MOVBLZX r8 r32 +// Construct and append a MOVBLZX instruction to the active function. +func (c *Context) MOVBLZX(mr, r operand.Op) { + c.addinstruction(x86.MOVBLZX(mr, r)) +} + +// MOVBLZX: Move with Zero-Extend. +// +// Forms: +// +// MOVBLZX m8 r32 +// MOVBLZX r8 r32 +// Construct and append a MOVBLZX instruction to the active function. +// Operates on the global context. +func MOVBLZX(mr, r operand.Op) { ctx.MOVBLZX(mr, r) } + +// MOVBQSX: Move with Sign-Extension. +// +// Forms: +// +// MOVBQSX m8 r64 +// MOVBQSX r8 r64 +// Construct and append a MOVBQSX instruction to the active function. +func (c *Context) MOVBQSX(mr, r operand.Op) { + c.addinstruction(x86.MOVBQSX(mr, r)) +} + +// MOVBQSX: Move with Sign-Extension. +// +// Forms: +// +// MOVBQSX m8 r64 +// MOVBQSX r8 r64 +// Construct and append a MOVBQSX instruction to the active function. +// Operates on the global context. +func MOVBQSX(mr, r operand.Op) { ctx.MOVBQSX(mr, r) } + +// MOVBQZX: Move with Zero-Extend. +// +// Forms: +// +// MOVBQZX m8 r64 +// MOVBQZX r8 r64 +// Construct and append a MOVBQZX instruction to the active function. +func (c *Context) MOVBQZX(mr, r operand.Op) { + c.addinstruction(x86.MOVBQZX(mr, r)) +} + +// MOVBQZX: Move with Zero-Extend. +// +// Forms: +// +// MOVBQZX m8 r64 +// MOVBQZX r8 r64 +// Construct and append a MOVBQZX instruction to the active function. +// Operates on the global context. +func MOVBQZX(mr, r operand.Op) { ctx.MOVBQZX(mr, r) } + +// MOVBWSX: Move with Sign-Extension. +// +// Forms: +// +// MOVBWSX m8 r16 +// MOVBWSX r8 r16 +// Construct and append a MOVBWSX instruction to the active function. +func (c *Context) MOVBWSX(mr, r operand.Op) { + c.addinstruction(x86.MOVBWSX(mr, r)) +} + +// MOVBWSX: Move with Sign-Extension. +// +// Forms: +// +// MOVBWSX m8 r16 +// MOVBWSX r8 r16 +// Construct and append a MOVBWSX instruction to the active function. +// Operates on the global context. +func MOVBWSX(mr, r operand.Op) { ctx.MOVBWSX(mr, r) } + +// MOVBWZX: Move with Zero-Extend. +// +// Forms: +// +// MOVBWZX m8 r16 +// MOVBWZX r8 r16 +// Construct and append a MOVBWZX instruction to the active function. +func (c *Context) MOVBWZX(mr, r operand.Op) { + c.addinstruction(x86.MOVBWZX(mr, r)) +} + +// MOVBWZX: Move with Zero-Extend. +// +// Forms: +// +// MOVBWZX m8 r16 +// MOVBWZX r8 r16 +// Construct and append a MOVBWZX instruction to the active function. +// Operates on the global context. +func MOVBWZX(mr, r operand.Op) { ctx.MOVBWZX(mr, r) } + +// MOVD: Move. +// +// Forms: +// +// MOVD m32 xmm +// MOVD m64 xmm +// MOVD r32 xmm +// MOVD r64 xmm +// MOVD xmm m32 +// MOVD xmm m64 +// MOVD xmm r32 +// MOVD xmm r64 +// MOVD xmm xmm +// MOVD imm32 m64 +// MOVD imm32 r64 +// MOVD imm64 r64 +// MOVD m64 r64 +// MOVD r64 m64 +// MOVD r64 r64 +// Construct and append a MOVD instruction to the active function. +func (c *Context) MOVD(imrx, mrx operand.Op) { + c.addinstruction(x86.MOVD(imrx, mrx)) +} + +// MOVD: Move. +// +// Forms: +// +// MOVD m32 xmm +// MOVD m64 xmm +// MOVD r32 xmm +// MOVD r64 xmm +// MOVD xmm m32 +// MOVD xmm m64 +// MOVD xmm r32 +// MOVD xmm r64 +// MOVD xmm xmm +// MOVD imm32 m64 +// MOVD imm32 r64 +// MOVD imm64 r64 +// MOVD m64 r64 +// MOVD r64 m64 +// MOVD r64 r64 +// Construct and append a MOVD instruction to the active function. +// Operates on the global context. +func MOVD(imrx, mrx operand.Op) { ctx.MOVD(imrx, mrx) } + +// MOVDDUP: Move One Double-FP and Duplicate. +// +// Forms: +// +// MOVDDUP m64 xmm +// MOVDDUP xmm xmm +// Construct and append a MOVDDUP instruction to the active function. +func (c *Context) MOVDDUP(mx, x operand.Op) { + c.addinstruction(x86.MOVDDUP(mx, x)) +} + +// MOVDDUP: Move One Double-FP and Duplicate. +// +// Forms: +// +// MOVDDUP m64 xmm +// MOVDDUP xmm xmm +// Construct and append a MOVDDUP instruction to the active function. +// Operates on the global context. +func MOVDDUP(mx, x operand.Op) { ctx.MOVDDUP(mx, x) } + +// MOVDQ2Q: Move. +// +// Forms: +// +// MOVDQ2Q m32 xmm +// MOVDQ2Q m64 xmm +// MOVDQ2Q r32 xmm +// MOVDQ2Q r64 xmm +// MOVDQ2Q xmm m32 +// MOVDQ2Q xmm m64 +// MOVDQ2Q xmm r32 +// MOVDQ2Q xmm r64 +// MOVDQ2Q xmm xmm +// MOVDQ2Q imm32 m64 +// MOVDQ2Q imm32 r64 +// MOVDQ2Q imm64 r64 +// MOVDQ2Q m64 r64 +// MOVDQ2Q r64 m64 +// MOVDQ2Q r64 r64 +// Construct and append a MOVDQ2Q instruction to the active function. +func (c *Context) MOVDQ2Q(imrx, mrx operand.Op) { + c.addinstruction(x86.MOVDQ2Q(imrx, mrx)) +} + +// MOVDQ2Q: Move. +// +// Forms: +// +// MOVDQ2Q m32 xmm +// MOVDQ2Q m64 xmm +// MOVDQ2Q r32 xmm +// MOVDQ2Q r64 xmm +// MOVDQ2Q xmm m32 +// MOVDQ2Q xmm m64 +// MOVDQ2Q xmm r32 +// MOVDQ2Q xmm r64 +// MOVDQ2Q xmm xmm +// MOVDQ2Q imm32 m64 +// MOVDQ2Q imm32 r64 +// MOVDQ2Q imm64 r64 +// MOVDQ2Q m64 r64 +// MOVDQ2Q r64 m64 +// MOVDQ2Q r64 r64 +// Construct and append a MOVDQ2Q instruction to the active function. +// Operates on the global context. +func MOVDQ2Q(imrx, mrx operand.Op) { ctx.MOVDQ2Q(imrx, mrx) } + +// MOVHLPS: Move Packed Single-Precision Floating-Point Values High to Low. +// +// Forms: +// +// MOVHLPS xmm xmm +// Construct and append a MOVHLPS instruction to the active function. +func (c *Context) MOVHLPS(x, x1 operand.Op) { + c.addinstruction(x86.MOVHLPS(x, x1)) +} + +// MOVHLPS: Move Packed Single-Precision Floating-Point Values High to Low. +// +// Forms: +// +// MOVHLPS xmm xmm +// Construct and append a MOVHLPS instruction to the active function. +// Operates on the global context. +func MOVHLPS(x, x1 operand.Op) { ctx.MOVHLPS(x, x1) } + +// MOVHPD: Move High Packed Double-Precision Floating-Point Value. +// +// Forms: +// +// MOVHPD m64 xmm +// MOVHPD xmm m64 +// Construct and append a MOVHPD instruction to the active function. +func (c *Context) MOVHPD(mx, mx1 operand.Op) { + c.addinstruction(x86.MOVHPD(mx, mx1)) +} + +// MOVHPD: Move High Packed Double-Precision Floating-Point Value. +// +// Forms: +// +// MOVHPD m64 xmm +// MOVHPD xmm m64 +// Construct and append a MOVHPD instruction to the active function. +// Operates on the global context. +func MOVHPD(mx, mx1 operand.Op) { ctx.MOVHPD(mx, mx1) } + +// MOVHPS: Move High Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// MOVHPS m64 xmm +// MOVHPS xmm m64 +// Construct and append a MOVHPS instruction to the active function. +func (c *Context) MOVHPS(mx, mx1 operand.Op) { + c.addinstruction(x86.MOVHPS(mx, mx1)) +} + +// MOVHPS: Move High Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// MOVHPS m64 xmm +// MOVHPS xmm m64 +// Construct and append a MOVHPS instruction to the active function. +// Operates on the global context. +func MOVHPS(mx, mx1 operand.Op) { ctx.MOVHPS(mx, mx1) } + +// MOVL: Move. +// +// Forms: +// +// MOVL imm32 m32 +// MOVL imm32 r32 +// MOVL m32 r32 +// MOVL r32 m32 +// MOVL r32 r32 +// Construct and append a MOVL instruction to the active function. +func (c *Context) MOVL(imr, mr operand.Op) { + c.addinstruction(x86.MOVL(imr, mr)) +} + +// MOVL: Move. +// +// Forms: +// +// MOVL imm32 m32 +// MOVL imm32 r32 +// MOVL m32 r32 +// MOVL r32 m32 +// MOVL r32 r32 +// Construct and append a MOVL instruction to the active function. +// Operates on the global context. +func MOVL(imr, mr operand.Op) { ctx.MOVL(imr, mr) } + +// MOVLHPS: Move Packed Single-Precision Floating-Point Values Low to High. +// +// Forms: +// +// MOVLHPS xmm xmm +// Construct and append a MOVLHPS instruction to the active function. +func (c *Context) MOVLHPS(x, x1 operand.Op) { + c.addinstruction(x86.MOVLHPS(x, x1)) +} + +// MOVLHPS: Move Packed Single-Precision Floating-Point Values Low to High. +// +// Forms: +// +// MOVLHPS xmm xmm +// Construct and append a MOVLHPS instruction to the active function. +// Operates on the global context. +func MOVLHPS(x, x1 operand.Op) { ctx.MOVLHPS(x, x1) } + +// MOVLPD: Move Low Packed Double-Precision Floating-Point Value. +// +// Forms: +// +// MOVLPD m64 xmm +// MOVLPD xmm m64 +// Construct and append a MOVLPD instruction to the active function. +func (c *Context) MOVLPD(mx, mx1 operand.Op) { + c.addinstruction(x86.MOVLPD(mx, mx1)) +} + +// MOVLPD: Move Low Packed Double-Precision Floating-Point Value. +// +// Forms: +// +// MOVLPD m64 xmm +// MOVLPD xmm m64 +// Construct and append a MOVLPD instruction to the active function. +// Operates on the global context. +func MOVLPD(mx, mx1 operand.Op) { ctx.MOVLPD(mx, mx1) } + +// MOVLPS: Move Low Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// MOVLPS m64 xmm +// MOVLPS xmm m64 +// Construct and append a MOVLPS instruction to the active function. +func (c *Context) MOVLPS(mx, mx1 operand.Op) { + c.addinstruction(x86.MOVLPS(mx, mx1)) +} + +// MOVLPS: Move Low Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// MOVLPS m64 xmm +// MOVLPS xmm m64 +// Construct and append a MOVLPS instruction to the active function. +// Operates on the global context. +func MOVLPS(mx, mx1 operand.Op) { ctx.MOVLPS(mx, mx1) } + +// MOVLQSX: Move Doubleword to Quadword with Sign-Extension. +// +// Forms: +// +// MOVLQSX m32 r64 +// MOVLQSX r32 r64 +// Construct and append a MOVLQSX instruction to the active function. +func (c *Context) MOVLQSX(mr, r operand.Op) { + c.addinstruction(x86.MOVLQSX(mr, r)) +} + +// MOVLQSX: Move Doubleword to Quadword with Sign-Extension. +// +// Forms: +// +// MOVLQSX m32 r64 +// MOVLQSX r32 r64 +// Construct and append a MOVLQSX instruction to the active function. +// Operates on the global context. +func MOVLQSX(mr, r operand.Op) { ctx.MOVLQSX(mr, r) } + +// MOVLQZX: Move with Zero-Extend. +// +// Forms: +// +// MOVLQZX m32 r64 +// Construct and append a MOVLQZX instruction to the active function. +func (c *Context) MOVLQZX(m, r operand.Op) { + c.addinstruction(x86.MOVLQZX(m, r)) +} + +// MOVLQZX: Move with Zero-Extend. +// +// Forms: +// +// MOVLQZX m32 r64 +// Construct and append a MOVLQZX instruction to the active function. +// Operates on the global context. +func MOVLQZX(m, r operand.Op) { ctx.MOVLQZX(m, r) } + +// MOVMSKPD: Extract Packed Double-Precision Floating-Point Sign Mask. +// +// Forms: +// +// MOVMSKPD xmm r32 +// Construct and append a MOVMSKPD instruction to the active function. +func (c *Context) MOVMSKPD(x, r operand.Op) { + c.addinstruction(x86.MOVMSKPD(x, r)) +} + +// MOVMSKPD: Extract Packed Double-Precision Floating-Point Sign Mask. +// +// Forms: +// +// MOVMSKPD xmm r32 +// Construct and append a MOVMSKPD instruction to the active function. +// Operates on the global context. +func MOVMSKPD(x, r operand.Op) { ctx.MOVMSKPD(x, r) } + +// MOVMSKPS: Extract Packed Single-Precision Floating-Point Sign Mask. +// +// Forms: +// +// MOVMSKPS xmm r32 +// Construct and append a MOVMSKPS instruction to the active function. +func (c *Context) MOVMSKPS(x, r operand.Op) { + c.addinstruction(x86.MOVMSKPS(x, r)) +} + +// MOVMSKPS: Extract Packed Single-Precision Floating-Point Sign Mask. +// +// Forms: +// +// MOVMSKPS xmm r32 +// Construct and append a MOVMSKPS instruction to the active function. +// Operates on the global context. +func MOVMSKPS(x, r operand.Op) { ctx.MOVMSKPS(x, r) } + +// MOVNTDQ: Store Double Quadword Using Non-Temporal Hint. +// +// Forms: +// +// MOVNTDQ xmm m128 +// Construct and append a MOVNTDQ instruction to the active function. +func (c *Context) MOVNTDQ(x, m operand.Op) { + c.addinstruction(x86.MOVNTDQ(x, m)) +} + +// MOVNTDQ: Store Double Quadword Using Non-Temporal Hint. +// +// Forms: +// +// MOVNTDQ xmm m128 +// Construct and append a MOVNTDQ instruction to the active function. +// Operates on the global context. +func MOVNTDQ(x, m operand.Op) { ctx.MOVNTDQ(x, m) } + +// MOVNTDQA: Load Double Quadword Non-Temporal Aligned Hint. +// +// Forms: +// +// MOVNTDQA m128 xmm +// Construct and append a MOVNTDQA instruction to the active function. +func (c *Context) MOVNTDQA(m, x operand.Op) { + c.addinstruction(x86.MOVNTDQA(m, x)) +} + +// MOVNTDQA: Load Double Quadword Non-Temporal Aligned Hint. +// +// Forms: +// +// MOVNTDQA m128 xmm +// Construct and append a MOVNTDQA instruction to the active function. +// Operates on the global context. +func MOVNTDQA(m, x operand.Op) { ctx.MOVNTDQA(m, x) } + +// MOVNTIL: Store Doubleword Using Non-Temporal Hint. +// +// Forms: +// +// MOVNTIL r32 m32 +// Construct and append a MOVNTIL instruction to the active function. +func (c *Context) MOVNTIL(r, m operand.Op) { + c.addinstruction(x86.MOVNTIL(r, m)) +} + +// MOVNTIL: Store Doubleword Using Non-Temporal Hint. +// +// Forms: +// +// MOVNTIL r32 m32 +// Construct and append a MOVNTIL instruction to the active function. +// Operates on the global context. +func MOVNTIL(r, m operand.Op) { ctx.MOVNTIL(r, m) } + +// MOVNTIQ: Store Doubleword Using Non-Temporal Hint. +// +// Forms: +// +// MOVNTIQ r64 m64 +// Construct and append a MOVNTIQ instruction to the active function. +func (c *Context) MOVNTIQ(r, m operand.Op) { + c.addinstruction(x86.MOVNTIQ(r, m)) +} + +// MOVNTIQ: Store Doubleword Using Non-Temporal Hint. +// +// Forms: +// +// MOVNTIQ r64 m64 +// Construct and append a MOVNTIQ instruction to the active function. +// Operates on the global context. +func MOVNTIQ(r, m operand.Op) { ctx.MOVNTIQ(r, m) } + +// MOVNTO: Store Double Quadword Using Non-Temporal Hint. +// +// Forms: +// +// MOVNTO xmm m128 +// Construct and append a MOVNTO instruction to the active function. +func (c *Context) MOVNTO(x, m operand.Op) { + c.addinstruction(x86.MOVNTO(x, m)) +} + +// MOVNTO: Store Double Quadword Using Non-Temporal Hint. +// +// Forms: +// +// MOVNTO xmm m128 +// Construct and append a MOVNTO instruction to the active function. +// Operates on the global context. +func MOVNTO(x, m operand.Op) { ctx.MOVNTO(x, m) } + +// MOVNTPD: Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint. +// +// Forms: +// +// MOVNTPD xmm m128 +// Construct and append a MOVNTPD instruction to the active function. +func (c *Context) MOVNTPD(x, m operand.Op) { + c.addinstruction(x86.MOVNTPD(x, m)) +} + +// MOVNTPD: Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint. +// +// Forms: +// +// MOVNTPD xmm m128 +// Construct and append a MOVNTPD instruction to the active function. +// Operates on the global context. +func MOVNTPD(x, m operand.Op) { ctx.MOVNTPD(x, m) } + +// MOVNTPS: Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint. +// +// Forms: +// +// MOVNTPS xmm m128 +// Construct and append a MOVNTPS instruction to the active function. +func (c *Context) MOVNTPS(x, m operand.Op) { + c.addinstruction(x86.MOVNTPS(x, m)) +} + +// MOVNTPS: Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint. +// +// Forms: +// +// MOVNTPS xmm m128 +// Construct and append a MOVNTPS instruction to the active function. +// Operates on the global context. +func MOVNTPS(x, m operand.Op) { ctx.MOVNTPS(x, m) } + +// MOVO: Move Aligned Double Quadword. +// +// Forms: +// +// MOVO m128 xmm +// MOVO xmm m128 +// MOVO xmm xmm +// Construct and append a MOVO instruction to the active function. +func (c *Context) MOVO(mx, mx1 operand.Op) { + c.addinstruction(x86.MOVO(mx, mx1)) +} + +// MOVO: Move Aligned Double Quadword. +// +// Forms: +// +// MOVO m128 xmm +// MOVO xmm m128 +// MOVO xmm xmm +// Construct and append a MOVO instruction to the active function. +// Operates on the global context. +func MOVO(mx, mx1 operand.Op) { ctx.MOVO(mx, mx1) } + +// MOVOA: Move Aligned Double Quadword. +// +// Forms: +// +// MOVOA m128 xmm +// MOVOA xmm m128 +// MOVOA xmm xmm +// Construct and append a MOVOA instruction to the active function. +func (c *Context) MOVOA(mx, mx1 operand.Op) { + c.addinstruction(x86.MOVOA(mx, mx1)) +} + +// MOVOA: Move Aligned Double Quadword. +// +// Forms: +// +// MOVOA m128 xmm +// MOVOA xmm m128 +// MOVOA xmm xmm +// Construct and append a MOVOA instruction to the active function. +// Operates on the global context. +func MOVOA(mx, mx1 operand.Op) { ctx.MOVOA(mx, mx1) } + +// MOVOU: Move Unaligned Double Quadword. +// +// Forms: +// +// MOVOU m128 xmm +// MOVOU xmm m128 +// MOVOU xmm xmm +// Construct and append a MOVOU instruction to the active function. +func (c *Context) MOVOU(mx, mx1 operand.Op) { + c.addinstruction(x86.MOVOU(mx, mx1)) +} + +// MOVOU: Move Unaligned Double Quadword. +// +// Forms: +// +// MOVOU m128 xmm +// MOVOU xmm m128 +// MOVOU xmm xmm +// Construct and append a MOVOU instruction to the active function. +// Operates on the global context. +func MOVOU(mx, mx1 operand.Op) { ctx.MOVOU(mx, mx1) } + +// MOVQ: Move. +// +// Forms: +// +// MOVQ m32 xmm +// MOVQ m64 xmm +// MOVQ r32 xmm +// MOVQ r64 xmm +// MOVQ xmm m32 +// MOVQ xmm m64 +// MOVQ xmm r32 +// MOVQ xmm r64 +// MOVQ xmm xmm +// MOVQ imm32 m64 +// MOVQ imm32 r64 +// MOVQ imm64 r64 +// MOVQ m64 r64 +// MOVQ r64 m64 +// MOVQ r64 r64 +// Construct and append a MOVQ instruction to the active function. +func (c *Context) MOVQ(imrx, mrx operand.Op) { + c.addinstruction(x86.MOVQ(imrx, mrx)) +} + +// MOVQ: Move. +// +// Forms: +// +// MOVQ m32 xmm +// MOVQ m64 xmm +// MOVQ r32 xmm +// MOVQ r64 xmm +// MOVQ xmm m32 +// MOVQ xmm m64 +// MOVQ xmm r32 +// MOVQ xmm r64 +// MOVQ xmm xmm +// MOVQ imm32 m64 +// MOVQ imm32 r64 +// MOVQ imm64 r64 +// MOVQ m64 r64 +// MOVQ r64 m64 +// MOVQ r64 r64 +// Construct and append a MOVQ instruction to the active function. +// Operates on the global context. +func MOVQ(imrx, mrx operand.Op) { ctx.MOVQ(imrx, mrx) } + +// MOVSD: Move Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// MOVSD m64 xmm +// MOVSD xmm m64 +// MOVSD xmm xmm +// Construct and append a MOVSD instruction to the active function. +func (c *Context) MOVSD(mx, mx1 operand.Op) { + c.addinstruction(x86.MOVSD(mx, mx1)) +} + +// MOVSD: Move Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// MOVSD m64 xmm +// MOVSD xmm m64 +// MOVSD xmm xmm +// Construct and append a MOVSD instruction to the active function. +// Operates on the global context. +func MOVSD(mx, mx1 operand.Op) { ctx.MOVSD(mx, mx1) } + +// MOVSHDUP: Move Packed Single-FP High and Duplicate. +// +// Forms: +// +// MOVSHDUP m128 xmm +// MOVSHDUP xmm xmm +// Construct and append a MOVSHDUP instruction to the active function. +func (c *Context) MOVSHDUP(mx, x operand.Op) { + c.addinstruction(x86.MOVSHDUP(mx, x)) +} + +// MOVSHDUP: Move Packed Single-FP High and Duplicate. +// +// Forms: +// +// MOVSHDUP m128 xmm +// MOVSHDUP xmm xmm +// Construct and append a MOVSHDUP instruction to the active function. +// Operates on the global context. +func MOVSHDUP(mx, x operand.Op) { ctx.MOVSHDUP(mx, x) } + +// MOVSLDUP: Move Packed Single-FP Low and Duplicate. +// +// Forms: +// +// MOVSLDUP m128 xmm +// MOVSLDUP xmm xmm +// Construct and append a MOVSLDUP instruction to the active function. +func (c *Context) MOVSLDUP(mx, x operand.Op) { + c.addinstruction(x86.MOVSLDUP(mx, x)) +} + +// MOVSLDUP: Move Packed Single-FP Low and Duplicate. +// +// Forms: +// +// MOVSLDUP m128 xmm +// MOVSLDUP xmm xmm +// Construct and append a MOVSLDUP instruction to the active function. +// Operates on the global context. +func MOVSLDUP(mx, x operand.Op) { ctx.MOVSLDUP(mx, x) } + +// MOVSS: Move Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// MOVSS m32 xmm +// MOVSS xmm m32 +// MOVSS xmm xmm +// Construct and append a MOVSS instruction to the active function. +func (c *Context) MOVSS(mx, mx1 operand.Op) { + c.addinstruction(x86.MOVSS(mx, mx1)) +} + +// MOVSS: Move Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// MOVSS m32 xmm +// MOVSS xmm m32 +// MOVSS xmm xmm +// Construct and append a MOVSS instruction to the active function. +// Operates on the global context. +func MOVSS(mx, mx1 operand.Op) { ctx.MOVSS(mx, mx1) } + +// MOVUPD: Move Unaligned Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// MOVUPD m128 xmm +// MOVUPD xmm m128 +// MOVUPD xmm xmm +// Construct and append a MOVUPD instruction to the active function. +func (c *Context) MOVUPD(mx, mx1 operand.Op) { + c.addinstruction(x86.MOVUPD(mx, mx1)) +} + +// MOVUPD: Move Unaligned Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// MOVUPD m128 xmm +// MOVUPD xmm m128 +// MOVUPD xmm xmm +// Construct and append a MOVUPD instruction to the active function. +// Operates on the global context. +func MOVUPD(mx, mx1 operand.Op) { ctx.MOVUPD(mx, mx1) } + +// MOVUPS: Move Unaligned Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// MOVUPS m128 xmm +// MOVUPS xmm m128 +// MOVUPS xmm xmm +// Construct and append a MOVUPS instruction to the active function. +func (c *Context) MOVUPS(mx, mx1 operand.Op) { + c.addinstruction(x86.MOVUPS(mx, mx1)) +} + +// MOVUPS: Move Unaligned Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// MOVUPS m128 xmm +// MOVUPS xmm m128 +// MOVUPS xmm xmm +// Construct and append a MOVUPS instruction to the active function. +// Operates on the global context. +func MOVUPS(mx, mx1 operand.Op) { ctx.MOVUPS(mx, mx1) } + +// MOVW: Move. +// +// Forms: +// +// MOVW imm16 m16 +// MOVW imm16 r16 +// MOVW m16 r16 +// MOVW r16 m16 +// MOVW r16 r16 +// Construct and append a MOVW instruction to the active function. +func (c *Context) MOVW(imr, mr operand.Op) { + c.addinstruction(x86.MOVW(imr, mr)) +} + +// MOVW: Move. +// +// Forms: +// +// MOVW imm16 m16 +// MOVW imm16 r16 +// MOVW m16 r16 +// MOVW r16 m16 +// MOVW r16 r16 +// Construct and append a MOVW instruction to the active function. +// Operates on the global context. +func MOVW(imr, mr operand.Op) { ctx.MOVW(imr, mr) } + +// MOVWLSX: Move with Sign-Extension. +// +// Forms: +// +// MOVWLSX m16 r32 +// MOVWLSX r16 r32 +// Construct and append a MOVWLSX instruction to the active function. +func (c *Context) MOVWLSX(mr, r operand.Op) { + c.addinstruction(x86.MOVWLSX(mr, r)) +} + +// MOVWLSX: Move with Sign-Extension. +// +// Forms: +// +// MOVWLSX m16 r32 +// MOVWLSX r16 r32 +// Construct and append a MOVWLSX instruction to the active function. +// Operates on the global context. +func MOVWLSX(mr, r operand.Op) { ctx.MOVWLSX(mr, r) } + +// MOVWLZX: Move with Zero-Extend. +// +// Forms: +// +// MOVWLZX m16 r32 +// MOVWLZX r16 r32 +// Construct and append a MOVWLZX instruction to the active function. +func (c *Context) MOVWLZX(mr, r operand.Op) { + c.addinstruction(x86.MOVWLZX(mr, r)) +} + +// MOVWLZX: Move with Zero-Extend. +// +// Forms: +// +// MOVWLZX m16 r32 +// MOVWLZX r16 r32 +// Construct and append a MOVWLZX instruction to the active function. +// Operates on the global context. +func MOVWLZX(mr, r operand.Op) { ctx.MOVWLZX(mr, r) } + +// MOVWQSX: Move with Sign-Extension. +// +// Forms: +// +// MOVWQSX m16 r64 +// MOVWQSX r16 r64 +// Construct and append a MOVWQSX instruction to the active function. +func (c *Context) MOVWQSX(mr, r operand.Op) { + c.addinstruction(x86.MOVWQSX(mr, r)) +} + +// MOVWQSX: Move with Sign-Extension. +// +// Forms: +// +// MOVWQSX m16 r64 +// MOVWQSX r16 r64 +// Construct and append a MOVWQSX instruction to the active function. +// Operates on the global context. +func MOVWQSX(mr, r operand.Op) { ctx.MOVWQSX(mr, r) } + +// MOVWQZX: Move with Zero-Extend. +// +// Forms: +// +// MOVWQZX m16 r64 +// MOVWQZX r16 r64 +// Construct and append a MOVWQZX instruction to the active function. func (c *Context) MOVWQZX(mr, r operand.Op) { - if inst, err := x86.MOVWQZX(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.MOVWQZX(mr, r)) +} + +// MOVWQZX: Move with Zero-Extend. +// +// Forms: +// +// MOVWQZX m16 r64 +// MOVWQZX r16 r64 +// Construct and append a MOVWQZX instruction to the active function. +// Operates on the global context. +func MOVWQZX(mr, r operand.Op) { ctx.MOVWQZX(mr, r) } + +// MPSADBW: Compute Multiple Packed Sums of Absolute Difference. +// +// Forms: +// +// MPSADBW imm8 m128 xmm +// MPSADBW imm8 xmm xmm +// Construct and append a MPSADBW instruction to the active function. +func (c *Context) MPSADBW(i, mx, x operand.Op) { + c.addinstruction(x86.MPSADBW(i, mx, x)) +} + +// MPSADBW: Compute Multiple Packed Sums of Absolute Difference. +// +// Forms: +// +// MPSADBW imm8 m128 xmm +// MPSADBW imm8 xmm xmm +// Construct and append a MPSADBW instruction to the active function. +// Operates on the global context. +func MPSADBW(i, mx, x operand.Op) { ctx.MPSADBW(i, mx, x) } + +// MULB: Unsigned Multiply. +// +// Forms: +// +// MULB m8 +// MULB r8 +// Construct and append a MULB instruction to the active function. +func (c *Context) MULB(mr operand.Op) { + c.addinstruction(x86.MULB(mr)) +} + +// MULB: Unsigned Multiply. +// +// Forms: +// +// MULB m8 +// MULB r8 +// Construct and append a MULB instruction to the active function. +// Operates on the global context. +func MULB(mr operand.Op) { ctx.MULB(mr) } + +// MULL: Unsigned Multiply. +// +// Forms: +// +// MULL m32 +// MULL r32 +// Construct and append a MULL instruction to the active function. +func (c *Context) MULL(mr operand.Op) { + c.addinstruction(x86.MULL(mr)) +} + +// MULL: Unsigned Multiply. +// +// Forms: +// +// MULL m32 +// MULL r32 +// Construct and append a MULL instruction to the active function. +// Operates on the global context. +func MULL(mr operand.Op) { ctx.MULL(mr) } + +// MULPD: Multiply Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// MULPD m128 xmm +// MULPD xmm xmm +// Construct and append a MULPD instruction to the active function. +func (c *Context) MULPD(mx, x operand.Op) { + c.addinstruction(x86.MULPD(mx, x)) +} + +// MULPD: Multiply Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// MULPD m128 xmm +// MULPD xmm xmm +// Construct and append a MULPD instruction to the active function. +// Operates on the global context. +func MULPD(mx, x operand.Op) { ctx.MULPD(mx, x) } + +// MULPS: Multiply Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// MULPS m128 xmm +// MULPS xmm xmm +// Construct and append a MULPS instruction to the active function. +func (c *Context) MULPS(mx, x operand.Op) { + c.addinstruction(x86.MULPS(mx, x)) +} + +// MULPS: Multiply Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// MULPS m128 xmm +// MULPS xmm xmm +// Construct and append a MULPS instruction to the active function. +// Operates on the global context. +func MULPS(mx, x operand.Op) { ctx.MULPS(mx, x) } + +// MULQ: Unsigned Multiply. +// +// Forms: +// +// MULQ m64 +// MULQ r64 +// Construct and append a MULQ instruction to the active function. +func (c *Context) MULQ(mr operand.Op) { + c.addinstruction(x86.MULQ(mr)) +} + +// MULQ: Unsigned Multiply. +// +// Forms: +// +// MULQ m64 +// MULQ r64 +// Construct and append a MULQ instruction to the active function. +// Operates on the global context. +func MULQ(mr operand.Op) { ctx.MULQ(mr) } + +// MULSD: Multiply Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// MULSD m64 xmm +// MULSD xmm xmm +// Construct and append a MULSD instruction to the active function. +func (c *Context) MULSD(mx, x operand.Op) { + c.addinstruction(x86.MULSD(mx, x)) +} + +// MULSD: Multiply Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// MULSD m64 xmm +// MULSD xmm xmm +// Construct and append a MULSD instruction to the active function. +// Operates on the global context. +func MULSD(mx, x operand.Op) { ctx.MULSD(mx, x) } + +// MULSS: Multiply Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// MULSS m32 xmm +// MULSS xmm xmm +// Construct and append a MULSS instruction to the active function. +func (c *Context) MULSS(mx, x operand.Op) { + c.addinstruction(x86.MULSS(mx, x)) +} + +// MULSS: Multiply Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// MULSS m32 xmm +// MULSS xmm xmm +// Construct and append a MULSS instruction to the active function. +// Operates on the global context. +func MULSS(mx, x operand.Op) { ctx.MULSS(mx, x) } + +// MULW: Unsigned Multiply. +// +// Forms: +// +// MULW m16 +// MULW r16 +// Construct and append a MULW instruction to the active function. +func (c *Context) MULW(mr operand.Op) { + c.addinstruction(x86.MULW(mr)) +} + +// MULW: Unsigned Multiply. +// +// Forms: +// +// MULW m16 +// MULW r16 +// Construct and append a MULW instruction to the active function. +// Operates on the global context. +func MULW(mr operand.Op) { ctx.MULW(mr) } + +// MULXL: Unsigned Multiply Without Affecting Flags. +// +// Forms: +// +// MULXL m32 r32 r32 +// MULXL r32 r32 r32 +// Construct and append a MULXL instruction to the active function. +func (c *Context) MULXL(mr, r, r1 operand.Op) { + c.addinstruction(x86.MULXL(mr, r, r1)) +} + +// MULXL: Unsigned Multiply Without Affecting Flags. +// +// Forms: +// +// MULXL m32 r32 r32 +// MULXL r32 r32 r32 +// Construct and append a MULXL instruction to the active function. +// Operates on the global context. +func MULXL(mr, r, r1 operand.Op) { ctx.MULXL(mr, r, r1) } + +// MULXQ: Unsigned Multiply Without Affecting Flags. +// +// Forms: +// +// MULXQ m64 r64 r64 +// MULXQ r64 r64 r64 +// Construct and append a MULXQ instruction to the active function. +func (c *Context) MULXQ(mr, r, r1 operand.Op) { + c.addinstruction(x86.MULXQ(mr, r, r1)) +} + +// MULXQ: Unsigned Multiply Without Affecting Flags. +// +// Forms: +// +// MULXQ m64 r64 r64 +// MULXQ r64 r64 r64 +// Construct and append a MULXQ instruction to the active function. +// Operates on the global context. +func MULXQ(mr, r, r1 operand.Op) { ctx.MULXQ(mr, r, r1) } + +// MWAIT: Monitor Wait. +// +// Forms: +// +// MWAIT +// Construct and append a MWAIT instruction to the active function. +func (c *Context) MWAIT() { + c.addinstruction(x86.MWAIT()) +} + +// MWAIT: Monitor Wait. +// +// Forms: +// +// MWAIT +// Construct and append a MWAIT instruction to the active function. +// Operates on the global context. +func MWAIT() { ctx.MWAIT() } + +// NEGB: Two's Complement Negation. +// +// Forms: +// +// NEGB m8 +// NEGB r8 +// Construct and append a NEGB instruction to the active function. +func (c *Context) NEGB(mr operand.Op) { + c.addinstruction(x86.NEGB(mr)) +} + +// NEGB: Two's Complement Negation. +// +// Forms: +// +// NEGB m8 +// NEGB r8 +// Construct and append a NEGB instruction to the active function. +// Operates on the global context. +func NEGB(mr operand.Op) { ctx.NEGB(mr) } + +// NEGL: Two's Complement Negation. +// +// Forms: +// +// NEGL m32 +// NEGL r32 +// Construct and append a NEGL instruction to the active function. +func (c *Context) NEGL(mr operand.Op) { + c.addinstruction(x86.NEGL(mr)) +} + +// NEGL: Two's Complement Negation. +// +// Forms: +// +// NEGL m32 +// NEGL r32 +// Construct and append a NEGL instruction to the active function. +// Operates on the global context. +func NEGL(mr operand.Op) { ctx.NEGL(mr) } + +// NEGQ: Two's Complement Negation. +// +// Forms: +// +// NEGQ m64 +// NEGQ r64 +// Construct and append a NEGQ instruction to the active function. +func (c *Context) NEGQ(mr operand.Op) { + c.addinstruction(x86.NEGQ(mr)) +} + +// NEGQ: Two's Complement Negation. +// +// Forms: +// +// NEGQ m64 +// NEGQ r64 +// Construct and append a NEGQ instruction to the active function. +// Operates on the global context. +func NEGQ(mr operand.Op) { ctx.NEGQ(mr) } + +// NEGW: Two's Complement Negation. +// +// Forms: +// +// NEGW m16 +// NEGW r16 +// Construct and append a NEGW instruction to the active function. +func (c *Context) NEGW(mr operand.Op) { + c.addinstruction(x86.NEGW(mr)) +} + +// NEGW: Two's Complement Negation. +// +// Forms: +// +// NEGW m16 +// NEGW r16 +// Construct and append a NEGW instruction to the active function. +// Operates on the global context. +func NEGW(mr operand.Op) { ctx.NEGW(mr) } + +// NOP: No Operation. +// +// Forms: +// +// NOP +// Construct and append a NOP instruction to the active function. +func (c *Context) NOP() { + c.addinstruction(x86.NOP()) +} + +// NOP: No Operation. +// +// Forms: +// +// NOP +// Construct and append a NOP instruction to the active function. +// Operates on the global context. +func NOP() { ctx.NOP() } + +// NOTB: One's Complement Negation. +// +// Forms: +// +// NOTB m8 +// NOTB r8 +// Construct and append a NOTB instruction to the active function. +func (c *Context) NOTB(mr operand.Op) { + c.addinstruction(x86.NOTB(mr)) +} + +// NOTB: One's Complement Negation. +// +// Forms: +// +// NOTB m8 +// NOTB r8 +// Construct and append a NOTB instruction to the active function. +// Operates on the global context. +func NOTB(mr operand.Op) { ctx.NOTB(mr) } + +// NOTL: One's Complement Negation. +// +// Forms: +// +// NOTL m32 +// NOTL r32 +// Construct and append a NOTL instruction to the active function. +func (c *Context) NOTL(mr operand.Op) { + c.addinstruction(x86.NOTL(mr)) +} + +// NOTL: One's Complement Negation. +// +// Forms: +// +// NOTL m32 +// NOTL r32 +// Construct and append a NOTL instruction to the active function. +// Operates on the global context. +func NOTL(mr operand.Op) { ctx.NOTL(mr) } + +// NOTQ: One's Complement Negation. +// +// Forms: +// +// NOTQ m64 +// NOTQ r64 +// Construct and append a NOTQ instruction to the active function. +func (c *Context) NOTQ(mr operand.Op) { + c.addinstruction(x86.NOTQ(mr)) +} + +// NOTQ: One's Complement Negation. +// +// Forms: +// +// NOTQ m64 +// NOTQ r64 +// Construct and append a NOTQ instruction to the active function. +// Operates on the global context. +func NOTQ(mr operand.Op) { ctx.NOTQ(mr) } + +// NOTW: One's Complement Negation. +// +// Forms: +// +// NOTW m16 +// NOTW r16 +// Construct and append a NOTW instruction to the active function. +func (c *Context) NOTW(mr operand.Op) { + c.addinstruction(x86.NOTW(mr)) +} + +// NOTW: One's Complement Negation. +// +// Forms: +// +// NOTW m16 +// NOTW r16 +// Construct and append a NOTW instruction to the active function. +// Operates on the global context. +func NOTW(mr operand.Op) { ctx.NOTW(mr) } + +// ORB: Logical Inclusive OR. +// +// Forms: +// +// ORB imm8 al +// ORB imm8 m8 +// ORB imm8 r8 +// ORB m8 r8 +// ORB r8 m8 +// ORB r8 r8 +// Construct and append a ORB instruction to the active function. +func (c *Context) ORB(imr, amr operand.Op) { + c.addinstruction(x86.ORB(imr, amr)) +} + +// ORB: Logical Inclusive OR. +// +// Forms: +// +// ORB imm8 al +// ORB imm8 m8 +// ORB imm8 r8 +// ORB m8 r8 +// ORB r8 m8 +// ORB r8 r8 +// Construct and append a ORB instruction to the active function. +// Operates on the global context. +func ORB(imr, amr operand.Op) { ctx.ORB(imr, amr) } + +// ORL: Logical Inclusive OR. +// +// Forms: +// +// ORL imm32 eax +// ORL imm32 m32 +// ORL imm32 r32 +// ORL imm8 m32 +// ORL imm8 r32 +// ORL m32 r32 +// ORL r32 m32 +// ORL r32 r32 +// Construct and append a ORL instruction to the active function. +func (c *Context) ORL(imr, emr operand.Op) { + c.addinstruction(x86.ORL(imr, emr)) +} + +// ORL: Logical Inclusive OR. +// +// Forms: +// +// ORL imm32 eax +// ORL imm32 m32 +// ORL imm32 r32 +// ORL imm8 m32 +// ORL imm8 r32 +// ORL m32 r32 +// ORL r32 m32 +// ORL r32 r32 +// Construct and append a ORL instruction to the active function. +// Operates on the global context. +func ORL(imr, emr operand.Op) { ctx.ORL(imr, emr) } + +// ORPD: Bitwise Logical OR of Double-Precision Floating-Point Values. +// +// Forms: +// +// ORPD m128 xmm +// ORPD xmm xmm +// Construct and append a ORPD instruction to the active function. +func (c *Context) ORPD(mx, x operand.Op) { + c.addinstruction(x86.ORPD(mx, x)) +} + +// ORPD: Bitwise Logical OR of Double-Precision Floating-Point Values. +// +// Forms: +// +// ORPD m128 xmm +// ORPD xmm xmm +// Construct and append a ORPD instruction to the active function. +// Operates on the global context. +func ORPD(mx, x operand.Op) { ctx.ORPD(mx, x) } + +// ORPS: Bitwise Logical OR of Single-Precision Floating-Point Values. +// +// Forms: +// +// ORPS m128 xmm +// ORPS xmm xmm +// Construct and append a ORPS instruction to the active function. +func (c *Context) ORPS(mx, x operand.Op) { + c.addinstruction(x86.ORPS(mx, x)) +} + +// ORPS: Bitwise Logical OR of Single-Precision Floating-Point Values. +// +// Forms: +// +// ORPS m128 xmm +// ORPS xmm xmm +// Construct and append a ORPS instruction to the active function. +// Operates on the global context. +func ORPS(mx, x operand.Op) { ctx.ORPS(mx, x) } + +// ORQ: Logical Inclusive OR. +// +// Forms: +// +// ORQ imm32 m64 +// ORQ imm32 r64 +// ORQ imm32 rax +// ORQ imm8 m64 +// ORQ imm8 r64 +// ORQ m64 r64 +// ORQ r64 m64 +// ORQ r64 r64 +// Construct and append a ORQ instruction to the active function. +func (c *Context) ORQ(imr, mr operand.Op) { + c.addinstruction(x86.ORQ(imr, mr)) +} + +// ORQ: Logical Inclusive OR. +// +// Forms: +// +// ORQ imm32 m64 +// ORQ imm32 r64 +// ORQ imm32 rax +// ORQ imm8 m64 +// ORQ imm8 r64 +// ORQ m64 r64 +// ORQ r64 m64 +// ORQ r64 r64 +// Construct and append a ORQ instruction to the active function. +// Operates on the global context. +func ORQ(imr, mr operand.Op) { ctx.ORQ(imr, mr) } + +// ORW: Logical Inclusive OR. +// +// Forms: +// +// ORW imm16 ax +// ORW imm16 m16 +// ORW imm16 r16 +// ORW imm8 m16 +// ORW imm8 r16 +// ORW m16 r16 +// ORW r16 m16 +// ORW r16 r16 +// Construct and append a ORW instruction to the active function. +func (c *Context) ORW(imr, amr operand.Op) { + c.addinstruction(x86.ORW(imr, amr)) +} + +// ORW: Logical Inclusive OR. +// +// Forms: +// +// ORW imm16 ax +// ORW imm16 m16 +// ORW imm16 r16 +// ORW imm8 m16 +// ORW imm8 r16 +// ORW m16 r16 +// ORW r16 m16 +// ORW r16 r16 +// Construct and append a ORW instruction to the active function. +// Operates on the global context. +func ORW(imr, amr operand.Op) { ctx.ORW(imr, amr) } + +// PABSB: Packed Absolute Value of Byte Integers. +// +// Forms: +// +// PABSB m128 xmm +// PABSB xmm xmm +// Construct and append a PABSB instruction to the active function. +func (c *Context) PABSB(mx, x operand.Op) { + c.addinstruction(x86.PABSB(mx, x)) +} + +// PABSB: Packed Absolute Value of Byte Integers. +// +// Forms: +// +// PABSB m128 xmm +// PABSB xmm xmm +// Construct and append a PABSB instruction to the active function. +// Operates on the global context. +func PABSB(mx, x operand.Op) { ctx.PABSB(mx, x) } + +// PABSD: Packed Absolute Value of Doubleword Integers. +// +// Forms: +// +// PABSD m128 xmm +// PABSD xmm xmm +// Construct and append a PABSD instruction to the active function. +func (c *Context) PABSD(mx, x operand.Op) { + c.addinstruction(x86.PABSD(mx, x)) +} + +// PABSD: Packed Absolute Value of Doubleword Integers. +// +// Forms: +// +// PABSD m128 xmm +// PABSD xmm xmm +// Construct and append a PABSD instruction to the active function. +// Operates on the global context. +func PABSD(mx, x operand.Op) { ctx.PABSD(mx, x) } + +// PABSW: Packed Absolute Value of Word Integers. +// +// Forms: +// +// PABSW m128 xmm +// PABSW xmm xmm +// Construct and append a PABSW instruction to the active function. +func (c *Context) PABSW(mx, x operand.Op) { + c.addinstruction(x86.PABSW(mx, x)) +} + +// PABSW: Packed Absolute Value of Word Integers. +// +// Forms: +// +// PABSW m128 xmm +// PABSW xmm xmm +// Construct and append a PABSW instruction to the active function. +// Operates on the global context. +func PABSW(mx, x operand.Op) { ctx.PABSW(mx, x) } + +// PACKSSLW: Pack Doublewords into Words with Signed Saturation. +// +// Forms: +// +// PACKSSLW m128 xmm +// PACKSSLW xmm xmm +// Construct and append a PACKSSLW instruction to the active function. +func (c *Context) PACKSSLW(mx, x operand.Op) { + c.addinstruction(x86.PACKSSLW(mx, x)) +} + +// PACKSSLW: Pack Doublewords into Words with Signed Saturation. +// +// Forms: +// +// PACKSSLW m128 xmm +// PACKSSLW xmm xmm +// Construct and append a PACKSSLW instruction to the active function. +// Operates on the global context. +func PACKSSLW(mx, x operand.Op) { ctx.PACKSSLW(mx, x) } + +// PACKSSWB: Pack Words into Bytes with Signed Saturation. +// +// Forms: +// +// PACKSSWB m128 xmm +// PACKSSWB xmm xmm +// Construct and append a PACKSSWB instruction to the active function. +func (c *Context) PACKSSWB(mx, x operand.Op) { + c.addinstruction(x86.PACKSSWB(mx, x)) +} + +// PACKSSWB: Pack Words into Bytes with Signed Saturation. +// +// Forms: +// +// PACKSSWB m128 xmm +// PACKSSWB xmm xmm +// Construct and append a PACKSSWB instruction to the active function. +// Operates on the global context. +func PACKSSWB(mx, x operand.Op) { ctx.PACKSSWB(mx, x) } + +// PACKUSDW: Pack Doublewords into Words with Unsigned Saturation. +// +// Forms: +// +// PACKUSDW m128 xmm +// PACKUSDW xmm xmm +// Construct and append a PACKUSDW instruction to the active function. +func (c *Context) PACKUSDW(mx, x operand.Op) { + c.addinstruction(x86.PACKUSDW(mx, x)) +} + +// PACKUSDW: Pack Doublewords into Words with Unsigned Saturation. +// +// Forms: +// +// PACKUSDW m128 xmm +// PACKUSDW xmm xmm +// Construct and append a PACKUSDW instruction to the active function. +// Operates on the global context. +func PACKUSDW(mx, x operand.Op) { ctx.PACKUSDW(mx, x) } + +// PACKUSWB: Pack Words into Bytes with Unsigned Saturation. +// +// Forms: +// +// PACKUSWB m128 xmm +// PACKUSWB xmm xmm +// Construct and append a PACKUSWB instruction to the active function. +func (c *Context) PACKUSWB(mx, x operand.Op) { + c.addinstruction(x86.PACKUSWB(mx, x)) +} + +// PACKUSWB: Pack Words into Bytes with Unsigned Saturation. +// +// Forms: +// +// PACKUSWB m128 xmm +// PACKUSWB xmm xmm +// Construct and append a PACKUSWB instruction to the active function. +// Operates on the global context. +func PACKUSWB(mx, x operand.Op) { ctx.PACKUSWB(mx, x) } + +// PADDB: Add Packed Byte Integers. +// +// Forms: +// +// PADDB m128 xmm +// PADDB xmm xmm +// Construct and append a PADDB instruction to the active function. +func (c *Context) PADDB(mx, x operand.Op) { + c.addinstruction(x86.PADDB(mx, x)) +} + +// PADDB: Add Packed Byte Integers. +// +// Forms: +// +// PADDB m128 xmm +// PADDB xmm xmm +// Construct and append a PADDB instruction to the active function. +// Operates on the global context. +func PADDB(mx, x operand.Op) { ctx.PADDB(mx, x) } + +// PADDD: Add Packed Doubleword Integers. +// +// Forms: +// +// PADDD m128 xmm +// PADDD xmm xmm +// Construct and append a PADDD instruction to the active function. +func (c *Context) PADDD(mx, x operand.Op) { + c.addinstruction(x86.PADDD(mx, x)) +} + +// PADDD: Add Packed Doubleword Integers. +// +// Forms: +// +// PADDD m128 xmm +// PADDD xmm xmm +// Construct and append a PADDD instruction to the active function. +// Operates on the global context. +func PADDD(mx, x operand.Op) { ctx.PADDD(mx, x) } + +// PADDL: Add Packed Doubleword Integers. +// +// Forms: +// +// PADDL m128 xmm +// PADDL xmm xmm +// Construct and append a PADDL instruction to the active function. +func (c *Context) PADDL(mx, x operand.Op) { + c.addinstruction(x86.PADDL(mx, x)) +} + +// PADDL: Add Packed Doubleword Integers. +// +// Forms: +// +// PADDL m128 xmm +// PADDL xmm xmm +// Construct and append a PADDL instruction to the active function. +// Operates on the global context. +func PADDL(mx, x operand.Op) { ctx.PADDL(mx, x) } + +// PADDQ: Add Packed Quadword Integers. +// +// Forms: +// +// PADDQ m128 xmm +// PADDQ xmm xmm +// Construct and append a PADDQ instruction to the active function. +func (c *Context) PADDQ(mx, x operand.Op) { + c.addinstruction(x86.PADDQ(mx, x)) +} + +// PADDQ: Add Packed Quadword Integers. +// +// Forms: +// +// PADDQ m128 xmm +// PADDQ xmm xmm +// Construct and append a PADDQ instruction to the active function. +// Operates on the global context. +func PADDQ(mx, x operand.Op) { ctx.PADDQ(mx, x) } + +// PADDSB: Add Packed Signed Byte Integers with Signed Saturation. +// +// Forms: +// +// PADDSB m128 xmm +// PADDSB xmm xmm +// Construct and append a PADDSB instruction to the active function. +func (c *Context) PADDSB(mx, x operand.Op) { + c.addinstruction(x86.PADDSB(mx, x)) +} + +// PADDSB: Add Packed Signed Byte Integers with Signed Saturation. +// +// Forms: +// +// PADDSB m128 xmm +// PADDSB xmm xmm +// Construct and append a PADDSB instruction to the active function. +// Operates on the global context. +func PADDSB(mx, x operand.Op) { ctx.PADDSB(mx, x) } + +// PADDSW: Add Packed Signed Word Integers with Signed Saturation. +// +// Forms: +// +// PADDSW m128 xmm +// PADDSW xmm xmm +// Construct and append a PADDSW instruction to the active function. +func (c *Context) PADDSW(mx, x operand.Op) { + c.addinstruction(x86.PADDSW(mx, x)) +} + +// PADDSW: Add Packed Signed Word Integers with Signed Saturation. +// +// Forms: +// +// PADDSW m128 xmm +// PADDSW xmm xmm +// Construct and append a PADDSW instruction to the active function. +// Operates on the global context. +func PADDSW(mx, x operand.Op) { ctx.PADDSW(mx, x) } + +// PADDUSB: Add Packed Unsigned Byte Integers with Unsigned Saturation. +// +// Forms: +// +// PADDUSB m128 xmm +// PADDUSB xmm xmm +// Construct and append a PADDUSB instruction to the active function. +func (c *Context) PADDUSB(mx, x operand.Op) { + c.addinstruction(x86.PADDUSB(mx, x)) +} + +// PADDUSB: Add Packed Unsigned Byte Integers with Unsigned Saturation. +// +// Forms: +// +// PADDUSB m128 xmm +// PADDUSB xmm xmm +// Construct and append a PADDUSB instruction to the active function. +// Operates on the global context. +func PADDUSB(mx, x operand.Op) { ctx.PADDUSB(mx, x) } + +// PADDUSW: Add Packed Unsigned Word Integers with Unsigned Saturation. +// +// Forms: +// +// PADDUSW m128 xmm +// PADDUSW xmm xmm +// Construct and append a PADDUSW instruction to the active function. +func (c *Context) PADDUSW(mx, x operand.Op) { + c.addinstruction(x86.PADDUSW(mx, x)) +} + +// PADDUSW: Add Packed Unsigned Word Integers with Unsigned Saturation. +// +// Forms: +// +// PADDUSW m128 xmm +// PADDUSW xmm xmm +// Construct and append a PADDUSW instruction to the active function. +// Operates on the global context. +func PADDUSW(mx, x operand.Op) { ctx.PADDUSW(mx, x) } + +// PADDW: Add Packed Word Integers. +// +// Forms: +// +// PADDW m128 xmm +// PADDW xmm xmm +// Construct and append a PADDW instruction to the active function. +func (c *Context) PADDW(mx, x operand.Op) { + c.addinstruction(x86.PADDW(mx, x)) +} + +// PADDW: Add Packed Word Integers. +// +// Forms: +// +// PADDW m128 xmm +// PADDW xmm xmm +// Construct and append a PADDW instruction to the active function. +// Operates on the global context. +func PADDW(mx, x operand.Op) { ctx.PADDW(mx, x) } + +// PALIGNR: Packed Align Right. +// +// Forms: +// +// PALIGNR imm8 m128 xmm +// PALIGNR imm8 xmm xmm +// Construct and append a PALIGNR instruction to the active function. +func (c *Context) PALIGNR(i, mx, x operand.Op) { + c.addinstruction(x86.PALIGNR(i, mx, x)) +} + +// PALIGNR: Packed Align Right. +// +// Forms: +// +// PALIGNR imm8 m128 xmm +// PALIGNR imm8 xmm xmm +// Construct and append a PALIGNR instruction to the active function. +// Operates on the global context. +func PALIGNR(i, mx, x operand.Op) { ctx.PALIGNR(i, mx, x) } + +// PAND: Packed Bitwise Logical AND. +// +// Forms: +// +// PAND m128 xmm +// PAND xmm xmm +// Construct and append a PAND instruction to the active function. +func (c *Context) PAND(mx, x operand.Op) { + c.addinstruction(x86.PAND(mx, x)) +} + +// PAND: Packed Bitwise Logical AND. +// +// Forms: +// +// PAND m128 xmm +// PAND xmm xmm +// Construct and append a PAND instruction to the active function. +// Operates on the global context. +func PAND(mx, x operand.Op) { ctx.PAND(mx, x) } + +// PANDN: Packed Bitwise Logical AND NOT. +// +// Forms: +// +// PANDN m128 xmm +// PANDN xmm xmm +// Construct and append a PANDN instruction to the active function. +func (c *Context) PANDN(mx, x operand.Op) { + c.addinstruction(x86.PANDN(mx, x)) +} + +// PANDN: Packed Bitwise Logical AND NOT. +// +// Forms: +// +// PANDN m128 xmm +// PANDN xmm xmm +// Construct and append a PANDN instruction to the active function. +// Operates on the global context. +func PANDN(mx, x operand.Op) { ctx.PANDN(mx, x) } + +// PAUSE: Spin Loop Hint. +// +// Forms: +// +// PAUSE +// Construct and append a PAUSE instruction to the active function. +func (c *Context) PAUSE() { + c.addinstruction(x86.PAUSE()) +} + +// PAUSE: Spin Loop Hint. +// +// Forms: +// +// PAUSE +// Construct and append a PAUSE instruction to the active function. +// Operates on the global context. +func PAUSE() { ctx.PAUSE() } + +// PAVGB: Average Packed Byte Integers. +// +// Forms: +// +// PAVGB m128 xmm +// PAVGB xmm xmm +// Construct and append a PAVGB instruction to the active function. +func (c *Context) PAVGB(mx, x operand.Op) { + c.addinstruction(x86.PAVGB(mx, x)) +} + +// PAVGB: Average Packed Byte Integers. +// +// Forms: +// +// PAVGB m128 xmm +// PAVGB xmm xmm +// Construct and append a PAVGB instruction to the active function. +// Operates on the global context. +func PAVGB(mx, x operand.Op) { ctx.PAVGB(mx, x) } + +// PAVGW: Average Packed Word Integers. +// +// Forms: +// +// PAVGW m128 xmm +// PAVGW xmm xmm +// Construct and append a PAVGW instruction to the active function. +func (c *Context) PAVGW(mx, x operand.Op) { + c.addinstruction(x86.PAVGW(mx, x)) +} + +// PAVGW: Average Packed Word Integers. +// +// Forms: +// +// PAVGW m128 xmm +// PAVGW xmm xmm +// Construct and append a PAVGW instruction to the active function. +// Operates on the global context. +func PAVGW(mx, x operand.Op) { ctx.PAVGW(mx, x) } + +// PBLENDVB: Variable Blend Packed Bytes. +// +// Forms: +// +// PBLENDVB xmm0 m128 xmm +// PBLENDVB xmm0 xmm xmm +// Construct and append a PBLENDVB instruction to the active function. +func (c *Context) PBLENDVB(x, mx, x1 operand.Op) { + c.addinstruction(x86.PBLENDVB(x, mx, x1)) +} + +// PBLENDVB: Variable Blend Packed Bytes. +// +// Forms: +// +// PBLENDVB xmm0 m128 xmm +// PBLENDVB xmm0 xmm xmm +// Construct and append a PBLENDVB instruction to the active function. +// Operates on the global context. +func PBLENDVB(x, mx, x1 operand.Op) { ctx.PBLENDVB(x, mx, x1) } + +// PBLENDW: Blend Packed Words. +// +// Forms: +// +// PBLENDW imm8 m128 xmm +// PBLENDW imm8 xmm xmm +// Construct and append a PBLENDW instruction to the active function. +func (c *Context) PBLENDW(i, mx, x operand.Op) { + c.addinstruction(x86.PBLENDW(i, mx, x)) +} + +// PBLENDW: Blend Packed Words. +// +// Forms: +// +// PBLENDW imm8 m128 xmm +// PBLENDW imm8 xmm xmm +// Construct and append a PBLENDW instruction to the active function. +// Operates on the global context. +func PBLENDW(i, mx, x operand.Op) { ctx.PBLENDW(i, mx, x) } + +// PCLMULQDQ: Carry-Less Quadword Multiplication. +// +// Forms: +// +// PCLMULQDQ imm8 m128 xmm +// PCLMULQDQ imm8 xmm xmm +// Construct and append a PCLMULQDQ instruction to the active function. +func (c *Context) PCLMULQDQ(i, mx, x operand.Op) { + c.addinstruction(x86.PCLMULQDQ(i, mx, x)) +} + +// PCLMULQDQ: Carry-Less Quadword Multiplication. +// +// Forms: +// +// PCLMULQDQ imm8 m128 xmm +// PCLMULQDQ imm8 xmm xmm +// Construct and append a PCLMULQDQ instruction to the active function. +// Operates on the global context. +func PCLMULQDQ(i, mx, x operand.Op) { ctx.PCLMULQDQ(i, mx, x) } + +// PCMPEQB: Compare Packed Byte Data for Equality. +// +// Forms: +// +// PCMPEQB m128 xmm +// PCMPEQB xmm xmm +// Construct and append a PCMPEQB instruction to the active function. +func (c *Context) PCMPEQB(mx, x operand.Op) { + c.addinstruction(x86.PCMPEQB(mx, x)) +} + +// PCMPEQB: Compare Packed Byte Data for Equality. +// +// Forms: +// +// PCMPEQB m128 xmm +// PCMPEQB xmm xmm +// Construct and append a PCMPEQB instruction to the active function. +// Operates on the global context. +func PCMPEQB(mx, x operand.Op) { ctx.PCMPEQB(mx, x) } + +// PCMPEQL: Compare Packed Doubleword Data for Equality. +// +// Forms: +// +// PCMPEQL m128 xmm +// PCMPEQL xmm xmm +// Construct and append a PCMPEQL instruction to the active function. +func (c *Context) PCMPEQL(mx, x operand.Op) { + c.addinstruction(x86.PCMPEQL(mx, x)) +} + +// PCMPEQL: Compare Packed Doubleword Data for Equality. +// +// Forms: +// +// PCMPEQL m128 xmm +// PCMPEQL xmm xmm +// Construct and append a PCMPEQL instruction to the active function. +// Operates on the global context. +func PCMPEQL(mx, x operand.Op) { ctx.PCMPEQL(mx, x) } + +// PCMPEQQ: Compare Packed Quadword Data for Equality. +// +// Forms: +// +// PCMPEQQ m128 xmm +// PCMPEQQ xmm xmm +// Construct and append a PCMPEQQ instruction to the active function. +func (c *Context) PCMPEQQ(mx, x operand.Op) { + c.addinstruction(x86.PCMPEQQ(mx, x)) +} + +// PCMPEQQ: Compare Packed Quadword Data for Equality. +// +// Forms: +// +// PCMPEQQ m128 xmm +// PCMPEQQ xmm xmm +// Construct and append a PCMPEQQ instruction to the active function. +// Operates on the global context. +func PCMPEQQ(mx, x operand.Op) { ctx.PCMPEQQ(mx, x) } + +// PCMPEQW: Compare Packed Word Data for Equality. +// +// Forms: +// +// PCMPEQW m128 xmm +// PCMPEQW xmm xmm +// Construct and append a PCMPEQW instruction to the active function. +func (c *Context) PCMPEQW(mx, x operand.Op) { + c.addinstruction(x86.PCMPEQW(mx, x)) +} + +// PCMPEQW: Compare Packed Word Data for Equality. +// +// Forms: +// +// PCMPEQW m128 xmm +// PCMPEQW xmm xmm +// Construct and append a PCMPEQW instruction to the active function. +// Operates on the global context. +func PCMPEQW(mx, x operand.Op) { ctx.PCMPEQW(mx, x) } + +// PCMPESTRI: Packed Compare Explicit Length Strings, Return Index. +// +// Forms: +// +// PCMPESTRI imm8 m128 xmm +// PCMPESTRI imm8 xmm xmm +// Construct and append a PCMPESTRI instruction to the active function. +func (c *Context) PCMPESTRI(i, mx, x operand.Op) { + c.addinstruction(x86.PCMPESTRI(i, mx, x)) +} + +// PCMPESTRI: Packed Compare Explicit Length Strings, Return Index. +// +// Forms: +// +// PCMPESTRI imm8 m128 xmm +// PCMPESTRI imm8 xmm xmm +// Construct and append a PCMPESTRI instruction to the active function. +// Operates on the global context. +func PCMPESTRI(i, mx, x operand.Op) { ctx.PCMPESTRI(i, mx, x) } + +// PCMPESTRM: Packed Compare Explicit Length Strings, Return Mask. +// +// Forms: +// +// PCMPESTRM imm8 m128 xmm +// PCMPESTRM imm8 xmm xmm +// Construct and append a PCMPESTRM instruction to the active function. +func (c *Context) PCMPESTRM(i, mx, x operand.Op) { + c.addinstruction(x86.PCMPESTRM(i, mx, x)) +} + +// PCMPESTRM: Packed Compare Explicit Length Strings, Return Mask. +// +// Forms: +// +// PCMPESTRM imm8 m128 xmm +// PCMPESTRM imm8 xmm xmm +// Construct and append a PCMPESTRM instruction to the active function. +// Operates on the global context. +func PCMPESTRM(i, mx, x operand.Op) { ctx.PCMPESTRM(i, mx, x) } + +// PCMPGTB: Compare Packed Signed Byte Integers for Greater Than. +// +// Forms: +// +// PCMPGTB m128 xmm +// PCMPGTB xmm xmm +// Construct and append a PCMPGTB instruction to the active function. +func (c *Context) PCMPGTB(mx, x operand.Op) { + c.addinstruction(x86.PCMPGTB(mx, x)) +} + +// PCMPGTB: Compare Packed Signed Byte Integers for Greater Than. +// +// Forms: +// +// PCMPGTB m128 xmm +// PCMPGTB xmm xmm +// Construct and append a PCMPGTB instruction to the active function. +// Operates on the global context. +func PCMPGTB(mx, x operand.Op) { ctx.PCMPGTB(mx, x) } + +// PCMPGTL: Compare Packed Signed Doubleword Integers for Greater Than. +// +// Forms: +// +// PCMPGTL m128 xmm +// PCMPGTL xmm xmm +// Construct and append a PCMPGTL instruction to the active function. +func (c *Context) PCMPGTL(mx, x operand.Op) { + c.addinstruction(x86.PCMPGTL(mx, x)) +} + +// PCMPGTL: Compare Packed Signed Doubleword Integers for Greater Than. +// +// Forms: +// +// PCMPGTL m128 xmm +// PCMPGTL xmm xmm +// Construct and append a PCMPGTL instruction to the active function. +// Operates on the global context. +func PCMPGTL(mx, x operand.Op) { ctx.PCMPGTL(mx, x) } + +// PCMPGTQ: Compare Packed Data for Greater Than. +// +// Forms: +// +// PCMPGTQ m128 xmm +// PCMPGTQ xmm xmm +// Construct and append a PCMPGTQ instruction to the active function. +func (c *Context) PCMPGTQ(mx, x operand.Op) { + c.addinstruction(x86.PCMPGTQ(mx, x)) +} + +// PCMPGTQ: Compare Packed Data for Greater Than. +// +// Forms: +// +// PCMPGTQ m128 xmm +// PCMPGTQ xmm xmm +// Construct and append a PCMPGTQ instruction to the active function. +// Operates on the global context. +func PCMPGTQ(mx, x operand.Op) { ctx.PCMPGTQ(mx, x) } + +// PCMPGTW: Compare Packed Signed Word Integers for Greater Than. +// +// Forms: +// +// PCMPGTW m128 xmm +// PCMPGTW xmm xmm +// Construct and append a PCMPGTW instruction to the active function. +func (c *Context) PCMPGTW(mx, x operand.Op) { + c.addinstruction(x86.PCMPGTW(mx, x)) +} + +// PCMPGTW: Compare Packed Signed Word Integers for Greater Than. +// +// Forms: +// +// PCMPGTW m128 xmm +// PCMPGTW xmm xmm +// Construct and append a PCMPGTW instruction to the active function. +// Operates on the global context. +func PCMPGTW(mx, x operand.Op) { ctx.PCMPGTW(mx, x) } + +// PCMPISTRI: Packed Compare Implicit Length Strings, Return Index. +// +// Forms: +// +// PCMPISTRI imm8 m128 xmm +// PCMPISTRI imm8 xmm xmm +// Construct and append a PCMPISTRI instruction to the active function. +func (c *Context) PCMPISTRI(i, mx, x operand.Op) { + c.addinstruction(x86.PCMPISTRI(i, mx, x)) +} + +// PCMPISTRI: Packed Compare Implicit Length Strings, Return Index. +// +// Forms: +// +// PCMPISTRI imm8 m128 xmm +// PCMPISTRI imm8 xmm xmm +// Construct and append a PCMPISTRI instruction to the active function. +// Operates on the global context. +func PCMPISTRI(i, mx, x operand.Op) { ctx.PCMPISTRI(i, mx, x) } + +// PCMPISTRM: Packed Compare Implicit Length Strings, Return Mask. +// +// Forms: +// +// PCMPISTRM imm8 m128 xmm +// PCMPISTRM imm8 xmm xmm +// Construct and append a PCMPISTRM instruction to the active function. +func (c *Context) PCMPISTRM(i, mx, x operand.Op) { + c.addinstruction(x86.PCMPISTRM(i, mx, x)) +} + +// PCMPISTRM: Packed Compare Implicit Length Strings, Return Mask. +// +// Forms: +// +// PCMPISTRM imm8 m128 xmm +// PCMPISTRM imm8 xmm xmm +// Construct and append a PCMPISTRM instruction to the active function. +// Operates on the global context. +func PCMPISTRM(i, mx, x operand.Op) { ctx.PCMPISTRM(i, mx, x) } + +// PDEPL: Parallel Bits Deposit. +// +// Forms: +// +// PDEPL m32 r32 r32 +// PDEPL r32 r32 r32 +// Construct and append a PDEPL instruction to the active function. +func (c *Context) PDEPL(mr, r, r1 operand.Op) { + c.addinstruction(x86.PDEPL(mr, r, r1)) +} + +// PDEPL: Parallel Bits Deposit. +// +// Forms: +// +// PDEPL m32 r32 r32 +// PDEPL r32 r32 r32 +// Construct and append a PDEPL instruction to the active function. +// Operates on the global context. +func PDEPL(mr, r, r1 operand.Op) { ctx.PDEPL(mr, r, r1) } + +// PDEPQ: Parallel Bits Deposit. +// +// Forms: +// +// PDEPQ m64 r64 r64 +// PDEPQ r64 r64 r64 +// Construct and append a PDEPQ instruction to the active function. +func (c *Context) PDEPQ(mr, r, r1 operand.Op) { + c.addinstruction(x86.PDEPQ(mr, r, r1)) +} + +// PDEPQ: Parallel Bits Deposit. +// +// Forms: +// +// PDEPQ m64 r64 r64 +// PDEPQ r64 r64 r64 +// Construct and append a PDEPQ instruction to the active function. +// Operates on the global context. +func PDEPQ(mr, r, r1 operand.Op) { ctx.PDEPQ(mr, r, r1) } + +// PEXTL: Parallel Bits Extract. +// +// Forms: +// +// PEXTL m32 r32 r32 +// PEXTL r32 r32 r32 +// Construct and append a PEXTL instruction to the active function. +func (c *Context) PEXTL(mr, r, r1 operand.Op) { + c.addinstruction(x86.PEXTL(mr, r, r1)) +} + +// PEXTL: Parallel Bits Extract. +// +// Forms: +// +// PEXTL m32 r32 r32 +// PEXTL r32 r32 r32 +// Construct and append a PEXTL instruction to the active function. +// Operates on the global context. +func PEXTL(mr, r, r1 operand.Op) { ctx.PEXTL(mr, r, r1) } + +// PEXTQ: Parallel Bits Extract. +// +// Forms: +// +// PEXTQ m64 r64 r64 +// PEXTQ r64 r64 r64 +// Construct and append a PEXTQ instruction to the active function. +func (c *Context) PEXTQ(mr, r, r1 operand.Op) { + c.addinstruction(x86.PEXTQ(mr, r, r1)) +} + +// PEXTQ: Parallel Bits Extract. +// +// Forms: +// +// PEXTQ m64 r64 r64 +// PEXTQ r64 r64 r64 +// Construct and append a PEXTQ instruction to the active function. +// Operates on the global context. +func PEXTQ(mr, r, r1 operand.Op) { ctx.PEXTQ(mr, r, r1) } + +// PEXTRB: Extract Byte. +// +// Forms: +// +// PEXTRB imm8 xmm m8 +// PEXTRB imm8 xmm r32 +// Construct and append a PEXTRB instruction to the active function. +func (c *Context) PEXTRB(i, x, mr operand.Op) { + c.addinstruction(x86.PEXTRB(i, x, mr)) +} + +// PEXTRB: Extract Byte. +// +// Forms: +// +// PEXTRB imm8 xmm m8 +// PEXTRB imm8 xmm r32 +// Construct and append a PEXTRB instruction to the active function. +// Operates on the global context. +func PEXTRB(i, x, mr operand.Op) { ctx.PEXTRB(i, x, mr) } + +// PEXTRD: Extract Doubleword. +// +// Forms: +// +// PEXTRD imm8 xmm m32 +// PEXTRD imm8 xmm r32 +// Construct and append a PEXTRD instruction to the active function. +func (c *Context) PEXTRD(i, x, mr operand.Op) { + c.addinstruction(x86.PEXTRD(i, x, mr)) +} + +// PEXTRD: Extract Doubleword. +// +// Forms: +// +// PEXTRD imm8 xmm m32 +// PEXTRD imm8 xmm r32 +// Construct and append a PEXTRD instruction to the active function. +// Operates on the global context. +func PEXTRD(i, x, mr operand.Op) { ctx.PEXTRD(i, x, mr) } + +// PEXTRQ: Extract Quadword. +// +// Forms: +// +// PEXTRQ imm8 xmm m64 +// PEXTRQ imm8 xmm r64 +// Construct and append a PEXTRQ instruction to the active function. +func (c *Context) PEXTRQ(i, x, mr operand.Op) { + c.addinstruction(x86.PEXTRQ(i, x, mr)) +} + +// PEXTRQ: Extract Quadword. +// +// Forms: +// +// PEXTRQ imm8 xmm m64 +// PEXTRQ imm8 xmm r64 +// Construct and append a PEXTRQ instruction to the active function. +// Operates on the global context. +func PEXTRQ(i, x, mr operand.Op) { ctx.PEXTRQ(i, x, mr) } + +// PEXTRW: Extract Word. +// +// Forms: +// +// PEXTRW imm8 xmm m16 +// PEXTRW imm8 xmm r32 +// Construct and append a PEXTRW instruction to the active function. +func (c *Context) PEXTRW(i, x, mr operand.Op) { + c.addinstruction(x86.PEXTRW(i, x, mr)) +} + +// PEXTRW: Extract Word. +// +// Forms: +// +// PEXTRW imm8 xmm m16 +// PEXTRW imm8 xmm r32 +// Construct and append a PEXTRW instruction to the active function. +// Operates on the global context. +func PEXTRW(i, x, mr operand.Op) { ctx.PEXTRW(i, x, mr) } + +// PHADDD: Packed Horizontal Add Doubleword Integer. +// +// Forms: +// +// PHADDD m128 xmm +// PHADDD xmm xmm +// Construct and append a PHADDD instruction to the active function. +func (c *Context) PHADDD(mx, x operand.Op) { + c.addinstruction(x86.PHADDD(mx, x)) +} + +// PHADDD: Packed Horizontal Add Doubleword Integer. +// +// Forms: +// +// PHADDD m128 xmm +// PHADDD xmm xmm +// Construct and append a PHADDD instruction to the active function. +// Operates on the global context. +func PHADDD(mx, x operand.Op) { ctx.PHADDD(mx, x) } + +// PHADDSW: Packed Horizontal Add Signed Word Integers with Signed Saturation. +// +// Forms: +// +// PHADDSW m128 xmm +// PHADDSW xmm xmm +// Construct and append a PHADDSW instruction to the active function. +func (c *Context) PHADDSW(mx, x operand.Op) { + c.addinstruction(x86.PHADDSW(mx, x)) +} + +// PHADDSW: Packed Horizontal Add Signed Word Integers with Signed Saturation. +// +// Forms: +// +// PHADDSW m128 xmm +// PHADDSW xmm xmm +// Construct and append a PHADDSW instruction to the active function. +// Operates on the global context. +func PHADDSW(mx, x operand.Op) { ctx.PHADDSW(mx, x) } + +// PHADDW: Packed Horizontal Add Word Integers. +// +// Forms: +// +// PHADDW m128 xmm +// PHADDW xmm xmm +// Construct and append a PHADDW instruction to the active function. +func (c *Context) PHADDW(mx, x operand.Op) { + c.addinstruction(x86.PHADDW(mx, x)) +} + +// PHADDW: Packed Horizontal Add Word Integers. +// +// Forms: +// +// PHADDW m128 xmm +// PHADDW xmm xmm +// Construct and append a PHADDW instruction to the active function. +// Operates on the global context. +func PHADDW(mx, x operand.Op) { ctx.PHADDW(mx, x) } + +// PHMINPOSUW: Packed Horizontal Minimum of Unsigned Word Integers. +// +// Forms: +// +// PHMINPOSUW m128 xmm +// PHMINPOSUW xmm xmm +// Construct and append a PHMINPOSUW instruction to the active function. +func (c *Context) PHMINPOSUW(mx, x operand.Op) { + c.addinstruction(x86.PHMINPOSUW(mx, x)) +} + +// PHMINPOSUW: Packed Horizontal Minimum of Unsigned Word Integers. +// +// Forms: +// +// PHMINPOSUW m128 xmm +// PHMINPOSUW xmm xmm +// Construct and append a PHMINPOSUW instruction to the active function. +// Operates on the global context. +func PHMINPOSUW(mx, x operand.Op) { ctx.PHMINPOSUW(mx, x) } + +// PHSUBD: Packed Horizontal Subtract Doubleword Integers. +// +// Forms: +// +// PHSUBD m128 xmm +// PHSUBD xmm xmm +// Construct and append a PHSUBD instruction to the active function. +func (c *Context) PHSUBD(mx, x operand.Op) { + c.addinstruction(x86.PHSUBD(mx, x)) +} + +// PHSUBD: Packed Horizontal Subtract Doubleword Integers. +// +// Forms: +// +// PHSUBD m128 xmm +// PHSUBD xmm xmm +// Construct and append a PHSUBD instruction to the active function. +// Operates on the global context. +func PHSUBD(mx, x operand.Op) { ctx.PHSUBD(mx, x) } + +// PHSUBSW: Packed Horizontal Subtract Signed Word Integers with Signed Saturation. +// +// Forms: +// +// PHSUBSW m128 xmm +// PHSUBSW xmm xmm +// Construct and append a PHSUBSW instruction to the active function. +func (c *Context) PHSUBSW(mx, x operand.Op) { + c.addinstruction(x86.PHSUBSW(mx, x)) +} + +// PHSUBSW: Packed Horizontal Subtract Signed Word Integers with Signed Saturation. +// +// Forms: +// +// PHSUBSW m128 xmm +// PHSUBSW xmm xmm +// Construct and append a PHSUBSW instruction to the active function. +// Operates on the global context. +func PHSUBSW(mx, x operand.Op) { ctx.PHSUBSW(mx, x) } + +// PHSUBW: Packed Horizontal Subtract Word Integers. +// +// Forms: +// +// PHSUBW m128 xmm +// PHSUBW xmm xmm +// Construct and append a PHSUBW instruction to the active function. +func (c *Context) PHSUBW(mx, x operand.Op) { + c.addinstruction(x86.PHSUBW(mx, x)) +} + +// PHSUBW: Packed Horizontal Subtract Word Integers. +// +// Forms: +// +// PHSUBW m128 xmm +// PHSUBW xmm xmm +// Construct and append a PHSUBW instruction to the active function. +// Operates on the global context. +func PHSUBW(mx, x operand.Op) { ctx.PHSUBW(mx, x) } + +// PINSRB: Insert Byte. +// +// Forms: +// +// PINSRB imm8 m8 xmm +// PINSRB imm8 r32 xmm +// Construct and append a PINSRB instruction to the active function. +func (c *Context) PINSRB(i, mr, x operand.Op) { + c.addinstruction(x86.PINSRB(i, mr, x)) +} + +// PINSRB: Insert Byte. +// +// Forms: +// +// PINSRB imm8 m8 xmm +// PINSRB imm8 r32 xmm +// Construct and append a PINSRB instruction to the active function. +// Operates on the global context. +func PINSRB(i, mr, x operand.Op) { ctx.PINSRB(i, mr, x) } + +// PINSRD: Insert Doubleword. +// +// Forms: +// +// PINSRD imm8 m32 xmm +// PINSRD imm8 r32 xmm +// Construct and append a PINSRD instruction to the active function. +func (c *Context) PINSRD(i, mr, x operand.Op) { + c.addinstruction(x86.PINSRD(i, mr, x)) +} + +// PINSRD: Insert Doubleword. +// +// Forms: +// +// PINSRD imm8 m32 xmm +// PINSRD imm8 r32 xmm +// Construct and append a PINSRD instruction to the active function. +// Operates on the global context. +func PINSRD(i, mr, x operand.Op) { ctx.PINSRD(i, mr, x) } + +// PINSRQ: Insert Quadword. +// +// Forms: +// +// PINSRQ imm8 m64 xmm +// PINSRQ imm8 r64 xmm +// Construct and append a PINSRQ instruction to the active function. +func (c *Context) PINSRQ(i, mr, x operand.Op) { + c.addinstruction(x86.PINSRQ(i, mr, x)) +} + +// PINSRQ: Insert Quadword. +// +// Forms: +// +// PINSRQ imm8 m64 xmm +// PINSRQ imm8 r64 xmm +// Construct and append a PINSRQ instruction to the active function. +// Operates on the global context. +func PINSRQ(i, mr, x operand.Op) { ctx.PINSRQ(i, mr, x) } + +// PINSRW: Insert Word. +// +// Forms: +// +// PINSRW imm8 m16 xmm +// PINSRW imm8 r32 xmm +// Construct and append a PINSRW instruction to the active function. +func (c *Context) PINSRW(i, mr, x operand.Op) { + c.addinstruction(x86.PINSRW(i, mr, x)) +} + +// PINSRW: Insert Word. +// +// Forms: +// +// PINSRW imm8 m16 xmm +// PINSRW imm8 r32 xmm +// Construct and append a PINSRW instruction to the active function. +// Operates on the global context. +func PINSRW(i, mr, x operand.Op) { ctx.PINSRW(i, mr, x) } + +// PMADDUBSW: Multiply and Add Packed Signed and Unsigned Byte Integers. +// +// Forms: +// +// PMADDUBSW m128 xmm +// PMADDUBSW xmm xmm +// Construct and append a PMADDUBSW instruction to the active function. +func (c *Context) PMADDUBSW(mx, x operand.Op) { + c.addinstruction(x86.PMADDUBSW(mx, x)) +} + +// PMADDUBSW: Multiply and Add Packed Signed and Unsigned Byte Integers. +// +// Forms: +// +// PMADDUBSW m128 xmm +// PMADDUBSW xmm xmm +// Construct and append a PMADDUBSW instruction to the active function. +// Operates on the global context. +func PMADDUBSW(mx, x operand.Op) { ctx.PMADDUBSW(mx, x) } + +// PMADDWL: Multiply and Add Packed Signed Word Integers. +// +// Forms: +// +// PMADDWL m128 xmm +// PMADDWL xmm xmm +// Construct and append a PMADDWL instruction to the active function. +func (c *Context) PMADDWL(mx, x operand.Op) { + c.addinstruction(x86.PMADDWL(mx, x)) +} + +// PMADDWL: Multiply and Add Packed Signed Word Integers. +// +// Forms: +// +// PMADDWL m128 xmm +// PMADDWL xmm xmm +// Construct and append a PMADDWL instruction to the active function. +// Operates on the global context. +func PMADDWL(mx, x operand.Op) { ctx.PMADDWL(mx, x) } + +// PMAXSB: Maximum of Packed Signed Byte Integers. +// +// Forms: +// +// PMAXSB m128 xmm +// PMAXSB xmm xmm +// Construct and append a PMAXSB instruction to the active function. +func (c *Context) PMAXSB(mx, x operand.Op) { + c.addinstruction(x86.PMAXSB(mx, x)) +} + +// PMAXSB: Maximum of Packed Signed Byte Integers. +// +// Forms: +// +// PMAXSB m128 xmm +// PMAXSB xmm xmm +// Construct and append a PMAXSB instruction to the active function. +// Operates on the global context. +func PMAXSB(mx, x operand.Op) { ctx.PMAXSB(mx, x) } + +// PMAXSD: Maximum of Packed Signed Doubleword Integers. +// +// Forms: +// +// PMAXSD m128 xmm +// PMAXSD xmm xmm +// Construct and append a PMAXSD instruction to the active function. +func (c *Context) PMAXSD(mx, x operand.Op) { + c.addinstruction(x86.PMAXSD(mx, x)) +} + +// PMAXSD: Maximum of Packed Signed Doubleword Integers. +// +// Forms: +// +// PMAXSD m128 xmm +// PMAXSD xmm xmm +// Construct and append a PMAXSD instruction to the active function. +// Operates on the global context. +func PMAXSD(mx, x operand.Op) { ctx.PMAXSD(mx, x) } + +// PMAXSW: Maximum of Packed Signed Word Integers. +// +// Forms: +// +// PMAXSW m128 xmm +// PMAXSW xmm xmm +// Construct and append a PMAXSW instruction to the active function. +func (c *Context) PMAXSW(mx, x operand.Op) { + c.addinstruction(x86.PMAXSW(mx, x)) +} + +// PMAXSW: Maximum of Packed Signed Word Integers. +// +// Forms: +// +// PMAXSW m128 xmm +// PMAXSW xmm xmm +// Construct and append a PMAXSW instruction to the active function. +// Operates on the global context. +func PMAXSW(mx, x operand.Op) { ctx.PMAXSW(mx, x) } + +// PMAXUB: Maximum of Packed Unsigned Byte Integers. +// +// Forms: +// +// PMAXUB m128 xmm +// PMAXUB xmm xmm +// Construct and append a PMAXUB instruction to the active function. +func (c *Context) PMAXUB(mx, x operand.Op) { + c.addinstruction(x86.PMAXUB(mx, x)) +} + +// PMAXUB: Maximum of Packed Unsigned Byte Integers. +// +// Forms: +// +// PMAXUB m128 xmm +// PMAXUB xmm xmm +// Construct and append a PMAXUB instruction to the active function. +// Operates on the global context. +func PMAXUB(mx, x operand.Op) { ctx.PMAXUB(mx, x) } + +// PMAXUD: Maximum of Packed Unsigned Doubleword Integers. +// +// Forms: +// +// PMAXUD m128 xmm +// PMAXUD xmm xmm +// Construct and append a PMAXUD instruction to the active function. +func (c *Context) PMAXUD(mx, x operand.Op) { + c.addinstruction(x86.PMAXUD(mx, x)) +} + +// PMAXUD: Maximum of Packed Unsigned Doubleword Integers. +// +// Forms: +// +// PMAXUD m128 xmm +// PMAXUD xmm xmm +// Construct and append a PMAXUD instruction to the active function. +// Operates on the global context. +func PMAXUD(mx, x operand.Op) { ctx.PMAXUD(mx, x) } + +// PMAXUW: Maximum of Packed Unsigned Word Integers. +// +// Forms: +// +// PMAXUW m128 xmm +// PMAXUW xmm xmm +// Construct and append a PMAXUW instruction to the active function. +func (c *Context) PMAXUW(mx, x operand.Op) { + c.addinstruction(x86.PMAXUW(mx, x)) +} + +// PMAXUW: Maximum of Packed Unsigned Word Integers. +// +// Forms: +// +// PMAXUW m128 xmm +// PMAXUW xmm xmm +// Construct and append a PMAXUW instruction to the active function. +// Operates on the global context. +func PMAXUW(mx, x operand.Op) { ctx.PMAXUW(mx, x) } + +// PMINSB: Minimum of Packed Signed Byte Integers. +// +// Forms: +// +// PMINSB m128 xmm +// PMINSB xmm xmm +// Construct and append a PMINSB instruction to the active function. +func (c *Context) PMINSB(mx, x operand.Op) { + c.addinstruction(x86.PMINSB(mx, x)) +} + +// PMINSB: Minimum of Packed Signed Byte Integers. +// +// Forms: +// +// PMINSB m128 xmm +// PMINSB xmm xmm +// Construct and append a PMINSB instruction to the active function. +// Operates on the global context. +func PMINSB(mx, x operand.Op) { ctx.PMINSB(mx, x) } + +// PMINSD: Minimum of Packed Signed Doubleword Integers. +// +// Forms: +// +// PMINSD m128 xmm +// PMINSD xmm xmm +// Construct and append a PMINSD instruction to the active function. +func (c *Context) PMINSD(mx, x operand.Op) { + c.addinstruction(x86.PMINSD(mx, x)) +} + +// PMINSD: Minimum of Packed Signed Doubleword Integers. +// +// Forms: +// +// PMINSD m128 xmm +// PMINSD xmm xmm +// Construct and append a PMINSD instruction to the active function. +// Operates on the global context. +func PMINSD(mx, x operand.Op) { ctx.PMINSD(mx, x) } + +// PMINSW: Minimum of Packed Signed Word Integers. +// +// Forms: +// +// PMINSW m128 xmm +// PMINSW xmm xmm +// Construct and append a PMINSW instruction to the active function. +func (c *Context) PMINSW(mx, x operand.Op) { + c.addinstruction(x86.PMINSW(mx, x)) +} + +// PMINSW: Minimum of Packed Signed Word Integers. +// +// Forms: +// +// PMINSW m128 xmm +// PMINSW xmm xmm +// Construct and append a PMINSW instruction to the active function. +// Operates on the global context. +func PMINSW(mx, x operand.Op) { ctx.PMINSW(mx, x) } + +// PMINUB: Minimum of Packed Unsigned Byte Integers. +// +// Forms: +// +// PMINUB m128 xmm +// PMINUB xmm xmm +// Construct and append a PMINUB instruction to the active function. +func (c *Context) PMINUB(mx, x operand.Op) { + c.addinstruction(x86.PMINUB(mx, x)) +} + +// PMINUB: Minimum of Packed Unsigned Byte Integers. +// +// Forms: +// +// PMINUB m128 xmm +// PMINUB xmm xmm +// Construct and append a PMINUB instruction to the active function. +// Operates on the global context. +func PMINUB(mx, x operand.Op) { ctx.PMINUB(mx, x) } + +// PMINUD: Minimum of Packed Unsigned Doubleword Integers. +// +// Forms: +// +// PMINUD m128 xmm +// PMINUD xmm xmm +// Construct and append a PMINUD instruction to the active function. +func (c *Context) PMINUD(mx, x operand.Op) { + c.addinstruction(x86.PMINUD(mx, x)) +} + +// PMINUD: Minimum of Packed Unsigned Doubleword Integers. +// +// Forms: +// +// PMINUD m128 xmm +// PMINUD xmm xmm +// Construct and append a PMINUD instruction to the active function. +// Operates on the global context. +func PMINUD(mx, x operand.Op) { ctx.PMINUD(mx, x) } + +// PMINUW: Minimum of Packed Unsigned Word Integers. +// +// Forms: +// +// PMINUW m128 xmm +// PMINUW xmm xmm +// Construct and append a PMINUW instruction to the active function. +func (c *Context) PMINUW(mx, x operand.Op) { + c.addinstruction(x86.PMINUW(mx, x)) +} + +// PMINUW: Minimum of Packed Unsigned Word Integers. +// +// Forms: +// +// PMINUW m128 xmm +// PMINUW xmm xmm +// Construct and append a PMINUW instruction to the active function. +// Operates on the global context. +func PMINUW(mx, x operand.Op) { ctx.PMINUW(mx, x) } + +// PMOVMSKB: Move Byte Mask. +// +// Forms: +// +// PMOVMSKB xmm r32 +// Construct and append a PMOVMSKB instruction to the active function. +func (c *Context) PMOVMSKB(x, r operand.Op) { + c.addinstruction(x86.PMOVMSKB(x, r)) +} + +// PMOVMSKB: Move Byte Mask. +// +// Forms: +// +// PMOVMSKB xmm r32 +// Construct and append a PMOVMSKB instruction to the active function. +// Operates on the global context. +func PMOVMSKB(x, r operand.Op) { ctx.PMOVMSKB(x, r) } + +// PMOVSXBD: Move Packed Byte Integers to Doubleword Integers with Sign Extension. +// +// Forms: +// +// PMOVSXBD m32 xmm +// PMOVSXBD xmm xmm +// Construct and append a PMOVSXBD instruction to the active function. +func (c *Context) PMOVSXBD(mx, x operand.Op) { + c.addinstruction(x86.PMOVSXBD(mx, x)) +} + +// PMOVSXBD: Move Packed Byte Integers to Doubleword Integers with Sign Extension. +// +// Forms: +// +// PMOVSXBD m32 xmm +// PMOVSXBD xmm xmm +// Construct and append a PMOVSXBD instruction to the active function. +// Operates on the global context. +func PMOVSXBD(mx, x operand.Op) { ctx.PMOVSXBD(mx, x) } + +// PMOVSXBQ: Move Packed Byte Integers to Quadword Integers with Sign Extension. +// +// Forms: +// +// PMOVSXBQ m16 xmm +// PMOVSXBQ xmm xmm +// Construct and append a PMOVSXBQ instruction to the active function. +func (c *Context) PMOVSXBQ(mx, x operand.Op) { + c.addinstruction(x86.PMOVSXBQ(mx, x)) +} + +// PMOVSXBQ: Move Packed Byte Integers to Quadword Integers with Sign Extension. +// +// Forms: +// +// PMOVSXBQ m16 xmm +// PMOVSXBQ xmm xmm +// Construct and append a PMOVSXBQ instruction to the active function. +// Operates on the global context. +func PMOVSXBQ(mx, x operand.Op) { ctx.PMOVSXBQ(mx, x) } + +// PMOVSXBW: Move Packed Byte Integers to Word Integers with Sign Extension. +// +// Forms: +// +// PMOVSXBW m64 xmm +// PMOVSXBW xmm xmm +// Construct and append a PMOVSXBW instruction to the active function. +func (c *Context) PMOVSXBW(mx, x operand.Op) { + c.addinstruction(x86.PMOVSXBW(mx, x)) +} + +// PMOVSXBW: Move Packed Byte Integers to Word Integers with Sign Extension. +// +// Forms: +// +// PMOVSXBW m64 xmm +// PMOVSXBW xmm xmm +// Construct and append a PMOVSXBW instruction to the active function. +// Operates on the global context. +func PMOVSXBW(mx, x operand.Op) { ctx.PMOVSXBW(mx, x) } + +// PMOVSXDQ: Move Packed Doubleword Integers to Quadword Integers with Sign Extension. +// +// Forms: +// +// PMOVSXDQ m64 xmm +// PMOVSXDQ xmm xmm +// Construct and append a PMOVSXDQ instruction to the active function. +func (c *Context) PMOVSXDQ(mx, x operand.Op) { + c.addinstruction(x86.PMOVSXDQ(mx, x)) +} + +// PMOVSXDQ: Move Packed Doubleword Integers to Quadword Integers with Sign Extension. +// +// Forms: +// +// PMOVSXDQ m64 xmm +// PMOVSXDQ xmm xmm +// Construct and append a PMOVSXDQ instruction to the active function. +// Operates on the global context. +func PMOVSXDQ(mx, x operand.Op) { ctx.PMOVSXDQ(mx, x) } + +// PMOVSXWD: Move Packed Word Integers to Doubleword Integers with Sign Extension. +// +// Forms: +// +// PMOVSXWD m64 xmm +// PMOVSXWD xmm xmm +// Construct and append a PMOVSXWD instruction to the active function. +func (c *Context) PMOVSXWD(mx, x operand.Op) { + c.addinstruction(x86.PMOVSXWD(mx, x)) +} + +// PMOVSXWD: Move Packed Word Integers to Doubleword Integers with Sign Extension. +// +// Forms: +// +// PMOVSXWD m64 xmm +// PMOVSXWD xmm xmm +// Construct and append a PMOVSXWD instruction to the active function. +// Operates on the global context. +func PMOVSXWD(mx, x operand.Op) { ctx.PMOVSXWD(mx, x) } + +// PMOVSXWQ: Move Packed Word Integers to Quadword Integers with Sign Extension. +// +// Forms: +// +// PMOVSXWQ m32 xmm +// PMOVSXWQ xmm xmm +// Construct and append a PMOVSXWQ instruction to the active function. +func (c *Context) PMOVSXWQ(mx, x operand.Op) { + c.addinstruction(x86.PMOVSXWQ(mx, x)) +} + +// PMOVSXWQ: Move Packed Word Integers to Quadword Integers with Sign Extension. +// +// Forms: +// +// PMOVSXWQ m32 xmm +// PMOVSXWQ xmm xmm +// Construct and append a PMOVSXWQ instruction to the active function. +// Operates on the global context. +func PMOVSXWQ(mx, x operand.Op) { ctx.PMOVSXWQ(mx, x) } + +// PMOVZXBD: Move Packed Byte Integers to Doubleword Integers with Zero Extension. +// +// Forms: +// +// PMOVZXBD m32 xmm +// PMOVZXBD xmm xmm +// Construct and append a PMOVZXBD instruction to the active function. +func (c *Context) PMOVZXBD(mx, x operand.Op) { + c.addinstruction(x86.PMOVZXBD(mx, x)) +} + +// PMOVZXBD: Move Packed Byte Integers to Doubleword Integers with Zero Extension. +// +// Forms: +// +// PMOVZXBD m32 xmm +// PMOVZXBD xmm xmm +// Construct and append a PMOVZXBD instruction to the active function. +// Operates on the global context. +func PMOVZXBD(mx, x operand.Op) { ctx.PMOVZXBD(mx, x) } + +// PMOVZXBQ: Move Packed Byte Integers to Quadword Integers with Zero Extension. +// +// Forms: +// +// PMOVZXBQ m16 xmm +// PMOVZXBQ xmm xmm +// Construct and append a PMOVZXBQ instruction to the active function. +func (c *Context) PMOVZXBQ(mx, x operand.Op) { + c.addinstruction(x86.PMOVZXBQ(mx, x)) +} + +// PMOVZXBQ: Move Packed Byte Integers to Quadword Integers with Zero Extension. +// +// Forms: +// +// PMOVZXBQ m16 xmm +// PMOVZXBQ xmm xmm +// Construct and append a PMOVZXBQ instruction to the active function. +// Operates on the global context. +func PMOVZXBQ(mx, x operand.Op) { ctx.PMOVZXBQ(mx, x) } + +// PMOVZXBW: Move Packed Byte Integers to Word Integers with Zero Extension. +// +// Forms: +// +// PMOVZXBW m64 xmm +// PMOVZXBW xmm xmm +// Construct and append a PMOVZXBW instruction to the active function. +func (c *Context) PMOVZXBW(mx, x operand.Op) { + c.addinstruction(x86.PMOVZXBW(mx, x)) +} + +// PMOVZXBW: Move Packed Byte Integers to Word Integers with Zero Extension. +// +// Forms: +// +// PMOVZXBW m64 xmm +// PMOVZXBW xmm xmm +// Construct and append a PMOVZXBW instruction to the active function. +// Operates on the global context. +func PMOVZXBW(mx, x operand.Op) { ctx.PMOVZXBW(mx, x) } + +// PMOVZXDQ: Move Packed Doubleword Integers to Quadword Integers with Zero Extension. +// +// Forms: +// +// PMOVZXDQ m64 xmm +// PMOVZXDQ xmm xmm +// Construct and append a PMOVZXDQ instruction to the active function. +func (c *Context) PMOVZXDQ(mx, x operand.Op) { + c.addinstruction(x86.PMOVZXDQ(mx, x)) +} + +// PMOVZXDQ: Move Packed Doubleword Integers to Quadword Integers with Zero Extension. +// +// Forms: +// +// PMOVZXDQ m64 xmm +// PMOVZXDQ xmm xmm +// Construct and append a PMOVZXDQ instruction to the active function. +// Operates on the global context. +func PMOVZXDQ(mx, x operand.Op) { ctx.PMOVZXDQ(mx, x) } + +// PMOVZXWD: Move Packed Word Integers to Doubleword Integers with Zero Extension. +// +// Forms: +// +// PMOVZXWD m64 xmm +// PMOVZXWD xmm xmm +// Construct and append a PMOVZXWD instruction to the active function. +func (c *Context) PMOVZXWD(mx, x operand.Op) { + c.addinstruction(x86.PMOVZXWD(mx, x)) +} + +// PMOVZXWD: Move Packed Word Integers to Doubleword Integers with Zero Extension. +// +// Forms: +// +// PMOVZXWD m64 xmm +// PMOVZXWD xmm xmm +// Construct and append a PMOVZXWD instruction to the active function. +// Operates on the global context. +func PMOVZXWD(mx, x operand.Op) { ctx.PMOVZXWD(mx, x) } + +// PMOVZXWQ: Move Packed Word Integers to Quadword Integers with Zero Extension. +// +// Forms: +// +// PMOVZXWQ m32 xmm +// PMOVZXWQ xmm xmm +// Construct and append a PMOVZXWQ instruction to the active function. +func (c *Context) PMOVZXWQ(mx, x operand.Op) { + c.addinstruction(x86.PMOVZXWQ(mx, x)) +} + +// PMOVZXWQ: Move Packed Word Integers to Quadword Integers with Zero Extension. +// +// Forms: +// +// PMOVZXWQ m32 xmm +// PMOVZXWQ xmm xmm +// Construct and append a PMOVZXWQ instruction to the active function. +// Operates on the global context. +func PMOVZXWQ(mx, x operand.Op) { ctx.PMOVZXWQ(mx, x) } + +// PMULDQ: Multiply Packed Signed Doubleword Integers and Store Quadword Result. +// +// Forms: +// +// PMULDQ m128 xmm +// PMULDQ xmm xmm +// Construct and append a PMULDQ instruction to the active function. +func (c *Context) PMULDQ(mx, x operand.Op) { + c.addinstruction(x86.PMULDQ(mx, x)) +} + +// PMULDQ: Multiply Packed Signed Doubleword Integers and Store Quadword Result. +// +// Forms: +// +// PMULDQ m128 xmm +// PMULDQ xmm xmm +// Construct and append a PMULDQ instruction to the active function. +// Operates on the global context. +func PMULDQ(mx, x operand.Op) { ctx.PMULDQ(mx, x) } + +// PMULHRSW: Packed Multiply Signed Word Integers and Store High Result with Round and Scale. +// +// Forms: +// +// PMULHRSW m128 xmm +// PMULHRSW xmm xmm +// Construct and append a PMULHRSW instruction to the active function. +func (c *Context) PMULHRSW(mx, x operand.Op) { + c.addinstruction(x86.PMULHRSW(mx, x)) +} + +// PMULHRSW: Packed Multiply Signed Word Integers and Store High Result with Round and Scale. +// +// Forms: +// +// PMULHRSW m128 xmm +// PMULHRSW xmm xmm +// Construct and append a PMULHRSW instruction to the active function. +// Operates on the global context. +func PMULHRSW(mx, x operand.Op) { ctx.PMULHRSW(mx, x) } + +// PMULHUW: Multiply Packed Unsigned Word Integers and Store High Result. +// +// Forms: +// +// PMULHUW m128 xmm +// PMULHUW xmm xmm +// Construct and append a PMULHUW instruction to the active function. +func (c *Context) PMULHUW(mx, x operand.Op) { + c.addinstruction(x86.PMULHUW(mx, x)) +} + +// PMULHUW: Multiply Packed Unsigned Word Integers and Store High Result. +// +// Forms: +// +// PMULHUW m128 xmm +// PMULHUW xmm xmm +// Construct and append a PMULHUW instruction to the active function. +// Operates on the global context. +func PMULHUW(mx, x operand.Op) { ctx.PMULHUW(mx, x) } + +// PMULHW: Multiply Packed Signed Word Integers and Store High Result. +// +// Forms: +// +// PMULHW m128 xmm +// PMULHW xmm xmm +// Construct and append a PMULHW instruction to the active function. +func (c *Context) PMULHW(mx, x operand.Op) { + c.addinstruction(x86.PMULHW(mx, x)) +} + +// PMULHW: Multiply Packed Signed Word Integers and Store High Result. +// +// Forms: +// +// PMULHW m128 xmm +// PMULHW xmm xmm +// Construct and append a PMULHW instruction to the active function. +// Operates on the global context. +func PMULHW(mx, x operand.Op) { ctx.PMULHW(mx, x) } + +// PMULLD: Multiply Packed Signed Doubleword Integers and Store Low Result. +// +// Forms: +// +// PMULLD m128 xmm +// PMULLD xmm xmm +// Construct and append a PMULLD instruction to the active function. +func (c *Context) PMULLD(mx, x operand.Op) { + c.addinstruction(x86.PMULLD(mx, x)) +} + +// PMULLD: Multiply Packed Signed Doubleword Integers and Store Low Result. +// +// Forms: +// +// PMULLD m128 xmm +// PMULLD xmm xmm +// Construct and append a PMULLD instruction to the active function. +// Operates on the global context. +func PMULLD(mx, x operand.Op) { ctx.PMULLD(mx, x) } + +// PMULLW: Multiply Packed Signed Word Integers and Store Low Result. +// +// Forms: +// +// PMULLW m128 xmm +// PMULLW xmm xmm +// Construct and append a PMULLW instruction to the active function. +func (c *Context) PMULLW(mx, x operand.Op) { + c.addinstruction(x86.PMULLW(mx, x)) +} + +// PMULLW: Multiply Packed Signed Word Integers and Store Low Result. +// +// Forms: +// +// PMULLW m128 xmm +// PMULLW xmm xmm +// Construct and append a PMULLW instruction to the active function. +// Operates on the global context. +func PMULLW(mx, x operand.Op) { ctx.PMULLW(mx, x) } + +// PMULULQ: Multiply Packed Unsigned Doubleword Integers. +// +// Forms: +// +// PMULULQ m128 xmm +// PMULULQ xmm xmm +// Construct and append a PMULULQ instruction to the active function. +func (c *Context) PMULULQ(mx, x operand.Op) { + c.addinstruction(x86.PMULULQ(mx, x)) +} + +// PMULULQ: Multiply Packed Unsigned Doubleword Integers. +// +// Forms: +// +// PMULULQ m128 xmm +// PMULULQ xmm xmm +// Construct and append a PMULULQ instruction to the active function. +// Operates on the global context. +func PMULULQ(mx, x operand.Op) { ctx.PMULULQ(mx, x) } + +// POPCNTL: Count of Number of Bits Set to 1. +// +// Forms: +// +// POPCNTL m32 r32 +// POPCNTL r32 r32 +// Construct and append a POPCNTL instruction to the active function. +func (c *Context) POPCNTL(mr, r operand.Op) { + c.addinstruction(x86.POPCNTL(mr, r)) +} + +// POPCNTL: Count of Number of Bits Set to 1. +// +// Forms: +// +// POPCNTL m32 r32 +// POPCNTL r32 r32 +// Construct and append a POPCNTL instruction to the active function. +// Operates on the global context. +func POPCNTL(mr, r operand.Op) { ctx.POPCNTL(mr, r) } + +// POPCNTQ: Count of Number of Bits Set to 1. +// +// Forms: +// +// POPCNTQ m64 r64 +// POPCNTQ r64 r64 +// Construct and append a POPCNTQ instruction to the active function. +func (c *Context) POPCNTQ(mr, r operand.Op) { + c.addinstruction(x86.POPCNTQ(mr, r)) +} + +// POPCNTQ: Count of Number of Bits Set to 1. +// +// Forms: +// +// POPCNTQ m64 r64 +// POPCNTQ r64 r64 +// Construct and append a POPCNTQ instruction to the active function. +// Operates on the global context. +func POPCNTQ(mr, r operand.Op) { ctx.POPCNTQ(mr, r) } + +// POPCNTW: Count of Number of Bits Set to 1. +// +// Forms: +// +// POPCNTW m16 r16 +// POPCNTW r16 r16 +// Construct and append a POPCNTW instruction to the active function. +func (c *Context) POPCNTW(mr, r operand.Op) { + c.addinstruction(x86.POPCNTW(mr, r)) +} + +// POPCNTW: Count of Number of Bits Set to 1. +// +// Forms: +// +// POPCNTW m16 r16 +// POPCNTW r16 r16 +// Construct and append a POPCNTW instruction to the active function. +// Operates on the global context. +func POPCNTW(mr, r operand.Op) { ctx.POPCNTW(mr, r) } + +// POPQ: Pop a Value from the Stack. +// +// Forms: +// +// POPQ m64 +// POPQ r64 +// Construct and append a POPQ instruction to the active function. +func (c *Context) POPQ(mr operand.Op) { + c.addinstruction(x86.POPQ(mr)) +} + +// POPQ: Pop a Value from the Stack. +// +// Forms: +// +// POPQ m64 +// POPQ r64 +// Construct and append a POPQ instruction to the active function. +// Operates on the global context. +func POPQ(mr operand.Op) { ctx.POPQ(mr) } + +// POPW: Pop a Value from the Stack. +// +// Forms: +// +// POPW m16 +// POPW r16 +// Construct and append a POPW instruction to the active function. +func (c *Context) POPW(mr operand.Op) { + c.addinstruction(x86.POPW(mr)) +} + +// POPW: Pop a Value from the Stack. +// +// Forms: +// +// POPW m16 +// POPW r16 +// Construct and append a POPW instruction to the active function. +// Operates on the global context. +func POPW(mr operand.Op) { ctx.POPW(mr) } + +// POR: Packed Bitwise Logical OR. +// +// Forms: +// +// POR m128 xmm +// POR xmm xmm +// Construct and append a POR instruction to the active function. +func (c *Context) POR(mx, x operand.Op) { + c.addinstruction(x86.POR(mx, x)) +} + +// POR: Packed Bitwise Logical OR. +// +// Forms: +// +// POR m128 xmm +// POR xmm xmm +// Construct and append a POR instruction to the active function. +// Operates on the global context. +func POR(mx, x operand.Op) { ctx.POR(mx, x) } + +// PREFETCHNTA: Prefetch Data Into Caches using NTA Hint. +// +// Forms: +// +// PREFETCHNTA m8 +// Construct and append a PREFETCHNTA instruction to the active function. +func (c *Context) PREFETCHNTA(m operand.Op) { + c.addinstruction(x86.PREFETCHNTA(m)) +} + +// PREFETCHNTA: Prefetch Data Into Caches using NTA Hint. +// +// Forms: +// +// PREFETCHNTA m8 +// Construct and append a PREFETCHNTA instruction to the active function. +// Operates on the global context. +func PREFETCHNTA(m operand.Op) { ctx.PREFETCHNTA(m) } + +// PREFETCHT0: Prefetch Data Into Caches using T0 Hint. +// +// Forms: +// +// PREFETCHT0 m8 +// Construct and append a PREFETCHT0 instruction to the active function. +func (c *Context) PREFETCHT0(m operand.Op) { + c.addinstruction(x86.PREFETCHT0(m)) +} + +// PREFETCHT0: Prefetch Data Into Caches using T0 Hint. +// +// Forms: +// +// PREFETCHT0 m8 +// Construct and append a PREFETCHT0 instruction to the active function. +// Operates on the global context. +func PREFETCHT0(m operand.Op) { ctx.PREFETCHT0(m) } + +// PREFETCHT1: Prefetch Data Into Caches using T1 Hint. +// +// Forms: +// +// PREFETCHT1 m8 +// Construct and append a PREFETCHT1 instruction to the active function. +func (c *Context) PREFETCHT1(m operand.Op) { + c.addinstruction(x86.PREFETCHT1(m)) +} + +// PREFETCHT1: Prefetch Data Into Caches using T1 Hint. +// +// Forms: +// +// PREFETCHT1 m8 +// Construct and append a PREFETCHT1 instruction to the active function. +// Operates on the global context. +func PREFETCHT1(m operand.Op) { ctx.PREFETCHT1(m) } + +// PREFETCHT2: Prefetch Data Into Caches using T2 Hint. +// +// Forms: +// +// PREFETCHT2 m8 +// Construct and append a PREFETCHT2 instruction to the active function. +func (c *Context) PREFETCHT2(m operand.Op) { + c.addinstruction(x86.PREFETCHT2(m)) +} + +// PREFETCHT2: Prefetch Data Into Caches using T2 Hint. +// +// Forms: +// +// PREFETCHT2 m8 +// Construct and append a PREFETCHT2 instruction to the active function. +// Operates on the global context. +func PREFETCHT2(m operand.Op) { ctx.PREFETCHT2(m) } + +// PSADBW: Compute Sum of Absolute Differences. +// +// Forms: +// +// PSADBW m128 xmm +// PSADBW xmm xmm +// Construct and append a PSADBW instruction to the active function. +func (c *Context) PSADBW(mx, x operand.Op) { + c.addinstruction(x86.PSADBW(mx, x)) +} + +// PSADBW: Compute Sum of Absolute Differences. +// +// Forms: +// +// PSADBW m128 xmm +// PSADBW xmm xmm +// Construct and append a PSADBW instruction to the active function. +// Operates on the global context. +func PSADBW(mx, x operand.Op) { ctx.PSADBW(mx, x) } + +// PSHUFB: Packed Shuffle Bytes. +// +// Forms: +// +// PSHUFB m128 xmm +// PSHUFB xmm xmm +// Construct and append a PSHUFB instruction to the active function. +func (c *Context) PSHUFB(mx, x operand.Op) { + c.addinstruction(x86.PSHUFB(mx, x)) +} + +// PSHUFB: Packed Shuffle Bytes. +// +// Forms: +// +// PSHUFB m128 xmm +// PSHUFB xmm xmm +// Construct and append a PSHUFB instruction to the active function. +// Operates on the global context. +func PSHUFB(mx, x operand.Op) { ctx.PSHUFB(mx, x) } + +// PSHUFD: Shuffle Packed Doublewords. +// +// Forms: +// +// PSHUFD imm8 m128 xmm +// PSHUFD imm8 xmm xmm +// Construct and append a PSHUFD instruction to the active function. +func (c *Context) PSHUFD(i, mx, x operand.Op) { + c.addinstruction(x86.PSHUFD(i, mx, x)) +} + +// PSHUFD: Shuffle Packed Doublewords. +// +// Forms: +// +// PSHUFD imm8 m128 xmm +// PSHUFD imm8 xmm xmm +// Construct and append a PSHUFD instruction to the active function. +// Operates on the global context. +func PSHUFD(i, mx, x operand.Op) { ctx.PSHUFD(i, mx, x) } + +// PSHUFHW: Shuffle Packed High Words. +// +// Forms: +// +// PSHUFHW imm8 m128 xmm +// PSHUFHW imm8 xmm xmm +// Construct and append a PSHUFHW instruction to the active function. +func (c *Context) PSHUFHW(i, mx, x operand.Op) { + c.addinstruction(x86.PSHUFHW(i, mx, x)) +} + +// PSHUFHW: Shuffle Packed High Words. +// +// Forms: +// +// PSHUFHW imm8 m128 xmm +// PSHUFHW imm8 xmm xmm +// Construct and append a PSHUFHW instruction to the active function. +// Operates on the global context. +func PSHUFHW(i, mx, x operand.Op) { ctx.PSHUFHW(i, mx, x) } + +// PSHUFL: Shuffle Packed Doublewords. +// +// Forms: +// +// PSHUFL imm8 m128 xmm +// PSHUFL imm8 xmm xmm +// Construct and append a PSHUFL instruction to the active function. +func (c *Context) PSHUFL(i, mx, x operand.Op) { + c.addinstruction(x86.PSHUFL(i, mx, x)) +} + +// PSHUFL: Shuffle Packed Doublewords. +// +// Forms: +// +// PSHUFL imm8 m128 xmm +// PSHUFL imm8 xmm xmm +// Construct and append a PSHUFL instruction to the active function. +// Operates on the global context. +func PSHUFL(i, mx, x operand.Op) { ctx.PSHUFL(i, mx, x) } + +// PSHUFLW: Shuffle Packed Low Words. +// +// Forms: +// +// PSHUFLW imm8 m128 xmm +// PSHUFLW imm8 xmm xmm +// Construct and append a PSHUFLW instruction to the active function. +func (c *Context) PSHUFLW(i, mx, x operand.Op) { + c.addinstruction(x86.PSHUFLW(i, mx, x)) +} + +// PSHUFLW: Shuffle Packed Low Words. +// +// Forms: +// +// PSHUFLW imm8 m128 xmm +// PSHUFLW imm8 xmm xmm +// Construct and append a PSHUFLW instruction to the active function. +// Operates on the global context. +func PSHUFLW(i, mx, x operand.Op) { ctx.PSHUFLW(i, mx, x) } + +// PSIGNB: Packed Sign of Byte Integers. +// +// Forms: +// +// PSIGNB m128 xmm +// PSIGNB xmm xmm +// Construct and append a PSIGNB instruction to the active function. +func (c *Context) PSIGNB(mx, x operand.Op) { + c.addinstruction(x86.PSIGNB(mx, x)) +} + +// PSIGNB: Packed Sign of Byte Integers. +// +// Forms: +// +// PSIGNB m128 xmm +// PSIGNB xmm xmm +// Construct and append a PSIGNB instruction to the active function. +// Operates on the global context. +func PSIGNB(mx, x operand.Op) { ctx.PSIGNB(mx, x) } + +// PSIGND: Packed Sign of Doubleword Integers. +// +// Forms: +// +// PSIGND m128 xmm +// PSIGND xmm xmm +// Construct and append a PSIGND instruction to the active function. +func (c *Context) PSIGND(mx, x operand.Op) { + c.addinstruction(x86.PSIGND(mx, x)) +} + +// PSIGND: Packed Sign of Doubleword Integers. +// +// Forms: +// +// PSIGND m128 xmm +// PSIGND xmm xmm +// Construct and append a PSIGND instruction to the active function. +// Operates on the global context. +func PSIGND(mx, x operand.Op) { ctx.PSIGND(mx, x) } + +// PSIGNW: Packed Sign of Word Integers. +// +// Forms: +// +// PSIGNW m128 xmm +// PSIGNW xmm xmm +// Construct and append a PSIGNW instruction to the active function. +func (c *Context) PSIGNW(mx, x operand.Op) { + c.addinstruction(x86.PSIGNW(mx, x)) +} + +// PSIGNW: Packed Sign of Word Integers. +// +// Forms: +// +// PSIGNW m128 xmm +// PSIGNW xmm xmm +// Construct and append a PSIGNW instruction to the active function. +// Operates on the global context. +func PSIGNW(mx, x operand.Op) { ctx.PSIGNW(mx, x) } + +// PSLLDQ: Shift Packed Double Quadword Left Logical. +// +// Forms: +// +// PSLLDQ imm8 xmm +// Construct and append a PSLLDQ instruction to the active function. +func (c *Context) PSLLDQ(i, x operand.Op) { + c.addinstruction(x86.PSLLDQ(i, x)) +} + +// PSLLDQ: Shift Packed Double Quadword Left Logical. +// +// Forms: +// +// PSLLDQ imm8 xmm +// Construct and append a PSLLDQ instruction to the active function. +// Operates on the global context. +func PSLLDQ(i, x operand.Op) { ctx.PSLLDQ(i, x) } + +// PSLLL: Shift Packed Doubleword Data Left Logical. +// +// Forms: +// +// PSLLL imm8 xmm +// PSLLL m128 xmm +// PSLLL xmm xmm +// Construct and append a PSLLL instruction to the active function. +func (c *Context) PSLLL(imx, x operand.Op) { + c.addinstruction(x86.PSLLL(imx, x)) +} + +// PSLLL: Shift Packed Doubleword Data Left Logical. +// +// Forms: +// +// PSLLL imm8 xmm +// PSLLL m128 xmm +// PSLLL xmm xmm +// Construct and append a PSLLL instruction to the active function. +// Operates on the global context. +func PSLLL(imx, x operand.Op) { ctx.PSLLL(imx, x) } + +// PSLLO: Shift Packed Double Quadword Left Logical. +// +// Forms: +// +// PSLLO imm8 xmm +// Construct and append a PSLLO instruction to the active function. +func (c *Context) PSLLO(i, x operand.Op) { + c.addinstruction(x86.PSLLO(i, x)) +} + +// PSLLO: Shift Packed Double Quadword Left Logical. +// +// Forms: +// +// PSLLO imm8 xmm +// Construct and append a PSLLO instruction to the active function. +// Operates on the global context. +func PSLLO(i, x operand.Op) { ctx.PSLLO(i, x) } + +// PSLLQ: Shift Packed Quadword Data Left Logical. +// +// Forms: +// +// PSLLQ imm8 xmm +// PSLLQ m128 xmm +// PSLLQ xmm xmm +// Construct and append a PSLLQ instruction to the active function. +func (c *Context) PSLLQ(imx, x operand.Op) { + c.addinstruction(x86.PSLLQ(imx, x)) +} + +// PSLLQ: Shift Packed Quadword Data Left Logical. +// +// Forms: +// +// PSLLQ imm8 xmm +// PSLLQ m128 xmm +// PSLLQ xmm xmm +// Construct and append a PSLLQ instruction to the active function. +// Operates on the global context. +func PSLLQ(imx, x operand.Op) { ctx.PSLLQ(imx, x) } + +// PSLLW: Shift Packed Word Data Left Logical. +// +// Forms: +// +// PSLLW imm8 xmm +// PSLLW m128 xmm +// PSLLW xmm xmm +// Construct and append a PSLLW instruction to the active function. +func (c *Context) PSLLW(imx, x operand.Op) { + c.addinstruction(x86.PSLLW(imx, x)) +} + +// PSLLW: Shift Packed Word Data Left Logical. +// +// Forms: +// +// PSLLW imm8 xmm +// PSLLW m128 xmm +// PSLLW xmm xmm +// Construct and append a PSLLW instruction to the active function. +// Operates on the global context. +func PSLLW(imx, x operand.Op) { ctx.PSLLW(imx, x) } + +// PSRAL: Shift Packed Doubleword Data Right Arithmetic. +// +// Forms: +// +// PSRAL imm8 xmm +// PSRAL m128 xmm +// PSRAL xmm xmm +// Construct and append a PSRAL instruction to the active function. +func (c *Context) PSRAL(imx, x operand.Op) { + c.addinstruction(x86.PSRAL(imx, x)) +} + +// PSRAL: Shift Packed Doubleword Data Right Arithmetic. +// +// Forms: +// +// PSRAL imm8 xmm +// PSRAL m128 xmm +// PSRAL xmm xmm +// Construct and append a PSRAL instruction to the active function. +// Operates on the global context. +func PSRAL(imx, x operand.Op) { ctx.PSRAL(imx, x) } + +// PSRAW: Shift Packed Word Data Right Arithmetic. +// +// Forms: +// +// PSRAW imm8 xmm +// PSRAW m128 xmm +// PSRAW xmm xmm +// Construct and append a PSRAW instruction to the active function. +func (c *Context) PSRAW(imx, x operand.Op) { + c.addinstruction(x86.PSRAW(imx, x)) +} + +// PSRAW: Shift Packed Word Data Right Arithmetic. +// +// Forms: +// +// PSRAW imm8 xmm +// PSRAW m128 xmm +// PSRAW xmm xmm +// Construct and append a PSRAW instruction to the active function. +// Operates on the global context. +func PSRAW(imx, x operand.Op) { ctx.PSRAW(imx, x) } + +// PSRLDQ: Shift Packed Double Quadword Right Logical. +// +// Forms: +// +// PSRLDQ imm8 xmm +// Construct and append a PSRLDQ instruction to the active function. +func (c *Context) PSRLDQ(i, x operand.Op) { + c.addinstruction(x86.PSRLDQ(i, x)) +} + +// PSRLDQ: Shift Packed Double Quadword Right Logical. +// +// Forms: +// +// PSRLDQ imm8 xmm +// Construct and append a PSRLDQ instruction to the active function. +// Operates on the global context. +func PSRLDQ(i, x operand.Op) { ctx.PSRLDQ(i, x) } + +// PSRLL: Shift Packed Doubleword Data Right Logical. +// +// Forms: +// +// PSRLL imm8 xmm +// PSRLL m128 xmm +// PSRLL xmm xmm +// Construct and append a PSRLL instruction to the active function. +func (c *Context) PSRLL(imx, x operand.Op) { + c.addinstruction(x86.PSRLL(imx, x)) +} + +// PSRLL: Shift Packed Doubleword Data Right Logical. +// +// Forms: +// +// PSRLL imm8 xmm +// PSRLL m128 xmm +// PSRLL xmm xmm +// Construct and append a PSRLL instruction to the active function. +// Operates on the global context. +func PSRLL(imx, x operand.Op) { ctx.PSRLL(imx, x) } + +// PSRLO: Shift Packed Double Quadword Right Logical. +// +// Forms: +// +// PSRLO imm8 xmm +// Construct and append a PSRLO instruction to the active function. +func (c *Context) PSRLO(i, x operand.Op) { + c.addinstruction(x86.PSRLO(i, x)) +} + +// PSRLO: Shift Packed Double Quadword Right Logical. +// +// Forms: +// +// PSRLO imm8 xmm +// Construct and append a PSRLO instruction to the active function. +// Operates on the global context. +func PSRLO(i, x operand.Op) { ctx.PSRLO(i, x) } + +// PSRLQ: Shift Packed Quadword Data Right Logical. +// +// Forms: +// +// PSRLQ imm8 xmm +// PSRLQ m128 xmm +// PSRLQ xmm xmm +// Construct and append a PSRLQ instruction to the active function. +func (c *Context) PSRLQ(imx, x operand.Op) { + c.addinstruction(x86.PSRLQ(imx, x)) +} + +// PSRLQ: Shift Packed Quadword Data Right Logical. +// +// Forms: +// +// PSRLQ imm8 xmm +// PSRLQ m128 xmm +// PSRLQ xmm xmm +// Construct and append a PSRLQ instruction to the active function. +// Operates on the global context. +func PSRLQ(imx, x operand.Op) { ctx.PSRLQ(imx, x) } + +// PSRLW: Shift Packed Word Data Right Logical. +// +// Forms: +// +// PSRLW imm8 xmm +// PSRLW m128 xmm +// PSRLW xmm xmm +// Construct and append a PSRLW instruction to the active function. +func (c *Context) PSRLW(imx, x operand.Op) { + c.addinstruction(x86.PSRLW(imx, x)) +} + +// PSRLW: Shift Packed Word Data Right Logical. +// +// Forms: +// +// PSRLW imm8 xmm +// PSRLW m128 xmm +// PSRLW xmm xmm +// Construct and append a PSRLW instruction to the active function. +// Operates on the global context. +func PSRLW(imx, x operand.Op) { ctx.PSRLW(imx, x) } + +// PSUBB: Subtract Packed Byte Integers. +// +// Forms: +// +// PSUBB m128 xmm +// PSUBB xmm xmm +// Construct and append a PSUBB instruction to the active function. +func (c *Context) PSUBB(mx, x operand.Op) { + c.addinstruction(x86.PSUBB(mx, x)) +} + +// PSUBB: Subtract Packed Byte Integers. +// +// Forms: +// +// PSUBB m128 xmm +// PSUBB xmm xmm +// Construct and append a PSUBB instruction to the active function. +// Operates on the global context. +func PSUBB(mx, x operand.Op) { ctx.PSUBB(mx, x) } + +// PSUBL: Subtract Packed Doubleword Integers. +// +// Forms: +// +// PSUBL m128 xmm +// PSUBL xmm xmm +// Construct and append a PSUBL instruction to the active function. +func (c *Context) PSUBL(mx, x operand.Op) { + c.addinstruction(x86.PSUBL(mx, x)) +} + +// PSUBL: Subtract Packed Doubleword Integers. +// +// Forms: +// +// PSUBL m128 xmm +// PSUBL xmm xmm +// Construct and append a PSUBL instruction to the active function. +// Operates on the global context. +func PSUBL(mx, x operand.Op) { ctx.PSUBL(mx, x) } + +// PSUBQ: Subtract Packed Quadword Integers. +// +// Forms: +// +// PSUBQ m128 xmm +// PSUBQ xmm xmm +// Construct and append a PSUBQ instruction to the active function. +func (c *Context) PSUBQ(mx, x operand.Op) { + c.addinstruction(x86.PSUBQ(mx, x)) +} + +// PSUBQ: Subtract Packed Quadword Integers. +// +// Forms: +// +// PSUBQ m128 xmm +// PSUBQ xmm xmm +// Construct and append a PSUBQ instruction to the active function. +// Operates on the global context. +func PSUBQ(mx, x operand.Op) { ctx.PSUBQ(mx, x) } + +// PSUBSB: Subtract Packed Signed Byte Integers with Signed Saturation. +// +// Forms: +// +// PSUBSB m128 xmm +// PSUBSB xmm xmm +// Construct and append a PSUBSB instruction to the active function. +func (c *Context) PSUBSB(mx, x operand.Op) { + c.addinstruction(x86.PSUBSB(mx, x)) +} + +// PSUBSB: Subtract Packed Signed Byte Integers with Signed Saturation. +// +// Forms: +// +// PSUBSB m128 xmm +// PSUBSB xmm xmm +// Construct and append a PSUBSB instruction to the active function. +// Operates on the global context. +func PSUBSB(mx, x operand.Op) { ctx.PSUBSB(mx, x) } + +// PSUBSW: Subtract Packed Signed Word Integers with Signed Saturation. +// +// Forms: +// +// PSUBSW m128 xmm +// PSUBSW xmm xmm +// Construct and append a PSUBSW instruction to the active function. +func (c *Context) PSUBSW(mx, x operand.Op) { + c.addinstruction(x86.PSUBSW(mx, x)) +} + +// PSUBSW: Subtract Packed Signed Word Integers with Signed Saturation. +// +// Forms: +// +// PSUBSW m128 xmm +// PSUBSW xmm xmm +// Construct and append a PSUBSW instruction to the active function. +// Operates on the global context. +func PSUBSW(mx, x operand.Op) { ctx.PSUBSW(mx, x) } + +// PSUBUSB: Subtract Packed Unsigned Byte Integers with Unsigned Saturation. +// +// Forms: +// +// PSUBUSB m128 xmm +// PSUBUSB xmm xmm +// Construct and append a PSUBUSB instruction to the active function. +func (c *Context) PSUBUSB(mx, x operand.Op) { + c.addinstruction(x86.PSUBUSB(mx, x)) +} + +// PSUBUSB: Subtract Packed Unsigned Byte Integers with Unsigned Saturation. +// +// Forms: +// +// PSUBUSB m128 xmm +// PSUBUSB xmm xmm +// Construct and append a PSUBUSB instruction to the active function. +// Operates on the global context. +func PSUBUSB(mx, x operand.Op) { ctx.PSUBUSB(mx, x) } + +// PSUBUSW: Subtract Packed Unsigned Word Integers with Unsigned Saturation. +// +// Forms: +// +// PSUBUSW m128 xmm +// PSUBUSW xmm xmm +// Construct and append a PSUBUSW instruction to the active function. +func (c *Context) PSUBUSW(mx, x operand.Op) { + c.addinstruction(x86.PSUBUSW(mx, x)) +} + +// PSUBUSW: Subtract Packed Unsigned Word Integers with Unsigned Saturation. +// +// Forms: +// +// PSUBUSW m128 xmm +// PSUBUSW xmm xmm +// Construct and append a PSUBUSW instruction to the active function. +// Operates on the global context. +func PSUBUSW(mx, x operand.Op) { ctx.PSUBUSW(mx, x) } + +// PSUBW: Subtract Packed Word Integers. +// +// Forms: +// +// PSUBW m128 xmm +// PSUBW xmm xmm +// Construct and append a PSUBW instruction to the active function. +func (c *Context) PSUBW(mx, x operand.Op) { + c.addinstruction(x86.PSUBW(mx, x)) +} + +// PSUBW: Subtract Packed Word Integers. +// +// Forms: +// +// PSUBW m128 xmm +// PSUBW xmm xmm +// Construct and append a PSUBW instruction to the active function. +// Operates on the global context. +func PSUBW(mx, x operand.Op) { ctx.PSUBW(mx, x) } + +// PTEST: Packed Logical Compare. +// +// Forms: +// +// PTEST m128 xmm +// PTEST xmm xmm +// Construct and append a PTEST instruction to the active function. +func (c *Context) PTEST(mx, x operand.Op) { + c.addinstruction(x86.PTEST(mx, x)) +} + +// PTEST: Packed Logical Compare. +// +// Forms: +// +// PTEST m128 xmm +// PTEST xmm xmm +// Construct and append a PTEST instruction to the active function. +// Operates on the global context. +func PTEST(mx, x operand.Op) { ctx.PTEST(mx, x) } + +// PUNPCKHBW: Unpack and Interleave High-Order Bytes into Words. +// +// Forms: +// +// PUNPCKHBW m128 xmm +// PUNPCKHBW xmm xmm +// Construct and append a PUNPCKHBW instruction to the active function. +func (c *Context) PUNPCKHBW(mx, x operand.Op) { + c.addinstruction(x86.PUNPCKHBW(mx, x)) +} + +// PUNPCKHBW: Unpack and Interleave High-Order Bytes into Words. +// +// Forms: +// +// PUNPCKHBW m128 xmm +// PUNPCKHBW xmm xmm +// Construct and append a PUNPCKHBW instruction to the active function. +// Operates on the global context. +func PUNPCKHBW(mx, x operand.Op) { ctx.PUNPCKHBW(mx, x) } + +// PUNPCKHLQ: Unpack and Interleave High-Order Doublewords into Quadwords. +// +// Forms: +// +// PUNPCKHLQ m128 xmm +// PUNPCKHLQ xmm xmm +// Construct and append a PUNPCKHLQ instruction to the active function. +func (c *Context) PUNPCKHLQ(mx, x operand.Op) { + c.addinstruction(x86.PUNPCKHLQ(mx, x)) +} + +// PUNPCKHLQ: Unpack and Interleave High-Order Doublewords into Quadwords. +// +// Forms: +// +// PUNPCKHLQ m128 xmm +// PUNPCKHLQ xmm xmm +// Construct and append a PUNPCKHLQ instruction to the active function. +// Operates on the global context. +func PUNPCKHLQ(mx, x operand.Op) { ctx.PUNPCKHLQ(mx, x) } + +// PUNPCKHQDQ: Unpack and Interleave High-Order Quadwords into Double Quadwords. +// +// Forms: +// +// PUNPCKHQDQ m128 xmm +// PUNPCKHQDQ xmm xmm +// Construct and append a PUNPCKHQDQ instruction to the active function. +func (c *Context) PUNPCKHQDQ(mx, x operand.Op) { + c.addinstruction(x86.PUNPCKHQDQ(mx, x)) +} + +// PUNPCKHQDQ: Unpack and Interleave High-Order Quadwords into Double Quadwords. +// +// Forms: +// +// PUNPCKHQDQ m128 xmm +// PUNPCKHQDQ xmm xmm +// Construct and append a PUNPCKHQDQ instruction to the active function. +// Operates on the global context. +func PUNPCKHQDQ(mx, x operand.Op) { ctx.PUNPCKHQDQ(mx, x) } + +// PUNPCKHWL: Unpack and Interleave High-Order Words into Doublewords. +// +// Forms: +// +// PUNPCKHWL m128 xmm +// PUNPCKHWL xmm xmm +// Construct and append a PUNPCKHWL instruction to the active function. +func (c *Context) PUNPCKHWL(mx, x operand.Op) { + c.addinstruction(x86.PUNPCKHWL(mx, x)) +} + +// PUNPCKHWL: Unpack and Interleave High-Order Words into Doublewords. +// +// Forms: +// +// PUNPCKHWL m128 xmm +// PUNPCKHWL xmm xmm +// Construct and append a PUNPCKHWL instruction to the active function. +// Operates on the global context. +func PUNPCKHWL(mx, x operand.Op) { ctx.PUNPCKHWL(mx, x) } + +// PUNPCKLBW: Unpack and Interleave Low-Order Bytes into Words. +// +// Forms: +// +// PUNPCKLBW m128 xmm +// PUNPCKLBW xmm xmm +// Construct and append a PUNPCKLBW instruction to the active function. +func (c *Context) PUNPCKLBW(mx, x operand.Op) { + c.addinstruction(x86.PUNPCKLBW(mx, x)) +} + +// PUNPCKLBW: Unpack and Interleave Low-Order Bytes into Words. +// +// Forms: +// +// PUNPCKLBW m128 xmm +// PUNPCKLBW xmm xmm +// Construct and append a PUNPCKLBW instruction to the active function. +// Operates on the global context. +func PUNPCKLBW(mx, x operand.Op) { ctx.PUNPCKLBW(mx, x) } + +// PUNPCKLLQ: Unpack and Interleave Low-Order Doublewords into Quadwords. +// +// Forms: +// +// PUNPCKLLQ m128 xmm +// PUNPCKLLQ xmm xmm +// Construct and append a PUNPCKLLQ instruction to the active function. +func (c *Context) PUNPCKLLQ(mx, x operand.Op) { + c.addinstruction(x86.PUNPCKLLQ(mx, x)) +} + +// PUNPCKLLQ: Unpack and Interleave Low-Order Doublewords into Quadwords. +// +// Forms: +// +// PUNPCKLLQ m128 xmm +// PUNPCKLLQ xmm xmm +// Construct and append a PUNPCKLLQ instruction to the active function. +// Operates on the global context. +func PUNPCKLLQ(mx, x operand.Op) { ctx.PUNPCKLLQ(mx, x) } + +// PUNPCKLQDQ: Unpack and Interleave Low-Order Quadwords into Double Quadwords. +// +// Forms: +// +// PUNPCKLQDQ m128 xmm +// PUNPCKLQDQ xmm xmm +// Construct and append a PUNPCKLQDQ instruction to the active function. +func (c *Context) PUNPCKLQDQ(mx, x operand.Op) { + c.addinstruction(x86.PUNPCKLQDQ(mx, x)) +} + +// PUNPCKLQDQ: Unpack and Interleave Low-Order Quadwords into Double Quadwords. +// +// Forms: +// +// PUNPCKLQDQ m128 xmm +// PUNPCKLQDQ xmm xmm +// Construct and append a PUNPCKLQDQ instruction to the active function. +// Operates on the global context. +func PUNPCKLQDQ(mx, x operand.Op) { ctx.PUNPCKLQDQ(mx, x) } + +// PUNPCKLWL: Unpack and Interleave Low-Order Words into Doublewords. +// +// Forms: +// +// PUNPCKLWL m128 xmm +// PUNPCKLWL xmm xmm +// Construct and append a PUNPCKLWL instruction to the active function. +func (c *Context) PUNPCKLWL(mx, x operand.Op) { + c.addinstruction(x86.PUNPCKLWL(mx, x)) +} + +// PUNPCKLWL: Unpack and Interleave Low-Order Words into Doublewords. +// +// Forms: +// +// PUNPCKLWL m128 xmm +// PUNPCKLWL xmm xmm +// Construct and append a PUNPCKLWL instruction to the active function. +// Operates on the global context. +func PUNPCKLWL(mx, x operand.Op) { ctx.PUNPCKLWL(mx, x) } + +// PUSHQ: Push Value Onto the Stack. +// +// Forms: +// +// PUSHQ imm32 +// PUSHQ imm8 +// PUSHQ m64 +// PUSHQ r64 +// Construct and append a PUSHQ instruction to the active function. +func (c *Context) PUSHQ(imr operand.Op) { + c.addinstruction(x86.PUSHQ(imr)) +} + +// PUSHQ: Push Value Onto the Stack. +// +// Forms: +// +// PUSHQ imm32 +// PUSHQ imm8 +// PUSHQ m64 +// PUSHQ r64 +// Construct and append a PUSHQ instruction to the active function. +// Operates on the global context. +func PUSHQ(imr operand.Op) { ctx.PUSHQ(imr) } + +// PUSHW: Push Value Onto the Stack. +// +// Forms: +// +// PUSHW m16 +// PUSHW r16 +// Construct and append a PUSHW instruction to the active function. +func (c *Context) PUSHW(mr operand.Op) { + c.addinstruction(x86.PUSHW(mr)) +} + +// PUSHW: Push Value Onto the Stack. +// +// Forms: +// +// PUSHW m16 +// PUSHW r16 +// Construct and append a PUSHW instruction to the active function. +// Operates on the global context. +func PUSHW(mr operand.Op) { ctx.PUSHW(mr) } + +// PXOR: Packed Bitwise Logical Exclusive OR. +// +// Forms: +// +// PXOR m128 xmm +// PXOR xmm xmm +// Construct and append a PXOR instruction to the active function. +func (c *Context) PXOR(mx, x operand.Op) { + c.addinstruction(x86.PXOR(mx, x)) +} + +// PXOR: Packed Bitwise Logical Exclusive OR. +// +// Forms: +// +// PXOR m128 xmm +// PXOR xmm xmm +// Construct and append a PXOR instruction to the active function. +// Operates on the global context. +func PXOR(mx, x operand.Op) { ctx.PXOR(mx, x) } + +// RCLB: Rotate Left through Carry Flag. +// +// Forms: +// +// RCLB 1 m8 +// RCLB 1 r8 +// RCLB cl m8 +// RCLB cl r8 +// RCLB imm8 m8 +// RCLB imm8 r8 +// Construct and append a RCLB instruction to the active function. +func (c *Context) RCLB(ci, mr operand.Op) { + c.addinstruction(x86.RCLB(ci, mr)) +} + +// RCLB: Rotate Left through Carry Flag. +// +// Forms: +// +// RCLB 1 m8 +// RCLB 1 r8 +// RCLB cl m8 +// RCLB cl r8 +// RCLB imm8 m8 +// RCLB imm8 r8 +// Construct and append a RCLB instruction to the active function. +// Operates on the global context. +func RCLB(ci, mr operand.Op) { ctx.RCLB(ci, mr) } + +// RCLL: Rotate Left through Carry Flag. +// +// Forms: +// +// RCLL 1 m32 +// RCLL 1 r32 +// RCLL cl m32 +// RCLL cl r32 +// RCLL imm8 m32 +// RCLL imm8 r32 +// Construct and append a RCLL instruction to the active function. +func (c *Context) RCLL(ci, mr operand.Op) { + c.addinstruction(x86.RCLL(ci, mr)) +} + +// RCLL: Rotate Left through Carry Flag. +// +// Forms: +// +// RCLL 1 m32 +// RCLL 1 r32 +// RCLL cl m32 +// RCLL cl r32 +// RCLL imm8 m32 +// RCLL imm8 r32 +// Construct and append a RCLL instruction to the active function. +// Operates on the global context. +func RCLL(ci, mr operand.Op) { ctx.RCLL(ci, mr) } + +// RCLQ: Rotate Left through Carry Flag. +// +// Forms: +// +// RCLQ 1 m64 +// RCLQ 1 r64 +// RCLQ cl m64 +// RCLQ cl r64 +// RCLQ imm8 m64 +// RCLQ imm8 r64 +// Construct and append a RCLQ instruction to the active function. +func (c *Context) RCLQ(ci, mr operand.Op) { + c.addinstruction(x86.RCLQ(ci, mr)) +} + +// RCLQ: Rotate Left through Carry Flag. +// +// Forms: +// +// RCLQ 1 m64 +// RCLQ 1 r64 +// RCLQ cl m64 +// RCLQ cl r64 +// RCLQ imm8 m64 +// RCLQ imm8 r64 +// Construct and append a RCLQ instruction to the active function. +// Operates on the global context. +func RCLQ(ci, mr operand.Op) { ctx.RCLQ(ci, mr) } + +// RCLW: Rotate Left through Carry Flag. +// +// Forms: +// +// RCLW 1 m16 +// RCLW 1 r16 +// RCLW cl m16 +// RCLW cl r16 +// RCLW imm8 m16 +// RCLW imm8 r16 +// Construct and append a RCLW instruction to the active function. +func (c *Context) RCLW(ci, mr operand.Op) { + c.addinstruction(x86.RCLW(ci, mr)) +} + +// RCLW: Rotate Left through Carry Flag. +// +// Forms: +// +// RCLW 1 m16 +// RCLW 1 r16 +// RCLW cl m16 +// RCLW cl r16 +// RCLW imm8 m16 +// RCLW imm8 r16 +// Construct and append a RCLW instruction to the active function. +// Operates on the global context. +func RCLW(ci, mr operand.Op) { ctx.RCLW(ci, mr) } + +// RCPPS: Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// RCPPS m128 xmm +// RCPPS xmm xmm +// Construct and append a RCPPS instruction to the active function. +func (c *Context) RCPPS(mx, x operand.Op) { + c.addinstruction(x86.RCPPS(mx, x)) +} + +// RCPPS: Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// RCPPS m128 xmm +// RCPPS xmm xmm +// Construct and append a RCPPS instruction to the active function. +// Operates on the global context. +func RCPPS(mx, x operand.Op) { ctx.RCPPS(mx, x) } + +// RCPSS: Compute Approximate Reciprocal of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// RCPSS m32 xmm +// RCPSS xmm xmm +// Construct and append a RCPSS instruction to the active function. +func (c *Context) RCPSS(mx, x operand.Op) { + c.addinstruction(x86.RCPSS(mx, x)) +} + +// RCPSS: Compute Approximate Reciprocal of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// RCPSS m32 xmm +// RCPSS xmm xmm +// Construct and append a RCPSS instruction to the active function. +// Operates on the global context. +func RCPSS(mx, x operand.Op) { ctx.RCPSS(mx, x) } + +// RCRB: Rotate Right through Carry Flag. +// +// Forms: +// +// RCRB 1 m8 +// RCRB 1 r8 +// RCRB cl m8 +// RCRB cl r8 +// RCRB imm8 m8 +// RCRB imm8 r8 +// Construct and append a RCRB instruction to the active function. +func (c *Context) RCRB(ci, mr operand.Op) { + c.addinstruction(x86.RCRB(ci, mr)) +} + +// RCRB: Rotate Right through Carry Flag. +// +// Forms: +// +// RCRB 1 m8 +// RCRB 1 r8 +// RCRB cl m8 +// RCRB cl r8 +// RCRB imm8 m8 +// RCRB imm8 r8 +// Construct and append a RCRB instruction to the active function. +// Operates on the global context. +func RCRB(ci, mr operand.Op) { ctx.RCRB(ci, mr) } + +// RCRL: Rotate Right through Carry Flag. +// +// Forms: +// +// RCRL 1 m32 +// RCRL 1 r32 +// RCRL cl m32 +// RCRL cl r32 +// RCRL imm8 m32 +// RCRL imm8 r32 +// Construct and append a RCRL instruction to the active function. +func (c *Context) RCRL(ci, mr operand.Op) { + c.addinstruction(x86.RCRL(ci, mr)) +} + +// RCRL: Rotate Right through Carry Flag. +// +// Forms: +// +// RCRL 1 m32 +// RCRL 1 r32 +// RCRL cl m32 +// RCRL cl r32 +// RCRL imm8 m32 +// RCRL imm8 r32 +// Construct and append a RCRL instruction to the active function. +// Operates on the global context. +func RCRL(ci, mr operand.Op) { ctx.RCRL(ci, mr) } + +// RCRQ: Rotate Right through Carry Flag. +// +// Forms: +// +// RCRQ 1 m64 +// RCRQ 1 r64 +// RCRQ cl m64 +// RCRQ cl r64 +// RCRQ imm8 m64 +// RCRQ imm8 r64 +// Construct and append a RCRQ instruction to the active function. +func (c *Context) RCRQ(ci, mr operand.Op) { + c.addinstruction(x86.RCRQ(ci, mr)) +} + +// RCRQ: Rotate Right through Carry Flag. +// +// Forms: +// +// RCRQ 1 m64 +// RCRQ 1 r64 +// RCRQ cl m64 +// RCRQ cl r64 +// RCRQ imm8 m64 +// RCRQ imm8 r64 +// Construct and append a RCRQ instruction to the active function. +// Operates on the global context. +func RCRQ(ci, mr operand.Op) { ctx.RCRQ(ci, mr) } + +// RCRW: Rotate Right through Carry Flag. +// +// Forms: +// +// RCRW 1 m16 +// RCRW 1 r16 +// RCRW cl m16 +// RCRW cl r16 +// RCRW imm8 m16 +// RCRW imm8 r16 +// Construct and append a RCRW instruction to the active function. +func (c *Context) RCRW(ci, mr operand.Op) { + c.addinstruction(x86.RCRW(ci, mr)) +} + +// RCRW: Rotate Right through Carry Flag. +// +// Forms: +// +// RCRW 1 m16 +// RCRW 1 r16 +// RCRW cl m16 +// RCRW cl r16 +// RCRW imm8 m16 +// RCRW imm8 r16 +// Construct and append a RCRW instruction to the active function. +// Operates on the global context. +func RCRW(ci, mr operand.Op) { ctx.RCRW(ci, mr) } + +// RDRANDL: Read Random Number. +// +// Forms: +// +// RDRANDL r16 +// RDRANDL r32 +// RDRANDL r64 +// Construct and append a RDRANDL instruction to the active function. +func (c *Context) RDRANDL(r operand.Op) { + c.addinstruction(x86.RDRANDL(r)) +} + +// RDRANDL: Read Random Number. +// +// Forms: +// +// RDRANDL r16 +// RDRANDL r32 +// RDRANDL r64 +// Construct and append a RDRANDL instruction to the active function. +// Operates on the global context. +func RDRANDL(r operand.Op) { ctx.RDRANDL(r) } + +// RDSEEDL: Read Random SEED. +// +// Forms: +// +// RDSEEDL r16 +// RDSEEDL r32 +// RDSEEDL r64 +// Construct and append a RDSEEDL instruction to the active function. +func (c *Context) RDSEEDL(r operand.Op) { + c.addinstruction(x86.RDSEEDL(r)) +} + +// RDSEEDL: Read Random SEED. +// +// Forms: +// +// RDSEEDL r16 +// RDSEEDL r32 +// RDSEEDL r64 +// Construct and append a RDSEEDL instruction to the active function. +// Operates on the global context. +func RDSEEDL(r operand.Op) { ctx.RDSEEDL(r) } + +// RDTSC: Read Time-Stamp Counter. +// +// Forms: +// +// RDTSC +// Construct and append a RDTSC instruction to the active function. +func (c *Context) RDTSC() { + c.addinstruction(x86.RDTSC()) +} + +// RDTSC: Read Time-Stamp Counter. +// +// Forms: +// +// RDTSC +// Construct and append a RDTSC instruction to the active function. +// Operates on the global context. +func RDTSC() { ctx.RDTSC() } + +// RDTSCP: Read Time-Stamp Counter and Processor ID. +// +// Forms: +// +// RDTSCP +// Construct and append a RDTSCP instruction to the active function. +func (c *Context) RDTSCP() { + c.addinstruction(x86.RDTSCP()) +} + +// RDTSCP: Read Time-Stamp Counter and Processor ID. +// +// Forms: +// +// RDTSCP +// Construct and append a RDTSCP instruction to the active function. +// Operates on the global context. +func RDTSCP() { ctx.RDTSCP() } + +// RET: Return from Procedure. +// +// Forms: +// +// RET +// Construct and append a RET instruction to the active function. +func (c *Context) RET() { + c.addinstruction(x86.RET()) +} + +// RET: Return from Procedure. +// +// Forms: +// +// RET +// Construct and append a RET instruction to the active function. +// Operates on the global context. +func RET() { ctx.RET() } + +// RETFL: Return from Procedure. +// +// Forms: +// +// RETFL imm16 +// Construct and append a RETFL instruction to the active function. +func (c *Context) RETFL(i operand.Op) { + c.addinstruction(x86.RETFL(i)) +} + +// RETFL: Return from Procedure. +// +// Forms: +// +// RETFL imm16 +// Construct and append a RETFL instruction to the active function. +// Operates on the global context. +func RETFL(i operand.Op) { ctx.RETFL(i) } + +// RETFQ: Return from Procedure. +// +// Forms: +// +// RETFQ imm16 +// Construct and append a RETFQ instruction to the active function. +func (c *Context) RETFQ(i operand.Op) { + c.addinstruction(x86.RETFQ(i)) +} + +// RETFQ: Return from Procedure. +// +// Forms: +// +// RETFQ imm16 +// Construct and append a RETFQ instruction to the active function. +// Operates on the global context. +func RETFQ(i operand.Op) { ctx.RETFQ(i) } + +// RETFW: Return from Procedure. +// +// Forms: +// +// RETFW imm16 +// Construct and append a RETFW instruction to the active function. +func (c *Context) RETFW(i operand.Op) { + c.addinstruction(x86.RETFW(i)) +} + +// RETFW: Return from Procedure. +// +// Forms: +// +// RETFW imm16 +// Construct and append a RETFW instruction to the active function. +// Operates on the global context. +func RETFW(i operand.Op) { ctx.RETFW(i) } + +// ROLB: Rotate Left. +// +// Forms: +// +// ROLB 1 m8 +// ROLB 1 r8 +// ROLB cl m8 +// ROLB cl r8 +// ROLB imm8 m8 +// ROLB imm8 r8 +// Construct and append a ROLB instruction to the active function. +func (c *Context) ROLB(ci, mr operand.Op) { + c.addinstruction(x86.ROLB(ci, mr)) +} + +// ROLB: Rotate Left. +// +// Forms: +// +// ROLB 1 m8 +// ROLB 1 r8 +// ROLB cl m8 +// ROLB cl r8 +// ROLB imm8 m8 +// ROLB imm8 r8 +// Construct and append a ROLB instruction to the active function. +// Operates on the global context. +func ROLB(ci, mr operand.Op) { ctx.ROLB(ci, mr) } + +// ROLL: Rotate Left. +// +// Forms: +// +// ROLL 1 m32 +// ROLL 1 r32 +// ROLL cl m32 +// ROLL cl r32 +// ROLL imm8 m32 +// ROLL imm8 r32 +// Construct and append a ROLL instruction to the active function. +func (c *Context) ROLL(ci, mr operand.Op) { + c.addinstruction(x86.ROLL(ci, mr)) +} + +// ROLL: Rotate Left. +// +// Forms: +// +// ROLL 1 m32 +// ROLL 1 r32 +// ROLL cl m32 +// ROLL cl r32 +// ROLL imm8 m32 +// ROLL imm8 r32 +// Construct and append a ROLL instruction to the active function. +// Operates on the global context. +func ROLL(ci, mr operand.Op) { ctx.ROLL(ci, mr) } + +// ROLQ: Rotate Left. +// +// Forms: +// +// ROLQ 1 m64 +// ROLQ 1 r64 +// ROLQ cl m64 +// ROLQ cl r64 +// ROLQ imm8 m64 +// ROLQ imm8 r64 +// Construct and append a ROLQ instruction to the active function. +func (c *Context) ROLQ(ci, mr operand.Op) { + c.addinstruction(x86.ROLQ(ci, mr)) +} + +// ROLQ: Rotate Left. +// +// Forms: +// +// ROLQ 1 m64 +// ROLQ 1 r64 +// ROLQ cl m64 +// ROLQ cl r64 +// ROLQ imm8 m64 +// ROLQ imm8 r64 +// Construct and append a ROLQ instruction to the active function. +// Operates on the global context. +func ROLQ(ci, mr operand.Op) { ctx.ROLQ(ci, mr) } + +// ROLW: Rotate Left. +// +// Forms: +// +// ROLW 1 m16 +// ROLW 1 r16 +// ROLW cl m16 +// ROLW cl r16 +// ROLW imm8 m16 +// ROLW imm8 r16 +// Construct and append a ROLW instruction to the active function. +func (c *Context) ROLW(ci, mr operand.Op) { + c.addinstruction(x86.ROLW(ci, mr)) +} + +// ROLW: Rotate Left. +// +// Forms: +// +// ROLW 1 m16 +// ROLW 1 r16 +// ROLW cl m16 +// ROLW cl r16 +// ROLW imm8 m16 +// ROLW imm8 r16 +// Construct and append a ROLW instruction to the active function. +// Operates on the global context. +func ROLW(ci, mr operand.Op) { ctx.ROLW(ci, mr) } + +// RORB: Rotate Right. +// +// Forms: +// +// RORB 1 m8 +// RORB 1 r8 +// RORB cl m8 +// RORB cl r8 +// RORB imm8 m8 +// RORB imm8 r8 +// Construct and append a RORB instruction to the active function. +func (c *Context) RORB(ci, mr operand.Op) { + c.addinstruction(x86.RORB(ci, mr)) +} + +// RORB: Rotate Right. +// +// Forms: +// +// RORB 1 m8 +// RORB 1 r8 +// RORB cl m8 +// RORB cl r8 +// RORB imm8 m8 +// RORB imm8 r8 +// Construct and append a RORB instruction to the active function. +// Operates on the global context. +func RORB(ci, mr operand.Op) { ctx.RORB(ci, mr) } + +// RORL: Rotate Right. +// +// Forms: +// +// RORL 1 m32 +// RORL 1 r32 +// RORL cl m32 +// RORL cl r32 +// RORL imm8 m32 +// RORL imm8 r32 +// Construct and append a RORL instruction to the active function. +func (c *Context) RORL(ci, mr operand.Op) { + c.addinstruction(x86.RORL(ci, mr)) +} + +// RORL: Rotate Right. +// +// Forms: +// +// RORL 1 m32 +// RORL 1 r32 +// RORL cl m32 +// RORL cl r32 +// RORL imm8 m32 +// RORL imm8 r32 +// Construct and append a RORL instruction to the active function. +// Operates on the global context. +func RORL(ci, mr operand.Op) { ctx.RORL(ci, mr) } + +// RORQ: Rotate Right. +// +// Forms: +// +// RORQ 1 m64 +// RORQ 1 r64 +// RORQ cl m64 +// RORQ cl r64 +// RORQ imm8 m64 +// RORQ imm8 r64 +// Construct and append a RORQ instruction to the active function. +func (c *Context) RORQ(ci, mr operand.Op) { + c.addinstruction(x86.RORQ(ci, mr)) +} + +// RORQ: Rotate Right. +// +// Forms: +// +// RORQ 1 m64 +// RORQ 1 r64 +// RORQ cl m64 +// RORQ cl r64 +// RORQ imm8 m64 +// RORQ imm8 r64 +// Construct and append a RORQ instruction to the active function. +// Operates on the global context. +func RORQ(ci, mr operand.Op) { ctx.RORQ(ci, mr) } + +// RORW: Rotate Right. +// +// Forms: +// +// RORW 1 m16 +// RORW 1 r16 +// RORW cl m16 +// RORW cl r16 +// RORW imm8 m16 +// RORW imm8 r16 +// Construct and append a RORW instruction to the active function. +func (c *Context) RORW(ci, mr operand.Op) { + c.addinstruction(x86.RORW(ci, mr)) +} + +// RORW: Rotate Right. +// +// Forms: +// +// RORW 1 m16 +// RORW 1 r16 +// RORW cl m16 +// RORW cl r16 +// RORW imm8 m16 +// RORW imm8 r16 +// Construct and append a RORW instruction to the active function. +// Operates on the global context. +func RORW(ci, mr operand.Op) { ctx.RORW(ci, mr) } + +// RORXL: Rotate Right Logical Without Affecting Flags. +// +// Forms: +// +// RORXL imm8 m32 r32 +// RORXL imm8 r32 r32 +// Construct and append a RORXL instruction to the active function. +func (c *Context) RORXL(i, mr, r operand.Op) { + c.addinstruction(x86.RORXL(i, mr, r)) +} + +// RORXL: Rotate Right Logical Without Affecting Flags. +// +// Forms: +// +// RORXL imm8 m32 r32 +// RORXL imm8 r32 r32 +// Construct and append a RORXL instruction to the active function. +// Operates on the global context. +func RORXL(i, mr, r operand.Op) { ctx.RORXL(i, mr, r) } + +// RORXQ: Rotate Right Logical Without Affecting Flags. +// +// Forms: +// +// RORXQ imm8 m64 r64 +// RORXQ imm8 r64 r64 +// Construct and append a RORXQ instruction to the active function. +func (c *Context) RORXQ(i, mr, r operand.Op) { + c.addinstruction(x86.RORXQ(i, mr, r)) +} + +// RORXQ: Rotate Right Logical Without Affecting Flags. +// +// Forms: +// +// RORXQ imm8 m64 r64 +// RORXQ imm8 r64 r64 +// Construct and append a RORXQ instruction to the active function. +// Operates on the global context. +func RORXQ(i, mr, r operand.Op) { ctx.RORXQ(i, mr, r) } + +// ROUNDPD: Round Packed Double Precision Floating-Point Values. +// +// Forms: +// +// ROUNDPD imm8 m128 xmm +// ROUNDPD imm8 xmm xmm +// Construct and append a ROUNDPD instruction to the active function. +func (c *Context) ROUNDPD(i, mx, x operand.Op) { + c.addinstruction(x86.ROUNDPD(i, mx, x)) +} + +// ROUNDPD: Round Packed Double Precision Floating-Point Values. +// +// Forms: +// +// ROUNDPD imm8 m128 xmm +// ROUNDPD imm8 xmm xmm +// Construct and append a ROUNDPD instruction to the active function. +// Operates on the global context. +func ROUNDPD(i, mx, x operand.Op) { ctx.ROUNDPD(i, mx, x) } + +// ROUNDPS: Round Packed Single Precision Floating-Point Values. +// +// Forms: +// +// ROUNDPS imm8 m128 xmm +// ROUNDPS imm8 xmm xmm +// Construct and append a ROUNDPS instruction to the active function. +func (c *Context) ROUNDPS(i, mx, x operand.Op) { + c.addinstruction(x86.ROUNDPS(i, mx, x)) +} + +// ROUNDPS: Round Packed Single Precision Floating-Point Values. +// +// Forms: +// +// ROUNDPS imm8 m128 xmm +// ROUNDPS imm8 xmm xmm +// Construct and append a ROUNDPS instruction to the active function. +// Operates on the global context. +func ROUNDPS(i, mx, x operand.Op) { ctx.ROUNDPS(i, mx, x) } + +// ROUNDSD: Round Scalar Double Precision Floating-Point Values. +// +// Forms: +// +// ROUNDSD imm8 m64 xmm +// ROUNDSD imm8 xmm xmm +// Construct and append a ROUNDSD instruction to the active function. +func (c *Context) ROUNDSD(i, mx, x operand.Op) { + c.addinstruction(x86.ROUNDSD(i, mx, x)) +} + +// ROUNDSD: Round Scalar Double Precision Floating-Point Values. +// +// Forms: +// +// ROUNDSD imm8 m64 xmm +// ROUNDSD imm8 xmm xmm +// Construct and append a ROUNDSD instruction to the active function. +// Operates on the global context. +func ROUNDSD(i, mx, x operand.Op) { ctx.ROUNDSD(i, mx, x) } + +// ROUNDSS: Round Scalar Single Precision Floating-Point Values. +// +// Forms: +// +// ROUNDSS imm8 m32 xmm +// ROUNDSS imm8 xmm xmm +// Construct and append a ROUNDSS instruction to the active function. +func (c *Context) ROUNDSS(i, mx, x operand.Op) { + c.addinstruction(x86.ROUNDSS(i, mx, x)) +} + +// ROUNDSS: Round Scalar Single Precision Floating-Point Values. +// +// Forms: +// +// ROUNDSS imm8 m32 xmm +// ROUNDSS imm8 xmm xmm +// Construct and append a ROUNDSS instruction to the active function. +// Operates on the global context. +func ROUNDSS(i, mx, x operand.Op) { ctx.ROUNDSS(i, mx, x) } + +// RSQRTPS: Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// RSQRTPS m128 xmm +// RSQRTPS xmm xmm +// Construct and append a RSQRTPS instruction to the active function. +func (c *Context) RSQRTPS(mx, x operand.Op) { + c.addinstruction(x86.RSQRTPS(mx, x)) +} + +// RSQRTPS: Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// RSQRTPS m128 xmm +// RSQRTPS xmm xmm +// Construct and append a RSQRTPS instruction to the active function. +// Operates on the global context. +func RSQRTPS(mx, x operand.Op) { ctx.RSQRTPS(mx, x) } + +// RSQRTSS: Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value. +// +// Forms: +// +// RSQRTSS m32 xmm +// RSQRTSS xmm xmm +// Construct and append a RSQRTSS instruction to the active function. +func (c *Context) RSQRTSS(mx, x operand.Op) { + c.addinstruction(x86.RSQRTSS(mx, x)) +} + +// RSQRTSS: Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value. +// +// Forms: +// +// RSQRTSS m32 xmm +// RSQRTSS xmm xmm +// Construct and append a RSQRTSS instruction to the active function. +// Operates on the global context. +func RSQRTSS(mx, x operand.Op) { ctx.RSQRTSS(mx, x) } + +// SALB: Arithmetic Shift Left. +// +// Forms: +// +// SALB 1 m8 +// SALB 1 r8 +// SALB cl m8 +// SALB cl r8 +// SALB imm8 m8 +// SALB imm8 r8 +// Construct and append a SALB instruction to the active function. +func (c *Context) SALB(ci, mr operand.Op) { + c.addinstruction(x86.SALB(ci, mr)) +} + +// SALB: Arithmetic Shift Left. +// +// Forms: +// +// SALB 1 m8 +// SALB 1 r8 +// SALB cl m8 +// SALB cl r8 +// SALB imm8 m8 +// SALB imm8 r8 +// Construct and append a SALB instruction to the active function. +// Operates on the global context. +func SALB(ci, mr operand.Op) { ctx.SALB(ci, mr) } + +// SALL: Arithmetic Shift Left. +// +// Forms: +// +// SALL 1 m32 +// SALL 1 r32 +// SALL cl m32 +// SALL cl r32 +// SALL imm8 m32 +// SALL imm8 r32 +// Construct and append a SALL instruction to the active function. +func (c *Context) SALL(ci, mr operand.Op) { + c.addinstruction(x86.SALL(ci, mr)) +} + +// SALL: Arithmetic Shift Left. +// +// Forms: +// +// SALL 1 m32 +// SALL 1 r32 +// SALL cl m32 +// SALL cl r32 +// SALL imm8 m32 +// SALL imm8 r32 +// Construct and append a SALL instruction to the active function. +// Operates on the global context. +func SALL(ci, mr operand.Op) { ctx.SALL(ci, mr) } + +// SALQ: Arithmetic Shift Left. +// +// Forms: +// +// SALQ 1 m64 +// SALQ 1 r64 +// SALQ cl m64 +// SALQ cl r64 +// SALQ imm8 m64 +// SALQ imm8 r64 +// Construct and append a SALQ instruction to the active function. +func (c *Context) SALQ(ci, mr operand.Op) { + c.addinstruction(x86.SALQ(ci, mr)) +} + +// SALQ: Arithmetic Shift Left. +// +// Forms: +// +// SALQ 1 m64 +// SALQ 1 r64 +// SALQ cl m64 +// SALQ cl r64 +// SALQ imm8 m64 +// SALQ imm8 r64 +// Construct and append a SALQ instruction to the active function. +// Operates on the global context. +func SALQ(ci, mr operand.Op) { ctx.SALQ(ci, mr) } + +// SALW: Arithmetic Shift Left. +// +// Forms: +// +// SALW 1 m16 +// SALW 1 r16 +// SALW cl m16 +// SALW cl r16 +// SALW imm8 m16 +// SALW imm8 r16 +// Construct and append a SALW instruction to the active function. +func (c *Context) SALW(ci, mr operand.Op) { + c.addinstruction(x86.SALW(ci, mr)) +} + +// SALW: Arithmetic Shift Left. +// +// Forms: +// +// SALW 1 m16 +// SALW 1 r16 +// SALW cl m16 +// SALW cl r16 +// SALW imm8 m16 +// SALW imm8 r16 +// Construct and append a SALW instruction to the active function. +// Operates on the global context. +func SALW(ci, mr operand.Op) { ctx.SALW(ci, mr) } + +// SARB: Arithmetic Shift Right. +// +// Forms: +// +// SARB 1 m8 +// SARB 1 r8 +// SARB cl m8 +// SARB cl r8 +// SARB imm8 m8 +// SARB imm8 r8 +// Construct and append a SARB instruction to the active function. +func (c *Context) SARB(ci, mr operand.Op) { + c.addinstruction(x86.SARB(ci, mr)) +} + +// SARB: Arithmetic Shift Right. +// +// Forms: +// +// SARB 1 m8 +// SARB 1 r8 +// SARB cl m8 +// SARB cl r8 +// SARB imm8 m8 +// SARB imm8 r8 +// Construct and append a SARB instruction to the active function. +// Operates on the global context. +func SARB(ci, mr operand.Op) { ctx.SARB(ci, mr) } + +// SARL: Arithmetic Shift Right. +// +// Forms: +// +// SARL 1 m32 +// SARL 1 r32 +// SARL cl m32 +// SARL cl r32 +// SARL imm8 m32 +// SARL imm8 r32 +// Construct and append a SARL instruction to the active function. +func (c *Context) SARL(ci, mr operand.Op) { + c.addinstruction(x86.SARL(ci, mr)) +} + +// SARL: Arithmetic Shift Right. +// +// Forms: +// +// SARL 1 m32 +// SARL 1 r32 +// SARL cl m32 +// SARL cl r32 +// SARL imm8 m32 +// SARL imm8 r32 +// Construct and append a SARL instruction to the active function. +// Operates on the global context. +func SARL(ci, mr operand.Op) { ctx.SARL(ci, mr) } + +// SARQ: Arithmetic Shift Right. +// +// Forms: +// +// SARQ 1 m64 +// SARQ 1 r64 +// SARQ cl m64 +// SARQ cl r64 +// SARQ imm8 m64 +// SARQ imm8 r64 +// Construct and append a SARQ instruction to the active function. +func (c *Context) SARQ(ci, mr operand.Op) { + c.addinstruction(x86.SARQ(ci, mr)) +} + +// SARQ: Arithmetic Shift Right. +// +// Forms: +// +// SARQ 1 m64 +// SARQ 1 r64 +// SARQ cl m64 +// SARQ cl r64 +// SARQ imm8 m64 +// SARQ imm8 r64 +// Construct and append a SARQ instruction to the active function. +// Operates on the global context. +func SARQ(ci, mr operand.Op) { ctx.SARQ(ci, mr) } + +// SARW: Arithmetic Shift Right. +// +// Forms: +// +// SARW 1 m16 +// SARW 1 r16 +// SARW cl m16 +// SARW cl r16 +// SARW imm8 m16 +// SARW imm8 r16 +// Construct and append a SARW instruction to the active function. +func (c *Context) SARW(ci, mr operand.Op) { + c.addinstruction(x86.SARW(ci, mr)) +} + +// SARW: Arithmetic Shift Right. +// +// Forms: +// +// SARW 1 m16 +// SARW 1 r16 +// SARW cl m16 +// SARW cl r16 +// SARW imm8 m16 +// SARW imm8 r16 +// Construct and append a SARW instruction to the active function. +// Operates on the global context. +func SARW(ci, mr operand.Op) { ctx.SARW(ci, mr) } + +// SARXL: Arithmetic Shift Right Without Affecting Flags. +// +// Forms: +// +// SARXL r32 m32 r32 +// SARXL r32 r32 r32 +// Construct and append a SARXL instruction to the active function. +func (c *Context) SARXL(r, mr, r1 operand.Op) { + c.addinstruction(x86.SARXL(r, mr, r1)) +} + +// SARXL: Arithmetic Shift Right Without Affecting Flags. +// +// Forms: +// +// SARXL r32 m32 r32 +// SARXL r32 r32 r32 +// Construct and append a SARXL instruction to the active function. +// Operates on the global context. +func SARXL(r, mr, r1 operand.Op) { ctx.SARXL(r, mr, r1) } + +// SARXQ: Arithmetic Shift Right Without Affecting Flags. +// +// Forms: +// +// SARXQ r64 m64 r64 +// SARXQ r64 r64 r64 +// Construct and append a SARXQ instruction to the active function. +func (c *Context) SARXQ(r, mr, r1 operand.Op) { + c.addinstruction(x86.SARXQ(r, mr, r1)) +} + +// SARXQ: Arithmetic Shift Right Without Affecting Flags. +// +// Forms: +// +// SARXQ r64 m64 r64 +// SARXQ r64 r64 r64 +// Construct and append a SARXQ instruction to the active function. +// Operates on the global context. +func SARXQ(r, mr, r1 operand.Op) { ctx.SARXQ(r, mr, r1) } + +// SBBB: Subtract with Borrow. +// +// Forms: +// +// SBBB imm8 al +// SBBB imm8 m8 +// SBBB imm8 r8 +// SBBB m8 r8 +// SBBB r8 m8 +// SBBB r8 r8 +// Construct and append a SBBB instruction to the active function. +func (c *Context) SBBB(imr, amr operand.Op) { + c.addinstruction(x86.SBBB(imr, amr)) +} + +// SBBB: Subtract with Borrow. +// +// Forms: +// +// SBBB imm8 al +// SBBB imm8 m8 +// SBBB imm8 r8 +// SBBB m8 r8 +// SBBB r8 m8 +// SBBB r8 r8 +// Construct and append a SBBB instruction to the active function. +// Operates on the global context. +func SBBB(imr, amr operand.Op) { ctx.SBBB(imr, amr) } + +// SBBL: Subtract with Borrow. +// +// Forms: +// +// SBBL imm32 eax +// SBBL imm32 m32 +// SBBL imm32 r32 +// SBBL imm8 m32 +// SBBL imm8 r32 +// SBBL m32 r32 +// SBBL r32 m32 +// SBBL r32 r32 +// Construct and append a SBBL instruction to the active function. +func (c *Context) SBBL(imr, emr operand.Op) { + c.addinstruction(x86.SBBL(imr, emr)) +} + +// SBBL: Subtract with Borrow. +// +// Forms: +// +// SBBL imm32 eax +// SBBL imm32 m32 +// SBBL imm32 r32 +// SBBL imm8 m32 +// SBBL imm8 r32 +// SBBL m32 r32 +// SBBL r32 m32 +// SBBL r32 r32 +// Construct and append a SBBL instruction to the active function. +// Operates on the global context. +func SBBL(imr, emr operand.Op) { ctx.SBBL(imr, emr) } + +// SBBQ: Subtract with Borrow. +// +// Forms: +// +// SBBQ imm32 m64 +// SBBQ imm32 r64 +// SBBQ imm32 rax +// SBBQ imm8 m64 +// SBBQ imm8 r64 +// SBBQ m64 r64 +// SBBQ r64 m64 +// SBBQ r64 r64 +// Construct and append a SBBQ instruction to the active function. +func (c *Context) SBBQ(imr, mr operand.Op) { + c.addinstruction(x86.SBBQ(imr, mr)) +} + +// SBBQ: Subtract with Borrow. +// +// Forms: +// +// SBBQ imm32 m64 +// SBBQ imm32 r64 +// SBBQ imm32 rax +// SBBQ imm8 m64 +// SBBQ imm8 r64 +// SBBQ m64 r64 +// SBBQ r64 m64 +// SBBQ r64 r64 +// Construct and append a SBBQ instruction to the active function. +// Operates on the global context. +func SBBQ(imr, mr operand.Op) { ctx.SBBQ(imr, mr) } + +// SBBW: Subtract with Borrow. +// +// Forms: +// +// SBBW imm16 ax +// SBBW imm16 m16 +// SBBW imm16 r16 +// SBBW imm8 m16 +// SBBW imm8 r16 +// SBBW m16 r16 +// SBBW r16 m16 +// SBBW r16 r16 +// Construct and append a SBBW instruction to the active function. +func (c *Context) SBBW(imr, amr operand.Op) { + c.addinstruction(x86.SBBW(imr, amr)) +} + +// SBBW: Subtract with Borrow. +// +// Forms: +// +// SBBW imm16 ax +// SBBW imm16 m16 +// SBBW imm16 r16 +// SBBW imm8 m16 +// SBBW imm8 r16 +// SBBW m16 r16 +// SBBW r16 m16 +// SBBW r16 r16 +// Construct and append a SBBW instruction to the active function. +// Operates on the global context. +func SBBW(imr, amr operand.Op) { ctx.SBBW(imr, amr) } + +// SETCC: Set byte if above or equal (CF == 0). +// +// Forms: +// +// SETCC m8 +// SETCC r8 +// Construct and append a SETCC instruction to the active function. +func (c *Context) SETCC(mr operand.Op) { + c.addinstruction(x86.SETCC(mr)) +} + +// SETCC: Set byte if above or equal (CF == 0). +// +// Forms: +// +// SETCC m8 +// SETCC r8 +// Construct and append a SETCC instruction to the active function. +// Operates on the global context. +func SETCC(mr operand.Op) { ctx.SETCC(mr) } + +// SETCS: Set byte if below (CF == 1). +// +// Forms: +// +// SETCS m8 +// SETCS r8 +// Construct and append a SETCS instruction to the active function. +func (c *Context) SETCS(mr operand.Op) { + c.addinstruction(x86.SETCS(mr)) +} + +// SETCS: Set byte if below (CF == 1). +// +// Forms: +// +// SETCS m8 +// SETCS r8 +// Construct and append a SETCS instruction to the active function. +// Operates on the global context. +func SETCS(mr operand.Op) { ctx.SETCS(mr) } + +// SETEQ: Set byte if equal (ZF == 1). +// +// Forms: +// +// SETEQ m8 +// SETEQ r8 +// Construct and append a SETEQ instruction to the active function. +func (c *Context) SETEQ(mr operand.Op) { + c.addinstruction(x86.SETEQ(mr)) +} + +// SETEQ: Set byte if equal (ZF == 1). +// +// Forms: +// +// SETEQ m8 +// SETEQ r8 +// Construct and append a SETEQ instruction to the active function. +// Operates on the global context. +func SETEQ(mr operand.Op) { ctx.SETEQ(mr) } + +// SETGE: Set byte if greater or equal (SF == OF). +// +// Forms: +// +// SETGE m8 +// SETGE r8 +// Construct and append a SETGE instruction to the active function. +func (c *Context) SETGE(mr operand.Op) { + c.addinstruction(x86.SETGE(mr)) +} + +// SETGE: Set byte if greater or equal (SF == OF). +// +// Forms: +// +// SETGE m8 +// SETGE r8 +// Construct and append a SETGE instruction to the active function. +// Operates on the global context. +func SETGE(mr operand.Op) { ctx.SETGE(mr) } + +// SETGT: Set byte if greater (ZF == 0 and SF == OF). +// +// Forms: +// +// SETGT m8 +// SETGT r8 +// Construct and append a SETGT instruction to the active function. +func (c *Context) SETGT(mr operand.Op) { + c.addinstruction(x86.SETGT(mr)) +} + +// SETGT: Set byte if greater (ZF == 0 and SF == OF). +// +// Forms: +// +// SETGT m8 +// SETGT r8 +// Construct and append a SETGT instruction to the active function. +// Operates on the global context. +func SETGT(mr operand.Op) { ctx.SETGT(mr) } + +// SETHI: Set byte if above (CF == 0 and ZF == 0). +// +// Forms: +// +// SETHI m8 +// SETHI r8 +// Construct and append a SETHI instruction to the active function. +func (c *Context) SETHI(mr operand.Op) { + c.addinstruction(x86.SETHI(mr)) +} + +// SETHI: Set byte if above (CF == 0 and ZF == 0). +// +// Forms: +// +// SETHI m8 +// SETHI r8 +// Construct and append a SETHI instruction to the active function. +// Operates on the global context. +func SETHI(mr operand.Op) { ctx.SETHI(mr) } + +// SETLE: Set byte if less or equal (ZF == 1 or SF != OF). +// +// Forms: +// +// SETLE m8 +// SETLE r8 +// Construct and append a SETLE instruction to the active function. +func (c *Context) SETLE(mr operand.Op) { + c.addinstruction(x86.SETLE(mr)) +} + +// SETLE: Set byte if less or equal (ZF == 1 or SF != OF). +// +// Forms: +// +// SETLE m8 +// SETLE r8 +// Construct and append a SETLE instruction to the active function. +// Operates on the global context. +func SETLE(mr operand.Op) { ctx.SETLE(mr) } + +// SETLS: Set byte if below or equal (CF == 1 or ZF == 1). +// +// Forms: +// +// SETLS m8 +// SETLS r8 +// Construct and append a SETLS instruction to the active function. +func (c *Context) SETLS(mr operand.Op) { + c.addinstruction(x86.SETLS(mr)) +} + +// SETLS: Set byte if below or equal (CF == 1 or ZF == 1). +// +// Forms: +// +// SETLS m8 +// SETLS r8 +// Construct and append a SETLS instruction to the active function. +// Operates on the global context. +func SETLS(mr operand.Op) { ctx.SETLS(mr) } + +// SETLT: Set byte if less (SF != OF). +// +// Forms: +// +// SETLT m8 +// SETLT r8 +// Construct and append a SETLT instruction to the active function. +func (c *Context) SETLT(mr operand.Op) { + c.addinstruction(x86.SETLT(mr)) +} + +// SETLT: Set byte if less (SF != OF). +// +// Forms: +// +// SETLT m8 +// SETLT r8 +// Construct and append a SETLT instruction to the active function. +// Operates on the global context. +func SETLT(mr operand.Op) { ctx.SETLT(mr) } + +// SETMI: Set byte if sign (SF == 1). +// +// Forms: +// +// SETMI m8 +// SETMI r8 +// Construct and append a SETMI instruction to the active function. +func (c *Context) SETMI(mr operand.Op) { + c.addinstruction(x86.SETMI(mr)) +} + +// SETMI: Set byte if sign (SF == 1). +// +// Forms: +// +// SETMI m8 +// SETMI r8 +// Construct and append a SETMI instruction to the active function. +// Operates on the global context. +func SETMI(mr operand.Op) { ctx.SETMI(mr) } + +// SETNE: Set byte if not equal (ZF == 0). +// +// Forms: +// +// SETNE m8 +// SETNE r8 +// Construct and append a SETNE instruction to the active function. +func (c *Context) SETNE(mr operand.Op) { + c.addinstruction(x86.SETNE(mr)) +} + +// SETNE: Set byte if not equal (ZF == 0). +// +// Forms: +// +// SETNE m8 +// SETNE r8 +// Construct and append a SETNE instruction to the active function. +// Operates on the global context. +func SETNE(mr operand.Op) { ctx.SETNE(mr) } + +// SETOC: Set byte if not overflow (OF == 0). +// +// Forms: +// +// SETOC m8 +// SETOC r8 +// Construct and append a SETOC instruction to the active function. +func (c *Context) SETOC(mr operand.Op) { + c.addinstruction(x86.SETOC(mr)) +} + +// SETOC: Set byte if not overflow (OF == 0). +// +// Forms: +// +// SETOC m8 +// SETOC r8 +// Construct and append a SETOC instruction to the active function. +// Operates on the global context. +func SETOC(mr operand.Op) { ctx.SETOC(mr) } + +// SETOS: Set byte if overflow (OF == 1). +// +// Forms: +// +// SETOS m8 +// SETOS r8 +// Construct and append a SETOS instruction to the active function. +func (c *Context) SETOS(mr operand.Op) { + c.addinstruction(x86.SETOS(mr)) +} + +// SETOS: Set byte if overflow (OF == 1). +// +// Forms: +// +// SETOS m8 +// SETOS r8 +// Construct and append a SETOS instruction to the active function. +// Operates on the global context. +func SETOS(mr operand.Op) { ctx.SETOS(mr) } + +// SETPC: Set byte if not parity (PF == 0). +// +// Forms: +// +// SETPC m8 +// SETPC r8 +// Construct and append a SETPC instruction to the active function. +func (c *Context) SETPC(mr operand.Op) { + c.addinstruction(x86.SETPC(mr)) +} + +// SETPC: Set byte if not parity (PF == 0). +// +// Forms: +// +// SETPC m8 +// SETPC r8 +// Construct and append a SETPC instruction to the active function. +// Operates on the global context. +func SETPC(mr operand.Op) { ctx.SETPC(mr) } + +// SETPL: Set byte if not sign (SF == 0). +// +// Forms: +// +// SETPL m8 +// SETPL r8 +// Construct and append a SETPL instruction to the active function. +func (c *Context) SETPL(mr operand.Op) { + c.addinstruction(x86.SETPL(mr)) +} + +// SETPL: Set byte if not sign (SF == 0). +// +// Forms: +// +// SETPL m8 +// SETPL r8 +// Construct and append a SETPL instruction to the active function. +// Operates on the global context. +func SETPL(mr operand.Op) { ctx.SETPL(mr) } + +// SETPS: Set byte if parity (PF == 1). +// +// Forms: +// +// SETPS m8 +// SETPS r8 +// Construct and append a SETPS instruction to the active function. +func (c *Context) SETPS(mr operand.Op) { + c.addinstruction(x86.SETPS(mr)) +} + +// SETPS: Set byte if parity (PF == 1). +// +// Forms: +// +// SETPS m8 +// SETPS r8 +// Construct and append a SETPS instruction to the active function. +// Operates on the global context. +func SETPS(mr operand.Op) { ctx.SETPS(mr) } + +// SFENCE: Store Fence. +// +// Forms: +// +// SFENCE +// Construct and append a SFENCE instruction to the active function. +func (c *Context) SFENCE() { + c.addinstruction(x86.SFENCE()) +} + +// SFENCE: Store Fence. +// +// Forms: +// +// SFENCE +// Construct and append a SFENCE instruction to the active function. +// Operates on the global context. +func SFENCE() { ctx.SFENCE() } + +// SHA1MSG1: Perform an Intermediate Calculation for the Next Four SHA1 Message Doublewords. +// +// Forms: +// +// SHA1MSG1 m128 xmm +// SHA1MSG1 xmm xmm +// Construct and append a SHA1MSG1 instruction to the active function. +func (c *Context) SHA1MSG1(mx, x operand.Op) { + c.addinstruction(x86.SHA1MSG1(mx, x)) +} + +// SHA1MSG1: Perform an Intermediate Calculation for the Next Four SHA1 Message Doublewords. +// +// Forms: +// +// SHA1MSG1 m128 xmm +// SHA1MSG1 xmm xmm +// Construct and append a SHA1MSG1 instruction to the active function. +// Operates on the global context. +func SHA1MSG1(mx, x operand.Op) { ctx.SHA1MSG1(mx, x) } + +// SHA1MSG2: Perform a Final Calculation for the Next Four SHA1 Message Doublewords. +// +// Forms: +// +// SHA1MSG2 m128 xmm +// SHA1MSG2 xmm xmm +// Construct and append a SHA1MSG2 instruction to the active function. +func (c *Context) SHA1MSG2(mx, x operand.Op) { + c.addinstruction(x86.SHA1MSG2(mx, x)) +} + +// SHA1MSG2: Perform a Final Calculation for the Next Four SHA1 Message Doublewords. +// +// Forms: +// +// SHA1MSG2 m128 xmm +// SHA1MSG2 xmm xmm +// Construct and append a SHA1MSG2 instruction to the active function. +// Operates on the global context. +func SHA1MSG2(mx, x operand.Op) { ctx.SHA1MSG2(mx, x) } + +// SHA1NEXTE: Calculate SHA1 State Variable E after Four Rounds. +// +// Forms: +// +// SHA1NEXTE m128 xmm +// SHA1NEXTE xmm xmm +// Construct and append a SHA1NEXTE instruction to the active function. +func (c *Context) SHA1NEXTE(mx, x operand.Op) { + c.addinstruction(x86.SHA1NEXTE(mx, x)) +} + +// SHA1NEXTE: Calculate SHA1 State Variable E after Four Rounds. +// +// Forms: +// +// SHA1NEXTE m128 xmm +// SHA1NEXTE xmm xmm +// Construct and append a SHA1NEXTE instruction to the active function. +// Operates on the global context. +func SHA1NEXTE(mx, x operand.Op) { ctx.SHA1NEXTE(mx, x) } + +// SHA1RNDS4: Perform Four Rounds of SHA1 Operation. +// +// Forms: +// +// SHA1RNDS4 imm2u m128 xmm +// SHA1RNDS4 imm2u xmm xmm +// Construct and append a SHA1RNDS4 instruction to the active function. +func (c *Context) SHA1RNDS4(i, mx, x operand.Op) { + c.addinstruction(x86.SHA1RNDS4(i, mx, x)) +} + +// SHA1RNDS4: Perform Four Rounds of SHA1 Operation. +// +// Forms: +// +// SHA1RNDS4 imm2u m128 xmm +// SHA1RNDS4 imm2u xmm xmm +// Construct and append a SHA1RNDS4 instruction to the active function. +// Operates on the global context. +func SHA1RNDS4(i, mx, x operand.Op) { ctx.SHA1RNDS4(i, mx, x) } + +// SHA256MSG1: Perform an Intermediate Calculation for the Next Four SHA256 Message Doublewords. +// +// Forms: +// +// SHA256MSG1 m128 xmm +// SHA256MSG1 xmm xmm +// Construct and append a SHA256MSG1 instruction to the active function. +func (c *Context) SHA256MSG1(mx, x operand.Op) { + c.addinstruction(x86.SHA256MSG1(mx, x)) +} + +// SHA256MSG1: Perform an Intermediate Calculation for the Next Four SHA256 Message Doublewords. +// +// Forms: +// +// SHA256MSG1 m128 xmm +// SHA256MSG1 xmm xmm +// Construct and append a SHA256MSG1 instruction to the active function. +// Operates on the global context. +func SHA256MSG1(mx, x operand.Op) { ctx.SHA256MSG1(mx, x) } + +// SHA256MSG2: Perform a Final Calculation for the Next Four SHA256 Message Doublewords. +// +// Forms: +// +// SHA256MSG2 m128 xmm +// SHA256MSG2 xmm xmm +// Construct and append a SHA256MSG2 instruction to the active function. +func (c *Context) SHA256MSG2(mx, x operand.Op) { + c.addinstruction(x86.SHA256MSG2(mx, x)) +} + +// SHA256MSG2: Perform a Final Calculation for the Next Four SHA256 Message Doublewords. +// +// Forms: +// +// SHA256MSG2 m128 xmm +// SHA256MSG2 xmm xmm +// Construct and append a SHA256MSG2 instruction to the active function. +// Operates on the global context. +func SHA256MSG2(mx, x operand.Op) { ctx.SHA256MSG2(mx, x) } + +// SHA256RNDS2: Perform Two Rounds of SHA256 Operation. +// +// Forms: +// +// SHA256RNDS2 xmm0 m128 xmm +// SHA256RNDS2 xmm0 xmm xmm +// Construct and append a SHA256RNDS2 instruction to the active function. +func (c *Context) SHA256RNDS2(x, mx, x1 operand.Op) { + c.addinstruction(x86.SHA256RNDS2(x, mx, x1)) +} + +// SHA256RNDS2: Perform Two Rounds of SHA256 Operation. +// +// Forms: +// +// SHA256RNDS2 xmm0 m128 xmm +// SHA256RNDS2 xmm0 xmm xmm +// Construct and append a SHA256RNDS2 instruction to the active function. +// Operates on the global context. +func SHA256RNDS2(x, mx, x1 operand.Op) { ctx.SHA256RNDS2(x, mx, x1) } + +// SHLB: Logical Shift Left. +// +// Forms: +// +// SHLB 1 m8 +// SHLB 1 r8 +// SHLB cl m8 +// SHLB cl r8 +// SHLB imm8 m8 +// SHLB imm8 r8 +// Construct and append a SHLB instruction to the active function. +func (c *Context) SHLB(ci, mr operand.Op) { + c.addinstruction(x86.SHLB(ci, mr)) +} + +// SHLB: Logical Shift Left. +// +// Forms: +// +// SHLB 1 m8 +// SHLB 1 r8 +// SHLB cl m8 +// SHLB cl r8 +// SHLB imm8 m8 +// SHLB imm8 r8 +// Construct and append a SHLB instruction to the active function. +// Operates on the global context. +func SHLB(ci, mr operand.Op) { ctx.SHLB(ci, mr) } + +// SHLL: Logical Shift Left. +// +// Forms: +// +// SHLL 1 m32 +// SHLL 1 r32 +// SHLL cl m32 +// SHLL cl r32 +// SHLL cl r32 m32 +// SHLL cl r32 r32 +// SHLL imm8 m32 +// SHLL imm8 r32 +// SHLL imm8 r32 m32 +// SHLL imm8 r32 r32 +// Construct and append a SHLL instruction to the active function. +func (c *Context) SHLL(ops ...operand.Op) { + c.addinstruction(x86.SHLL(ops...)) +} + +// SHLL: Logical Shift Left. +// +// Forms: +// +// SHLL 1 m32 +// SHLL 1 r32 +// SHLL cl m32 +// SHLL cl r32 +// SHLL cl r32 m32 +// SHLL cl r32 r32 +// SHLL imm8 m32 +// SHLL imm8 r32 +// SHLL imm8 r32 m32 +// SHLL imm8 r32 r32 +// Construct and append a SHLL instruction to the active function. +// Operates on the global context. +func SHLL(ops ...operand.Op) { ctx.SHLL(ops...) } + +// SHLQ: Logical Shift Left. +// +// Forms: +// +// SHLQ 1 m64 +// SHLQ 1 r64 +// SHLQ cl m64 +// SHLQ cl r64 +// SHLQ cl r64 m64 +// SHLQ cl r64 r64 +// SHLQ imm8 m64 +// SHLQ imm8 r64 +// SHLQ imm8 r64 m64 +// SHLQ imm8 r64 r64 +// Construct and append a SHLQ instruction to the active function. +func (c *Context) SHLQ(ops ...operand.Op) { + c.addinstruction(x86.SHLQ(ops...)) +} + +// SHLQ: Logical Shift Left. +// +// Forms: +// +// SHLQ 1 m64 +// SHLQ 1 r64 +// SHLQ cl m64 +// SHLQ cl r64 +// SHLQ cl r64 m64 +// SHLQ cl r64 r64 +// SHLQ imm8 m64 +// SHLQ imm8 r64 +// SHLQ imm8 r64 m64 +// SHLQ imm8 r64 r64 +// Construct and append a SHLQ instruction to the active function. +// Operates on the global context. +func SHLQ(ops ...operand.Op) { ctx.SHLQ(ops...) } + +// SHLW: Logical Shift Left. +// +// Forms: +// +// SHLW 1 m16 +// SHLW 1 r16 +// SHLW cl m16 +// SHLW cl r16 +// SHLW cl r16 m16 +// SHLW cl r16 r16 +// SHLW imm8 m16 +// SHLW imm8 r16 +// SHLW imm8 r16 m16 +// SHLW imm8 r16 r16 +// Construct and append a SHLW instruction to the active function. +func (c *Context) SHLW(ops ...operand.Op) { + c.addinstruction(x86.SHLW(ops...)) +} + +// SHLW: Logical Shift Left. +// +// Forms: +// +// SHLW 1 m16 +// SHLW 1 r16 +// SHLW cl m16 +// SHLW cl r16 +// SHLW cl r16 m16 +// SHLW cl r16 r16 +// SHLW imm8 m16 +// SHLW imm8 r16 +// SHLW imm8 r16 m16 +// SHLW imm8 r16 r16 +// Construct and append a SHLW instruction to the active function. +// Operates on the global context. +func SHLW(ops ...operand.Op) { ctx.SHLW(ops...) } + +// SHLXL: Logical Shift Left Without Affecting Flags. +// +// Forms: +// +// SHLXL r32 m32 r32 +// SHLXL r32 r32 r32 +// Construct and append a SHLXL instruction to the active function. +func (c *Context) SHLXL(r, mr, r1 operand.Op) { + c.addinstruction(x86.SHLXL(r, mr, r1)) +} + +// SHLXL: Logical Shift Left Without Affecting Flags. +// +// Forms: +// +// SHLXL r32 m32 r32 +// SHLXL r32 r32 r32 +// Construct and append a SHLXL instruction to the active function. +// Operates on the global context. +func SHLXL(r, mr, r1 operand.Op) { ctx.SHLXL(r, mr, r1) } + +// SHLXQ: Logical Shift Left Without Affecting Flags. +// +// Forms: +// +// SHLXQ r64 m64 r64 +// SHLXQ r64 r64 r64 +// Construct and append a SHLXQ instruction to the active function. +func (c *Context) SHLXQ(r, mr, r1 operand.Op) { + c.addinstruction(x86.SHLXQ(r, mr, r1)) +} + +// SHLXQ: Logical Shift Left Without Affecting Flags. +// +// Forms: +// +// SHLXQ r64 m64 r64 +// SHLXQ r64 r64 r64 +// Construct and append a SHLXQ instruction to the active function. +// Operates on the global context. +func SHLXQ(r, mr, r1 operand.Op) { ctx.SHLXQ(r, mr, r1) } + +// SHRB: Logical Shift Right. +// +// Forms: +// +// SHRB 1 m8 +// SHRB 1 r8 +// SHRB cl m8 +// SHRB cl r8 +// SHRB imm8 m8 +// SHRB imm8 r8 +// Construct and append a SHRB instruction to the active function. +func (c *Context) SHRB(ci, mr operand.Op) { + c.addinstruction(x86.SHRB(ci, mr)) +} + +// SHRB: Logical Shift Right. +// +// Forms: +// +// SHRB 1 m8 +// SHRB 1 r8 +// SHRB cl m8 +// SHRB cl r8 +// SHRB imm8 m8 +// SHRB imm8 r8 +// Construct and append a SHRB instruction to the active function. +// Operates on the global context. +func SHRB(ci, mr operand.Op) { ctx.SHRB(ci, mr) } + +// SHRL: Logical Shift Right. +// +// Forms: +// +// SHRL 1 m32 +// SHRL 1 r32 +// SHRL cl m32 +// SHRL cl r32 +// SHRL cl r32 m32 +// SHRL cl r32 r32 +// SHRL imm8 m32 +// SHRL imm8 r32 +// SHRL imm8 r32 m32 +// SHRL imm8 r32 r32 +// Construct and append a SHRL instruction to the active function. +func (c *Context) SHRL(ops ...operand.Op) { + c.addinstruction(x86.SHRL(ops...)) +} + +// SHRL: Logical Shift Right. +// +// Forms: +// +// SHRL 1 m32 +// SHRL 1 r32 +// SHRL cl m32 +// SHRL cl r32 +// SHRL cl r32 m32 +// SHRL cl r32 r32 +// SHRL imm8 m32 +// SHRL imm8 r32 +// SHRL imm8 r32 m32 +// SHRL imm8 r32 r32 +// Construct and append a SHRL instruction to the active function. +// Operates on the global context. +func SHRL(ops ...operand.Op) { ctx.SHRL(ops...) } + +// SHRQ: Logical Shift Right. +// +// Forms: +// +// SHRQ 1 m64 +// SHRQ 1 r64 +// SHRQ cl m64 +// SHRQ cl r64 +// SHRQ cl r64 m64 +// SHRQ cl r64 r64 +// SHRQ imm8 m64 +// SHRQ imm8 r64 +// SHRQ imm8 r64 m64 +// SHRQ imm8 r64 r64 +// Construct and append a SHRQ instruction to the active function. +func (c *Context) SHRQ(ops ...operand.Op) { + c.addinstruction(x86.SHRQ(ops...)) +} + +// SHRQ: Logical Shift Right. +// +// Forms: +// +// SHRQ 1 m64 +// SHRQ 1 r64 +// SHRQ cl m64 +// SHRQ cl r64 +// SHRQ cl r64 m64 +// SHRQ cl r64 r64 +// SHRQ imm8 m64 +// SHRQ imm8 r64 +// SHRQ imm8 r64 m64 +// SHRQ imm8 r64 r64 +// Construct and append a SHRQ instruction to the active function. +// Operates on the global context. +func SHRQ(ops ...operand.Op) { ctx.SHRQ(ops...) } + +// SHRW: Logical Shift Right. +// +// Forms: +// +// SHRW 1 m16 +// SHRW 1 r16 +// SHRW cl m16 +// SHRW cl r16 +// SHRW cl r16 m16 +// SHRW cl r16 r16 +// SHRW imm8 m16 +// SHRW imm8 r16 +// SHRW imm8 r16 m16 +// SHRW imm8 r16 r16 +// Construct and append a SHRW instruction to the active function. +func (c *Context) SHRW(ops ...operand.Op) { + c.addinstruction(x86.SHRW(ops...)) +} + +// SHRW: Logical Shift Right. +// +// Forms: +// +// SHRW 1 m16 +// SHRW 1 r16 +// SHRW cl m16 +// SHRW cl r16 +// SHRW cl r16 m16 +// SHRW cl r16 r16 +// SHRW imm8 m16 +// SHRW imm8 r16 +// SHRW imm8 r16 m16 +// SHRW imm8 r16 r16 +// Construct and append a SHRW instruction to the active function. +// Operates on the global context. +func SHRW(ops ...operand.Op) { ctx.SHRW(ops...) } + +// SHRXL: Logical Shift Right Without Affecting Flags. +// +// Forms: +// +// SHRXL r32 m32 r32 +// SHRXL r32 r32 r32 +// Construct and append a SHRXL instruction to the active function. +func (c *Context) SHRXL(r, mr, r1 operand.Op) { + c.addinstruction(x86.SHRXL(r, mr, r1)) +} + +// SHRXL: Logical Shift Right Without Affecting Flags. +// +// Forms: +// +// SHRXL r32 m32 r32 +// SHRXL r32 r32 r32 +// Construct and append a SHRXL instruction to the active function. +// Operates on the global context. +func SHRXL(r, mr, r1 operand.Op) { ctx.SHRXL(r, mr, r1) } + +// SHRXQ: Logical Shift Right Without Affecting Flags. +// +// Forms: +// +// SHRXQ r64 m64 r64 +// SHRXQ r64 r64 r64 +// Construct and append a SHRXQ instruction to the active function. +func (c *Context) SHRXQ(r, mr, r1 operand.Op) { + c.addinstruction(x86.SHRXQ(r, mr, r1)) +} + +// SHRXQ: Logical Shift Right Without Affecting Flags. +// +// Forms: +// +// SHRXQ r64 m64 r64 +// SHRXQ r64 r64 r64 +// Construct and append a SHRXQ instruction to the active function. +// Operates on the global context. +func SHRXQ(r, mr, r1 operand.Op) { ctx.SHRXQ(r, mr, r1) } + +// SHUFPD: Shuffle Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// SHUFPD imm8 m128 xmm +// SHUFPD imm8 xmm xmm +// Construct and append a SHUFPD instruction to the active function. +func (c *Context) SHUFPD(i, mx, x operand.Op) { + c.addinstruction(x86.SHUFPD(i, mx, x)) +} + +// SHUFPD: Shuffle Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// SHUFPD imm8 m128 xmm +// SHUFPD imm8 xmm xmm +// Construct and append a SHUFPD instruction to the active function. +// Operates on the global context. +func SHUFPD(i, mx, x operand.Op) { ctx.SHUFPD(i, mx, x) } + +// SHUFPS: Shuffle Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// SHUFPS imm8 m128 xmm +// SHUFPS imm8 xmm xmm +// Construct and append a SHUFPS instruction to the active function. +func (c *Context) SHUFPS(i, mx, x operand.Op) { + c.addinstruction(x86.SHUFPS(i, mx, x)) +} + +// SHUFPS: Shuffle Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// SHUFPS imm8 m128 xmm +// SHUFPS imm8 xmm xmm +// Construct and append a SHUFPS instruction to the active function. +// Operates on the global context. +func SHUFPS(i, mx, x operand.Op) { ctx.SHUFPS(i, mx, x) } + +// SQRTPD: Compute Square Roots of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// SQRTPD m128 xmm +// SQRTPD xmm xmm +// Construct and append a SQRTPD instruction to the active function. +func (c *Context) SQRTPD(mx, x operand.Op) { + c.addinstruction(x86.SQRTPD(mx, x)) +} + +// SQRTPD: Compute Square Roots of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// SQRTPD m128 xmm +// SQRTPD xmm xmm +// Construct and append a SQRTPD instruction to the active function. +// Operates on the global context. +func SQRTPD(mx, x operand.Op) { ctx.SQRTPD(mx, x) } + +// SQRTPS: Compute Square Roots of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// SQRTPS m128 xmm +// SQRTPS xmm xmm +// Construct and append a SQRTPS instruction to the active function. +func (c *Context) SQRTPS(mx, x operand.Op) { + c.addinstruction(x86.SQRTPS(mx, x)) +} + +// SQRTPS: Compute Square Roots of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// SQRTPS m128 xmm +// SQRTPS xmm xmm +// Construct and append a SQRTPS instruction to the active function. +// Operates on the global context. +func SQRTPS(mx, x operand.Op) { ctx.SQRTPS(mx, x) } + +// SQRTSD: Compute Square Root of Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// SQRTSD m64 xmm +// SQRTSD xmm xmm +// Construct and append a SQRTSD instruction to the active function. +func (c *Context) SQRTSD(mx, x operand.Op) { + c.addinstruction(x86.SQRTSD(mx, x)) +} + +// SQRTSD: Compute Square Root of Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// SQRTSD m64 xmm +// SQRTSD xmm xmm +// Construct and append a SQRTSD instruction to the active function. +// Operates on the global context. +func SQRTSD(mx, x operand.Op) { ctx.SQRTSD(mx, x) } + +// SQRTSS: Compute Square Root of Scalar Single-Precision Floating-Point Value. +// +// Forms: +// +// SQRTSS m32 xmm +// SQRTSS xmm xmm +// Construct and append a SQRTSS instruction to the active function. +func (c *Context) SQRTSS(mx, x operand.Op) { + c.addinstruction(x86.SQRTSS(mx, x)) +} + +// SQRTSS: Compute Square Root of Scalar Single-Precision Floating-Point Value. +// +// Forms: +// +// SQRTSS m32 xmm +// SQRTSS xmm xmm +// Construct and append a SQRTSS instruction to the active function. +// Operates on the global context. +func SQRTSS(mx, x operand.Op) { ctx.SQRTSS(mx, x) } + +// STC: Set Carry Flag. +// +// Forms: +// +// STC +// Construct and append a STC instruction to the active function. +func (c *Context) STC() { + c.addinstruction(x86.STC()) +} + +// STC: Set Carry Flag. +// +// Forms: +// +// STC +// Construct and append a STC instruction to the active function. +// Operates on the global context. +func STC() { ctx.STC() } + +// STD: Set Direction Flag. +// +// Forms: +// +// STD +// Construct and append a STD instruction to the active function. +func (c *Context) STD() { + c.addinstruction(x86.STD()) +} + +// STD: Set Direction Flag. +// +// Forms: +// +// STD +// Construct and append a STD instruction to the active function. +// Operates on the global context. +func STD() { ctx.STD() } + +// STMXCSR: Store MXCSR Register State. +// +// Forms: +// +// STMXCSR m32 +// Construct and append a STMXCSR instruction to the active function. +func (c *Context) STMXCSR(m operand.Op) { + c.addinstruction(x86.STMXCSR(m)) +} + +// STMXCSR: Store MXCSR Register State. +// +// Forms: +// +// STMXCSR m32 +// Construct and append a STMXCSR instruction to the active function. +// Operates on the global context. +func STMXCSR(m operand.Op) { ctx.STMXCSR(m) } + +// SUBB: Subtract. +// +// Forms: +// +// SUBB imm8 al +// SUBB imm8 m8 +// SUBB imm8 r8 +// SUBB m8 r8 +// SUBB r8 m8 +// SUBB r8 r8 +// Construct and append a SUBB instruction to the active function. +func (c *Context) SUBB(imr, amr operand.Op) { + c.addinstruction(x86.SUBB(imr, amr)) +} + +// SUBB: Subtract. +// +// Forms: +// +// SUBB imm8 al +// SUBB imm8 m8 +// SUBB imm8 r8 +// SUBB m8 r8 +// SUBB r8 m8 +// SUBB r8 r8 +// Construct and append a SUBB instruction to the active function. +// Operates on the global context. +func SUBB(imr, amr operand.Op) { ctx.SUBB(imr, amr) } + +// SUBL: Subtract. +// +// Forms: +// +// SUBL imm32 eax +// SUBL imm32 m32 +// SUBL imm32 r32 +// SUBL imm8 m32 +// SUBL imm8 r32 +// SUBL m32 r32 +// SUBL r32 m32 +// SUBL r32 r32 +// Construct and append a SUBL instruction to the active function. +func (c *Context) SUBL(imr, emr operand.Op) { + c.addinstruction(x86.SUBL(imr, emr)) +} + +// SUBL: Subtract. +// +// Forms: +// +// SUBL imm32 eax +// SUBL imm32 m32 +// SUBL imm32 r32 +// SUBL imm8 m32 +// SUBL imm8 r32 +// SUBL m32 r32 +// SUBL r32 m32 +// SUBL r32 r32 +// Construct and append a SUBL instruction to the active function. +// Operates on the global context. +func SUBL(imr, emr operand.Op) { ctx.SUBL(imr, emr) } + +// SUBPD: Subtract Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// SUBPD m128 xmm +// SUBPD xmm xmm +// Construct and append a SUBPD instruction to the active function. +func (c *Context) SUBPD(mx, x operand.Op) { + c.addinstruction(x86.SUBPD(mx, x)) +} + +// SUBPD: Subtract Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// SUBPD m128 xmm +// SUBPD xmm xmm +// Construct and append a SUBPD instruction to the active function. +// Operates on the global context. +func SUBPD(mx, x operand.Op) { ctx.SUBPD(mx, x) } + +// SUBPS: Subtract Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// SUBPS m128 xmm +// SUBPS xmm xmm +// Construct and append a SUBPS instruction to the active function. +func (c *Context) SUBPS(mx, x operand.Op) { + c.addinstruction(x86.SUBPS(mx, x)) +} + +// SUBPS: Subtract Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// SUBPS m128 xmm +// SUBPS xmm xmm +// Construct and append a SUBPS instruction to the active function. +// Operates on the global context. +func SUBPS(mx, x operand.Op) { ctx.SUBPS(mx, x) } + +// SUBQ: Subtract. +// +// Forms: +// +// SUBQ imm32 m64 +// SUBQ imm32 r64 +// SUBQ imm32 rax +// SUBQ imm8 m64 +// SUBQ imm8 r64 +// SUBQ m64 r64 +// SUBQ r64 m64 +// SUBQ r64 r64 +// Construct and append a SUBQ instruction to the active function. +func (c *Context) SUBQ(imr, mr operand.Op) { + c.addinstruction(x86.SUBQ(imr, mr)) +} + +// SUBQ: Subtract. +// +// Forms: +// +// SUBQ imm32 m64 +// SUBQ imm32 r64 +// SUBQ imm32 rax +// SUBQ imm8 m64 +// SUBQ imm8 r64 +// SUBQ m64 r64 +// SUBQ r64 m64 +// SUBQ r64 r64 +// Construct and append a SUBQ instruction to the active function. +// Operates on the global context. +func SUBQ(imr, mr operand.Op) { ctx.SUBQ(imr, mr) } + +// SUBSD: Subtract Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// SUBSD m64 xmm +// SUBSD xmm xmm +// Construct and append a SUBSD instruction to the active function. +func (c *Context) SUBSD(mx, x operand.Op) { + c.addinstruction(x86.SUBSD(mx, x)) +} + +// SUBSD: Subtract Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// SUBSD m64 xmm +// SUBSD xmm xmm +// Construct and append a SUBSD instruction to the active function. +// Operates on the global context. +func SUBSD(mx, x operand.Op) { ctx.SUBSD(mx, x) } + +// SUBSS: Subtract Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// SUBSS m32 xmm +// SUBSS xmm xmm +// Construct and append a SUBSS instruction to the active function. +func (c *Context) SUBSS(mx, x operand.Op) { + c.addinstruction(x86.SUBSS(mx, x)) +} + +// SUBSS: Subtract Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// SUBSS m32 xmm +// SUBSS xmm xmm +// Construct and append a SUBSS instruction to the active function. +// Operates on the global context. +func SUBSS(mx, x operand.Op) { ctx.SUBSS(mx, x) } + +// SUBW: Subtract. +// +// Forms: +// +// SUBW imm16 ax +// SUBW imm16 m16 +// SUBW imm16 r16 +// SUBW imm8 m16 +// SUBW imm8 r16 +// SUBW m16 r16 +// SUBW r16 m16 +// SUBW r16 r16 +// Construct and append a SUBW instruction to the active function. +func (c *Context) SUBW(imr, amr operand.Op) { + c.addinstruction(x86.SUBW(imr, amr)) +} + +// SUBW: Subtract. +// +// Forms: +// +// SUBW imm16 ax +// SUBW imm16 m16 +// SUBW imm16 r16 +// SUBW imm8 m16 +// SUBW imm8 r16 +// SUBW m16 r16 +// SUBW r16 m16 +// SUBW r16 r16 +// Construct and append a SUBW instruction to the active function. +// Operates on the global context. +func SUBW(imr, amr operand.Op) { ctx.SUBW(imr, amr) } + +// SYSCALL: Fast System Call. +// +// Forms: +// +// SYSCALL +// Construct and append a SYSCALL instruction to the active function. +func (c *Context) SYSCALL() { + c.addinstruction(x86.SYSCALL()) +} + +// SYSCALL: Fast System Call. +// +// Forms: +// +// SYSCALL +// Construct and append a SYSCALL instruction to the active function. +// Operates on the global context. +func SYSCALL() { ctx.SYSCALL() } + +// TESTB: Logical Compare. +// +// Forms: +// +// TESTB imm8 al +// TESTB imm8 m8 +// TESTB imm8 r8 +// TESTB r8 m8 +// TESTB r8 r8 +// Construct and append a TESTB instruction to the active function. +func (c *Context) TESTB(ir, amr operand.Op) { + c.addinstruction(x86.TESTB(ir, amr)) +} + +// TESTB: Logical Compare. +// +// Forms: +// +// TESTB imm8 al +// TESTB imm8 m8 +// TESTB imm8 r8 +// TESTB r8 m8 +// TESTB r8 r8 +// Construct and append a TESTB instruction to the active function. +// Operates on the global context. +func TESTB(ir, amr operand.Op) { ctx.TESTB(ir, amr) } + +// TESTL: Logical Compare. +// +// Forms: +// +// TESTL imm32 eax +// TESTL imm32 m32 +// TESTL imm32 r32 +// TESTL r32 m32 +// TESTL r32 r32 +// Construct and append a TESTL instruction to the active function. +func (c *Context) TESTL(ir, emr operand.Op) { + c.addinstruction(x86.TESTL(ir, emr)) +} + +// TESTL: Logical Compare. +// +// Forms: +// +// TESTL imm32 eax +// TESTL imm32 m32 +// TESTL imm32 r32 +// TESTL r32 m32 +// TESTL r32 r32 +// Construct and append a TESTL instruction to the active function. +// Operates on the global context. +func TESTL(ir, emr operand.Op) { ctx.TESTL(ir, emr) } + +// TESTQ: Logical Compare. +// +// Forms: +// +// TESTQ imm32 m64 +// TESTQ imm32 r64 +// TESTQ imm32 rax +// TESTQ r64 m64 +// TESTQ r64 r64 +// Construct and append a TESTQ instruction to the active function. +func (c *Context) TESTQ(ir, mr operand.Op) { + c.addinstruction(x86.TESTQ(ir, mr)) +} + +// TESTQ: Logical Compare. +// +// Forms: +// +// TESTQ imm32 m64 +// TESTQ imm32 r64 +// TESTQ imm32 rax +// TESTQ r64 m64 +// TESTQ r64 r64 +// Construct and append a TESTQ instruction to the active function. +// Operates on the global context. +func TESTQ(ir, mr operand.Op) { ctx.TESTQ(ir, mr) } + +// TESTW: Logical Compare. +// +// Forms: +// +// TESTW imm16 ax +// TESTW imm16 m16 +// TESTW imm16 r16 +// TESTW r16 m16 +// TESTW r16 r16 +// Construct and append a TESTW instruction to the active function. +func (c *Context) TESTW(ir, amr operand.Op) { + c.addinstruction(x86.TESTW(ir, amr)) +} + +// TESTW: Logical Compare. +// +// Forms: +// +// TESTW imm16 ax +// TESTW imm16 m16 +// TESTW imm16 r16 +// TESTW r16 m16 +// TESTW r16 r16 +// Construct and append a TESTW instruction to the active function. +// Operates on the global context. +func TESTW(ir, amr operand.Op) { ctx.TESTW(ir, amr) } + +// TZCNTL: Count the Number of Trailing Zero Bits. +// +// Forms: +// +// TZCNTL m32 r32 +// TZCNTL r32 r32 +// Construct and append a TZCNTL instruction to the active function. +func (c *Context) TZCNTL(mr, r operand.Op) { + c.addinstruction(x86.TZCNTL(mr, r)) +} + +// TZCNTL: Count the Number of Trailing Zero Bits. +// +// Forms: +// +// TZCNTL m32 r32 +// TZCNTL r32 r32 +// Construct and append a TZCNTL instruction to the active function. +// Operates on the global context. +func TZCNTL(mr, r operand.Op) { ctx.TZCNTL(mr, r) } + +// TZCNTQ: Count the Number of Trailing Zero Bits. +// +// Forms: +// +// TZCNTQ m64 r64 +// TZCNTQ r64 r64 +// Construct and append a TZCNTQ instruction to the active function. +func (c *Context) TZCNTQ(mr, r operand.Op) { + c.addinstruction(x86.TZCNTQ(mr, r)) +} + +// TZCNTQ: Count the Number of Trailing Zero Bits. +// +// Forms: +// +// TZCNTQ m64 r64 +// TZCNTQ r64 r64 +// Construct and append a TZCNTQ instruction to the active function. +// Operates on the global context. +func TZCNTQ(mr, r operand.Op) { ctx.TZCNTQ(mr, r) } + +// TZCNTW: Count the Number of Trailing Zero Bits. +// +// Forms: +// +// TZCNTW m16 r16 +// TZCNTW r16 r16 +// Construct and append a TZCNTW instruction to the active function. +func (c *Context) TZCNTW(mr, r operand.Op) { + c.addinstruction(x86.TZCNTW(mr, r)) +} + +// TZCNTW: Count the Number of Trailing Zero Bits. +// +// Forms: +// +// TZCNTW m16 r16 +// TZCNTW r16 r16 +// Construct and append a TZCNTW instruction to the active function. +// Operates on the global context. +func TZCNTW(mr, r operand.Op) { ctx.TZCNTW(mr, r) } + +// UCOMISD: Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS. +// +// Forms: +// +// UCOMISD m64 xmm +// UCOMISD xmm xmm +// Construct and append a UCOMISD instruction to the active function. +func (c *Context) UCOMISD(mx, x operand.Op) { + c.addinstruction(x86.UCOMISD(mx, x)) +} + +// UCOMISD: Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS. +// +// Forms: +// +// UCOMISD m64 xmm +// UCOMISD xmm xmm +// Construct and append a UCOMISD instruction to the active function. +// Operates on the global context. +func UCOMISD(mx, x operand.Op) { ctx.UCOMISD(mx, x) } + +// UCOMISS: Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS. +// +// Forms: +// +// UCOMISS m32 xmm +// UCOMISS xmm xmm +// Construct and append a UCOMISS instruction to the active function. +func (c *Context) UCOMISS(mx, x operand.Op) { + c.addinstruction(x86.UCOMISS(mx, x)) +} + +// UCOMISS: Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS. +// +// Forms: +// +// UCOMISS m32 xmm +// UCOMISS xmm xmm +// Construct and append a UCOMISS instruction to the active function. +// Operates on the global context. +func UCOMISS(mx, x operand.Op) { ctx.UCOMISS(mx, x) } + +// UD2: Undefined Instruction. +// +// Forms: +// +// UD2 +// Construct and append a UD2 instruction to the active function. +func (c *Context) UD2() { + c.addinstruction(x86.UD2()) +} + +// UD2: Undefined Instruction. +// +// Forms: +// +// UD2 +// Construct and append a UD2 instruction to the active function. +// Operates on the global context. +func UD2() { ctx.UD2() } + +// UNPCKHPD: Unpack and Interleave High Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// UNPCKHPD m128 xmm +// UNPCKHPD xmm xmm +// Construct and append a UNPCKHPD instruction to the active function. +func (c *Context) UNPCKHPD(mx, x operand.Op) { + c.addinstruction(x86.UNPCKHPD(mx, x)) +} + +// UNPCKHPD: Unpack and Interleave High Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// UNPCKHPD m128 xmm +// UNPCKHPD xmm xmm +// Construct and append a UNPCKHPD instruction to the active function. +// Operates on the global context. +func UNPCKHPD(mx, x operand.Op) { ctx.UNPCKHPD(mx, x) } + +// UNPCKHPS: Unpack and Interleave High Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// UNPCKHPS m128 xmm +// UNPCKHPS xmm xmm +// Construct and append a UNPCKHPS instruction to the active function. +func (c *Context) UNPCKHPS(mx, x operand.Op) { + c.addinstruction(x86.UNPCKHPS(mx, x)) +} + +// UNPCKHPS: Unpack and Interleave High Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// UNPCKHPS m128 xmm +// UNPCKHPS xmm xmm +// Construct and append a UNPCKHPS instruction to the active function. +// Operates on the global context. +func UNPCKHPS(mx, x operand.Op) { ctx.UNPCKHPS(mx, x) } + +// UNPCKLPD: Unpack and Interleave Low Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// UNPCKLPD m128 xmm +// UNPCKLPD xmm xmm +// Construct and append a UNPCKLPD instruction to the active function. +func (c *Context) UNPCKLPD(mx, x operand.Op) { + c.addinstruction(x86.UNPCKLPD(mx, x)) +} + +// UNPCKLPD: Unpack and Interleave Low Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// UNPCKLPD m128 xmm +// UNPCKLPD xmm xmm +// Construct and append a UNPCKLPD instruction to the active function. +// Operates on the global context. +func UNPCKLPD(mx, x operand.Op) { ctx.UNPCKLPD(mx, x) } + +// UNPCKLPS: Unpack and Interleave Low Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// UNPCKLPS m128 xmm +// UNPCKLPS xmm xmm +// Construct and append a UNPCKLPS instruction to the active function. +func (c *Context) UNPCKLPS(mx, x operand.Op) { + c.addinstruction(x86.UNPCKLPS(mx, x)) +} + +// UNPCKLPS: Unpack and Interleave Low Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// UNPCKLPS m128 xmm +// UNPCKLPS xmm xmm +// Construct and append a UNPCKLPS instruction to the active function. +// Operates on the global context. +func UNPCKLPS(mx, x operand.Op) { ctx.UNPCKLPS(mx, x) } + +// VADDPD: Add Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VADDPD m128 xmm xmm +// VADDPD m256 ymm ymm +// VADDPD xmm xmm xmm +// VADDPD ymm ymm ymm +// VADDPD m128 xmm k xmm +// VADDPD m256 ymm k ymm +// VADDPD xmm xmm k xmm +// VADDPD ymm ymm k ymm +// VADDPD m512 zmm k zmm +// VADDPD m512 zmm zmm +// VADDPD zmm zmm k zmm +// VADDPD zmm zmm zmm +// Construct and append a VADDPD instruction to the active function. +func (c *Context) VADDPD(ops ...operand.Op) { + c.addinstruction(x86.VADDPD(ops...)) +} + +// VADDPD: Add Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VADDPD m128 xmm xmm +// VADDPD m256 ymm ymm +// VADDPD xmm xmm xmm +// VADDPD ymm ymm ymm +// VADDPD m128 xmm k xmm +// VADDPD m256 ymm k ymm +// VADDPD xmm xmm k xmm +// VADDPD ymm ymm k ymm +// VADDPD m512 zmm k zmm +// VADDPD m512 zmm zmm +// VADDPD zmm zmm k zmm +// VADDPD zmm zmm zmm +// Construct and append a VADDPD instruction to the active function. +// Operates on the global context. +func VADDPD(ops ...operand.Op) { ctx.VADDPD(ops...) } + +// VADDPD_BCST: Add Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VADDPD.BCST m64 xmm k xmm +// VADDPD.BCST m64 xmm xmm +// VADDPD.BCST m64 ymm k ymm +// VADDPD.BCST m64 ymm ymm +// VADDPD.BCST m64 zmm k zmm +// VADDPD.BCST m64 zmm zmm +// Construct and append a VADDPD.BCST instruction to the active function. +func (c *Context) VADDPD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VADDPD_BCST(ops...)) +} + +// VADDPD_BCST: Add Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VADDPD.BCST m64 xmm k xmm +// VADDPD.BCST m64 xmm xmm +// VADDPD.BCST m64 ymm k ymm +// VADDPD.BCST m64 ymm ymm +// VADDPD.BCST m64 zmm k zmm +// VADDPD.BCST m64 zmm zmm +// Construct and append a VADDPD.BCST instruction to the active function. +// Operates on the global context. +func VADDPD_BCST(ops ...operand.Op) { ctx.VADDPD_BCST(ops...) } + +// VADDPD_BCST_Z: Add Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VADDPD.BCST.Z m64 xmm k xmm +// VADDPD.BCST.Z m64 ymm k ymm +// VADDPD.BCST.Z m64 zmm k zmm +// Construct and append a VADDPD.BCST.Z instruction to the active function. +func (c *Context) VADDPD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VADDPD_BCST_Z(m, xyz, k, xyz1)) +} + +// VADDPD_BCST_Z: Add Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VADDPD.BCST.Z m64 xmm k xmm +// VADDPD.BCST.Z m64 ymm k ymm +// VADDPD.BCST.Z m64 zmm k zmm +// Construct and append a VADDPD.BCST.Z instruction to the active function. +// Operates on the global context. +func VADDPD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VADDPD_BCST_Z(m, xyz, k, xyz1) } + +// VADDPD_RD_SAE: Add Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VADDPD.RD_SAE zmm zmm k zmm +// VADDPD.RD_SAE zmm zmm zmm +// Construct and append a VADDPD.RD_SAE instruction to the active function. +func (c *Context) VADDPD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VADDPD_RD_SAE(ops...)) +} + +// VADDPD_RD_SAE: Add Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VADDPD.RD_SAE zmm zmm k zmm +// VADDPD.RD_SAE zmm zmm zmm +// Construct and append a VADDPD.RD_SAE instruction to the active function. +// Operates on the global context. +func VADDPD_RD_SAE(ops ...operand.Op) { ctx.VADDPD_RD_SAE(ops...) } + +// VADDPD_RD_SAE_Z: Add Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VADDPD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VADDPD.RD_SAE.Z instruction to the active function. +func (c *Context) VADDPD_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VADDPD_RD_SAE_Z(z, z1, k, z2)) +} + +// VADDPD_RD_SAE_Z: Add Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VADDPD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VADDPD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VADDPD_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VADDPD_RD_SAE_Z(z, z1, k, z2) } + +// VADDPD_RN_SAE: Add Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VADDPD.RN_SAE zmm zmm k zmm +// VADDPD.RN_SAE zmm zmm zmm +// Construct and append a VADDPD.RN_SAE instruction to the active function. +func (c *Context) VADDPD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VADDPD_RN_SAE(ops...)) +} + +// VADDPD_RN_SAE: Add Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VADDPD.RN_SAE zmm zmm k zmm +// VADDPD.RN_SAE zmm zmm zmm +// Construct and append a VADDPD.RN_SAE instruction to the active function. +// Operates on the global context. +func VADDPD_RN_SAE(ops ...operand.Op) { ctx.VADDPD_RN_SAE(ops...) } + +// VADDPD_RN_SAE_Z: Add Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VADDPD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VADDPD.RN_SAE.Z instruction to the active function. +func (c *Context) VADDPD_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VADDPD_RN_SAE_Z(z, z1, k, z2)) +} + +// VADDPD_RN_SAE_Z: Add Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VADDPD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VADDPD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VADDPD_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VADDPD_RN_SAE_Z(z, z1, k, z2) } + +// VADDPD_RU_SAE: Add Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VADDPD.RU_SAE zmm zmm k zmm +// VADDPD.RU_SAE zmm zmm zmm +// Construct and append a VADDPD.RU_SAE instruction to the active function. +func (c *Context) VADDPD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VADDPD_RU_SAE(ops...)) +} + +// VADDPD_RU_SAE: Add Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VADDPD.RU_SAE zmm zmm k zmm +// VADDPD.RU_SAE zmm zmm zmm +// Construct and append a VADDPD.RU_SAE instruction to the active function. +// Operates on the global context. +func VADDPD_RU_SAE(ops ...operand.Op) { ctx.VADDPD_RU_SAE(ops...) } + +// VADDPD_RU_SAE_Z: Add Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VADDPD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VADDPD.RU_SAE.Z instruction to the active function. +func (c *Context) VADDPD_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VADDPD_RU_SAE_Z(z, z1, k, z2)) +} + +// VADDPD_RU_SAE_Z: Add Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VADDPD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VADDPD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VADDPD_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VADDPD_RU_SAE_Z(z, z1, k, z2) } + +// VADDPD_RZ_SAE: Add Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VADDPD.RZ_SAE zmm zmm k zmm +// VADDPD.RZ_SAE zmm zmm zmm +// Construct and append a VADDPD.RZ_SAE instruction to the active function. +func (c *Context) VADDPD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VADDPD_RZ_SAE(ops...)) +} + +// VADDPD_RZ_SAE: Add Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VADDPD.RZ_SAE zmm zmm k zmm +// VADDPD.RZ_SAE zmm zmm zmm +// Construct and append a VADDPD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VADDPD_RZ_SAE(ops ...operand.Op) { ctx.VADDPD_RZ_SAE(ops...) } + +// VADDPD_RZ_SAE_Z: Add Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VADDPD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VADDPD.RZ_SAE.Z instruction to the active function. +func (c *Context) VADDPD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VADDPD_RZ_SAE_Z(z, z1, k, z2)) +} + +// VADDPD_RZ_SAE_Z: Add Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VADDPD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VADDPD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VADDPD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VADDPD_RZ_SAE_Z(z, z1, k, z2) } + +// VADDPD_Z: Add Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VADDPD.Z m128 xmm k xmm +// VADDPD.Z m256 ymm k ymm +// VADDPD.Z xmm xmm k xmm +// VADDPD.Z ymm ymm k ymm +// VADDPD.Z m512 zmm k zmm +// VADDPD.Z zmm zmm k zmm +// Construct and append a VADDPD.Z instruction to the active function. +func (c *Context) VADDPD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VADDPD_Z(mxyz, xyz, k, xyz1)) +} + +// VADDPD_Z: Add Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VADDPD.Z m128 xmm k xmm +// VADDPD.Z m256 ymm k ymm +// VADDPD.Z xmm xmm k xmm +// VADDPD.Z ymm ymm k ymm +// VADDPD.Z m512 zmm k zmm +// VADDPD.Z zmm zmm k zmm +// Construct and append a VADDPD.Z instruction to the active function. +// Operates on the global context. +func VADDPD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VADDPD_Z(mxyz, xyz, k, xyz1) } + +// VADDPS: Add Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VADDPS m128 xmm xmm +// VADDPS m256 ymm ymm +// VADDPS xmm xmm xmm +// VADDPS ymm ymm ymm +// VADDPS m128 xmm k xmm +// VADDPS m256 ymm k ymm +// VADDPS xmm xmm k xmm +// VADDPS ymm ymm k ymm +// VADDPS m512 zmm k zmm +// VADDPS m512 zmm zmm +// VADDPS zmm zmm k zmm +// VADDPS zmm zmm zmm +// Construct and append a VADDPS instruction to the active function. +func (c *Context) VADDPS(ops ...operand.Op) { + c.addinstruction(x86.VADDPS(ops...)) +} + +// VADDPS: Add Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VADDPS m128 xmm xmm +// VADDPS m256 ymm ymm +// VADDPS xmm xmm xmm +// VADDPS ymm ymm ymm +// VADDPS m128 xmm k xmm +// VADDPS m256 ymm k ymm +// VADDPS xmm xmm k xmm +// VADDPS ymm ymm k ymm +// VADDPS m512 zmm k zmm +// VADDPS m512 zmm zmm +// VADDPS zmm zmm k zmm +// VADDPS zmm zmm zmm +// Construct and append a VADDPS instruction to the active function. +// Operates on the global context. +func VADDPS(ops ...operand.Op) { ctx.VADDPS(ops...) } + +// VADDPS_BCST: Add Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VADDPS.BCST m32 xmm k xmm +// VADDPS.BCST m32 xmm xmm +// VADDPS.BCST m32 ymm k ymm +// VADDPS.BCST m32 ymm ymm +// VADDPS.BCST m32 zmm k zmm +// VADDPS.BCST m32 zmm zmm +// Construct and append a VADDPS.BCST instruction to the active function. +func (c *Context) VADDPS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VADDPS_BCST(ops...)) +} + +// VADDPS_BCST: Add Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VADDPS.BCST m32 xmm k xmm +// VADDPS.BCST m32 xmm xmm +// VADDPS.BCST m32 ymm k ymm +// VADDPS.BCST m32 ymm ymm +// VADDPS.BCST m32 zmm k zmm +// VADDPS.BCST m32 zmm zmm +// Construct and append a VADDPS.BCST instruction to the active function. +// Operates on the global context. +func VADDPS_BCST(ops ...operand.Op) { ctx.VADDPS_BCST(ops...) } + +// VADDPS_BCST_Z: Add Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VADDPS.BCST.Z m32 xmm k xmm +// VADDPS.BCST.Z m32 ymm k ymm +// VADDPS.BCST.Z m32 zmm k zmm +// Construct and append a VADDPS.BCST.Z instruction to the active function. +func (c *Context) VADDPS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VADDPS_BCST_Z(m, xyz, k, xyz1)) +} + +// VADDPS_BCST_Z: Add Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VADDPS.BCST.Z m32 xmm k xmm +// VADDPS.BCST.Z m32 ymm k ymm +// VADDPS.BCST.Z m32 zmm k zmm +// Construct and append a VADDPS.BCST.Z instruction to the active function. +// Operates on the global context. +func VADDPS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VADDPS_BCST_Z(m, xyz, k, xyz1) } + +// VADDPS_RD_SAE: Add Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VADDPS.RD_SAE zmm zmm k zmm +// VADDPS.RD_SAE zmm zmm zmm +// Construct and append a VADDPS.RD_SAE instruction to the active function. +func (c *Context) VADDPS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VADDPS_RD_SAE(ops...)) +} + +// VADDPS_RD_SAE: Add Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VADDPS.RD_SAE zmm zmm k zmm +// VADDPS.RD_SAE zmm zmm zmm +// Construct and append a VADDPS.RD_SAE instruction to the active function. +// Operates on the global context. +func VADDPS_RD_SAE(ops ...operand.Op) { ctx.VADDPS_RD_SAE(ops...) } + +// VADDPS_RD_SAE_Z: Add Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VADDPS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VADDPS.RD_SAE.Z instruction to the active function. +func (c *Context) VADDPS_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VADDPS_RD_SAE_Z(z, z1, k, z2)) +} + +// VADDPS_RD_SAE_Z: Add Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VADDPS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VADDPS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VADDPS_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VADDPS_RD_SAE_Z(z, z1, k, z2) } + +// VADDPS_RN_SAE: Add Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VADDPS.RN_SAE zmm zmm k zmm +// VADDPS.RN_SAE zmm zmm zmm +// Construct and append a VADDPS.RN_SAE instruction to the active function. +func (c *Context) VADDPS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VADDPS_RN_SAE(ops...)) +} + +// VADDPS_RN_SAE: Add Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VADDPS.RN_SAE zmm zmm k zmm +// VADDPS.RN_SAE zmm zmm zmm +// Construct and append a VADDPS.RN_SAE instruction to the active function. +// Operates on the global context. +func VADDPS_RN_SAE(ops ...operand.Op) { ctx.VADDPS_RN_SAE(ops...) } + +// VADDPS_RN_SAE_Z: Add Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VADDPS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VADDPS.RN_SAE.Z instruction to the active function. +func (c *Context) VADDPS_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VADDPS_RN_SAE_Z(z, z1, k, z2)) +} + +// VADDPS_RN_SAE_Z: Add Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VADDPS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VADDPS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VADDPS_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VADDPS_RN_SAE_Z(z, z1, k, z2) } + +// VADDPS_RU_SAE: Add Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VADDPS.RU_SAE zmm zmm k zmm +// VADDPS.RU_SAE zmm zmm zmm +// Construct and append a VADDPS.RU_SAE instruction to the active function. +func (c *Context) VADDPS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VADDPS_RU_SAE(ops...)) +} + +// VADDPS_RU_SAE: Add Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VADDPS.RU_SAE zmm zmm k zmm +// VADDPS.RU_SAE zmm zmm zmm +// Construct and append a VADDPS.RU_SAE instruction to the active function. +// Operates on the global context. +func VADDPS_RU_SAE(ops ...operand.Op) { ctx.VADDPS_RU_SAE(ops...) } + +// VADDPS_RU_SAE_Z: Add Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VADDPS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VADDPS.RU_SAE.Z instruction to the active function. +func (c *Context) VADDPS_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VADDPS_RU_SAE_Z(z, z1, k, z2)) +} + +// VADDPS_RU_SAE_Z: Add Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VADDPS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VADDPS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VADDPS_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VADDPS_RU_SAE_Z(z, z1, k, z2) } + +// VADDPS_RZ_SAE: Add Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VADDPS.RZ_SAE zmm zmm k zmm +// VADDPS.RZ_SAE zmm zmm zmm +// Construct and append a VADDPS.RZ_SAE instruction to the active function. +func (c *Context) VADDPS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VADDPS_RZ_SAE(ops...)) +} + +// VADDPS_RZ_SAE: Add Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VADDPS.RZ_SAE zmm zmm k zmm +// VADDPS.RZ_SAE zmm zmm zmm +// Construct and append a VADDPS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VADDPS_RZ_SAE(ops ...operand.Op) { ctx.VADDPS_RZ_SAE(ops...) } + +// VADDPS_RZ_SAE_Z: Add Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VADDPS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VADDPS.RZ_SAE.Z instruction to the active function. +func (c *Context) VADDPS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VADDPS_RZ_SAE_Z(z, z1, k, z2)) +} + +// VADDPS_RZ_SAE_Z: Add Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VADDPS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VADDPS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VADDPS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VADDPS_RZ_SAE_Z(z, z1, k, z2) } + +// VADDPS_Z: Add Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VADDPS.Z m128 xmm k xmm +// VADDPS.Z m256 ymm k ymm +// VADDPS.Z xmm xmm k xmm +// VADDPS.Z ymm ymm k ymm +// VADDPS.Z m512 zmm k zmm +// VADDPS.Z zmm zmm k zmm +// Construct and append a VADDPS.Z instruction to the active function. +func (c *Context) VADDPS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VADDPS_Z(mxyz, xyz, k, xyz1)) +} + +// VADDPS_Z: Add Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VADDPS.Z m128 xmm k xmm +// VADDPS.Z m256 ymm k ymm +// VADDPS.Z xmm xmm k xmm +// VADDPS.Z ymm ymm k ymm +// VADDPS.Z m512 zmm k zmm +// VADDPS.Z zmm zmm k zmm +// Construct and append a VADDPS.Z instruction to the active function. +// Operates on the global context. +func VADDPS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VADDPS_Z(mxyz, xyz, k, xyz1) } + +// VADDSD: Add Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VADDSD m64 xmm xmm +// VADDSD xmm xmm xmm +// VADDSD m64 xmm k xmm +// VADDSD xmm xmm k xmm +// Construct and append a VADDSD instruction to the active function. +func (c *Context) VADDSD(ops ...operand.Op) { + c.addinstruction(x86.VADDSD(ops...)) +} + +// VADDSD: Add Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VADDSD m64 xmm xmm +// VADDSD xmm xmm xmm +// VADDSD m64 xmm k xmm +// VADDSD xmm xmm k xmm +// Construct and append a VADDSD instruction to the active function. +// Operates on the global context. +func VADDSD(ops ...operand.Op) { ctx.VADDSD(ops...) } + +// VADDSD_RD_SAE: Add Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VADDSD.RD_SAE xmm xmm k xmm +// VADDSD.RD_SAE xmm xmm xmm +// Construct and append a VADDSD.RD_SAE instruction to the active function. +func (c *Context) VADDSD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VADDSD_RD_SAE(ops...)) +} + +// VADDSD_RD_SAE: Add Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VADDSD.RD_SAE xmm xmm k xmm +// VADDSD.RD_SAE xmm xmm xmm +// Construct and append a VADDSD.RD_SAE instruction to the active function. +// Operates on the global context. +func VADDSD_RD_SAE(ops ...operand.Op) { ctx.VADDSD_RD_SAE(ops...) } + +// VADDSD_RD_SAE_Z: Add Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VADDSD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VADDSD.RD_SAE.Z instruction to the active function. +func (c *Context) VADDSD_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VADDSD_RD_SAE_Z(x, x1, k, x2)) +} + +// VADDSD_RD_SAE_Z: Add Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VADDSD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VADDSD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VADDSD_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VADDSD_RD_SAE_Z(x, x1, k, x2) } + +// VADDSD_RN_SAE: Add Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VADDSD.RN_SAE xmm xmm k xmm +// VADDSD.RN_SAE xmm xmm xmm +// Construct and append a VADDSD.RN_SAE instruction to the active function. +func (c *Context) VADDSD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VADDSD_RN_SAE(ops...)) +} + +// VADDSD_RN_SAE: Add Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VADDSD.RN_SAE xmm xmm k xmm +// VADDSD.RN_SAE xmm xmm xmm +// Construct and append a VADDSD.RN_SAE instruction to the active function. +// Operates on the global context. +func VADDSD_RN_SAE(ops ...operand.Op) { ctx.VADDSD_RN_SAE(ops...) } + +// VADDSD_RN_SAE_Z: Add Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VADDSD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VADDSD.RN_SAE.Z instruction to the active function. +func (c *Context) VADDSD_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VADDSD_RN_SAE_Z(x, x1, k, x2)) +} + +// VADDSD_RN_SAE_Z: Add Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VADDSD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VADDSD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VADDSD_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VADDSD_RN_SAE_Z(x, x1, k, x2) } + +// VADDSD_RU_SAE: Add Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VADDSD.RU_SAE xmm xmm k xmm +// VADDSD.RU_SAE xmm xmm xmm +// Construct and append a VADDSD.RU_SAE instruction to the active function. +func (c *Context) VADDSD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VADDSD_RU_SAE(ops...)) +} + +// VADDSD_RU_SAE: Add Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VADDSD.RU_SAE xmm xmm k xmm +// VADDSD.RU_SAE xmm xmm xmm +// Construct and append a VADDSD.RU_SAE instruction to the active function. +// Operates on the global context. +func VADDSD_RU_SAE(ops ...operand.Op) { ctx.VADDSD_RU_SAE(ops...) } + +// VADDSD_RU_SAE_Z: Add Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VADDSD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VADDSD.RU_SAE.Z instruction to the active function. +func (c *Context) VADDSD_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VADDSD_RU_SAE_Z(x, x1, k, x2)) +} + +// VADDSD_RU_SAE_Z: Add Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VADDSD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VADDSD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VADDSD_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VADDSD_RU_SAE_Z(x, x1, k, x2) } + +// VADDSD_RZ_SAE: Add Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VADDSD.RZ_SAE xmm xmm k xmm +// VADDSD.RZ_SAE xmm xmm xmm +// Construct and append a VADDSD.RZ_SAE instruction to the active function. +func (c *Context) VADDSD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VADDSD_RZ_SAE(ops...)) +} + +// VADDSD_RZ_SAE: Add Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VADDSD.RZ_SAE xmm xmm k xmm +// VADDSD.RZ_SAE xmm xmm xmm +// Construct and append a VADDSD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VADDSD_RZ_SAE(ops ...operand.Op) { ctx.VADDSD_RZ_SAE(ops...) } + +// VADDSD_RZ_SAE_Z: Add Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VADDSD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VADDSD.RZ_SAE.Z instruction to the active function. +func (c *Context) VADDSD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VADDSD_RZ_SAE_Z(x, x1, k, x2)) +} + +// VADDSD_RZ_SAE_Z: Add Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VADDSD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VADDSD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VADDSD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VADDSD_RZ_SAE_Z(x, x1, k, x2) } + +// VADDSD_Z: Add Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VADDSD.Z m64 xmm k xmm +// VADDSD.Z xmm xmm k xmm +// Construct and append a VADDSD.Z instruction to the active function. +func (c *Context) VADDSD_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VADDSD_Z(mx, x, k, x1)) +} + +// VADDSD_Z: Add Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VADDSD.Z m64 xmm k xmm +// VADDSD.Z xmm xmm k xmm +// Construct and append a VADDSD.Z instruction to the active function. +// Operates on the global context. +func VADDSD_Z(mx, x, k, x1 operand.Op) { ctx.VADDSD_Z(mx, x, k, x1) } + +// VADDSS: Add Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VADDSS m32 xmm xmm +// VADDSS xmm xmm xmm +// VADDSS m32 xmm k xmm +// VADDSS xmm xmm k xmm +// Construct and append a VADDSS instruction to the active function. +func (c *Context) VADDSS(ops ...operand.Op) { + c.addinstruction(x86.VADDSS(ops...)) +} + +// VADDSS: Add Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VADDSS m32 xmm xmm +// VADDSS xmm xmm xmm +// VADDSS m32 xmm k xmm +// VADDSS xmm xmm k xmm +// Construct and append a VADDSS instruction to the active function. +// Operates on the global context. +func VADDSS(ops ...operand.Op) { ctx.VADDSS(ops...) } + +// VADDSS_RD_SAE: Add Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VADDSS.RD_SAE xmm xmm k xmm +// VADDSS.RD_SAE xmm xmm xmm +// Construct and append a VADDSS.RD_SAE instruction to the active function. +func (c *Context) VADDSS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VADDSS_RD_SAE(ops...)) +} + +// VADDSS_RD_SAE: Add Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VADDSS.RD_SAE xmm xmm k xmm +// VADDSS.RD_SAE xmm xmm xmm +// Construct and append a VADDSS.RD_SAE instruction to the active function. +// Operates on the global context. +func VADDSS_RD_SAE(ops ...operand.Op) { ctx.VADDSS_RD_SAE(ops...) } + +// VADDSS_RD_SAE_Z: Add Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VADDSS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VADDSS.RD_SAE.Z instruction to the active function. +func (c *Context) VADDSS_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VADDSS_RD_SAE_Z(x, x1, k, x2)) +} + +// VADDSS_RD_SAE_Z: Add Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VADDSS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VADDSS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VADDSS_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VADDSS_RD_SAE_Z(x, x1, k, x2) } + +// VADDSS_RN_SAE: Add Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VADDSS.RN_SAE xmm xmm k xmm +// VADDSS.RN_SAE xmm xmm xmm +// Construct and append a VADDSS.RN_SAE instruction to the active function. +func (c *Context) VADDSS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VADDSS_RN_SAE(ops...)) +} + +// VADDSS_RN_SAE: Add Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VADDSS.RN_SAE xmm xmm k xmm +// VADDSS.RN_SAE xmm xmm xmm +// Construct and append a VADDSS.RN_SAE instruction to the active function. +// Operates on the global context. +func VADDSS_RN_SAE(ops ...operand.Op) { ctx.VADDSS_RN_SAE(ops...) } + +// VADDSS_RN_SAE_Z: Add Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VADDSS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VADDSS.RN_SAE.Z instruction to the active function. +func (c *Context) VADDSS_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VADDSS_RN_SAE_Z(x, x1, k, x2)) +} + +// VADDSS_RN_SAE_Z: Add Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VADDSS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VADDSS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VADDSS_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VADDSS_RN_SAE_Z(x, x1, k, x2) } + +// VADDSS_RU_SAE: Add Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VADDSS.RU_SAE xmm xmm k xmm +// VADDSS.RU_SAE xmm xmm xmm +// Construct and append a VADDSS.RU_SAE instruction to the active function. +func (c *Context) VADDSS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VADDSS_RU_SAE(ops...)) +} + +// VADDSS_RU_SAE: Add Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VADDSS.RU_SAE xmm xmm k xmm +// VADDSS.RU_SAE xmm xmm xmm +// Construct and append a VADDSS.RU_SAE instruction to the active function. +// Operates on the global context. +func VADDSS_RU_SAE(ops ...operand.Op) { ctx.VADDSS_RU_SAE(ops...) } + +// VADDSS_RU_SAE_Z: Add Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VADDSS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VADDSS.RU_SAE.Z instruction to the active function. +func (c *Context) VADDSS_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VADDSS_RU_SAE_Z(x, x1, k, x2)) +} + +// VADDSS_RU_SAE_Z: Add Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VADDSS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VADDSS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VADDSS_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VADDSS_RU_SAE_Z(x, x1, k, x2) } + +// VADDSS_RZ_SAE: Add Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VADDSS.RZ_SAE xmm xmm k xmm +// VADDSS.RZ_SAE xmm xmm xmm +// Construct and append a VADDSS.RZ_SAE instruction to the active function. +func (c *Context) VADDSS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VADDSS_RZ_SAE(ops...)) +} + +// VADDSS_RZ_SAE: Add Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VADDSS.RZ_SAE xmm xmm k xmm +// VADDSS.RZ_SAE xmm xmm xmm +// Construct and append a VADDSS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VADDSS_RZ_SAE(ops ...operand.Op) { ctx.VADDSS_RZ_SAE(ops...) } + +// VADDSS_RZ_SAE_Z: Add Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VADDSS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VADDSS.RZ_SAE.Z instruction to the active function. +func (c *Context) VADDSS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VADDSS_RZ_SAE_Z(x, x1, k, x2)) +} + +// VADDSS_RZ_SAE_Z: Add Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VADDSS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VADDSS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VADDSS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VADDSS_RZ_SAE_Z(x, x1, k, x2) } + +// VADDSS_Z: Add Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VADDSS.Z m32 xmm k xmm +// VADDSS.Z xmm xmm k xmm +// Construct and append a VADDSS.Z instruction to the active function. +func (c *Context) VADDSS_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VADDSS_Z(mx, x, k, x1)) +} + +// VADDSS_Z: Add Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VADDSS.Z m32 xmm k xmm +// VADDSS.Z xmm xmm k xmm +// Construct and append a VADDSS.Z instruction to the active function. +// Operates on the global context. +func VADDSS_Z(mx, x, k, x1 operand.Op) { ctx.VADDSS_Z(mx, x, k, x1) } + +// VADDSUBPD: Packed Double-FP Add/Subtract. +// +// Forms: +// +// VADDSUBPD m128 xmm xmm +// VADDSUBPD m256 ymm ymm +// VADDSUBPD xmm xmm xmm +// VADDSUBPD ymm ymm ymm +// Construct and append a VADDSUBPD instruction to the active function. +func (c *Context) VADDSUBPD(mxy, xy, xy1 operand.Op) { + c.addinstruction(x86.VADDSUBPD(mxy, xy, xy1)) +} + +// VADDSUBPD: Packed Double-FP Add/Subtract. +// +// Forms: +// +// VADDSUBPD m128 xmm xmm +// VADDSUBPD m256 ymm ymm +// VADDSUBPD xmm xmm xmm +// VADDSUBPD ymm ymm ymm +// Construct and append a VADDSUBPD instruction to the active function. +// Operates on the global context. +func VADDSUBPD(mxy, xy, xy1 operand.Op) { ctx.VADDSUBPD(mxy, xy, xy1) } + +// VADDSUBPS: Packed Single-FP Add/Subtract. +// +// Forms: +// +// VADDSUBPS m128 xmm xmm +// VADDSUBPS m256 ymm ymm +// VADDSUBPS xmm xmm xmm +// VADDSUBPS ymm ymm ymm +// Construct and append a VADDSUBPS instruction to the active function. +func (c *Context) VADDSUBPS(mxy, xy, xy1 operand.Op) { + c.addinstruction(x86.VADDSUBPS(mxy, xy, xy1)) +} + +// VADDSUBPS: Packed Single-FP Add/Subtract. +// +// Forms: +// +// VADDSUBPS m128 xmm xmm +// VADDSUBPS m256 ymm ymm +// VADDSUBPS xmm xmm xmm +// VADDSUBPS ymm ymm ymm +// Construct and append a VADDSUBPS instruction to the active function. +// Operates on the global context. +func VADDSUBPS(mxy, xy, xy1 operand.Op) { ctx.VADDSUBPS(mxy, xy, xy1) } + +// VAESDEC: Perform One Round of an AES Decryption Flow. +// +// Forms: +// +// VAESDEC m128 xmm xmm +// VAESDEC xmm xmm xmm +// Construct and append a VAESDEC instruction to the active function. +func (c *Context) VAESDEC(mx, x, x1 operand.Op) { + c.addinstruction(x86.VAESDEC(mx, x, x1)) +} + +// VAESDEC: Perform One Round of an AES Decryption Flow. +// +// Forms: +// +// VAESDEC m128 xmm xmm +// VAESDEC xmm xmm xmm +// Construct and append a VAESDEC instruction to the active function. +// Operates on the global context. +func VAESDEC(mx, x, x1 operand.Op) { ctx.VAESDEC(mx, x, x1) } + +// VAESDECLAST: Perform Last Round of an AES Decryption Flow. +// +// Forms: +// +// VAESDECLAST m128 xmm xmm +// VAESDECLAST xmm xmm xmm +// Construct and append a VAESDECLAST instruction to the active function. +func (c *Context) VAESDECLAST(mx, x, x1 operand.Op) { + c.addinstruction(x86.VAESDECLAST(mx, x, x1)) +} + +// VAESDECLAST: Perform Last Round of an AES Decryption Flow. +// +// Forms: +// +// VAESDECLAST m128 xmm xmm +// VAESDECLAST xmm xmm xmm +// Construct and append a VAESDECLAST instruction to the active function. +// Operates on the global context. +func VAESDECLAST(mx, x, x1 operand.Op) { ctx.VAESDECLAST(mx, x, x1) } + +// VAESENC: Perform One Round of an AES Encryption Flow. +// +// Forms: +// +// VAESENC m128 xmm xmm +// VAESENC xmm xmm xmm +// Construct and append a VAESENC instruction to the active function. +func (c *Context) VAESENC(mx, x, x1 operand.Op) { + c.addinstruction(x86.VAESENC(mx, x, x1)) +} + +// VAESENC: Perform One Round of an AES Encryption Flow. +// +// Forms: +// +// VAESENC m128 xmm xmm +// VAESENC xmm xmm xmm +// Construct and append a VAESENC instruction to the active function. +// Operates on the global context. +func VAESENC(mx, x, x1 operand.Op) { ctx.VAESENC(mx, x, x1) } + +// VAESENCLAST: Perform Last Round of an AES Encryption Flow. +// +// Forms: +// +// VAESENCLAST m128 xmm xmm +// VAESENCLAST xmm xmm xmm +// Construct and append a VAESENCLAST instruction to the active function. +func (c *Context) VAESENCLAST(mx, x, x1 operand.Op) { + c.addinstruction(x86.VAESENCLAST(mx, x, x1)) +} + +// VAESENCLAST: Perform Last Round of an AES Encryption Flow. +// +// Forms: +// +// VAESENCLAST m128 xmm xmm +// VAESENCLAST xmm xmm xmm +// Construct and append a VAESENCLAST instruction to the active function. +// Operates on the global context. +func VAESENCLAST(mx, x, x1 operand.Op) { ctx.VAESENCLAST(mx, x, x1) } + +// VAESIMC: Perform the AES InvMixColumn Transformation. +// +// Forms: +// +// VAESIMC m128 xmm +// VAESIMC xmm xmm +// Construct and append a VAESIMC instruction to the active function. +func (c *Context) VAESIMC(mx, x operand.Op) { + c.addinstruction(x86.VAESIMC(mx, x)) +} + +// VAESIMC: Perform the AES InvMixColumn Transformation. +// +// Forms: +// +// VAESIMC m128 xmm +// VAESIMC xmm xmm +// Construct and append a VAESIMC instruction to the active function. +// Operates on the global context. +func VAESIMC(mx, x operand.Op) { ctx.VAESIMC(mx, x) } + +// VAESKEYGENASSIST: AES Round Key Generation Assist. +// +// Forms: +// +// VAESKEYGENASSIST imm8 m128 xmm +// VAESKEYGENASSIST imm8 xmm xmm +// Construct and append a VAESKEYGENASSIST instruction to the active function. +func (c *Context) VAESKEYGENASSIST(i, mx, x operand.Op) { + c.addinstruction(x86.VAESKEYGENASSIST(i, mx, x)) +} + +// VAESKEYGENASSIST: AES Round Key Generation Assist. +// +// Forms: +// +// VAESKEYGENASSIST imm8 m128 xmm +// VAESKEYGENASSIST imm8 xmm xmm +// Construct and append a VAESKEYGENASSIST instruction to the active function. +// Operates on the global context. +func VAESKEYGENASSIST(i, mx, x operand.Op) { ctx.VAESKEYGENASSIST(i, mx, x) } + +// VALIGND: Align Doubleword Vectors. +// +// Forms: +// +// VALIGND imm8 m128 xmm k xmm +// VALIGND imm8 m128 xmm xmm +// VALIGND imm8 m256 ymm k ymm +// VALIGND imm8 m256 ymm ymm +// VALIGND imm8 xmm xmm k xmm +// VALIGND imm8 xmm xmm xmm +// VALIGND imm8 ymm ymm k ymm +// VALIGND imm8 ymm ymm ymm +// VALIGND imm8 m512 zmm k zmm +// VALIGND imm8 m512 zmm zmm +// VALIGND imm8 zmm zmm k zmm +// VALIGND imm8 zmm zmm zmm +// Construct and append a VALIGND instruction to the active function. +func (c *Context) VALIGND(ops ...operand.Op) { + c.addinstruction(x86.VALIGND(ops...)) +} + +// VALIGND: Align Doubleword Vectors. +// +// Forms: +// +// VALIGND imm8 m128 xmm k xmm +// VALIGND imm8 m128 xmm xmm +// VALIGND imm8 m256 ymm k ymm +// VALIGND imm8 m256 ymm ymm +// VALIGND imm8 xmm xmm k xmm +// VALIGND imm8 xmm xmm xmm +// VALIGND imm8 ymm ymm k ymm +// VALIGND imm8 ymm ymm ymm +// VALIGND imm8 m512 zmm k zmm +// VALIGND imm8 m512 zmm zmm +// VALIGND imm8 zmm zmm k zmm +// VALIGND imm8 zmm zmm zmm +// Construct and append a VALIGND instruction to the active function. +// Operates on the global context. +func VALIGND(ops ...operand.Op) { ctx.VALIGND(ops...) } + +// VALIGND_BCST: Align Doubleword Vectors (Broadcast). +// +// Forms: +// +// VALIGND.BCST imm8 m32 xmm k xmm +// VALIGND.BCST imm8 m32 xmm xmm +// VALIGND.BCST imm8 m32 ymm k ymm +// VALIGND.BCST imm8 m32 ymm ymm +// VALIGND.BCST imm8 m32 zmm k zmm +// VALIGND.BCST imm8 m32 zmm zmm +// Construct and append a VALIGND.BCST instruction to the active function. +func (c *Context) VALIGND_BCST(ops ...operand.Op) { + c.addinstruction(x86.VALIGND_BCST(ops...)) +} + +// VALIGND_BCST: Align Doubleword Vectors (Broadcast). +// +// Forms: +// +// VALIGND.BCST imm8 m32 xmm k xmm +// VALIGND.BCST imm8 m32 xmm xmm +// VALIGND.BCST imm8 m32 ymm k ymm +// VALIGND.BCST imm8 m32 ymm ymm +// VALIGND.BCST imm8 m32 zmm k zmm +// VALIGND.BCST imm8 m32 zmm zmm +// Construct and append a VALIGND.BCST instruction to the active function. +// Operates on the global context. +func VALIGND_BCST(ops ...operand.Op) { ctx.VALIGND_BCST(ops...) } + +// VALIGND_BCST_Z: Align Doubleword Vectors (Broadcast, Zeroing Masking). +// +// Forms: +// +// VALIGND.BCST.Z imm8 m32 xmm k xmm +// VALIGND.BCST.Z imm8 m32 ymm k ymm +// VALIGND.BCST.Z imm8 m32 zmm k zmm +// Construct and append a VALIGND.BCST.Z instruction to the active function. +func (c *Context) VALIGND_BCST_Z(i, m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VALIGND_BCST_Z(i, m, xyz, k, xyz1)) +} + +// VALIGND_BCST_Z: Align Doubleword Vectors (Broadcast, Zeroing Masking). +// +// Forms: +// +// VALIGND.BCST.Z imm8 m32 xmm k xmm +// VALIGND.BCST.Z imm8 m32 ymm k ymm +// VALIGND.BCST.Z imm8 m32 zmm k zmm +// Construct and append a VALIGND.BCST.Z instruction to the active function. +// Operates on the global context. +func VALIGND_BCST_Z(i, m, xyz, k, xyz1 operand.Op) { ctx.VALIGND_BCST_Z(i, m, xyz, k, xyz1) } + +// VALIGND_Z: Align Doubleword Vectors (Zeroing Masking). +// +// Forms: +// +// VALIGND.Z imm8 m128 xmm k xmm +// VALIGND.Z imm8 m256 ymm k ymm +// VALIGND.Z imm8 xmm xmm k xmm +// VALIGND.Z imm8 ymm ymm k ymm +// VALIGND.Z imm8 m512 zmm k zmm +// VALIGND.Z imm8 zmm zmm k zmm +// Construct and append a VALIGND.Z instruction to the active function. +func (c *Context) VALIGND_Z(i, mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VALIGND_Z(i, mxyz, xyz, k, xyz1)) +} + +// VALIGND_Z: Align Doubleword Vectors (Zeroing Masking). +// +// Forms: +// +// VALIGND.Z imm8 m128 xmm k xmm +// VALIGND.Z imm8 m256 ymm k ymm +// VALIGND.Z imm8 xmm xmm k xmm +// VALIGND.Z imm8 ymm ymm k ymm +// VALIGND.Z imm8 m512 zmm k zmm +// VALIGND.Z imm8 zmm zmm k zmm +// Construct and append a VALIGND.Z instruction to the active function. +// Operates on the global context. +func VALIGND_Z(i, mxyz, xyz, k, xyz1 operand.Op) { ctx.VALIGND_Z(i, mxyz, xyz, k, xyz1) } + +// VALIGNQ: Align Quadword Vectors. +// +// Forms: +// +// VALIGNQ imm8 m128 xmm k xmm +// VALIGNQ imm8 m128 xmm xmm +// VALIGNQ imm8 m256 ymm k ymm +// VALIGNQ imm8 m256 ymm ymm +// VALIGNQ imm8 xmm xmm k xmm +// VALIGNQ imm8 xmm xmm xmm +// VALIGNQ imm8 ymm ymm k ymm +// VALIGNQ imm8 ymm ymm ymm +// VALIGNQ imm8 m512 zmm k zmm +// VALIGNQ imm8 m512 zmm zmm +// VALIGNQ imm8 zmm zmm k zmm +// VALIGNQ imm8 zmm zmm zmm +// Construct and append a VALIGNQ instruction to the active function. +func (c *Context) VALIGNQ(ops ...operand.Op) { + c.addinstruction(x86.VALIGNQ(ops...)) +} + +// VALIGNQ: Align Quadword Vectors. +// +// Forms: +// +// VALIGNQ imm8 m128 xmm k xmm +// VALIGNQ imm8 m128 xmm xmm +// VALIGNQ imm8 m256 ymm k ymm +// VALIGNQ imm8 m256 ymm ymm +// VALIGNQ imm8 xmm xmm k xmm +// VALIGNQ imm8 xmm xmm xmm +// VALIGNQ imm8 ymm ymm k ymm +// VALIGNQ imm8 ymm ymm ymm +// VALIGNQ imm8 m512 zmm k zmm +// VALIGNQ imm8 m512 zmm zmm +// VALIGNQ imm8 zmm zmm k zmm +// VALIGNQ imm8 zmm zmm zmm +// Construct and append a VALIGNQ instruction to the active function. +// Operates on the global context. +func VALIGNQ(ops ...operand.Op) { ctx.VALIGNQ(ops...) } + +// VALIGNQ_BCST: Align Quadword Vectors (Broadcast). +// +// Forms: +// +// VALIGNQ.BCST imm8 m64 xmm k xmm +// VALIGNQ.BCST imm8 m64 xmm xmm +// VALIGNQ.BCST imm8 m64 ymm k ymm +// VALIGNQ.BCST imm8 m64 ymm ymm +// VALIGNQ.BCST imm8 m64 zmm k zmm +// VALIGNQ.BCST imm8 m64 zmm zmm +// Construct and append a VALIGNQ.BCST instruction to the active function. +func (c *Context) VALIGNQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VALIGNQ_BCST(ops...)) +} + +// VALIGNQ_BCST: Align Quadword Vectors (Broadcast). +// +// Forms: +// +// VALIGNQ.BCST imm8 m64 xmm k xmm +// VALIGNQ.BCST imm8 m64 xmm xmm +// VALIGNQ.BCST imm8 m64 ymm k ymm +// VALIGNQ.BCST imm8 m64 ymm ymm +// VALIGNQ.BCST imm8 m64 zmm k zmm +// VALIGNQ.BCST imm8 m64 zmm zmm +// Construct and append a VALIGNQ.BCST instruction to the active function. +// Operates on the global context. +func VALIGNQ_BCST(ops ...operand.Op) { ctx.VALIGNQ_BCST(ops...) } + +// VALIGNQ_BCST_Z: Align Quadword Vectors (Broadcast, Zeroing Masking). +// +// Forms: +// +// VALIGNQ.BCST.Z imm8 m64 xmm k xmm +// VALIGNQ.BCST.Z imm8 m64 ymm k ymm +// VALIGNQ.BCST.Z imm8 m64 zmm k zmm +// Construct and append a VALIGNQ.BCST.Z instruction to the active function. +func (c *Context) VALIGNQ_BCST_Z(i, m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VALIGNQ_BCST_Z(i, m, xyz, k, xyz1)) +} + +// VALIGNQ_BCST_Z: Align Quadword Vectors (Broadcast, Zeroing Masking). +// +// Forms: +// +// VALIGNQ.BCST.Z imm8 m64 xmm k xmm +// VALIGNQ.BCST.Z imm8 m64 ymm k ymm +// VALIGNQ.BCST.Z imm8 m64 zmm k zmm +// Construct and append a VALIGNQ.BCST.Z instruction to the active function. +// Operates on the global context. +func VALIGNQ_BCST_Z(i, m, xyz, k, xyz1 operand.Op) { ctx.VALIGNQ_BCST_Z(i, m, xyz, k, xyz1) } + +// VALIGNQ_Z: Align Quadword Vectors (Zeroing Masking). +// +// Forms: +// +// VALIGNQ.Z imm8 m128 xmm k xmm +// VALIGNQ.Z imm8 m256 ymm k ymm +// VALIGNQ.Z imm8 xmm xmm k xmm +// VALIGNQ.Z imm8 ymm ymm k ymm +// VALIGNQ.Z imm8 m512 zmm k zmm +// VALIGNQ.Z imm8 zmm zmm k zmm +// Construct and append a VALIGNQ.Z instruction to the active function. +func (c *Context) VALIGNQ_Z(i, mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VALIGNQ_Z(i, mxyz, xyz, k, xyz1)) +} + +// VALIGNQ_Z: Align Quadword Vectors (Zeroing Masking). +// +// Forms: +// +// VALIGNQ.Z imm8 m128 xmm k xmm +// VALIGNQ.Z imm8 m256 ymm k ymm +// VALIGNQ.Z imm8 xmm xmm k xmm +// VALIGNQ.Z imm8 ymm ymm k ymm +// VALIGNQ.Z imm8 m512 zmm k zmm +// VALIGNQ.Z imm8 zmm zmm k zmm +// Construct and append a VALIGNQ.Z instruction to the active function. +// Operates on the global context. +func VALIGNQ_Z(i, mxyz, xyz, k, xyz1 operand.Op) { ctx.VALIGNQ_Z(i, mxyz, xyz, k, xyz1) } + +// VANDNPD: Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VANDNPD m128 xmm xmm +// VANDNPD m256 ymm ymm +// VANDNPD xmm xmm xmm +// VANDNPD ymm ymm ymm +// VANDNPD m128 xmm k xmm +// VANDNPD m256 ymm k ymm +// VANDNPD xmm xmm k xmm +// VANDNPD ymm ymm k ymm +// VANDNPD m512 zmm k zmm +// VANDNPD m512 zmm zmm +// VANDNPD zmm zmm k zmm +// VANDNPD zmm zmm zmm +// Construct and append a VANDNPD instruction to the active function. +func (c *Context) VANDNPD(ops ...operand.Op) { + c.addinstruction(x86.VANDNPD(ops...)) +} + +// VANDNPD: Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VANDNPD m128 xmm xmm +// VANDNPD m256 ymm ymm +// VANDNPD xmm xmm xmm +// VANDNPD ymm ymm ymm +// VANDNPD m128 xmm k xmm +// VANDNPD m256 ymm k ymm +// VANDNPD xmm xmm k xmm +// VANDNPD ymm ymm k ymm +// VANDNPD m512 zmm k zmm +// VANDNPD m512 zmm zmm +// VANDNPD zmm zmm k zmm +// VANDNPD zmm zmm zmm +// Construct and append a VANDNPD instruction to the active function. +// Operates on the global context. +func VANDNPD(ops ...operand.Op) { ctx.VANDNPD(ops...) } + +// VANDNPD_BCST: Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VANDNPD.BCST m64 xmm k xmm +// VANDNPD.BCST m64 xmm xmm +// VANDNPD.BCST m64 ymm k ymm +// VANDNPD.BCST m64 ymm ymm +// VANDNPD.BCST m64 zmm k zmm +// VANDNPD.BCST m64 zmm zmm +// Construct and append a VANDNPD.BCST instruction to the active function. +func (c *Context) VANDNPD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VANDNPD_BCST(ops...)) +} + +// VANDNPD_BCST: Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VANDNPD.BCST m64 xmm k xmm +// VANDNPD.BCST m64 xmm xmm +// VANDNPD.BCST m64 ymm k ymm +// VANDNPD.BCST m64 ymm ymm +// VANDNPD.BCST m64 zmm k zmm +// VANDNPD.BCST m64 zmm zmm +// Construct and append a VANDNPD.BCST instruction to the active function. +// Operates on the global context. +func VANDNPD_BCST(ops ...operand.Op) { ctx.VANDNPD_BCST(ops...) } + +// VANDNPD_BCST_Z: Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VANDNPD.BCST.Z m64 xmm k xmm +// VANDNPD.BCST.Z m64 ymm k ymm +// VANDNPD.BCST.Z m64 zmm k zmm +// Construct and append a VANDNPD.BCST.Z instruction to the active function. +func (c *Context) VANDNPD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VANDNPD_BCST_Z(m, xyz, k, xyz1)) +} + +// VANDNPD_BCST_Z: Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VANDNPD.BCST.Z m64 xmm k xmm +// VANDNPD.BCST.Z m64 ymm k ymm +// VANDNPD.BCST.Z m64 zmm k zmm +// Construct and append a VANDNPD.BCST.Z instruction to the active function. +// Operates on the global context. +func VANDNPD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VANDNPD_BCST_Z(m, xyz, k, xyz1) } + +// VANDNPD_Z: Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VANDNPD.Z m128 xmm k xmm +// VANDNPD.Z m256 ymm k ymm +// VANDNPD.Z xmm xmm k xmm +// VANDNPD.Z ymm ymm k ymm +// VANDNPD.Z m512 zmm k zmm +// VANDNPD.Z zmm zmm k zmm +// Construct and append a VANDNPD.Z instruction to the active function. +func (c *Context) VANDNPD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VANDNPD_Z(mxyz, xyz, k, xyz1)) +} + +// VANDNPD_Z: Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VANDNPD.Z m128 xmm k xmm +// VANDNPD.Z m256 ymm k ymm +// VANDNPD.Z xmm xmm k xmm +// VANDNPD.Z ymm ymm k ymm +// VANDNPD.Z m512 zmm k zmm +// VANDNPD.Z zmm zmm k zmm +// Construct and append a VANDNPD.Z instruction to the active function. +// Operates on the global context. +func VANDNPD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VANDNPD_Z(mxyz, xyz, k, xyz1) } + +// VANDNPS: Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VANDNPS m128 xmm xmm +// VANDNPS m256 ymm ymm +// VANDNPS xmm xmm xmm +// VANDNPS ymm ymm ymm +// VANDNPS m128 xmm k xmm +// VANDNPS m256 ymm k ymm +// VANDNPS xmm xmm k xmm +// VANDNPS ymm ymm k ymm +// VANDNPS m512 zmm k zmm +// VANDNPS m512 zmm zmm +// VANDNPS zmm zmm k zmm +// VANDNPS zmm zmm zmm +// Construct and append a VANDNPS instruction to the active function. +func (c *Context) VANDNPS(ops ...operand.Op) { + c.addinstruction(x86.VANDNPS(ops...)) +} + +// VANDNPS: Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VANDNPS m128 xmm xmm +// VANDNPS m256 ymm ymm +// VANDNPS xmm xmm xmm +// VANDNPS ymm ymm ymm +// VANDNPS m128 xmm k xmm +// VANDNPS m256 ymm k ymm +// VANDNPS xmm xmm k xmm +// VANDNPS ymm ymm k ymm +// VANDNPS m512 zmm k zmm +// VANDNPS m512 zmm zmm +// VANDNPS zmm zmm k zmm +// VANDNPS zmm zmm zmm +// Construct and append a VANDNPS instruction to the active function. +// Operates on the global context. +func VANDNPS(ops ...operand.Op) { ctx.VANDNPS(ops...) } + +// VANDNPS_BCST: Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VANDNPS.BCST m32 xmm k xmm +// VANDNPS.BCST m32 xmm xmm +// VANDNPS.BCST m32 ymm k ymm +// VANDNPS.BCST m32 ymm ymm +// VANDNPS.BCST m32 zmm k zmm +// VANDNPS.BCST m32 zmm zmm +// Construct and append a VANDNPS.BCST instruction to the active function. +func (c *Context) VANDNPS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VANDNPS_BCST(ops...)) +} + +// VANDNPS_BCST: Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VANDNPS.BCST m32 xmm k xmm +// VANDNPS.BCST m32 xmm xmm +// VANDNPS.BCST m32 ymm k ymm +// VANDNPS.BCST m32 ymm ymm +// VANDNPS.BCST m32 zmm k zmm +// VANDNPS.BCST m32 zmm zmm +// Construct and append a VANDNPS.BCST instruction to the active function. +// Operates on the global context. +func VANDNPS_BCST(ops ...operand.Op) { ctx.VANDNPS_BCST(ops...) } + +// VANDNPS_BCST_Z: Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VANDNPS.BCST.Z m32 xmm k xmm +// VANDNPS.BCST.Z m32 ymm k ymm +// VANDNPS.BCST.Z m32 zmm k zmm +// Construct and append a VANDNPS.BCST.Z instruction to the active function. +func (c *Context) VANDNPS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VANDNPS_BCST_Z(m, xyz, k, xyz1)) +} + +// VANDNPS_BCST_Z: Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VANDNPS.BCST.Z m32 xmm k xmm +// VANDNPS.BCST.Z m32 ymm k ymm +// VANDNPS.BCST.Z m32 zmm k zmm +// Construct and append a VANDNPS.BCST.Z instruction to the active function. +// Operates on the global context. +func VANDNPS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VANDNPS_BCST_Z(m, xyz, k, xyz1) } + +// VANDNPS_Z: Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VANDNPS.Z m128 xmm k xmm +// VANDNPS.Z m256 ymm k ymm +// VANDNPS.Z xmm xmm k xmm +// VANDNPS.Z ymm ymm k ymm +// VANDNPS.Z m512 zmm k zmm +// VANDNPS.Z zmm zmm k zmm +// Construct and append a VANDNPS.Z instruction to the active function. +func (c *Context) VANDNPS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VANDNPS_Z(mxyz, xyz, k, xyz1)) +} + +// VANDNPS_Z: Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VANDNPS.Z m128 xmm k xmm +// VANDNPS.Z m256 ymm k ymm +// VANDNPS.Z xmm xmm k xmm +// VANDNPS.Z ymm ymm k ymm +// VANDNPS.Z m512 zmm k zmm +// VANDNPS.Z zmm zmm k zmm +// Construct and append a VANDNPS.Z instruction to the active function. +// Operates on the global context. +func VANDNPS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VANDNPS_Z(mxyz, xyz, k, xyz1) } + +// VANDPD: Bitwise Logical AND of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VANDPD m128 xmm xmm +// VANDPD m256 ymm ymm +// VANDPD xmm xmm xmm +// VANDPD ymm ymm ymm +// VANDPD m128 xmm k xmm +// VANDPD m256 ymm k ymm +// VANDPD xmm xmm k xmm +// VANDPD ymm ymm k ymm +// VANDPD m512 zmm k zmm +// VANDPD m512 zmm zmm +// VANDPD zmm zmm k zmm +// VANDPD zmm zmm zmm +// Construct and append a VANDPD instruction to the active function. +func (c *Context) VANDPD(ops ...operand.Op) { + c.addinstruction(x86.VANDPD(ops...)) +} + +// VANDPD: Bitwise Logical AND of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VANDPD m128 xmm xmm +// VANDPD m256 ymm ymm +// VANDPD xmm xmm xmm +// VANDPD ymm ymm ymm +// VANDPD m128 xmm k xmm +// VANDPD m256 ymm k ymm +// VANDPD xmm xmm k xmm +// VANDPD ymm ymm k ymm +// VANDPD m512 zmm k zmm +// VANDPD m512 zmm zmm +// VANDPD zmm zmm k zmm +// VANDPD zmm zmm zmm +// Construct and append a VANDPD instruction to the active function. +// Operates on the global context. +func VANDPD(ops ...operand.Op) { ctx.VANDPD(ops...) } + +// VANDPD_BCST: Bitwise Logical AND of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VANDPD.BCST m64 xmm k xmm +// VANDPD.BCST m64 xmm xmm +// VANDPD.BCST m64 ymm k ymm +// VANDPD.BCST m64 ymm ymm +// VANDPD.BCST m64 zmm k zmm +// VANDPD.BCST m64 zmm zmm +// Construct and append a VANDPD.BCST instruction to the active function. +func (c *Context) VANDPD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VANDPD_BCST(ops...)) +} + +// VANDPD_BCST: Bitwise Logical AND of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VANDPD.BCST m64 xmm k xmm +// VANDPD.BCST m64 xmm xmm +// VANDPD.BCST m64 ymm k ymm +// VANDPD.BCST m64 ymm ymm +// VANDPD.BCST m64 zmm k zmm +// VANDPD.BCST m64 zmm zmm +// Construct and append a VANDPD.BCST instruction to the active function. +// Operates on the global context. +func VANDPD_BCST(ops ...operand.Op) { ctx.VANDPD_BCST(ops...) } + +// VANDPD_BCST_Z: Bitwise Logical AND of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VANDPD.BCST.Z m64 xmm k xmm +// VANDPD.BCST.Z m64 ymm k ymm +// VANDPD.BCST.Z m64 zmm k zmm +// Construct and append a VANDPD.BCST.Z instruction to the active function. +func (c *Context) VANDPD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VANDPD_BCST_Z(m, xyz, k, xyz1)) +} + +// VANDPD_BCST_Z: Bitwise Logical AND of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VANDPD.BCST.Z m64 xmm k xmm +// VANDPD.BCST.Z m64 ymm k ymm +// VANDPD.BCST.Z m64 zmm k zmm +// Construct and append a VANDPD.BCST.Z instruction to the active function. +// Operates on the global context. +func VANDPD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VANDPD_BCST_Z(m, xyz, k, xyz1) } + +// VANDPD_Z: Bitwise Logical AND of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VANDPD.Z m128 xmm k xmm +// VANDPD.Z m256 ymm k ymm +// VANDPD.Z xmm xmm k xmm +// VANDPD.Z ymm ymm k ymm +// VANDPD.Z m512 zmm k zmm +// VANDPD.Z zmm zmm k zmm +// Construct and append a VANDPD.Z instruction to the active function. +func (c *Context) VANDPD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VANDPD_Z(mxyz, xyz, k, xyz1)) +} + +// VANDPD_Z: Bitwise Logical AND of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VANDPD.Z m128 xmm k xmm +// VANDPD.Z m256 ymm k ymm +// VANDPD.Z xmm xmm k xmm +// VANDPD.Z ymm ymm k ymm +// VANDPD.Z m512 zmm k zmm +// VANDPD.Z zmm zmm k zmm +// Construct and append a VANDPD.Z instruction to the active function. +// Operates on the global context. +func VANDPD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VANDPD_Z(mxyz, xyz, k, xyz1) } + +// VANDPS: Bitwise Logical AND of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VANDPS m128 xmm xmm +// VANDPS m256 ymm ymm +// VANDPS xmm xmm xmm +// VANDPS ymm ymm ymm +// VANDPS m128 xmm k xmm +// VANDPS m256 ymm k ymm +// VANDPS xmm xmm k xmm +// VANDPS ymm ymm k ymm +// VANDPS m512 zmm k zmm +// VANDPS m512 zmm zmm +// VANDPS zmm zmm k zmm +// VANDPS zmm zmm zmm +// Construct and append a VANDPS instruction to the active function. +func (c *Context) VANDPS(ops ...operand.Op) { + c.addinstruction(x86.VANDPS(ops...)) +} + +// VANDPS: Bitwise Logical AND of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VANDPS m128 xmm xmm +// VANDPS m256 ymm ymm +// VANDPS xmm xmm xmm +// VANDPS ymm ymm ymm +// VANDPS m128 xmm k xmm +// VANDPS m256 ymm k ymm +// VANDPS xmm xmm k xmm +// VANDPS ymm ymm k ymm +// VANDPS m512 zmm k zmm +// VANDPS m512 zmm zmm +// VANDPS zmm zmm k zmm +// VANDPS zmm zmm zmm +// Construct and append a VANDPS instruction to the active function. +// Operates on the global context. +func VANDPS(ops ...operand.Op) { ctx.VANDPS(ops...) } + +// VANDPS_BCST: Bitwise Logical AND of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VANDPS.BCST m32 xmm k xmm +// VANDPS.BCST m32 xmm xmm +// VANDPS.BCST m32 ymm k ymm +// VANDPS.BCST m32 ymm ymm +// VANDPS.BCST m32 zmm k zmm +// VANDPS.BCST m32 zmm zmm +// Construct and append a VANDPS.BCST instruction to the active function. +func (c *Context) VANDPS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VANDPS_BCST(ops...)) +} + +// VANDPS_BCST: Bitwise Logical AND of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VANDPS.BCST m32 xmm k xmm +// VANDPS.BCST m32 xmm xmm +// VANDPS.BCST m32 ymm k ymm +// VANDPS.BCST m32 ymm ymm +// VANDPS.BCST m32 zmm k zmm +// VANDPS.BCST m32 zmm zmm +// Construct and append a VANDPS.BCST instruction to the active function. +// Operates on the global context. +func VANDPS_BCST(ops ...operand.Op) { ctx.VANDPS_BCST(ops...) } + +// VANDPS_BCST_Z: Bitwise Logical AND of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VANDPS.BCST.Z m32 xmm k xmm +// VANDPS.BCST.Z m32 ymm k ymm +// VANDPS.BCST.Z m32 zmm k zmm +// Construct and append a VANDPS.BCST.Z instruction to the active function. +func (c *Context) VANDPS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VANDPS_BCST_Z(m, xyz, k, xyz1)) +} + +// VANDPS_BCST_Z: Bitwise Logical AND of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VANDPS.BCST.Z m32 xmm k xmm +// VANDPS.BCST.Z m32 ymm k ymm +// VANDPS.BCST.Z m32 zmm k zmm +// Construct and append a VANDPS.BCST.Z instruction to the active function. +// Operates on the global context. +func VANDPS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VANDPS_BCST_Z(m, xyz, k, xyz1) } + +// VANDPS_Z: Bitwise Logical AND of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VANDPS.Z m128 xmm k xmm +// VANDPS.Z m256 ymm k ymm +// VANDPS.Z xmm xmm k xmm +// VANDPS.Z ymm ymm k ymm +// VANDPS.Z m512 zmm k zmm +// VANDPS.Z zmm zmm k zmm +// Construct and append a VANDPS.Z instruction to the active function. +func (c *Context) VANDPS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VANDPS_Z(mxyz, xyz, k, xyz1)) +} + +// VANDPS_Z: Bitwise Logical AND of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VANDPS.Z m128 xmm k xmm +// VANDPS.Z m256 ymm k ymm +// VANDPS.Z xmm xmm k xmm +// VANDPS.Z ymm ymm k ymm +// VANDPS.Z m512 zmm k zmm +// VANDPS.Z zmm zmm k zmm +// Construct and append a VANDPS.Z instruction to the active function. +// Operates on the global context. +func VANDPS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VANDPS_Z(mxyz, xyz, k, xyz1) } + +// VBLENDMPD: Blend Packed Double-Precision Floating-Point Vectors Using an OpMask Control. +// +// Forms: +// +// VBLENDMPD m128 xmm k xmm +// VBLENDMPD m128 xmm xmm +// VBLENDMPD m256 ymm k ymm +// VBLENDMPD m256 ymm ymm +// VBLENDMPD xmm xmm k xmm +// VBLENDMPD xmm xmm xmm +// VBLENDMPD ymm ymm k ymm +// VBLENDMPD ymm ymm ymm +// VBLENDMPD m512 zmm k zmm +// VBLENDMPD m512 zmm zmm +// VBLENDMPD zmm zmm k zmm +// VBLENDMPD zmm zmm zmm +// Construct and append a VBLENDMPD instruction to the active function. +func (c *Context) VBLENDMPD(ops ...operand.Op) { + c.addinstruction(x86.VBLENDMPD(ops...)) +} + +// VBLENDMPD: Blend Packed Double-Precision Floating-Point Vectors Using an OpMask Control. +// +// Forms: +// +// VBLENDMPD m128 xmm k xmm +// VBLENDMPD m128 xmm xmm +// VBLENDMPD m256 ymm k ymm +// VBLENDMPD m256 ymm ymm +// VBLENDMPD xmm xmm k xmm +// VBLENDMPD xmm xmm xmm +// VBLENDMPD ymm ymm k ymm +// VBLENDMPD ymm ymm ymm +// VBLENDMPD m512 zmm k zmm +// VBLENDMPD m512 zmm zmm +// VBLENDMPD zmm zmm k zmm +// VBLENDMPD zmm zmm zmm +// Construct and append a VBLENDMPD instruction to the active function. +// Operates on the global context. +func VBLENDMPD(ops ...operand.Op) { ctx.VBLENDMPD(ops...) } + +// VBLENDMPD_BCST: Blend Packed Double-Precision Floating-Point Vectors Using an OpMask Control (Broadcast). +// +// Forms: +// +// VBLENDMPD.BCST m64 xmm k xmm +// VBLENDMPD.BCST m64 xmm xmm +// VBLENDMPD.BCST m64 ymm k ymm +// VBLENDMPD.BCST m64 ymm ymm +// VBLENDMPD.BCST m64 zmm k zmm +// VBLENDMPD.BCST m64 zmm zmm +// Construct and append a VBLENDMPD.BCST instruction to the active function. +func (c *Context) VBLENDMPD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VBLENDMPD_BCST(ops...)) +} + +// VBLENDMPD_BCST: Blend Packed Double-Precision Floating-Point Vectors Using an OpMask Control (Broadcast). +// +// Forms: +// +// VBLENDMPD.BCST m64 xmm k xmm +// VBLENDMPD.BCST m64 xmm xmm +// VBLENDMPD.BCST m64 ymm k ymm +// VBLENDMPD.BCST m64 ymm ymm +// VBLENDMPD.BCST m64 zmm k zmm +// VBLENDMPD.BCST m64 zmm zmm +// Construct and append a VBLENDMPD.BCST instruction to the active function. +// Operates on the global context. +func VBLENDMPD_BCST(ops ...operand.Op) { ctx.VBLENDMPD_BCST(ops...) } + +// VBLENDMPD_BCST_Z: Blend Packed Double-Precision Floating-Point Vectors Using an OpMask Control (Broadcast, Zeroing Masking). +// +// Forms: +// +// VBLENDMPD.BCST.Z m64 xmm k xmm +// VBLENDMPD.BCST.Z m64 ymm k ymm +// VBLENDMPD.BCST.Z m64 zmm k zmm +// Construct and append a VBLENDMPD.BCST.Z instruction to the active function. +func (c *Context) VBLENDMPD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VBLENDMPD_BCST_Z(m, xyz, k, xyz1)) +} + +// VBLENDMPD_BCST_Z: Blend Packed Double-Precision Floating-Point Vectors Using an OpMask Control (Broadcast, Zeroing Masking). +// +// Forms: +// +// VBLENDMPD.BCST.Z m64 xmm k xmm +// VBLENDMPD.BCST.Z m64 ymm k ymm +// VBLENDMPD.BCST.Z m64 zmm k zmm +// Construct and append a VBLENDMPD.BCST.Z instruction to the active function. +// Operates on the global context. +func VBLENDMPD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VBLENDMPD_BCST_Z(m, xyz, k, xyz1) } + +// VBLENDMPD_Z: Blend Packed Double-Precision Floating-Point Vectors Using an OpMask Control (Zeroing Masking). +// +// Forms: +// +// VBLENDMPD.Z m128 xmm k xmm +// VBLENDMPD.Z m256 ymm k ymm +// VBLENDMPD.Z xmm xmm k xmm +// VBLENDMPD.Z ymm ymm k ymm +// VBLENDMPD.Z m512 zmm k zmm +// VBLENDMPD.Z zmm zmm k zmm +// Construct and append a VBLENDMPD.Z instruction to the active function. +func (c *Context) VBLENDMPD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VBLENDMPD_Z(mxyz, xyz, k, xyz1)) +} + +// VBLENDMPD_Z: Blend Packed Double-Precision Floating-Point Vectors Using an OpMask Control (Zeroing Masking). +// +// Forms: +// +// VBLENDMPD.Z m128 xmm k xmm +// VBLENDMPD.Z m256 ymm k ymm +// VBLENDMPD.Z xmm xmm k xmm +// VBLENDMPD.Z ymm ymm k ymm +// VBLENDMPD.Z m512 zmm k zmm +// VBLENDMPD.Z zmm zmm k zmm +// Construct and append a VBLENDMPD.Z instruction to the active function. +// Operates on the global context. +func VBLENDMPD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VBLENDMPD_Z(mxyz, xyz, k, xyz1) } + +// VBLENDMPS: Blend Packed Single-Precision Floating-Point Vectors Using an OpMask Control. +// +// Forms: +// +// VBLENDMPS m128 xmm k xmm +// VBLENDMPS m128 xmm xmm +// VBLENDMPS m256 ymm k ymm +// VBLENDMPS m256 ymm ymm +// VBLENDMPS xmm xmm k xmm +// VBLENDMPS xmm xmm xmm +// VBLENDMPS ymm ymm k ymm +// VBLENDMPS ymm ymm ymm +// VBLENDMPS m512 zmm k zmm +// VBLENDMPS m512 zmm zmm +// VBLENDMPS zmm zmm k zmm +// VBLENDMPS zmm zmm zmm +// Construct and append a VBLENDMPS instruction to the active function. +func (c *Context) VBLENDMPS(ops ...operand.Op) { + c.addinstruction(x86.VBLENDMPS(ops...)) +} + +// VBLENDMPS: Blend Packed Single-Precision Floating-Point Vectors Using an OpMask Control. +// +// Forms: +// +// VBLENDMPS m128 xmm k xmm +// VBLENDMPS m128 xmm xmm +// VBLENDMPS m256 ymm k ymm +// VBLENDMPS m256 ymm ymm +// VBLENDMPS xmm xmm k xmm +// VBLENDMPS xmm xmm xmm +// VBLENDMPS ymm ymm k ymm +// VBLENDMPS ymm ymm ymm +// VBLENDMPS m512 zmm k zmm +// VBLENDMPS m512 zmm zmm +// VBLENDMPS zmm zmm k zmm +// VBLENDMPS zmm zmm zmm +// Construct and append a VBLENDMPS instruction to the active function. +// Operates on the global context. +func VBLENDMPS(ops ...operand.Op) { ctx.VBLENDMPS(ops...) } + +// VBLENDMPS_BCST: Blend Packed Single-Precision Floating-Point Vectors Using an OpMask Control (Broadcast). +// +// Forms: +// +// VBLENDMPS.BCST m32 xmm k xmm +// VBLENDMPS.BCST m32 xmm xmm +// VBLENDMPS.BCST m32 ymm k ymm +// VBLENDMPS.BCST m32 ymm ymm +// VBLENDMPS.BCST m32 zmm k zmm +// VBLENDMPS.BCST m32 zmm zmm +// Construct and append a VBLENDMPS.BCST instruction to the active function. +func (c *Context) VBLENDMPS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VBLENDMPS_BCST(ops...)) +} + +// VBLENDMPS_BCST: Blend Packed Single-Precision Floating-Point Vectors Using an OpMask Control (Broadcast). +// +// Forms: +// +// VBLENDMPS.BCST m32 xmm k xmm +// VBLENDMPS.BCST m32 xmm xmm +// VBLENDMPS.BCST m32 ymm k ymm +// VBLENDMPS.BCST m32 ymm ymm +// VBLENDMPS.BCST m32 zmm k zmm +// VBLENDMPS.BCST m32 zmm zmm +// Construct and append a VBLENDMPS.BCST instruction to the active function. +// Operates on the global context. +func VBLENDMPS_BCST(ops ...operand.Op) { ctx.VBLENDMPS_BCST(ops...) } + +// VBLENDMPS_BCST_Z: Blend Packed Single-Precision Floating-Point Vectors Using an OpMask Control (Broadcast, Zeroing Masking). +// +// Forms: +// +// VBLENDMPS.BCST.Z m32 xmm k xmm +// VBLENDMPS.BCST.Z m32 ymm k ymm +// VBLENDMPS.BCST.Z m32 zmm k zmm +// Construct and append a VBLENDMPS.BCST.Z instruction to the active function. +func (c *Context) VBLENDMPS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VBLENDMPS_BCST_Z(m, xyz, k, xyz1)) +} + +// VBLENDMPS_BCST_Z: Blend Packed Single-Precision Floating-Point Vectors Using an OpMask Control (Broadcast, Zeroing Masking). +// +// Forms: +// +// VBLENDMPS.BCST.Z m32 xmm k xmm +// VBLENDMPS.BCST.Z m32 ymm k ymm +// VBLENDMPS.BCST.Z m32 zmm k zmm +// Construct and append a VBLENDMPS.BCST.Z instruction to the active function. +// Operates on the global context. +func VBLENDMPS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VBLENDMPS_BCST_Z(m, xyz, k, xyz1) } + +// VBLENDMPS_Z: Blend Packed Single-Precision Floating-Point Vectors Using an OpMask Control (Zeroing Masking). +// +// Forms: +// +// VBLENDMPS.Z m128 xmm k xmm +// VBLENDMPS.Z m256 ymm k ymm +// VBLENDMPS.Z xmm xmm k xmm +// VBLENDMPS.Z ymm ymm k ymm +// VBLENDMPS.Z m512 zmm k zmm +// VBLENDMPS.Z zmm zmm k zmm +// Construct and append a VBLENDMPS.Z instruction to the active function. +func (c *Context) VBLENDMPS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VBLENDMPS_Z(mxyz, xyz, k, xyz1)) +} + +// VBLENDMPS_Z: Blend Packed Single-Precision Floating-Point Vectors Using an OpMask Control (Zeroing Masking). +// +// Forms: +// +// VBLENDMPS.Z m128 xmm k xmm +// VBLENDMPS.Z m256 ymm k ymm +// VBLENDMPS.Z xmm xmm k xmm +// VBLENDMPS.Z ymm ymm k ymm +// VBLENDMPS.Z m512 zmm k zmm +// VBLENDMPS.Z zmm zmm k zmm +// Construct and append a VBLENDMPS.Z instruction to the active function. +// Operates on the global context. +func VBLENDMPS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VBLENDMPS_Z(mxyz, xyz, k, xyz1) } + +// VBLENDPD: Blend Packed Double Precision Floating-Point Values. +// +// Forms: +// +// VBLENDPD imm8 m128 xmm xmm +// VBLENDPD imm8 m256 ymm ymm +// VBLENDPD imm8 xmm xmm xmm +// VBLENDPD imm8 ymm ymm ymm +// Construct and append a VBLENDPD instruction to the active function. +func (c *Context) VBLENDPD(i, mxy, xy, xy1 operand.Op) { + c.addinstruction(x86.VBLENDPD(i, mxy, xy, xy1)) +} + +// VBLENDPD: Blend Packed Double Precision Floating-Point Values. +// +// Forms: +// +// VBLENDPD imm8 m128 xmm xmm +// VBLENDPD imm8 m256 ymm ymm +// VBLENDPD imm8 xmm xmm xmm +// VBLENDPD imm8 ymm ymm ymm +// Construct and append a VBLENDPD instruction to the active function. +// Operates on the global context. +func VBLENDPD(i, mxy, xy, xy1 operand.Op) { ctx.VBLENDPD(i, mxy, xy, xy1) } + +// VBLENDPS: Blend Packed Single Precision Floating-Point Values. +// +// Forms: +// +// VBLENDPS imm8 m128 xmm xmm +// VBLENDPS imm8 m256 ymm ymm +// VBLENDPS imm8 xmm xmm xmm +// VBLENDPS imm8 ymm ymm ymm +// Construct and append a VBLENDPS instruction to the active function. +func (c *Context) VBLENDPS(i, mxy, xy, xy1 operand.Op) { + c.addinstruction(x86.VBLENDPS(i, mxy, xy, xy1)) +} + +// VBLENDPS: Blend Packed Single Precision Floating-Point Values. +// +// Forms: +// +// VBLENDPS imm8 m128 xmm xmm +// VBLENDPS imm8 m256 ymm ymm +// VBLENDPS imm8 xmm xmm xmm +// VBLENDPS imm8 ymm ymm ymm +// Construct and append a VBLENDPS instruction to the active function. +// Operates on the global context. +func VBLENDPS(i, mxy, xy, xy1 operand.Op) { ctx.VBLENDPS(i, mxy, xy, xy1) } + +// VBLENDVPD: Variable Blend Packed Double Precision Floating-Point Values. +// +// Forms: +// +// VBLENDVPD xmm m128 xmm xmm +// VBLENDVPD xmm xmm xmm xmm +// VBLENDVPD ymm m256 ymm ymm +// VBLENDVPD ymm ymm ymm ymm +// Construct and append a VBLENDVPD instruction to the active function. +func (c *Context) VBLENDVPD(xy, mxy, xy1, xy2 operand.Op) { + c.addinstruction(x86.VBLENDVPD(xy, mxy, xy1, xy2)) +} + +// VBLENDVPD: Variable Blend Packed Double Precision Floating-Point Values. +// +// Forms: +// +// VBLENDVPD xmm m128 xmm xmm +// VBLENDVPD xmm xmm xmm xmm +// VBLENDVPD ymm m256 ymm ymm +// VBLENDVPD ymm ymm ymm ymm +// Construct and append a VBLENDVPD instruction to the active function. +// Operates on the global context. +func VBLENDVPD(xy, mxy, xy1, xy2 operand.Op) { ctx.VBLENDVPD(xy, mxy, xy1, xy2) } + +// VBLENDVPS: Variable Blend Packed Single Precision Floating-Point Values. +// +// Forms: +// +// VBLENDVPS xmm m128 xmm xmm +// VBLENDVPS xmm xmm xmm xmm +// VBLENDVPS ymm m256 ymm ymm +// VBLENDVPS ymm ymm ymm ymm +// Construct and append a VBLENDVPS instruction to the active function. +func (c *Context) VBLENDVPS(xy, mxy, xy1, xy2 operand.Op) { + c.addinstruction(x86.VBLENDVPS(xy, mxy, xy1, xy2)) +} + +// VBLENDVPS: Variable Blend Packed Single Precision Floating-Point Values. +// +// Forms: +// +// VBLENDVPS xmm m128 xmm xmm +// VBLENDVPS xmm xmm xmm xmm +// VBLENDVPS ymm m256 ymm ymm +// VBLENDVPS ymm ymm ymm ymm +// Construct and append a VBLENDVPS instruction to the active function. +// Operates on the global context. +func VBLENDVPS(xy, mxy, xy1, xy2 operand.Op) { ctx.VBLENDVPS(xy, mxy, xy1, xy2) } + +// VBROADCASTF128: Broadcast 128 Bit of Floating-Point Data. +// +// Forms: +// +// VBROADCASTF128 m128 ymm +// Construct and append a VBROADCASTF128 instruction to the active function. +func (c *Context) VBROADCASTF128(m, y operand.Op) { + c.addinstruction(x86.VBROADCASTF128(m, y)) +} + +// VBROADCASTF128: Broadcast 128 Bit of Floating-Point Data. +// +// Forms: +// +// VBROADCASTF128 m128 ymm +// Construct and append a VBROADCASTF128 instruction to the active function. +// Operates on the global context. +func VBROADCASTF128(m, y operand.Op) { ctx.VBROADCASTF128(m, y) } + +// VBROADCASTF32X2: Broadcast Two Single-Precision Floating-Point Elements. +// +// Forms: +// +// VBROADCASTF32X2 m64 k ymm +// VBROADCASTF32X2 m64 ymm +// VBROADCASTF32X2 xmm k ymm +// VBROADCASTF32X2 xmm ymm +// VBROADCASTF32X2 m64 k zmm +// VBROADCASTF32X2 m64 zmm +// VBROADCASTF32X2 xmm k zmm +// VBROADCASTF32X2 xmm zmm +// Construct and append a VBROADCASTF32X2 instruction to the active function. +func (c *Context) VBROADCASTF32X2(ops ...operand.Op) { + c.addinstruction(x86.VBROADCASTF32X2(ops...)) +} + +// VBROADCASTF32X2: Broadcast Two Single-Precision Floating-Point Elements. +// +// Forms: +// +// VBROADCASTF32X2 m64 k ymm +// VBROADCASTF32X2 m64 ymm +// VBROADCASTF32X2 xmm k ymm +// VBROADCASTF32X2 xmm ymm +// VBROADCASTF32X2 m64 k zmm +// VBROADCASTF32X2 m64 zmm +// VBROADCASTF32X2 xmm k zmm +// VBROADCASTF32X2 xmm zmm +// Construct and append a VBROADCASTF32X2 instruction to the active function. +// Operates on the global context. +func VBROADCASTF32X2(ops ...operand.Op) { ctx.VBROADCASTF32X2(ops...) } + +// VBROADCASTF32X2_Z: Broadcast Two Single-Precision Floating-Point Elements (Zeroing Masking). +// +// Forms: +// +// VBROADCASTF32X2.Z m64 k ymm +// VBROADCASTF32X2.Z xmm k ymm +// VBROADCASTF32X2.Z m64 k zmm +// VBROADCASTF32X2.Z xmm k zmm +// Construct and append a VBROADCASTF32X2.Z instruction to the active function. +func (c *Context) VBROADCASTF32X2_Z(mx, k, yz operand.Op) { + c.addinstruction(x86.VBROADCASTF32X2_Z(mx, k, yz)) +} + +// VBROADCASTF32X2_Z: Broadcast Two Single-Precision Floating-Point Elements (Zeroing Masking). +// +// Forms: +// +// VBROADCASTF32X2.Z m64 k ymm +// VBROADCASTF32X2.Z xmm k ymm +// VBROADCASTF32X2.Z m64 k zmm +// VBROADCASTF32X2.Z xmm k zmm +// Construct and append a VBROADCASTF32X2.Z instruction to the active function. +// Operates on the global context. +func VBROADCASTF32X2_Z(mx, k, yz operand.Op) { ctx.VBROADCASTF32X2_Z(mx, k, yz) } + +// VBROADCASTF32X4: Broadcast Four Single-Precision Floating-Point Elements. +// +// Forms: +// +// VBROADCASTF32X4 m128 k ymm +// VBROADCASTF32X4 m128 ymm +// VBROADCASTF32X4 m128 k zmm +// VBROADCASTF32X4 m128 zmm +// Construct and append a VBROADCASTF32X4 instruction to the active function. +func (c *Context) VBROADCASTF32X4(ops ...operand.Op) { + c.addinstruction(x86.VBROADCASTF32X4(ops...)) +} + +// VBROADCASTF32X4: Broadcast Four Single-Precision Floating-Point Elements. +// +// Forms: +// +// VBROADCASTF32X4 m128 k ymm +// VBROADCASTF32X4 m128 ymm +// VBROADCASTF32X4 m128 k zmm +// VBROADCASTF32X4 m128 zmm +// Construct and append a VBROADCASTF32X4 instruction to the active function. +// Operates on the global context. +func VBROADCASTF32X4(ops ...operand.Op) { ctx.VBROADCASTF32X4(ops...) } + +// VBROADCASTF32X4_Z: Broadcast Four Single-Precision Floating-Point Elements (Zeroing Masking). +// +// Forms: +// +// VBROADCASTF32X4.Z m128 k ymm +// VBROADCASTF32X4.Z m128 k zmm +// Construct and append a VBROADCASTF32X4.Z instruction to the active function. +func (c *Context) VBROADCASTF32X4_Z(m, k, yz operand.Op) { + c.addinstruction(x86.VBROADCASTF32X4_Z(m, k, yz)) +} + +// VBROADCASTF32X4_Z: Broadcast Four Single-Precision Floating-Point Elements (Zeroing Masking). +// +// Forms: +// +// VBROADCASTF32X4.Z m128 k ymm +// VBROADCASTF32X4.Z m128 k zmm +// Construct and append a VBROADCASTF32X4.Z instruction to the active function. +// Operates on the global context. +func VBROADCASTF32X4_Z(m, k, yz operand.Op) { ctx.VBROADCASTF32X4_Z(m, k, yz) } + +// VBROADCASTF32X8: Broadcast Eight Single-Precision Floating-Point Elements. +// +// Forms: +// +// VBROADCASTF32X8 m256 k zmm +// VBROADCASTF32X8 m256 zmm +// Construct and append a VBROADCASTF32X8 instruction to the active function. +func (c *Context) VBROADCASTF32X8(ops ...operand.Op) { + c.addinstruction(x86.VBROADCASTF32X8(ops...)) +} + +// VBROADCASTF32X8: Broadcast Eight Single-Precision Floating-Point Elements. +// +// Forms: +// +// VBROADCASTF32X8 m256 k zmm +// VBROADCASTF32X8 m256 zmm +// Construct and append a VBROADCASTF32X8 instruction to the active function. +// Operates on the global context. +func VBROADCASTF32X8(ops ...operand.Op) { ctx.VBROADCASTF32X8(ops...) } + +// VBROADCASTF32X8_Z: Broadcast Eight Single-Precision Floating-Point Elements (Zeroing Masking). +// +// Forms: +// +// VBROADCASTF32X8.Z m256 k zmm +// Construct and append a VBROADCASTF32X8.Z instruction to the active function. +func (c *Context) VBROADCASTF32X8_Z(m, k, z operand.Op) { + c.addinstruction(x86.VBROADCASTF32X8_Z(m, k, z)) +} + +// VBROADCASTF32X8_Z: Broadcast Eight Single-Precision Floating-Point Elements (Zeroing Masking). +// +// Forms: +// +// VBROADCASTF32X8.Z m256 k zmm +// Construct and append a VBROADCASTF32X8.Z instruction to the active function. +// Operates on the global context. +func VBROADCASTF32X8_Z(m, k, z operand.Op) { ctx.VBROADCASTF32X8_Z(m, k, z) } + +// VBROADCASTF64X2: Broadcast Two Double-Precision Floating-Point Elements. +// +// Forms: +// +// VBROADCASTF64X2 m128 k ymm +// VBROADCASTF64X2 m128 ymm +// VBROADCASTF64X2 m128 k zmm +// VBROADCASTF64X2 m128 zmm +// Construct and append a VBROADCASTF64X2 instruction to the active function. +func (c *Context) VBROADCASTF64X2(ops ...operand.Op) { + c.addinstruction(x86.VBROADCASTF64X2(ops...)) +} + +// VBROADCASTF64X2: Broadcast Two Double-Precision Floating-Point Elements. +// +// Forms: +// +// VBROADCASTF64X2 m128 k ymm +// VBROADCASTF64X2 m128 ymm +// VBROADCASTF64X2 m128 k zmm +// VBROADCASTF64X2 m128 zmm +// Construct and append a VBROADCASTF64X2 instruction to the active function. +// Operates on the global context. +func VBROADCASTF64X2(ops ...operand.Op) { ctx.VBROADCASTF64X2(ops...) } + +// VBROADCASTF64X2_Z: Broadcast Two Double-Precision Floating-Point Elements (Zeroing Masking). +// +// Forms: +// +// VBROADCASTF64X2.Z m128 k ymm +// VBROADCASTF64X2.Z m128 k zmm +// Construct and append a VBROADCASTF64X2.Z instruction to the active function. +func (c *Context) VBROADCASTF64X2_Z(m, k, yz operand.Op) { + c.addinstruction(x86.VBROADCASTF64X2_Z(m, k, yz)) +} + +// VBROADCASTF64X2_Z: Broadcast Two Double-Precision Floating-Point Elements (Zeroing Masking). +// +// Forms: +// +// VBROADCASTF64X2.Z m128 k ymm +// VBROADCASTF64X2.Z m128 k zmm +// Construct and append a VBROADCASTF64X2.Z instruction to the active function. +// Operates on the global context. +func VBROADCASTF64X2_Z(m, k, yz operand.Op) { ctx.VBROADCASTF64X2_Z(m, k, yz) } + +// VBROADCASTF64X4: Broadcast Four Double-Precision Floating-Point Elements. +// +// Forms: +// +// VBROADCASTF64X4 m256 k zmm +// VBROADCASTF64X4 m256 zmm +// Construct and append a VBROADCASTF64X4 instruction to the active function. +func (c *Context) VBROADCASTF64X4(ops ...operand.Op) { + c.addinstruction(x86.VBROADCASTF64X4(ops...)) +} + +// VBROADCASTF64X4: Broadcast Four Double-Precision Floating-Point Elements. +// +// Forms: +// +// VBROADCASTF64X4 m256 k zmm +// VBROADCASTF64X4 m256 zmm +// Construct and append a VBROADCASTF64X4 instruction to the active function. +// Operates on the global context. +func VBROADCASTF64X4(ops ...operand.Op) { ctx.VBROADCASTF64X4(ops...) } + +// VBROADCASTF64X4_Z: Broadcast Four Double-Precision Floating-Point Elements (Zeroing Masking). +// +// Forms: +// +// VBROADCASTF64X4.Z m256 k zmm +// Construct and append a VBROADCASTF64X4.Z instruction to the active function. +func (c *Context) VBROADCASTF64X4_Z(m, k, z operand.Op) { + c.addinstruction(x86.VBROADCASTF64X4_Z(m, k, z)) +} + +// VBROADCASTF64X4_Z: Broadcast Four Double-Precision Floating-Point Elements (Zeroing Masking). +// +// Forms: +// +// VBROADCASTF64X4.Z m256 k zmm +// Construct and append a VBROADCASTF64X4.Z instruction to the active function. +// Operates on the global context. +func VBROADCASTF64X4_Z(m, k, z operand.Op) { ctx.VBROADCASTF64X4_Z(m, k, z) } + +// VBROADCASTI128: Broadcast 128 Bits of Integer Data. +// +// Forms: +// +// VBROADCASTI128 m128 ymm +// Construct and append a VBROADCASTI128 instruction to the active function. +func (c *Context) VBROADCASTI128(m, y operand.Op) { + c.addinstruction(x86.VBROADCASTI128(m, y)) +} + +// VBROADCASTI128: Broadcast 128 Bits of Integer Data. +// +// Forms: +// +// VBROADCASTI128 m128 ymm +// Construct and append a VBROADCASTI128 instruction to the active function. +// Operates on the global context. +func VBROADCASTI128(m, y operand.Op) { ctx.VBROADCASTI128(m, y) } + +// VBROADCASTI32X2: Broadcast Two Doubleword Elements. +// +// Forms: +// +// VBROADCASTI32X2 m64 k xmm +// VBROADCASTI32X2 m64 k ymm +// VBROADCASTI32X2 m64 xmm +// VBROADCASTI32X2 m64 ymm +// VBROADCASTI32X2 xmm k xmm +// VBROADCASTI32X2 xmm k ymm +// VBROADCASTI32X2 xmm xmm +// VBROADCASTI32X2 xmm ymm +// VBROADCASTI32X2 m64 k zmm +// VBROADCASTI32X2 m64 zmm +// VBROADCASTI32X2 xmm k zmm +// VBROADCASTI32X2 xmm zmm +// Construct and append a VBROADCASTI32X2 instruction to the active function. +func (c *Context) VBROADCASTI32X2(ops ...operand.Op) { + c.addinstruction(x86.VBROADCASTI32X2(ops...)) +} + +// VBROADCASTI32X2: Broadcast Two Doubleword Elements. +// +// Forms: +// +// VBROADCASTI32X2 m64 k xmm +// VBROADCASTI32X2 m64 k ymm +// VBROADCASTI32X2 m64 xmm +// VBROADCASTI32X2 m64 ymm +// VBROADCASTI32X2 xmm k xmm +// VBROADCASTI32X2 xmm k ymm +// VBROADCASTI32X2 xmm xmm +// VBROADCASTI32X2 xmm ymm +// VBROADCASTI32X2 m64 k zmm +// VBROADCASTI32X2 m64 zmm +// VBROADCASTI32X2 xmm k zmm +// VBROADCASTI32X2 xmm zmm +// Construct and append a VBROADCASTI32X2 instruction to the active function. +// Operates on the global context. +func VBROADCASTI32X2(ops ...operand.Op) { ctx.VBROADCASTI32X2(ops...) } + +// VBROADCASTI32X2_Z: Broadcast Two Doubleword Elements (Zeroing Masking). +// +// Forms: +// +// VBROADCASTI32X2.Z m64 k xmm +// VBROADCASTI32X2.Z m64 k ymm +// VBROADCASTI32X2.Z xmm k xmm +// VBROADCASTI32X2.Z xmm k ymm +// VBROADCASTI32X2.Z m64 k zmm +// VBROADCASTI32X2.Z xmm k zmm +// Construct and append a VBROADCASTI32X2.Z instruction to the active function. +func (c *Context) VBROADCASTI32X2_Z(mx, k, xyz operand.Op) { + c.addinstruction(x86.VBROADCASTI32X2_Z(mx, k, xyz)) +} + +// VBROADCASTI32X2_Z: Broadcast Two Doubleword Elements (Zeroing Masking). +// +// Forms: +// +// VBROADCASTI32X2.Z m64 k xmm +// VBROADCASTI32X2.Z m64 k ymm +// VBROADCASTI32X2.Z xmm k xmm +// VBROADCASTI32X2.Z xmm k ymm +// VBROADCASTI32X2.Z m64 k zmm +// VBROADCASTI32X2.Z xmm k zmm +// Construct and append a VBROADCASTI32X2.Z instruction to the active function. +// Operates on the global context. +func VBROADCASTI32X2_Z(mx, k, xyz operand.Op) { ctx.VBROADCASTI32X2_Z(mx, k, xyz) } + +// VBROADCASTI32X4: Broadcast Four Doubleword Elements. +// +// Forms: +// +// VBROADCASTI32X4 m128 k ymm +// VBROADCASTI32X4 m128 ymm +// VBROADCASTI32X4 m128 k zmm +// VBROADCASTI32X4 m128 zmm +// Construct and append a VBROADCASTI32X4 instruction to the active function. +func (c *Context) VBROADCASTI32X4(ops ...operand.Op) { + c.addinstruction(x86.VBROADCASTI32X4(ops...)) +} + +// VBROADCASTI32X4: Broadcast Four Doubleword Elements. +// +// Forms: +// +// VBROADCASTI32X4 m128 k ymm +// VBROADCASTI32X4 m128 ymm +// VBROADCASTI32X4 m128 k zmm +// VBROADCASTI32X4 m128 zmm +// Construct and append a VBROADCASTI32X4 instruction to the active function. +// Operates on the global context. +func VBROADCASTI32X4(ops ...operand.Op) { ctx.VBROADCASTI32X4(ops...) } + +// VBROADCASTI32X4_Z: Broadcast Four Doubleword Elements (Zeroing Masking). +// +// Forms: +// +// VBROADCASTI32X4.Z m128 k ymm +// VBROADCASTI32X4.Z m128 k zmm +// Construct and append a VBROADCASTI32X4.Z instruction to the active function. +func (c *Context) VBROADCASTI32X4_Z(m, k, yz operand.Op) { + c.addinstruction(x86.VBROADCASTI32X4_Z(m, k, yz)) +} + +// VBROADCASTI32X4_Z: Broadcast Four Doubleword Elements (Zeroing Masking). +// +// Forms: +// +// VBROADCASTI32X4.Z m128 k ymm +// VBROADCASTI32X4.Z m128 k zmm +// Construct and append a VBROADCASTI32X4.Z instruction to the active function. +// Operates on the global context. +func VBROADCASTI32X4_Z(m, k, yz operand.Op) { ctx.VBROADCASTI32X4_Z(m, k, yz) } + +// VBROADCASTI32X8: Broadcast Eight Doubleword Elements. +// +// Forms: +// +// VBROADCASTI32X8 m256 k zmm +// VBROADCASTI32X8 m256 zmm +// Construct and append a VBROADCASTI32X8 instruction to the active function. +func (c *Context) VBROADCASTI32X8(ops ...operand.Op) { + c.addinstruction(x86.VBROADCASTI32X8(ops...)) +} + +// VBROADCASTI32X8: Broadcast Eight Doubleword Elements. +// +// Forms: +// +// VBROADCASTI32X8 m256 k zmm +// VBROADCASTI32X8 m256 zmm +// Construct and append a VBROADCASTI32X8 instruction to the active function. +// Operates on the global context. +func VBROADCASTI32X8(ops ...operand.Op) { ctx.VBROADCASTI32X8(ops...) } + +// VBROADCASTI32X8_Z: Broadcast Eight Doubleword Elements (Zeroing Masking). +// +// Forms: +// +// VBROADCASTI32X8.Z m256 k zmm +// Construct and append a VBROADCASTI32X8.Z instruction to the active function. +func (c *Context) VBROADCASTI32X8_Z(m, k, z operand.Op) { + c.addinstruction(x86.VBROADCASTI32X8_Z(m, k, z)) +} + +// VBROADCASTI32X8_Z: Broadcast Eight Doubleword Elements (Zeroing Masking). +// +// Forms: +// +// VBROADCASTI32X8.Z m256 k zmm +// Construct and append a VBROADCASTI32X8.Z instruction to the active function. +// Operates on the global context. +func VBROADCASTI32X8_Z(m, k, z operand.Op) { ctx.VBROADCASTI32X8_Z(m, k, z) } + +// VBROADCASTI64X2: Broadcast Two Quadword Elements. +// +// Forms: +// +// VBROADCASTI64X2 m128 k ymm +// VBROADCASTI64X2 m128 ymm +// VBROADCASTI64X2 m128 k zmm +// VBROADCASTI64X2 m128 zmm +// Construct and append a VBROADCASTI64X2 instruction to the active function. +func (c *Context) VBROADCASTI64X2(ops ...operand.Op) { + c.addinstruction(x86.VBROADCASTI64X2(ops...)) +} + +// VBROADCASTI64X2: Broadcast Two Quadword Elements. +// +// Forms: +// +// VBROADCASTI64X2 m128 k ymm +// VBROADCASTI64X2 m128 ymm +// VBROADCASTI64X2 m128 k zmm +// VBROADCASTI64X2 m128 zmm +// Construct and append a VBROADCASTI64X2 instruction to the active function. +// Operates on the global context. +func VBROADCASTI64X2(ops ...operand.Op) { ctx.VBROADCASTI64X2(ops...) } + +// VBROADCASTI64X2_Z: Broadcast Two Quadword Elements (Zeroing Masking). +// +// Forms: +// +// VBROADCASTI64X2.Z m128 k ymm +// VBROADCASTI64X2.Z m128 k zmm +// Construct and append a VBROADCASTI64X2.Z instruction to the active function. +func (c *Context) VBROADCASTI64X2_Z(m, k, yz operand.Op) { + c.addinstruction(x86.VBROADCASTI64X2_Z(m, k, yz)) +} + +// VBROADCASTI64X2_Z: Broadcast Two Quadword Elements (Zeroing Masking). +// +// Forms: +// +// VBROADCASTI64X2.Z m128 k ymm +// VBROADCASTI64X2.Z m128 k zmm +// Construct and append a VBROADCASTI64X2.Z instruction to the active function. +// Operates on the global context. +func VBROADCASTI64X2_Z(m, k, yz operand.Op) { ctx.VBROADCASTI64X2_Z(m, k, yz) } + +// VBROADCASTI64X4: Broadcast Four Quadword Elements. +// +// Forms: +// +// VBROADCASTI64X4 m256 k zmm +// VBROADCASTI64X4 m256 zmm +// Construct and append a VBROADCASTI64X4 instruction to the active function. +func (c *Context) VBROADCASTI64X4(ops ...operand.Op) { + c.addinstruction(x86.VBROADCASTI64X4(ops...)) +} + +// VBROADCASTI64X4: Broadcast Four Quadword Elements. +// +// Forms: +// +// VBROADCASTI64X4 m256 k zmm +// VBROADCASTI64X4 m256 zmm +// Construct and append a VBROADCASTI64X4 instruction to the active function. +// Operates on the global context. +func VBROADCASTI64X4(ops ...operand.Op) { ctx.VBROADCASTI64X4(ops...) } + +// VBROADCASTI64X4_Z: Broadcast Four Quadword Elements (Zeroing Masking). +// +// Forms: +// +// VBROADCASTI64X4.Z m256 k zmm +// Construct and append a VBROADCASTI64X4.Z instruction to the active function. +func (c *Context) VBROADCASTI64X4_Z(m, k, z operand.Op) { + c.addinstruction(x86.VBROADCASTI64X4_Z(m, k, z)) +} + +// VBROADCASTI64X4_Z: Broadcast Four Quadword Elements (Zeroing Masking). +// +// Forms: +// +// VBROADCASTI64X4.Z m256 k zmm +// Construct and append a VBROADCASTI64X4.Z instruction to the active function. +// Operates on the global context. +func VBROADCASTI64X4_Z(m, k, z operand.Op) { ctx.VBROADCASTI64X4_Z(m, k, z) } + +// VBROADCASTSD: Broadcast Double-Precision Floating-Point Element. +// +// Forms: +// +// VBROADCASTSD xmm ymm +// VBROADCASTSD m64 ymm +// VBROADCASTSD m64 k ymm +// VBROADCASTSD xmm k ymm +// VBROADCASTSD m64 k zmm +// VBROADCASTSD m64 zmm +// VBROADCASTSD xmm k zmm +// VBROADCASTSD xmm zmm +// Construct and append a VBROADCASTSD instruction to the active function. +func (c *Context) VBROADCASTSD(ops ...operand.Op) { + c.addinstruction(x86.VBROADCASTSD(ops...)) +} + +// VBROADCASTSD: Broadcast Double-Precision Floating-Point Element. +// +// Forms: +// +// VBROADCASTSD xmm ymm +// VBROADCASTSD m64 ymm +// VBROADCASTSD m64 k ymm +// VBROADCASTSD xmm k ymm +// VBROADCASTSD m64 k zmm +// VBROADCASTSD m64 zmm +// VBROADCASTSD xmm k zmm +// VBROADCASTSD xmm zmm +// Construct and append a VBROADCASTSD instruction to the active function. +// Operates on the global context. +func VBROADCASTSD(ops ...operand.Op) { ctx.VBROADCASTSD(ops...) } + +// VBROADCASTSD_Z: Broadcast Double-Precision Floating-Point Element (Zeroing Masking). +// +// Forms: +// +// VBROADCASTSD.Z m64 k ymm +// VBROADCASTSD.Z xmm k ymm +// VBROADCASTSD.Z m64 k zmm +// VBROADCASTSD.Z xmm k zmm +// Construct and append a VBROADCASTSD.Z instruction to the active function. +func (c *Context) VBROADCASTSD_Z(mx, k, yz operand.Op) { + c.addinstruction(x86.VBROADCASTSD_Z(mx, k, yz)) +} + +// VBROADCASTSD_Z: Broadcast Double-Precision Floating-Point Element (Zeroing Masking). +// +// Forms: +// +// VBROADCASTSD.Z m64 k ymm +// VBROADCASTSD.Z xmm k ymm +// VBROADCASTSD.Z m64 k zmm +// VBROADCASTSD.Z xmm k zmm +// Construct and append a VBROADCASTSD.Z instruction to the active function. +// Operates on the global context. +func VBROADCASTSD_Z(mx, k, yz operand.Op) { ctx.VBROADCASTSD_Z(mx, k, yz) } + +// VBROADCASTSS: Broadcast Single-Precision Floating-Point Element. +// +// Forms: +// +// VBROADCASTSS xmm xmm +// VBROADCASTSS xmm ymm +// VBROADCASTSS m32 xmm +// VBROADCASTSS m32 ymm +// VBROADCASTSS m32 k ymm +// VBROADCASTSS xmm k ymm +// VBROADCASTSS m32 k zmm +// VBROADCASTSS m32 zmm +// VBROADCASTSS xmm k zmm +// VBROADCASTSS xmm zmm +// Construct and append a VBROADCASTSS instruction to the active function. +func (c *Context) VBROADCASTSS(ops ...operand.Op) { + c.addinstruction(x86.VBROADCASTSS(ops...)) +} + +// VBROADCASTSS: Broadcast Single-Precision Floating-Point Element. +// +// Forms: +// +// VBROADCASTSS xmm xmm +// VBROADCASTSS xmm ymm +// VBROADCASTSS m32 xmm +// VBROADCASTSS m32 ymm +// VBROADCASTSS m32 k ymm +// VBROADCASTSS xmm k ymm +// VBROADCASTSS m32 k zmm +// VBROADCASTSS m32 zmm +// VBROADCASTSS xmm k zmm +// VBROADCASTSS xmm zmm +// Construct and append a VBROADCASTSS instruction to the active function. +// Operates on the global context. +func VBROADCASTSS(ops ...operand.Op) { ctx.VBROADCASTSS(ops...) } + +// VBROADCASTSS_Z: Broadcast Single-Precision Floating-Point Element (Zeroing Masking). +// +// Forms: +// +// VBROADCASTSS.Z m32 k ymm +// VBROADCASTSS.Z xmm k ymm +// VBROADCASTSS.Z m32 k zmm +// VBROADCASTSS.Z xmm k zmm +// Construct and append a VBROADCASTSS.Z instruction to the active function. +func (c *Context) VBROADCASTSS_Z(mx, k, yz operand.Op) { + c.addinstruction(x86.VBROADCASTSS_Z(mx, k, yz)) +} + +// VBROADCASTSS_Z: Broadcast Single-Precision Floating-Point Element (Zeroing Masking). +// +// Forms: +// +// VBROADCASTSS.Z m32 k ymm +// VBROADCASTSS.Z xmm k ymm +// VBROADCASTSS.Z m32 k zmm +// VBROADCASTSS.Z xmm k zmm +// Construct and append a VBROADCASTSS.Z instruction to the active function. +// Operates on the global context. +func VBROADCASTSS_Z(mx, k, yz operand.Op) { ctx.VBROADCASTSS_Z(mx, k, yz) } + +// VCMPPD: Compare Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VCMPPD imm8 m128 xmm xmm +// VCMPPD imm8 m256 ymm ymm +// VCMPPD imm8 xmm xmm xmm +// VCMPPD imm8 ymm ymm ymm +// VCMPPD imm8 m128 xmm k k +// VCMPPD imm8 m128 xmm k +// VCMPPD imm8 m256 ymm k k +// VCMPPD imm8 m256 ymm k +// VCMPPD imm8 xmm xmm k k +// VCMPPD imm8 xmm xmm k +// VCMPPD imm8 ymm ymm k k +// VCMPPD imm8 ymm ymm k +// VCMPPD imm8 m512 zmm k k +// VCMPPD imm8 m512 zmm k +// VCMPPD imm8 zmm zmm k k +// VCMPPD imm8 zmm zmm k +// Construct and append a VCMPPD instruction to the active function. +func (c *Context) VCMPPD(ops ...operand.Op) { + c.addinstruction(x86.VCMPPD(ops...)) +} + +// VCMPPD: Compare Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VCMPPD imm8 m128 xmm xmm +// VCMPPD imm8 m256 ymm ymm +// VCMPPD imm8 xmm xmm xmm +// VCMPPD imm8 ymm ymm ymm +// VCMPPD imm8 m128 xmm k k +// VCMPPD imm8 m128 xmm k +// VCMPPD imm8 m256 ymm k k +// VCMPPD imm8 m256 ymm k +// VCMPPD imm8 xmm xmm k k +// VCMPPD imm8 xmm xmm k +// VCMPPD imm8 ymm ymm k k +// VCMPPD imm8 ymm ymm k +// VCMPPD imm8 m512 zmm k k +// VCMPPD imm8 m512 zmm k +// VCMPPD imm8 zmm zmm k k +// VCMPPD imm8 zmm zmm k +// Construct and append a VCMPPD instruction to the active function. +// Operates on the global context. +func VCMPPD(ops ...operand.Op) { ctx.VCMPPD(ops...) } + +// VCMPPD_BCST: Compare Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCMPPD.BCST imm8 m64 xmm k k +// VCMPPD.BCST imm8 m64 xmm k +// VCMPPD.BCST imm8 m64 ymm k k +// VCMPPD.BCST imm8 m64 ymm k +// VCMPPD.BCST imm8 m64 zmm k k +// VCMPPD.BCST imm8 m64 zmm k +// Construct and append a VCMPPD.BCST instruction to the active function. +func (c *Context) VCMPPD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCMPPD_BCST(ops...)) +} + +// VCMPPD_BCST: Compare Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCMPPD.BCST imm8 m64 xmm k k +// VCMPPD.BCST imm8 m64 xmm k +// VCMPPD.BCST imm8 m64 ymm k k +// VCMPPD.BCST imm8 m64 ymm k +// VCMPPD.BCST imm8 m64 zmm k k +// VCMPPD.BCST imm8 m64 zmm k +// Construct and append a VCMPPD.BCST instruction to the active function. +// Operates on the global context. +func VCMPPD_BCST(ops ...operand.Op) { ctx.VCMPPD_BCST(ops...) } + +// VCMPPD_SAE: Compare Packed Double-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VCMPPD.SAE imm8 zmm zmm k k +// VCMPPD.SAE imm8 zmm zmm k +// Construct and append a VCMPPD.SAE instruction to the active function. +func (c *Context) VCMPPD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCMPPD_SAE(ops...)) +} + +// VCMPPD_SAE: Compare Packed Double-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VCMPPD.SAE imm8 zmm zmm k k +// VCMPPD.SAE imm8 zmm zmm k +// Construct and append a VCMPPD.SAE instruction to the active function. +// Operates on the global context. +func VCMPPD_SAE(ops ...operand.Op) { ctx.VCMPPD_SAE(ops...) } + +// VCMPPS: Compare Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VCMPPS imm8 m128 xmm xmm +// VCMPPS imm8 m256 ymm ymm +// VCMPPS imm8 xmm xmm xmm +// VCMPPS imm8 ymm ymm ymm +// VCMPPS imm8 m128 xmm k k +// VCMPPS imm8 m128 xmm k +// VCMPPS imm8 m256 ymm k k +// VCMPPS imm8 m256 ymm k +// VCMPPS imm8 xmm xmm k k +// VCMPPS imm8 xmm xmm k +// VCMPPS imm8 ymm ymm k k +// VCMPPS imm8 ymm ymm k +// VCMPPS imm8 m512 zmm k k +// VCMPPS imm8 m512 zmm k +// VCMPPS imm8 zmm zmm k k +// VCMPPS imm8 zmm zmm k +// Construct and append a VCMPPS instruction to the active function. +func (c *Context) VCMPPS(ops ...operand.Op) { + c.addinstruction(x86.VCMPPS(ops...)) +} + +// VCMPPS: Compare Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VCMPPS imm8 m128 xmm xmm +// VCMPPS imm8 m256 ymm ymm +// VCMPPS imm8 xmm xmm xmm +// VCMPPS imm8 ymm ymm ymm +// VCMPPS imm8 m128 xmm k k +// VCMPPS imm8 m128 xmm k +// VCMPPS imm8 m256 ymm k k +// VCMPPS imm8 m256 ymm k +// VCMPPS imm8 xmm xmm k k +// VCMPPS imm8 xmm xmm k +// VCMPPS imm8 ymm ymm k k +// VCMPPS imm8 ymm ymm k +// VCMPPS imm8 m512 zmm k k +// VCMPPS imm8 m512 zmm k +// VCMPPS imm8 zmm zmm k k +// VCMPPS imm8 zmm zmm k +// Construct and append a VCMPPS instruction to the active function. +// Operates on the global context. +func VCMPPS(ops ...operand.Op) { ctx.VCMPPS(ops...) } + +// VCMPPS_BCST: Compare Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCMPPS.BCST imm8 m32 xmm k k +// VCMPPS.BCST imm8 m32 xmm k +// VCMPPS.BCST imm8 m32 ymm k k +// VCMPPS.BCST imm8 m32 ymm k +// VCMPPS.BCST imm8 m32 zmm k k +// VCMPPS.BCST imm8 m32 zmm k +// Construct and append a VCMPPS.BCST instruction to the active function. +func (c *Context) VCMPPS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCMPPS_BCST(ops...)) +} + +// VCMPPS_BCST: Compare Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCMPPS.BCST imm8 m32 xmm k k +// VCMPPS.BCST imm8 m32 xmm k +// VCMPPS.BCST imm8 m32 ymm k k +// VCMPPS.BCST imm8 m32 ymm k +// VCMPPS.BCST imm8 m32 zmm k k +// VCMPPS.BCST imm8 m32 zmm k +// Construct and append a VCMPPS.BCST instruction to the active function. +// Operates on the global context. +func VCMPPS_BCST(ops ...operand.Op) { ctx.VCMPPS_BCST(ops...) } + +// VCMPPS_SAE: Compare Packed Single-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VCMPPS.SAE imm8 zmm zmm k k +// VCMPPS.SAE imm8 zmm zmm k +// Construct and append a VCMPPS.SAE instruction to the active function. +func (c *Context) VCMPPS_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCMPPS_SAE(ops...)) +} + +// VCMPPS_SAE: Compare Packed Single-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VCMPPS.SAE imm8 zmm zmm k k +// VCMPPS.SAE imm8 zmm zmm k +// Construct and append a VCMPPS.SAE instruction to the active function. +// Operates on the global context. +func VCMPPS_SAE(ops ...operand.Op) { ctx.VCMPPS_SAE(ops...) } + +// VCMPSD: Compare Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VCMPSD imm8 m64 xmm xmm +// VCMPSD imm8 xmm xmm xmm +// VCMPSD imm8 m64 xmm k k +// VCMPSD imm8 m64 xmm k +// VCMPSD imm8 xmm xmm k k +// VCMPSD imm8 xmm xmm k +// Construct and append a VCMPSD instruction to the active function. +func (c *Context) VCMPSD(ops ...operand.Op) { + c.addinstruction(x86.VCMPSD(ops...)) +} + +// VCMPSD: Compare Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VCMPSD imm8 m64 xmm xmm +// VCMPSD imm8 xmm xmm xmm +// VCMPSD imm8 m64 xmm k k +// VCMPSD imm8 m64 xmm k +// VCMPSD imm8 xmm xmm k k +// VCMPSD imm8 xmm xmm k +// Construct and append a VCMPSD instruction to the active function. +// Operates on the global context. +func VCMPSD(ops ...operand.Op) { ctx.VCMPSD(ops...) } + +// VCMPSD_SAE: Compare Scalar Double-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VCMPSD.SAE imm8 xmm xmm k k +// VCMPSD.SAE imm8 xmm xmm k +// Construct and append a VCMPSD.SAE instruction to the active function. +func (c *Context) VCMPSD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCMPSD_SAE(ops...)) +} + +// VCMPSD_SAE: Compare Scalar Double-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VCMPSD.SAE imm8 xmm xmm k k +// VCMPSD.SAE imm8 xmm xmm k +// Construct and append a VCMPSD.SAE instruction to the active function. +// Operates on the global context. +func VCMPSD_SAE(ops ...operand.Op) { ctx.VCMPSD_SAE(ops...) } + +// VCMPSS: Compare Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VCMPSS imm8 m32 xmm xmm +// VCMPSS imm8 xmm xmm xmm +// VCMPSS imm8 m32 xmm k k +// VCMPSS imm8 m32 xmm k +// VCMPSS imm8 xmm xmm k k +// VCMPSS imm8 xmm xmm k +// Construct and append a VCMPSS instruction to the active function. +func (c *Context) VCMPSS(ops ...operand.Op) { + c.addinstruction(x86.VCMPSS(ops...)) +} + +// VCMPSS: Compare Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VCMPSS imm8 m32 xmm xmm +// VCMPSS imm8 xmm xmm xmm +// VCMPSS imm8 m32 xmm k k +// VCMPSS imm8 m32 xmm k +// VCMPSS imm8 xmm xmm k k +// VCMPSS imm8 xmm xmm k +// Construct and append a VCMPSS instruction to the active function. +// Operates on the global context. +func VCMPSS(ops ...operand.Op) { ctx.VCMPSS(ops...) } + +// VCMPSS_SAE: Compare Scalar Single-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VCMPSS.SAE imm8 xmm xmm k k +// VCMPSS.SAE imm8 xmm xmm k +// Construct and append a VCMPSS.SAE instruction to the active function. +func (c *Context) VCMPSS_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCMPSS_SAE(ops...)) +} + +// VCMPSS_SAE: Compare Scalar Single-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VCMPSS.SAE imm8 xmm xmm k k +// VCMPSS.SAE imm8 xmm xmm k +// Construct and append a VCMPSS.SAE instruction to the active function. +// Operates on the global context. +func VCMPSS_SAE(ops ...operand.Op) { ctx.VCMPSS_SAE(ops...) } + +// VCOMISD: Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS. +// +// Forms: +// +// VCOMISD m64 xmm +// VCOMISD xmm xmm +// Construct and append a VCOMISD instruction to the active function. +func (c *Context) VCOMISD(mx, x operand.Op) { + c.addinstruction(x86.VCOMISD(mx, x)) +} + +// VCOMISD: Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS. +// +// Forms: +// +// VCOMISD m64 xmm +// VCOMISD xmm xmm +// Construct and append a VCOMISD instruction to the active function. +// Operates on the global context. +func VCOMISD(mx, x operand.Op) { ctx.VCOMISD(mx, x) } + +// VCOMISD_SAE: Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS (Suppress All Exceptions). +// +// Forms: +// +// VCOMISD.SAE xmm xmm +// Construct and append a VCOMISD.SAE instruction to the active function. +func (c *Context) VCOMISD_SAE(x, x1 operand.Op) { + c.addinstruction(x86.VCOMISD_SAE(x, x1)) +} + +// VCOMISD_SAE: Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS (Suppress All Exceptions). +// +// Forms: +// +// VCOMISD.SAE xmm xmm +// Construct and append a VCOMISD.SAE instruction to the active function. +// Operates on the global context. +func VCOMISD_SAE(x, x1 operand.Op) { ctx.VCOMISD_SAE(x, x1) } + +// VCOMISS: Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS. +// +// Forms: +// +// VCOMISS m32 xmm +// VCOMISS xmm xmm +// Construct and append a VCOMISS instruction to the active function. +func (c *Context) VCOMISS(mx, x operand.Op) { + c.addinstruction(x86.VCOMISS(mx, x)) +} + +// VCOMISS: Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS. +// +// Forms: +// +// VCOMISS m32 xmm +// VCOMISS xmm xmm +// Construct and append a VCOMISS instruction to the active function. +// Operates on the global context. +func VCOMISS(mx, x operand.Op) { ctx.VCOMISS(mx, x) } + +// VCOMISS_SAE: Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS (Suppress All Exceptions). +// +// Forms: +// +// VCOMISS.SAE xmm xmm +// Construct and append a VCOMISS.SAE instruction to the active function. +func (c *Context) VCOMISS_SAE(x, x1 operand.Op) { + c.addinstruction(x86.VCOMISS_SAE(x, x1)) +} + +// VCOMISS_SAE: Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS (Suppress All Exceptions). +// +// Forms: +// +// VCOMISS.SAE xmm xmm +// Construct and append a VCOMISS.SAE instruction to the active function. +// Operates on the global context. +func VCOMISS_SAE(x, x1 operand.Op) { ctx.VCOMISS_SAE(x, x1) } + +// VCOMPRESSPD: Store Sparse Packed Double-Precision Floating-Point Values into Dense Memory/Register. +// +// Forms: +// +// VCOMPRESSPD xmm k m128 +// VCOMPRESSPD xmm k xmm +// VCOMPRESSPD xmm m128 +// VCOMPRESSPD xmm xmm +// VCOMPRESSPD ymm k m256 +// VCOMPRESSPD ymm k ymm +// VCOMPRESSPD ymm m256 +// VCOMPRESSPD ymm ymm +// VCOMPRESSPD zmm k m512 +// VCOMPRESSPD zmm k zmm +// VCOMPRESSPD zmm m512 +// VCOMPRESSPD zmm zmm +// Construct and append a VCOMPRESSPD instruction to the active function. +func (c *Context) VCOMPRESSPD(ops ...operand.Op) { + c.addinstruction(x86.VCOMPRESSPD(ops...)) +} + +// VCOMPRESSPD: Store Sparse Packed Double-Precision Floating-Point Values into Dense Memory/Register. +// +// Forms: +// +// VCOMPRESSPD xmm k m128 +// VCOMPRESSPD xmm k xmm +// VCOMPRESSPD xmm m128 +// VCOMPRESSPD xmm xmm +// VCOMPRESSPD ymm k m256 +// VCOMPRESSPD ymm k ymm +// VCOMPRESSPD ymm m256 +// VCOMPRESSPD ymm ymm +// VCOMPRESSPD zmm k m512 +// VCOMPRESSPD zmm k zmm +// VCOMPRESSPD zmm m512 +// VCOMPRESSPD zmm zmm +// Construct and append a VCOMPRESSPD instruction to the active function. +// Operates on the global context. +func VCOMPRESSPD(ops ...operand.Op) { ctx.VCOMPRESSPD(ops...) } + +// VCOMPRESSPD_Z: Store Sparse Packed Double-Precision Floating-Point Values into Dense Memory/Register (Zeroing Masking). +// +// Forms: +// +// VCOMPRESSPD.Z xmm k m128 +// VCOMPRESSPD.Z xmm k xmm +// VCOMPRESSPD.Z ymm k m256 +// VCOMPRESSPD.Z ymm k ymm +// VCOMPRESSPD.Z zmm k m512 +// VCOMPRESSPD.Z zmm k zmm +// Construct and append a VCOMPRESSPD.Z instruction to the active function. +func (c *Context) VCOMPRESSPD_Z(xyz, k, mxyz operand.Op) { + c.addinstruction(x86.VCOMPRESSPD_Z(xyz, k, mxyz)) +} + +// VCOMPRESSPD_Z: Store Sparse Packed Double-Precision Floating-Point Values into Dense Memory/Register (Zeroing Masking). +// +// Forms: +// +// VCOMPRESSPD.Z xmm k m128 +// VCOMPRESSPD.Z xmm k xmm +// VCOMPRESSPD.Z ymm k m256 +// VCOMPRESSPD.Z ymm k ymm +// VCOMPRESSPD.Z zmm k m512 +// VCOMPRESSPD.Z zmm k zmm +// Construct and append a VCOMPRESSPD.Z instruction to the active function. +// Operates on the global context. +func VCOMPRESSPD_Z(xyz, k, mxyz operand.Op) { ctx.VCOMPRESSPD_Z(xyz, k, mxyz) } + +// VCOMPRESSPS: Store Sparse Packed Single-Precision Floating-Point Values into Dense Memory/Register. +// +// Forms: +// +// VCOMPRESSPS xmm k m128 +// VCOMPRESSPS xmm k xmm +// VCOMPRESSPS xmm m128 +// VCOMPRESSPS xmm xmm +// VCOMPRESSPS ymm k m256 +// VCOMPRESSPS ymm k ymm +// VCOMPRESSPS ymm m256 +// VCOMPRESSPS ymm ymm +// VCOMPRESSPS zmm k m512 +// VCOMPRESSPS zmm k zmm +// VCOMPRESSPS zmm m512 +// VCOMPRESSPS zmm zmm +// Construct and append a VCOMPRESSPS instruction to the active function. +func (c *Context) VCOMPRESSPS(ops ...operand.Op) { + c.addinstruction(x86.VCOMPRESSPS(ops...)) +} + +// VCOMPRESSPS: Store Sparse Packed Single-Precision Floating-Point Values into Dense Memory/Register. +// +// Forms: +// +// VCOMPRESSPS xmm k m128 +// VCOMPRESSPS xmm k xmm +// VCOMPRESSPS xmm m128 +// VCOMPRESSPS xmm xmm +// VCOMPRESSPS ymm k m256 +// VCOMPRESSPS ymm k ymm +// VCOMPRESSPS ymm m256 +// VCOMPRESSPS ymm ymm +// VCOMPRESSPS zmm k m512 +// VCOMPRESSPS zmm k zmm +// VCOMPRESSPS zmm m512 +// VCOMPRESSPS zmm zmm +// Construct and append a VCOMPRESSPS instruction to the active function. +// Operates on the global context. +func VCOMPRESSPS(ops ...operand.Op) { ctx.VCOMPRESSPS(ops...) } + +// VCOMPRESSPS_Z: Store Sparse Packed Single-Precision Floating-Point Values into Dense Memory/Register (Zeroing Masking). +// +// Forms: +// +// VCOMPRESSPS.Z xmm k m128 +// VCOMPRESSPS.Z xmm k xmm +// VCOMPRESSPS.Z ymm k m256 +// VCOMPRESSPS.Z ymm k ymm +// VCOMPRESSPS.Z zmm k m512 +// VCOMPRESSPS.Z zmm k zmm +// Construct and append a VCOMPRESSPS.Z instruction to the active function. +func (c *Context) VCOMPRESSPS_Z(xyz, k, mxyz operand.Op) { + c.addinstruction(x86.VCOMPRESSPS_Z(xyz, k, mxyz)) +} + +// VCOMPRESSPS_Z: Store Sparse Packed Single-Precision Floating-Point Values into Dense Memory/Register (Zeroing Masking). +// +// Forms: +// +// VCOMPRESSPS.Z xmm k m128 +// VCOMPRESSPS.Z xmm k xmm +// VCOMPRESSPS.Z ymm k m256 +// VCOMPRESSPS.Z ymm k ymm +// VCOMPRESSPS.Z zmm k m512 +// VCOMPRESSPS.Z zmm k zmm +// Construct and append a VCOMPRESSPS.Z instruction to the active function. +// Operates on the global context. +func VCOMPRESSPS_Z(xyz, k, mxyz operand.Op) { ctx.VCOMPRESSPS_Z(xyz, k, mxyz) } + +// VCVTDQ2PD: Convert Packed Dword Integers to Packed Double-Precision FP Values. +// +// Forms: +// +// VCVTDQ2PD m128 ymm +// VCVTDQ2PD m64 xmm +// VCVTDQ2PD xmm xmm +// VCVTDQ2PD xmm ymm +// VCVTDQ2PD m128 k ymm +// VCVTDQ2PD m64 k xmm +// VCVTDQ2PD xmm k xmm +// VCVTDQ2PD xmm k ymm +// VCVTDQ2PD m256 k zmm +// VCVTDQ2PD m256 zmm +// VCVTDQ2PD ymm k zmm +// VCVTDQ2PD ymm zmm +// Construct and append a VCVTDQ2PD instruction to the active function. +func (c *Context) VCVTDQ2PD(ops ...operand.Op) { + c.addinstruction(x86.VCVTDQ2PD(ops...)) +} + +// VCVTDQ2PD: Convert Packed Dword Integers to Packed Double-Precision FP Values. +// +// Forms: +// +// VCVTDQ2PD m128 ymm +// VCVTDQ2PD m64 xmm +// VCVTDQ2PD xmm xmm +// VCVTDQ2PD xmm ymm +// VCVTDQ2PD m128 k ymm +// VCVTDQ2PD m64 k xmm +// VCVTDQ2PD xmm k xmm +// VCVTDQ2PD xmm k ymm +// VCVTDQ2PD m256 k zmm +// VCVTDQ2PD m256 zmm +// VCVTDQ2PD ymm k zmm +// VCVTDQ2PD ymm zmm +// Construct and append a VCVTDQ2PD instruction to the active function. +// Operates on the global context. +func VCVTDQ2PD(ops ...operand.Op) { ctx.VCVTDQ2PD(ops...) } + +// VCVTDQ2PD_BCST: Convert Packed Dword Integers to Packed Double-Precision FP Values (Broadcast). +// +// Forms: +// +// VCVTDQ2PD.BCST m32 k xmm +// VCVTDQ2PD.BCST m32 k ymm +// VCVTDQ2PD.BCST m32 xmm +// VCVTDQ2PD.BCST m32 ymm +// VCVTDQ2PD.BCST m32 k zmm +// VCVTDQ2PD.BCST m32 zmm +// Construct and append a VCVTDQ2PD.BCST instruction to the active function. +func (c *Context) VCVTDQ2PD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTDQ2PD_BCST(ops...)) +} + +// VCVTDQ2PD_BCST: Convert Packed Dword Integers to Packed Double-Precision FP Values (Broadcast). +// +// Forms: +// +// VCVTDQ2PD.BCST m32 k xmm +// VCVTDQ2PD.BCST m32 k ymm +// VCVTDQ2PD.BCST m32 xmm +// VCVTDQ2PD.BCST m32 ymm +// VCVTDQ2PD.BCST m32 k zmm +// VCVTDQ2PD.BCST m32 zmm +// Construct and append a VCVTDQ2PD.BCST instruction to the active function. +// Operates on the global context. +func VCVTDQ2PD_BCST(ops ...operand.Op) { ctx.VCVTDQ2PD_BCST(ops...) } + +// VCVTDQ2PD_BCST_Z: Convert Packed Dword Integers to Packed Double-Precision FP Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTDQ2PD.BCST.Z m32 k xmm +// VCVTDQ2PD.BCST.Z m32 k ymm +// VCVTDQ2PD.BCST.Z m32 k zmm +// Construct and append a VCVTDQ2PD.BCST.Z instruction to the active function. +func (c *Context) VCVTDQ2PD_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VCVTDQ2PD_BCST_Z(m, k, xyz)) +} + +// VCVTDQ2PD_BCST_Z: Convert Packed Dword Integers to Packed Double-Precision FP Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTDQ2PD.BCST.Z m32 k xmm +// VCVTDQ2PD.BCST.Z m32 k ymm +// VCVTDQ2PD.BCST.Z m32 k zmm +// Construct and append a VCVTDQ2PD.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTDQ2PD_BCST_Z(m, k, xyz operand.Op) { ctx.VCVTDQ2PD_BCST_Z(m, k, xyz) } + +// VCVTDQ2PD_Z: Convert Packed Dword Integers to Packed Double-Precision FP Values (Zeroing Masking). +// +// Forms: +// +// VCVTDQ2PD.Z m128 k ymm +// VCVTDQ2PD.Z m64 k xmm +// VCVTDQ2PD.Z xmm k xmm +// VCVTDQ2PD.Z xmm k ymm +// VCVTDQ2PD.Z m256 k zmm +// VCVTDQ2PD.Z ymm k zmm +// Construct and append a VCVTDQ2PD.Z instruction to the active function. +func (c *Context) VCVTDQ2PD_Z(mxy, k, xyz operand.Op) { + c.addinstruction(x86.VCVTDQ2PD_Z(mxy, k, xyz)) +} + +// VCVTDQ2PD_Z: Convert Packed Dword Integers to Packed Double-Precision FP Values (Zeroing Masking). +// +// Forms: +// +// VCVTDQ2PD.Z m128 k ymm +// VCVTDQ2PD.Z m64 k xmm +// VCVTDQ2PD.Z xmm k xmm +// VCVTDQ2PD.Z xmm k ymm +// VCVTDQ2PD.Z m256 k zmm +// VCVTDQ2PD.Z ymm k zmm +// Construct and append a VCVTDQ2PD.Z instruction to the active function. +// Operates on the global context. +func VCVTDQ2PD_Z(mxy, k, xyz operand.Op) { ctx.VCVTDQ2PD_Z(mxy, k, xyz) } + +// VCVTDQ2PS: Convert Packed Dword Integers to Packed Single-Precision FP Values. +// +// Forms: +// +// VCVTDQ2PS m128 xmm +// VCVTDQ2PS m256 ymm +// VCVTDQ2PS xmm xmm +// VCVTDQ2PS ymm ymm +// VCVTDQ2PS m128 k xmm +// VCVTDQ2PS m256 k ymm +// VCVTDQ2PS xmm k xmm +// VCVTDQ2PS ymm k ymm +// VCVTDQ2PS m512 k zmm +// VCVTDQ2PS m512 zmm +// VCVTDQ2PS zmm k zmm +// VCVTDQ2PS zmm zmm +// Construct and append a VCVTDQ2PS instruction to the active function. +func (c *Context) VCVTDQ2PS(ops ...operand.Op) { + c.addinstruction(x86.VCVTDQ2PS(ops...)) +} + +// VCVTDQ2PS: Convert Packed Dword Integers to Packed Single-Precision FP Values. +// +// Forms: +// +// VCVTDQ2PS m128 xmm +// VCVTDQ2PS m256 ymm +// VCVTDQ2PS xmm xmm +// VCVTDQ2PS ymm ymm +// VCVTDQ2PS m128 k xmm +// VCVTDQ2PS m256 k ymm +// VCVTDQ2PS xmm k xmm +// VCVTDQ2PS ymm k ymm +// VCVTDQ2PS m512 k zmm +// VCVTDQ2PS m512 zmm +// VCVTDQ2PS zmm k zmm +// VCVTDQ2PS zmm zmm +// Construct and append a VCVTDQ2PS instruction to the active function. +// Operates on the global context. +func VCVTDQ2PS(ops ...operand.Op) { ctx.VCVTDQ2PS(ops...) } + +// VCVTDQ2PS_BCST: Convert Packed Dword Integers to Packed Single-Precision FP Values (Broadcast). +// +// Forms: +// +// VCVTDQ2PS.BCST m32 k xmm +// VCVTDQ2PS.BCST m32 k ymm +// VCVTDQ2PS.BCST m32 xmm +// VCVTDQ2PS.BCST m32 ymm +// VCVTDQ2PS.BCST m32 k zmm +// VCVTDQ2PS.BCST m32 zmm +// Construct and append a VCVTDQ2PS.BCST instruction to the active function. +func (c *Context) VCVTDQ2PS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTDQ2PS_BCST(ops...)) +} + +// VCVTDQ2PS_BCST: Convert Packed Dword Integers to Packed Single-Precision FP Values (Broadcast). +// +// Forms: +// +// VCVTDQ2PS.BCST m32 k xmm +// VCVTDQ2PS.BCST m32 k ymm +// VCVTDQ2PS.BCST m32 xmm +// VCVTDQ2PS.BCST m32 ymm +// VCVTDQ2PS.BCST m32 k zmm +// VCVTDQ2PS.BCST m32 zmm +// Construct and append a VCVTDQ2PS.BCST instruction to the active function. +// Operates on the global context. +func VCVTDQ2PS_BCST(ops ...operand.Op) { ctx.VCVTDQ2PS_BCST(ops...) } + +// VCVTDQ2PS_BCST_Z: Convert Packed Dword Integers to Packed Single-Precision FP Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTDQ2PS.BCST.Z m32 k xmm +// VCVTDQ2PS.BCST.Z m32 k ymm +// VCVTDQ2PS.BCST.Z m32 k zmm +// Construct and append a VCVTDQ2PS.BCST.Z instruction to the active function. +func (c *Context) VCVTDQ2PS_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VCVTDQ2PS_BCST_Z(m, k, xyz)) +} + +// VCVTDQ2PS_BCST_Z: Convert Packed Dword Integers to Packed Single-Precision FP Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTDQ2PS.BCST.Z m32 k xmm +// VCVTDQ2PS.BCST.Z m32 k ymm +// VCVTDQ2PS.BCST.Z m32 k zmm +// Construct and append a VCVTDQ2PS.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTDQ2PS_BCST_Z(m, k, xyz operand.Op) { ctx.VCVTDQ2PS_BCST_Z(m, k, xyz) } + +// VCVTDQ2PS_RD_SAE: Convert Packed Dword Integers to Packed Single-Precision FP Values (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTDQ2PS.RD_SAE zmm k zmm +// VCVTDQ2PS.RD_SAE zmm zmm +// Construct and append a VCVTDQ2PS.RD_SAE instruction to the active function. +func (c *Context) VCVTDQ2PS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTDQ2PS_RD_SAE(ops...)) +} + +// VCVTDQ2PS_RD_SAE: Convert Packed Dword Integers to Packed Single-Precision FP Values (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTDQ2PS.RD_SAE zmm k zmm +// VCVTDQ2PS.RD_SAE zmm zmm +// Construct and append a VCVTDQ2PS.RD_SAE instruction to the active function. +// Operates on the global context. +func VCVTDQ2PS_RD_SAE(ops ...operand.Op) { ctx.VCVTDQ2PS_RD_SAE(ops...) } + +// VCVTDQ2PS_RD_SAE_Z: Convert Packed Dword Integers to Packed Single-Precision FP Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTDQ2PS.RD_SAE.Z zmm k zmm +// Construct and append a VCVTDQ2PS.RD_SAE.Z instruction to the active function. +func (c *Context) VCVTDQ2PS_RD_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTDQ2PS_RD_SAE_Z(z, k, z1)) +} + +// VCVTDQ2PS_RD_SAE_Z: Convert Packed Dword Integers to Packed Single-Precision FP Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTDQ2PS.RD_SAE.Z zmm k zmm +// Construct and append a VCVTDQ2PS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTDQ2PS_RD_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTDQ2PS_RD_SAE_Z(z, k, z1) } + +// VCVTDQ2PS_RN_SAE: Convert Packed Dword Integers to Packed Single-Precision FP Values (Round Towards Nearest). +// +// Forms: +// +// VCVTDQ2PS.RN_SAE zmm k zmm +// VCVTDQ2PS.RN_SAE zmm zmm +// Construct and append a VCVTDQ2PS.RN_SAE instruction to the active function. +func (c *Context) VCVTDQ2PS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTDQ2PS_RN_SAE(ops...)) +} + +// VCVTDQ2PS_RN_SAE: Convert Packed Dword Integers to Packed Single-Precision FP Values (Round Towards Nearest). +// +// Forms: +// +// VCVTDQ2PS.RN_SAE zmm k zmm +// VCVTDQ2PS.RN_SAE zmm zmm +// Construct and append a VCVTDQ2PS.RN_SAE instruction to the active function. +// Operates on the global context. +func VCVTDQ2PS_RN_SAE(ops ...operand.Op) { ctx.VCVTDQ2PS_RN_SAE(ops...) } + +// VCVTDQ2PS_RN_SAE_Z: Convert Packed Dword Integers to Packed Single-Precision FP Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTDQ2PS.RN_SAE.Z zmm k zmm +// Construct and append a VCVTDQ2PS.RN_SAE.Z instruction to the active function. +func (c *Context) VCVTDQ2PS_RN_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTDQ2PS_RN_SAE_Z(z, k, z1)) +} + +// VCVTDQ2PS_RN_SAE_Z: Convert Packed Dword Integers to Packed Single-Precision FP Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTDQ2PS.RN_SAE.Z zmm k zmm +// Construct and append a VCVTDQ2PS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTDQ2PS_RN_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTDQ2PS_RN_SAE_Z(z, k, z1) } + +// VCVTDQ2PS_RU_SAE: Convert Packed Dword Integers to Packed Single-Precision FP Values (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTDQ2PS.RU_SAE zmm k zmm +// VCVTDQ2PS.RU_SAE zmm zmm +// Construct and append a VCVTDQ2PS.RU_SAE instruction to the active function. +func (c *Context) VCVTDQ2PS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTDQ2PS_RU_SAE(ops...)) +} + +// VCVTDQ2PS_RU_SAE: Convert Packed Dword Integers to Packed Single-Precision FP Values (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTDQ2PS.RU_SAE zmm k zmm +// VCVTDQ2PS.RU_SAE zmm zmm +// Construct and append a VCVTDQ2PS.RU_SAE instruction to the active function. +// Operates on the global context. +func VCVTDQ2PS_RU_SAE(ops ...operand.Op) { ctx.VCVTDQ2PS_RU_SAE(ops...) } + +// VCVTDQ2PS_RU_SAE_Z: Convert Packed Dword Integers to Packed Single-Precision FP Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTDQ2PS.RU_SAE.Z zmm k zmm +// Construct and append a VCVTDQ2PS.RU_SAE.Z instruction to the active function. +func (c *Context) VCVTDQ2PS_RU_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTDQ2PS_RU_SAE_Z(z, k, z1)) +} + +// VCVTDQ2PS_RU_SAE_Z: Convert Packed Dword Integers to Packed Single-Precision FP Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTDQ2PS.RU_SAE.Z zmm k zmm +// Construct and append a VCVTDQ2PS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTDQ2PS_RU_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTDQ2PS_RU_SAE_Z(z, k, z1) } + +// VCVTDQ2PS_RZ_SAE: Convert Packed Dword Integers to Packed Single-Precision FP Values (Round Towards Zero). +// +// Forms: +// +// VCVTDQ2PS.RZ_SAE zmm k zmm +// VCVTDQ2PS.RZ_SAE zmm zmm +// Construct and append a VCVTDQ2PS.RZ_SAE instruction to the active function. +func (c *Context) VCVTDQ2PS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTDQ2PS_RZ_SAE(ops...)) +} + +// VCVTDQ2PS_RZ_SAE: Convert Packed Dword Integers to Packed Single-Precision FP Values (Round Towards Zero). +// +// Forms: +// +// VCVTDQ2PS.RZ_SAE zmm k zmm +// VCVTDQ2PS.RZ_SAE zmm zmm +// Construct and append a VCVTDQ2PS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VCVTDQ2PS_RZ_SAE(ops ...operand.Op) { ctx.VCVTDQ2PS_RZ_SAE(ops...) } + +// VCVTDQ2PS_RZ_SAE_Z: Convert Packed Dword Integers to Packed Single-Precision FP Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTDQ2PS.RZ_SAE.Z zmm k zmm +// Construct and append a VCVTDQ2PS.RZ_SAE.Z instruction to the active function. +func (c *Context) VCVTDQ2PS_RZ_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTDQ2PS_RZ_SAE_Z(z, k, z1)) +} + +// VCVTDQ2PS_RZ_SAE_Z: Convert Packed Dword Integers to Packed Single-Precision FP Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTDQ2PS.RZ_SAE.Z zmm k zmm +// Construct and append a VCVTDQ2PS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTDQ2PS_RZ_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTDQ2PS_RZ_SAE_Z(z, k, z1) } + +// VCVTDQ2PS_Z: Convert Packed Dword Integers to Packed Single-Precision FP Values (Zeroing Masking). +// +// Forms: +// +// VCVTDQ2PS.Z m128 k xmm +// VCVTDQ2PS.Z m256 k ymm +// VCVTDQ2PS.Z xmm k xmm +// VCVTDQ2PS.Z ymm k ymm +// VCVTDQ2PS.Z m512 k zmm +// VCVTDQ2PS.Z zmm k zmm +// Construct and append a VCVTDQ2PS.Z instruction to the active function. +func (c *Context) VCVTDQ2PS_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VCVTDQ2PS_Z(mxyz, k, xyz)) +} + +// VCVTDQ2PS_Z: Convert Packed Dword Integers to Packed Single-Precision FP Values (Zeroing Masking). +// +// Forms: +// +// VCVTDQ2PS.Z m128 k xmm +// VCVTDQ2PS.Z m256 k ymm +// VCVTDQ2PS.Z xmm k xmm +// VCVTDQ2PS.Z ymm k ymm +// VCVTDQ2PS.Z m512 k zmm +// VCVTDQ2PS.Z zmm k zmm +// Construct and append a VCVTDQ2PS.Z instruction to the active function. +// Operates on the global context. +func VCVTDQ2PS_Z(mxyz, k, xyz operand.Op) { ctx.VCVTDQ2PS_Z(mxyz, k, xyz) } + +// VCVTPD2DQ: Convert Packed Double-Precision FP Values to Packed Dword Integers. +// +// Forms: +// +// VCVTPD2DQ m512 k ymm +// VCVTPD2DQ m512 ymm +// VCVTPD2DQ zmm k ymm +// VCVTPD2DQ zmm ymm +// Construct and append a VCVTPD2DQ instruction to the active function. +func (c *Context) VCVTPD2DQ(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2DQ(ops...)) +} + +// VCVTPD2DQ: Convert Packed Double-Precision FP Values to Packed Dword Integers. +// +// Forms: +// +// VCVTPD2DQ m512 k ymm +// VCVTPD2DQ m512 ymm +// VCVTPD2DQ zmm k ymm +// VCVTPD2DQ zmm ymm +// Construct and append a VCVTPD2DQ instruction to the active function. +// Operates on the global context. +func VCVTPD2DQ(ops ...operand.Op) { ctx.VCVTPD2DQ(ops...) } + +// VCVTPD2DQX: Convert Packed Double-Precision FP Values to Packed Dword Integers. +// +// Forms: +// +// VCVTPD2DQX m128 xmm +// VCVTPD2DQX xmm xmm +// VCVTPD2DQX m128 k xmm +// VCVTPD2DQX xmm k xmm +// Construct and append a VCVTPD2DQX instruction to the active function. +func (c *Context) VCVTPD2DQX(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2DQX(ops...)) +} + +// VCVTPD2DQX: Convert Packed Double-Precision FP Values to Packed Dword Integers. +// +// Forms: +// +// VCVTPD2DQX m128 xmm +// VCVTPD2DQX xmm xmm +// VCVTPD2DQX m128 k xmm +// VCVTPD2DQX xmm k xmm +// Construct and append a VCVTPD2DQX instruction to the active function. +// Operates on the global context. +func VCVTPD2DQX(ops ...operand.Op) { ctx.VCVTPD2DQX(ops...) } + +// VCVTPD2DQX_BCST: Convert Packed Double-Precision FP Values to Packed Dword Integers (Broadcast). +// +// Forms: +// +// VCVTPD2DQX.BCST m64 k xmm +// VCVTPD2DQX.BCST m64 xmm +// Construct and append a VCVTPD2DQX.BCST instruction to the active function. +func (c *Context) VCVTPD2DQX_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2DQX_BCST(ops...)) +} + +// VCVTPD2DQX_BCST: Convert Packed Double-Precision FP Values to Packed Dword Integers (Broadcast). +// +// Forms: +// +// VCVTPD2DQX.BCST m64 k xmm +// VCVTPD2DQX.BCST m64 xmm +// Construct and append a VCVTPD2DQX.BCST instruction to the active function. +// Operates on the global context. +func VCVTPD2DQX_BCST(ops ...operand.Op) { ctx.VCVTPD2DQX_BCST(ops...) } + +// VCVTPD2DQX_BCST_Z: Convert Packed Double-Precision FP Values to Packed Dword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2DQX.BCST.Z m64 k xmm +// Construct and append a VCVTPD2DQX.BCST.Z instruction to the active function. +func (c *Context) VCVTPD2DQX_BCST_Z(m, k, x operand.Op) { + c.addinstruction(x86.VCVTPD2DQX_BCST_Z(m, k, x)) +} + +// VCVTPD2DQX_BCST_Z: Convert Packed Double-Precision FP Values to Packed Dword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2DQX.BCST.Z m64 k xmm +// Construct and append a VCVTPD2DQX.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2DQX_BCST_Z(m, k, x operand.Op) { ctx.VCVTPD2DQX_BCST_Z(m, k, x) } + +// VCVTPD2DQX_Z: Convert Packed Double-Precision FP Values to Packed Dword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTPD2DQX.Z m128 k xmm +// VCVTPD2DQX.Z xmm k xmm +// Construct and append a VCVTPD2DQX.Z instruction to the active function. +func (c *Context) VCVTPD2DQX_Z(mx, k, x operand.Op) { + c.addinstruction(x86.VCVTPD2DQX_Z(mx, k, x)) +} + +// VCVTPD2DQX_Z: Convert Packed Double-Precision FP Values to Packed Dword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTPD2DQX.Z m128 k xmm +// VCVTPD2DQX.Z xmm k xmm +// Construct and append a VCVTPD2DQX.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2DQX_Z(mx, k, x operand.Op) { ctx.VCVTPD2DQX_Z(mx, k, x) } + +// VCVTPD2DQY: Convert Packed Double-Precision FP Values to Packed Dword Integers. +// +// Forms: +// +// VCVTPD2DQY m256 xmm +// VCVTPD2DQY ymm xmm +// VCVTPD2DQY m256 k xmm +// VCVTPD2DQY ymm k xmm +// Construct and append a VCVTPD2DQY instruction to the active function. +func (c *Context) VCVTPD2DQY(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2DQY(ops...)) +} + +// VCVTPD2DQY: Convert Packed Double-Precision FP Values to Packed Dword Integers. +// +// Forms: +// +// VCVTPD2DQY m256 xmm +// VCVTPD2DQY ymm xmm +// VCVTPD2DQY m256 k xmm +// VCVTPD2DQY ymm k xmm +// Construct and append a VCVTPD2DQY instruction to the active function. +// Operates on the global context. +func VCVTPD2DQY(ops ...operand.Op) { ctx.VCVTPD2DQY(ops...) } + +// VCVTPD2DQY_BCST: Convert Packed Double-Precision FP Values to Packed Dword Integers (Broadcast). +// +// Forms: +// +// VCVTPD2DQY.BCST m64 k xmm +// VCVTPD2DQY.BCST m64 xmm +// Construct and append a VCVTPD2DQY.BCST instruction to the active function. +func (c *Context) VCVTPD2DQY_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2DQY_BCST(ops...)) +} + +// VCVTPD2DQY_BCST: Convert Packed Double-Precision FP Values to Packed Dword Integers (Broadcast). +// +// Forms: +// +// VCVTPD2DQY.BCST m64 k xmm +// VCVTPD2DQY.BCST m64 xmm +// Construct and append a VCVTPD2DQY.BCST instruction to the active function. +// Operates on the global context. +func VCVTPD2DQY_BCST(ops ...operand.Op) { ctx.VCVTPD2DQY_BCST(ops...) } + +// VCVTPD2DQY_BCST_Z: Convert Packed Double-Precision FP Values to Packed Dword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2DQY.BCST.Z m64 k xmm +// Construct and append a VCVTPD2DQY.BCST.Z instruction to the active function. +func (c *Context) VCVTPD2DQY_BCST_Z(m, k, x operand.Op) { + c.addinstruction(x86.VCVTPD2DQY_BCST_Z(m, k, x)) +} + +// VCVTPD2DQY_BCST_Z: Convert Packed Double-Precision FP Values to Packed Dword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2DQY.BCST.Z m64 k xmm +// Construct and append a VCVTPD2DQY.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2DQY_BCST_Z(m, k, x operand.Op) { ctx.VCVTPD2DQY_BCST_Z(m, k, x) } + +// VCVTPD2DQY_Z: Convert Packed Double-Precision FP Values to Packed Dword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTPD2DQY.Z m256 k xmm +// VCVTPD2DQY.Z ymm k xmm +// Construct and append a VCVTPD2DQY.Z instruction to the active function. +func (c *Context) VCVTPD2DQY_Z(my, k, x operand.Op) { + c.addinstruction(x86.VCVTPD2DQY_Z(my, k, x)) +} + +// VCVTPD2DQY_Z: Convert Packed Double-Precision FP Values to Packed Dword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTPD2DQY.Z m256 k xmm +// VCVTPD2DQY.Z ymm k xmm +// Construct and append a VCVTPD2DQY.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2DQY_Z(my, k, x operand.Op) { ctx.VCVTPD2DQY_Z(my, k, x) } + +// VCVTPD2DQ_BCST: Convert Packed Double-Precision FP Values to Packed Dword Integers (Broadcast). +// +// Forms: +// +// VCVTPD2DQ.BCST m64 k ymm +// VCVTPD2DQ.BCST m64 ymm +// Construct and append a VCVTPD2DQ.BCST instruction to the active function. +func (c *Context) VCVTPD2DQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2DQ_BCST(ops...)) +} + +// VCVTPD2DQ_BCST: Convert Packed Double-Precision FP Values to Packed Dword Integers (Broadcast). +// +// Forms: +// +// VCVTPD2DQ.BCST m64 k ymm +// VCVTPD2DQ.BCST m64 ymm +// Construct and append a VCVTPD2DQ.BCST instruction to the active function. +// Operates on the global context. +func VCVTPD2DQ_BCST(ops ...operand.Op) { ctx.VCVTPD2DQ_BCST(ops...) } + +// VCVTPD2DQ_BCST_Z: Convert Packed Double-Precision FP Values to Packed Dword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2DQ.BCST.Z m64 k ymm +// Construct and append a VCVTPD2DQ.BCST.Z instruction to the active function. +func (c *Context) VCVTPD2DQ_BCST_Z(m, k, y operand.Op) { + c.addinstruction(x86.VCVTPD2DQ_BCST_Z(m, k, y)) +} + +// VCVTPD2DQ_BCST_Z: Convert Packed Double-Precision FP Values to Packed Dword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2DQ.BCST.Z m64 k ymm +// Construct and append a VCVTPD2DQ.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2DQ_BCST_Z(m, k, y operand.Op) { ctx.VCVTPD2DQ_BCST_Z(m, k, y) } + +// VCVTPD2DQ_RD_SAE: Convert Packed Double-Precision FP Values to Packed Dword Integers (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTPD2DQ.RD_SAE zmm k ymm +// VCVTPD2DQ.RD_SAE zmm ymm +// Construct and append a VCVTPD2DQ.RD_SAE instruction to the active function. +func (c *Context) VCVTPD2DQ_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2DQ_RD_SAE(ops...)) +} + +// VCVTPD2DQ_RD_SAE: Convert Packed Double-Precision FP Values to Packed Dword Integers (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTPD2DQ.RD_SAE zmm k ymm +// VCVTPD2DQ.RD_SAE zmm ymm +// Construct and append a VCVTPD2DQ.RD_SAE instruction to the active function. +// Operates on the global context. +func VCVTPD2DQ_RD_SAE(ops ...operand.Op) { ctx.VCVTPD2DQ_RD_SAE(ops...) } + +// VCVTPD2DQ_RD_SAE_Z: Convert Packed Double-Precision FP Values to Packed Dword Integers (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPD2DQ.RD_SAE.Z zmm k ymm +// Construct and append a VCVTPD2DQ.RD_SAE.Z instruction to the active function. +func (c *Context) VCVTPD2DQ_RD_SAE_Z(z, k, y operand.Op) { + c.addinstruction(x86.VCVTPD2DQ_RD_SAE_Z(z, k, y)) +} + +// VCVTPD2DQ_RD_SAE_Z: Convert Packed Double-Precision FP Values to Packed Dword Integers (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPD2DQ.RD_SAE.Z zmm k ymm +// Construct and append a VCVTPD2DQ.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2DQ_RD_SAE_Z(z, k, y operand.Op) { ctx.VCVTPD2DQ_RD_SAE_Z(z, k, y) } + +// VCVTPD2DQ_RN_SAE: Convert Packed Double-Precision FP Values to Packed Dword Integers (Round Towards Nearest). +// +// Forms: +// +// VCVTPD2DQ.RN_SAE zmm k ymm +// VCVTPD2DQ.RN_SAE zmm ymm +// Construct and append a VCVTPD2DQ.RN_SAE instruction to the active function. +func (c *Context) VCVTPD2DQ_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2DQ_RN_SAE(ops...)) +} + +// VCVTPD2DQ_RN_SAE: Convert Packed Double-Precision FP Values to Packed Dword Integers (Round Towards Nearest). +// +// Forms: +// +// VCVTPD2DQ.RN_SAE zmm k ymm +// VCVTPD2DQ.RN_SAE zmm ymm +// Construct and append a VCVTPD2DQ.RN_SAE instruction to the active function. +// Operates on the global context. +func VCVTPD2DQ_RN_SAE(ops ...operand.Op) { ctx.VCVTPD2DQ_RN_SAE(ops...) } + +// VCVTPD2DQ_RN_SAE_Z: Convert Packed Double-Precision FP Values to Packed Dword Integers (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTPD2DQ.RN_SAE.Z zmm k ymm +// Construct and append a VCVTPD2DQ.RN_SAE.Z instruction to the active function. +func (c *Context) VCVTPD2DQ_RN_SAE_Z(z, k, y operand.Op) { + c.addinstruction(x86.VCVTPD2DQ_RN_SAE_Z(z, k, y)) +} + +// VCVTPD2DQ_RN_SAE_Z: Convert Packed Double-Precision FP Values to Packed Dword Integers (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTPD2DQ.RN_SAE.Z zmm k ymm +// Construct and append a VCVTPD2DQ.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2DQ_RN_SAE_Z(z, k, y operand.Op) { ctx.VCVTPD2DQ_RN_SAE_Z(z, k, y) } + +// VCVTPD2DQ_RU_SAE: Convert Packed Double-Precision FP Values to Packed Dword Integers (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTPD2DQ.RU_SAE zmm k ymm +// VCVTPD2DQ.RU_SAE zmm ymm +// Construct and append a VCVTPD2DQ.RU_SAE instruction to the active function. +func (c *Context) VCVTPD2DQ_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2DQ_RU_SAE(ops...)) +} + +// VCVTPD2DQ_RU_SAE: Convert Packed Double-Precision FP Values to Packed Dword Integers (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTPD2DQ.RU_SAE zmm k ymm +// VCVTPD2DQ.RU_SAE zmm ymm +// Construct and append a VCVTPD2DQ.RU_SAE instruction to the active function. +// Operates on the global context. +func VCVTPD2DQ_RU_SAE(ops ...operand.Op) { ctx.VCVTPD2DQ_RU_SAE(ops...) } + +// VCVTPD2DQ_RU_SAE_Z: Convert Packed Double-Precision FP Values to Packed Dword Integers (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPD2DQ.RU_SAE.Z zmm k ymm +// Construct and append a VCVTPD2DQ.RU_SAE.Z instruction to the active function. +func (c *Context) VCVTPD2DQ_RU_SAE_Z(z, k, y operand.Op) { + c.addinstruction(x86.VCVTPD2DQ_RU_SAE_Z(z, k, y)) +} + +// VCVTPD2DQ_RU_SAE_Z: Convert Packed Double-Precision FP Values to Packed Dword Integers (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPD2DQ.RU_SAE.Z zmm k ymm +// Construct and append a VCVTPD2DQ.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2DQ_RU_SAE_Z(z, k, y operand.Op) { ctx.VCVTPD2DQ_RU_SAE_Z(z, k, y) } + +// VCVTPD2DQ_RZ_SAE: Convert Packed Double-Precision FP Values to Packed Dword Integers (Round Towards Zero). +// +// Forms: +// +// VCVTPD2DQ.RZ_SAE zmm k ymm +// VCVTPD2DQ.RZ_SAE zmm ymm +// Construct and append a VCVTPD2DQ.RZ_SAE instruction to the active function. +func (c *Context) VCVTPD2DQ_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2DQ_RZ_SAE(ops...)) +} + +// VCVTPD2DQ_RZ_SAE: Convert Packed Double-Precision FP Values to Packed Dword Integers (Round Towards Zero). +// +// Forms: +// +// VCVTPD2DQ.RZ_SAE zmm k ymm +// VCVTPD2DQ.RZ_SAE zmm ymm +// Construct and append a VCVTPD2DQ.RZ_SAE instruction to the active function. +// Operates on the global context. +func VCVTPD2DQ_RZ_SAE(ops ...operand.Op) { ctx.VCVTPD2DQ_RZ_SAE(ops...) } + +// VCVTPD2DQ_RZ_SAE_Z: Convert Packed Double-Precision FP Values to Packed Dword Integers (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTPD2DQ.RZ_SAE.Z zmm k ymm +// Construct and append a VCVTPD2DQ.RZ_SAE.Z instruction to the active function. +func (c *Context) VCVTPD2DQ_RZ_SAE_Z(z, k, y operand.Op) { + c.addinstruction(x86.VCVTPD2DQ_RZ_SAE_Z(z, k, y)) +} + +// VCVTPD2DQ_RZ_SAE_Z: Convert Packed Double-Precision FP Values to Packed Dword Integers (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTPD2DQ.RZ_SAE.Z zmm k ymm +// Construct and append a VCVTPD2DQ.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2DQ_RZ_SAE_Z(z, k, y operand.Op) { ctx.VCVTPD2DQ_RZ_SAE_Z(z, k, y) } + +// VCVTPD2DQ_Z: Convert Packed Double-Precision FP Values to Packed Dword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTPD2DQ.Z m512 k ymm +// VCVTPD2DQ.Z zmm k ymm +// Construct and append a VCVTPD2DQ.Z instruction to the active function. +func (c *Context) VCVTPD2DQ_Z(mz, k, y operand.Op) { + c.addinstruction(x86.VCVTPD2DQ_Z(mz, k, y)) +} + +// VCVTPD2DQ_Z: Convert Packed Double-Precision FP Values to Packed Dword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTPD2DQ.Z m512 k ymm +// VCVTPD2DQ.Z zmm k ymm +// Construct and append a VCVTPD2DQ.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2DQ_Z(mz, k, y operand.Op) { ctx.VCVTPD2DQ_Z(mz, k, y) } + +// VCVTPD2PS: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values. +// +// Forms: +// +// VCVTPD2PS m512 k ymm +// VCVTPD2PS m512 ymm +// VCVTPD2PS zmm k ymm +// VCVTPD2PS zmm ymm +// Construct and append a VCVTPD2PS instruction to the active function. +func (c *Context) VCVTPD2PS(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2PS(ops...)) +} + +// VCVTPD2PS: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values. +// +// Forms: +// +// VCVTPD2PS m512 k ymm +// VCVTPD2PS m512 ymm +// VCVTPD2PS zmm k ymm +// VCVTPD2PS zmm ymm +// Construct and append a VCVTPD2PS instruction to the active function. +// Operates on the global context. +func VCVTPD2PS(ops ...operand.Op) { ctx.VCVTPD2PS(ops...) } + +// VCVTPD2PSX: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values. +// +// Forms: +// +// VCVTPD2PSX m128 xmm +// VCVTPD2PSX xmm xmm +// VCVTPD2PSX m128 k xmm +// VCVTPD2PSX xmm k xmm +// Construct and append a VCVTPD2PSX instruction to the active function. +func (c *Context) VCVTPD2PSX(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2PSX(ops...)) +} + +// VCVTPD2PSX: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values. +// +// Forms: +// +// VCVTPD2PSX m128 xmm +// VCVTPD2PSX xmm xmm +// VCVTPD2PSX m128 k xmm +// VCVTPD2PSX xmm k xmm +// Construct and append a VCVTPD2PSX instruction to the active function. +// Operates on the global context. +func VCVTPD2PSX(ops ...operand.Op) { ctx.VCVTPD2PSX(ops...) } + +// VCVTPD2PSX_BCST: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Broadcast). +// +// Forms: +// +// VCVTPD2PSX.BCST m64 k xmm +// VCVTPD2PSX.BCST m64 xmm +// Construct and append a VCVTPD2PSX.BCST instruction to the active function. +func (c *Context) VCVTPD2PSX_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2PSX_BCST(ops...)) +} + +// VCVTPD2PSX_BCST: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Broadcast). +// +// Forms: +// +// VCVTPD2PSX.BCST m64 k xmm +// VCVTPD2PSX.BCST m64 xmm +// Construct and append a VCVTPD2PSX.BCST instruction to the active function. +// Operates on the global context. +func VCVTPD2PSX_BCST(ops ...operand.Op) { ctx.VCVTPD2PSX_BCST(ops...) } + +// VCVTPD2PSX_BCST_Z: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2PSX.BCST.Z m64 k xmm +// Construct and append a VCVTPD2PSX.BCST.Z instruction to the active function. +func (c *Context) VCVTPD2PSX_BCST_Z(m, k, x operand.Op) { + c.addinstruction(x86.VCVTPD2PSX_BCST_Z(m, k, x)) +} + +// VCVTPD2PSX_BCST_Z: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2PSX.BCST.Z m64 k xmm +// Construct and append a VCVTPD2PSX.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2PSX_BCST_Z(m, k, x operand.Op) { ctx.VCVTPD2PSX_BCST_Z(m, k, x) } + +// VCVTPD2PSX_Z: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Zeroing Masking). +// +// Forms: +// +// VCVTPD2PSX.Z m128 k xmm +// VCVTPD2PSX.Z xmm k xmm +// Construct and append a VCVTPD2PSX.Z instruction to the active function. +func (c *Context) VCVTPD2PSX_Z(mx, k, x operand.Op) { + c.addinstruction(x86.VCVTPD2PSX_Z(mx, k, x)) +} + +// VCVTPD2PSX_Z: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Zeroing Masking). +// +// Forms: +// +// VCVTPD2PSX.Z m128 k xmm +// VCVTPD2PSX.Z xmm k xmm +// Construct and append a VCVTPD2PSX.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2PSX_Z(mx, k, x operand.Op) { ctx.VCVTPD2PSX_Z(mx, k, x) } + +// VCVTPD2PSY: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values. +// +// Forms: +// +// VCVTPD2PSY m256 xmm +// VCVTPD2PSY ymm xmm +// VCVTPD2PSY m256 k xmm +// VCVTPD2PSY ymm k xmm +// Construct and append a VCVTPD2PSY instruction to the active function. +func (c *Context) VCVTPD2PSY(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2PSY(ops...)) +} + +// VCVTPD2PSY: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values. +// +// Forms: +// +// VCVTPD2PSY m256 xmm +// VCVTPD2PSY ymm xmm +// VCVTPD2PSY m256 k xmm +// VCVTPD2PSY ymm k xmm +// Construct and append a VCVTPD2PSY instruction to the active function. +// Operates on the global context. +func VCVTPD2PSY(ops ...operand.Op) { ctx.VCVTPD2PSY(ops...) } + +// VCVTPD2PSY_BCST: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Broadcast). +// +// Forms: +// +// VCVTPD2PSY.BCST m64 k xmm +// VCVTPD2PSY.BCST m64 xmm +// Construct and append a VCVTPD2PSY.BCST instruction to the active function. +func (c *Context) VCVTPD2PSY_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2PSY_BCST(ops...)) +} + +// VCVTPD2PSY_BCST: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Broadcast). +// +// Forms: +// +// VCVTPD2PSY.BCST m64 k xmm +// VCVTPD2PSY.BCST m64 xmm +// Construct and append a VCVTPD2PSY.BCST instruction to the active function. +// Operates on the global context. +func VCVTPD2PSY_BCST(ops ...operand.Op) { ctx.VCVTPD2PSY_BCST(ops...) } + +// VCVTPD2PSY_BCST_Z: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2PSY.BCST.Z m64 k xmm +// Construct and append a VCVTPD2PSY.BCST.Z instruction to the active function. +func (c *Context) VCVTPD2PSY_BCST_Z(m, k, x operand.Op) { + c.addinstruction(x86.VCVTPD2PSY_BCST_Z(m, k, x)) +} + +// VCVTPD2PSY_BCST_Z: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2PSY.BCST.Z m64 k xmm +// Construct and append a VCVTPD2PSY.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2PSY_BCST_Z(m, k, x operand.Op) { ctx.VCVTPD2PSY_BCST_Z(m, k, x) } + +// VCVTPD2PSY_Z: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Zeroing Masking). +// +// Forms: +// +// VCVTPD2PSY.Z m256 k xmm +// VCVTPD2PSY.Z ymm k xmm +// Construct and append a VCVTPD2PSY.Z instruction to the active function. +func (c *Context) VCVTPD2PSY_Z(my, k, x operand.Op) { + c.addinstruction(x86.VCVTPD2PSY_Z(my, k, x)) +} + +// VCVTPD2PSY_Z: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Zeroing Masking). +// +// Forms: +// +// VCVTPD2PSY.Z m256 k xmm +// VCVTPD2PSY.Z ymm k xmm +// Construct and append a VCVTPD2PSY.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2PSY_Z(my, k, x operand.Op) { ctx.VCVTPD2PSY_Z(my, k, x) } + +// VCVTPD2PS_BCST: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Broadcast). +// +// Forms: +// +// VCVTPD2PS.BCST m64 k ymm +// VCVTPD2PS.BCST m64 ymm +// Construct and append a VCVTPD2PS.BCST instruction to the active function. +func (c *Context) VCVTPD2PS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2PS_BCST(ops...)) +} + +// VCVTPD2PS_BCST: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Broadcast). +// +// Forms: +// +// VCVTPD2PS.BCST m64 k ymm +// VCVTPD2PS.BCST m64 ymm +// Construct and append a VCVTPD2PS.BCST instruction to the active function. +// Operates on the global context. +func VCVTPD2PS_BCST(ops ...operand.Op) { ctx.VCVTPD2PS_BCST(ops...) } + +// VCVTPD2PS_BCST_Z: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2PS.BCST.Z m64 k ymm +// Construct and append a VCVTPD2PS.BCST.Z instruction to the active function. +func (c *Context) VCVTPD2PS_BCST_Z(m, k, y operand.Op) { + c.addinstruction(x86.VCVTPD2PS_BCST_Z(m, k, y)) +} + +// VCVTPD2PS_BCST_Z: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2PS.BCST.Z m64 k ymm +// Construct and append a VCVTPD2PS.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2PS_BCST_Z(m, k, y operand.Op) { ctx.VCVTPD2PS_BCST_Z(m, k, y) } + +// VCVTPD2PS_RD_SAE: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTPD2PS.RD_SAE zmm k ymm +// VCVTPD2PS.RD_SAE zmm ymm +// Construct and append a VCVTPD2PS.RD_SAE instruction to the active function. +func (c *Context) VCVTPD2PS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2PS_RD_SAE(ops...)) +} + +// VCVTPD2PS_RD_SAE: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTPD2PS.RD_SAE zmm k ymm +// VCVTPD2PS.RD_SAE zmm ymm +// Construct and append a VCVTPD2PS.RD_SAE instruction to the active function. +// Operates on the global context. +func VCVTPD2PS_RD_SAE(ops ...operand.Op) { ctx.VCVTPD2PS_RD_SAE(ops...) } + +// VCVTPD2PS_RD_SAE_Z: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPD2PS.RD_SAE.Z zmm k ymm +// Construct and append a VCVTPD2PS.RD_SAE.Z instruction to the active function. +func (c *Context) VCVTPD2PS_RD_SAE_Z(z, k, y operand.Op) { + c.addinstruction(x86.VCVTPD2PS_RD_SAE_Z(z, k, y)) +} + +// VCVTPD2PS_RD_SAE_Z: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPD2PS.RD_SAE.Z zmm k ymm +// Construct and append a VCVTPD2PS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2PS_RD_SAE_Z(z, k, y operand.Op) { ctx.VCVTPD2PS_RD_SAE_Z(z, k, y) } + +// VCVTPD2PS_RN_SAE: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Round Towards Nearest). +// +// Forms: +// +// VCVTPD2PS.RN_SAE zmm k ymm +// VCVTPD2PS.RN_SAE zmm ymm +// Construct and append a VCVTPD2PS.RN_SAE instruction to the active function. +func (c *Context) VCVTPD2PS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2PS_RN_SAE(ops...)) +} + +// VCVTPD2PS_RN_SAE: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Round Towards Nearest). +// +// Forms: +// +// VCVTPD2PS.RN_SAE zmm k ymm +// VCVTPD2PS.RN_SAE zmm ymm +// Construct and append a VCVTPD2PS.RN_SAE instruction to the active function. +// Operates on the global context. +func VCVTPD2PS_RN_SAE(ops ...operand.Op) { ctx.VCVTPD2PS_RN_SAE(ops...) } + +// VCVTPD2PS_RN_SAE_Z: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTPD2PS.RN_SAE.Z zmm k ymm +// Construct and append a VCVTPD2PS.RN_SAE.Z instruction to the active function. +func (c *Context) VCVTPD2PS_RN_SAE_Z(z, k, y operand.Op) { + c.addinstruction(x86.VCVTPD2PS_RN_SAE_Z(z, k, y)) +} + +// VCVTPD2PS_RN_SAE_Z: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTPD2PS.RN_SAE.Z zmm k ymm +// Construct and append a VCVTPD2PS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2PS_RN_SAE_Z(z, k, y operand.Op) { ctx.VCVTPD2PS_RN_SAE_Z(z, k, y) } + +// VCVTPD2PS_RU_SAE: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTPD2PS.RU_SAE zmm k ymm +// VCVTPD2PS.RU_SAE zmm ymm +// Construct and append a VCVTPD2PS.RU_SAE instruction to the active function. +func (c *Context) VCVTPD2PS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2PS_RU_SAE(ops...)) +} + +// VCVTPD2PS_RU_SAE: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTPD2PS.RU_SAE zmm k ymm +// VCVTPD2PS.RU_SAE zmm ymm +// Construct and append a VCVTPD2PS.RU_SAE instruction to the active function. +// Operates on the global context. +func VCVTPD2PS_RU_SAE(ops ...operand.Op) { ctx.VCVTPD2PS_RU_SAE(ops...) } + +// VCVTPD2PS_RU_SAE_Z: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPD2PS.RU_SAE.Z zmm k ymm +// Construct and append a VCVTPD2PS.RU_SAE.Z instruction to the active function. +func (c *Context) VCVTPD2PS_RU_SAE_Z(z, k, y operand.Op) { + c.addinstruction(x86.VCVTPD2PS_RU_SAE_Z(z, k, y)) +} + +// VCVTPD2PS_RU_SAE_Z: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPD2PS.RU_SAE.Z zmm k ymm +// Construct and append a VCVTPD2PS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2PS_RU_SAE_Z(z, k, y operand.Op) { ctx.VCVTPD2PS_RU_SAE_Z(z, k, y) } + +// VCVTPD2PS_RZ_SAE: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Round Towards Zero). +// +// Forms: +// +// VCVTPD2PS.RZ_SAE zmm k ymm +// VCVTPD2PS.RZ_SAE zmm ymm +// Construct and append a VCVTPD2PS.RZ_SAE instruction to the active function. +func (c *Context) VCVTPD2PS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2PS_RZ_SAE(ops...)) +} + +// VCVTPD2PS_RZ_SAE: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Round Towards Zero). +// +// Forms: +// +// VCVTPD2PS.RZ_SAE zmm k ymm +// VCVTPD2PS.RZ_SAE zmm ymm +// Construct and append a VCVTPD2PS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VCVTPD2PS_RZ_SAE(ops ...operand.Op) { ctx.VCVTPD2PS_RZ_SAE(ops...) } + +// VCVTPD2PS_RZ_SAE_Z: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTPD2PS.RZ_SAE.Z zmm k ymm +// Construct and append a VCVTPD2PS.RZ_SAE.Z instruction to the active function. +func (c *Context) VCVTPD2PS_RZ_SAE_Z(z, k, y operand.Op) { + c.addinstruction(x86.VCVTPD2PS_RZ_SAE_Z(z, k, y)) +} + +// VCVTPD2PS_RZ_SAE_Z: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTPD2PS.RZ_SAE.Z zmm k ymm +// Construct and append a VCVTPD2PS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2PS_RZ_SAE_Z(z, k, y operand.Op) { ctx.VCVTPD2PS_RZ_SAE_Z(z, k, y) } + +// VCVTPD2PS_Z: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Zeroing Masking). +// +// Forms: +// +// VCVTPD2PS.Z m512 k ymm +// VCVTPD2PS.Z zmm k ymm +// Construct and append a VCVTPD2PS.Z instruction to the active function. +func (c *Context) VCVTPD2PS_Z(mz, k, y operand.Op) { + c.addinstruction(x86.VCVTPD2PS_Z(mz, k, y)) +} + +// VCVTPD2PS_Z: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Zeroing Masking). +// +// Forms: +// +// VCVTPD2PS.Z m512 k ymm +// VCVTPD2PS.Z zmm k ymm +// Construct and append a VCVTPD2PS.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2PS_Z(mz, k, y operand.Op) { ctx.VCVTPD2PS_Z(mz, k, y) } + +// VCVTPD2QQ: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers. +// +// Forms: +// +// VCVTPD2QQ m128 k xmm +// VCVTPD2QQ m128 xmm +// VCVTPD2QQ m256 k ymm +// VCVTPD2QQ m256 ymm +// VCVTPD2QQ xmm k xmm +// VCVTPD2QQ xmm xmm +// VCVTPD2QQ ymm k ymm +// VCVTPD2QQ ymm ymm +// VCVTPD2QQ m512 k zmm +// VCVTPD2QQ m512 zmm +// VCVTPD2QQ zmm k zmm +// VCVTPD2QQ zmm zmm +// Construct and append a VCVTPD2QQ instruction to the active function. +func (c *Context) VCVTPD2QQ(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2QQ(ops...)) +} + +// VCVTPD2QQ: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers. +// +// Forms: +// +// VCVTPD2QQ m128 k xmm +// VCVTPD2QQ m128 xmm +// VCVTPD2QQ m256 k ymm +// VCVTPD2QQ m256 ymm +// VCVTPD2QQ xmm k xmm +// VCVTPD2QQ xmm xmm +// VCVTPD2QQ ymm k ymm +// VCVTPD2QQ ymm ymm +// VCVTPD2QQ m512 k zmm +// VCVTPD2QQ m512 zmm +// VCVTPD2QQ zmm k zmm +// VCVTPD2QQ zmm zmm +// Construct and append a VCVTPD2QQ instruction to the active function. +// Operates on the global context. +func VCVTPD2QQ(ops ...operand.Op) { ctx.VCVTPD2QQ(ops...) } + +// VCVTPD2QQ_BCST: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Broadcast). +// +// Forms: +// +// VCVTPD2QQ.BCST m64 k xmm +// VCVTPD2QQ.BCST m64 k ymm +// VCVTPD2QQ.BCST m64 xmm +// VCVTPD2QQ.BCST m64 ymm +// VCVTPD2QQ.BCST m64 k zmm +// VCVTPD2QQ.BCST m64 zmm +// Construct and append a VCVTPD2QQ.BCST instruction to the active function. +func (c *Context) VCVTPD2QQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2QQ_BCST(ops...)) +} + +// VCVTPD2QQ_BCST: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Broadcast). +// +// Forms: +// +// VCVTPD2QQ.BCST m64 k xmm +// VCVTPD2QQ.BCST m64 k ymm +// VCVTPD2QQ.BCST m64 xmm +// VCVTPD2QQ.BCST m64 ymm +// VCVTPD2QQ.BCST m64 k zmm +// VCVTPD2QQ.BCST m64 zmm +// Construct and append a VCVTPD2QQ.BCST instruction to the active function. +// Operates on the global context. +func VCVTPD2QQ_BCST(ops ...operand.Op) { ctx.VCVTPD2QQ_BCST(ops...) } + +// VCVTPD2QQ_BCST_Z: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2QQ.BCST.Z m64 k xmm +// VCVTPD2QQ.BCST.Z m64 k ymm +// VCVTPD2QQ.BCST.Z m64 k zmm +// Construct and append a VCVTPD2QQ.BCST.Z instruction to the active function. +func (c *Context) VCVTPD2QQ_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VCVTPD2QQ_BCST_Z(m, k, xyz)) +} + +// VCVTPD2QQ_BCST_Z: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2QQ.BCST.Z m64 k xmm +// VCVTPD2QQ.BCST.Z m64 k ymm +// VCVTPD2QQ.BCST.Z m64 k zmm +// Construct and append a VCVTPD2QQ.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2QQ_BCST_Z(m, k, xyz operand.Op) { ctx.VCVTPD2QQ_BCST_Z(m, k, xyz) } + +// VCVTPD2QQ_RD_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTPD2QQ.RD_SAE zmm k zmm +// VCVTPD2QQ.RD_SAE zmm zmm +// Construct and append a VCVTPD2QQ.RD_SAE instruction to the active function. +func (c *Context) VCVTPD2QQ_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2QQ_RD_SAE(ops...)) +} + +// VCVTPD2QQ_RD_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTPD2QQ.RD_SAE zmm k zmm +// VCVTPD2QQ.RD_SAE zmm zmm +// Construct and append a VCVTPD2QQ.RD_SAE instruction to the active function. +// Operates on the global context. +func VCVTPD2QQ_RD_SAE(ops ...operand.Op) { ctx.VCVTPD2QQ_RD_SAE(ops...) } + +// VCVTPD2QQ_RD_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPD2QQ.RD_SAE.Z zmm k zmm +// Construct and append a VCVTPD2QQ.RD_SAE.Z instruction to the active function. +func (c *Context) VCVTPD2QQ_RD_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTPD2QQ_RD_SAE_Z(z, k, z1)) +} + +// VCVTPD2QQ_RD_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPD2QQ.RD_SAE.Z zmm k zmm +// Construct and append a VCVTPD2QQ.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2QQ_RD_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTPD2QQ_RD_SAE_Z(z, k, z1) } + +// VCVTPD2QQ_RN_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Round Towards Nearest). +// +// Forms: +// +// VCVTPD2QQ.RN_SAE zmm k zmm +// VCVTPD2QQ.RN_SAE zmm zmm +// Construct and append a VCVTPD2QQ.RN_SAE instruction to the active function. +func (c *Context) VCVTPD2QQ_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2QQ_RN_SAE(ops...)) +} + +// VCVTPD2QQ_RN_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Round Towards Nearest). +// +// Forms: +// +// VCVTPD2QQ.RN_SAE zmm k zmm +// VCVTPD2QQ.RN_SAE zmm zmm +// Construct and append a VCVTPD2QQ.RN_SAE instruction to the active function. +// Operates on the global context. +func VCVTPD2QQ_RN_SAE(ops ...operand.Op) { ctx.VCVTPD2QQ_RN_SAE(ops...) } + +// VCVTPD2QQ_RN_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTPD2QQ.RN_SAE.Z zmm k zmm +// Construct and append a VCVTPD2QQ.RN_SAE.Z instruction to the active function. +func (c *Context) VCVTPD2QQ_RN_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTPD2QQ_RN_SAE_Z(z, k, z1)) +} + +// VCVTPD2QQ_RN_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTPD2QQ.RN_SAE.Z zmm k zmm +// Construct and append a VCVTPD2QQ.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2QQ_RN_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTPD2QQ_RN_SAE_Z(z, k, z1) } + +// VCVTPD2QQ_RU_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTPD2QQ.RU_SAE zmm k zmm +// VCVTPD2QQ.RU_SAE zmm zmm +// Construct and append a VCVTPD2QQ.RU_SAE instruction to the active function. +func (c *Context) VCVTPD2QQ_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2QQ_RU_SAE(ops...)) +} + +// VCVTPD2QQ_RU_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTPD2QQ.RU_SAE zmm k zmm +// VCVTPD2QQ.RU_SAE zmm zmm +// Construct and append a VCVTPD2QQ.RU_SAE instruction to the active function. +// Operates on the global context. +func VCVTPD2QQ_RU_SAE(ops ...operand.Op) { ctx.VCVTPD2QQ_RU_SAE(ops...) } + +// VCVTPD2QQ_RU_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPD2QQ.RU_SAE.Z zmm k zmm +// Construct and append a VCVTPD2QQ.RU_SAE.Z instruction to the active function. +func (c *Context) VCVTPD2QQ_RU_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTPD2QQ_RU_SAE_Z(z, k, z1)) +} + +// VCVTPD2QQ_RU_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPD2QQ.RU_SAE.Z zmm k zmm +// Construct and append a VCVTPD2QQ.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2QQ_RU_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTPD2QQ_RU_SAE_Z(z, k, z1) } + +// VCVTPD2QQ_RZ_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Round Towards Zero). +// +// Forms: +// +// VCVTPD2QQ.RZ_SAE zmm k zmm +// VCVTPD2QQ.RZ_SAE zmm zmm +// Construct and append a VCVTPD2QQ.RZ_SAE instruction to the active function. +func (c *Context) VCVTPD2QQ_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2QQ_RZ_SAE(ops...)) +} + +// VCVTPD2QQ_RZ_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Round Towards Zero). +// +// Forms: +// +// VCVTPD2QQ.RZ_SAE zmm k zmm +// VCVTPD2QQ.RZ_SAE zmm zmm +// Construct and append a VCVTPD2QQ.RZ_SAE instruction to the active function. +// Operates on the global context. +func VCVTPD2QQ_RZ_SAE(ops ...operand.Op) { ctx.VCVTPD2QQ_RZ_SAE(ops...) } + +// VCVTPD2QQ_RZ_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTPD2QQ.RZ_SAE.Z zmm k zmm +// Construct and append a VCVTPD2QQ.RZ_SAE.Z instruction to the active function. +func (c *Context) VCVTPD2QQ_RZ_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTPD2QQ_RZ_SAE_Z(z, k, z1)) +} + +// VCVTPD2QQ_RZ_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTPD2QQ.RZ_SAE.Z zmm k zmm +// Construct and append a VCVTPD2QQ.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2QQ_RZ_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTPD2QQ_RZ_SAE_Z(z, k, z1) } + +// VCVTPD2QQ_Z: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTPD2QQ.Z m128 k xmm +// VCVTPD2QQ.Z m256 k ymm +// VCVTPD2QQ.Z xmm k xmm +// VCVTPD2QQ.Z ymm k ymm +// VCVTPD2QQ.Z m512 k zmm +// VCVTPD2QQ.Z zmm k zmm +// Construct and append a VCVTPD2QQ.Z instruction to the active function. +func (c *Context) VCVTPD2QQ_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VCVTPD2QQ_Z(mxyz, k, xyz)) +} + +// VCVTPD2QQ_Z: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTPD2QQ.Z m128 k xmm +// VCVTPD2QQ.Z m256 k ymm +// VCVTPD2QQ.Z xmm k xmm +// VCVTPD2QQ.Z ymm k ymm +// VCVTPD2QQ.Z m512 k zmm +// VCVTPD2QQ.Z zmm k zmm +// Construct and append a VCVTPD2QQ.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2QQ_Z(mxyz, k, xyz operand.Op) { ctx.VCVTPD2QQ_Z(mxyz, k, xyz) } + +// VCVTPD2UDQ: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers. +// +// Forms: +// +// VCVTPD2UDQ m512 k ymm +// VCVTPD2UDQ m512 ymm +// VCVTPD2UDQ zmm k ymm +// VCVTPD2UDQ zmm ymm +// Construct and append a VCVTPD2UDQ instruction to the active function. +func (c *Context) VCVTPD2UDQ(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2UDQ(ops...)) +} + +// VCVTPD2UDQ: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers. +// +// Forms: +// +// VCVTPD2UDQ m512 k ymm +// VCVTPD2UDQ m512 ymm +// VCVTPD2UDQ zmm k ymm +// VCVTPD2UDQ zmm ymm +// Construct and append a VCVTPD2UDQ instruction to the active function. +// Operates on the global context. +func VCVTPD2UDQ(ops ...operand.Op) { ctx.VCVTPD2UDQ(ops...) } + +// VCVTPD2UDQX: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers. +// +// Forms: +// +// VCVTPD2UDQX m128 k xmm +// VCVTPD2UDQX m128 xmm +// VCVTPD2UDQX xmm k xmm +// VCVTPD2UDQX xmm xmm +// Construct and append a VCVTPD2UDQX instruction to the active function. +func (c *Context) VCVTPD2UDQX(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2UDQX(ops...)) +} + +// VCVTPD2UDQX: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers. +// +// Forms: +// +// VCVTPD2UDQX m128 k xmm +// VCVTPD2UDQX m128 xmm +// VCVTPD2UDQX xmm k xmm +// VCVTPD2UDQX xmm xmm +// Construct and append a VCVTPD2UDQX instruction to the active function. +// Operates on the global context. +func VCVTPD2UDQX(ops ...operand.Op) { ctx.VCVTPD2UDQX(ops...) } + +// VCVTPD2UDQX_BCST: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast). +// +// Forms: +// +// VCVTPD2UDQX.BCST m64 k xmm +// VCVTPD2UDQX.BCST m64 xmm +// Construct and append a VCVTPD2UDQX.BCST instruction to the active function. +func (c *Context) VCVTPD2UDQX_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2UDQX_BCST(ops...)) +} + +// VCVTPD2UDQX_BCST: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast). +// +// Forms: +// +// VCVTPD2UDQX.BCST m64 k xmm +// VCVTPD2UDQX.BCST m64 xmm +// Construct and append a VCVTPD2UDQX.BCST instruction to the active function. +// Operates on the global context. +func VCVTPD2UDQX_BCST(ops ...operand.Op) { ctx.VCVTPD2UDQX_BCST(ops...) } + +// VCVTPD2UDQX_BCST_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UDQX.BCST.Z m64 k xmm +// Construct and append a VCVTPD2UDQX.BCST.Z instruction to the active function. +func (c *Context) VCVTPD2UDQX_BCST_Z(m, k, x operand.Op) { + c.addinstruction(x86.VCVTPD2UDQX_BCST_Z(m, k, x)) +} + +// VCVTPD2UDQX_BCST_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UDQX.BCST.Z m64 k xmm +// Construct and append a VCVTPD2UDQX.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2UDQX_BCST_Z(m, k, x operand.Op) { ctx.VCVTPD2UDQX_BCST_Z(m, k, x) } + +// VCVTPD2UDQX_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTPD2UDQX.Z m128 k xmm +// VCVTPD2UDQX.Z xmm k xmm +// Construct and append a VCVTPD2UDQX.Z instruction to the active function. +func (c *Context) VCVTPD2UDQX_Z(mx, k, x operand.Op) { + c.addinstruction(x86.VCVTPD2UDQX_Z(mx, k, x)) +} + +// VCVTPD2UDQX_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTPD2UDQX.Z m128 k xmm +// VCVTPD2UDQX.Z xmm k xmm +// Construct and append a VCVTPD2UDQX.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2UDQX_Z(mx, k, x operand.Op) { ctx.VCVTPD2UDQX_Z(mx, k, x) } + +// VCVTPD2UDQY: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers. +// +// Forms: +// +// VCVTPD2UDQY m256 k xmm +// VCVTPD2UDQY m256 xmm +// VCVTPD2UDQY ymm k xmm +// VCVTPD2UDQY ymm xmm +// Construct and append a VCVTPD2UDQY instruction to the active function. +func (c *Context) VCVTPD2UDQY(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2UDQY(ops...)) +} + +// VCVTPD2UDQY: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers. +// +// Forms: +// +// VCVTPD2UDQY m256 k xmm +// VCVTPD2UDQY m256 xmm +// VCVTPD2UDQY ymm k xmm +// VCVTPD2UDQY ymm xmm +// Construct and append a VCVTPD2UDQY instruction to the active function. +// Operates on the global context. +func VCVTPD2UDQY(ops ...operand.Op) { ctx.VCVTPD2UDQY(ops...) } + +// VCVTPD2UDQY_BCST: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast). +// +// Forms: +// +// VCVTPD2UDQY.BCST m64 k xmm +// VCVTPD2UDQY.BCST m64 xmm +// Construct and append a VCVTPD2UDQY.BCST instruction to the active function. +func (c *Context) VCVTPD2UDQY_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2UDQY_BCST(ops...)) +} + +// VCVTPD2UDQY_BCST: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast). +// +// Forms: +// +// VCVTPD2UDQY.BCST m64 k xmm +// VCVTPD2UDQY.BCST m64 xmm +// Construct and append a VCVTPD2UDQY.BCST instruction to the active function. +// Operates on the global context. +func VCVTPD2UDQY_BCST(ops ...operand.Op) { ctx.VCVTPD2UDQY_BCST(ops...) } + +// VCVTPD2UDQY_BCST_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UDQY.BCST.Z m64 k xmm +// Construct and append a VCVTPD2UDQY.BCST.Z instruction to the active function. +func (c *Context) VCVTPD2UDQY_BCST_Z(m, k, x operand.Op) { + c.addinstruction(x86.VCVTPD2UDQY_BCST_Z(m, k, x)) +} + +// VCVTPD2UDQY_BCST_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UDQY.BCST.Z m64 k xmm +// Construct and append a VCVTPD2UDQY.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2UDQY_BCST_Z(m, k, x operand.Op) { ctx.VCVTPD2UDQY_BCST_Z(m, k, x) } + +// VCVTPD2UDQY_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTPD2UDQY.Z m256 k xmm +// VCVTPD2UDQY.Z ymm k xmm +// Construct and append a VCVTPD2UDQY.Z instruction to the active function. +func (c *Context) VCVTPD2UDQY_Z(my, k, x operand.Op) { + c.addinstruction(x86.VCVTPD2UDQY_Z(my, k, x)) +} + +// VCVTPD2UDQY_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTPD2UDQY.Z m256 k xmm +// VCVTPD2UDQY.Z ymm k xmm +// Construct and append a VCVTPD2UDQY.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2UDQY_Z(my, k, x operand.Op) { ctx.VCVTPD2UDQY_Z(my, k, x) } + +// VCVTPD2UDQ_BCST: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast). +// +// Forms: +// +// VCVTPD2UDQ.BCST m64 k ymm +// VCVTPD2UDQ.BCST m64 ymm +// Construct and append a VCVTPD2UDQ.BCST instruction to the active function. +func (c *Context) VCVTPD2UDQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2UDQ_BCST(ops...)) +} + +// VCVTPD2UDQ_BCST: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast). +// +// Forms: +// +// VCVTPD2UDQ.BCST m64 k ymm +// VCVTPD2UDQ.BCST m64 ymm +// Construct and append a VCVTPD2UDQ.BCST instruction to the active function. +// Operates on the global context. +func VCVTPD2UDQ_BCST(ops ...operand.Op) { ctx.VCVTPD2UDQ_BCST(ops...) } + +// VCVTPD2UDQ_BCST_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UDQ.BCST.Z m64 k ymm +// Construct and append a VCVTPD2UDQ.BCST.Z instruction to the active function. +func (c *Context) VCVTPD2UDQ_BCST_Z(m, k, y operand.Op) { + c.addinstruction(x86.VCVTPD2UDQ_BCST_Z(m, k, y)) +} + +// VCVTPD2UDQ_BCST_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UDQ.BCST.Z m64 k ymm +// Construct and append a VCVTPD2UDQ.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2UDQ_BCST_Z(m, k, y operand.Op) { ctx.VCVTPD2UDQ_BCST_Z(m, k, y) } + +// VCVTPD2UDQ_RD_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTPD2UDQ.RD_SAE zmm k ymm +// VCVTPD2UDQ.RD_SAE zmm ymm +// Construct and append a VCVTPD2UDQ.RD_SAE instruction to the active function. +func (c *Context) VCVTPD2UDQ_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2UDQ_RD_SAE(ops...)) +} + +// VCVTPD2UDQ_RD_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTPD2UDQ.RD_SAE zmm k ymm +// VCVTPD2UDQ.RD_SAE zmm ymm +// Construct and append a VCVTPD2UDQ.RD_SAE instruction to the active function. +// Operates on the global context. +func VCVTPD2UDQ_RD_SAE(ops ...operand.Op) { ctx.VCVTPD2UDQ_RD_SAE(ops...) } + +// VCVTPD2UDQ_RD_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UDQ.RD_SAE.Z zmm k ymm +// Construct and append a VCVTPD2UDQ.RD_SAE.Z instruction to the active function. +func (c *Context) VCVTPD2UDQ_RD_SAE_Z(z, k, y operand.Op) { + c.addinstruction(x86.VCVTPD2UDQ_RD_SAE_Z(z, k, y)) +} + +// VCVTPD2UDQ_RD_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UDQ.RD_SAE.Z zmm k ymm +// Construct and append a VCVTPD2UDQ.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2UDQ_RD_SAE_Z(z, k, y operand.Op) { ctx.VCVTPD2UDQ_RD_SAE_Z(z, k, y) } + +// VCVTPD2UDQ_RN_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Round Towards Nearest). +// +// Forms: +// +// VCVTPD2UDQ.RN_SAE zmm k ymm +// VCVTPD2UDQ.RN_SAE zmm ymm +// Construct and append a VCVTPD2UDQ.RN_SAE instruction to the active function. +func (c *Context) VCVTPD2UDQ_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2UDQ_RN_SAE(ops...)) +} + +// VCVTPD2UDQ_RN_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Round Towards Nearest). +// +// Forms: +// +// VCVTPD2UDQ.RN_SAE zmm k ymm +// VCVTPD2UDQ.RN_SAE zmm ymm +// Construct and append a VCVTPD2UDQ.RN_SAE instruction to the active function. +// Operates on the global context. +func VCVTPD2UDQ_RN_SAE(ops ...operand.Op) { ctx.VCVTPD2UDQ_RN_SAE(ops...) } + +// VCVTPD2UDQ_RN_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UDQ.RN_SAE.Z zmm k ymm +// Construct and append a VCVTPD2UDQ.RN_SAE.Z instruction to the active function. +func (c *Context) VCVTPD2UDQ_RN_SAE_Z(z, k, y operand.Op) { + c.addinstruction(x86.VCVTPD2UDQ_RN_SAE_Z(z, k, y)) +} + +// VCVTPD2UDQ_RN_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UDQ.RN_SAE.Z zmm k ymm +// Construct and append a VCVTPD2UDQ.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2UDQ_RN_SAE_Z(z, k, y operand.Op) { ctx.VCVTPD2UDQ_RN_SAE_Z(z, k, y) } + +// VCVTPD2UDQ_RU_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTPD2UDQ.RU_SAE zmm k ymm +// VCVTPD2UDQ.RU_SAE zmm ymm +// Construct and append a VCVTPD2UDQ.RU_SAE instruction to the active function. +func (c *Context) VCVTPD2UDQ_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2UDQ_RU_SAE(ops...)) +} + +// VCVTPD2UDQ_RU_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTPD2UDQ.RU_SAE zmm k ymm +// VCVTPD2UDQ.RU_SAE zmm ymm +// Construct and append a VCVTPD2UDQ.RU_SAE instruction to the active function. +// Operates on the global context. +func VCVTPD2UDQ_RU_SAE(ops ...operand.Op) { ctx.VCVTPD2UDQ_RU_SAE(ops...) } + +// VCVTPD2UDQ_RU_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UDQ.RU_SAE.Z zmm k ymm +// Construct and append a VCVTPD2UDQ.RU_SAE.Z instruction to the active function. +func (c *Context) VCVTPD2UDQ_RU_SAE_Z(z, k, y operand.Op) { + c.addinstruction(x86.VCVTPD2UDQ_RU_SAE_Z(z, k, y)) +} + +// VCVTPD2UDQ_RU_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UDQ.RU_SAE.Z zmm k ymm +// Construct and append a VCVTPD2UDQ.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2UDQ_RU_SAE_Z(z, k, y operand.Op) { ctx.VCVTPD2UDQ_RU_SAE_Z(z, k, y) } + +// VCVTPD2UDQ_RZ_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Round Towards Zero). +// +// Forms: +// +// VCVTPD2UDQ.RZ_SAE zmm k ymm +// VCVTPD2UDQ.RZ_SAE zmm ymm +// Construct and append a VCVTPD2UDQ.RZ_SAE instruction to the active function. +func (c *Context) VCVTPD2UDQ_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2UDQ_RZ_SAE(ops...)) +} + +// VCVTPD2UDQ_RZ_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Round Towards Zero). +// +// Forms: +// +// VCVTPD2UDQ.RZ_SAE zmm k ymm +// VCVTPD2UDQ.RZ_SAE zmm ymm +// Construct and append a VCVTPD2UDQ.RZ_SAE instruction to the active function. +// Operates on the global context. +func VCVTPD2UDQ_RZ_SAE(ops ...operand.Op) { ctx.VCVTPD2UDQ_RZ_SAE(ops...) } + +// VCVTPD2UDQ_RZ_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UDQ.RZ_SAE.Z zmm k ymm +// Construct and append a VCVTPD2UDQ.RZ_SAE.Z instruction to the active function. +func (c *Context) VCVTPD2UDQ_RZ_SAE_Z(z, k, y operand.Op) { + c.addinstruction(x86.VCVTPD2UDQ_RZ_SAE_Z(z, k, y)) +} + +// VCVTPD2UDQ_RZ_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UDQ.RZ_SAE.Z zmm k ymm +// Construct and append a VCVTPD2UDQ.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2UDQ_RZ_SAE_Z(z, k, y operand.Op) { ctx.VCVTPD2UDQ_RZ_SAE_Z(z, k, y) } + +// VCVTPD2UDQ_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTPD2UDQ.Z m512 k ymm +// VCVTPD2UDQ.Z zmm k ymm +// Construct and append a VCVTPD2UDQ.Z instruction to the active function. +func (c *Context) VCVTPD2UDQ_Z(mz, k, y operand.Op) { + c.addinstruction(x86.VCVTPD2UDQ_Z(mz, k, y)) +} + +// VCVTPD2UDQ_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTPD2UDQ.Z m512 k ymm +// VCVTPD2UDQ.Z zmm k ymm +// Construct and append a VCVTPD2UDQ.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2UDQ_Z(mz, k, y operand.Op) { ctx.VCVTPD2UDQ_Z(mz, k, y) } + +// VCVTPD2UQQ: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers. +// +// Forms: +// +// VCVTPD2UQQ m128 k xmm +// VCVTPD2UQQ m128 xmm +// VCVTPD2UQQ m256 k ymm +// VCVTPD2UQQ m256 ymm +// VCVTPD2UQQ xmm k xmm +// VCVTPD2UQQ xmm xmm +// VCVTPD2UQQ ymm k ymm +// VCVTPD2UQQ ymm ymm +// VCVTPD2UQQ m512 k zmm +// VCVTPD2UQQ m512 zmm +// VCVTPD2UQQ zmm k zmm +// VCVTPD2UQQ zmm zmm +// Construct and append a VCVTPD2UQQ instruction to the active function. +func (c *Context) VCVTPD2UQQ(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2UQQ(ops...)) +} + +// VCVTPD2UQQ: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers. +// +// Forms: +// +// VCVTPD2UQQ m128 k xmm +// VCVTPD2UQQ m128 xmm +// VCVTPD2UQQ m256 k ymm +// VCVTPD2UQQ m256 ymm +// VCVTPD2UQQ xmm k xmm +// VCVTPD2UQQ xmm xmm +// VCVTPD2UQQ ymm k ymm +// VCVTPD2UQQ ymm ymm +// VCVTPD2UQQ m512 k zmm +// VCVTPD2UQQ m512 zmm +// VCVTPD2UQQ zmm k zmm +// VCVTPD2UQQ zmm zmm +// Construct and append a VCVTPD2UQQ instruction to the active function. +// Operates on the global context. +func VCVTPD2UQQ(ops ...operand.Op) { ctx.VCVTPD2UQQ(ops...) } + +// VCVTPD2UQQ_BCST: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Broadcast). +// +// Forms: +// +// VCVTPD2UQQ.BCST m64 k xmm +// VCVTPD2UQQ.BCST m64 k ymm +// VCVTPD2UQQ.BCST m64 xmm +// VCVTPD2UQQ.BCST m64 ymm +// VCVTPD2UQQ.BCST m64 k zmm +// VCVTPD2UQQ.BCST m64 zmm +// Construct and append a VCVTPD2UQQ.BCST instruction to the active function. +func (c *Context) VCVTPD2UQQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2UQQ_BCST(ops...)) +} + +// VCVTPD2UQQ_BCST: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Broadcast). +// +// Forms: +// +// VCVTPD2UQQ.BCST m64 k xmm +// VCVTPD2UQQ.BCST m64 k ymm +// VCVTPD2UQQ.BCST m64 xmm +// VCVTPD2UQQ.BCST m64 ymm +// VCVTPD2UQQ.BCST m64 k zmm +// VCVTPD2UQQ.BCST m64 zmm +// Construct and append a VCVTPD2UQQ.BCST instruction to the active function. +// Operates on the global context. +func VCVTPD2UQQ_BCST(ops ...operand.Op) { ctx.VCVTPD2UQQ_BCST(ops...) } + +// VCVTPD2UQQ_BCST_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UQQ.BCST.Z m64 k xmm +// VCVTPD2UQQ.BCST.Z m64 k ymm +// VCVTPD2UQQ.BCST.Z m64 k zmm +// Construct and append a VCVTPD2UQQ.BCST.Z instruction to the active function. +func (c *Context) VCVTPD2UQQ_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VCVTPD2UQQ_BCST_Z(m, k, xyz)) +} + +// VCVTPD2UQQ_BCST_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UQQ.BCST.Z m64 k xmm +// VCVTPD2UQQ.BCST.Z m64 k ymm +// VCVTPD2UQQ.BCST.Z m64 k zmm +// Construct and append a VCVTPD2UQQ.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2UQQ_BCST_Z(m, k, xyz operand.Op) { ctx.VCVTPD2UQQ_BCST_Z(m, k, xyz) } + +// VCVTPD2UQQ_RD_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTPD2UQQ.RD_SAE zmm k zmm +// VCVTPD2UQQ.RD_SAE zmm zmm +// Construct and append a VCVTPD2UQQ.RD_SAE instruction to the active function. +func (c *Context) VCVTPD2UQQ_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2UQQ_RD_SAE(ops...)) +} + +// VCVTPD2UQQ_RD_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTPD2UQQ.RD_SAE zmm k zmm +// VCVTPD2UQQ.RD_SAE zmm zmm +// Construct and append a VCVTPD2UQQ.RD_SAE instruction to the active function. +// Operates on the global context. +func VCVTPD2UQQ_RD_SAE(ops ...operand.Op) { ctx.VCVTPD2UQQ_RD_SAE(ops...) } + +// VCVTPD2UQQ_RD_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UQQ.RD_SAE.Z zmm k zmm +// Construct and append a VCVTPD2UQQ.RD_SAE.Z instruction to the active function. +func (c *Context) VCVTPD2UQQ_RD_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTPD2UQQ_RD_SAE_Z(z, k, z1)) +} + +// VCVTPD2UQQ_RD_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UQQ.RD_SAE.Z zmm k zmm +// Construct and append a VCVTPD2UQQ.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2UQQ_RD_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTPD2UQQ_RD_SAE_Z(z, k, z1) } + +// VCVTPD2UQQ_RN_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Round Towards Nearest). +// +// Forms: +// +// VCVTPD2UQQ.RN_SAE zmm k zmm +// VCVTPD2UQQ.RN_SAE zmm zmm +// Construct and append a VCVTPD2UQQ.RN_SAE instruction to the active function. +func (c *Context) VCVTPD2UQQ_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2UQQ_RN_SAE(ops...)) +} + +// VCVTPD2UQQ_RN_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Round Towards Nearest). +// +// Forms: +// +// VCVTPD2UQQ.RN_SAE zmm k zmm +// VCVTPD2UQQ.RN_SAE zmm zmm +// Construct and append a VCVTPD2UQQ.RN_SAE instruction to the active function. +// Operates on the global context. +func VCVTPD2UQQ_RN_SAE(ops ...operand.Op) { ctx.VCVTPD2UQQ_RN_SAE(ops...) } + +// VCVTPD2UQQ_RN_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UQQ.RN_SAE.Z zmm k zmm +// Construct and append a VCVTPD2UQQ.RN_SAE.Z instruction to the active function. +func (c *Context) VCVTPD2UQQ_RN_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTPD2UQQ_RN_SAE_Z(z, k, z1)) +} + +// VCVTPD2UQQ_RN_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UQQ.RN_SAE.Z zmm k zmm +// Construct and append a VCVTPD2UQQ.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2UQQ_RN_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTPD2UQQ_RN_SAE_Z(z, k, z1) } + +// VCVTPD2UQQ_RU_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTPD2UQQ.RU_SAE zmm k zmm +// VCVTPD2UQQ.RU_SAE zmm zmm +// Construct and append a VCVTPD2UQQ.RU_SAE instruction to the active function. +func (c *Context) VCVTPD2UQQ_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2UQQ_RU_SAE(ops...)) +} + +// VCVTPD2UQQ_RU_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTPD2UQQ.RU_SAE zmm k zmm +// VCVTPD2UQQ.RU_SAE zmm zmm +// Construct and append a VCVTPD2UQQ.RU_SAE instruction to the active function. +// Operates on the global context. +func VCVTPD2UQQ_RU_SAE(ops ...operand.Op) { ctx.VCVTPD2UQQ_RU_SAE(ops...) } + +// VCVTPD2UQQ_RU_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UQQ.RU_SAE.Z zmm k zmm +// Construct and append a VCVTPD2UQQ.RU_SAE.Z instruction to the active function. +func (c *Context) VCVTPD2UQQ_RU_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTPD2UQQ_RU_SAE_Z(z, k, z1)) +} + +// VCVTPD2UQQ_RU_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UQQ.RU_SAE.Z zmm k zmm +// Construct and append a VCVTPD2UQQ.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2UQQ_RU_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTPD2UQQ_RU_SAE_Z(z, k, z1) } + +// VCVTPD2UQQ_RZ_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Round Towards Zero). +// +// Forms: +// +// VCVTPD2UQQ.RZ_SAE zmm k zmm +// VCVTPD2UQQ.RZ_SAE zmm zmm +// Construct and append a VCVTPD2UQQ.RZ_SAE instruction to the active function. +func (c *Context) VCVTPD2UQQ_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPD2UQQ_RZ_SAE(ops...)) +} + +// VCVTPD2UQQ_RZ_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Round Towards Zero). +// +// Forms: +// +// VCVTPD2UQQ.RZ_SAE zmm k zmm +// VCVTPD2UQQ.RZ_SAE zmm zmm +// Construct and append a VCVTPD2UQQ.RZ_SAE instruction to the active function. +// Operates on the global context. +func VCVTPD2UQQ_RZ_SAE(ops ...operand.Op) { ctx.VCVTPD2UQQ_RZ_SAE(ops...) } + +// VCVTPD2UQQ_RZ_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UQQ.RZ_SAE.Z zmm k zmm +// Construct and append a VCVTPD2UQQ.RZ_SAE.Z instruction to the active function. +func (c *Context) VCVTPD2UQQ_RZ_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTPD2UQQ_RZ_SAE_Z(z, k, z1)) +} + +// VCVTPD2UQQ_RZ_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UQQ.RZ_SAE.Z zmm k zmm +// Construct and append a VCVTPD2UQQ.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2UQQ_RZ_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTPD2UQQ_RZ_SAE_Z(z, k, z1) } + +// VCVTPD2UQQ_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTPD2UQQ.Z m128 k xmm +// VCVTPD2UQQ.Z m256 k ymm +// VCVTPD2UQQ.Z xmm k xmm +// VCVTPD2UQQ.Z ymm k ymm +// VCVTPD2UQQ.Z m512 k zmm +// VCVTPD2UQQ.Z zmm k zmm +// Construct and append a VCVTPD2UQQ.Z instruction to the active function. +func (c *Context) VCVTPD2UQQ_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VCVTPD2UQQ_Z(mxyz, k, xyz)) +} + +// VCVTPD2UQQ_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTPD2UQQ.Z m128 k xmm +// VCVTPD2UQQ.Z m256 k ymm +// VCVTPD2UQQ.Z xmm k xmm +// VCVTPD2UQQ.Z ymm k ymm +// VCVTPD2UQQ.Z m512 k zmm +// VCVTPD2UQQ.Z zmm k zmm +// Construct and append a VCVTPD2UQQ.Z instruction to the active function. +// Operates on the global context. +func VCVTPD2UQQ_Z(mxyz, k, xyz operand.Op) { ctx.VCVTPD2UQQ_Z(mxyz, k, xyz) } + +// VCVTPH2PS: Convert Half-Precision FP Values to Single-Precision FP Values. +// +// Forms: +// +// VCVTPH2PS m128 ymm +// VCVTPH2PS m64 xmm +// VCVTPH2PS xmm xmm +// VCVTPH2PS xmm ymm +// VCVTPH2PS m128 k ymm +// VCVTPH2PS m64 k xmm +// VCVTPH2PS xmm k xmm +// VCVTPH2PS xmm k ymm +// VCVTPH2PS m256 k zmm +// VCVTPH2PS m256 zmm +// VCVTPH2PS ymm k zmm +// VCVTPH2PS ymm zmm +// Construct and append a VCVTPH2PS instruction to the active function. +func (c *Context) VCVTPH2PS(ops ...operand.Op) { + c.addinstruction(x86.VCVTPH2PS(ops...)) +} + +// VCVTPH2PS: Convert Half-Precision FP Values to Single-Precision FP Values. +// +// Forms: +// +// VCVTPH2PS m128 ymm +// VCVTPH2PS m64 xmm +// VCVTPH2PS xmm xmm +// VCVTPH2PS xmm ymm +// VCVTPH2PS m128 k ymm +// VCVTPH2PS m64 k xmm +// VCVTPH2PS xmm k xmm +// VCVTPH2PS xmm k ymm +// VCVTPH2PS m256 k zmm +// VCVTPH2PS m256 zmm +// VCVTPH2PS ymm k zmm +// VCVTPH2PS ymm zmm +// Construct and append a VCVTPH2PS instruction to the active function. +// Operates on the global context. +func VCVTPH2PS(ops ...operand.Op) { ctx.VCVTPH2PS(ops...) } + +// VCVTPH2PS_SAE: Convert Half-Precision FP Values to Single-Precision FP Values (Suppress All Exceptions). +// +// Forms: +// +// VCVTPH2PS.SAE ymm k zmm +// VCVTPH2PS.SAE ymm zmm +// Construct and append a VCVTPH2PS.SAE instruction to the active function. +func (c *Context) VCVTPH2PS_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPH2PS_SAE(ops...)) +} + +// VCVTPH2PS_SAE: Convert Half-Precision FP Values to Single-Precision FP Values (Suppress All Exceptions). +// +// Forms: +// +// VCVTPH2PS.SAE ymm k zmm +// VCVTPH2PS.SAE ymm zmm +// Construct and append a VCVTPH2PS.SAE instruction to the active function. +// Operates on the global context. +func VCVTPH2PS_SAE(ops ...operand.Op) { ctx.VCVTPH2PS_SAE(ops...) } + +// VCVTPH2PS_SAE_Z: Convert Half-Precision FP Values to Single-Precision FP Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTPH2PS.SAE.Z ymm k zmm +// Construct and append a VCVTPH2PS.SAE.Z instruction to the active function. +func (c *Context) VCVTPH2PS_SAE_Z(y, k, z operand.Op) { + c.addinstruction(x86.VCVTPH2PS_SAE_Z(y, k, z)) +} + +// VCVTPH2PS_SAE_Z: Convert Half-Precision FP Values to Single-Precision FP Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTPH2PS.SAE.Z ymm k zmm +// Construct and append a VCVTPH2PS.SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPH2PS_SAE_Z(y, k, z operand.Op) { ctx.VCVTPH2PS_SAE_Z(y, k, z) } + +// VCVTPH2PS_Z: Convert Half-Precision FP Values to Single-Precision FP Values (Zeroing Masking). +// +// Forms: +// +// VCVTPH2PS.Z m128 k ymm +// VCVTPH2PS.Z m64 k xmm +// VCVTPH2PS.Z xmm k xmm +// VCVTPH2PS.Z xmm k ymm +// VCVTPH2PS.Z m256 k zmm +// VCVTPH2PS.Z ymm k zmm +// Construct and append a VCVTPH2PS.Z instruction to the active function. +func (c *Context) VCVTPH2PS_Z(mxy, k, xyz operand.Op) { + c.addinstruction(x86.VCVTPH2PS_Z(mxy, k, xyz)) +} + +// VCVTPH2PS_Z: Convert Half-Precision FP Values to Single-Precision FP Values (Zeroing Masking). +// +// Forms: +// +// VCVTPH2PS.Z m128 k ymm +// VCVTPH2PS.Z m64 k xmm +// VCVTPH2PS.Z xmm k xmm +// VCVTPH2PS.Z xmm k ymm +// VCVTPH2PS.Z m256 k zmm +// VCVTPH2PS.Z ymm k zmm +// Construct and append a VCVTPH2PS.Z instruction to the active function. +// Operates on the global context. +func VCVTPH2PS_Z(mxy, k, xyz operand.Op) { ctx.VCVTPH2PS_Z(mxy, k, xyz) } + +// VCVTPS2DQ: Convert Packed Single-Precision FP Values to Packed Dword Integers. +// +// Forms: +// +// VCVTPS2DQ m128 xmm +// VCVTPS2DQ m256 ymm +// VCVTPS2DQ xmm xmm +// VCVTPS2DQ ymm ymm +// VCVTPS2DQ m128 k xmm +// VCVTPS2DQ m256 k ymm +// VCVTPS2DQ xmm k xmm +// VCVTPS2DQ ymm k ymm +// VCVTPS2DQ m512 k zmm +// VCVTPS2DQ m512 zmm +// VCVTPS2DQ zmm k zmm +// VCVTPS2DQ zmm zmm +// Construct and append a VCVTPS2DQ instruction to the active function. +func (c *Context) VCVTPS2DQ(ops ...operand.Op) { + c.addinstruction(x86.VCVTPS2DQ(ops...)) +} + +// VCVTPS2DQ: Convert Packed Single-Precision FP Values to Packed Dword Integers. +// +// Forms: +// +// VCVTPS2DQ m128 xmm +// VCVTPS2DQ m256 ymm +// VCVTPS2DQ xmm xmm +// VCVTPS2DQ ymm ymm +// VCVTPS2DQ m128 k xmm +// VCVTPS2DQ m256 k ymm +// VCVTPS2DQ xmm k xmm +// VCVTPS2DQ ymm k ymm +// VCVTPS2DQ m512 k zmm +// VCVTPS2DQ m512 zmm +// VCVTPS2DQ zmm k zmm +// VCVTPS2DQ zmm zmm +// Construct and append a VCVTPS2DQ instruction to the active function. +// Operates on the global context. +func VCVTPS2DQ(ops ...operand.Op) { ctx.VCVTPS2DQ(ops...) } + +// VCVTPS2DQ_BCST: Convert Packed Single-Precision FP Values to Packed Dword Integers (Broadcast). +// +// Forms: +// +// VCVTPS2DQ.BCST m32 k xmm +// VCVTPS2DQ.BCST m32 k ymm +// VCVTPS2DQ.BCST m32 xmm +// VCVTPS2DQ.BCST m32 ymm +// VCVTPS2DQ.BCST m32 k zmm +// VCVTPS2DQ.BCST m32 zmm +// Construct and append a VCVTPS2DQ.BCST instruction to the active function. +func (c *Context) VCVTPS2DQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTPS2DQ_BCST(ops...)) +} + +// VCVTPS2DQ_BCST: Convert Packed Single-Precision FP Values to Packed Dword Integers (Broadcast). +// +// Forms: +// +// VCVTPS2DQ.BCST m32 k xmm +// VCVTPS2DQ.BCST m32 k ymm +// VCVTPS2DQ.BCST m32 xmm +// VCVTPS2DQ.BCST m32 ymm +// VCVTPS2DQ.BCST m32 k zmm +// VCVTPS2DQ.BCST m32 zmm +// Construct and append a VCVTPS2DQ.BCST instruction to the active function. +// Operates on the global context. +func VCVTPS2DQ_BCST(ops ...operand.Op) { ctx.VCVTPS2DQ_BCST(ops...) } + +// VCVTPS2DQ_BCST_Z: Convert Packed Single-Precision FP Values to Packed Dword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPS2DQ.BCST.Z m32 k xmm +// VCVTPS2DQ.BCST.Z m32 k ymm +// VCVTPS2DQ.BCST.Z m32 k zmm +// Construct and append a VCVTPS2DQ.BCST.Z instruction to the active function. +func (c *Context) VCVTPS2DQ_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VCVTPS2DQ_BCST_Z(m, k, xyz)) +} + +// VCVTPS2DQ_BCST_Z: Convert Packed Single-Precision FP Values to Packed Dword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPS2DQ.BCST.Z m32 k xmm +// VCVTPS2DQ.BCST.Z m32 k ymm +// VCVTPS2DQ.BCST.Z m32 k zmm +// Construct and append a VCVTPS2DQ.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTPS2DQ_BCST_Z(m, k, xyz operand.Op) { ctx.VCVTPS2DQ_BCST_Z(m, k, xyz) } + +// VCVTPS2DQ_RD_SAE: Convert Packed Single-Precision FP Values to Packed Dword Integers (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTPS2DQ.RD_SAE zmm k zmm +// VCVTPS2DQ.RD_SAE zmm zmm +// Construct and append a VCVTPS2DQ.RD_SAE instruction to the active function. +func (c *Context) VCVTPS2DQ_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPS2DQ_RD_SAE(ops...)) +} + +// VCVTPS2DQ_RD_SAE: Convert Packed Single-Precision FP Values to Packed Dword Integers (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTPS2DQ.RD_SAE zmm k zmm +// VCVTPS2DQ.RD_SAE zmm zmm +// Construct and append a VCVTPS2DQ.RD_SAE instruction to the active function. +// Operates on the global context. +func VCVTPS2DQ_RD_SAE(ops ...operand.Op) { ctx.VCVTPS2DQ_RD_SAE(ops...) } + +// VCVTPS2DQ_RD_SAE_Z: Convert Packed Single-Precision FP Values to Packed Dword Integers (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPS2DQ.RD_SAE.Z zmm k zmm +// Construct and append a VCVTPS2DQ.RD_SAE.Z instruction to the active function. +func (c *Context) VCVTPS2DQ_RD_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTPS2DQ_RD_SAE_Z(z, k, z1)) +} + +// VCVTPS2DQ_RD_SAE_Z: Convert Packed Single-Precision FP Values to Packed Dword Integers (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPS2DQ.RD_SAE.Z zmm k zmm +// Construct and append a VCVTPS2DQ.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPS2DQ_RD_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTPS2DQ_RD_SAE_Z(z, k, z1) } + +// VCVTPS2DQ_RN_SAE: Convert Packed Single-Precision FP Values to Packed Dword Integers (Round Towards Nearest). +// +// Forms: +// +// VCVTPS2DQ.RN_SAE zmm k zmm +// VCVTPS2DQ.RN_SAE zmm zmm +// Construct and append a VCVTPS2DQ.RN_SAE instruction to the active function. +func (c *Context) VCVTPS2DQ_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPS2DQ_RN_SAE(ops...)) +} + +// VCVTPS2DQ_RN_SAE: Convert Packed Single-Precision FP Values to Packed Dword Integers (Round Towards Nearest). +// +// Forms: +// +// VCVTPS2DQ.RN_SAE zmm k zmm +// VCVTPS2DQ.RN_SAE zmm zmm +// Construct and append a VCVTPS2DQ.RN_SAE instruction to the active function. +// Operates on the global context. +func VCVTPS2DQ_RN_SAE(ops ...operand.Op) { ctx.VCVTPS2DQ_RN_SAE(ops...) } + +// VCVTPS2DQ_RN_SAE_Z: Convert Packed Single-Precision FP Values to Packed Dword Integers (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTPS2DQ.RN_SAE.Z zmm k zmm +// Construct and append a VCVTPS2DQ.RN_SAE.Z instruction to the active function. +func (c *Context) VCVTPS2DQ_RN_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTPS2DQ_RN_SAE_Z(z, k, z1)) +} + +// VCVTPS2DQ_RN_SAE_Z: Convert Packed Single-Precision FP Values to Packed Dword Integers (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTPS2DQ.RN_SAE.Z zmm k zmm +// Construct and append a VCVTPS2DQ.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPS2DQ_RN_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTPS2DQ_RN_SAE_Z(z, k, z1) } + +// VCVTPS2DQ_RU_SAE: Convert Packed Single-Precision FP Values to Packed Dword Integers (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTPS2DQ.RU_SAE zmm k zmm +// VCVTPS2DQ.RU_SAE zmm zmm +// Construct and append a VCVTPS2DQ.RU_SAE instruction to the active function. +func (c *Context) VCVTPS2DQ_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPS2DQ_RU_SAE(ops...)) +} + +// VCVTPS2DQ_RU_SAE: Convert Packed Single-Precision FP Values to Packed Dword Integers (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTPS2DQ.RU_SAE zmm k zmm +// VCVTPS2DQ.RU_SAE zmm zmm +// Construct and append a VCVTPS2DQ.RU_SAE instruction to the active function. +// Operates on the global context. +func VCVTPS2DQ_RU_SAE(ops ...operand.Op) { ctx.VCVTPS2DQ_RU_SAE(ops...) } + +// VCVTPS2DQ_RU_SAE_Z: Convert Packed Single-Precision FP Values to Packed Dword Integers (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPS2DQ.RU_SAE.Z zmm k zmm +// Construct and append a VCVTPS2DQ.RU_SAE.Z instruction to the active function. +func (c *Context) VCVTPS2DQ_RU_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTPS2DQ_RU_SAE_Z(z, k, z1)) +} + +// VCVTPS2DQ_RU_SAE_Z: Convert Packed Single-Precision FP Values to Packed Dword Integers (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPS2DQ.RU_SAE.Z zmm k zmm +// Construct and append a VCVTPS2DQ.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPS2DQ_RU_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTPS2DQ_RU_SAE_Z(z, k, z1) } + +// VCVTPS2DQ_RZ_SAE: Convert Packed Single-Precision FP Values to Packed Dword Integers (Round Towards Zero). +// +// Forms: +// +// VCVTPS2DQ.RZ_SAE zmm k zmm +// VCVTPS2DQ.RZ_SAE zmm zmm +// Construct and append a VCVTPS2DQ.RZ_SAE instruction to the active function. +func (c *Context) VCVTPS2DQ_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPS2DQ_RZ_SAE(ops...)) +} + +// VCVTPS2DQ_RZ_SAE: Convert Packed Single-Precision FP Values to Packed Dword Integers (Round Towards Zero). +// +// Forms: +// +// VCVTPS2DQ.RZ_SAE zmm k zmm +// VCVTPS2DQ.RZ_SAE zmm zmm +// Construct and append a VCVTPS2DQ.RZ_SAE instruction to the active function. +// Operates on the global context. +func VCVTPS2DQ_RZ_SAE(ops ...operand.Op) { ctx.VCVTPS2DQ_RZ_SAE(ops...) } + +// VCVTPS2DQ_RZ_SAE_Z: Convert Packed Single-Precision FP Values to Packed Dword Integers (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTPS2DQ.RZ_SAE.Z zmm k zmm +// Construct and append a VCVTPS2DQ.RZ_SAE.Z instruction to the active function. +func (c *Context) VCVTPS2DQ_RZ_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTPS2DQ_RZ_SAE_Z(z, k, z1)) +} + +// VCVTPS2DQ_RZ_SAE_Z: Convert Packed Single-Precision FP Values to Packed Dword Integers (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTPS2DQ.RZ_SAE.Z zmm k zmm +// Construct and append a VCVTPS2DQ.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPS2DQ_RZ_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTPS2DQ_RZ_SAE_Z(z, k, z1) } + +// VCVTPS2DQ_Z: Convert Packed Single-Precision FP Values to Packed Dword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTPS2DQ.Z m128 k xmm +// VCVTPS2DQ.Z m256 k ymm +// VCVTPS2DQ.Z xmm k xmm +// VCVTPS2DQ.Z ymm k ymm +// VCVTPS2DQ.Z m512 k zmm +// VCVTPS2DQ.Z zmm k zmm +// Construct and append a VCVTPS2DQ.Z instruction to the active function. +func (c *Context) VCVTPS2DQ_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VCVTPS2DQ_Z(mxyz, k, xyz)) +} + +// VCVTPS2DQ_Z: Convert Packed Single-Precision FP Values to Packed Dword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTPS2DQ.Z m128 k xmm +// VCVTPS2DQ.Z m256 k ymm +// VCVTPS2DQ.Z xmm k xmm +// VCVTPS2DQ.Z ymm k ymm +// VCVTPS2DQ.Z m512 k zmm +// VCVTPS2DQ.Z zmm k zmm +// Construct and append a VCVTPS2DQ.Z instruction to the active function. +// Operates on the global context. +func VCVTPS2DQ_Z(mxyz, k, xyz operand.Op) { ctx.VCVTPS2DQ_Z(mxyz, k, xyz) } + +// VCVTPS2PD: Convert Packed Single-Precision FP Values to Packed Double-Precision FP Values. +// +// Forms: +// +// VCVTPS2PD m128 ymm +// VCVTPS2PD m64 xmm +// VCVTPS2PD xmm xmm +// VCVTPS2PD xmm ymm +// VCVTPS2PD m64 k xmm +// VCVTPS2PD xmm k xmm +// VCVTPS2PD m256 k zmm +// VCVTPS2PD m256 zmm +// VCVTPS2PD ymm k zmm +// VCVTPS2PD ymm zmm +// VCVTPS2PD m128 k ymm +// VCVTPS2PD xmm k ymm +// Construct and append a VCVTPS2PD instruction to the active function. +func (c *Context) VCVTPS2PD(ops ...operand.Op) { + c.addinstruction(x86.VCVTPS2PD(ops...)) +} + +// VCVTPS2PD: Convert Packed Single-Precision FP Values to Packed Double-Precision FP Values. +// +// Forms: +// +// VCVTPS2PD m128 ymm +// VCVTPS2PD m64 xmm +// VCVTPS2PD xmm xmm +// VCVTPS2PD xmm ymm +// VCVTPS2PD m64 k xmm +// VCVTPS2PD xmm k xmm +// VCVTPS2PD m256 k zmm +// VCVTPS2PD m256 zmm +// VCVTPS2PD ymm k zmm +// VCVTPS2PD ymm zmm +// VCVTPS2PD m128 k ymm +// VCVTPS2PD xmm k ymm +// Construct and append a VCVTPS2PD instruction to the active function. +// Operates on the global context. +func VCVTPS2PD(ops ...operand.Op) { ctx.VCVTPS2PD(ops...) } + +// VCVTPS2PD_BCST: Convert Packed Single-Precision FP Values to Packed Double-Precision FP Values (Broadcast). +// +// Forms: +// +// VCVTPS2PD.BCST m32 k xmm +// VCVTPS2PD.BCST m32 xmm +// VCVTPS2PD.BCST m32 k zmm +// VCVTPS2PD.BCST m32 zmm +// VCVTPS2PD.BCST m32 k ymm +// VCVTPS2PD.BCST m32 ymm +// Construct and append a VCVTPS2PD.BCST instruction to the active function. +func (c *Context) VCVTPS2PD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTPS2PD_BCST(ops...)) +} + +// VCVTPS2PD_BCST: Convert Packed Single-Precision FP Values to Packed Double-Precision FP Values (Broadcast). +// +// Forms: +// +// VCVTPS2PD.BCST m32 k xmm +// VCVTPS2PD.BCST m32 xmm +// VCVTPS2PD.BCST m32 k zmm +// VCVTPS2PD.BCST m32 zmm +// VCVTPS2PD.BCST m32 k ymm +// VCVTPS2PD.BCST m32 ymm +// Construct and append a VCVTPS2PD.BCST instruction to the active function. +// Operates on the global context. +func VCVTPS2PD_BCST(ops ...operand.Op) { ctx.VCVTPS2PD_BCST(ops...) } + +// VCVTPS2PD_BCST_Z: Convert Packed Single-Precision FP Values to Packed Double-Precision FP Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPS2PD.BCST.Z m32 k xmm +// VCVTPS2PD.BCST.Z m32 k zmm +// VCVTPS2PD.BCST.Z m32 k ymm +// Construct and append a VCVTPS2PD.BCST.Z instruction to the active function. +func (c *Context) VCVTPS2PD_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VCVTPS2PD_BCST_Z(m, k, xyz)) +} + +// VCVTPS2PD_BCST_Z: Convert Packed Single-Precision FP Values to Packed Double-Precision FP Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPS2PD.BCST.Z m32 k xmm +// VCVTPS2PD.BCST.Z m32 k zmm +// VCVTPS2PD.BCST.Z m32 k ymm +// Construct and append a VCVTPS2PD.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTPS2PD_BCST_Z(m, k, xyz operand.Op) { ctx.VCVTPS2PD_BCST_Z(m, k, xyz) } + +// VCVTPS2PD_SAE: Convert Packed Single-Precision FP Values to Packed Double-Precision FP Values (Suppress All Exceptions). +// +// Forms: +// +// VCVTPS2PD.SAE ymm k zmm +// VCVTPS2PD.SAE ymm zmm +// Construct and append a VCVTPS2PD.SAE instruction to the active function. +func (c *Context) VCVTPS2PD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPS2PD_SAE(ops...)) +} + +// VCVTPS2PD_SAE: Convert Packed Single-Precision FP Values to Packed Double-Precision FP Values (Suppress All Exceptions). +// +// Forms: +// +// VCVTPS2PD.SAE ymm k zmm +// VCVTPS2PD.SAE ymm zmm +// Construct and append a VCVTPS2PD.SAE instruction to the active function. +// Operates on the global context. +func VCVTPS2PD_SAE(ops ...operand.Op) { ctx.VCVTPS2PD_SAE(ops...) } + +// VCVTPS2PD_SAE_Z: Convert Packed Single-Precision FP Values to Packed Double-Precision FP Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTPS2PD.SAE.Z ymm k zmm +// Construct and append a VCVTPS2PD.SAE.Z instruction to the active function. +func (c *Context) VCVTPS2PD_SAE_Z(y, k, z operand.Op) { + c.addinstruction(x86.VCVTPS2PD_SAE_Z(y, k, z)) +} + +// VCVTPS2PD_SAE_Z: Convert Packed Single-Precision FP Values to Packed Double-Precision FP Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTPS2PD.SAE.Z ymm k zmm +// Construct and append a VCVTPS2PD.SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPS2PD_SAE_Z(y, k, z operand.Op) { ctx.VCVTPS2PD_SAE_Z(y, k, z) } + +// VCVTPS2PD_Z: Convert Packed Single-Precision FP Values to Packed Double-Precision FP Values (Zeroing Masking). +// +// Forms: +// +// VCVTPS2PD.Z m64 k xmm +// VCVTPS2PD.Z xmm k xmm +// VCVTPS2PD.Z m256 k zmm +// VCVTPS2PD.Z ymm k zmm +// VCVTPS2PD.Z m128 k ymm +// VCVTPS2PD.Z xmm k ymm +// Construct and append a VCVTPS2PD.Z instruction to the active function. +func (c *Context) VCVTPS2PD_Z(mxy, k, xyz operand.Op) { + c.addinstruction(x86.VCVTPS2PD_Z(mxy, k, xyz)) +} + +// VCVTPS2PD_Z: Convert Packed Single-Precision FP Values to Packed Double-Precision FP Values (Zeroing Masking). +// +// Forms: +// +// VCVTPS2PD.Z m64 k xmm +// VCVTPS2PD.Z xmm k xmm +// VCVTPS2PD.Z m256 k zmm +// VCVTPS2PD.Z ymm k zmm +// VCVTPS2PD.Z m128 k ymm +// VCVTPS2PD.Z xmm k ymm +// Construct and append a VCVTPS2PD.Z instruction to the active function. +// Operates on the global context. +func VCVTPS2PD_Z(mxy, k, xyz operand.Op) { ctx.VCVTPS2PD_Z(mxy, k, xyz) } + +// VCVTPS2PH: Convert Single-Precision FP value to Half-Precision FP value. +// +// Forms: +// +// VCVTPS2PH imm8 xmm m64 +// VCVTPS2PH imm8 xmm xmm +// VCVTPS2PH imm8 ymm m128 +// VCVTPS2PH imm8 ymm xmm +// VCVTPS2PH imm8 xmm k m64 +// VCVTPS2PH imm8 xmm k xmm +// VCVTPS2PH imm8 ymm k m128 +// VCVTPS2PH imm8 ymm k xmm +// VCVTPS2PH imm8 zmm k m256 +// VCVTPS2PH imm8 zmm k ymm +// VCVTPS2PH imm8 zmm m256 +// VCVTPS2PH imm8 zmm ymm +// Construct and append a VCVTPS2PH instruction to the active function. +func (c *Context) VCVTPS2PH(ops ...operand.Op) { + c.addinstruction(x86.VCVTPS2PH(ops...)) +} + +// VCVTPS2PH: Convert Single-Precision FP value to Half-Precision FP value. +// +// Forms: +// +// VCVTPS2PH imm8 xmm m64 +// VCVTPS2PH imm8 xmm xmm +// VCVTPS2PH imm8 ymm m128 +// VCVTPS2PH imm8 ymm xmm +// VCVTPS2PH imm8 xmm k m64 +// VCVTPS2PH imm8 xmm k xmm +// VCVTPS2PH imm8 ymm k m128 +// VCVTPS2PH imm8 ymm k xmm +// VCVTPS2PH imm8 zmm k m256 +// VCVTPS2PH imm8 zmm k ymm +// VCVTPS2PH imm8 zmm m256 +// VCVTPS2PH imm8 zmm ymm +// Construct and append a VCVTPS2PH instruction to the active function. +// Operates on the global context. +func VCVTPS2PH(ops ...operand.Op) { ctx.VCVTPS2PH(ops...) } + +// VCVTPS2PH_SAE: Convert Single-Precision FP value to Half-Precision FP value (Suppress All Exceptions). +// +// Forms: +// +// VCVTPS2PH.SAE imm8 zmm k ymm +// VCVTPS2PH.SAE imm8 zmm ymm +// Construct and append a VCVTPS2PH.SAE instruction to the active function. +func (c *Context) VCVTPS2PH_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPS2PH_SAE(ops...)) +} + +// VCVTPS2PH_SAE: Convert Single-Precision FP value to Half-Precision FP value (Suppress All Exceptions). +// +// Forms: +// +// VCVTPS2PH.SAE imm8 zmm k ymm +// VCVTPS2PH.SAE imm8 zmm ymm +// Construct and append a VCVTPS2PH.SAE instruction to the active function. +// Operates on the global context. +func VCVTPS2PH_SAE(ops ...operand.Op) { ctx.VCVTPS2PH_SAE(ops...) } + +// VCVTPS2PH_SAE_Z: Convert Single-Precision FP value to Half-Precision FP value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTPS2PH.SAE.Z imm8 zmm k ymm +// Construct and append a VCVTPS2PH.SAE.Z instruction to the active function. +func (c *Context) VCVTPS2PH_SAE_Z(i, z, k, y operand.Op) { + c.addinstruction(x86.VCVTPS2PH_SAE_Z(i, z, k, y)) +} + +// VCVTPS2PH_SAE_Z: Convert Single-Precision FP value to Half-Precision FP value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTPS2PH.SAE.Z imm8 zmm k ymm +// Construct and append a VCVTPS2PH.SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPS2PH_SAE_Z(i, z, k, y operand.Op) { ctx.VCVTPS2PH_SAE_Z(i, z, k, y) } + +// VCVTPS2PH_Z: Convert Single-Precision FP value to Half-Precision FP value (Zeroing Masking). +// +// Forms: +// +// VCVTPS2PH.Z imm8 xmm k m64 +// VCVTPS2PH.Z imm8 xmm k xmm +// VCVTPS2PH.Z imm8 ymm k m128 +// VCVTPS2PH.Z imm8 ymm k xmm +// VCVTPS2PH.Z imm8 zmm k m256 +// VCVTPS2PH.Z imm8 zmm k ymm +// Construct and append a VCVTPS2PH.Z instruction to the active function. +func (c *Context) VCVTPS2PH_Z(i, xyz, k, mxy operand.Op) { + c.addinstruction(x86.VCVTPS2PH_Z(i, xyz, k, mxy)) +} + +// VCVTPS2PH_Z: Convert Single-Precision FP value to Half-Precision FP value (Zeroing Masking). +// +// Forms: +// +// VCVTPS2PH.Z imm8 xmm k m64 +// VCVTPS2PH.Z imm8 xmm k xmm +// VCVTPS2PH.Z imm8 ymm k m128 +// VCVTPS2PH.Z imm8 ymm k xmm +// VCVTPS2PH.Z imm8 zmm k m256 +// VCVTPS2PH.Z imm8 zmm k ymm +// Construct and append a VCVTPS2PH.Z instruction to the active function. +// Operates on the global context. +func VCVTPS2PH_Z(i, xyz, k, mxy operand.Op) { ctx.VCVTPS2PH_Z(i, xyz, k, mxy) } + +// VCVTPS2QQ: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values. +// +// Forms: +// +// VCVTPS2QQ m128 k ymm +// VCVTPS2QQ m128 ymm +// VCVTPS2QQ m64 k xmm +// VCVTPS2QQ m64 xmm +// VCVTPS2QQ xmm k xmm +// VCVTPS2QQ xmm k ymm +// VCVTPS2QQ xmm xmm +// VCVTPS2QQ xmm ymm +// VCVTPS2QQ m256 k zmm +// VCVTPS2QQ m256 zmm +// VCVTPS2QQ ymm k zmm +// VCVTPS2QQ ymm zmm +// Construct and append a VCVTPS2QQ instruction to the active function. +func (c *Context) VCVTPS2QQ(ops ...operand.Op) { + c.addinstruction(x86.VCVTPS2QQ(ops...)) +} + +// VCVTPS2QQ: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values. +// +// Forms: +// +// VCVTPS2QQ m128 k ymm +// VCVTPS2QQ m128 ymm +// VCVTPS2QQ m64 k xmm +// VCVTPS2QQ m64 xmm +// VCVTPS2QQ xmm k xmm +// VCVTPS2QQ xmm k ymm +// VCVTPS2QQ xmm xmm +// VCVTPS2QQ xmm ymm +// VCVTPS2QQ m256 k zmm +// VCVTPS2QQ m256 zmm +// VCVTPS2QQ ymm k zmm +// VCVTPS2QQ ymm zmm +// Construct and append a VCVTPS2QQ instruction to the active function. +// Operates on the global context. +func VCVTPS2QQ(ops ...operand.Op) { ctx.VCVTPS2QQ(ops...) } + +// VCVTPS2QQ_BCST: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Broadcast). +// +// Forms: +// +// VCVTPS2QQ.BCST m32 k xmm +// VCVTPS2QQ.BCST m32 k ymm +// VCVTPS2QQ.BCST m32 xmm +// VCVTPS2QQ.BCST m32 ymm +// VCVTPS2QQ.BCST m32 k zmm +// VCVTPS2QQ.BCST m32 zmm +// Construct and append a VCVTPS2QQ.BCST instruction to the active function. +func (c *Context) VCVTPS2QQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTPS2QQ_BCST(ops...)) +} + +// VCVTPS2QQ_BCST: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Broadcast). +// +// Forms: +// +// VCVTPS2QQ.BCST m32 k xmm +// VCVTPS2QQ.BCST m32 k ymm +// VCVTPS2QQ.BCST m32 xmm +// VCVTPS2QQ.BCST m32 ymm +// VCVTPS2QQ.BCST m32 k zmm +// VCVTPS2QQ.BCST m32 zmm +// Construct and append a VCVTPS2QQ.BCST instruction to the active function. +// Operates on the global context. +func VCVTPS2QQ_BCST(ops ...operand.Op) { ctx.VCVTPS2QQ_BCST(ops...) } + +// VCVTPS2QQ_BCST_Z: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPS2QQ.BCST.Z m32 k xmm +// VCVTPS2QQ.BCST.Z m32 k ymm +// VCVTPS2QQ.BCST.Z m32 k zmm +// Construct and append a VCVTPS2QQ.BCST.Z instruction to the active function. +func (c *Context) VCVTPS2QQ_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VCVTPS2QQ_BCST_Z(m, k, xyz)) +} + +// VCVTPS2QQ_BCST_Z: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPS2QQ.BCST.Z m32 k xmm +// VCVTPS2QQ.BCST.Z m32 k ymm +// VCVTPS2QQ.BCST.Z m32 k zmm +// Construct and append a VCVTPS2QQ.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTPS2QQ_BCST_Z(m, k, xyz operand.Op) { ctx.VCVTPS2QQ_BCST_Z(m, k, xyz) } + +// VCVTPS2QQ_RD_SAE: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTPS2QQ.RD_SAE ymm k zmm +// VCVTPS2QQ.RD_SAE ymm zmm +// Construct and append a VCVTPS2QQ.RD_SAE instruction to the active function. +func (c *Context) VCVTPS2QQ_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPS2QQ_RD_SAE(ops...)) +} + +// VCVTPS2QQ_RD_SAE: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTPS2QQ.RD_SAE ymm k zmm +// VCVTPS2QQ.RD_SAE ymm zmm +// Construct and append a VCVTPS2QQ.RD_SAE instruction to the active function. +// Operates on the global context. +func VCVTPS2QQ_RD_SAE(ops ...operand.Op) { ctx.VCVTPS2QQ_RD_SAE(ops...) } + +// VCVTPS2QQ_RD_SAE_Z: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPS2QQ.RD_SAE.Z ymm k zmm +// Construct and append a VCVTPS2QQ.RD_SAE.Z instruction to the active function. +func (c *Context) VCVTPS2QQ_RD_SAE_Z(y, k, z operand.Op) { + c.addinstruction(x86.VCVTPS2QQ_RD_SAE_Z(y, k, z)) +} + +// VCVTPS2QQ_RD_SAE_Z: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPS2QQ.RD_SAE.Z ymm k zmm +// Construct and append a VCVTPS2QQ.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPS2QQ_RD_SAE_Z(y, k, z operand.Op) { ctx.VCVTPS2QQ_RD_SAE_Z(y, k, z) } + +// VCVTPS2QQ_RN_SAE: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Round Towards Nearest). +// +// Forms: +// +// VCVTPS2QQ.RN_SAE ymm k zmm +// VCVTPS2QQ.RN_SAE ymm zmm +// Construct and append a VCVTPS2QQ.RN_SAE instruction to the active function. +func (c *Context) VCVTPS2QQ_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPS2QQ_RN_SAE(ops...)) +} + +// VCVTPS2QQ_RN_SAE: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Round Towards Nearest). +// +// Forms: +// +// VCVTPS2QQ.RN_SAE ymm k zmm +// VCVTPS2QQ.RN_SAE ymm zmm +// Construct and append a VCVTPS2QQ.RN_SAE instruction to the active function. +// Operates on the global context. +func VCVTPS2QQ_RN_SAE(ops ...operand.Op) { ctx.VCVTPS2QQ_RN_SAE(ops...) } + +// VCVTPS2QQ_RN_SAE_Z: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTPS2QQ.RN_SAE.Z ymm k zmm +// Construct and append a VCVTPS2QQ.RN_SAE.Z instruction to the active function. +func (c *Context) VCVTPS2QQ_RN_SAE_Z(y, k, z operand.Op) { + c.addinstruction(x86.VCVTPS2QQ_RN_SAE_Z(y, k, z)) +} + +// VCVTPS2QQ_RN_SAE_Z: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTPS2QQ.RN_SAE.Z ymm k zmm +// Construct and append a VCVTPS2QQ.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPS2QQ_RN_SAE_Z(y, k, z operand.Op) { ctx.VCVTPS2QQ_RN_SAE_Z(y, k, z) } + +// VCVTPS2QQ_RU_SAE: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTPS2QQ.RU_SAE ymm k zmm +// VCVTPS2QQ.RU_SAE ymm zmm +// Construct and append a VCVTPS2QQ.RU_SAE instruction to the active function. +func (c *Context) VCVTPS2QQ_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPS2QQ_RU_SAE(ops...)) +} + +// VCVTPS2QQ_RU_SAE: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTPS2QQ.RU_SAE ymm k zmm +// VCVTPS2QQ.RU_SAE ymm zmm +// Construct and append a VCVTPS2QQ.RU_SAE instruction to the active function. +// Operates on the global context. +func VCVTPS2QQ_RU_SAE(ops ...operand.Op) { ctx.VCVTPS2QQ_RU_SAE(ops...) } + +// VCVTPS2QQ_RU_SAE_Z: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPS2QQ.RU_SAE.Z ymm k zmm +// Construct and append a VCVTPS2QQ.RU_SAE.Z instruction to the active function. +func (c *Context) VCVTPS2QQ_RU_SAE_Z(y, k, z operand.Op) { + c.addinstruction(x86.VCVTPS2QQ_RU_SAE_Z(y, k, z)) +} + +// VCVTPS2QQ_RU_SAE_Z: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPS2QQ.RU_SAE.Z ymm k zmm +// Construct and append a VCVTPS2QQ.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPS2QQ_RU_SAE_Z(y, k, z operand.Op) { ctx.VCVTPS2QQ_RU_SAE_Z(y, k, z) } + +// VCVTPS2QQ_RZ_SAE: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Round Towards Zero). +// +// Forms: +// +// VCVTPS2QQ.RZ_SAE ymm k zmm +// VCVTPS2QQ.RZ_SAE ymm zmm +// Construct and append a VCVTPS2QQ.RZ_SAE instruction to the active function. +func (c *Context) VCVTPS2QQ_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPS2QQ_RZ_SAE(ops...)) +} + +// VCVTPS2QQ_RZ_SAE: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Round Towards Zero). +// +// Forms: +// +// VCVTPS2QQ.RZ_SAE ymm k zmm +// VCVTPS2QQ.RZ_SAE ymm zmm +// Construct and append a VCVTPS2QQ.RZ_SAE instruction to the active function. +// Operates on the global context. +func VCVTPS2QQ_RZ_SAE(ops ...operand.Op) { ctx.VCVTPS2QQ_RZ_SAE(ops...) } + +// VCVTPS2QQ_RZ_SAE_Z: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTPS2QQ.RZ_SAE.Z ymm k zmm +// Construct and append a VCVTPS2QQ.RZ_SAE.Z instruction to the active function. +func (c *Context) VCVTPS2QQ_RZ_SAE_Z(y, k, z operand.Op) { + c.addinstruction(x86.VCVTPS2QQ_RZ_SAE_Z(y, k, z)) +} + +// VCVTPS2QQ_RZ_SAE_Z: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTPS2QQ.RZ_SAE.Z ymm k zmm +// Construct and append a VCVTPS2QQ.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPS2QQ_RZ_SAE_Z(y, k, z operand.Op) { ctx.VCVTPS2QQ_RZ_SAE_Z(y, k, z) } + +// VCVTPS2QQ_Z: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Zeroing Masking). +// +// Forms: +// +// VCVTPS2QQ.Z m128 k ymm +// VCVTPS2QQ.Z m64 k xmm +// VCVTPS2QQ.Z xmm k xmm +// VCVTPS2QQ.Z xmm k ymm +// VCVTPS2QQ.Z m256 k zmm +// VCVTPS2QQ.Z ymm k zmm +// Construct and append a VCVTPS2QQ.Z instruction to the active function. +func (c *Context) VCVTPS2QQ_Z(mxy, k, xyz operand.Op) { + c.addinstruction(x86.VCVTPS2QQ_Z(mxy, k, xyz)) +} + +// VCVTPS2QQ_Z: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Zeroing Masking). +// +// Forms: +// +// VCVTPS2QQ.Z m128 k ymm +// VCVTPS2QQ.Z m64 k xmm +// VCVTPS2QQ.Z xmm k xmm +// VCVTPS2QQ.Z xmm k ymm +// VCVTPS2QQ.Z m256 k zmm +// VCVTPS2QQ.Z ymm k zmm +// Construct and append a VCVTPS2QQ.Z instruction to the active function. +// Operates on the global context. +func VCVTPS2QQ_Z(mxy, k, xyz operand.Op) { ctx.VCVTPS2QQ_Z(mxy, k, xyz) } + +// VCVTPS2UDQ: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values. +// +// Forms: +// +// VCVTPS2UDQ m128 k xmm +// VCVTPS2UDQ m128 xmm +// VCVTPS2UDQ m256 k ymm +// VCVTPS2UDQ m256 ymm +// VCVTPS2UDQ xmm k xmm +// VCVTPS2UDQ xmm xmm +// VCVTPS2UDQ ymm k ymm +// VCVTPS2UDQ ymm ymm +// VCVTPS2UDQ m512 k zmm +// VCVTPS2UDQ m512 zmm +// VCVTPS2UDQ zmm k zmm +// VCVTPS2UDQ zmm zmm +// Construct and append a VCVTPS2UDQ instruction to the active function. +func (c *Context) VCVTPS2UDQ(ops ...operand.Op) { + c.addinstruction(x86.VCVTPS2UDQ(ops...)) +} + +// VCVTPS2UDQ: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values. +// +// Forms: +// +// VCVTPS2UDQ m128 k xmm +// VCVTPS2UDQ m128 xmm +// VCVTPS2UDQ m256 k ymm +// VCVTPS2UDQ m256 ymm +// VCVTPS2UDQ xmm k xmm +// VCVTPS2UDQ xmm xmm +// VCVTPS2UDQ ymm k ymm +// VCVTPS2UDQ ymm ymm +// VCVTPS2UDQ m512 k zmm +// VCVTPS2UDQ m512 zmm +// VCVTPS2UDQ zmm k zmm +// VCVTPS2UDQ zmm zmm +// Construct and append a VCVTPS2UDQ instruction to the active function. +// Operates on the global context. +func VCVTPS2UDQ(ops ...operand.Op) { ctx.VCVTPS2UDQ(ops...) } + +// VCVTPS2UDQ_BCST: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Broadcast). +// +// Forms: +// +// VCVTPS2UDQ.BCST m32 k xmm +// VCVTPS2UDQ.BCST m32 k ymm +// VCVTPS2UDQ.BCST m32 xmm +// VCVTPS2UDQ.BCST m32 ymm +// VCVTPS2UDQ.BCST m32 k zmm +// VCVTPS2UDQ.BCST m32 zmm +// Construct and append a VCVTPS2UDQ.BCST instruction to the active function. +func (c *Context) VCVTPS2UDQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTPS2UDQ_BCST(ops...)) +} + +// VCVTPS2UDQ_BCST: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Broadcast). +// +// Forms: +// +// VCVTPS2UDQ.BCST m32 k xmm +// VCVTPS2UDQ.BCST m32 k ymm +// VCVTPS2UDQ.BCST m32 xmm +// VCVTPS2UDQ.BCST m32 ymm +// VCVTPS2UDQ.BCST m32 k zmm +// VCVTPS2UDQ.BCST m32 zmm +// Construct and append a VCVTPS2UDQ.BCST instruction to the active function. +// Operates on the global context. +func VCVTPS2UDQ_BCST(ops ...operand.Op) { ctx.VCVTPS2UDQ_BCST(ops...) } + +// VCVTPS2UDQ_BCST_Z: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPS2UDQ.BCST.Z m32 k xmm +// VCVTPS2UDQ.BCST.Z m32 k ymm +// VCVTPS2UDQ.BCST.Z m32 k zmm +// Construct and append a VCVTPS2UDQ.BCST.Z instruction to the active function. +func (c *Context) VCVTPS2UDQ_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VCVTPS2UDQ_BCST_Z(m, k, xyz)) +} + +// VCVTPS2UDQ_BCST_Z: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPS2UDQ.BCST.Z m32 k xmm +// VCVTPS2UDQ.BCST.Z m32 k ymm +// VCVTPS2UDQ.BCST.Z m32 k zmm +// Construct and append a VCVTPS2UDQ.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTPS2UDQ_BCST_Z(m, k, xyz operand.Op) { ctx.VCVTPS2UDQ_BCST_Z(m, k, xyz) } + +// VCVTPS2UDQ_RD_SAE: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTPS2UDQ.RD_SAE zmm k zmm +// VCVTPS2UDQ.RD_SAE zmm zmm +// Construct and append a VCVTPS2UDQ.RD_SAE instruction to the active function. +func (c *Context) VCVTPS2UDQ_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPS2UDQ_RD_SAE(ops...)) +} + +// VCVTPS2UDQ_RD_SAE: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTPS2UDQ.RD_SAE zmm k zmm +// VCVTPS2UDQ.RD_SAE zmm zmm +// Construct and append a VCVTPS2UDQ.RD_SAE instruction to the active function. +// Operates on the global context. +func VCVTPS2UDQ_RD_SAE(ops ...operand.Op) { ctx.VCVTPS2UDQ_RD_SAE(ops...) } + +// VCVTPS2UDQ_RD_SAE_Z: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPS2UDQ.RD_SAE.Z zmm k zmm +// Construct and append a VCVTPS2UDQ.RD_SAE.Z instruction to the active function. +func (c *Context) VCVTPS2UDQ_RD_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTPS2UDQ_RD_SAE_Z(z, k, z1)) +} + +// VCVTPS2UDQ_RD_SAE_Z: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPS2UDQ.RD_SAE.Z zmm k zmm +// Construct and append a VCVTPS2UDQ.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPS2UDQ_RD_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTPS2UDQ_RD_SAE_Z(z, k, z1) } + +// VCVTPS2UDQ_RN_SAE: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Round Towards Nearest). +// +// Forms: +// +// VCVTPS2UDQ.RN_SAE zmm k zmm +// VCVTPS2UDQ.RN_SAE zmm zmm +// Construct and append a VCVTPS2UDQ.RN_SAE instruction to the active function. +func (c *Context) VCVTPS2UDQ_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPS2UDQ_RN_SAE(ops...)) +} + +// VCVTPS2UDQ_RN_SAE: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Round Towards Nearest). +// +// Forms: +// +// VCVTPS2UDQ.RN_SAE zmm k zmm +// VCVTPS2UDQ.RN_SAE zmm zmm +// Construct and append a VCVTPS2UDQ.RN_SAE instruction to the active function. +// Operates on the global context. +func VCVTPS2UDQ_RN_SAE(ops ...operand.Op) { ctx.VCVTPS2UDQ_RN_SAE(ops...) } + +// VCVTPS2UDQ_RN_SAE_Z: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTPS2UDQ.RN_SAE.Z zmm k zmm +// Construct and append a VCVTPS2UDQ.RN_SAE.Z instruction to the active function. +func (c *Context) VCVTPS2UDQ_RN_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTPS2UDQ_RN_SAE_Z(z, k, z1)) +} + +// VCVTPS2UDQ_RN_SAE_Z: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTPS2UDQ.RN_SAE.Z zmm k zmm +// Construct and append a VCVTPS2UDQ.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPS2UDQ_RN_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTPS2UDQ_RN_SAE_Z(z, k, z1) } + +// VCVTPS2UDQ_RU_SAE: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTPS2UDQ.RU_SAE zmm k zmm +// VCVTPS2UDQ.RU_SAE zmm zmm +// Construct and append a VCVTPS2UDQ.RU_SAE instruction to the active function. +func (c *Context) VCVTPS2UDQ_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPS2UDQ_RU_SAE(ops...)) +} + +// VCVTPS2UDQ_RU_SAE: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTPS2UDQ.RU_SAE zmm k zmm +// VCVTPS2UDQ.RU_SAE zmm zmm +// Construct and append a VCVTPS2UDQ.RU_SAE instruction to the active function. +// Operates on the global context. +func VCVTPS2UDQ_RU_SAE(ops ...operand.Op) { ctx.VCVTPS2UDQ_RU_SAE(ops...) } + +// VCVTPS2UDQ_RU_SAE_Z: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPS2UDQ.RU_SAE.Z zmm k zmm +// Construct and append a VCVTPS2UDQ.RU_SAE.Z instruction to the active function. +func (c *Context) VCVTPS2UDQ_RU_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTPS2UDQ_RU_SAE_Z(z, k, z1)) +} + +// VCVTPS2UDQ_RU_SAE_Z: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPS2UDQ.RU_SAE.Z zmm k zmm +// Construct and append a VCVTPS2UDQ.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPS2UDQ_RU_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTPS2UDQ_RU_SAE_Z(z, k, z1) } + +// VCVTPS2UDQ_RZ_SAE: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Round Towards Zero). +// +// Forms: +// +// VCVTPS2UDQ.RZ_SAE zmm k zmm +// VCVTPS2UDQ.RZ_SAE zmm zmm +// Construct and append a VCVTPS2UDQ.RZ_SAE instruction to the active function. +func (c *Context) VCVTPS2UDQ_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPS2UDQ_RZ_SAE(ops...)) +} + +// VCVTPS2UDQ_RZ_SAE: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Round Towards Zero). +// +// Forms: +// +// VCVTPS2UDQ.RZ_SAE zmm k zmm +// VCVTPS2UDQ.RZ_SAE zmm zmm +// Construct and append a VCVTPS2UDQ.RZ_SAE instruction to the active function. +// Operates on the global context. +func VCVTPS2UDQ_RZ_SAE(ops ...operand.Op) { ctx.VCVTPS2UDQ_RZ_SAE(ops...) } + +// VCVTPS2UDQ_RZ_SAE_Z: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTPS2UDQ.RZ_SAE.Z zmm k zmm +// Construct and append a VCVTPS2UDQ.RZ_SAE.Z instruction to the active function. +func (c *Context) VCVTPS2UDQ_RZ_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTPS2UDQ_RZ_SAE_Z(z, k, z1)) +} + +// VCVTPS2UDQ_RZ_SAE_Z: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTPS2UDQ.RZ_SAE.Z zmm k zmm +// Construct and append a VCVTPS2UDQ.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPS2UDQ_RZ_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTPS2UDQ_RZ_SAE_Z(z, k, z1) } + +// VCVTPS2UDQ_Z: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Zeroing Masking). +// +// Forms: +// +// VCVTPS2UDQ.Z m128 k xmm +// VCVTPS2UDQ.Z m256 k ymm +// VCVTPS2UDQ.Z xmm k xmm +// VCVTPS2UDQ.Z ymm k ymm +// VCVTPS2UDQ.Z m512 k zmm +// VCVTPS2UDQ.Z zmm k zmm +// Construct and append a VCVTPS2UDQ.Z instruction to the active function. +func (c *Context) VCVTPS2UDQ_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VCVTPS2UDQ_Z(mxyz, k, xyz)) +} + +// VCVTPS2UDQ_Z: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Zeroing Masking). +// +// Forms: +// +// VCVTPS2UDQ.Z m128 k xmm +// VCVTPS2UDQ.Z m256 k ymm +// VCVTPS2UDQ.Z xmm k xmm +// VCVTPS2UDQ.Z ymm k ymm +// VCVTPS2UDQ.Z m512 k zmm +// VCVTPS2UDQ.Z zmm k zmm +// Construct and append a VCVTPS2UDQ.Z instruction to the active function. +// Operates on the global context. +func VCVTPS2UDQ_Z(mxyz, k, xyz operand.Op) { ctx.VCVTPS2UDQ_Z(mxyz, k, xyz) } + +// VCVTPS2UQQ: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values. +// +// Forms: +// +// VCVTPS2UQQ m128 k ymm +// VCVTPS2UQQ m128 ymm +// VCVTPS2UQQ m64 k xmm +// VCVTPS2UQQ m64 xmm +// VCVTPS2UQQ xmm k xmm +// VCVTPS2UQQ xmm k ymm +// VCVTPS2UQQ xmm xmm +// VCVTPS2UQQ xmm ymm +// VCVTPS2UQQ m256 k zmm +// VCVTPS2UQQ m256 zmm +// VCVTPS2UQQ ymm k zmm +// VCVTPS2UQQ ymm zmm +// Construct and append a VCVTPS2UQQ instruction to the active function. +func (c *Context) VCVTPS2UQQ(ops ...operand.Op) { + c.addinstruction(x86.VCVTPS2UQQ(ops...)) +} + +// VCVTPS2UQQ: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values. +// +// Forms: +// +// VCVTPS2UQQ m128 k ymm +// VCVTPS2UQQ m128 ymm +// VCVTPS2UQQ m64 k xmm +// VCVTPS2UQQ m64 xmm +// VCVTPS2UQQ xmm k xmm +// VCVTPS2UQQ xmm k ymm +// VCVTPS2UQQ xmm xmm +// VCVTPS2UQQ xmm ymm +// VCVTPS2UQQ m256 k zmm +// VCVTPS2UQQ m256 zmm +// VCVTPS2UQQ ymm k zmm +// VCVTPS2UQQ ymm zmm +// Construct and append a VCVTPS2UQQ instruction to the active function. +// Operates on the global context. +func VCVTPS2UQQ(ops ...operand.Op) { ctx.VCVTPS2UQQ(ops...) } + +// VCVTPS2UQQ_BCST: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Broadcast). +// +// Forms: +// +// VCVTPS2UQQ.BCST m32 k xmm +// VCVTPS2UQQ.BCST m32 k ymm +// VCVTPS2UQQ.BCST m32 xmm +// VCVTPS2UQQ.BCST m32 ymm +// VCVTPS2UQQ.BCST m32 k zmm +// VCVTPS2UQQ.BCST m32 zmm +// Construct and append a VCVTPS2UQQ.BCST instruction to the active function. +func (c *Context) VCVTPS2UQQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTPS2UQQ_BCST(ops...)) +} + +// VCVTPS2UQQ_BCST: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Broadcast). +// +// Forms: +// +// VCVTPS2UQQ.BCST m32 k xmm +// VCVTPS2UQQ.BCST m32 k ymm +// VCVTPS2UQQ.BCST m32 xmm +// VCVTPS2UQQ.BCST m32 ymm +// VCVTPS2UQQ.BCST m32 k zmm +// VCVTPS2UQQ.BCST m32 zmm +// Construct and append a VCVTPS2UQQ.BCST instruction to the active function. +// Operates on the global context. +func VCVTPS2UQQ_BCST(ops ...operand.Op) { ctx.VCVTPS2UQQ_BCST(ops...) } + +// VCVTPS2UQQ_BCST_Z: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPS2UQQ.BCST.Z m32 k xmm +// VCVTPS2UQQ.BCST.Z m32 k ymm +// VCVTPS2UQQ.BCST.Z m32 k zmm +// Construct and append a VCVTPS2UQQ.BCST.Z instruction to the active function. +func (c *Context) VCVTPS2UQQ_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VCVTPS2UQQ_BCST_Z(m, k, xyz)) +} + +// VCVTPS2UQQ_BCST_Z: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPS2UQQ.BCST.Z m32 k xmm +// VCVTPS2UQQ.BCST.Z m32 k ymm +// VCVTPS2UQQ.BCST.Z m32 k zmm +// Construct and append a VCVTPS2UQQ.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTPS2UQQ_BCST_Z(m, k, xyz operand.Op) { ctx.VCVTPS2UQQ_BCST_Z(m, k, xyz) } + +// VCVTPS2UQQ_RD_SAE: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTPS2UQQ.RD_SAE ymm k zmm +// VCVTPS2UQQ.RD_SAE ymm zmm +// Construct and append a VCVTPS2UQQ.RD_SAE instruction to the active function. +func (c *Context) VCVTPS2UQQ_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPS2UQQ_RD_SAE(ops...)) +} + +// VCVTPS2UQQ_RD_SAE: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTPS2UQQ.RD_SAE ymm k zmm +// VCVTPS2UQQ.RD_SAE ymm zmm +// Construct and append a VCVTPS2UQQ.RD_SAE instruction to the active function. +// Operates on the global context. +func VCVTPS2UQQ_RD_SAE(ops ...operand.Op) { ctx.VCVTPS2UQQ_RD_SAE(ops...) } + +// VCVTPS2UQQ_RD_SAE_Z: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPS2UQQ.RD_SAE.Z ymm k zmm +// Construct and append a VCVTPS2UQQ.RD_SAE.Z instruction to the active function. +func (c *Context) VCVTPS2UQQ_RD_SAE_Z(y, k, z operand.Op) { + c.addinstruction(x86.VCVTPS2UQQ_RD_SAE_Z(y, k, z)) +} + +// VCVTPS2UQQ_RD_SAE_Z: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPS2UQQ.RD_SAE.Z ymm k zmm +// Construct and append a VCVTPS2UQQ.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPS2UQQ_RD_SAE_Z(y, k, z operand.Op) { ctx.VCVTPS2UQQ_RD_SAE_Z(y, k, z) } + +// VCVTPS2UQQ_RN_SAE: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Round Towards Nearest). +// +// Forms: +// +// VCVTPS2UQQ.RN_SAE ymm k zmm +// VCVTPS2UQQ.RN_SAE ymm zmm +// Construct and append a VCVTPS2UQQ.RN_SAE instruction to the active function. +func (c *Context) VCVTPS2UQQ_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPS2UQQ_RN_SAE(ops...)) +} + +// VCVTPS2UQQ_RN_SAE: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Round Towards Nearest). +// +// Forms: +// +// VCVTPS2UQQ.RN_SAE ymm k zmm +// VCVTPS2UQQ.RN_SAE ymm zmm +// Construct and append a VCVTPS2UQQ.RN_SAE instruction to the active function. +// Operates on the global context. +func VCVTPS2UQQ_RN_SAE(ops ...operand.Op) { ctx.VCVTPS2UQQ_RN_SAE(ops...) } + +// VCVTPS2UQQ_RN_SAE_Z: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTPS2UQQ.RN_SAE.Z ymm k zmm +// Construct and append a VCVTPS2UQQ.RN_SAE.Z instruction to the active function. +func (c *Context) VCVTPS2UQQ_RN_SAE_Z(y, k, z operand.Op) { + c.addinstruction(x86.VCVTPS2UQQ_RN_SAE_Z(y, k, z)) +} + +// VCVTPS2UQQ_RN_SAE_Z: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTPS2UQQ.RN_SAE.Z ymm k zmm +// Construct and append a VCVTPS2UQQ.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPS2UQQ_RN_SAE_Z(y, k, z operand.Op) { ctx.VCVTPS2UQQ_RN_SAE_Z(y, k, z) } + +// VCVTPS2UQQ_RU_SAE: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTPS2UQQ.RU_SAE ymm k zmm +// VCVTPS2UQQ.RU_SAE ymm zmm +// Construct and append a VCVTPS2UQQ.RU_SAE instruction to the active function. +func (c *Context) VCVTPS2UQQ_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPS2UQQ_RU_SAE(ops...)) +} + +// VCVTPS2UQQ_RU_SAE: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTPS2UQQ.RU_SAE ymm k zmm +// VCVTPS2UQQ.RU_SAE ymm zmm +// Construct and append a VCVTPS2UQQ.RU_SAE instruction to the active function. +// Operates on the global context. +func VCVTPS2UQQ_RU_SAE(ops ...operand.Op) { ctx.VCVTPS2UQQ_RU_SAE(ops...) } + +// VCVTPS2UQQ_RU_SAE_Z: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPS2UQQ.RU_SAE.Z ymm k zmm +// Construct and append a VCVTPS2UQQ.RU_SAE.Z instruction to the active function. +func (c *Context) VCVTPS2UQQ_RU_SAE_Z(y, k, z operand.Op) { + c.addinstruction(x86.VCVTPS2UQQ_RU_SAE_Z(y, k, z)) +} + +// VCVTPS2UQQ_RU_SAE_Z: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPS2UQQ.RU_SAE.Z ymm k zmm +// Construct and append a VCVTPS2UQQ.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPS2UQQ_RU_SAE_Z(y, k, z operand.Op) { ctx.VCVTPS2UQQ_RU_SAE_Z(y, k, z) } + +// VCVTPS2UQQ_RZ_SAE: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Round Towards Zero). +// +// Forms: +// +// VCVTPS2UQQ.RZ_SAE ymm k zmm +// VCVTPS2UQQ.RZ_SAE ymm zmm +// Construct and append a VCVTPS2UQQ.RZ_SAE instruction to the active function. +func (c *Context) VCVTPS2UQQ_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTPS2UQQ_RZ_SAE(ops...)) +} + +// VCVTPS2UQQ_RZ_SAE: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Round Towards Zero). +// +// Forms: +// +// VCVTPS2UQQ.RZ_SAE ymm k zmm +// VCVTPS2UQQ.RZ_SAE ymm zmm +// Construct and append a VCVTPS2UQQ.RZ_SAE instruction to the active function. +// Operates on the global context. +func VCVTPS2UQQ_RZ_SAE(ops ...operand.Op) { ctx.VCVTPS2UQQ_RZ_SAE(ops...) } + +// VCVTPS2UQQ_RZ_SAE_Z: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTPS2UQQ.RZ_SAE.Z ymm k zmm +// Construct and append a VCVTPS2UQQ.RZ_SAE.Z instruction to the active function. +func (c *Context) VCVTPS2UQQ_RZ_SAE_Z(y, k, z operand.Op) { + c.addinstruction(x86.VCVTPS2UQQ_RZ_SAE_Z(y, k, z)) +} + +// VCVTPS2UQQ_RZ_SAE_Z: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTPS2UQQ.RZ_SAE.Z ymm k zmm +// Construct and append a VCVTPS2UQQ.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTPS2UQQ_RZ_SAE_Z(y, k, z operand.Op) { ctx.VCVTPS2UQQ_RZ_SAE_Z(y, k, z) } + +// VCVTPS2UQQ_Z: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Zeroing Masking). +// +// Forms: +// +// VCVTPS2UQQ.Z m128 k ymm +// VCVTPS2UQQ.Z m64 k xmm +// VCVTPS2UQQ.Z xmm k xmm +// VCVTPS2UQQ.Z xmm k ymm +// VCVTPS2UQQ.Z m256 k zmm +// VCVTPS2UQQ.Z ymm k zmm +// Construct and append a VCVTPS2UQQ.Z instruction to the active function. +func (c *Context) VCVTPS2UQQ_Z(mxy, k, xyz operand.Op) { + c.addinstruction(x86.VCVTPS2UQQ_Z(mxy, k, xyz)) +} + +// VCVTPS2UQQ_Z: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Zeroing Masking). +// +// Forms: +// +// VCVTPS2UQQ.Z m128 k ymm +// VCVTPS2UQQ.Z m64 k xmm +// VCVTPS2UQQ.Z xmm k xmm +// VCVTPS2UQQ.Z xmm k ymm +// VCVTPS2UQQ.Z m256 k zmm +// VCVTPS2UQQ.Z ymm k zmm +// Construct and append a VCVTPS2UQQ.Z instruction to the active function. +// Operates on the global context. +func VCVTPS2UQQ_Z(mxy, k, xyz operand.Op) { ctx.VCVTPS2UQQ_Z(mxy, k, xyz) } + +// VCVTQQ2PD: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VCVTQQ2PD m128 k xmm +// VCVTQQ2PD m128 xmm +// VCVTQQ2PD m256 k ymm +// VCVTQQ2PD m256 ymm +// VCVTQQ2PD xmm k xmm +// VCVTQQ2PD xmm xmm +// VCVTQQ2PD ymm k ymm +// VCVTQQ2PD ymm ymm +// VCVTQQ2PD m512 k zmm +// VCVTQQ2PD m512 zmm +// VCVTQQ2PD zmm k zmm +// VCVTQQ2PD zmm zmm +// Construct and append a VCVTQQ2PD instruction to the active function. +func (c *Context) VCVTQQ2PD(ops ...operand.Op) { + c.addinstruction(x86.VCVTQQ2PD(ops...)) +} + +// VCVTQQ2PD: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VCVTQQ2PD m128 k xmm +// VCVTQQ2PD m128 xmm +// VCVTQQ2PD m256 k ymm +// VCVTQQ2PD m256 ymm +// VCVTQQ2PD xmm k xmm +// VCVTQQ2PD xmm xmm +// VCVTQQ2PD ymm k ymm +// VCVTQQ2PD ymm ymm +// VCVTQQ2PD m512 k zmm +// VCVTQQ2PD m512 zmm +// VCVTQQ2PD zmm k zmm +// VCVTQQ2PD zmm zmm +// Construct and append a VCVTQQ2PD instruction to the active function. +// Operates on the global context. +func VCVTQQ2PD(ops ...operand.Op) { ctx.VCVTQQ2PD(ops...) } + +// VCVTQQ2PD_BCST: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCVTQQ2PD.BCST m64 k xmm +// VCVTQQ2PD.BCST m64 k ymm +// VCVTQQ2PD.BCST m64 xmm +// VCVTQQ2PD.BCST m64 ymm +// VCVTQQ2PD.BCST m64 k zmm +// VCVTQQ2PD.BCST m64 zmm +// Construct and append a VCVTQQ2PD.BCST instruction to the active function. +func (c *Context) VCVTQQ2PD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTQQ2PD_BCST(ops...)) +} + +// VCVTQQ2PD_BCST: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCVTQQ2PD.BCST m64 k xmm +// VCVTQQ2PD.BCST m64 k ymm +// VCVTQQ2PD.BCST m64 xmm +// VCVTQQ2PD.BCST m64 ymm +// VCVTQQ2PD.BCST m64 k zmm +// VCVTQQ2PD.BCST m64 zmm +// Construct and append a VCVTQQ2PD.BCST instruction to the active function. +// Operates on the global context. +func VCVTQQ2PD_BCST(ops ...operand.Op) { ctx.VCVTQQ2PD_BCST(ops...) } + +// VCVTQQ2PD_BCST_Z: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PD.BCST.Z m64 k xmm +// VCVTQQ2PD.BCST.Z m64 k ymm +// VCVTQQ2PD.BCST.Z m64 k zmm +// Construct and append a VCVTQQ2PD.BCST.Z instruction to the active function. +func (c *Context) VCVTQQ2PD_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VCVTQQ2PD_BCST_Z(m, k, xyz)) +} + +// VCVTQQ2PD_BCST_Z: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PD.BCST.Z m64 k xmm +// VCVTQQ2PD.BCST.Z m64 k ymm +// VCVTQQ2PD.BCST.Z m64 k zmm +// Construct and append a VCVTQQ2PD.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTQQ2PD_BCST_Z(m, k, xyz operand.Op) { ctx.VCVTQQ2PD_BCST_Z(m, k, xyz) } + +// VCVTQQ2PD_RD_SAE: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTQQ2PD.RD_SAE zmm k zmm +// VCVTQQ2PD.RD_SAE zmm zmm +// Construct and append a VCVTQQ2PD.RD_SAE instruction to the active function. +func (c *Context) VCVTQQ2PD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTQQ2PD_RD_SAE(ops...)) +} + +// VCVTQQ2PD_RD_SAE: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTQQ2PD.RD_SAE zmm k zmm +// VCVTQQ2PD.RD_SAE zmm zmm +// Construct and append a VCVTQQ2PD.RD_SAE instruction to the active function. +// Operates on the global context. +func VCVTQQ2PD_RD_SAE(ops ...operand.Op) { ctx.VCVTQQ2PD_RD_SAE(ops...) } + +// VCVTQQ2PD_RD_SAE_Z: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PD.RD_SAE.Z zmm k zmm +// Construct and append a VCVTQQ2PD.RD_SAE.Z instruction to the active function. +func (c *Context) VCVTQQ2PD_RD_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTQQ2PD_RD_SAE_Z(z, k, z1)) +} + +// VCVTQQ2PD_RD_SAE_Z: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PD.RD_SAE.Z zmm k zmm +// Construct and append a VCVTQQ2PD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTQQ2PD_RD_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTQQ2PD_RD_SAE_Z(z, k, z1) } + +// VCVTQQ2PD_RN_SAE: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VCVTQQ2PD.RN_SAE zmm k zmm +// VCVTQQ2PD.RN_SAE zmm zmm +// Construct and append a VCVTQQ2PD.RN_SAE instruction to the active function. +func (c *Context) VCVTQQ2PD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTQQ2PD_RN_SAE(ops...)) +} + +// VCVTQQ2PD_RN_SAE: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VCVTQQ2PD.RN_SAE zmm k zmm +// VCVTQQ2PD.RN_SAE zmm zmm +// Construct and append a VCVTQQ2PD.RN_SAE instruction to the active function. +// Operates on the global context. +func VCVTQQ2PD_RN_SAE(ops ...operand.Op) { ctx.VCVTQQ2PD_RN_SAE(ops...) } + +// VCVTQQ2PD_RN_SAE_Z: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PD.RN_SAE.Z zmm k zmm +// Construct and append a VCVTQQ2PD.RN_SAE.Z instruction to the active function. +func (c *Context) VCVTQQ2PD_RN_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTQQ2PD_RN_SAE_Z(z, k, z1)) +} + +// VCVTQQ2PD_RN_SAE_Z: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PD.RN_SAE.Z zmm k zmm +// Construct and append a VCVTQQ2PD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTQQ2PD_RN_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTQQ2PD_RN_SAE_Z(z, k, z1) } + +// VCVTQQ2PD_RU_SAE: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTQQ2PD.RU_SAE zmm k zmm +// VCVTQQ2PD.RU_SAE zmm zmm +// Construct and append a VCVTQQ2PD.RU_SAE instruction to the active function. +func (c *Context) VCVTQQ2PD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTQQ2PD_RU_SAE(ops...)) +} + +// VCVTQQ2PD_RU_SAE: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTQQ2PD.RU_SAE zmm k zmm +// VCVTQQ2PD.RU_SAE zmm zmm +// Construct and append a VCVTQQ2PD.RU_SAE instruction to the active function. +// Operates on the global context. +func VCVTQQ2PD_RU_SAE(ops ...operand.Op) { ctx.VCVTQQ2PD_RU_SAE(ops...) } + +// VCVTQQ2PD_RU_SAE_Z: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PD.RU_SAE.Z zmm k zmm +// Construct and append a VCVTQQ2PD.RU_SAE.Z instruction to the active function. +func (c *Context) VCVTQQ2PD_RU_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTQQ2PD_RU_SAE_Z(z, k, z1)) +} + +// VCVTQQ2PD_RU_SAE_Z: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PD.RU_SAE.Z zmm k zmm +// Construct and append a VCVTQQ2PD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTQQ2PD_RU_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTQQ2PD_RU_SAE_Z(z, k, z1) } + +// VCVTQQ2PD_RZ_SAE: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VCVTQQ2PD.RZ_SAE zmm k zmm +// VCVTQQ2PD.RZ_SAE zmm zmm +// Construct and append a VCVTQQ2PD.RZ_SAE instruction to the active function. +func (c *Context) VCVTQQ2PD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTQQ2PD_RZ_SAE(ops...)) +} + +// VCVTQQ2PD_RZ_SAE: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VCVTQQ2PD.RZ_SAE zmm k zmm +// VCVTQQ2PD.RZ_SAE zmm zmm +// Construct and append a VCVTQQ2PD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VCVTQQ2PD_RZ_SAE(ops ...operand.Op) { ctx.VCVTQQ2PD_RZ_SAE(ops...) } + +// VCVTQQ2PD_RZ_SAE_Z: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PD.RZ_SAE.Z zmm k zmm +// Construct and append a VCVTQQ2PD.RZ_SAE.Z instruction to the active function. +func (c *Context) VCVTQQ2PD_RZ_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTQQ2PD_RZ_SAE_Z(z, k, z1)) +} + +// VCVTQQ2PD_RZ_SAE_Z: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PD.RZ_SAE.Z zmm k zmm +// Construct and append a VCVTQQ2PD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTQQ2PD_RZ_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTQQ2PD_RZ_SAE_Z(z, k, z1) } + +// VCVTQQ2PD_Z: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PD.Z m128 k xmm +// VCVTQQ2PD.Z m256 k ymm +// VCVTQQ2PD.Z xmm k xmm +// VCVTQQ2PD.Z ymm k ymm +// VCVTQQ2PD.Z m512 k zmm +// VCVTQQ2PD.Z zmm k zmm +// Construct and append a VCVTQQ2PD.Z instruction to the active function. +func (c *Context) VCVTQQ2PD_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VCVTQQ2PD_Z(mxyz, k, xyz)) +} + +// VCVTQQ2PD_Z: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PD.Z m128 k xmm +// VCVTQQ2PD.Z m256 k ymm +// VCVTQQ2PD.Z xmm k xmm +// VCVTQQ2PD.Z ymm k ymm +// VCVTQQ2PD.Z m512 k zmm +// VCVTQQ2PD.Z zmm k zmm +// Construct and append a VCVTQQ2PD.Z instruction to the active function. +// Operates on the global context. +func VCVTQQ2PD_Z(mxyz, k, xyz operand.Op) { ctx.VCVTQQ2PD_Z(mxyz, k, xyz) } + +// VCVTQQ2PS: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VCVTQQ2PS m512 k ymm +// VCVTQQ2PS m512 ymm +// VCVTQQ2PS zmm k ymm +// VCVTQQ2PS zmm ymm +// Construct and append a VCVTQQ2PS instruction to the active function. +func (c *Context) VCVTQQ2PS(ops ...operand.Op) { + c.addinstruction(x86.VCVTQQ2PS(ops...)) +} + +// VCVTQQ2PS: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VCVTQQ2PS m512 k ymm +// VCVTQQ2PS m512 ymm +// VCVTQQ2PS zmm k ymm +// VCVTQQ2PS zmm ymm +// Construct and append a VCVTQQ2PS instruction to the active function. +// Operates on the global context. +func VCVTQQ2PS(ops ...operand.Op) { ctx.VCVTQQ2PS(ops...) } + +// VCVTQQ2PSX: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VCVTQQ2PSX m128 k xmm +// VCVTQQ2PSX m128 xmm +// VCVTQQ2PSX xmm k xmm +// VCVTQQ2PSX xmm xmm +// Construct and append a VCVTQQ2PSX instruction to the active function. +func (c *Context) VCVTQQ2PSX(ops ...operand.Op) { + c.addinstruction(x86.VCVTQQ2PSX(ops...)) +} + +// VCVTQQ2PSX: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VCVTQQ2PSX m128 k xmm +// VCVTQQ2PSX m128 xmm +// VCVTQQ2PSX xmm k xmm +// VCVTQQ2PSX xmm xmm +// Construct and append a VCVTQQ2PSX instruction to the active function. +// Operates on the global context. +func VCVTQQ2PSX(ops ...operand.Op) { ctx.VCVTQQ2PSX(ops...) } + +// VCVTQQ2PSX_BCST: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCVTQQ2PSX.BCST m64 k xmm +// VCVTQQ2PSX.BCST m64 xmm +// Construct and append a VCVTQQ2PSX.BCST instruction to the active function. +func (c *Context) VCVTQQ2PSX_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTQQ2PSX_BCST(ops...)) +} + +// VCVTQQ2PSX_BCST: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCVTQQ2PSX.BCST m64 k xmm +// VCVTQQ2PSX.BCST m64 xmm +// Construct and append a VCVTQQ2PSX.BCST instruction to the active function. +// Operates on the global context. +func VCVTQQ2PSX_BCST(ops ...operand.Op) { ctx.VCVTQQ2PSX_BCST(ops...) } + +// VCVTQQ2PSX_BCST_Z: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PSX.BCST.Z m64 k xmm +// Construct and append a VCVTQQ2PSX.BCST.Z instruction to the active function. +func (c *Context) VCVTQQ2PSX_BCST_Z(m, k, x operand.Op) { + c.addinstruction(x86.VCVTQQ2PSX_BCST_Z(m, k, x)) +} + +// VCVTQQ2PSX_BCST_Z: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PSX.BCST.Z m64 k xmm +// Construct and append a VCVTQQ2PSX.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTQQ2PSX_BCST_Z(m, k, x operand.Op) { ctx.VCVTQQ2PSX_BCST_Z(m, k, x) } + +// VCVTQQ2PSX_Z: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PSX.Z m128 k xmm +// VCVTQQ2PSX.Z xmm k xmm +// Construct and append a VCVTQQ2PSX.Z instruction to the active function. +func (c *Context) VCVTQQ2PSX_Z(mx, k, x operand.Op) { + c.addinstruction(x86.VCVTQQ2PSX_Z(mx, k, x)) +} + +// VCVTQQ2PSX_Z: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PSX.Z m128 k xmm +// VCVTQQ2PSX.Z xmm k xmm +// Construct and append a VCVTQQ2PSX.Z instruction to the active function. +// Operates on the global context. +func VCVTQQ2PSX_Z(mx, k, x operand.Op) { ctx.VCVTQQ2PSX_Z(mx, k, x) } + +// VCVTQQ2PSY: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VCVTQQ2PSY m256 k xmm +// VCVTQQ2PSY m256 xmm +// VCVTQQ2PSY ymm k xmm +// VCVTQQ2PSY ymm xmm +// Construct and append a VCVTQQ2PSY instruction to the active function. +func (c *Context) VCVTQQ2PSY(ops ...operand.Op) { + c.addinstruction(x86.VCVTQQ2PSY(ops...)) +} + +// VCVTQQ2PSY: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VCVTQQ2PSY m256 k xmm +// VCVTQQ2PSY m256 xmm +// VCVTQQ2PSY ymm k xmm +// VCVTQQ2PSY ymm xmm +// Construct and append a VCVTQQ2PSY instruction to the active function. +// Operates on the global context. +func VCVTQQ2PSY(ops ...operand.Op) { ctx.VCVTQQ2PSY(ops...) } + +// VCVTQQ2PSY_BCST: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCVTQQ2PSY.BCST m64 k xmm +// VCVTQQ2PSY.BCST m64 xmm +// Construct and append a VCVTQQ2PSY.BCST instruction to the active function. +func (c *Context) VCVTQQ2PSY_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTQQ2PSY_BCST(ops...)) +} + +// VCVTQQ2PSY_BCST: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCVTQQ2PSY.BCST m64 k xmm +// VCVTQQ2PSY.BCST m64 xmm +// Construct and append a VCVTQQ2PSY.BCST instruction to the active function. +// Operates on the global context. +func VCVTQQ2PSY_BCST(ops ...operand.Op) { ctx.VCVTQQ2PSY_BCST(ops...) } + +// VCVTQQ2PSY_BCST_Z: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PSY.BCST.Z m64 k xmm +// Construct and append a VCVTQQ2PSY.BCST.Z instruction to the active function. +func (c *Context) VCVTQQ2PSY_BCST_Z(m, k, x operand.Op) { + c.addinstruction(x86.VCVTQQ2PSY_BCST_Z(m, k, x)) +} + +// VCVTQQ2PSY_BCST_Z: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PSY.BCST.Z m64 k xmm +// Construct and append a VCVTQQ2PSY.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTQQ2PSY_BCST_Z(m, k, x operand.Op) { ctx.VCVTQQ2PSY_BCST_Z(m, k, x) } + +// VCVTQQ2PSY_Z: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PSY.Z m256 k xmm +// VCVTQQ2PSY.Z ymm k xmm +// Construct and append a VCVTQQ2PSY.Z instruction to the active function. +func (c *Context) VCVTQQ2PSY_Z(my, k, x operand.Op) { + c.addinstruction(x86.VCVTQQ2PSY_Z(my, k, x)) +} + +// VCVTQQ2PSY_Z: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PSY.Z m256 k xmm +// VCVTQQ2PSY.Z ymm k xmm +// Construct and append a VCVTQQ2PSY.Z instruction to the active function. +// Operates on the global context. +func VCVTQQ2PSY_Z(my, k, x operand.Op) { ctx.VCVTQQ2PSY_Z(my, k, x) } + +// VCVTQQ2PS_BCST: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCVTQQ2PS.BCST m64 k ymm +// VCVTQQ2PS.BCST m64 ymm +// Construct and append a VCVTQQ2PS.BCST instruction to the active function. +func (c *Context) VCVTQQ2PS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTQQ2PS_BCST(ops...)) +} + +// VCVTQQ2PS_BCST: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCVTQQ2PS.BCST m64 k ymm +// VCVTQQ2PS.BCST m64 ymm +// Construct and append a VCVTQQ2PS.BCST instruction to the active function. +// Operates on the global context. +func VCVTQQ2PS_BCST(ops ...operand.Op) { ctx.VCVTQQ2PS_BCST(ops...) } + +// VCVTQQ2PS_BCST_Z: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PS.BCST.Z m64 k ymm +// Construct and append a VCVTQQ2PS.BCST.Z instruction to the active function. +func (c *Context) VCVTQQ2PS_BCST_Z(m, k, y operand.Op) { + c.addinstruction(x86.VCVTQQ2PS_BCST_Z(m, k, y)) +} + +// VCVTQQ2PS_BCST_Z: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PS.BCST.Z m64 k ymm +// Construct and append a VCVTQQ2PS.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTQQ2PS_BCST_Z(m, k, y operand.Op) { ctx.VCVTQQ2PS_BCST_Z(m, k, y) } + +// VCVTQQ2PS_RD_SAE: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTQQ2PS.RD_SAE zmm k ymm +// VCVTQQ2PS.RD_SAE zmm ymm +// Construct and append a VCVTQQ2PS.RD_SAE instruction to the active function. +func (c *Context) VCVTQQ2PS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTQQ2PS_RD_SAE(ops...)) +} + +// VCVTQQ2PS_RD_SAE: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTQQ2PS.RD_SAE zmm k ymm +// VCVTQQ2PS.RD_SAE zmm ymm +// Construct and append a VCVTQQ2PS.RD_SAE instruction to the active function. +// Operates on the global context. +func VCVTQQ2PS_RD_SAE(ops ...operand.Op) { ctx.VCVTQQ2PS_RD_SAE(ops...) } + +// VCVTQQ2PS_RD_SAE_Z: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PS.RD_SAE.Z zmm k ymm +// Construct and append a VCVTQQ2PS.RD_SAE.Z instruction to the active function. +func (c *Context) VCVTQQ2PS_RD_SAE_Z(z, k, y operand.Op) { + c.addinstruction(x86.VCVTQQ2PS_RD_SAE_Z(z, k, y)) +} + +// VCVTQQ2PS_RD_SAE_Z: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PS.RD_SAE.Z zmm k ymm +// Construct and append a VCVTQQ2PS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTQQ2PS_RD_SAE_Z(z, k, y operand.Op) { ctx.VCVTQQ2PS_RD_SAE_Z(z, k, y) } + +// VCVTQQ2PS_RN_SAE: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VCVTQQ2PS.RN_SAE zmm k ymm +// VCVTQQ2PS.RN_SAE zmm ymm +// Construct and append a VCVTQQ2PS.RN_SAE instruction to the active function. +func (c *Context) VCVTQQ2PS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTQQ2PS_RN_SAE(ops...)) +} + +// VCVTQQ2PS_RN_SAE: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VCVTQQ2PS.RN_SAE zmm k ymm +// VCVTQQ2PS.RN_SAE zmm ymm +// Construct and append a VCVTQQ2PS.RN_SAE instruction to the active function. +// Operates on the global context. +func VCVTQQ2PS_RN_SAE(ops ...operand.Op) { ctx.VCVTQQ2PS_RN_SAE(ops...) } + +// VCVTQQ2PS_RN_SAE_Z: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PS.RN_SAE.Z zmm k ymm +// Construct and append a VCVTQQ2PS.RN_SAE.Z instruction to the active function. +func (c *Context) VCVTQQ2PS_RN_SAE_Z(z, k, y operand.Op) { + c.addinstruction(x86.VCVTQQ2PS_RN_SAE_Z(z, k, y)) +} + +// VCVTQQ2PS_RN_SAE_Z: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PS.RN_SAE.Z zmm k ymm +// Construct and append a VCVTQQ2PS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTQQ2PS_RN_SAE_Z(z, k, y operand.Op) { ctx.VCVTQQ2PS_RN_SAE_Z(z, k, y) } + +// VCVTQQ2PS_RU_SAE: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTQQ2PS.RU_SAE zmm k ymm +// VCVTQQ2PS.RU_SAE zmm ymm +// Construct and append a VCVTQQ2PS.RU_SAE instruction to the active function. +func (c *Context) VCVTQQ2PS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTQQ2PS_RU_SAE(ops...)) +} + +// VCVTQQ2PS_RU_SAE: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTQQ2PS.RU_SAE zmm k ymm +// VCVTQQ2PS.RU_SAE zmm ymm +// Construct and append a VCVTQQ2PS.RU_SAE instruction to the active function. +// Operates on the global context. +func VCVTQQ2PS_RU_SAE(ops ...operand.Op) { ctx.VCVTQQ2PS_RU_SAE(ops...) } + +// VCVTQQ2PS_RU_SAE_Z: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PS.RU_SAE.Z zmm k ymm +// Construct and append a VCVTQQ2PS.RU_SAE.Z instruction to the active function. +func (c *Context) VCVTQQ2PS_RU_SAE_Z(z, k, y operand.Op) { + c.addinstruction(x86.VCVTQQ2PS_RU_SAE_Z(z, k, y)) +} + +// VCVTQQ2PS_RU_SAE_Z: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PS.RU_SAE.Z zmm k ymm +// Construct and append a VCVTQQ2PS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTQQ2PS_RU_SAE_Z(z, k, y operand.Op) { ctx.VCVTQQ2PS_RU_SAE_Z(z, k, y) } + +// VCVTQQ2PS_RZ_SAE: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VCVTQQ2PS.RZ_SAE zmm k ymm +// VCVTQQ2PS.RZ_SAE zmm ymm +// Construct and append a VCVTQQ2PS.RZ_SAE instruction to the active function. +func (c *Context) VCVTQQ2PS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTQQ2PS_RZ_SAE(ops...)) +} + +// VCVTQQ2PS_RZ_SAE: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VCVTQQ2PS.RZ_SAE zmm k ymm +// VCVTQQ2PS.RZ_SAE zmm ymm +// Construct and append a VCVTQQ2PS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VCVTQQ2PS_RZ_SAE(ops ...operand.Op) { ctx.VCVTQQ2PS_RZ_SAE(ops...) } + +// VCVTQQ2PS_RZ_SAE_Z: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PS.RZ_SAE.Z zmm k ymm +// Construct and append a VCVTQQ2PS.RZ_SAE.Z instruction to the active function. +func (c *Context) VCVTQQ2PS_RZ_SAE_Z(z, k, y operand.Op) { + c.addinstruction(x86.VCVTQQ2PS_RZ_SAE_Z(z, k, y)) +} + +// VCVTQQ2PS_RZ_SAE_Z: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PS.RZ_SAE.Z zmm k ymm +// Construct and append a VCVTQQ2PS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTQQ2PS_RZ_SAE_Z(z, k, y operand.Op) { ctx.VCVTQQ2PS_RZ_SAE_Z(z, k, y) } + +// VCVTQQ2PS_Z: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PS.Z m512 k ymm +// VCVTQQ2PS.Z zmm k ymm +// Construct and append a VCVTQQ2PS.Z instruction to the active function. +func (c *Context) VCVTQQ2PS_Z(mz, k, y operand.Op) { + c.addinstruction(x86.VCVTQQ2PS_Z(mz, k, y)) +} + +// VCVTQQ2PS_Z: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PS.Z m512 k ymm +// VCVTQQ2PS.Z zmm k ymm +// Construct and append a VCVTQQ2PS.Z instruction to the active function. +// Operates on the global context. +func VCVTQQ2PS_Z(mz, k, y operand.Op) { ctx.VCVTQQ2PS_Z(mz, k, y) } + +// VCVTSD2SI: Convert Scalar Double-Precision FP Value to Integer. +// +// Forms: +// +// VCVTSD2SI m64 r32 +// VCVTSD2SI xmm r32 +// Construct and append a VCVTSD2SI instruction to the active function. +func (c *Context) VCVTSD2SI(mx, r operand.Op) { + c.addinstruction(x86.VCVTSD2SI(mx, r)) +} + +// VCVTSD2SI: Convert Scalar Double-Precision FP Value to Integer. +// +// Forms: +// +// VCVTSD2SI m64 r32 +// VCVTSD2SI xmm r32 +// Construct and append a VCVTSD2SI instruction to the active function. +// Operates on the global context. +func VCVTSD2SI(mx, r operand.Op) { ctx.VCVTSD2SI(mx, r) } + +// VCVTSD2SIQ: Convert Scalar Double-Precision FP Value to Integer. +// +// Forms: +// +// VCVTSD2SIQ m64 r64 +// VCVTSD2SIQ xmm r64 +// Construct and append a VCVTSD2SIQ instruction to the active function. +func (c *Context) VCVTSD2SIQ(mx, r operand.Op) { + c.addinstruction(x86.VCVTSD2SIQ(mx, r)) +} + +// VCVTSD2SIQ: Convert Scalar Double-Precision FP Value to Integer. +// +// Forms: +// +// VCVTSD2SIQ m64 r64 +// VCVTSD2SIQ xmm r64 +// Construct and append a VCVTSD2SIQ instruction to the active function. +// Operates on the global context. +func VCVTSD2SIQ(mx, r operand.Op) { ctx.VCVTSD2SIQ(mx, r) } + +// VCVTSD2SIQ_RD_SAE: Convert Scalar Double-Precision FP Value to Integer (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSD2SIQ.RD_SAE xmm r64 +// Construct and append a VCVTSD2SIQ.RD_SAE instruction to the active function. +func (c *Context) VCVTSD2SIQ_RD_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSD2SIQ_RD_SAE(x, r)) +} + +// VCVTSD2SIQ_RD_SAE: Convert Scalar Double-Precision FP Value to Integer (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSD2SIQ.RD_SAE xmm r64 +// Construct and append a VCVTSD2SIQ.RD_SAE instruction to the active function. +// Operates on the global context. +func VCVTSD2SIQ_RD_SAE(x, r operand.Op) { ctx.VCVTSD2SIQ_RD_SAE(x, r) } + +// VCVTSD2SIQ_RN_SAE: Convert Scalar Double-Precision FP Value to Integer (Round Towards Nearest). +// +// Forms: +// +// VCVTSD2SIQ.RN_SAE xmm r64 +// Construct and append a VCVTSD2SIQ.RN_SAE instruction to the active function. +func (c *Context) VCVTSD2SIQ_RN_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSD2SIQ_RN_SAE(x, r)) +} + +// VCVTSD2SIQ_RN_SAE: Convert Scalar Double-Precision FP Value to Integer (Round Towards Nearest). +// +// Forms: +// +// VCVTSD2SIQ.RN_SAE xmm r64 +// Construct and append a VCVTSD2SIQ.RN_SAE instruction to the active function. +// Operates on the global context. +func VCVTSD2SIQ_RN_SAE(x, r operand.Op) { ctx.VCVTSD2SIQ_RN_SAE(x, r) } + +// VCVTSD2SIQ_RU_SAE: Convert Scalar Double-Precision FP Value to Integer (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSD2SIQ.RU_SAE xmm r64 +// Construct and append a VCVTSD2SIQ.RU_SAE instruction to the active function. +func (c *Context) VCVTSD2SIQ_RU_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSD2SIQ_RU_SAE(x, r)) +} + +// VCVTSD2SIQ_RU_SAE: Convert Scalar Double-Precision FP Value to Integer (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSD2SIQ.RU_SAE xmm r64 +// Construct and append a VCVTSD2SIQ.RU_SAE instruction to the active function. +// Operates on the global context. +func VCVTSD2SIQ_RU_SAE(x, r operand.Op) { ctx.VCVTSD2SIQ_RU_SAE(x, r) } + +// VCVTSD2SIQ_RZ_SAE: Convert Scalar Double-Precision FP Value to Integer (Round Towards Zero). +// +// Forms: +// +// VCVTSD2SIQ.RZ_SAE xmm r64 +// Construct and append a VCVTSD2SIQ.RZ_SAE instruction to the active function. +func (c *Context) VCVTSD2SIQ_RZ_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSD2SIQ_RZ_SAE(x, r)) +} + +// VCVTSD2SIQ_RZ_SAE: Convert Scalar Double-Precision FP Value to Integer (Round Towards Zero). +// +// Forms: +// +// VCVTSD2SIQ.RZ_SAE xmm r64 +// Construct and append a VCVTSD2SIQ.RZ_SAE instruction to the active function. +// Operates on the global context. +func VCVTSD2SIQ_RZ_SAE(x, r operand.Op) { ctx.VCVTSD2SIQ_RZ_SAE(x, r) } + +// VCVTSD2SI_RD_SAE: Convert Scalar Double-Precision FP Value to Integer (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSD2SI.RD_SAE xmm r32 +// Construct and append a VCVTSD2SI.RD_SAE instruction to the active function. +func (c *Context) VCVTSD2SI_RD_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSD2SI_RD_SAE(x, r)) +} + +// VCVTSD2SI_RD_SAE: Convert Scalar Double-Precision FP Value to Integer (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSD2SI.RD_SAE xmm r32 +// Construct and append a VCVTSD2SI.RD_SAE instruction to the active function. +// Operates on the global context. +func VCVTSD2SI_RD_SAE(x, r operand.Op) { ctx.VCVTSD2SI_RD_SAE(x, r) } + +// VCVTSD2SI_RN_SAE: Convert Scalar Double-Precision FP Value to Integer (Round Towards Nearest). +// +// Forms: +// +// VCVTSD2SI.RN_SAE xmm r32 +// Construct and append a VCVTSD2SI.RN_SAE instruction to the active function. +func (c *Context) VCVTSD2SI_RN_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSD2SI_RN_SAE(x, r)) +} + +// VCVTSD2SI_RN_SAE: Convert Scalar Double-Precision FP Value to Integer (Round Towards Nearest). +// +// Forms: +// +// VCVTSD2SI.RN_SAE xmm r32 +// Construct and append a VCVTSD2SI.RN_SAE instruction to the active function. +// Operates on the global context. +func VCVTSD2SI_RN_SAE(x, r operand.Op) { ctx.VCVTSD2SI_RN_SAE(x, r) } + +// VCVTSD2SI_RU_SAE: Convert Scalar Double-Precision FP Value to Integer (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSD2SI.RU_SAE xmm r32 +// Construct and append a VCVTSD2SI.RU_SAE instruction to the active function. +func (c *Context) VCVTSD2SI_RU_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSD2SI_RU_SAE(x, r)) +} + +// VCVTSD2SI_RU_SAE: Convert Scalar Double-Precision FP Value to Integer (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSD2SI.RU_SAE xmm r32 +// Construct and append a VCVTSD2SI.RU_SAE instruction to the active function. +// Operates on the global context. +func VCVTSD2SI_RU_SAE(x, r operand.Op) { ctx.VCVTSD2SI_RU_SAE(x, r) } + +// VCVTSD2SI_RZ_SAE: Convert Scalar Double-Precision FP Value to Integer (Round Towards Zero). +// +// Forms: +// +// VCVTSD2SI.RZ_SAE xmm r32 +// Construct and append a VCVTSD2SI.RZ_SAE instruction to the active function. +func (c *Context) VCVTSD2SI_RZ_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSD2SI_RZ_SAE(x, r)) +} + +// VCVTSD2SI_RZ_SAE: Convert Scalar Double-Precision FP Value to Integer (Round Towards Zero). +// +// Forms: +// +// VCVTSD2SI.RZ_SAE xmm r32 +// Construct and append a VCVTSD2SI.RZ_SAE instruction to the active function. +// Operates on the global context. +func VCVTSD2SI_RZ_SAE(x, r operand.Op) { ctx.VCVTSD2SI_RZ_SAE(x, r) } + +// VCVTSD2SS: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value. +// +// Forms: +// +// VCVTSD2SS m64 xmm xmm +// VCVTSD2SS xmm xmm xmm +// VCVTSD2SS m64 xmm k xmm +// VCVTSD2SS xmm xmm k xmm +// Construct and append a VCVTSD2SS instruction to the active function. +func (c *Context) VCVTSD2SS(ops ...operand.Op) { + c.addinstruction(x86.VCVTSD2SS(ops...)) +} + +// VCVTSD2SS: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value. +// +// Forms: +// +// VCVTSD2SS m64 xmm xmm +// VCVTSD2SS xmm xmm xmm +// VCVTSD2SS m64 xmm k xmm +// VCVTSD2SS xmm xmm k xmm +// Construct and append a VCVTSD2SS instruction to the active function. +// Operates on the global context. +func VCVTSD2SS(ops ...operand.Op) { ctx.VCVTSD2SS(ops...) } + +// VCVTSD2SS_RD_SAE: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSD2SS.RD_SAE xmm xmm k xmm +// VCVTSD2SS.RD_SAE xmm xmm xmm +// Construct and append a VCVTSD2SS.RD_SAE instruction to the active function. +func (c *Context) VCVTSD2SS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTSD2SS_RD_SAE(ops...)) +} + +// VCVTSD2SS_RD_SAE: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSD2SS.RD_SAE xmm xmm k xmm +// VCVTSD2SS.RD_SAE xmm xmm xmm +// Construct and append a VCVTSD2SS.RD_SAE instruction to the active function. +// Operates on the global context. +func VCVTSD2SS_RD_SAE(ops ...operand.Op) { ctx.VCVTSD2SS_RD_SAE(ops...) } + +// VCVTSD2SS_RD_SAE_Z: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTSD2SS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VCVTSD2SS.RD_SAE.Z instruction to the active function. +func (c *Context) VCVTSD2SS_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VCVTSD2SS_RD_SAE_Z(x, x1, k, x2)) +} + +// VCVTSD2SS_RD_SAE_Z: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTSD2SS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VCVTSD2SS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTSD2SS_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VCVTSD2SS_RD_SAE_Z(x, x1, k, x2) } + +// VCVTSD2SS_RN_SAE: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value (Round Towards Nearest). +// +// Forms: +// +// VCVTSD2SS.RN_SAE xmm xmm k xmm +// VCVTSD2SS.RN_SAE xmm xmm xmm +// Construct and append a VCVTSD2SS.RN_SAE instruction to the active function. +func (c *Context) VCVTSD2SS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTSD2SS_RN_SAE(ops...)) +} + +// VCVTSD2SS_RN_SAE: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value (Round Towards Nearest). +// +// Forms: +// +// VCVTSD2SS.RN_SAE xmm xmm k xmm +// VCVTSD2SS.RN_SAE xmm xmm xmm +// Construct and append a VCVTSD2SS.RN_SAE instruction to the active function. +// Operates on the global context. +func VCVTSD2SS_RN_SAE(ops ...operand.Op) { ctx.VCVTSD2SS_RN_SAE(ops...) } + +// VCVTSD2SS_RN_SAE_Z: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTSD2SS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VCVTSD2SS.RN_SAE.Z instruction to the active function. +func (c *Context) VCVTSD2SS_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VCVTSD2SS_RN_SAE_Z(x, x1, k, x2)) +} + +// VCVTSD2SS_RN_SAE_Z: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTSD2SS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VCVTSD2SS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTSD2SS_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VCVTSD2SS_RN_SAE_Z(x, x1, k, x2) } + +// VCVTSD2SS_RU_SAE: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSD2SS.RU_SAE xmm xmm k xmm +// VCVTSD2SS.RU_SAE xmm xmm xmm +// Construct and append a VCVTSD2SS.RU_SAE instruction to the active function. +func (c *Context) VCVTSD2SS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTSD2SS_RU_SAE(ops...)) +} + +// VCVTSD2SS_RU_SAE: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSD2SS.RU_SAE xmm xmm k xmm +// VCVTSD2SS.RU_SAE xmm xmm xmm +// Construct and append a VCVTSD2SS.RU_SAE instruction to the active function. +// Operates on the global context. +func VCVTSD2SS_RU_SAE(ops ...operand.Op) { ctx.VCVTSD2SS_RU_SAE(ops...) } + +// VCVTSD2SS_RU_SAE_Z: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTSD2SS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VCVTSD2SS.RU_SAE.Z instruction to the active function. +func (c *Context) VCVTSD2SS_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VCVTSD2SS_RU_SAE_Z(x, x1, k, x2)) +} + +// VCVTSD2SS_RU_SAE_Z: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTSD2SS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VCVTSD2SS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTSD2SS_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VCVTSD2SS_RU_SAE_Z(x, x1, k, x2) } + +// VCVTSD2SS_RZ_SAE: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value (Round Towards Zero). +// +// Forms: +// +// VCVTSD2SS.RZ_SAE xmm xmm k xmm +// VCVTSD2SS.RZ_SAE xmm xmm xmm +// Construct and append a VCVTSD2SS.RZ_SAE instruction to the active function. +func (c *Context) VCVTSD2SS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTSD2SS_RZ_SAE(ops...)) +} + +// VCVTSD2SS_RZ_SAE: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value (Round Towards Zero). +// +// Forms: +// +// VCVTSD2SS.RZ_SAE xmm xmm k xmm +// VCVTSD2SS.RZ_SAE xmm xmm xmm +// Construct and append a VCVTSD2SS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VCVTSD2SS_RZ_SAE(ops ...operand.Op) { ctx.VCVTSD2SS_RZ_SAE(ops...) } + +// VCVTSD2SS_RZ_SAE_Z: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTSD2SS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VCVTSD2SS.RZ_SAE.Z instruction to the active function. +func (c *Context) VCVTSD2SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VCVTSD2SS_RZ_SAE_Z(x, x1, k, x2)) +} + +// VCVTSD2SS_RZ_SAE_Z: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTSD2SS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VCVTSD2SS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTSD2SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VCVTSD2SS_RZ_SAE_Z(x, x1, k, x2) } + +// VCVTSD2SS_Z: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value (Zeroing Masking). +// +// Forms: +// +// VCVTSD2SS.Z m64 xmm k xmm +// VCVTSD2SS.Z xmm xmm k xmm +// Construct and append a VCVTSD2SS.Z instruction to the active function. +func (c *Context) VCVTSD2SS_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VCVTSD2SS_Z(mx, x, k, x1)) +} + +// VCVTSD2SS_Z: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value (Zeroing Masking). +// +// Forms: +// +// VCVTSD2SS.Z m64 xmm k xmm +// VCVTSD2SS.Z xmm xmm k xmm +// Construct and append a VCVTSD2SS.Z instruction to the active function. +// Operates on the global context. +func VCVTSD2SS_Z(mx, x, k, x1 operand.Op) { ctx.VCVTSD2SS_Z(mx, x, k, x1) } + +// VCVTSD2USIL: Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer. +// +// Forms: +// +// VCVTSD2USIL m64 r32 +// VCVTSD2USIL xmm r32 +// Construct and append a VCVTSD2USIL instruction to the active function. +func (c *Context) VCVTSD2USIL(mx, r operand.Op) { + c.addinstruction(x86.VCVTSD2USIL(mx, r)) +} + +// VCVTSD2USIL: Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer. +// +// Forms: +// +// VCVTSD2USIL m64 r32 +// VCVTSD2USIL xmm r32 +// Construct and append a VCVTSD2USIL instruction to the active function. +// Operates on the global context. +func VCVTSD2USIL(mx, r operand.Op) { ctx.VCVTSD2USIL(mx, r) } + +// VCVTSD2USIL_RD_SAE: Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSD2USIL.RD_SAE xmm r32 +// Construct and append a VCVTSD2USIL.RD_SAE instruction to the active function. +func (c *Context) VCVTSD2USIL_RD_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSD2USIL_RD_SAE(x, r)) +} + +// VCVTSD2USIL_RD_SAE: Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSD2USIL.RD_SAE xmm r32 +// Construct and append a VCVTSD2USIL.RD_SAE instruction to the active function. +// Operates on the global context. +func VCVTSD2USIL_RD_SAE(x, r operand.Op) { ctx.VCVTSD2USIL_RD_SAE(x, r) } + +// VCVTSD2USIL_RN_SAE: Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Nearest). +// +// Forms: +// +// VCVTSD2USIL.RN_SAE xmm r32 +// Construct and append a VCVTSD2USIL.RN_SAE instruction to the active function. +func (c *Context) VCVTSD2USIL_RN_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSD2USIL_RN_SAE(x, r)) +} + +// VCVTSD2USIL_RN_SAE: Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Nearest). +// +// Forms: +// +// VCVTSD2USIL.RN_SAE xmm r32 +// Construct and append a VCVTSD2USIL.RN_SAE instruction to the active function. +// Operates on the global context. +func VCVTSD2USIL_RN_SAE(x, r operand.Op) { ctx.VCVTSD2USIL_RN_SAE(x, r) } + +// VCVTSD2USIL_RU_SAE: Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSD2USIL.RU_SAE xmm r32 +// Construct and append a VCVTSD2USIL.RU_SAE instruction to the active function. +func (c *Context) VCVTSD2USIL_RU_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSD2USIL_RU_SAE(x, r)) +} + +// VCVTSD2USIL_RU_SAE: Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSD2USIL.RU_SAE xmm r32 +// Construct and append a VCVTSD2USIL.RU_SAE instruction to the active function. +// Operates on the global context. +func VCVTSD2USIL_RU_SAE(x, r operand.Op) { ctx.VCVTSD2USIL_RU_SAE(x, r) } + +// VCVTSD2USIL_RZ_SAE: Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Zero). +// +// Forms: +// +// VCVTSD2USIL.RZ_SAE xmm r32 +// Construct and append a VCVTSD2USIL.RZ_SAE instruction to the active function. +func (c *Context) VCVTSD2USIL_RZ_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSD2USIL_RZ_SAE(x, r)) +} + +// VCVTSD2USIL_RZ_SAE: Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Zero). +// +// Forms: +// +// VCVTSD2USIL.RZ_SAE xmm r32 +// Construct and append a VCVTSD2USIL.RZ_SAE instruction to the active function. +// Operates on the global context. +func VCVTSD2USIL_RZ_SAE(x, r operand.Op) { ctx.VCVTSD2USIL_RZ_SAE(x, r) } + +// VCVTSD2USIQ: Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer. +// +// Forms: +// +// VCVTSD2USIQ m64 r64 +// VCVTSD2USIQ xmm r64 +// Construct and append a VCVTSD2USIQ instruction to the active function. +func (c *Context) VCVTSD2USIQ(mx, r operand.Op) { + c.addinstruction(x86.VCVTSD2USIQ(mx, r)) +} + +// VCVTSD2USIQ: Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer. +// +// Forms: +// +// VCVTSD2USIQ m64 r64 +// VCVTSD2USIQ xmm r64 +// Construct and append a VCVTSD2USIQ instruction to the active function. +// Operates on the global context. +func VCVTSD2USIQ(mx, r operand.Op) { ctx.VCVTSD2USIQ(mx, r) } + +// VCVTSD2USIQ_RD_SAE: Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSD2USIQ.RD_SAE xmm r64 +// Construct and append a VCVTSD2USIQ.RD_SAE instruction to the active function. +func (c *Context) VCVTSD2USIQ_RD_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSD2USIQ_RD_SAE(x, r)) +} + +// VCVTSD2USIQ_RD_SAE: Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSD2USIQ.RD_SAE xmm r64 +// Construct and append a VCVTSD2USIQ.RD_SAE instruction to the active function. +// Operates on the global context. +func VCVTSD2USIQ_RD_SAE(x, r operand.Op) { ctx.VCVTSD2USIQ_RD_SAE(x, r) } + +// VCVTSD2USIQ_RN_SAE: Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Nearest). +// +// Forms: +// +// VCVTSD2USIQ.RN_SAE xmm r64 +// Construct and append a VCVTSD2USIQ.RN_SAE instruction to the active function. +func (c *Context) VCVTSD2USIQ_RN_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSD2USIQ_RN_SAE(x, r)) +} + +// VCVTSD2USIQ_RN_SAE: Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Nearest). +// +// Forms: +// +// VCVTSD2USIQ.RN_SAE xmm r64 +// Construct and append a VCVTSD2USIQ.RN_SAE instruction to the active function. +// Operates on the global context. +func VCVTSD2USIQ_RN_SAE(x, r operand.Op) { ctx.VCVTSD2USIQ_RN_SAE(x, r) } + +// VCVTSD2USIQ_RU_SAE: Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSD2USIQ.RU_SAE xmm r64 +// Construct and append a VCVTSD2USIQ.RU_SAE instruction to the active function. +func (c *Context) VCVTSD2USIQ_RU_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSD2USIQ_RU_SAE(x, r)) +} + +// VCVTSD2USIQ_RU_SAE: Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSD2USIQ.RU_SAE xmm r64 +// Construct and append a VCVTSD2USIQ.RU_SAE instruction to the active function. +// Operates on the global context. +func VCVTSD2USIQ_RU_SAE(x, r operand.Op) { ctx.VCVTSD2USIQ_RU_SAE(x, r) } + +// VCVTSD2USIQ_RZ_SAE: Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Zero). +// +// Forms: +// +// VCVTSD2USIQ.RZ_SAE xmm r64 +// Construct and append a VCVTSD2USIQ.RZ_SAE instruction to the active function. +func (c *Context) VCVTSD2USIQ_RZ_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSD2USIQ_RZ_SAE(x, r)) +} + +// VCVTSD2USIQ_RZ_SAE: Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Zero). +// +// Forms: +// +// VCVTSD2USIQ.RZ_SAE xmm r64 +// Construct and append a VCVTSD2USIQ.RZ_SAE instruction to the active function. +// Operates on the global context. +func VCVTSD2USIQ_RZ_SAE(x, r operand.Op) { ctx.VCVTSD2USIQ_RZ_SAE(x, r) } + +// VCVTSI2SDL: Convert Dword Integer to Scalar Double-Precision FP Value. +// +// Forms: +// +// VCVTSI2SDL m32 xmm xmm +// VCVTSI2SDL r32 xmm xmm +// Construct and append a VCVTSI2SDL instruction to the active function. +func (c *Context) VCVTSI2SDL(mr, x, x1 operand.Op) { + c.addinstruction(x86.VCVTSI2SDL(mr, x, x1)) +} + +// VCVTSI2SDL: Convert Dword Integer to Scalar Double-Precision FP Value. +// +// Forms: +// +// VCVTSI2SDL m32 xmm xmm +// VCVTSI2SDL r32 xmm xmm +// Construct and append a VCVTSI2SDL instruction to the active function. +// Operates on the global context. +func VCVTSI2SDL(mr, x, x1 operand.Op) { ctx.VCVTSI2SDL(mr, x, x1) } + +// VCVTSI2SDQ: Convert Dword Integer to Scalar Double-Precision FP Value. +// +// Forms: +// +// VCVTSI2SDQ m64 xmm xmm +// VCVTSI2SDQ r64 xmm xmm +// Construct and append a VCVTSI2SDQ instruction to the active function. +func (c *Context) VCVTSI2SDQ(mr, x, x1 operand.Op) { + c.addinstruction(x86.VCVTSI2SDQ(mr, x, x1)) +} + +// VCVTSI2SDQ: Convert Dword Integer to Scalar Double-Precision FP Value. +// +// Forms: +// +// VCVTSI2SDQ m64 xmm xmm +// VCVTSI2SDQ r64 xmm xmm +// Construct and append a VCVTSI2SDQ instruction to the active function. +// Operates on the global context. +func VCVTSI2SDQ(mr, x, x1 operand.Op) { ctx.VCVTSI2SDQ(mr, x, x1) } + +// VCVTSI2SDQ_RD_SAE: Convert Dword Integer to Scalar Double-Precision FP Value (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSI2SDQ.RD_SAE r64 xmm xmm +// Construct and append a VCVTSI2SDQ.RD_SAE instruction to the active function. +func (c *Context) VCVTSI2SDQ_RD_SAE(r, x, x1 operand.Op) { + c.addinstruction(x86.VCVTSI2SDQ_RD_SAE(r, x, x1)) +} + +// VCVTSI2SDQ_RD_SAE: Convert Dword Integer to Scalar Double-Precision FP Value (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSI2SDQ.RD_SAE r64 xmm xmm +// Construct and append a VCVTSI2SDQ.RD_SAE instruction to the active function. +// Operates on the global context. +func VCVTSI2SDQ_RD_SAE(r, x, x1 operand.Op) { ctx.VCVTSI2SDQ_RD_SAE(r, x, x1) } + +// VCVTSI2SDQ_RN_SAE: Convert Dword Integer to Scalar Double-Precision FP Value (Round Towards Nearest). +// +// Forms: +// +// VCVTSI2SDQ.RN_SAE r64 xmm xmm +// Construct and append a VCVTSI2SDQ.RN_SAE instruction to the active function. +func (c *Context) VCVTSI2SDQ_RN_SAE(r, x, x1 operand.Op) { + c.addinstruction(x86.VCVTSI2SDQ_RN_SAE(r, x, x1)) +} + +// VCVTSI2SDQ_RN_SAE: Convert Dword Integer to Scalar Double-Precision FP Value (Round Towards Nearest). +// +// Forms: +// +// VCVTSI2SDQ.RN_SAE r64 xmm xmm +// Construct and append a VCVTSI2SDQ.RN_SAE instruction to the active function. +// Operates on the global context. +func VCVTSI2SDQ_RN_SAE(r, x, x1 operand.Op) { ctx.VCVTSI2SDQ_RN_SAE(r, x, x1) } + +// VCVTSI2SDQ_RU_SAE: Convert Dword Integer to Scalar Double-Precision FP Value (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSI2SDQ.RU_SAE r64 xmm xmm +// Construct and append a VCVTSI2SDQ.RU_SAE instruction to the active function. +func (c *Context) VCVTSI2SDQ_RU_SAE(r, x, x1 operand.Op) { + c.addinstruction(x86.VCVTSI2SDQ_RU_SAE(r, x, x1)) +} + +// VCVTSI2SDQ_RU_SAE: Convert Dword Integer to Scalar Double-Precision FP Value (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSI2SDQ.RU_SAE r64 xmm xmm +// Construct and append a VCVTSI2SDQ.RU_SAE instruction to the active function. +// Operates on the global context. +func VCVTSI2SDQ_RU_SAE(r, x, x1 operand.Op) { ctx.VCVTSI2SDQ_RU_SAE(r, x, x1) } + +// VCVTSI2SDQ_RZ_SAE: Convert Dword Integer to Scalar Double-Precision FP Value (Round Towards Zero). +// +// Forms: +// +// VCVTSI2SDQ.RZ_SAE r64 xmm xmm +// Construct and append a VCVTSI2SDQ.RZ_SAE instruction to the active function. +func (c *Context) VCVTSI2SDQ_RZ_SAE(r, x, x1 operand.Op) { + c.addinstruction(x86.VCVTSI2SDQ_RZ_SAE(r, x, x1)) +} + +// VCVTSI2SDQ_RZ_SAE: Convert Dword Integer to Scalar Double-Precision FP Value (Round Towards Zero). +// +// Forms: +// +// VCVTSI2SDQ.RZ_SAE r64 xmm xmm +// Construct and append a VCVTSI2SDQ.RZ_SAE instruction to the active function. +// Operates on the global context. +func VCVTSI2SDQ_RZ_SAE(r, x, x1 operand.Op) { ctx.VCVTSI2SDQ_RZ_SAE(r, x, x1) } + +// VCVTSI2SSL: Convert Dword Integer to Scalar Single-Precision FP Value. +// +// Forms: +// +// VCVTSI2SSL m32 xmm xmm +// VCVTSI2SSL r32 xmm xmm +// Construct and append a VCVTSI2SSL instruction to the active function. +func (c *Context) VCVTSI2SSL(mr, x, x1 operand.Op) { + c.addinstruction(x86.VCVTSI2SSL(mr, x, x1)) +} + +// VCVTSI2SSL: Convert Dword Integer to Scalar Single-Precision FP Value. +// +// Forms: +// +// VCVTSI2SSL m32 xmm xmm +// VCVTSI2SSL r32 xmm xmm +// Construct and append a VCVTSI2SSL instruction to the active function. +// Operates on the global context. +func VCVTSI2SSL(mr, x, x1 operand.Op) { ctx.VCVTSI2SSL(mr, x, x1) } + +// VCVTSI2SSL_RD_SAE: Convert Dword Integer to Scalar Single-Precision FP Value (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSI2SSL.RD_SAE r32 xmm xmm +// Construct and append a VCVTSI2SSL.RD_SAE instruction to the active function. +func (c *Context) VCVTSI2SSL_RD_SAE(r, x, x1 operand.Op) { + c.addinstruction(x86.VCVTSI2SSL_RD_SAE(r, x, x1)) +} + +// VCVTSI2SSL_RD_SAE: Convert Dword Integer to Scalar Single-Precision FP Value (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSI2SSL.RD_SAE r32 xmm xmm +// Construct and append a VCVTSI2SSL.RD_SAE instruction to the active function. +// Operates on the global context. +func VCVTSI2SSL_RD_SAE(r, x, x1 operand.Op) { ctx.VCVTSI2SSL_RD_SAE(r, x, x1) } + +// VCVTSI2SSL_RN_SAE: Convert Dword Integer to Scalar Single-Precision FP Value (Round Towards Nearest). +// +// Forms: +// +// VCVTSI2SSL.RN_SAE r32 xmm xmm +// Construct and append a VCVTSI2SSL.RN_SAE instruction to the active function. +func (c *Context) VCVTSI2SSL_RN_SAE(r, x, x1 operand.Op) { + c.addinstruction(x86.VCVTSI2SSL_RN_SAE(r, x, x1)) +} + +// VCVTSI2SSL_RN_SAE: Convert Dword Integer to Scalar Single-Precision FP Value (Round Towards Nearest). +// +// Forms: +// +// VCVTSI2SSL.RN_SAE r32 xmm xmm +// Construct and append a VCVTSI2SSL.RN_SAE instruction to the active function. +// Operates on the global context. +func VCVTSI2SSL_RN_SAE(r, x, x1 operand.Op) { ctx.VCVTSI2SSL_RN_SAE(r, x, x1) } + +// VCVTSI2SSL_RU_SAE: Convert Dword Integer to Scalar Single-Precision FP Value (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSI2SSL.RU_SAE r32 xmm xmm +// Construct and append a VCVTSI2SSL.RU_SAE instruction to the active function. +func (c *Context) VCVTSI2SSL_RU_SAE(r, x, x1 operand.Op) { + c.addinstruction(x86.VCVTSI2SSL_RU_SAE(r, x, x1)) +} + +// VCVTSI2SSL_RU_SAE: Convert Dword Integer to Scalar Single-Precision FP Value (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSI2SSL.RU_SAE r32 xmm xmm +// Construct and append a VCVTSI2SSL.RU_SAE instruction to the active function. +// Operates on the global context. +func VCVTSI2SSL_RU_SAE(r, x, x1 operand.Op) { ctx.VCVTSI2SSL_RU_SAE(r, x, x1) } + +// VCVTSI2SSL_RZ_SAE: Convert Dword Integer to Scalar Single-Precision FP Value (Round Towards Zero). +// +// Forms: +// +// VCVTSI2SSL.RZ_SAE r32 xmm xmm +// Construct and append a VCVTSI2SSL.RZ_SAE instruction to the active function. +func (c *Context) VCVTSI2SSL_RZ_SAE(r, x, x1 operand.Op) { + c.addinstruction(x86.VCVTSI2SSL_RZ_SAE(r, x, x1)) +} + +// VCVTSI2SSL_RZ_SAE: Convert Dword Integer to Scalar Single-Precision FP Value (Round Towards Zero). +// +// Forms: +// +// VCVTSI2SSL.RZ_SAE r32 xmm xmm +// Construct and append a VCVTSI2SSL.RZ_SAE instruction to the active function. +// Operates on the global context. +func VCVTSI2SSL_RZ_SAE(r, x, x1 operand.Op) { ctx.VCVTSI2SSL_RZ_SAE(r, x, x1) } + +// VCVTSI2SSQ: Convert Dword Integer to Scalar Single-Precision FP Value. +// +// Forms: +// +// VCVTSI2SSQ m64 xmm xmm +// VCVTSI2SSQ r64 xmm xmm +// Construct and append a VCVTSI2SSQ instruction to the active function. +func (c *Context) VCVTSI2SSQ(mr, x, x1 operand.Op) { + c.addinstruction(x86.VCVTSI2SSQ(mr, x, x1)) +} + +// VCVTSI2SSQ: Convert Dword Integer to Scalar Single-Precision FP Value. +// +// Forms: +// +// VCVTSI2SSQ m64 xmm xmm +// VCVTSI2SSQ r64 xmm xmm +// Construct and append a VCVTSI2SSQ instruction to the active function. +// Operates on the global context. +func VCVTSI2SSQ(mr, x, x1 operand.Op) { ctx.VCVTSI2SSQ(mr, x, x1) } + +// VCVTSI2SSQ_RD_SAE: Convert Dword Integer to Scalar Single-Precision FP Value (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSI2SSQ.RD_SAE r64 xmm xmm +// Construct and append a VCVTSI2SSQ.RD_SAE instruction to the active function. +func (c *Context) VCVTSI2SSQ_RD_SAE(r, x, x1 operand.Op) { + c.addinstruction(x86.VCVTSI2SSQ_RD_SAE(r, x, x1)) +} + +// VCVTSI2SSQ_RD_SAE: Convert Dword Integer to Scalar Single-Precision FP Value (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSI2SSQ.RD_SAE r64 xmm xmm +// Construct and append a VCVTSI2SSQ.RD_SAE instruction to the active function. +// Operates on the global context. +func VCVTSI2SSQ_RD_SAE(r, x, x1 operand.Op) { ctx.VCVTSI2SSQ_RD_SAE(r, x, x1) } + +// VCVTSI2SSQ_RN_SAE: Convert Dword Integer to Scalar Single-Precision FP Value (Round Towards Nearest). +// +// Forms: +// +// VCVTSI2SSQ.RN_SAE r64 xmm xmm +// Construct and append a VCVTSI2SSQ.RN_SAE instruction to the active function. +func (c *Context) VCVTSI2SSQ_RN_SAE(r, x, x1 operand.Op) { + c.addinstruction(x86.VCVTSI2SSQ_RN_SAE(r, x, x1)) +} + +// VCVTSI2SSQ_RN_SAE: Convert Dword Integer to Scalar Single-Precision FP Value (Round Towards Nearest). +// +// Forms: +// +// VCVTSI2SSQ.RN_SAE r64 xmm xmm +// Construct and append a VCVTSI2SSQ.RN_SAE instruction to the active function. +// Operates on the global context. +func VCVTSI2SSQ_RN_SAE(r, x, x1 operand.Op) { ctx.VCVTSI2SSQ_RN_SAE(r, x, x1) } + +// VCVTSI2SSQ_RU_SAE: Convert Dword Integer to Scalar Single-Precision FP Value (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSI2SSQ.RU_SAE r64 xmm xmm +// Construct and append a VCVTSI2SSQ.RU_SAE instruction to the active function. +func (c *Context) VCVTSI2SSQ_RU_SAE(r, x, x1 operand.Op) { + c.addinstruction(x86.VCVTSI2SSQ_RU_SAE(r, x, x1)) +} + +// VCVTSI2SSQ_RU_SAE: Convert Dword Integer to Scalar Single-Precision FP Value (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSI2SSQ.RU_SAE r64 xmm xmm +// Construct and append a VCVTSI2SSQ.RU_SAE instruction to the active function. +// Operates on the global context. +func VCVTSI2SSQ_RU_SAE(r, x, x1 operand.Op) { ctx.VCVTSI2SSQ_RU_SAE(r, x, x1) } + +// VCVTSI2SSQ_RZ_SAE: Convert Dword Integer to Scalar Single-Precision FP Value (Round Towards Zero). +// +// Forms: +// +// VCVTSI2SSQ.RZ_SAE r64 xmm xmm +// Construct and append a VCVTSI2SSQ.RZ_SAE instruction to the active function. +func (c *Context) VCVTSI2SSQ_RZ_SAE(r, x, x1 operand.Op) { + c.addinstruction(x86.VCVTSI2SSQ_RZ_SAE(r, x, x1)) +} + +// VCVTSI2SSQ_RZ_SAE: Convert Dword Integer to Scalar Single-Precision FP Value (Round Towards Zero). +// +// Forms: +// +// VCVTSI2SSQ.RZ_SAE r64 xmm xmm +// Construct and append a VCVTSI2SSQ.RZ_SAE instruction to the active function. +// Operates on the global context. +func VCVTSI2SSQ_RZ_SAE(r, x, x1 operand.Op) { ctx.VCVTSI2SSQ_RZ_SAE(r, x, x1) } + +// VCVTSS2SD: Convert Scalar Single-Precision FP Value to Scalar Double-Precision FP Value. +// +// Forms: +// +// VCVTSS2SD m32 xmm xmm +// VCVTSS2SD xmm xmm xmm +// VCVTSS2SD m32 xmm k xmm +// VCVTSS2SD xmm xmm k xmm +// Construct and append a VCVTSS2SD instruction to the active function. +func (c *Context) VCVTSS2SD(ops ...operand.Op) { + c.addinstruction(x86.VCVTSS2SD(ops...)) +} + +// VCVTSS2SD: Convert Scalar Single-Precision FP Value to Scalar Double-Precision FP Value. +// +// Forms: +// +// VCVTSS2SD m32 xmm xmm +// VCVTSS2SD xmm xmm xmm +// VCVTSS2SD m32 xmm k xmm +// VCVTSS2SD xmm xmm k xmm +// Construct and append a VCVTSS2SD instruction to the active function. +// Operates on the global context. +func VCVTSS2SD(ops ...operand.Op) { ctx.VCVTSS2SD(ops...) } + +// VCVTSS2SD_SAE: Convert Scalar Single-Precision FP Value to Scalar Double-Precision FP Value (Suppress All Exceptions). +// +// Forms: +// +// VCVTSS2SD.SAE xmm xmm k xmm +// VCVTSS2SD.SAE xmm xmm xmm +// Construct and append a VCVTSS2SD.SAE instruction to the active function. +func (c *Context) VCVTSS2SD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTSS2SD_SAE(ops...)) +} + +// VCVTSS2SD_SAE: Convert Scalar Single-Precision FP Value to Scalar Double-Precision FP Value (Suppress All Exceptions). +// +// Forms: +// +// VCVTSS2SD.SAE xmm xmm k xmm +// VCVTSS2SD.SAE xmm xmm xmm +// Construct and append a VCVTSS2SD.SAE instruction to the active function. +// Operates on the global context. +func VCVTSS2SD_SAE(ops ...operand.Op) { ctx.VCVTSS2SD_SAE(ops...) } + +// VCVTSS2SD_SAE_Z: Convert Scalar Single-Precision FP Value to Scalar Double-Precision FP Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTSS2SD.SAE.Z xmm xmm k xmm +// Construct and append a VCVTSS2SD.SAE.Z instruction to the active function. +func (c *Context) VCVTSS2SD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VCVTSS2SD_SAE_Z(x, x1, k, x2)) +} + +// VCVTSS2SD_SAE_Z: Convert Scalar Single-Precision FP Value to Scalar Double-Precision FP Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTSS2SD.SAE.Z xmm xmm k xmm +// Construct and append a VCVTSS2SD.SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTSS2SD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VCVTSS2SD_SAE_Z(x, x1, k, x2) } + +// VCVTSS2SD_Z: Convert Scalar Single-Precision FP Value to Scalar Double-Precision FP Value (Zeroing Masking). +// +// Forms: +// +// VCVTSS2SD.Z m32 xmm k xmm +// VCVTSS2SD.Z xmm xmm k xmm +// Construct and append a VCVTSS2SD.Z instruction to the active function. +func (c *Context) VCVTSS2SD_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VCVTSS2SD_Z(mx, x, k, x1)) +} + +// VCVTSS2SD_Z: Convert Scalar Single-Precision FP Value to Scalar Double-Precision FP Value (Zeroing Masking). +// +// Forms: +// +// VCVTSS2SD.Z m32 xmm k xmm +// VCVTSS2SD.Z xmm xmm k xmm +// Construct and append a VCVTSS2SD.Z instruction to the active function. +// Operates on the global context. +func VCVTSS2SD_Z(mx, x, k, x1 operand.Op) { ctx.VCVTSS2SD_Z(mx, x, k, x1) } + +// VCVTSS2SI: Convert Scalar Single-Precision FP Value to Dword Integer. +// +// Forms: +// +// VCVTSS2SI m32 r32 +// VCVTSS2SI xmm r32 +// Construct and append a VCVTSS2SI instruction to the active function. +func (c *Context) VCVTSS2SI(mx, r operand.Op) { + c.addinstruction(x86.VCVTSS2SI(mx, r)) +} + +// VCVTSS2SI: Convert Scalar Single-Precision FP Value to Dword Integer. +// +// Forms: +// +// VCVTSS2SI m32 r32 +// VCVTSS2SI xmm r32 +// Construct and append a VCVTSS2SI instruction to the active function. +// Operates on the global context. +func VCVTSS2SI(mx, r operand.Op) { ctx.VCVTSS2SI(mx, r) } + +// VCVTSS2SIQ: Convert Scalar Single-Precision FP Value to Dword Integer. +// +// Forms: +// +// VCVTSS2SIQ m32 r64 +// VCVTSS2SIQ xmm r64 +// Construct and append a VCVTSS2SIQ instruction to the active function. +func (c *Context) VCVTSS2SIQ(mx, r operand.Op) { + c.addinstruction(x86.VCVTSS2SIQ(mx, r)) +} + +// VCVTSS2SIQ: Convert Scalar Single-Precision FP Value to Dword Integer. +// +// Forms: +// +// VCVTSS2SIQ m32 r64 +// VCVTSS2SIQ xmm r64 +// Construct and append a VCVTSS2SIQ instruction to the active function. +// Operates on the global context. +func VCVTSS2SIQ(mx, r operand.Op) { ctx.VCVTSS2SIQ(mx, r) } + +// VCVTSS2SIQ_RD_SAE: Convert Scalar Single-Precision FP Value to Dword Integer (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSS2SIQ.RD_SAE xmm r64 +// Construct and append a VCVTSS2SIQ.RD_SAE instruction to the active function. +func (c *Context) VCVTSS2SIQ_RD_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSS2SIQ_RD_SAE(x, r)) +} + +// VCVTSS2SIQ_RD_SAE: Convert Scalar Single-Precision FP Value to Dword Integer (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSS2SIQ.RD_SAE xmm r64 +// Construct and append a VCVTSS2SIQ.RD_SAE instruction to the active function. +// Operates on the global context. +func VCVTSS2SIQ_RD_SAE(x, r operand.Op) { ctx.VCVTSS2SIQ_RD_SAE(x, r) } + +// VCVTSS2SIQ_RN_SAE: Convert Scalar Single-Precision FP Value to Dword Integer (Round Towards Nearest). +// +// Forms: +// +// VCVTSS2SIQ.RN_SAE xmm r64 +// Construct and append a VCVTSS2SIQ.RN_SAE instruction to the active function. +func (c *Context) VCVTSS2SIQ_RN_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSS2SIQ_RN_SAE(x, r)) +} + +// VCVTSS2SIQ_RN_SAE: Convert Scalar Single-Precision FP Value to Dword Integer (Round Towards Nearest). +// +// Forms: +// +// VCVTSS2SIQ.RN_SAE xmm r64 +// Construct and append a VCVTSS2SIQ.RN_SAE instruction to the active function. +// Operates on the global context. +func VCVTSS2SIQ_RN_SAE(x, r operand.Op) { ctx.VCVTSS2SIQ_RN_SAE(x, r) } + +// VCVTSS2SIQ_RU_SAE: Convert Scalar Single-Precision FP Value to Dword Integer (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSS2SIQ.RU_SAE xmm r64 +// Construct and append a VCVTSS2SIQ.RU_SAE instruction to the active function. +func (c *Context) VCVTSS2SIQ_RU_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSS2SIQ_RU_SAE(x, r)) +} + +// VCVTSS2SIQ_RU_SAE: Convert Scalar Single-Precision FP Value to Dword Integer (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSS2SIQ.RU_SAE xmm r64 +// Construct and append a VCVTSS2SIQ.RU_SAE instruction to the active function. +// Operates on the global context. +func VCVTSS2SIQ_RU_SAE(x, r operand.Op) { ctx.VCVTSS2SIQ_RU_SAE(x, r) } + +// VCVTSS2SIQ_RZ_SAE: Convert Scalar Single-Precision FP Value to Dword Integer (Round Towards Zero). +// +// Forms: +// +// VCVTSS2SIQ.RZ_SAE xmm r64 +// Construct and append a VCVTSS2SIQ.RZ_SAE instruction to the active function. +func (c *Context) VCVTSS2SIQ_RZ_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSS2SIQ_RZ_SAE(x, r)) +} + +// VCVTSS2SIQ_RZ_SAE: Convert Scalar Single-Precision FP Value to Dword Integer (Round Towards Zero). +// +// Forms: +// +// VCVTSS2SIQ.RZ_SAE xmm r64 +// Construct and append a VCVTSS2SIQ.RZ_SAE instruction to the active function. +// Operates on the global context. +func VCVTSS2SIQ_RZ_SAE(x, r operand.Op) { ctx.VCVTSS2SIQ_RZ_SAE(x, r) } + +// VCVTSS2SI_RD_SAE: Convert Scalar Single-Precision FP Value to Dword Integer (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSS2SI.RD_SAE xmm r32 +// Construct and append a VCVTSS2SI.RD_SAE instruction to the active function. +func (c *Context) VCVTSS2SI_RD_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSS2SI_RD_SAE(x, r)) +} + +// VCVTSS2SI_RD_SAE: Convert Scalar Single-Precision FP Value to Dword Integer (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSS2SI.RD_SAE xmm r32 +// Construct and append a VCVTSS2SI.RD_SAE instruction to the active function. +// Operates on the global context. +func VCVTSS2SI_RD_SAE(x, r operand.Op) { ctx.VCVTSS2SI_RD_SAE(x, r) } + +// VCVTSS2SI_RN_SAE: Convert Scalar Single-Precision FP Value to Dword Integer (Round Towards Nearest). +// +// Forms: +// +// VCVTSS2SI.RN_SAE xmm r32 +// Construct and append a VCVTSS2SI.RN_SAE instruction to the active function. +func (c *Context) VCVTSS2SI_RN_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSS2SI_RN_SAE(x, r)) +} + +// VCVTSS2SI_RN_SAE: Convert Scalar Single-Precision FP Value to Dword Integer (Round Towards Nearest). +// +// Forms: +// +// VCVTSS2SI.RN_SAE xmm r32 +// Construct and append a VCVTSS2SI.RN_SAE instruction to the active function. +// Operates on the global context. +func VCVTSS2SI_RN_SAE(x, r operand.Op) { ctx.VCVTSS2SI_RN_SAE(x, r) } + +// VCVTSS2SI_RU_SAE: Convert Scalar Single-Precision FP Value to Dword Integer (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSS2SI.RU_SAE xmm r32 +// Construct and append a VCVTSS2SI.RU_SAE instruction to the active function. +func (c *Context) VCVTSS2SI_RU_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSS2SI_RU_SAE(x, r)) +} + +// VCVTSS2SI_RU_SAE: Convert Scalar Single-Precision FP Value to Dword Integer (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSS2SI.RU_SAE xmm r32 +// Construct and append a VCVTSS2SI.RU_SAE instruction to the active function. +// Operates on the global context. +func VCVTSS2SI_RU_SAE(x, r operand.Op) { ctx.VCVTSS2SI_RU_SAE(x, r) } + +// VCVTSS2SI_RZ_SAE: Convert Scalar Single-Precision FP Value to Dword Integer (Round Towards Zero). +// +// Forms: +// +// VCVTSS2SI.RZ_SAE xmm r32 +// Construct and append a VCVTSS2SI.RZ_SAE instruction to the active function. +func (c *Context) VCVTSS2SI_RZ_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSS2SI_RZ_SAE(x, r)) +} + +// VCVTSS2SI_RZ_SAE: Convert Scalar Single-Precision FP Value to Dword Integer (Round Towards Zero). +// +// Forms: +// +// VCVTSS2SI.RZ_SAE xmm r32 +// Construct and append a VCVTSS2SI.RZ_SAE instruction to the active function. +// Operates on the global context. +func VCVTSS2SI_RZ_SAE(x, r operand.Op) { ctx.VCVTSS2SI_RZ_SAE(x, r) } + +// VCVTSS2USIL: Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer. +// +// Forms: +// +// VCVTSS2USIL m32 r32 +// VCVTSS2USIL xmm r32 +// Construct and append a VCVTSS2USIL instruction to the active function. +func (c *Context) VCVTSS2USIL(mx, r operand.Op) { + c.addinstruction(x86.VCVTSS2USIL(mx, r)) +} + +// VCVTSS2USIL: Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer. +// +// Forms: +// +// VCVTSS2USIL m32 r32 +// VCVTSS2USIL xmm r32 +// Construct and append a VCVTSS2USIL instruction to the active function. +// Operates on the global context. +func VCVTSS2USIL(mx, r operand.Op) { ctx.VCVTSS2USIL(mx, r) } + +// VCVTSS2USIL_RD_SAE: Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSS2USIL.RD_SAE xmm r32 +// Construct and append a VCVTSS2USIL.RD_SAE instruction to the active function. +func (c *Context) VCVTSS2USIL_RD_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSS2USIL_RD_SAE(x, r)) +} + +// VCVTSS2USIL_RD_SAE: Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSS2USIL.RD_SAE xmm r32 +// Construct and append a VCVTSS2USIL.RD_SAE instruction to the active function. +// Operates on the global context. +func VCVTSS2USIL_RD_SAE(x, r operand.Op) { ctx.VCVTSS2USIL_RD_SAE(x, r) } + +// VCVTSS2USIL_RN_SAE: Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Nearest). +// +// Forms: +// +// VCVTSS2USIL.RN_SAE xmm r32 +// Construct and append a VCVTSS2USIL.RN_SAE instruction to the active function. +func (c *Context) VCVTSS2USIL_RN_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSS2USIL_RN_SAE(x, r)) +} + +// VCVTSS2USIL_RN_SAE: Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Nearest). +// +// Forms: +// +// VCVTSS2USIL.RN_SAE xmm r32 +// Construct and append a VCVTSS2USIL.RN_SAE instruction to the active function. +// Operates on the global context. +func VCVTSS2USIL_RN_SAE(x, r operand.Op) { ctx.VCVTSS2USIL_RN_SAE(x, r) } + +// VCVTSS2USIL_RU_SAE: Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSS2USIL.RU_SAE xmm r32 +// Construct and append a VCVTSS2USIL.RU_SAE instruction to the active function. +func (c *Context) VCVTSS2USIL_RU_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSS2USIL_RU_SAE(x, r)) +} + +// VCVTSS2USIL_RU_SAE: Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSS2USIL.RU_SAE xmm r32 +// Construct and append a VCVTSS2USIL.RU_SAE instruction to the active function. +// Operates on the global context. +func VCVTSS2USIL_RU_SAE(x, r operand.Op) { ctx.VCVTSS2USIL_RU_SAE(x, r) } + +// VCVTSS2USIL_RZ_SAE: Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Zero). +// +// Forms: +// +// VCVTSS2USIL.RZ_SAE xmm r32 +// Construct and append a VCVTSS2USIL.RZ_SAE instruction to the active function. +func (c *Context) VCVTSS2USIL_RZ_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSS2USIL_RZ_SAE(x, r)) +} + +// VCVTSS2USIL_RZ_SAE: Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Zero). +// +// Forms: +// +// VCVTSS2USIL.RZ_SAE xmm r32 +// Construct and append a VCVTSS2USIL.RZ_SAE instruction to the active function. +// Operates on the global context. +func VCVTSS2USIL_RZ_SAE(x, r operand.Op) { ctx.VCVTSS2USIL_RZ_SAE(x, r) } + +// VCVTSS2USIQ: Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer. +// +// Forms: +// +// VCVTSS2USIQ m32 r64 +// VCVTSS2USIQ xmm r64 +// Construct and append a VCVTSS2USIQ instruction to the active function. +func (c *Context) VCVTSS2USIQ(mx, r operand.Op) { + c.addinstruction(x86.VCVTSS2USIQ(mx, r)) +} + +// VCVTSS2USIQ: Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer. +// +// Forms: +// +// VCVTSS2USIQ m32 r64 +// VCVTSS2USIQ xmm r64 +// Construct and append a VCVTSS2USIQ instruction to the active function. +// Operates on the global context. +func VCVTSS2USIQ(mx, r operand.Op) { ctx.VCVTSS2USIQ(mx, r) } + +// VCVTSS2USIQ_RD_SAE: Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSS2USIQ.RD_SAE xmm r64 +// Construct and append a VCVTSS2USIQ.RD_SAE instruction to the active function. +func (c *Context) VCVTSS2USIQ_RD_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSS2USIQ_RD_SAE(x, r)) +} + +// VCVTSS2USIQ_RD_SAE: Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSS2USIQ.RD_SAE xmm r64 +// Construct and append a VCVTSS2USIQ.RD_SAE instruction to the active function. +// Operates on the global context. +func VCVTSS2USIQ_RD_SAE(x, r operand.Op) { ctx.VCVTSS2USIQ_RD_SAE(x, r) } + +// VCVTSS2USIQ_RN_SAE: Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Nearest). +// +// Forms: +// +// VCVTSS2USIQ.RN_SAE xmm r64 +// Construct and append a VCVTSS2USIQ.RN_SAE instruction to the active function. +func (c *Context) VCVTSS2USIQ_RN_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSS2USIQ_RN_SAE(x, r)) +} + +// VCVTSS2USIQ_RN_SAE: Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Nearest). +// +// Forms: +// +// VCVTSS2USIQ.RN_SAE xmm r64 +// Construct and append a VCVTSS2USIQ.RN_SAE instruction to the active function. +// Operates on the global context. +func VCVTSS2USIQ_RN_SAE(x, r operand.Op) { ctx.VCVTSS2USIQ_RN_SAE(x, r) } + +// VCVTSS2USIQ_RU_SAE: Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSS2USIQ.RU_SAE xmm r64 +// Construct and append a VCVTSS2USIQ.RU_SAE instruction to the active function. +func (c *Context) VCVTSS2USIQ_RU_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSS2USIQ_RU_SAE(x, r)) +} + +// VCVTSS2USIQ_RU_SAE: Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSS2USIQ.RU_SAE xmm r64 +// Construct and append a VCVTSS2USIQ.RU_SAE instruction to the active function. +// Operates on the global context. +func VCVTSS2USIQ_RU_SAE(x, r operand.Op) { ctx.VCVTSS2USIQ_RU_SAE(x, r) } + +// VCVTSS2USIQ_RZ_SAE: Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Zero). +// +// Forms: +// +// VCVTSS2USIQ.RZ_SAE xmm r64 +// Construct and append a VCVTSS2USIQ.RZ_SAE instruction to the active function. +func (c *Context) VCVTSS2USIQ_RZ_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTSS2USIQ_RZ_SAE(x, r)) +} + +// VCVTSS2USIQ_RZ_SAE: Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Zero). +// +// Forms: +// +// VCVTSS2USIQ.RZ_SAE xmm r64 +// Construct and append a VCVTSS2USIQ.RZ_SAE instruction to the active function. +// Operates on the global context. +func VCVTSS2USIQ_RZ_SAE(x, r operand.Op) { ctx.VCVTSS2USIQ_RZ_SAE(x, r) } + +// VCVTTPD2DQ: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers. +// +// Forms: +// +// VCVTTPD2DQ m512 k ymm +// VCVTTPD2DQ m512 ymm +// VCVTTPD2DQ zmm k ymm +// VCVTTPD2DQ zmm ymm +// Construct and append a VCVTTPD2DQ instruction to the active function. +func (c *Context) VCVTTPD2DQ(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPD2DQ(ops...)) +} + +// VCVTTPD2DQ: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers. +// +// Forms: +// +// VCVTTPD2DQ m512 k ymm +// VCVTTPD2DQ m512 ymm +// VCVTTPD2DQ zmm k ymm +// VCVTTPD2DQ zmm ymm +// Construct and append a VCVTTPD2DQ instruction to the active function. +// Operates on the global context. +func VCVTTPD2DQ(ops ...operand.Op) { ctx.VCVTTPD2DQ(ops...) } + +// VCVTTPD2DQX: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers. +// +// Forms: +// +// VCVTTPD2DQX m128 xmm +// VCVTTPD2DQX xmm xmm +// VCVTTPD2DQX m128 k xmm +// VCVTTPD2DQX xmm k xmm +// Construct and append a VCVTTPD2DQX instruction to the active function. +func (c *Context) VCVTTPD2DQX(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPD2DQX(ops...)) +} + +// VCVTTPD2DQX: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers. +// +// Forms: +// +// VCVTTPD2DQX m128 xmm +// VCVTTPD2DQX xmm xmm +// VCVTTPD2DQX m128 k xmm +// VCVTTPD2DQX xmm k xmm +// Construct and append a VCVTTPD2DQX instruction to the active function. +// Operates on the global context. +func VCVTTPD2DQX(ops ...operand.Op) { ctx.VCVTTPD2DQX(ops...) } + +// VCVTTPD2DQX_BCST: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Broadcast). +// +// Forms: +// +// VCVTTPD2DQX.BCST m64 k xmm +// VCVTTPD2DQX.BCST m64 xmm +// Construct and append a VCVTTPD2DQX.BCST instruction to the active function. +func (c *Context) VCVTTPD2DQX_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPD2DQX_BCST(ops...)) +} + +// VCVTTPD2DQX_BCST: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Broadcast). +// +// Forms: +// +// VCVTTPD2DQX.BCST m64 k xmm +// VCVTTPD2DQX.BCST m64 xmm +// Construct and append a VCVTTPD2DQX.BCST instruction to the active function. +// Operates on the global context. +func VCVTTPD2DQX_BCST(ops ...operand.Op) { ctx.VCVTTPD2DQX_BCST(ops...) } + +// VCVTTPD2DQX_BCST_Z: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2DQX.BCST.Z m64 k xmm +// Construct and append a VCVTTPD2DQX.BCST.Z instruction to the active function. +func (c *Context) VCVTTPD2DQX_BCST_Z(m, k, x operand.Op) { + c.addinstruction(x86.VCVTTPD2DQX_BCST_Z(m, k, x)) +} + +// VCVTTPD2DQX_BCST_Z: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2DQX.BCST.Z m64 k xmm +// Construct and append a VCVTTPD2DQX.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTTPD2DQX_BCST_Z(m, k, x operand.Op) { ctx.VCVTTPD2DQX_BCST_Z(m, k, x) } + +// VCVTTPD2DQX_Z: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTTPD2DQX.Z m128 k xmm +// VCVTTPD2DQX.Z xmm k xmm +// Construct and append a VCVTTPD2DQX.Z instruction to the active function. +func (c *Context) VCVTTPD2DQX_Z(mx, k, x operand.Op) { + c.addinstruction(x86.VCVTTPD2DQX_Z(mx, k, x)) +} + +// VCVTTPD2DQX_Z: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTTPD2DQX.Z m128 k xmm +// VCVTTPD2DQX.Z xmm k xmm +// Construct and append a VCVTTPD2DQX.Z instruction to the active function. +// Operates on the global context. +func VCVTTPD2DQX_Z(mx, k, x operand.Op) { ctx.VCVTTPD2DQX_Z(mx, k, x) } + +// VCVTTPD2DQY: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers. +// +// Forms: +// +// VCVTTPD2DQY m256 xmm +// VCVTTPD2DQY ymm xmm +// VCVTTPD2DQY m256 k xmm +// VCVTTPD2DQY ymm k xmm +// Construct and append a VCVTTPD2DQY instruction to the active function. +func (c *Context) VCVTTPD2DQY(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPD2DQY(ops...)) +} + +// VCVTTPD2DQY: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers. +// +// Forms: +// +// VCVTTPD2DQY m256 xmm +// VCVTTPD2DQY ymm xmm +// VCVTTPD2DQY m256 k xmm +// VCVTTPD2DQY ymm k xmm +// Construct and append a VCVTTPD2DQY instruction to the active function. +// Operates on the global context. +func VCVTTPD2DQY(ops ...operand.Op) { ctx.VCVTTPD2DQY(ops...) } + +// VCVTTPD2DQY_BCST: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Broadcast). +// +// Forms: +// +// VCVTTPD2DQY.BCST m64 k xmm +// VCVTTPD2DQY.BCST m64 xmm +// Construct and append a VCVTTPD2DQY.BCST instruction to the active function. +func (c *Context) VCVTTPD2DQY_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPD2DQY_BCST(ops...)) +} + +// VCVTTPD2DQY_BCST: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Broadcast). +// +// Forms: +// +// VCVTTPD2DQY.BCST m64 k xmm +// VCVTTPD2DQY.BCST m64 xmm +// Construct and append a VCVTTPD2DQY.BCST instruction to the active function. +// Operates on the global context. +func VCVTTPD2DQY_BCST(ops ...operand.Op) { ctx.VCVTTPD2DQY_BCST(ops...) } + +// VCVTTPD2DQY_BCST_Z: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2DQY.BCST.Z m64 k xmm +// Construct and append a VCVTTPD2DQY.BCST.Z instruction to the active function. +func (c *Context) VCVTTPD2DQY_BCST_Z(m, k, x operand.Op) { + c.addinstruction(x86.VCVTTPD2DQY_BCST_Z(m, k, x)) +} + +// VCVTTPD2DQY_BCST_Z: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2DQY.BCST.Z m64 k xmm +// Construct and append a VCVTTPD2DQY.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTTPD2DQY_BCST_Z(m, k, x operand.Op) { ctx.VCVTTPD2DQY_BCST_Z(m, k, x) } + +// VCVTTPD2DQY_Z: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTTPD2DQY.Z m256 k xmm +// VCVTTPD2DQY.Z ymm k xmm +// Construct and append a VCVTTPD2DQY.Z instruction to the active function. +func (c *Context) VCVTTPD2DQY_Z(my, k, x operand.Op) { + c.addinstruction(x86.VCVTTPD2DQY_Z(my, k, x)) +} + +// VCVTTPD2DQY_Z: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTTPD2DQY.Z m256 k xmm +// VCVTTPD2DQY.Z ymm k xmm +// Construct and append a VCVTTPD2DQY.Z instruction to the active function. +// Operates on the global context. +func VCVTTPD2DQY_Z(my, k, x operand.Op) { ctx.VCVTTPD2DQY_Z(my, k, x) } + +// VCVTTPD2DQ_BCST: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Broadcast). +// +// Forms: +// +// VCVTTPD2DQ.BCST m64 k ymm +// VCVTTPD2DQ.BCST m64 ymm +// Construct and append a VCVTTPD2DQ.BCST instruction to the active function. +func (c *Context) VCVTTPD2DQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPD2DQ_BCST(ops...)) +} + +// VCVTTPD2DQ_BCST: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Broadcast). +// +// Forms: +// +// VCVTTPD2DQ.BCST m64 k ymm +// VCVTTPD2DQ.BCST m64 ymm +// Construct and append a VCVTTPD2DQ.BCST instruction to the active function. +// Operates on the global context. +func VCVTTPD2DQ_BCST(ops ...operand.Op) { ctx.VCVTTPD2DQ_BCST(ops...) } + +// VCVTTPD2DQ_BCST_Z: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2DQ.BCST.Z m64 k ymm +// Construct and append a VCVTTPD2DQ.BCST.Z instruction to the active function. +func (c *Context) VCVTTPD2DQ_BCST_Z(m, k, y operand.Op) { + c.addinstruction(x86.VCVTTPD2DQ_BCST_Z(m, k, y)) +} + +// VCVTTPD2DQ_BCST_Z: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2DQ.BCST.Z m64 k ymm +// Construct and append a VCVTTPD2DQ.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTTPD2DQ_BCST_Z(m, k, y operand.Op) { ctx.VCVTTPD2DQ_BCST_Z(m, k, y) } + +// VCVTTPD2DQ_SAE: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Suppress All Exceptions). +// +// Forms: +// +// VCVTTPD2DQ.SAE zmm k ymm +// VCVTTPD2DQ.SAE zmm ymm +// Construct and append a VCVTTPD2DQ.SAE instruction to the active function. +func (c *Context) VCVTTPD2DQ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPD2DQ_SAE(ops...)) +} + +// VCVTTPD2DQ_SAE: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Suppress All Exceptions). +// +// Forms: +// +// VCVTTPD2DQ.SAE zmm k ymm +// VCVTTPD2DQ.SAE zmm ymm +// Construct and append a VCVTTPD2DQ.SAE instruction to the active function. +// Operates on the global context. +func VCVTTPD2DQ_SAE(ops ...operand.Op) { ctx.VCVTTPD2DQ_SAE(ops...) } + +// VCVTTPD2DQ_SAE_Z: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2DQ.SAE.Z zmm k ymm +// Construct and append a VCVTTPD2DQ.SAE.Z instruction to the active function. +func (c *Context) VCVTTPD2DQ_SAE_Z(z, k, y operand.Op) { + c.addinstruction(x86.VCVTTPD2DQ_SAE_Z(z, k, y)) +} + +// VCVTTPD2DQ_SAE_Z: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2DQ.SAE.Z zmm k ymm +// Construct and append a VCVTTPD2DQ.SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTTPD2DQ_SAE_Z(z, k, y operand.Op) { ctx.VCVTTPD2DQ_SAE_Z(z, k, y) } + +// VCVTTPD2DQ_Z: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTTPD2DQ.Z m512 k ymm +// VCVTTPD2DQ.Z zmm k ymm +// Construct and append a VCVTTPD2DQ.Z instruction to the active function. +func (c *Context) VCVTTPD2DQ_Z(mz, k, y operand.Op) { + c.addinstruction(x86.VCVTTPD2DQ_Z(mz, k, y)) +} + +// VCVTTPD2DQ_Z: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTTPD2DQ.Z m512 k ymm +// VCVTTPD2DQ.Z zmm k ymm +// Construct and append a VCVTTPD2DQ.Z instruction to the active function. +// Operates on the global context. +func VCVTTPD2DQ_Z(mz, k, y operand.Op) { ctx.VCVTTPD2DQ_Z(mz, k, y) } + +// VCVTTPD2QQ: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers. +// +// Forms: +// +// VCVTTPD2QQ m128 k xmm +// VCVTTPD2QQ m128 xmm +// VCVTTPD2QQ m256 k ymm +// VCVTTPD2QQ m256 ymm +// VCVTTPD2QQ xmm k xmm +// VCVTTPD2QQ xmm xmm +// VCVTTPD2QQ ymm k ymm +// VCVTTPD2QQ ymm ymm +// VCVTTPD2QQ m512 k zmm +// VCVTTPD2QQ m512 zmm +// VCVTTPD2QQ zmm k zmm +// VCVTTPD2QQ zmm zmm +// Construct and append a VCVTTPD2QQ instruction to the active function. +func (c *Context) VCVTTPD2QQ(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPD2QQ(ops...)) +} + +// VCVTTPD2QQ: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers. +// +// Forms: +// +// VCVTTPD2QQ m128 k xmm +// VCVTTPD2QQ m128 xmm +// VCVTTPD2QQ m256 k ymm +// VCVTTPD2QQ m256 ymm +// VCVTTPD2QQ xmm k xmm +// VCVTTPD2QQ xmm xmm +// VCVTTPD2QQ ymm k ymm +// VCVTTPD2QQ ymm ymm +// VCVTTPD2QQ m512 k zmm +// VCVTTPD2QQ m512 zmm +// VCVTTPD2QQ zmm k zmm +// VCVTTPD2QQ zmm zmm +// Construct and append a VCVTTPD2QQ instruction to the active function. +// Operates on the global context. +func VCVTTPD2QQ(ops ...operand.Op) { ctx.VCVTTPD2QQ(ops...) } + +// VCVTTPD2QQ_BCST: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Broadcast). +// +// Forms: +// +// VCVTTPD2QQ.BCST m64 k xmm +// VCVTTPD2QQ.BCST m64 k ymm +// VCVTTPD2QQ.BCST m64 xmm +// VCVTTPD2QQ.BCST m64 ymm +// VCVTTPD2QQ.BCST m64 k zmm +// VCVTTPD2QQ.BCST m64 zmm +// Construct and append a VCVTTPD2QQ.BCST instruction to the active function. +func (c *Context) VCVTTPD2QQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPD2QQ_BCST(ops...)) +} + +// VCVTTPD2QQ_BCST: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Broadcast). +// +// Forms: +// +// VCVTTPD2QQ.BCST m64 k xmm +// VCVTTPD2QQ.BCST m64 k ymm +// VCVTTPD2QQ.BCST m64 xmm +// VCVTTPD2QQ.BCST m64 ymm +// VCVTTPD2QQ.BCST m64 k zmm +// VCVTTPD2QQ.BCST m64 zmm +// Construct and append a VCVTTPD2QQ.BCST instruction to the active function. +// Operates on the global context. +func VCVTTPD2QQ_BCST(ops ...operand.Op) { ctx.VCVTTPD2QQ_BCST(ops...) } + +// VCVTTPD2QQ_BCST_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2QQ.BCST.Z m64 k xmm +// VCVTTPD2QQ.BCST.Z m64 k ymm +// VCVTTPD2QQ.BCST.Z m64 k zmm +// Construct and append a VCVTTPD2QQ.BCST.Z instruction to the active function. +func (c *Context) VCVTTPD2QQ_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VCVTTPD2QQ_BCST_Z(m, k, xyz)) +} + +// VCVTTPD2QQ_BCST_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2QQ.BCST.Z m64 k xmm +// VCVTTPD2QQ.BCST.Z m64 k ymm +// VCVTTPD2QQ.BCST.Z m64 k zmm +// Construct and append a VCVTTPD2QQ.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTTPD2QQ_BCST_Z(m, k, xyz operand.Op) { ctx.VCVTTPD2QQ_BCST_Z(m, k, xyz) } + +// VCVTTPD2QQ_SAE: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Suppress All Exceptions). +// +// Forms: +// +// VCVTTPD2QQ.SAE zmm k zmm +// VCVTTPD2QQ.SAE zmm zmm +// Construct and append a VCVTTPD2QQ.SAE instruction to the active function. +func (c *Context) VCVTTPD2QQ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPD2QQ_SAE(ops...)) +} + +// VCVTTPD2QQ_SAE: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Suppress All Exceptions). +// +// Forms: +// +// VCVTTPD2QQ.SAE zmm k zmm +// VCVTTPD2QQ.SAE zmm zmm +// Construct and append a VCVTTPD2QQ.SAE instruction to the active function. +// Operates on the global context. +func VCVTTPD2QQ_SAE(ops ...operand.Op) { ctx.VCVTTPD2QQ_SAE(ops...) } + +// VCVTTPD2QQ_SAE_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2QQ.SAE.Z zmm k zmm +// Construct and append a VCVTTPD2QQ.SAE.Z instruction to the active function. +func (c *Context) VCVTTPD2QQ_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTTPD2QQ_SAE_Z(z, k, z1)) +} + +// VCVTTPD2QQ_SAE_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2QQ.SAE.Z zmm k zmm +// Construct and append a VCVTTPD2QQ.SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTTPD2QQ_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTTPD2QQ_SAE_Z(z, k, z1) } + +// VCVTTPD2QQ_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTTPD2QQ.Z m128 k xmm +// VCVTTPD2QQ.Z m256 k ymm +// VCVTTPD2QQ.Z xmm k xmm +// VCVTTPD2QQ.Z ymm k ymm +// VCVTTPD2QQ.Z m512 k zmm +// VCVTTPD2QQ.Z zmm k zmm +// Construct and append a VCVTTPD2QQ.Z instruction to the active function. +func (c *Context) VCVTTPD2QQ_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VCVTTPD2QQ_Z(mxyz, k, xyz)) +} + +// VCVTTPD2QQ_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTTPD2QQ.Z m128 k xmm +// VCVTTPD2QQ.Z m256 k ymm +// VCVTTPD2QQ.Z xmm k xmm +// VCVTTPD2QQ.Z ymm k ymm +// VCVTTPD2QQ.Z m512 k zmm +// VCVTTPD2QQ.Z zmm k zmm +// Construct and append a VCVTTPD2QQ.Z instruction to the active function. +// Operates on the global context. +func VCVTTPD2QQ_Z(mxyz, k, xyz operand.Op) { ctx.VCVTTPD2QQ_Z(mxyz, k, xyz) } + +// VCVTTPD2UDQ: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers. +// +// Forms: +// +// VCVTTPD2UDQ m512 k ymm +// VCVTTPD2UDQ m512 ymm +// VCVTTPD2UDQ zmm k ymm +// VCVTTPD2UDQ zmm ymm +// Construct and append a VCVTTPD2UDQ instruction to the active function. +func (c *Context) VCVTTPD2UDQ(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPD2UDQ(ops...)) +} + +// VCVTTPD2UDQ: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers. +// +// Forms: +// +// VCVTTPD2UDQ m512 k ymm +// VCVTTPD2UDQ m512 ymm +// VCVTTPD2UDQ zmm k ymm +// VCVTTPD2UDQ zmm ymm +// Construct and append a VCVTTPD2UDQ instruction to the active function. +// Operates on the global context. +func VCVTTPD2UDQ(ops ...operand.Op) { ctx.VCVTTPD2UDQ(ops...) } + +// VCVTTPD2UDQX: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers. +// +// Forms: +// +// VCVTTPD2UDQX m128 k xmm +// VCVTTPD2UDQX m128 xmm +// VCVTTPD2UDQX xmm k xmm +// VCVTTPD2UDQX xmm xmm +// Construct and append a VCVTTPD2UDQX instruction to the active function. +func (c *Context) VCVTTPD2UDQX(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPD2UDQX(ops...)) +} + +// VCVTTPD2UDQX: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers. +// +// Forms: +// +// VCVTTPD2UDQX m128 k xmm +// VCVTTPD2UDQX m128 xmm +// VCVTTPD2UDQX xmm k xmm +// VCVTTPD2UDQX xmm xmm +// Construct and append a VCVTTPD2UDQX instruction to the active function. +// Operates on the global context. +func VCVTTPD2UDQX(ops ...operand.Op) { ctx.VCVTTPD2UDQX(ops...) } + +// VCVTTPD2UDQX_BCST: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast). +// +// Forms: +// +// VCVTTPD2UDQX.BCST m64 k xmm +// VCVTTPD2UDQX.BCST m64 xmm +// Construct and append a VCVTTPD2UDQX.BCST instruction to the active function. +func (c *Context) VCVTTPD2UDQX_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPD2UDQX_BCST(ops...)) +} + +// VCVTTPD2UDQX_BCST: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast). +// +// Forms: +// +// VCVTTPD2UDQX.BCST m64 k xmm +// VCVTTPD2UDQX.BCST m64 xmm +// Construct and append a VCVTTPD2UDQX.BCST instruction to the active function. +// Operates on the global context. +func VCVTTPD2UDQX_BCST(ops ...operand.Op) { ctx.VCVTTPD2UDQX_BCST(ops...) } + +// VCVTTPD2UDQX_BCST_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2UDQX.BCST.Z m64 k xmm +// Construct and append a VCVTTPD2UDQX.BCST.Z instruction to the active function. +func (c *Context) VCVTTPD2UDQX_BCST_Z(m, k, x operand.Op) { + c.addinstruction(x86.VCVTTPD2UDQX_BCST_Z(m, k, x)) +} + +// VCVTTPD2UDQX_BCST_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2UDQX.BCST.Z m64 k xmm +// Construct and append a VCVTTPD2UDQX.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTTPD2UDQX_BCST_Z(m, k, x operand.Op) { ctx.VCVTTPD2UDQX_BCST_Z(m, k, x) } + +// VCVTTPD2UDQX_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTTPD2UDQX.Z m128 k xmm +// VCVTTPD2UDQX.Z xmm k xmm +// Construct and append a VCVTTPD2UDQX.Z instruction to the active function. +func (c *Context) VCVTTPD2UDQX_Z(mx, k, x operand.Op) { + c.addinstruction(x86.VCVTTPD2UDQX_Z(mx, k, x)) +} + +// VCVTTPD2UDQX_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTTPD2UDQX.Z m128 k xmm +// VCVTTPD2UDQX.Z xmm k xmm +// Construct and append a VCVTTPD2UDQX.Z instruction to the active function. +// Operates on the global context. +func VCVTTPD2UDQX_Z(mx, k, x operand.Op) { ctx.VCVTTPD2UDQX_Z(mx, k, x) } + +// VCVTTPD2UDQY: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers. +// +// Forms: +// +// VCVTTPD2UDQY m256 k xmm +// VCVTTPD2UDQY m256 xmm +// VCVTTPD2UDQY ymm k xmm +// VCVTTPD2UDQY ymm xmm +// Construct and append a VCVTTPD2UDQY instruction to the active function. +func (c *Context) VCVTTPD2UDQY(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPD2UDQY(ops...)) +} + +// VCVTTPD2UDQY: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers. +// +// Forms: +// +// VCVTTPD2UDQY m256 k xmm +// VCVTTPD2UDQY m256 xmm +// VCVTTPD2UDQY ymm k xmm +// VCVTTPD2UDQY ymm xmm +// Construct and append a VCVTTPD2UDQY instruction to the active function. +// Operates on the global context. +func VCVTTPD2UDQY(ops ...operand.Op) { ctx.VCVTTPD2UDQY(ops...) } + +// VCVTTPD2UDQY_BCST: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast). +// +// Forms: +// +// VCVTTPD2UDQY.BCST m64 k xmm +// VCVTTPD2UDQY.BCST m64 xmm +// Construct and append a VCVTTPD2UDQY.BCST instruction to the active function. +func (c *Context) VCVTTPD2UDQY_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPD2UDQY_BCST(ops...)) +} + +// VCVTTPD2UDQY_BCST: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast). +// +// Forms: +// +// VCVTTPD2UDQY.BCST m64 k xmm +// VCVTTPD2UDQY.BCST m64 xmm +// Construct and append a VCVTTPD2UDQY.BCST instruction to the active function. +// Operates on the global context. +func VCVTTPD2UDQY_BCST(ops ...operand.Op) { ctx.VCVTTPD2UDQY_BCST(ops...) } + +// VCVTTPD2UDQY_BCST_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2UDQY.BCST.Z m64 k xmm +// Construct and append a VCVTTPD2UDQY.BCST.Z instruction to the active function. +func (c *Context) VCVTTPD2UDQY_BCST_Z(m, k, x operand.Op) { + c.addinstruction(x86.VCVTTPD2UDQY_BCST_Z(m, k, x)) +} + +// VCVTTPD2UDQY_BCST_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2UDQY.BCST.Z m64 k xmm +// Construct and append a VCVTTPD2UDQY.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTTPD2UDQY_BCST_Z(m, k, x operand.Op) { ctx.VCVTTPD2UDQY_BCST_Z(m, k, x) } + +// VCVTTPD2UDQY_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTTPD2UDQY.Z m256 k xmm +// VCVTTPD2UDQY.Z ymm k xmm +// Construct and append a VCVTTPD2UDQY.Z instruction to the active function. +func (c *Context) VCVTTPD2UDQY_Z(my, k, x operand.Op) { + c.addinstruction(x86.VCVTTPD2UDQY_Z(my, k, x)) +} + +// VCVTTPD2UDQY_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTTPD2UDQY.Z m256 k xmm +// VCVTTPD2UDQY.Z ymm k xmm +// Construct and append a VCVTTPD2UDQY.Z instruction to the active function. +// Operates on the global context. +func VCVTTPD2UDQY_Z(my, k, x operand.Op) { ctx.VCVTTPD2UDQY_Z(my, k, x) } + +// VCVTTPD2UDQ_BCST: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast). +// +// Forms: +// +// VCVTTPD2UDQ.BCST m64 k ymm +// VCVTTPD2UDQ.BCST m64 ymm +// Construct and append a VCVTTPD2UDQ.BCST instruction to the active function. +func (c *Context) VCVTTPD2UDQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPD2UDQ_BCST(ops...)) +} + +// VCVTTPD2UDQ_BCST: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast). +// +// Forms: +// +// VCVTTPD2UDQ.BCST m64 k ymm +// VCVTTPD2UDQ.BCST m64 ymm +// Construct and append a VCVTTPD2UDQ.BCST instruction to the active function. +// Operates on the global context. +func VCVTTPD2UDQ_BCST(ops ...operand.Op) { ctx.VCVTTPD2UDQ_BCST(ops...) } + +// VCVTTPD2UDQ_BCST_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2UDQ.BCST.Z m64 k ymm +// Construct and append a VCVTTPD2UDQ.BCST.Z instruction to the active function. +func (c *Context) VCVTTPD2UDQ_BCST_Z(m, k, y operand.Op) { + c.addinstruction(x86.VCVTTPD2UDQ_BCST_Z(m, k, y)) +} + +// VCVTTPD2UDQ_BCST_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2UDQ.BCST.Z m64 k ymm +// Construct and append a VCVTTPD2UDQ.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTTPD2UDQ_BCST_Z(m, k, y operand.Op) { ctx.VCVTTPD2UDQ_BCST_Z(m, k, y) } + +// VCVTTPD2UDQ_SAE: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Suppress All Exceptions). +// +// Forms: +// +// VCVTTPD2UDQ.SAE zmm k ymm +// VCVTTPD2UDQ.SAE zmm ymm +// Construct and append a VCVTTPD2UDQ.SAE instruction to the active function. +func (c *Context) VCVTTPD2UDQ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPD2UDQ_SAE(ops...)) +} + +// VCVTTPD2UDQ_SAE: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Suppress All Exceptions). +// +// Forms: +// +// VCVTTPD2UDQ.SAE zmm k ymm +// VCVTTPD2UDQ.SAE zmm ymm +// Construct and append a VCVTTPD2UDQ.SAE instruction to the active function. +// Operates on the global context. +func VCVTTPD2UDQ_SAE(ops ...operand.Op) { ctx.VCVTTPD2UDQ_SAE(ops...) } + +// VCVTTPD2UDQ_SAE_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2UDQ.SAE.Z zmm k ymm +// Construct and append a VCVTTPD2UDQ.SAE.Z instruction to the active function. +func (c *Context) VCVTTPD2UDQ_SAE_Z(z, k, y operand.Op) { + c.addinstruction(x86.VCVTTPD2UDQ_SAE_Z(z, k, y)) +} + +// VCVTTPD2UDQ_SAE_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2UDQ.SAE.Z zmm k ymm +// Construct and append a VCVTTPD2UDQ.SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTTPD2UDQ_SAE_Z(z, k, y operand.Op) { ctx.VCVTTPD2UDQ_SAE_Z(z, k, y) } + +// VCVTTPD2UDQ_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTTPD2UDQ.Z m512 k ymm +// VCVTTPD2UDQ.Z zmm k ymm +// Construct and append a VCVTTPD2UDQ.Z instruction to the active function. +func (c *Context) VCVTTPD2UDQ_Z(mz, k, y operand.Op) { + c.addinstruction(x86.VCVTTPD2UDQ_Z(mz, k, y)) +} + +// VCVTTPD2UDQ_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTTPD2UDQ.Z m512 k ymm +// VCVTTPD2UDQ.Z zmm k ymm +// Construct and append a VCVTTPD2UDQ.Z instruction to the active function. +// Operates on the global context. +func VCVTTPD2UDQ_Z(mz, k, y operand.Op) { ctx.VCVTTPD2UDQ_Z(mz, k, y) } + +// VCVTTPD2UQQ: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers. +// +// Forms: +// +// VCVTTPD2UQQ m128 k xmm +// VCVTTPD2UQQ m128 xmm +// VCVTTPD2UQQ m256 k ymm +// VCVTTPD2UQQ m256 ymm +// VCVTTPD2UQQ xmm k xmm +// VCVTTPD2UQQ xmm xmm +// VCVTTPD2UQQ ymm k ymm +// VCVTTPD2UQQ ymm ymm +// VCVTTPD2UQQ m512 k zmm +// VCVTTPD2UQQ m512 zmm +// VCVTTPD2UQQ zmm k zmm +// VCVTTPD2UQQ zmm zmm +// Construct and append a VCVTTPD2UQQ instruction to the active function. +func (c *Context) VCVTTPD2UQQ(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPD2UQQ(ops...)) +} + +// VCVTTPD2UQQ: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers. +// +// Forms: +// +// VCVTTPD2UQQ m128 k xmm +// VCVTTPD2UQQ m128 xmm +// VCVTTPD2UQQ m256 k ymm +// VCVTTPD2UQQ m256 ymm +// VCVTTPD2UQQ xmm k xmm +// VCVTTPD2UQQ xmm xmm +// VCVTTPD2UQQ ymm k ymm +// VCVTTPD2UQQ ymm ymm +// VCVTTPD2UQQ m512 k zmm +// VCVTTPD2UQQ m512 zmm +// VCVTTPD2UQQ zmm k zmm +// VCVTTPD2UQQ zmm zmm +// Construct and append a VCVTTPD2UQQ instruction to the active function. +// Operates on the global context. +func VCVTTPD2UQQ(ops ...operand.Op) { ctx.VCVTTPD2UQQ(ops...) } + +// VCVTTPD2UQQ_BCST: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Broadcast). +// +// Forms: +// +// VCVTTPD2UQQ.BCST m64 k xmm +// VCVTTPD2UQQ.BCST m64 k ymm +// VCVTTPD2UQQ.BCST m64 xmm +// VCVTTPD2UQQ.BCST m64 ymm +// VCVTTPD2UQQ.BCST m64 k zmm +// VCVTTPD2UQQ.BCST m64 zmm +// Construct and append a VCVTTPD2UQQ.BCST instruction to the active function. +func (c *Context) VCVTTPD2UQQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPD2UQQ_BCST(ops...)) +} + +// VCVTTPD2UQQ_BCST: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Broadcast). +// +// Forms: +// +// VCVTTPD2UQQ.BCST m64 k xmm +// VCVTTPD2UQQ.BCST m64 k ymm +// VCVTTPD2UQQ.BCST m64 xmm +// VCVTTPD2UQQ.BCST m64 ymm +// VCVTTPD2UQQ.BCST m64 k zmm +// VCVTTPD2UQQ.BCST m64 zmm +// Construct and append a VCVTTPD2UQQ.BCST instruction to the active function. +// Operates on the global context. +func VCVTTPD2UQQ_BCST(ops ...operand.Op) { ctx.VCVTTPD2UQQ_BCST(ops...) } + +// VCVTTPD2UQQ_BCST_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2UQQ.BCST.Z m64 k xmm +// VCVTTPD2UQQ.BCST.Z m64 k ymm +// VCVTTPD2UQQ.BCST.Z m64 k zmm +// Construct and append a VCVTTPD2UQQ.BCST.Z instruction to the active function. +func (c *Context) VCVTTPD2UQQ_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VCVTTPD2UQQ_BCST_Z(m, k, xyz)) +} + +// VCVTTPD2UQQ_BCST_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2UQQ.BCST.Z m64 k xmm +// VCVTTPD2UQQ.BCST.Z m64 k ymm +// VCVTTPD2UQQ.BCST.Z m64 k zmm +// Construct and append a VCVTTPD2UQQ.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTTPD2UQQ_BCST_Z(m, k, xyz operand.Op) { ctx.VCVTTPD2UQQ_BCST_Z(m, k, xyz) } + +// VCVTTPD2UQQ_SAE: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Suppress All Exceptions). +// +// Forms: +// +// VCVTTPD2UQQ.SAE zmm k zmm +// VCVTTPD2UQQ.SAE zmm zmm +// Construct and append a VCVTTPD2UQQ.SAE instruction to the active function. +func (c *Context) VCVTTPD2UQQ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPD2UQQ_SAE(ops...)) +} + +// VCVTTPD2UQQ_SAE: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Suppress All Exceptions). +// +// Forms: +// +// VCVTTPD2UQQ.SAE zmm k zmm +// VCVTTPD2UQQ.SAE zmm zmm +// Construct and append a VCVTTPD2UQQ.SAE instruction to the active function. +// Operates on the global context. +func VCVTTPD2UQQ_SAE(ops ...operand.Op) { ctx.VCVTTPD2UQQ_SAE(ops...) } + +// VCVTTPD2UQQ_SAE_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2UQQ.SAE.Z zmm k zmm +// Construct and append a VCVTTPD2UQQ.SAE.Z instruction to the active function. +func (c *Context) VCVTTPD2UQQ_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTTPD2UQQ_SAE_Z(z, k, z1)) +} + +// VCVTTPD2UQQ_SAE_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2UQQ.SAE.Z zmm k zmm +// Construct and append a VCVTTPD2UQQ.SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTTPD2UQQ_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTTPD2UQQ_SAE_Z(z, k, z1) } + +// VCVTTPD2UQQ_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTTPD2UQQ.Z m128 k xmm +// VCVTTPD2UQQ.Z m256 k ymm +// VCVTTPD2UQQ.Z xmm k xmm +// VCVTTPD2UQQ.Z ymm k ymm +// VCVTTPD2UQQ.Z m512 k zmm +// VCVTTPD2UQQ.Z zmm k zmm +// Construct and append a VCVTTPD2UQQ.Z instruction to the active function. +func (c *Context) VCVTTPD2UQQ_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VCVTTPD2UQQ_Z(mxyz, k, xyz)) +} + +// VCVTTPD2UQQ_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTTPD2UQQ.Z m128 k xmm +// VCVTTPD2UQQ.Z m256 k ymm +// VCVTTPD2UQQ.Z xmm k xmm +// VCVTTPD2UQQ.Z ymm k ymm +// VCVTTPD2UQQ.Z m512 k zmm +// VCVTTPD2UQQ.Z zmm k zmm +// Construct and append a VCVTTPD2UQQ.Z instruction to the active function. +// Operates on the global context. +func VCVTTPD2UQQ_Z(mxyz, k, xyz operand.Op) { ctx.VCVTTPD2UQQ_Z(mxyz, k, xyz) } + +// VCVTTPS2DQ: Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers. +// +// Forms: +// +// VCVTTPS2DQ m128 xmm +// VCVTTPS2DQ m256 ymm +// VCVTTPS2DQ xmm xmm +// VCVTTPS2DQ ymm ymm +// VCVTTPS2DQ m128 k xmm +// VCVTTPS2DQ m256 k ymm +// VCVTTPS2DQ xmm k xmm +// VCVTTPS2DQ ymm k ymm +// VCVTTPS2DQ m512 k zmm +// VCVTTPS2DQ m512 zmm +// VCVTTPS2DQ zmm k zmm +// VCVTTPS2DQ zmm zmm +// Construct and append a VCVTTPS2DQ instruction to the active function. +func (c *Context) VCVTTPS2DQ(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPS2DQ(ops...)) +} + +// VCVTTPS2DQ: Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers. +// +// Forms: +// +// VCVTTPS2DQ m128 xmm +// VCVTTPS2DQ m256 ymm +// VCVTTPS2DQ xmm xmm +// VCVTTPS2DQ ymm ymm +// VCVTTPS2DQ m128 k xmm +// VCVTTPS2DQ m256 k ymm +// VCVTTPS2DQ xmm k xmm +// VCVTTPS2DQ ymm k ymm +// VCVTTPS2DQ m512 k zmm +// VCVTTPS2DQ m512 zmm +// VCVTTPS2DQ zmm k zmm +// VCVTTPS2DQ zmm zmm +// Construct and append a VCVTTPS2DQ instruction to the active function. +// Operates on the global context. +func VCVTTPS2DQ(ops ...operand.Op) { ctx.VCVTTPS2DQ(ops...) } + +// VCVTTPS2DQ_BCST: Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers (Broadcast). +// +// Forms: +// +// VCVTTPS2DQ.BCST m32 k xmm +// VCVTTPS2DQ.BCST m32 k ymm +// VCVTTPS2DQ.BCST m32 xmm +// VCVTTPS2DQ.BCST m32 ymm +// VCVTTPS2DQ.BCST m32 k zmm +// VCVTTPS2DQ.BCST m32 zmm +// Construct and append a VCVTTPS2DQ.BCST instruction to the active function. +func (c *Context) VCVTTPS2DQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPS2DQ_BCST(ops...)) +} + +// VCVTTPS2DQ_BCST: Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers (Broadcast). +// +// Forms: +// +// VCVTTPS2DQ.BCST m32 k xmm +// VCVTTPS2DQ.BCST m32 k ymm +// VCVTTPS2DQ.BCST m32 xmm +// VCVTTPS2DQ.BCST m32 ymm +// VCVTTPS2DQ.BCST m32 k zmm +// VCVTTPS2DQ.BCST m32 zmm +// Construct and append a VCVTTPS2DQ.BCST instruction to the active function. +// Operates on the global context. +func VCVTTPS2DQ_BCST(ops ...operand.Op) { ctx.VCVTTPS2DQ_BCST(ops...) } + +// VCVTTPS2DQ_BCST_Z: Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPS2DQ.BCST.Z m32 k xmm +// VCVTTPS2DQ.BCST.Z m32 k ymm +// VCVTTPS2DQ.BCST.Z m32 k zmm +// Construct and append a VCVTTPS2DQ.BCST.Z instruction to the active function. +func (c *Context) VCVTTPS2DQ_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VCVTTPS2DQ_BCST_Z(m, k, xyz)) +} + +// VCVTTPS2DQ_BCST_Z: Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPS2DQ.BCST.Z m32 k xmm +// VCVTTPS2DQ.BCST.Z m32 k ymm +// VCVTTPS2DQ.BCST.Z m32 k zmm +// Construct and append a VCVTTPS2DQ.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTTPS2DQ_BCST_Z(m, k, xyz operand.Op) { ctx.VCVTTPS2DQ_BCST_Z(m, k, xyz) } + +// VCVTTPS2DQ_SAE: Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers (Suppress All Exceptions). +// +// Forms: +// +// VCVTTPS2DQ.SAE zmm k zmm +// VCVTTPS2DQ.SAE zmm zmm +// Construct and append a VCVTTPS2DQ.SAE instruction to the active function. +func (c *Context) VCVTTPS2DQ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPS2DQ_SAE(ops...)) +} + +// VCVTTPS2DQ_SAE: Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers (Suppress All Exceptions). +// +// Forms: +// +// VCVTTPS2DQ.SAE zmm k zmm +// VCVTTPS2DQ.SAE zmm zmm +// Construct and append a VCVTTPS2DQ.SAE instruction to the active function. +// Operates on the global context. +func VCVTTPS2DQ_SAE(ops ...operand.Op) { ctx.VCVTTPS2DQ_SAE(ops...) } + +// VCVTTPS2DQ_SAE_Z: Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTTPS2DQ.SAE.Z zmm k zmm +// Construct and append a VCVTTPS2DQ.SAE.Z instruction to the active function. +func (c *Context) VCVTTPS2DQ_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTTPS2DQ_SAE_Z(z, k, z1)) +} + +// VCVTTPS2DQ_SAE_Z: Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTTPS2DQ.SAE.Z zmm k zmm +// Construct and append a VCVTTPS2DQ.SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTTPS2DQ_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTTPS2DQ_SAE_Z(z, k, z1) } + +// VCVTTPS2DQ_Z: Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTTPS2DQ.Z m128 k xmm +// VCVTTPS2DQ.Z m256 k ymm +// VCVTTPS2DQ.Z xmm k xmm +// VCVTTPS2DQ.Z ymm k ymm +// VCVTTPS2DQ.Z m512 k zmm +// VCVTTPS2DQ.Z zmm k zmm +// Construct and append a VCVTTPS2DQ.Z instruction to the active function. +func (c *Context) VCVTTPS2DQ_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VCVTTPS2DQ_Z(mxyz, k, xyz)) +} + +// VCVTTPS2DQ_Z: Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTTPS2DQ.Z m128 k xmm +// VCVTTPS2DQ.Z m256 k ymm +// VCVTTPS2DQ.Z xmm k xmm +// VCVTTPS2DQ.Z ymm k ymm +// VCVTTPS2DQ.Z m512 k zmm +// VCVTTPS2DQ.Z zmm k zmm +// Construct and append a VCVTTPS2DQ.Z instruction to the active function. +// Operates on the global context. +func VCVTTPS2DQ_Z(mxyz, k, xyz operand.Op) { ctx.VCVTTPS2DQ_Z(mxyz, k, xyz) } + +// VCVTTPS2QQ: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values. +// +// Forms: +// +// VCVTTPS2QQ m128 k ymm +// VCVTTPS2QQ m128 ymm +// VCVTTPS2QQ m64 k xmm +// VCVTTPS2QQ m64 xmm +// VCVTTPS2QQ xmm k xmm +// VCVTTPS2QQ xmm k ymm +// VCVTTPS2QQ xmm xmm +// VCVTTPS2QQ xmm ymm +// VCVTTPS2QQ m256 k zmm +// VCVTTPS2QQ m256 zmm +// VCVTTPS2QQ ymm k zmm +// VCVTTPS2QQ ymm zmm +// Construct and append a VCVTTPS2QQ instruction to the active function. +func (c *Context) VCVTTPS2QQ(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPS2QQ(ops...)) +} + +// VCVTTPS2QQ: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values. +// +// Forms: +// +// VCVTTPS2QQ m128 k ymm +// VCVTTPS2QQ m128 ymm +// VCVTTPS2QQ m64 k xmm +// VCVTTPS2QQ m64 xmm +// VCVTTPS2QQ xmm k xmm +// VCVTTPS2QQ xmm k ymm +// VCVTTPS2QQ xmm xmm +// VCVTTPS2QQ xmm ymm +// VCVTTPS2QQ m256 k zmm +// VCVTTPS2QQ m256 zmm +// VCVTTPS2QQ ymm k zmm +// VCVTTPS2QQ ymm zmm +// Construct and append a VCVTTPS2QQ instruction to the active function. +// Operates on the global context. +func VCVTTPS2QQ(ops ...operand.Op) { ctx.VCVTTPS2QQ(ops...) } + +// VCVTTPS2QQ_BCST: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Broadcast). +// +// Forms: +// +// VCVTTPS2QQ.BCST m32 k xmm +// VCVTTPS2QQ.BCST m32 k ymm +// VCVTTPS2QQ.BCST m32 xmm +// VCVTTPS2QQ.BCST m32 ymm +// VCVTTPS2QQ.BCST m32 k zmm +// VCVTTPS2QQ.BCST m32 zmm +// Construct and append a VCVTTPS2QQ.BCST instruction to the active function. +func (c *Context) VCVTTPS2QQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPS2QQ_BCST(ops...)) +} + +// VCVTTPS2QQ_BCST: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Broadcast). +// +// Forms: +// +// VCVTTPS2QQ.BCST m32 k xmm +// VCVTTPS2QQ.BCST m32 k ymm +// VCVTTPS2QQ.BCST m32 xmm +// VCVTTPS2QQ.BCST m32 ymm +// VCVTTPS2QQ.BCST m32 k zmm +// VCVTTPS2QQ.BCST m32 zmm +// Construct and append a VCVTTPS2QQ.BCST instruction to the active function. +// Operates on the global context. +func VCVTTPS2QQ_BCST(ops ...operand.Op) { ctx.VCVTTPS2QQ_BCST(ops...) } + +// VCVTTPS2QQ_BCST_Z: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPS2QQ.BCST.Z m32 k xmm +// VCVTTPS2QQ.BCST.Z m32 k ymm +// VCVTTPS2QQ.BCST.Z m32 k zmm +// Construct and append a VCVTTPS2QQ.BCST.Z instruction to the active function. +func (c *Context) VCVTTPS2QQ_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VCVTTPS2QQ_BCST_Z(m, k, xyz)) +} + +// VCVTTPS2QQ_BCST_Z: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPS2QQ.BCST.Z m32 k xmm +// VCVTTPS2QQ.BCST.Z m32 k ymm +// VCVTTPS2QQ.BCST.Z m32 k zmm +// Construct and append a VCVTTPS2QQ.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTTPS2QQ_BCST_Z(m, k, xyz operand.Op) { ctx.VCVTTPS2QQ_BCST_Z(m, k, xyz) } + +// VCVTTPS2QQ_SAE: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Suppress All Exceptions). +// +// Forms: +// +// VCVTTPS2QQ.SAE ymm k zmm +// VCVTTPS2QQ.SAE ymm zmm +// Construct and append a VCVTTPS2QQ.SAE instruction to the active function. +func (c *Context) VCVTTPS2QQ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPS2QQ_SAE(ops...)) +} + +// VCVTTPS2QQ_SAE: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Suppress All Exceptions). +// +// Forms: +// +// VCVTTPS2QQ.SAE ymm k zmm +// VCVTTPS2QQ.SAE ymm zmm +// Construct and append a VCVTTPS2QQ.SAE instruction to the active function. +// Operates on the global context. +func VCVTTPS2QQ_SAE(ops ...operand.Op) { ctx.VCVTTPS2QQ_SAE(ops...) } + +// VCVTTPS2QQ_SAE_Z: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTTPS2QQ.SAE.Z ymm k zmm +// Construct and append a VCVTTPS2QQ.SAE.Z instruction to the active function. +func (c *Context) VCVTTPS2QQ_SAE_Z(y, k, z operand.Op) { + c.addinstruction(x86.VCVTTPS2QQ_SAE_Z(y, k, z)) +} + +// VCVTTPS2QQ_SAE_Z: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTTPS2QQ.SAE.Z ymm k zmm +// Construct and append a VCVTTPS2QQ.SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTTPS2QQ_SAE_Z(y, k, z operand.Op) { ctx.VCVTTPS2QQ_SAE_Z(y, k, z) } + +// VCVTTPS2QQ_Z: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Zeroing Masking). +// +// Forms: +// +// VCVTTPS2QQ.Z m128 k ymm +// VCVTTPS2QQ.Z m64 k xmm +// VCVTTPS2QQ.Z xmm k xmm +// VCVTTPS2QQ.Z xmm k ymm +// VCVTTPS2QQ.Z m256 k zmm +// VCVTTPS2QQ.Z ymm k zmm +// Construct and append a VCVTTPS2QQ.Z instruction to the active function. +func (c *Context) VCVTTPS2QQ_Z(mxy, k, xyz operand.Op) { + c.addinstruction(x86.VCVTTPS2QQ_Z(mxy, k, xyz)) +} + +// VCVTTPS2QQ_Z: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Zeroing Masking). +// +// Forms: +// +// VCVTTPS2QQ.Z m128 k ymm +// VCVTTPS2QQ.Z m64 k xmm +// VCVTTPS2QQ.Z xmm k xmm +// VCVTTPS2QQ.Z xmm k ymm +// VCVTTPS2QQ.Z m256 k zmm +// VCVTTPS2QQ.Z ymm k zmm +// Construct and append a VCVTTPS2QQ.Z instruction to the active function. +// Operates on the global context. +func VCVTTPS2QQ_Z(mxy, k, xyz operand.Op) { ctx.VCVTTPS2QQ_Z(mxy, k, xyz) } + +// VCVTTPS2UDQ: Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values. +// +// Forms: +// +// VCVTTPS2UDQ m128 k xmm +// VCVTTPS2UDQ m128 xmm +// VCVTTPS2UDQ m256 k ymm +// VCVTTPS2UDQ m256 ymm +// VCVTTPS2UDQ xmm k xmm +// VCVTTPS2UDQ xmm xmm +// VCVTTPS2UDQ ymm k ymm +// VCVTTPS2UDQ ymm ymm +// VCVTTPS2UDQ m512 k zmm +// VCVTTPS2UDQ m512 zmm +// VCVTTPS2UDQ zmm k zmm +// VCVTTPS2UDQ zmm zmm +// Construct and append a VCVTTPS2UDQ instruction to the active function. +func (c *Context) VCVTTPS2UDQ(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPS2UDQ(ops...)) +} + +// VCVTTPS2UDQ: Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values. +// +// Forms: +// +// VCVTTPS2UDQ m128 k xmm +// VCVTTPS2UDQ m128 xmm +// VCVTTPS2UDQ m256 k ymm +// VCVTTPS2UDQ m256 ymm +// VCVTTPS2UDQ xmm k xmm +// VCVTTPS2UDQ xmm xmm +// VCVTTPS2UDQ ymm k ymm +// VCVTTPS2UDQ ymm ymm +// VCVTTPS2UDQ m512 k zmm +// VCVTTPS2UDQ m512 zmm +// VCVTTPS2UDQ zmm k zmm +// VCVTTPS2UDQ zmm zmm +// Construct and append a VCVTTPS2UDQ instruction to the active function. +// Operates on the global context. +func VCVTTPS2UDQ(ops ...operand.Op) { ctx.VCVTTPS2UDQ(ops...) } + +// VCVTTPS2UDQ_BCST: Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Broadcast). +// +// Forms: +// +// VCVTTPS2UDQ.BCST m32 k xmm +// VCVTTPS2UDQ.BCST m32 k ymm +// VCVTTPS2UDQ.BCST m32 xmm +// VCVTTPS2UDQ.BCST m32 ymm +// VCVTTPS2UDQ.BCST m32 k zmm +// VCVTTPS2UDQ.BCST m32 zmm +// Construct and append a VCVTTPS2UDQ.BCST instruction to the active function. +func (c *Context) VCVTTPS2UDQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPS2UDQ_BCST(ops...)) +} + +// VCVTTPS2UDQ_BCST: Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Broadcast). +// +// Forms: +// +// VCVTTPS2UDQ.BCST m32 k xmm +// VCVTTPS2UDQ.BCST m32 k ymm +// VCVTTPS2UDQ.BCST m32 xmm +// VCVTTPS2UDQ.BCST m32 ymm +// VCVTTPS2UDQ.BCST m32 k zmm +// VCVTTPS2UDQ.BCST m32 zmm +// Construct and append a VCVTTPS2UDQ.BCST instruction to the active function. +// Operates on the global context. +func VCVTTPS2UDQ_BCST(ops ...operand.Op) { ctx.VCVTTPS2UDQ_BCST(ops...) } + +// VCVTTPS2UDQ_BCST_Z: Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPS2UDQ.BCST.Z m32 k xmm +// VCVTTPS2UDQ.BCST.Z m32 k ymm +// VCVTTPS2UDQ.BCST.Z m32 k zmm +// Construct and append a VCVTTPS2UDQ.BCST.Z instruction to the active function. +func (c *Context) VCVTTPS2UDQ_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VCVTTPS2UDQ_BCST_Z(m, k, xyz)) +} + +// VCVTTPS2UDQ_BCST_Z: Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPS2UDQ.BCST.Z m32 k xmm +// VCVTTPS2UDQ.BCST.Z m32 k ymm +// VCVTTPS2UDQ.BCST.Z m32 k zmm +// Construct and append a VCVTTPS2UDQ.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTTPS2UDQ_BCST_Z(m, k, xyz operand.Op) { ctx.VCVTTPS2UDQ_BCST_Z(m, k, xyz) } + +// VCVTTPS2UDQ_SAE: Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Suppress All Exceptions). +// +// Forms: +// +// VCVTTPS2UDQ.SAE zmm k zmm +// VCVTTPS2UDQ.SAE zmm zmm +// Construct and append a VCVTTPS2UDQ.SAE instruction to the active function. +func (c *Context) VCVTTPS2UDQ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPS2UDQ_SAE(ops...)) +} + +// VCVTTPS2UDQ_SAE: Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Suppress All Exceptions). +// +// Forms: +// +// VCVTTPS2UDQ.SAE zmm k zmm +// VCVTTPS2UDQ.SAE zmm zmm +// Construct and append a VCVTTPS2UDQ.SAE instruction to the active function. +// Operates on the global context. +func VCVTTPS2UDQ_SAE(ops ...operand.Op) { ctx.VCVTTPS2UDQ_SAE(ops...) } + +// VCVTTPS2UDQ_SAE_Z: Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTTPS2UDQ.SAE.Z zmm k zmm +// Construct and append a VCVTTPS2UDQ.SAE.Z instruction to the active function. +func (c *Context) VCVTTPS2UDQ_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTTPS2UDQ_SAE_Z(z, k, z1)) +} + +// VCVTTPS2UDQ_SAE_Z: Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTTPS2UDQ.SAE.Z zmm k zmm +// Construct and append a VCVTTPS2UDQ.SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTTPS2UDQ_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTTPS2UDQ_SAE_Z(z, k, z1) } + +// VCVTTPS2UDQ_Z: Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Zeroing Masking). +// +// Forms: +// +// VCVTTPS2UDQ.Z m128 k xmm +// VCVTTPS2UDQ.Z m256 k ymm +// VCVTTPS2UDQ.Z xmm k xmm +// VCVTTPS2UDQ.Z ymm k ymm +// VCVTTPS2UDQ.Z m512 k zmm +// VCVTTPS2UDQ.Z zmm k zmm +// Construct and append a VCVTTPS2UDQ.Z instruction to the active function. +func (c *Context) VCVTTPS2UDQ_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VCVTTPS2UDQ_Z(mxyz, k, xyz)) +} + +// VCVTTPS2UDQ_Z: Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Zeroing Masking). +// +// Forms: +// +// VCVTTPS2UDQ.Z m128 k xmm +// VCVTTPS2UDQ.Z m256 k ymm +// VCVTTPS2UDQ.Z xmm k xmm +// VCVTTPS2UDQ.Z ymm k ymm +// VCVTTPS2UDQ.Z m512 k zmm +// VCVTTPS2UDQ.Z zmm k zmm +// Construct and append a VCVTTPS2UDQ.Z instruction to the active function. +// Operates on the global context. +func VCVTTPS2UDQ_Z(mxyz, k, xyz operand.Op) { ctx.VCVTTPS2UDQ_Z(mxyz, k, xyz) } + +// VCVTTPS2UQQ: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values. +// +// Forms: +// +// VCVTTPS2UQQ m128 k ymm +// VCVTTPS2UQQ m128 ymm +// VCVTTPS2UQQ m64 k xmm +// VCVTTPS2UQQ m64 xmm +// VCVTTPS2UQQ xmm k xmm +// VCVTTPS2UQQ xmm k ymm +// VCVTTPS2UQQ xmm xmm +// VCVTTPS2UQQ xmm ymm +// VCVTTPS2UQQ m256 k zmm +// VCVTTPS2UQQ m256 zmm +// VCVTTPS2UQQ ymm k zmm +// VCVTTPS2UQQ ymm zmm +// Construct and append a VCVTTPS2UQQ instruction to the active function. +func (c *Context) VCVTTPS2UQQ(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPS2UQQ(ops...)) +} + +// VCVTTPS2UQQ: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values. +// +// Forms: +// +// VCVTTPS2UQQ m128 k ymm +// VCVTTPS2UQQ m128 ymm +// VCVTTPS2UQQ m64 k xmm +// VCVTTPS2UQQ m64 xmm +// VCVTTPS2UQQ xmm k xmm +// VCVTTPS2UQQ xmm k ymm +// VCVTTPS2UQQ xmm xmm +// VCVTTPS2UQQ xmm ymm +// VCVTTPS2UQQ m256 k zmm +// VCVTTPS2UQQ m256 zmm +// VCVTTPS2UQQ ymm k zmm +// VCVTTPS2UQQ ymm zmm +// Construct and append a VCVTTPS2UQQ instruction to the active function. +// Operates on the global context. +func VCVTTPS2UQQ(ops ...operand.Op) { ctx.VCVTTPS2UQQ(ops...) } + +// VCVTTPS2UQQ_BCST: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Broadcast). +// +// Forms: +// +// VCVTTPS2UQQ.BCST m32 k xmm +// VCVTTPS2UQQ.BCST m32 k ymm +// VCVTTPS2UQQ.BCST m32 xmm +// VCVTTPS2UQQ.BCST m32 ymm +// VCVTTPS2UQQ.BCST m32 k zmm +// VCVTTPS2UQQ.BCST m32 zmm +// Construct and append a VCVTTPS2UQQ.BCST instruction to the active function. +func (c *Context) VCVTTPS2UQQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPS2UQQ_BCST(ops...)) +} + +// VCVTTPS2UQQ_BCST: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Broadcast). +// +// Forms: +// +// VCVTTPS2UQQ.BCST m32 k xmm +// VCVTTPS2UQQ.BCST m32 k ymm +// VCVTTPS2UQQ.BCST m32 xmm +// VCVTTPS2UQQ.BCST m32 ymm +// VCVTTPS2UQQ.BCST m32 k zmm +// VCVTTPS2UQQ.BCST m32 zmm +// Construct and append a VCVTTPS2UQQ.BCST instruction to the active function. +// Operates on the global context. +func VCVTTPS2UQQ_BCST(ops ...operand.Op) { ctx.VCVTTPS2UQQ_BCST(ops...) } + +// VCVTTPS2UQQ_BCST_Z: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPS2UQQ.BCST.Z m32 k xmm +// VCVTTPS2UQQ.BCST.Z m32 k ymm +// VCVTTPS2UQQ.BCST.Z m32 k zmm +// Construct and append a VCVTTPS2UQQ.BCST.Z instruction to the active function. +func (c *Context) VCVTTPS2UQQ_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VCVTTPS2UQQ_BCST_Z(m, k, xyz)) +} + +// VCVTTPS2UQQ_BCST_Z: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPS2UQQ.BCST.Z m32 k xmm +// VCVTTPS2UQQ.BCST.Z m32 k ymm +// VCVTTPS2UQQ.BCST.Z m32 k zmm +// Construct and append a VCVTTPS2UQQ.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTTPS2UQQ_BCST_Z(m, k, xyz operand.Op) { ctx.VCVTTPS2UQQ_BCST_Z(m, k, xyz) } + +// VCVTTPS2UQQ_SAE: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Suppress All Exceptions). +// +// Forms: +// +// VCVTTPS2UQQ.SAE ymm k zmm +// VCVTTPS2UQQ.SAE ymm zmm +// Construct and append a VCVTTPS2UQQ.SAE instruction to the active function. +func (c *Context) VCVTTPS2UQQ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTTPS2UQQ_SAE(ops...)) +} + +// VCVTTPS2UQQ_SAE: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Suppress All Exceptions). +// +// Forms: +// +// VCVTTPS2UQQ.SAE ymm k zmm +// VCVTTPS2UQQ.SAE ymm zmm +// Construct and append a VCVTTPS2UQQ.SAE instruction to the active function. +// Operates on the global context. +func VCVTTPS2UQQ_SAE(ops ...operand.Op) { ctx.VCVTTPS2UQQ_SAE(ops...) } + +// VCVTTPS2UQQ_SAE_Z: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTTPS2UQQ.SAE.Z ymm k zmm +// Construct and append a VCVTTPS2UQQ.SAE.Z instruction to the active function. +func (c *Context) VCVTTPS2UQQ_SAE_Z(y, k, z operand.Op) { + c.addinstruction(x86.VCVTTPS2UQQ_SAE_Z(y, k, z)) +} + +// VCVTTPS2UQQ_SAE_Z: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTTPS2UQQ.SAE.Z ymm k zmm +// Construct and append a VCVTTPS2UQQ.SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTTPS2UQQ_SAE_Z(y, k, z operand.Op) { ctx.VCVTTPS2UQQ_SAE_Z(y, k, z) } + +// VCVTTPS2UQQ_Z: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Zeroing Masking). +// +// Forms: +// +// VCVTTPS2UQQ.Z m128 k ymm +// VCVTTPS2UQQ.Z m64 k xmm +// VCVTTPS2UQQ.Z xmm k xmm +// VCVTTPS2UQQ.Z xmm k ymm +// VCVTTPS2UQQ.Z m256 k zmm +// VCVTTPS2UQQ.Z ymm k zmm +// Construct and append a VCVTTPS2UQQ.Z instruction to the active function. +func (c *Context) VCVTTPS2UQQ_Z(mxy, k, xyz operand.Op) { + c.addinstruction(x86.VCVTTPS2UQQ_Z(mxy, k, xyz)) +} + +// VCVTTPS2UQQ_Z: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Zeroing Masking). +// +// Forms: +// +// VCVTTPS2UQQ.Z m128 k ymm +// VCVTTPS2UQQ.Z m64 k xmm +// VCVTTPS2UQQ.Z xmm k xmm +// VCVTTPS2UQQ.Z xmm k ymm +// VCVTTPS2UQQ.Z m256 k zmm +// VCVTTPS2UQQ.Z ymm k zmm +// Construct and append a VCVTTPS2UQQ.Z instruction to the active function. +// Operates on the global context. +func VCVTTPS2UQQ_Z(mxy, k, xyz operand.Op) { ctx.VCVTTPS2UQQ_Z(mxy, k, xyz) } + +// VCVTTSD2SI: Convert with Truncation Scalar Double-Precision FP Value to Signed Integer. +// +// Forms: +// +// VCVTTSD2SI m64 r32 +// VCVTTSD2SI xmm r32 +// Construct and append a VCVTTSD2SI instruction to the active function. +func (c *Context) VCVTTSD2SI(mx, r operand.Op) { + c.addinstruction(x86.VCVTTSD2SI(mx, r)) +} + +// VCVTTSD2SI: Convert with Truncation Scalar Double-Precision FP Value to Signed Integer. +// +// Forms: +// +// VCVTTSD2SI m64 r32 +// VCVTTSD2SI xmm r32 +// Construct and append a VCVTTSD2SI instruction to the active function. +// Operates on the global context. +func VCVTTSD2SI(mx, r operand.Op) { ctx.VCVTTSD2SI(mx, r) } + +// VCVTTSD2SIQ: Convert with Truncation Scalar Double-Precision FP Value to Signed Integer. +// +// Forms: +// +// VCVTTSD2SIQ m64 r64 +// VCVTTSD2SIQ xmm r64 +// Construct and append a VCVTTSD2SIQ instruction to the active function. +func (c *Context) VCVTTSD2SIQ(mx, r operand.Op) { + c.addinstruction(x86.VCVTTSD2SIQ(mx, r)) +} + +// VCVTTSD2SIQ: Convert with Truncation Scalar Double-Precision FP Value to Signed Integer. +// +// Forms: +// +// VCVTTSD2SIQ m64 r64 +// VCVTTSD2SIQ xmm r64 +// Construct and append a VCVTTSD2SIQ instruction to the active function. +// Operates on the global context. +func VCVTTSD2SIQ(mx, r operand.Op) { ctx.VCVTTSD2SIQ(mx, r) } + +// VCVTTSD2SIQ_SAE: Convert with Truncation Scalar Double-Precision FP Value to Signed Integer (Suppress All Exceptions). +// +// Forms: +// +// VCVTTSD2SIQ.SAE xmm r64 +// Construct and append a VCVTTSD2SIQ.SAE instruction to the active function. +func (c *Context) VCVTTSD2SIQ_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTTSD2SIQ_SAE(x, r)) +} + +// VCVTTSD2SIQ_SAE: Convert with Truncation Scalar Double-Precision FP Value to Signed Integer (Suppress All Exceptions). +// +// Forms: +// +// VCVTTSD2SIQ.SAE xmm r64 +// Construct and append a VCVTTSD2SIQ.SAE instruction to the active function. +// Operates on the global context. +func VCVTTSD2SIQ_SAE(x, r operand.Op) { ctx.VCVTTSD2SIQ_SAE(x, r) } + +// VCVTTSD2SI_SAE: Convert with Truncation Scalar Double-Precision FP Value to Signed Integer (Suppress All Exceptions). +// +// Forms: +// +// VCVTTSD2SI.SAE xmm r32 +// Construct and append a VCVTTSD2SI.SAE instruction to the active function. +func (c *Context) VCVTTSD2SI_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTTSD2SI_SAE(x, r)) +} + +// VCVTTSD2SI_SAE: Convert with Truncation Scalar Double-Precision FP Value to Signed Integer (Suppress All Exceptions). +// +// Forms: +// +// VCVTTSD2SI.SAE xmm r32 +// Construct and append a VCVTTSD2SI.SAE instruction to the active function. +// Operates on the global context. +func VCVTTSD2SI_SAE(x, r operand.Op) { ctx.VCVTTSD2SI_SAE(x, r) } + +// VCVTTSD2USIL: Convert with Truncation Scalar Double-Precision Floating-Point Value to Unsigned Integer. +// +// Forms: +// +// VCVTTSD2USIL m64 r32 +// VCVTTSD2USIL xmm r32 +// Construct and append a VCVTTSD2USIL instruction to the active function. +func (c *Context) VCVTTSD2USIL(mx, r operand.Op) { + c.addinstruction(x86.VCVTTSD2USIL(mx, r)) +} + +// VCVTTSD2USIL: Convert with Truncation Scalar Double-Precision Floating-Point Value to Unsigned Integer. +// +// Forms: +// +// VCVTTSD2USIL m64 r32 +// VCVTTSD2USIL xmm r32 +// Construct and append a VCVTTSD2USIL instruction to the active function. +// Operates on the global context. +func VCVTTSD2USIL(mx, r operand.Op) { ctx.VCVTTSD2USIL(mx, r) } + +// VCVTTSD2USIL_SAE: Convert with Truncation Scalar Double-Precision Floating-Point Value to Unsigned Integer (Suppress All Exceptions). +// +// Forms: +// +// VCVTTSD2USIL.SAE xmm r32 +// Construct and append a VCVTTSD2USIL.SAE instruction to the active function. +func (c *Context) VCVTTSD2USIL_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTTSD2USIL_SAE(x, r)) +} + +// VCVTTSD2USIL_SAE: Convert with Truncation Scalar Double-Precision Floating-Point Value to Unsigned Integer (Suppress All Exceptions). +// +// Forms: +// +// VCVTTSD2USIL.SAE xmm r32 +// Construct and append a VCVTTSD2USIL.SAE instruction to the active function. +// Operates on the global context. +func VCVTTSD2USIL_SAE(x, r operand.Op) { ctx.VCVTTSD2USIL_SAE(x, r) } + +// VCVTTSD2USIQ: Convert with Truncation Scalar Double-Precision Floating-Point Value to Unsigned Integer. +// +// Forms: +// +// VCVTTSD2USIQ m64 r64 +// VCVTTSD2USIQ xmm r64 +// Construct and append a VCVTTSD2USIQ instruction to the active function. +func (c *Context) VCVTTSD2USIQ(mx, r operand.Op) { + c.addinstruction(x86.VCVTTSD2USIQ(mx, r)) +} + +// VCVTTSD2USIQ: Convert with Truncation Scalar Double-Precision Floating-Point Value to Unsigned Integer. +// +// Forms: +// +// VCVTTSD2USIQ m64 r64 +// VCVTTSD2USIQ xmm r64 +// Construct and append a VCVTTSD2USIQ instruction to the active function. +// Operates on the global context. +func VCVTTSD2USIQ(mx, r operand.Op) { ctx.VCVTTSD2USIQ(mx, r) } + +// VCVTTSD2USIQ_SAE: Convert with Truncation Scalar Double-Precision Floating-Point Value to Unsigned Integer (Suppress All Exceptions). +// +// Forms: +// +// VCVTTSD2USIQ.SAE xmm r64 +// Construct and append a VCVTTSD2USIQ.SAE instruction to the active function. +func (c *Context) VCVTTSD2USIQ_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTTSD2USIQ_SAE(x, r)) +} + +// VCVTTSD2USIQ_SAE: Convert with Truncation Scalar Double-Precision Floating-Point Value to Unsigned Integer (Suppress All Exceptions). +// +// Forms: +// +// VCVTTSD2USIQ.SAE xmm r64 +// Construct and append a VCVTTSD2USIQ.SAE instruction to the active function. +// Operates on the global context. +func VCVTTSD2USIQ_SAE(x, r operand.Op) { ctx.VCVTTSD2USIQ_SAE(x, r) } + +// VCVTTSS2SI: Convert with Truncation Scalar Single-Precision FP Value to Dword Integer. +// +// Forms: +// +// VCVTTSS2SI m32 r32 +// VCVTTSS2SI xmm r32 +// Construct and append a VCVTTSS2SI instruction to the active function. +func (c *Context) VCVTTSS2SI(mx, r operand.Op) { + c.addinstruction(x86.VCVTTSS2SI(mx, r)) +} + +// VCVTTSS2SI: Convert with Truncation Scalar Single-Precision FP Value to Dword Integer. +// +// Forms: +// +// VCVTTSS2SI m32 r32 +// VCVTTSS2SI xmm r32 +// Construct and append a VCVTTSS2SI instruction to the active function. +// Operates on the global context. +func VCVTTSS2SI(mx, r operand.Op) { ctx.VCVTTSS2SI(mx, r) } + +// VCVTTSS2SIQ: Convert with Truncation Scalar Single-Precision FP Value to Dword Integer. +// +// Forms: +// +// VCVTTSS2SIQ m32 r64 +// VCVTTSS2SIQ xmm r64 +// Construct and append a VCVTTSS2SIQ instruction to the active function. +func (c *Context) VCVTTSS2SIQ(mx, r operand.Op) { + c.addinstruction(x86.VCVTTSS2SIQ(mx, r)) +} + +// VCVTTSS2SIQ: Convert with Truncation Scalar Single-Precision FP Value to Dword Integer. +// +// Forms: +// +// VCVTTSS2SIQ m32 r64 +// VCVTTSS2SIQ xmm r64 +// Construct and append a VCVTTSS2SIQ instruction to the active function. +// Operates on the global context. +func VCVTTSS2SIQ(mx, r operand.Op) { ctx.VCVTTSS2SIQ(mx, r) } + +// VCVTTSS2SIQ_SAE: Convert with Truncation Scalar Single-Precision FP Value to Dword Integer (Suppress All Exceptions). +// +// Forms: +// +// VCVTTSS2SIQ.SAE xmm r64 +// Construct and append a VCVTTSS2SIQ.SAE instruction to the active function. +func (c *Context) VCVTTSS2SIQ_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTTSS2SIQ_SAE(x, r)) +} + +// VCVTTSS2SIQ_SAE: Convert with Truncation Scalar Single-Precision FP Value to Dword Integer (Suppress All Exceptions). +// +// Forms: +// +// VCVTTSS2SIQ.SAE xmm r64 +// Construct and append a VCVTTSS2SIQ.SAE instruction to the active function. +// Operates on the global context. +func VCVTTSS2SIQ_SAE(x, r operand.Op) { ctx.VCVTTSS2SIQ_SAE(x, r) } + +// VCVTTSS2SI_SAE: Convert with Truncation Scalar Single-Precision FP Value to Dword Integer (Suppress All Exceptions). +// +// Forms: +// +// VCVTTSS2SI.SAE xmm r32 +// Construct and append a VCVTTSS2SI.SAE instruction to the active function. +func (c *Context) VCVTTSS2SI_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTTSS2SI_SAE(x, r)) +} + +// VCVTTSS2SI_SAE: Convert with Truncation Scalar Single-Precision FP Value to Dword Integer (Suppress All Exceptions). +// +// Forms: +// +// VCVTTSS2SI.SAE xmm r32 +// Construct and append a VCVTTSS2SI.SAE instruction to the active function. +// Operates on the global context. +func VCVTTSS2SI_SAE(x, r operand.Op) { ctx.VCVTTSS2SI_SAE(x, r) } + +// VCVTTSS2USIL: Convert with Truncation Scalar Single-Precision Floating-Point Value to Unsigned Integer. +// +// Forms: +// +// VCVTTSS2USIL m32 r32 +// VCVTTSS2USIL xmm r32 +// Construct and append a VCVTTSS2USIL instruction to the active function. +func (c *Context) VCVTTSS2USIL(mx, r operand.Op) { + c.addinstruction(x86.VCVTTSS2USIL(mx, r)) +} + +// VCVTTSS2USIL: Convert with Truncation Scalar Single-Precision Floating-Point Value to Unsigned Integer. +// +// Forms: +// +// VCVTTSS2USIL m32 r32 +// VCVTTSS2USIL xmm r32 +// Construct and append a VCVTTSS2USIL instruction to the active function. +// Operates on the global context. +func VCVTTSS2USIL(mx, r operand.Op) { ctx.VCVTTSS2USIL(mx, r) } + +// VCVTTSS2USIL_SAE: Convert with Truncation Scalar Single-Precision Floating-Point Value to Unsigned Integer (Suppress All Exceptions). +// +// Forms: +// +// VCVTTSS2USIL.SAE xmm r32 +// Construct and append a VCVTTSS2USIL.SAE instruction to the active function. +func (c *Context) VCVTTSS2USIL_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTTSS2USIL_SAE(x, r)) +} + +// VCVTTSS2USIL_SAE: Convert with Truncation Scalar Single-Precision Floating-Point Value to Unsigned Integer (Suppress All Exceptions). +// +// Forms: +// +// VCVTTSS2USIL.SAE xmm r32 +// Construct and append a VCVTTSS2USIL.SAE instruction to the active function. +// Operates on the global context. +func VCVTTSS2USIL_SAE(x, r operand.Op) { ctx.VCVTTSS2USIL_SAE(x, r) } + +// VCVTTSS2USIQ: Convert with Truncation Scalar Single-Precision Floating-Point Value to Unsigned Integer. +// +// Forms: +// +// VCVTTSS2USIQ m32 r64 +// VCVTTSS2USIQ xmm r64 +// Construct and append a VCVTTSS2USIQ instruction to the active function. +func (c *Context) VCVTTSS2USIQ(mx, r operand.Op) { + c.addinstruction(x86.VCVTTSS2USIQ(mx, r)) +} + +// VCVTTSS2USIQ: Convert with Truncation Scalar Single-Precision Floating-Point Value to Unsigned Integer. +// +// Forms: +// +// VCVTTSS2USIQ m32 r64 +// VCVTTSS2USIQ xmm r64 +// Construct and append a VCVTTSS2USIQ instruction to the active function. +// Operates on the global context. +func VCVTTSS2USIQ(mx, r operand.Op) { ctx.VCVTTSS2USIQ(mx, r) } + +// VCVTTSS2USIQ_SAE: Convert with Truncation Scalar Single-Precision Floating-Point Value to Unsigned Integer (Suppress All Exceptions). +// +// Forms: +// +// VCVTTSS2USIQ.SAE xmm r64 +// Construct and append a VCVTTSS2USIQ.SAE instruction to the active function. +func (c *Context) VCVTTSS2USIQ_SAE(x, r operand.Op) { + c.addinstruction(x86.VCVTTSS2USIQ_SAE(x, r)) +} + +// VCVTTSS2USIQ_SAE: Convert with Truncation Scalar Single-Precision Floating-Point Value to Unsigned Integer (Suppress All Exceptions). +// +// Forms: +// +// VCVTTSS2USIQ.SAE xmm r64 +// Construct and append a VCVTTSS2USIQ.SAE instruction to the active function. +// Operates on the global context. +func VCVTTSS2USIQ_SAE(x, r operand.Op) { ctx.VCVTTSS2USIQ_SAE(x, r) } + +// VCVTUDQ2PD: Convert Packed Unsigned Doubleword Integers to Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VCVTUDQ2PD m128 k ymm +// VCVTUDQ2PD m128 ymm +// VCVTUDQ2PD m64 k xmm +// VCVTUDQ2PD m64 xmm +// VCVTUDQ2PD xmm k xmm +// VCVTUDQ2PD xmm k ymm +// VCVTUDQ2PD xmm xmm +// VCVTUDQ2PD xmm ymm +// VCVTUDQ2PD m256 k zmm +// VCVTUDQ2PD m256 zmm +// VCVTUDQ2PD ymm k zmm +// VCVTUDQ2PD ymm zmm +// Construct and append a VCVTUDQ2PD instruction to the active function. +func (c *Context) VCVTUDQ2PD(ops ...operand.Op) { + c.addinstruction(x86.VCVTUDQ2PD(ops...)) +} + +// VCVTUDQ2PD: Convert Packed Unsigned Doubleword Integers to Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VCVTUDQ2PD m128 k ymm +// VCVTUDQ2PD m128 ymm +// VCVTUDQ2PD m64 k xmm +// VCVTUDQ2PD m64 xmm +// VCVTUDQ2PD xmm k xmm +// VCVTUDQ2PD xmm k ymm +// VCVTUDQ2PD xmm xmm +// VCVTUDQ2PD xmm ymm +// VCVTUDQ2PD m256 k zmm +// VCVTUDQ2PD m256 zmm +// VCVTUDQ2PD ymm k zmm +// VCVTUDQ2PD ymm zmm +// Construct and append a VCVTUDQ2PD instruction to the active function. +// Operates on the global context. +func VCVTUDQ2PD(ops ...operand.Op) { ctx.VCVTUDQ2PD(ops...) } + +// VCVTUDQ2PD_BCST: Convert Packed Unsigned Doubleword Integers to Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCVTUDQ2PD.BCST m32 k xmm +// VCVTUDQ2PD.BCST m32 k ymm +// VCVTUDQ2PD.BCST m32 xmm +// VCVTUDQ2PD.BCST m32 ymm +// VCVTUDQ2PD.BCST m32 k zmm +// VCVTUDQ2PD.BCST m32 zmm +// Construct and append a VCVTUDQ2PD.BCST instruction to the active function. +func (c *Context) VCVTUDQ2PD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTUDQ2PD_BCST(ops...)) +} + +// VCVTUDQ2PD_BCST: Convert Packed Unsigned Doubleword Integers to Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCVTUDQ2PD.BCST m32 k xmm +// VCVTUDQ2PD.BCST m32 k ymm +// VCVTUDQ2PD.BCST m32 xmm +// VCVTUDQ2PD.BCST m32 ymm +// VCVTUDQ2PD.BCST m32 k zmm +// VCVTUDQ2PD.BCST m32 zmm +// Construct and append a VCVTUDQ2PD.BCST instruction to the active function. +// Operates on the global context. +func VCVTUDQ2PD_BCST(ops ...operand.Op) { ctx.VCVTUDQ2PD_BCST(ops...) } + +// VCVTUDQ2PD_BCST_Z: Convert Packed Unsigned Doubleword Integers to Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTUDQ2PD.BCST.Z m32 k xmm +// VCVTUDQ2PD.BCST.Z m32 k ymm +// VCVTUDQ2PD.BCST.Z m32 k zmm +// Construct and append a VCVTUDQ2PD.BCST.Z instruction to the active function. +func (c *Context) VCVTUDQ2PD_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VCVTUDQ2PD_BCST_Z(m, k, xyz)) +} + +// VCVTUDQ2PD_BCST_Z: Convert Packed Unsigned Doubleword Integers to Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTUDQ2PD.BCST.Z m32 k xmm +// VCVTUDQ2PD.BCST.Z m32 k ymm +// VCVTUDQ2PD.BCST.Z m32 k zmm +// Construct and append a VCVTUDQ2PD.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTUDQ2PD_BCST_Z(m, k, xyz operand.Op) { ctx.VCVTUDQ2PD_BCST_Z(m, k, xyz) } + +// VCVTUDQ2PD_Z: Convert Packed Unsigned Doubleword Integers to Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VCVTUDQ2PD.Z m128 k ymm +// VCVTUDQ2PD.Z m64 k xmm +// VCVTUDQ2PD.Z xmm k xmm +// VCVTUDQ2PD.Z xmm k ymm +// VCVTUDQ2PD.Z m256 k zmm +// VCVTUDQ2PD.Z ymm k zmm +// Construct and append a VCVTUDQ2PD.Z instruction to the active function. +func (c *Context) VCVTUDQ2PD_Z(mxy, k, xyz operand.Op) { + c.addinstruction(x86.VCVTUDQ2PD_Z(mxy, k, xyz)) +} + +// VCVTUDQ2PD_Z: Convert Packed Unsigned Doubleword Integers to Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VCVTUDQ2PD.Z m128 k ymm +// VCVTUDQ2PD.Z m64 k xmm +// VCVTUDQ2PD.Z xmm k xmm +// VCVTUDQ2PD.Z xmm k ymm +// VCVTUDQ2PD.Z m256 k zmm +// VCVTUDQ2PD.Z ymm k zmm +// Construct and append a VCVTUDQ2PD.Z instruction to the active function. +// Operates on the global context. +func VCVTUDQ2PD_Z(mxy, k, xyz operand.Op) { ctx.VCVTUDQ2PD_Z(mxy, k, xyz) } + +// VCVTUDQ2PS: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VCVTUDQ2PS m128 k xmm +// VCVTUDQ2PS m128 xmm +// VCVTUDQ2PS m256 k ymm +// VCVTUDQ2PS m256 ymm +// VCVTUDQ2PS xmm k xmm +// VCVTUDQ2PS xmm xmm +// VCVTUDQ2PS ymm k ymm +// VCVTUDQ2PS ymm ymm +// VCVTUDQ2PS m512 k zmm +// VCVTUDQ2PS m512 zmm +// VCVTUDQ2PS zmm k zmm +// VCVTUDQ2PS zmm zmm +// Construct and append a VCVTUDQ2PS instruction to the active function. +func (c *Context) VCVTUDQ2PS(ops ...operand.Op) { + c.addinstruction(x86.VCVTUDQ2PS(ops...)) +} + +// VCVTUDQ2PS: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VCVTUDQ2PS m128 k xmm +// VCVTUDQ2PS m128 xmm +// VCVTUDQ2PS m256 k ymm +// VCVTUDQ2PS m256 ymm +// VCVTUDQ2PS xmm k xmm +// VCVTUDQ2PS xmm xmm +// VCVTUDQ2PS ymm k ymm +// VCVTUDQ2PS ymm ymm +// VCVTUDQ2PS m512 k zmm +// VCVTUDQ2PS m512 zmm +// VCVTUDQ2PS zmm k zmm +// VCVTUDQ2PS zmm zmm +// Construct and append a VCVTUDQ2PS instruction to the active function. +// Operates on the global context. +func VCVTUDQ2PS(ops ...operand.Op) { ctx.VCVTUDQ2PS(ops...) } + +// VCVTUDQ2PS_BCST: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCVTUDQ2PS.BCST m32 k xmm +// VCVTUDQ2PS.BCST m32 k ymm +// VCVTUDQ2PS.BCST m32 xmm +// VCVTUDQ2PS.BCST m32 ymm +// VCVTUDQ2PS.BCST m32 k zmm +// VCVTUDQ2PS.BCST m32 zmm +// Construct and append a VCVTUDQ2PS.BCST instruction to the active function. +func (c *Context) VCVTUDQ2PS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTUDQ2PS_BCST(ops...)) +} + +// VCVTUDQ2PS_BCST: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCVTUDQ2PS.BCST m32 k xmm +// VCVTUDQ2PS.BCST m32 k ymm +// VCVTUDQ2PS.BCST m32 xmm +// VCVTUDQ2PS.BCST m32 ymm +// VCVTUDQ2PS.BCST m32 k zmm +// VCVTUDQ2PS.BCST m32 zmm +// Construct and append a VCVTUDQ2PS.BCST instruction to the active function. +// Operates on the global context. +func VCVTUDQ2PS_BCST(ops ...operand.Op) { ctx.VCVTUDQ2PS_BCST(ops...) } + +// VCVTUDQ2PS_BCST_Z: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTUDQ2PS.BCST.Z m32 k xmm +// VCVTUDQ2PS.BCST.Z m32 k ymm +// VCVTUDQ2PS.BCST.Z m32 k zmm +// Construct and append a VCVTUDQ2PS.BCST.Z instruction to the active function. +func (c *Context) VCVTUDQ2PS_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VCVTUDQ2PS_BCST_Z(m, k, xyz)) +} + +// VCVTUDQ2PS_BCST_Z: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTUDQ2PS.BCST.Z m32 k xmm +// VCVTUDQ2PS.BCST.Z m32 k ymm +// VCVTUDQ2PS.BCST.Z m32 k zmm +// Construct and append a VCVTUDQ2PS.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTUDQ2PS_BCST_Z(m, k, xyz operand.Op) { ctx.VCVTUDQ2PS_BCST_Z(m, k, xyz) } + +// VCVTUDQ2PS_RD_SAE: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTUDQ2PS.RD_SAE zmm k zmm +// VCVTUDQ2PS.RD_SAE zmm zmm +// Construct and append a VCVTUDQ2PS.RD_SAE instruction to the active function. +func (c *Context) VCVTUDQ2PS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTUDQ2PS_RD_SAE(ops...)) +} + +// VCVTUDQ2PS_RD_SAE: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTUDQ2PS.RD_SAE zmm k zmm +// VCVTUDQ2PS.RD_SAE zmm zmm +// Construct and append a VCVTUDQ2PS.RD_SAE instruction to the active function. +// Operates on the global context. +func VCVTUDQ2PS_RD_SAE(ops ...operand.Op) { ctx.VCVTUDQ2PS_RD_SAE(ops...) } + +// VCVTUDQ2PS_RD_SAE_Z: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTUDQ2PS.RD_SAE.Z zmm k zmm +// Construct and append a VCVTUDQ2PS.RD_SAE.Z instruction to the active function. +func (c *Context) VCVTUDQ2PS_RD_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTUDQ2PS_RD_SAE_Z(z, k, z1)) +} + +// VCVTUDQ2PS_RD_SAE_Z: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTUDQ2PS.RD_SAE.Z zmm k zmm +// Construct and append a VCVTUDQ2PS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTUDQ2PS_RD_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTUDQ2PS_RD_SAE_Z(z, k, z1) } + +// VCVTUDQ2PS_RN_SAE: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VCVTUDQ2PS.RN_SAE zmm k zmm +// VCVTUDQ2PS.RN_SAE zmm zmm +// Construct and append a VCVTUDQ2PS.RN_SAE instruction to the active function. +func (c *Context) VCVTUDQ2PS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTUDQ2PS_RN_SAE(ops...)) +} + +// VCVTUDQ2PS_RN_SAE: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VCVTUDQ2PS.RN_SAE zmm k zmm +// VCVTUDQ2PS.RN_SAE zmm zmm +// Construct and append a VCVTUDQ2PS.RN_SAE instruction to the active function. +// Operates on the global context. +func VCVTUDQ2PS_RN_SAE(ops ...operand.Op) { ctx.VCVTUDQ2PS_RN_SAE(ops...) } + +// VCVTUDQ2PS_RN_SAE_Z: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTUDQ2PS.RN_SAE.Z zmm k zmm +// Construct and append a VCVTUDQ2PS.RN_SAE.Z instruction to the active function. +func (c *Context) VCVTUDQ2PS_RN_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTUDQ2PS_RN_SAE_Z(z, k, z1)) +} + +// VCVTUDQ2PS_RN_SAE_Z: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTUDQ2PS.RN_SAE.Z zmm k zmm +// Construct and append a VCVTUDQ2PS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTUDQ2PS_RN_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTUDQ2PS_RN_SAE_Z(z, k, z1) } + +// VCVTUDQ2PS_RU_SAE: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTUDQ2PS.RU_SAE zmm k zmm +// VCVTUDQ2PS.RU_SAE zmm zmm +// Construct and append a VCVTUDQ2PS.RU_SAE instruction to the active function. +func (c *Context) VCVTUDQ2PS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTUDQ2PS_RU_SAE(ops...)) +} + +// VCVTUDQ2PS_RU_SAE: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTUDQ2PS.RU_SAE zmm k zmm +// VCVTUDQ2PS.RU_SAE zmm zmm +// Construct and append a VCVTUDQ2PS.RU_SAE instruction to the active function. +// Operates on the global context. +func VCVTUDQ2PS_RU_SAE(ops ...operand.Op) { ctx.VCVTUDQ2PS_RU_SAE(ops...) } + +// VCVTUDQ2PS_RU_SAE_Z: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTUDQ2PS.RU_SAE.Z zmm k zmm +// Construct and append a VCVTUDQ2PS.RU_SAE.Z instruction to the active function. +func (c *Context) VCVTUDQ2PS_RU_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTUDQ2PS_RU_SAE_Z(z, k, z1)) +} + +// VCVTUDQ2PS_RU_SAE_Z: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTUDQ2PS.RU_SAE.Z zmm k zmm +// Construct and append a VCVTUDQ2PS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTUDQ2PS_RU_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTUDQ2PS_RU_SAE_Z(z, k, z1) } + +// VCVTUDQ2PS_RZ_SAE: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VCVTUDQ2PS.RZ_SAE zmm k zmm +// VCVTUDQ2PS.RZ_SAE zmm zmm +// Construct and append a VCVTUDQ2PS.RZ_SAE instruction to the active function. +func (c *Context) VCVTUDQ2PS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTUDQ2PS_RZ_SAE(ops...)) +} + +// VCVTUDQ2PS_RZ_SAE: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VCVTUDQ2PS.RZ_SAE zmm k zmm +// VCVTUDQ2PS.RZ_SAE zmm zmm +// Construct and append a VCVTUDQ2PS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VCVTUDQ2PS_RZ_SAE(ops ...operand.Op) { ctx.VCVTUDQ2PS_RZ_SAE(ops...) } + +// VCVTUDQ2PS_RZ_SAE_Z: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTUDQ2PS.RZ_SAE.Z zmm k zmm +// Construct and append a VCVTUDQ2PS.RZ_SAE.Z instruction to the active function. +func (c *Context) VCVTUDQ2PS_RZ_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTUDQ2PS_RZ_SAE_Z(z, k, z1)) +} + +// VCVTUDQ2PS_RZ_SAE_Z: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTUDQ2PS.RZ_SAE.Z zmm k zmm +// Construct and append a VCVTUDQ2PS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTUDQ2PS_RZ_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTUDQ2PS_RZ_SAE_Z(z, k, z1) } + +// VCVTUDQ2PS_Z: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VCVTUDQ2PS.Z m128 k xmm +// VCVTUDQ2PS.Z m256 k ymm +// VCVTUDQ2PS.Z xmm k xmm +// VCVTUDQ2PS.Z ymm k ymm +// VCVTUDQ2PS.Z m512 k zmm +// VCVTUDQ2PS.Z zmm k zmm +// Construct and append a VCVTUDQ2PS.Z instruction to the active function. +func (c *Context) VCVTUDQ2PS_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VCVTUDQ2PS_Z(mxyz, k, xyz)) +} + +// VCVTUDQ2PS_Z: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VCVTUDQ2PS.Z m128 k xmm +// VCVTUDQ2PS.Z m256 k ymm +// VCVTUDQ2PS.Z xmm k xmm +// VCVTUDQ2PS.Z ymm k ymm +// VCVTUDQ2PS.Z m512 k zmm +// VCVTUDQ2PS.Z zmm k zmm +// Construct and append a VCVTUDQ2PS.Z instruction to the active function. +// Operates on the global context. +func VCVTUDQ2PS_Z(mxyz, k, xyz operand.Op) { ctx.VCVTUDQ2PS_Z(mxyz, k, xyz) } + +// VCVTUQQ2PD: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VCVTUQQ2PD m128 k xmm +// VCVTUQQ2PD m128 xmm +// VCVTUQQ2PD m256 k ymm +// VCVTUQQ2PD m256 ymm +// VCVTUQQ2PD xmm k xmm +// VCVTUQQ2PD xmm xmm +// VCVTUQQ2PD ymm k ymm +// VCVTUQQ2PD ymm ymm +// VCVTUQQ2PD m512 k zmm +// VCVTUQQ2PD m512 zmm +// VCVTUQQ2PD zmm k zmm +// VCVTUQQ2PD zmm zmm +// Construct and append a VCVTUQQ2PD instruction to the active function. +func (c *Context) VCVTUQQ2PD(ops ...operand.Op) { + c.addinstruction(x86.VCVTUQQ2PD(ops...)) +} + +// VCVTUQQ2PD: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VCVTUQQ2PD m128 k xmm +// VCVTUQQ2PD m128 xmm +// VCVTUQQ2PD m256 k ymm +// VCVTUQQ2PD m256 ymm +// VCVTUQQ2PD xmm k xmm +// VCVTUQQ2PD xmm xmm +// VCVTUQQ2PD ymm k ymm +// VCVTUQQ2PD ymm ymm +// VCVTUQQ2PD m512 k zmm +// VCVTUQQ2PD m512 zmm +// VCVTUQQ2PD zmm k zmm +// VCVTUQQ2PD zmm zmm +// Construct and append a VCVTUQQ2PD instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PD(ops ...operand.Op) { ctx.VCVTUQQ2PD(ops...) } + +// VCVTUQQ2PD_BCST: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCVTUQQ2PD.BCST m64 k xmm +// VCVTUQQ2PD.BCST m64 k ymm +// VCVTUQQ2PD.BCST m64 xmm +// VCVTUQQ2PD.BCST m64 ymm +// VCVTUQQ2PD.BCST m64 k zmm +// VCVTUQQ2PD.BCST m64 zmm +// Construct and append a VCVTUQQ2PD.BCST instruction to the active function. +func (c *Context) VCVTUQQ2PD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTUQQ2PD_BCST(ops...)) +} + +// VCVTUQQ2PD_BCST: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCVTUQQ2PD.BCST m64 k xmm +// VCVTUQQ2PD.BCST m64 k ymm +// VCVTUQQ2PD.BCST m64 xmm +// VCVTUQQ2PD.BCST m64 ymm +// VCVTUQQ2PD.BCST m64 k zmm +// VCVTUQQ2PD.BCST m64 zmm +// Construct and append a VCVTUQQ2PD.BCST instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PD_BCST(ops ...operand.Op) { ctx.VCVTUQQ2PD_BCST(ops...) } + +// VCVTUQQ2PD_BCST_Z: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PD.BCST.Z m64 k xmm +// VCVTUQQ2PD.BCST.Z m64 k ymm +// VCVTUQQ2PD.BCST.Z m64 k zmm +// Construct and append a VCVTUQQ2PD.BCST.Z instruction to the active function. +func (c *Context) VCVTUQQ2PD_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VCVTUQQ2PD_BCST_Z(m, k, xyz)) +} + +// VCVTUQQ2PD_BCST_Z: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PD.BCST.Z m64 k xmm +// VCVTUQQ2PD.BCST.Z m64 k ymm +// VCVTUQQ2PD.BCST.Z m64 k zmm +// Construct and append a VCVTUQQ2PD.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PD_BCST_Z(m, k, xyz operand.Op) { ctx.VCVTUQQ2PD_BCST_Z(m, k, xyz) } + +// VCVTUQQ2PD_RD_SAE: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTUQQ2PD.RD_SAE zmm k zmm +// VCVTUQQ2PD.RD_SAE zmm zmm +// Construct and append a VCVTUQQ2PD.RD_SAE instruction to the active function. +func (c *Context) VCVTUQQ2PD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTUQQ2PD_RD_SAE(ops...)) +} + +// VCVTUQQ2PD_RD_SAE: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTUQQ2PD.RD_SAE zmm k zmm +// VCVTUQQ2PD.RD_SAE zmm zmm +// Construct and append a VCVTUQQ2PD.RD_SAE instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PD_RD_SAE(ops ...operand.Op) { ctx.VCVTUQQ2PD_RD_SAE(ops...) } + +// VCVTUQQ2PD_RD_SAE_Z: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PD.RD_SAE.Z zmm k zmm +// Construct and append a VCVTUQQ2PD.RD_SAE.Z instruction to the active function. +func (c *Context) VCVTUQQ2PD_RD_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTUQQ2PD_RD_SAE_Z(z, k, z1)) +} + +// VCVTUQQ2PD_RD_SAE_Z: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PD.RD_SAE.Z zmm k zmm +// Construct and append a VCVTUQQ2PD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PD_RD_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTUQQ2PD_RD_SAE_Z(z, k, z1) } + +// VCVTUQQ2PD_RN_SAE: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VCVTUQQ2PD.RN_SAE zmm k zmm +// VCVTUQQ2PD.RN_SAE zmm zmm +// Construct and append a VCVTUQQ2PD.RN_SAE instruction to the active function. +func (c *Context) VCVTUQQ2PD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTUQQ2PD_RN_SAE(ops...)) +} + +// VCVTUQQ2PD_RN_SAE: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VCVTUQQ2PD.RN_SAE zmm k zmm +// VCVTUQQ2PD.RN_SAE zmm zmm +// Construct and append a VCVTUQQ2PD.RN_SAE instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PD_RN_SAE(ops ...operand.Op) { ctx.VCVTUQQ2PD_RN_SAE(ops...) } + +// VCVTUQQ2PD_RN_SAE_Z: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PD.RN_SAE.Z zmm k zmm +// Construct and append a VCVTUQQ2PD.RN_SAE.Z instruction to the active function. +func (c *Context) VCVTUQQ2PD_RN_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTUQQ2PD_RN_SAE_Z(z, k, z1)) +} + +// VCVTUQQ2PD_RN_SAE_Z: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PD.RN_SAE.Z zmm k zmm +// Construct and append a VCVTUQQ2PD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PD_RN_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTUQQ2PD_RN_SAE_Z(z, k, z1) } + +// VCVTUQQ2PD_RU_SAE: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTUQQ2PD.RU_SAE zmm k zmm +// VCVTUQQ2PD.RU_SAE zmm zmm +// Construct and append a VCVTUQQ2PD.RU_SAE instruction to the active function. +func (c *Context) VCVTUQQ2PD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTUQQ2PD_RU_SAE(ops...)) +} + +// VCVTUQQ2PD_RU_SAE: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTUQQ2PD.RU_SAE zmm k zmm +// VCVTUQQ2PD.RU_SAE zmm zmm +// Construct and append a VCVTUQQ2PD.RU_SAE instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PD_RU_SAE(ops ...operand.Op) { ctx.VCVTUQQ2PD_RU_SAE(ops...) } + +// VCVTUQQ2PD_RU_SAE_Z: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PD.RU_SAE.Z zmm k zmm +// Construct and append a VCVTUQQ2PD.RU_SAE.Z instruction to the active function. +func (c *Context) VCVTUQQ2PD_RU_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTUQQ2PD_RU_SAE_Z(z, k, z1)) +} + +// VCVTUQQ2PD_RU_SAE_Z: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PD.RU_SAE.Z zmm k zmm +// Construct and append a VCVTUQQ2PD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PD_RU_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTUQQ2PD_RU_SAE_Z(z, k, z1) } + +// VCVTUQQ2PD_RZ_SAE: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VCVTUQQ2PD.RZ_SAE zmm k zmm +// VCVTUQQ2PD.RZ_SAE zmm zmm +// Construct and append a VCVTUQQ2PD.RZ_SAE instruction to the active function. +func (c *Context) VCVTUQQ2PD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTUQQ2PD_RZ_SAE(ops...)) +} + +// VCVTUQQ2PD_RZ_SAE: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VCVTUQQ2PD.RZ_SAE zmm k zmm +// VCVTUQQ2PD.RZ_SAE zmm zmm +// Construct and append a VCVTUQQ2PD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PD_RZ_SAE(ops ...operand.Op) { ctx.VCVTUQQ2PD_RZ_SAE(ops...) } + +// VCVTUQQ2PD_RZ_SAE_Z: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PD.RZ_SAE.Z zmm k zmm +// Construct and append a VCVTUQQ2PD.RZ_SAE.Z instruction to the active function. +func (c *Context) VCVTUQQ2PD_RZ_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VCVTUQQ2PD_RZ_SAE_Z(z, k, z1)) +} + +// VCVTUQQ2PD_RZ_SAE_Z: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PD.RZ_SAE.Z zmm k zmm +// Construct and append a VCVTUQQ2PD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PD_RZ_SAE_Z(z, k, z1 operand.Op) { ctx.VCVTUQQ2PD_RZ_SAE_Z(z, k, z1) } + +// VCVTUQQ2PD_Z: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PD.Z m128 k xmm +// VCVTUQQ2PD.Z m256 k ymm +// VCVTUQQ2PD.Z xmm k xmm +// VCVTUQQ2PD.Z ymm k ymm +// VCVTUQQ2PD.Z m512 k zmm +// VCVTUQQ2PD.Z zmm k zmm +// Construct and append a VCVTUQQ2PD.Z instruction to the active function. +func (c *Context) VCVTUQQ2PD_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VCVTUQQ2PD_Z(mxyz, k, xyz)) +} + +// VCVTUQQ2PD_Z: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PD.Z m128 k xmm +// VCVTUQQ2PD.Z m256 k ymm +// VCVTUQQ2PD.Z xmm k xmm +// VCVTUQQ2PD.Z ymm k ymm +// VCVTUQQ2PD.Z m512 k zmm +// VCVTUQQ2PD.Z zmm k zmm +// Construct and append a VCVTUQQ2PD.Z instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PD_Z(mxyz, k, xyz operand.Op) { ctx.VCVTUQQ2PD_Z(mxyz, k, xyz) } + +// VCVTUQQ2PS: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VCVTUQQ2PS m512 k ymm +// VCVTUQQ2PS m512 ymm +// VCVTUQQ2PS zmm k ymm +// VCVTUQQ2PS zmm ymm +// Construct and append a VCVTUQQ2PS instruction to the active function. +func (c *Context) VCVTUQQ2PS(ops ...operand.Op) { + c.addinstruction(x86.VCVTUQQ2PS(ops...)) +} + +// VCVTUQQ2PS: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VCVTUQQ2PS m512 k ymm +// VCVTUQQ2PS m512 ymm +// VCVTUQQ2PS zmm k ymm +// VCVTUQQ2PS zmm ymm +// Construct and append a VCVTUQQ2PS instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PS(ops ...operand.Op) { ctx.VCVTUQQ2PS(ops...) } + +// VCVTUQQ2PSX: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VCVTUQQ2PSX m128 k xmm +// VCVTUQQ2PSX m128 xmm +// VCVTUQQ2PSX xmm k xmm +// VCVTUQQ2PSX xmm xmm +// Construct and append a VCVTUQQ2PSX instruction to the active function. +func (c *Context) VCVTUQQ2PSX(ops ...operand.Op) { + c.addinstruction(x86.VCVTUQQ2PSX(ops...)) +} + +// VCVTUQQ2PSX: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VCVTUQQ2PSX m128 k xmm +// VCVTUQQ2PSX m128 xmm +// VCVTUQQ2PSX xmm k xmm +// VCVTUQQ2PSX xmm xmm +// Construct and append a VCVTUQQ2PSX instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PSX(ops ...operand.Op) { ctx.VCVTUQQ2PSX(ops...) } + +// VCVTUQQ2PSX_BCST: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCVTUQQ2PSX.BCST m64 k xmm +// VCVTUQQ2PSX.BCST m64 xmm +// Construct and append a VCVTUQQ2PSX.BCST instruction to the active function. +func (c *Context) VCVTUQQ2PSX_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTUQQ2PSX_BCST(ops...)) +} + +// VCVTUQQ2PSX_BCST: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCVTUQQ2PSX.BCST m64 k xmm +// VCVTUQQ2PSX.BCST m64 xmm +// Construct and append a VCVTUQQ2PSX.BCST instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PSX_BCST(ops ...operand.Op) { ctx.VCVTUQQ2PSX_BCST(ops...) } + +// VCVTUQQ2PSX_BCST_Z: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PSX.BCST.Z m64 k xmm +// Construct and append a VCVTUQQ2PSX.BCST.Z instruction to the active function. +func (c *Context) VCVTUQQ2PSX_BCST_Z(m, k, x operand.Op) { + c.addinstruction(x86.VCVTUQQ2PSX_BCST_Z(m, k, x)) +} + +// VCVTUQQ2PSX_BCST_Z: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PSX.BCST.Z m64 k xmm +// Construct and append a VCVTUQQ2PSX.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PSX_BCST_Z(m, k, x operand.Op) { ctx.VCVTUQQ2PSX_BCST_Z(m, k, x) } + +// VCVTUQQ2PSX_Z: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PSX.Z m128 k xmm +// VCVTUQQ2PSX.Z xmm k xmm +// Construct and append a VCVTUQQ2PSX.Z instruction to the active function. +func (c *Context) VCVTUQQ2PSX_Z(mx, k, x operand.Op) { + c.addinstruction(x86.VCVTUQQ2PSX_Z(mx, k, x)) +} + +// VCVTUQQ2PSX_Z: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PSX.Z m128 k xmm +// VCVTUQQ2PSX.Z xmm k xmm +// Construct and append a VCVTUQQ2PSX.Z instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PSX_Z(mx, k, x operand.Op) { ctx.VCVTUQQ2PSX_Z(mx, k, x) } + +// VCVTUQQ2PSY: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VCVTUQQ2PSY m256 k xmm +// VCVTUQQ2PSY m256 xmm +// VCVTUQQ2PSY ymm k xmm +// VCVTUQQ2PSY ymm xmm +// Construct and append a VCVTUQQ2PSY instruction to the active function. +func (c *Context) VCVTUQQ2PSY(ops ...operand.Op) { + c.addinstruction(x86.VCVTUQQ2PSY(ops...)) +} + +// VCVTUQQ2PSY: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VCVTUQQ2PSY m256 k xmm +// VCVTUQQ2PSY m256 xmm +// VCVTUQQ2PSY ymm k xmm +// VCVTUQQ2PSY ymm xmm +// Construct and append a VCVTUQQ2PSY instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PSY(ops ...operand.Op) { ctx.VCVTUQQ2PSY(ops...) } + +// VCVTUQQ2PSY_BCST: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCVTUQQ2PSY.BCST m64 k xmm +// VCVTUQQ2PSY.BCST m64 xmm +// Construct and append a VCVTUQQ2PSY.BCST instruction to the active function. +func (c *Context) VCVTUQQ2PSY_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTUQQ2PSY_BCST(ops...)) +} + +// VCVTUQQ2PSY_BCST: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCVTUQQ2PSY.BCST m64 k xmm +// VCVTUQQ2PSY.BCST m64 xmm +// Construct and append a VCVTUQQ2PSY.BCST instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PSY_BCST(ops ...operand.Op) { ctx.VCVTUQQ2PSY_BCST(ops...) } + +// VCVTUQQ2PSY_BCST_Z: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PSY.BCST.Z m64 k xmm +// Construct and append a VCVTUQQ2PSY.BCST.Z instruction to the active function. +func (c *Context) VCVTUQQ2PSY_BCST_Z(m, k, x operand.Op) { + c.addinstruction(x86.VCVTUQQ2PSY_BCST_Z(m, k, x)) +} + +// VCVTUQQ2PSY_BCST_Z: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PSY.BCST.Z m64 k xmm +// Construct and append a VCVTUQQ2PSY.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PSY_BCST_Z(m, k, x operand.Op) { ctx.VCVTUQQ2PSY_BCST_Z(m, k, x) } + +// VCVTUQQ2PSY_Z: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PSY.Z m256 k xmm +// VCVTUQQ2PSY.Z ymm k xmm +// Construct and append a VCVTUQQ2PSY.Z instruction to the active function. +func (c *Context) VCVTUQQ2PSY_Z(my, k, x operand.Op) { + c.addinstruction(x86.VCVTUQQ2PSY_Z(my, k, x)) +} + +// VCVTUQQ2PSY_Z: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PSY.Z m256 k xmm +// VCVTUQQ2PSY.Z ymm k xmm +// Construct and append a VCVTUQQ2PSY.Z instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PSY_Z(my, k, x operand.Op) { ctx.VCVTUQQ2PSY_Z(my, k, x) } + +// VCVTUQQ2PS_BCST: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCVTUQQ2PS.BCST m64 k ymm +// VCVTUQQ2PS.BCST m64 ymm +// Construct and append a VCVTUQQ2PS.BCST instruction to the active function. +func (c *Context) VCVTUQQ2PS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VCVTUQQ2PS_BCST(ops...)) +} + +// VCVTUQQ2PS_BCST: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCVTUQQ2PS.BCST m64 k ymm +// VCVTUQQ2PS.BCST m64 ymm +// Construct and append a VCVTUQQ2PS.BCST instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PS_BCST(ops ...operand.Op) { ctx.VCVTUQQ2PS_BCST(ops...) } + +// VCVTUQQ2PS_BCST_Z: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PS.BCST.Z m64 k ymm +// Construct and append a VCVTUQQ2PS.BCST.Z instruction to the active function. +func (c *Context) VCVTUQQ2PS_BCST_Z(m, k, y operand.Op) { + c.addinstruction(x86.VCVTUQQ2PS_BCST_Z(m, k, y)) +} + +// VCVTUQQ2PS_BCST_Z: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PS.BCST.Z m64 k ymm +// Construct and append a VCVTUQQ2PS.BCST.Z instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PS_BCST_Z(m, k, y operand.Op) { ctx.VCVTUQQ2PS_BCST_Z(m, k, y) } + +// VCVTUQQ2PS_RD_SAE: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTUQQ2PS.RD_SAE zmm k ymm +// VCVTUQQ2PS.RD_SAE zmm ymm +// Construct and append a VCVTUQQ2PS.RD_SAE instruction to the active function. +func (c *Context) VCVTUQQ2PS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTUQQ2PS_RD_SAE(ops...)) +} + +// VCVTUQQ2PS_RD_SAE: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTUQQ2PS.RD_SAE zmm k ymm +// VCVTUQQ2PS.RD_SAE zmm ymm +// Construct and append a VCVTUQQ2PS.RD_SAE instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PS_RD_SAE(ops ...operand.Op) { ctx.VCVTUQQ2PS_RD_SAE(ops...) } + +// VCVTUQQ2PS_RD_SAE_Z: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PS.RD_SAE.Z zmm k ymm +// Construct and append a VCVTUQQ2PS.RD_SAE.Z instruction to the active function. +func (c *Context) VCVTUQQ2PS_RD_SAE_Z(z, k, y operand.Op) { + c.addinstruction(x86.VCVTUQQ2PS_RD_SAE_Z(z, k, y)) +} + +// VCVTUQQ2PS_RD_SAE_Z: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PS.RD_SAE.Z zmm k ymm +// Construct and append a VCVTUQQ2PS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PS_RD_SAE_Z(z, k, y operand.Op) { ctx.VCVTUQQ2PS_RD_SAE_Z(z, k, y) } + +// VCVTUQQ2PS_RN_SAE: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VCVTUQQ2PS.RN_SAE zmm k ymm +// VCVTUQQ2PS.RN_SAE zmm ymm +// Construct and append a VCVTUQQ2PS.RN_SAE instruction to the active function. +func (c *Context) VCVTUQQ2PS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTUQQ2PS_RN_SAE(ops...)) +} + +// VCVTUQQ2PS_RN_SAE: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VCVTUQQ2PS.RN_SAE zmm k ymm +// VCVTUQQ2PS.RN_SAE zmm ymm +// Construct and append a VCVTUQQ2PS.RN_SAE instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PS_RN_SAE(ops ...operand.Op) { ctx.VCVTUQQ2PS_RN_SAE(ops...) } + +// VCVTUQQ2PS_RN_SAE_Z: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PS.RN_SAE.Z zmm k ymm +// Construct and append a VCVTUQQ2PS.RN_SAE.Z instruction to the active function. +func (c *Context) VCVTUQQ2PS_RN_SAE_Z(z, k, y operand.Op) { + c.addinstruction(x86.VCVTUQQ2PS_RN_SAE_Z(z, k, y)) +} + +// VCVTUQQ2PS_RN_SAE_Z: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PS.RN_SAE.Z zmm k ymm +// Construct and append a VCVTUQQ2PS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PS_RN_SAE_Z(z, k, y operand.Op) { ctx.VCVTUQQ2PS_RN_SAE_Z(z, k, y) } + +// VCVTUQQ2PS_RU_SAE: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTUQQ2PS.RU_SAE zmm k ymm +// VCVTUQQ2PS.RU_SAE zmm ymm +// Construct and append a VCVTUQQ2PS.RU_SAE instruction to the active function. +func (c *Context) VCVTUQQ2PS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTUQQ2PS_RU_SAE(ops...)) +} + +// VCVTUQQ2PS_RU_SAE: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTUQQ2PS.RU_SAE zmm k ymm +// VCVTUQQ2PS.RU_SAE zmm ymm +// Construct and append a VCVTUQQ2PS.RU_SAE instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PS_RU_SAE(ops ...operand.Op) { ctx.VCVTUQQ2PS_RU_SAE(ops...) } + +// VCVTUQQ2PS_RU_SAE_Z: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PS.RU_SAE.Z zmm k ymm +// Construct and append a VCVTUQQ2PS.RU_SAE.Z instruction to the active function. +func (c *Context) VCVTUQQ2PS_RU_SAE_Z(z, k, y operand.Op) { + c.addinstruction(x86.VCVTUQQ2PS_RU_SAE_Z(z, k, y)) +} + +// VCVTUQQ2PS_RU_SAE_Z: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PS.RU_SAE.Z zmm k ymm +// Construct and append a VCVTUQQ2PS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PS_RU_SAE_Z(z, k, y operand.Op) { ctx.VCVTUQQ2PS_RU_SAE_Z(z, k, y) } + +// VCVTUQQ2PS_RZ_SAE: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VCVTUQQ2PS.RZ_SAE zmm k ymm +// VCVTUQQ2PS.RZ_SAE zmm ymm +// Construct and append a VCVTUQQ2PS.RZ_SAE instruction to the active function. +func (c *Context) VCVTUQQ2PS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VCVTUQQ2PS_RZ_SAE(ops...)) +} + +// VCVTUQQ2PS_RZ_SAE: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VCVTUQQ2PS.RZ_SAE zmm k ymm +// VCVTUQQ2PS.RZ_SAE zmm ymm +// Construct and append a VCVTUQQ2PS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PS_RZ_SAE(ops ...operand.Op) { ctx.VCVTUQQ2PS_RZ_SAE(ops...) } + +// VCVTUQQ2PS_RZ_SAE_Z: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PS.RZ_SAE.Z zmm k ymm +// Construct and append a VCVTUQQ2PS.RZ_SAE.Z instruction to the active function. +func (c *Context) VCVTUQQ2PS_RZ_SAE_Z(z, k, y operand.Op) { + c.addinstruction(x86.VCVTUQQ2PS_RZ_SAE_Z(z, k, y)) +} + +// VCVTUQQ2PS_RZ_SAE_Z: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PS.RZ_SAE.Z zmm k ymm +// Construct and append a VCVTUQQ2PS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PS_RZ_SAE_Z(z, k, y operand.Op) { ctx.VCVTUQQ2PS_RZ_SAE_Z(z, k, y) } + +// VCVTUQQ2PS_Z: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PS.Z m512 k ymm +// VCVTUQQ2PS.Z zmm k ymm +// Construct and append a VCVTUQQ2PS.Z instruction to the active function. +func (c *Context) VCVTUQQ2PS_Z(mz, k, y operand.Op) { + c.addinstruction(x86.VCVTUQQ2PS_Z(mz, k, y)) +} + +// VCVTUQQ2PS_Z: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PS.Z m512 k ymm +// VCVTUQQ2PS.Z zmm k ymm +// Construct and append a VCVTUQQ2PS.Z instruction to the active function. +// Operates on the global context. +func VCVTUQQ2PS_Z(mz, k, y operand.Op) { ctx.VCVTUQQ2PS_Z(mz, k, y) } + +// VCVTUSI2SDL: Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// VCVTUSI2SDL m32 xmm xmm +// VCVTUSI2SDL r32 xmm xmm +// Construct and append a VCVTUSI2SDL instruction to the active function. +func (c *Context) VCVTUSI2SDL(mr, x, x1 operand.Op) { + c.addinstruction(x86.VCVTUSI2SDL(mr, x, x1)) +} + +// VCVTUSI2SDL: Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// VCVTUSI2SDL m32 xmm xmm +// VCVTUSI2SDL r32 xmm xmm +// Construct and append a VCVTUSI2SDL instruction to the active function. +// Operates on the global context. +func VCVTUSI2SDL(mr, x, x1 operand.Op) { ctx.VCVTUSI2SDL(mr, x, x1) } + +// VCVTUSI2SDQ: Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// VCVTUSI2SDQ m64 xmm xmm +// VCVTUSI2SDQ r64 xmm xmm +// Construct and append a VCVTUSI2SDQ instruction to the active function. +func (c *Context) VCVTUSI2SDQ(mr, x, x1 operand.Op) { + c.addinstruction(x86.VCVTUSI2SDQ(mr, x, x1)) +} + +// VCVTUSI2SDQ: Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// VCVTUSI2SDQ m64 xmm xmm +// VCVTUSI2SDQ r64 xmm xmm +// Construct and append a VCVTUSI2SDQ instruction to the active function. +// Operates on the global context. +func VCVTUSI2SDQ(mr, x, x1 operand.Op) { ctx.VCVTUSI2SDQ(mr, x, x1) } + +// VCVTUSI2SDQ_RD_SAE: Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTUSI2SDQ.RD_SAE r64 xmm xmm +// Construct and append a VCVTUSI2SDQ.RD_SAE instruction to the active function. +func (c *Context) VCVTUSI2SDQ_RD_SAE(r, x, x1 operand.Op) { + c.addinstruction(x86.VCVTUSI2SDQ_RD_SAE(r, x, x1)) +} + +// VCVTUSI2SDQ_RD_SAE: Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTUSI2SDQ.RD_SAE r64 xmm xmm +// Construct and append a VCVTUSI2SDQ.RD_SAE instruction to the active function. +// Operates on the global context. +func VCVTUSI2SDQ_RD_SAE(r, x, x1 operand.Op) { ctx.VCVTUSI2SDQ_RD_SAE(r, x, x1) } + +// VCVTUSI2SDQ_RN_SAE: Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value (Round Towards Nearest). +// +// Forms: +// +// VCVTUSI2SDQ.RN_SAE r64 xmm xmm +// Construct and append a VCVTUSI2SDQ.RN_SAE instruction to the active function. +func (c *Context) VCVTUSI2SDQ_RN_SAE(r, x, x1 operand.Op) { + c.addinstruction(x86.VCVTUSI2SDQ_RN_SAE(r, x, x1)) +} + +// VCVTUSI2SDQ_RN_SAE: Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value (Round Towards Nearest). +// +// Forms: +// +// VCVTUSI2SDQ.RN_SAE r64 xmm xmm +// Construct and append a VCVTUSI2SDQ.RN_SAE instruction to the active function. +// Operates on the global context. +func VCVTUSI2SDQ_RN_SAE(r, x, x1 operand.Op) { ctx.VCVTUSI2SDQ_RN_SAE(r, x, x1) } + +// VCVTUSI2SDQ_RU_SAE: Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTUSI2SDQ.RU_SAE r64 xmm xmm +// Construct and append a VCVTUSI2SDQ.RU_SAE instruction to the active function. +func (c *Context) VCVTUSI2SDQ_RU_SAE(r, x, x1 operand.Op) { + c.addinstruction(x86.VCVTUSI2SDQ_RU_SAE(r, x, x1)) +} + +// VCVTUSI2SDQ_RU_SAE: Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTUSI2SDQ.RU_SAE r64 xmm xmm +// Construct and append a VCVTUSI2SDQ.RU_SAE instruction to the active function. +// Operates on the global context. +func VCVTUSI2SDQ_RU_SAE(r, x, x1 operand.Op) { ctx.VCVTUSI2SDQ_RU_SAE(r, x, x1) } + +// VCVTUSI2SDQ_RZ_SAE: Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value (Round Towards Zero). +// +// Forms: +// +// VCVTUSI2SDQ.RZ_SAE r64 xmm xmm +// Construct and append a VCVTUSI2SDQ.RZ_SAE instruction to the active function. +func (c *Context) VCVTUSI2SDQ_RZ_SAE(r, x, x1 operand.Op) { + c.addinstruction(x86.VCVTUSI2SDQ_RZ_SAE(r, x, x1)) +} + +// VCVTUSI2SDQ_RZ_SAE: Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value (Round Towards Zero). +// +// Forms: +// +// VCVTUSI2SDQ.RZ_SAE r64 xmm xmm +// Construct and append a VCVTUSI2SDQ.RZ_SAE instruction to the active function. +// Operates on the global context. +func VCVTUSI2SDQ_RZ_SAE(r, x, x1 operand.Op) { ctx.VCVTUSI2SDQ_RZ_SAE(r, x, x1) } + +// VCVTUSI2SSL: Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value. +// +// Forms: +// +// VCVTUSI2SSL m32 xmm xmm +// VCVTUSI2SSL r32 xmm xmm +// Construct and append a VCVTUSI2SSL instruction to the active function. +func (c *Context) VCVTUSI2SSL(mr, x, x1 operand.Op) { + c.addinstruction(x86.VCVTUSI2SSL(mr, x, x1)) +} + +// VCVTUSI2SSL: Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value. +// +// Forms: +// +// VCVTUSI2SSL m32 xmm xmm +// VCVTUSI2SSL r32 xmm xmm +// Construct and append a VCVTUSI2SSL instruction to the active function. +// Operates on the global context. +func VCVTUSI2SSL(mr, x, x1 operand.Op) { ctx.VCVTUSI2SSL(mr, x, x1) } + +// VCVTUSI2SSL_RD_SAE: Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTUSI2SSL.RD_SAE r32 xmm xmm +// Construct and append a VCVTUSI2SSL.RD_SAE instruction to the active function. +func (c *Context) VCVTUSI2SSL_RD_SAE(r, x, x1 operand.Op) { + c.addinstruction(x86.VCVTUSI2SSL_RD_SAE(r, x, x1)) +} + +// VCVTUSI2SSL_RD_SAE: Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTUSI2SSL.RD_SAE r32 xmm xmm +// Construct and append a VCVTUSI2SSL.RD_SAE instruction to the active function. +// Operates on the global context. +func VCVTUSI2SSL_RD_SAE(r, x, x1 operand.Op) { ctx.VCVTUSI2SSL_RD_SAE(r, x, x1) } + +// VCVTUSI2SSL_RN_SAE: Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value (Round Towards Nearest). +// +// Forms: +// +// VCVTUSI2SSL.RN_SAE r32 xmm xmm +// Construct and append a VCVTUSI2SSL.RN_SAE instruction to the active function. +func (c *Context) VCVTUSI2SSL_RN_SAE(r, x, x1 operand.Op) { + c.addinstruction(x86.VCVTUSI2SSL_RN_SAE(r, x, x1)) +} + +// VCVTUSI2SSL_RN_SAE: Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value (Round Towards Nearest). +// +// Forms: +// +// VCVTUSI2SSL.RN_SAE r32 xmm xmm +// Construct and append a VCVTUSI2SSL.RN_SAE instruction to the active function. +// Operates on the global context. +func VCVTUSI2SSL_RN_SAE(r, x, x1 operand.Op) { ctx.VCVTUSI2SSL_RN_SAE(r, x, x1) } + +// VCVTUSI2SSL_RU_SAE: Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTUSI2SSL.RU_SAE r32 xmm xmm +// Construct and append a VCVTUSI2SSL.RU_SAE instruction to the active function. +func (c *Context) VCVTUSI2SSL_RU_SAE(r, x, x1 operand.Op) { + c.addinstruction(x86.VCVTUSI2SSL_RU_SAE(r, x, x1)) +} + +// VCVTUSI2SSL_RU_SAE: Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTUSI2SSL.RU_SAE r32 xmm xmm +// Construct and append a VCVTUSI2SSL.RU_SAE instruction to the active function. +// Operates on the global context. +func VCVTUSI2SSL_RU_SAE(r, x, x1 operand.Op) { ctx.VCVTUSI2SSL_RU_SAE(r, x, x1) } + +// VCVTUSI2SSL_RZ_SAE: Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value (Round Towards Zero). +// +// Forms: +// +// VCVTUSI2SSL.RZ_SAE r32 xmm xmm +// Construct and append a VCVTUSI2SSL.RZ_SAE instruction to the active function. +func (c *Context) VCVTUSI2SSL_RZ_SAE(r, x, x1 operand.Op) { + c.addinstruction(x86.VCVTUSI2SSL_RZ_SAE(r, x, x1)) +} + +// VCVTUSI2SSL_RZ_SAE: Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value (Round Towards Zero). +// +// Forms: +// +// VCVTUSI2SSL.RZ_SAE r32 xmm xmm +// Construct and append a VCVTUSI2SSL.RZ_SAE instruction to the active function. +// Operates on the global context. +func VCVTUSI2SSL_RZ_SAE(r, x, x1 operand.Op) { ctx.VCVTUSI2SSL_RZ_SAE(r, x, x1) } + +// VCVTUSI2SSQ: Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value. +// +// Forms: +// +// VCVTUSI2SSQ m64 xmm xmm +// VCVTUSI2SSQ r64 xmm xmm +// Construct and append a VCVTUSI2SSQ instruction to the active function. +func (c *Context) VCVTUSI2SSQ(mr, x, x1 operand.Op) { + c.addinstruction(x86.VCVTUSI2SSQ(mr, x, x1)) +} + +// VCVTUSI2SSQ: Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value. +// +// Forms: +// +// VCVTUSI2SSQ m64 xmm xmm +// VCVTUSI2SSQ r64 xmm xmm +// Construct and append a VCVTUSI2SSQ instruction to the active function. +// Operates on the global context. +func VCVTUSI2SSQ(mr, x, x1 operand.Op) { ctx.VCVTUSI2SSQ(mr, x, x1) } + +// VCVTUSI2SSQ_RD_SAE: Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTUSI2SSQ.RD_SAE r64 xmm xmm +// Construct and append a VCVTUSI2SSQ.RD_SAE instruction to the active function. +func (c *Context) VCVTUSI2SSQ_RD_SAE(r, x, x1 operand.Op) { + c.addinstruction(x86.VCVTUSI2SSQ_RD_SAE(r, x, x1)) +} + +// VCVTUSI2SSQ_RD_SAE: Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTUSI2SSQ.RD_SAE r64 xmm xmm +// Construct and append a VCVTUSI2SSQ.RD_SAE instruction to the active function. +// Operates on the global context. +func VCVTUSI2SSQ_RD_SAE(r, x, x1 operand.Op) { ctx.VCVTUSI2SSQ_RD_SAE(r, x, x1) } + +// VCVTUSI2SSQ_RN_SAE: Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value (Round Towards Nearest). +// +// Forms: +// +// VCVTUSI2SSQ.RN_SAE r64 xmm xmm +// Construct and append a VCVTUSI2SSQ.RN_SAE instruction to the active function. +func (c *Context) VCVTUSI2SSQ_RN_SAE(r, x, x1 operand.Op) { + c.addinstruction(x86.VCVTUSI2SSQ_RN_SAE(r, x, x1)) +} + +// VCVTUSI2SSQ_RN_SAE: Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value (Round Towards Nearest). +// +// Forms: +// +// VCVTUSI2SSQ.RN_SAE r64 xmm xmm +// Construct and append a VCVTUSI2SSQ.RN_SAE instruction to the active function. +// Operates on the global context. +func VCVTUSI2SSQ_RN_SAE(r, x, x1 operand.Op) { ctx.VCVTUSI2SSQ_RN_SAE(r, x, x1) } + +// VCVTUSI2SSQ_RU_SAE: Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTUSI2SSQ.RU_SAE r64 xmm xmm +// Construct and append a VCVTUSI2SSQ.RU_SAE instruction to the active function. +func (c *Context) VCVTUSI2SSQ_RU_SAE(r, x, x1 operand.Op) { + c.addinstruction(x86.VCVTUSI2SSQ_RU_SAE(r, x, x1)) +} + +// VCVTUSI2SSQ_RU_SAE: Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTUSI2SSQ.RU_SAE r64 xmm xmm +// Construct and append a VCVTUSI2SSQ.RU_SAE instruction to the active function. +// Operates on the global context. +func VCVTUSI2SSQ_RU_SAE(r, x, x1 operand.Op) { ctx.VCVTUSI2SSQ_RU_SAE(r, x, x1) } + +// VCVTUSI2SSQ_RZ_SAE: Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value (Round Towards Zero). +// +// Forms: +// +// VCVTUSI2SSQ.RZ_SAE r64 xmm xmm +// Construct and append a VCVTUSI2SSQ.RZ_SAE instruction to the active function. +func (c *Context) VCVTUSI2SSQ_RZ_SAE(r, x, x1 operand.Op) { + c.addinstruction(x86.VCVTUSI2SSQ_RZ_SAE(r, x, x1)) +} + +// VCVTUSI2SSQ_RZ_SAE: Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value (Round Towards Zero). +// +// Forms: +// +// VCVTUSI2SSQ.RZ_SAE r64 xmm xmm +// Construct and append a VCVTUSI2SSQ.RZ_SAE instruction to the active function. +// Operates on the global context. +func VCVTUSI2SSQ_RZ_SAE(r, x, x1 operand.Op) { ctx.VCVTUSI2SSQ_RZ_SAE(r, x, x1) } + +// VDBPSADBW: Double Block Packed Sum-Absolute-Differences on Unsigned Bytes. +// +// Forms: +// +// VDBPSADBW imm8 m128 xmm k xmm +// VDBPSADBW imm8 m128 xmm xmm +// VDBPSADBW imm8 m256 ymm k ymm +// VDBPSADBW imm8 m256 ymm ymm +// VDBPSADBW imm8 xmm xmm k xmm +// VDBPSADBW imm8 xmm xmm xmm +// VDBPSADBW imm8 ymm ymm k ymm +// VDBPSADBW imm8 ymm ymm ymm +// VDBPSADBW imm8 m512 zmm k zmm +// VDBPSADBW imm8 m512 zmm zmm +// VDBPSADBW imm8 zmm zmm k zmm +// VDBPSADBW imm8 zmm zmm zmm +// Construct and append a VDBPSADBW instruction to the active function. +func (c *Context) VDBPSADBW(ops ...operand.Op) { + c.addinstruction(x86.VDBPSADBW(ops...)) +} + +// VDBPSADBW: Double Block Packed Sum-Absolute-Differences on Unsigned Bytes. +// +// Forms: +// +// VDBPSADBW imm8 m128 xmm k xmm +// VDBPSADBW imm8 m128 xmm xmm +// VDBPSADBW imm8 m256 ymm k ymm +// VDBPSADBW imm8 m256 ymm ymm +// VDBPSADBW imm8 xmm xmm k xmm +// VDBPSADBW imm8 xmm xmm xmm +// VDBPSADBW imm8 ymm ymm k ymm +// VDBPSADBW imm8 ymm ymm ymm +// VDBPSADBW imm8 m512 zmm k zmm +// VDBPSADBW imm8 m512 zmm zmm +// VDBPSADBW imm8 zmm zmm k zmm +// VDBPSADBW imm8 zmm zmm zmm +// Construct and append a VDBPSADBW instruction to the active function. +// Operates on the global context. +func VDBPSADBW(ops ...operand.Op) { ctx.VDBPSADBW(ops...) } + +// VDBPSADBW_Z: Double Block Packed Sum-Absolute-Differences on Unsigned Bytes (Zeroing Masking). +// +// Forms: +// +// VDBPSADBW.Z imm8 m128 xmm k xmm +// VDBPSADBW.Z imm8 m256 ymm k ymm +// VDBPSADBW.Z imm8 xmm xmm k xmm +// VDBPSADBW.Z imm8 ymm ymm k ymm +// VDBPSADBW.Z imm8 m512 zmm k zmm +// VDBPSADBW.Z imm8 zmm zmm k zmm +// Construct and append a VDBPSADBW.Z instruction to the active function. +func (c *Context) VDBPSADBW_Z(i, mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VDBPSADBW_Z(i, mxyz, xyz, k, xyz1)) +} + +// VDBPSADBW_Z: Double Block Packed Sum-Absolute-Differences on Unsigned Bytes (Zeroing Masking). +// +// Forms: +// +// VDBPSADBW.Z imm8 m128 xmm k xmm +// VDBPSADBW.Z imm8 m256 ymm k ymm +// VDBPSADBW.Z imm8 xmm xmm k xmm +// VDBPSADBW.Z imm8 ymm ymm k ymm +// VDBPSADBW.Z imm8 m512 zmm k zmm +// VDBPSADBW.Z imm8 zmm zmm k zmm +// Construct and append a VDBPSADBW.Z instruction to the active function. +// Operates on the global context. +func VDBPSADBW_Z(i, mxyz, xyz, k, xyz1 operand.Op) { ctx.VDBPSADBW_Z(i, mxyz, xyz, k, xyz1) } + +// VDIVPD: Divide Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VDIVPD m128 xmm xmm +// VDIVPD m256 ymm ymm +// VDIVPD xmm xmm xmm +// VDIVPD ymm ymm ymm +// VDIVPD m128 xmm k xmm +// VDIVPD m256 ymm k ymm +// VDIVPD xmm xmm k xmm +// VDIVPD ymm ymm k ymm +// VDIVPD m512 zmm k zmm +// VDIVPD m512 zmm zmm +// VDIVPD zmm zmm k zmm +// VDIVPD zmm zmm zmm +// Construct and append a VDIVPD instruction to the active function. +func (c *Context) VDIVPD(ops ...operand.Op) { + c.addinstruction(x86.VDIVPD(ops...)) +} + +// VDIVPD: Divide Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VDIVPD m128 xmm xmm +// VDIVPD m256 ymm ymm +// VDIVPD xmm xmm xmm +// VDIVPD ymm ymm ymm +// VDIVPD m128 xmm k xmm +// VDIVPD m256 ymm k ymm +// VDIVPD xmm xmm k xmm +// VDIVPD ymm ymm k ymm +// VDIVPD m512 zmm k zmm +// VDIVPD m512 zmm zmm +// VDIVPD zmm zmm k zmm +// VDIVPD zmm zmm zmm +// Construct and append a VDIVPD instruction to the active function. +// Operates on the global context. +func VDIVPD(ops ...operand.Op) { ctx.VDIVPD(ops...) } + +// VDIVPD_BCST: Divide Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VDIVPD.BCST m64 xmm k xmm +// VDIVPD.BCST m64 xmm xmm +// VDIVPD.BCST m64 ymm k ymm +// VDIVPD.BCST m64 ymm ymm +// VDIVPD.BCST m64 zmm k zmm +// VDIVPD.BCST m64 zmm zmm +// Construct and append a VDIVPD.BCST instruction to the active function. +func (c *Context) VDIVPD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VDIVPD_BCST(ops...)) +} + +// VDIVPD_BCST: Divide Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VDIVPD.BCST m64 xmm k xmm +// VDIVPD.BCST m64 xmm xmm +// VDIVPD.BCST m64 ymm k ymm +// VDIVPD.BCST m64 ymm ymm +// VDIVPD.BCST m64 zmm k zmm +// VDIVPD.BCST m64 zmm zmm +// Construct and append a VDIVPD.BCST instruction to the active function. +// Operates on the global context. +func VDIVPD_BCST(ops ...operand.Op) { ctx.VDIVPD_BCST(ops...) } + +// VDIVPD_BCST_Z: Divide Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VDIVPD.BCST.Z m64 xmm k xmm +// VDIVPD.BCST.Z m64 ymm k ymm +// VDIVPD.BCST.Z m64 zmm k zmm +// Construct and append a VDIVPD.BCST.Z instruction to the active function. +func (c *Context) VDIVPD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VDIVPD_BCST_Z(m, xyz, k, xyz1)) +} + +// VDIVPD_BCST_Z: Divide Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VDIVPD.BCST.Z m64 xmm k xmm +// VDIVPD.BCST.Z m64 ymm k ymm +// VDIVPD.BCST.Z m64 zmm k zmm +// Construct and append a VDIVPD.BCST.Z instruction to the active function. +// Operates on the global context. +func VDIVPD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VDIVPD_BCST_Z(m, xyz, k, xyz1) } + +// VDIVPD_RD_SAE: Divide Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VDIVPD.RD_SAE zmm zmm k zmm +// VDIVPD.RD_SAE zmm zmm zmm +// Construct and append a VDIVPD.RD_SAE instruction to the active function. +func (c *Context) VDIVPD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VDIVPD_RD_SAE(ops...)) +} + +// VDIVPD_RD_SAE: Divide Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VDIVPD.RD_SAE zmm zmm k zmm +// VDIVPD.RD_SAE zmm zmm zmm +// Construct and append a VDIVPD.RD_SAE instruction to the active function. +// Operates on the global context. +func VDIVPD_RD_SAE(ops ...operand.Op) { ctx.VDIVPD_RD_SAE(ops...) } + +// VDIVPD_RD_SAE_Z: Divide Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VDIVPD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VDIVPD.RD_SAE.Z instruction to the active function. +func (c *Context) VDIVPD_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VDIVPD_RD_SAE_Z(z, z1, k, z2)) +} + +// VDIVPD_RD_SAE_Z: Divide Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VDIVPD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VDIVPD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VDIVPD_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VDIVPD_RD_SAE_Z(z, z1, k, z2) } + +// VDIVPD_RN_SAE: Divide Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VDIVPD.RN_SAE zmm zmm k zmm +// VDIVPD.RN_SAE zmm zmm zmm +// Construct and append a VDIVPD.RN_SAE instruction to the active function. +func (c *Context) VDIVPD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VDIVPD_RN_SAE(ops...)) +} + +// VDIVPD_RN_SAE: Divide Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VDIVPD.RN_SAE zmm zmm k zmm +// VDIVPD.RN_SAE zmm zmm zmm +// Construct and append a VDIVPD.RN_SAE instruction to the active function. +// Operates on the global context. +func VDIVPD_RN_SAE(ops ...operand.Op) { ctx.VDIVPD_RN_SAE(ops...) } + +// VDIVPD_RN_SAE_Z: Divide Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VDIVPD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VDIVPD.RN_SAE.Z instruction to the active function. +func (c *Context) VDIVPD_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VDIVPD_RN_SAE_Z(z, z1, k, z2)) +} + +// VDIVPD_RN_SAE_Z: Divide Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VDIVPD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VDIVPD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VDIVPD_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VDIVPD_RN_SAE_Z(z, z1, k, z2) } + +// VDIVPD_RU_SAE: Divide Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VDIVPD.RU_SAE zmm zmm k zmm +// VDIVPD.RU_SAE zmm zmm zmm +// Construct and append a VDIVPD.RU_SAE instruction to the active function. +func (c *Context) VDIVPD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VDIVPD_RU_SAE(ops...)) +} + +// VDIVPD_RU_SAE: Divide Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VDIVPD.RU_SAE zmm zmm k zmm +// VDIVPD.RU_SAE zmm zmm zmm +// Construct and append a VDIVPD.RU_SAE instruction to the active function. +// Operates on the global context. +func VDIVPD_RU_SAE(ops ...operand.Op) { ctx.VDIVPD_RU_SAE(ops...) } + +// VDIVPD_RU_SAE_Z: Divide Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VDIVPD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VDIVPD.RU_SAE.Z instruction to the active function. +func (c *Context) VDIVPD_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VDIVPD_RU_SAE_Z(z, z1, k, z2)) +} + +// VDIVPD_RU_SAE_Z: Divide Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VDIVPD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VDIVPD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VDIVPD_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VDIVPD_RU_SAE_Z(z, z1, k, z2) } + +// VDIVPD_RZ_SAE: Divide Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VDIVPD.RZ_SAE zmm zmm k zmm +// VDIVPD.RZ_SAE zmm zmm zmm +// Construct and append a VDIVPD.RZ_SAE instruction to the active function. +func (c *Context) VDIVPD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VDIVPD_RZ_SAE(ops...)) +} + +// VDIVPD_RZ_SAE: Divide Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VDIVPD.RZ_SAE zmm zmm k zmm +// VDIVPD.RZ_SAE zmm zmm zmm +// Construct and append a VDIVPD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VDIVPD_RZ_SAE(ops ...operand.Op) { ctx.VDIVPD_RZ_SAE(ops...) } + +// VDIVPD_RZ_SAE_Z: Divide Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VDIVPD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VDIVPD.RZ_SAE.Z instruction to the active function. +func (c *Context) VDIVPD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VDIVPD_RZ_SAE_Z(z, z1, k, z2)) +} + +// VDIVPD_RZ_SAE_Z: Divide Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VDIVPD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VDIVPD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VDIVPD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VDIVPD_RZ_SAE_Z(z, z1, k, z2) } + +// VDIVPD_Z: Divide Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VDIVPD.Z m128 xmm k xmm +// VDIVPD.Z m256 ymm k ymm +// VDIVPD.Z xmm xmm k xmm +// VDIVPD.Z ymm ymm k ymm +// VDIVPD.Z m512 zmm k zmm +// VDIVPD.Z zmm zmm k zmm +// Construct and append a VDIVPD.Z instruction to the active function. +func (c *Context) VDIVPD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VDIVPD_Z(mxyz, xyz, k, xyz1)) +} + +// VDIVPD_Z: Divide Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VDIVPD.Z m128 xmm k xmm +// VDIVPD.Z m256 ymm k ymm +// VDIVPD.Z xmm xmm k xmm +// VDIVPD.Z ymm ymm k ymm +// VDIVPD.Z m512 zmm k zmm +// VDIVPD.Z zmm zmm k zmm +// Construct and append a VDIVPD.Z instruction to the active function. +// Operates on the global context. +func VDIVPD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VDIVPD_Z(mxyz, xyz, k, xyz1) } + +// VDIVPS: Divide Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VDIVPS m128 xmm xmm +// VDIVPS m256 ymm ymm +// VDIVPS xmm xmm xmm +// VDIVPS ymm ymm ymm +// VDIVPS m128 xmm k xmm +// VDIVPS m256 ymm k ymm +// VDIVPS xmm xmm k xmm +// VDIVPS ymm ymm k ymm +// VDIVPS m512 zmm k zmm +// VDIVPS m512 zmm zmm +// VDIVPS zmm zmm k zmm +// VDIVPS zmm zmm zmm +// Construct and append a VDIVPS instruction to the active function. +func (c *Context) VDIVPS(ops ...operand.Op) { + c.addinstruction(x86.VDIVPS(ops...)) +} + +// VDIVPS: Divide Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VDIVPS m128 xmm xmm +// VDIVPS m256 ymm ymm +// VDIVPS xmm xmm xmm +// VDIVPS ymm ymm ymm +// VDIVPS m128 xmm k xmm +// VDIVPS m256 ymm k ymm +// VDIVPS xmm xmm k xmm +// VDIVPS ymm ymm k ymm +// VDIVPS m512 zmm k zmm +// VDIVPS m512 zmm zmm +// VDIVPS zmm zmm k zmm +// VDIVPS zmm zmm zmm +// Construct and append a VDIVPS instruction to the active function. +// Operates on the global context. +func VDIVPS(ops ...operand.Op) { ctx.VDIVPS(ops...) } + +// VDIVPS_BCST: Divide Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VDIVPS.BCST m32 xmm k xmm +// VDIVPS.BCST m32 xmm xmm +// VDIVPS.BCST m32 ymm k ymm +// VDIVPS.BCST m32 ymm ymm +// VDIVPS.BCST m32 zmm k zmm +// VDIVPS.BCST m32 zmm zmm +// Construct and append a VDIVPS.BCST instruction to the active function. +func (c *Context) VDIVPS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VDIVPS_BCST(ops...)) +} + +// VDIVPS_BCST: Divide Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VDIVPS.BCST m32 xmm k xmm +// VDIVPS.BCST m32 xmm xmm +// VDIVPS.BCST m32 ymm k ymm +// VDIVPS.BCST m32 ymm ymm +// VDIVPS.BCST m32 zmm k zmm +// VDIVPS.BCST m32 zmm zmm +// Construct and append a VDIVPS.BCST instruction to the active function. +// Operates on the global context. +func VDIVPS_BCST(ops ...operand.Op) { ctx.VDIVPS_BCST(ops...) } + +// VDIVPS_BCST_Z: Divide Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VDIVPS.BCST.Z m32 xmm k xmm +// VDIVPS.BCST.Z m32 ymm k ymm +// VDIVPS.BCST.Z m32 zmm k zmm +// Construct and append a VDIVPS.BCST.Z instruction to the active function. +func (c *Context) VDIVPS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VDIVPS_BCST_Z(m, xyz, k, xyz1)) +} + +// VDIVPS_BCST_Z: Divide Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VDIVPS.BCST.Z m32 xmm k xmm +// VDIVPS.BCST.Z m32 ymm k ymm +// VDIVPS.BCST.Z m32 zmm k zmm +// Construct and append a VDIVPS.BCST.Z instruction to the active function. +// Operates on the global context. +func VDIVPS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VDIVPS_BCST_Z(m, xyz, k, xyz1) } + +// VDIVPS_RD_SAE: Divide Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VDIVPS.RD_SAE zmm zmm k zmm +// VDIVPS.RD_SAE zmm zmm zmm +// Construct and append a VDIVPS.RD_SAE instruction to the active function. +func (c *Context) VDIVPS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VDIVPS_RD_SAE(ops...)) +} + +// VDIVPS_RD_SAE: Divide Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VDIVPS.RD_SAE zmm zmm k zmm +// VDIVPS.RD_SAE zmm zmm zmm +// Construct and append a VDIVPS.RD_SAE instruction to the active function. +// Operates on the global context. +func VDIVPS_RD_SAE(ops ...operand.Op) { ctx.VDIVPS_RD_SAE(ops...) } + +// VDIVPS_RD_SAE_Z: Divide Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VDIVPS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VDIVPS.RD_SAE.Z instruction to the active function. +func (c *Context) VDIVPS_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VDIVPS_RD_SAE_Z(z, z1, k, z2)) +} + +// VDIVPS_RD_SAE_Z: Divide Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VDIVPS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VDIVPS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VDIVPS_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VDIVPS_RD_SAE_Z(z, z1, k, z2) } + +// VDIVPS_RN_SAE: Divide Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VDIVPS.RN_SAE zmm zmm k zmm +// VDIVPS.RN_SAE zmm zmm zmm +// Construct and append a VDIVPS.RN_SAE instruction to the active function. +func (c *Context) VDIVPS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VDIVPS_RN_SAE(ops...)) +} + +// VDIVPS_RN_SAE: Divide Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VDIVPS.RN_SAE zmm zmm k zmm +// VDIVPS.RN_SAE zmm zmm zmm +// Construct and append a VDIVPS.RN_SAE instruction to the active function. +// Operates on the global context. +func VDIVPS_RN_SAE(ops ...operand.Op) { ctx.VDIVPS_RN_SAE(ops...) } + +// VDIVPS_RN_SAE_Z: Divide Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VDIVPS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VDIVPS.RN_SAE.Z instruction to the active function. +func (c *Context) VDIVPS_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VDIVPS_RN_SAE_Z(z, z1, k, z2)) +} + +// VDIVPS_RN_SAE_Z: Divide Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VDIVPS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VDIVPS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VDIVPS_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VDIVPS_RN_SAE_Z(z, z1, k, z2) } + +// VDIVPS_RU_SAE: Divide Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VDIVPS.RU_SAE zmm zmm k zmm +// VDIVPS.RU_SAE zmm zmm zmm +// Construct and append a VDIVPS.RU_SAE instruction to the active function. +func (c *Context) VDIVPS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VDIVPS_RU_SAE(ops...)) +} + +// VDIVPS_RU_SAE: Divide Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VDIVPS.RU_SAE zmm zmm k zmm +// VDIVPS.RU_SAE zmm zmm zmm +// Construct and append a VDIVPS.RU_SAE instruction to the active function. +// Operates on the global context. +func VDIVPS_RU_SAE(ops ...operand.Op) { ctx.VDIVPS_RU_SAE(ops...) } + +// VDIVPS_RU_SAE_Z: Divide Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VDIVPS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VDIVPS.RU_SAE.Z instruction to the active function. +func (c *Context) VDIVPS_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VDIVPS_RU_SAE_Z(z, z1, k, z2)) +} + +// VDIVPS_RU_SAE_Z: Divide Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VDIVPS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VDIVPS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VDIVPS_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VDIVPS_RU_SAE_Z(z, z1, k, z2) } + +// VDIVPS_RZ_SAE: Divide Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VDIVPS.RZ_SAE zmm zmm k zmm +// VDIVPS.RZ_SAE zmm zmm zmm +// Construct and append a VDIVPS.RZ_SAE instruction to the active function. +func (c *Context) VDIVPS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VDIVPS_RZ_SAE(ops...)) +} + +// VDIVPS_RZ_SAE: Divide Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VDIVPS.RZ_SAE zmm zmm k zmm +// VDIVPS.RZ_SAE zmm zmm zmm +// Construct and append a VDIVPS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VDIVPS_RZ_SAE(ops ...operand.Op) { ctx.VDIVPS_RZ_SAE(ops...) } + +// VDIVPS_RZ_SAE_Z: Divide Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VDIVPS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VDIVPS.RZ_SAE.Z instruction to the active function. +func (c *Context) VDIVPS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VDIVPS_RZ_SAE_Z(z, z1, k, z2)) +} + +// VDIVPS_RZ_SAE_Z: Divide Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VDIVPS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VDIVPS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VDIVPS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VDIVPS_RZ_SAE_Z(z, z1, k, z2) } + +// VDIVPS_Z: Divide Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VDIVPS.Z m128 xmm k xmm +// VDIVPS.Z m256 ymm k ymm +// VDIVPS.Z xmm xmm k xmm +// VDIVPS.Z ymm ymm k ymm +// VDIVPS.Z m512 zmm k zmm +// VDIVPS.Z zmm zmm k zmm +// Construct and append a VDIVPS.Z instruction to the active function. +func (c *Context) VDIVPS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VDIVPS_Z(mxyz, xyz, k, xyz1)) +} + +// VDIVPS_Z: Divide Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VDIVPS.Z m128 xmm k xmm +// VDIVPS.Z m256 ymm k ymm +// VDIVPS.Z xmm xmm k xmm +// VDIVPS.Z ymm ymm k ymm +// VDIVPS.Z m512 zmm k zmm +// VDIVPS.Z zmm zmm k zmm +// Construct and append a VDIVPS.Z instruction to the active function. +// Operates on the global context. +func VDIVPS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VDIVPS_Z(mxyz, xyz, k, xyz1) } + +// VDIVSD: Divide Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VDIVSD m64 xmm xmm +// VDIVSD xmm xmm xmm +// VDIVSD m64 xmm k xmm +// VDIVSD xmm xmm k xmm +// Construct and append a VDIVSD instruction to the active function. +func (c *Context) VDIVSD(ops ...operand.Op) { + c.addinstruction(x86.VDIVSD(ops...)) +} + +// VDIVSD: Divide Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VDIVSD m64 xmm xmm +// VDIVSD xmm xmm xmm +// VDIVSD m64 xmm k xmm +// VDIVSD xmm xmm k xmm +// Construct and append a VDIVSD instruction to the active function. +// Operates on the global context. +func VDIVSD(ops ...operand.Op) { ctx.VDIVSD(ops...) } + +// VDIVSD_RD_SAE: Divide Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VDIVSD.RD_SAE xmm xmm k xmm +// VDIVSD.RD_SAE xmm xmm xmm +// Construct and append a VDIVSD.RD_SAE instruction to the active function. +func (c *Context) VDIVSD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VDIVSD_RD_SAE(ops...)) +} + +// VDIVSD_RD_SAE: Divide Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VDIVSD.RD_SAE xmm xmm k xmm +// VDIVSD.RD_SAE xmm xmm xmm +// Construct and append a VDIVSD.RD_SAE instruction to the active function. +// Operates on the global context. +func VDIVSD_RD_SAE(ops ...operand.Op) { ctx.VDIVSD_RD_SAE(ops...) } + +// VDIVSD_RD_SAE_Z: Divide Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VDIVSD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VDIVSD.RD_SAE.Z instruction to the active function. +func (c *Context) VDIVSD_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VDIVSD_RD_SAE_Z(x, x1, k, x2)) +} + +// VDIVSD_RD_SAE_Z: Divide Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VDIVSD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VDIVSD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VDIVSD_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VDIVSD_RD_SAE_Z(x, x1, k, x2) } + +// VDIVSD_RN_SAE: Divide Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VDIVSD.RN_SAE xmm xmm k xmm +// VDIVSD.RN_SAE xmm xmm xmm +// Construct and append a VDIVSD.RN_SAE instruction to the active function. +func (c *Context) VDIVSD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VDIVSD_RN_SAE(ops...)) +} + +// VDIVSD_RN_SAE: Divide Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VDIVSD.RN_SAE xmm xmm k xmm +// VDIVSD.RN_SAE xmm xmm xmm +// Construct and append a VDIVSD.RN_SAE instruction to the active function. +// Operates on the global context. +func VDIVSD_RN_SAE(ops ...operand.Op) { ctx.VDIVSD_RN_SAE(ops...) } + +// VDIVSD_RN_SAE_Z: Divide Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VDIVSD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VDIVSD.RN_SAE.Z instruction to the active function. +func (c *Context) VDIVSD_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VDIVSD_RN_SAE_Z(x, x1, k, x2)) +} + +// VDIVSD_RN_SAE_Z: Divide Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VDIVSD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VDIVSD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VDIVSD_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VDIVSD_RN_SAE_Z(x, x1, k, x2) } + +// VDIVSD_RU_SAE: Divide Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VDIVSD.RU_SAE xmm xmm k xmm +// VDIVSD.RU_SAE xmm xmm xmm +// Construct and append a VDIVSD.RU_SAE instruction to the active function. +func (c *Context) VDIVSD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VDIVSD_RU_SAE(ops...)) +} + +// VDIVSD_RU_SAE: Divide Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VDIVSD.RU_SAE xmm xmm k xmm +// VDIVSD.RU_SAE xmm xmm xmm +// Construct and append a VDIVSD.RU_SAE instruction to the active function. +// Operates on the global context. +func VDIVSD_RU_SAE(ops ...operand.Op) { ctx.VDIVSD_RU_SAE(ops...) } + +// VDIVSD_RU_SAE_Z: Divide Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VDIVSD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VDIVSD.RU_SAE.Z instruction to the active function. +func (c *Context) VDIVSD_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VDIVSD_RU_SAE_Z(x, x1, k, x2)) +} + +// VDIVSD_RU_SAE_Z: Divide Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VDIVSD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VDIVSD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VDIVSD_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VDIVSD_RU_SAE_Z(x, x1, k, x2) } + +// VDIVSD_RZ_SAE: Divide Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VDIVSD.RZ_SAE xmm xmm k xmm +// VDIVSD.RZ_SAE xmm xmm xmm +// Construct and append a VDIVSD.RZ_SAE instruction to the active function. +func (c *Context) VDIVSD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VDIVSD_RZ_SAE(ops...)) +} + +// VDIVSD_RZ_SAE: Divide Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VDIVSD.RZ_SAE xmm xmm k xmm +// VDIVSD.RZ_SAE xmm xmm xmm +// Construct and append a VDIVSD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VDIVSD_RZ_SAE(ops ...operand.Op) { ctx.VDIVSD_RZ_SAE(ops...) } + +// VDIVSD_RZ_SAE_Z: Divide Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VDIVSD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VDIVSD.RZ_SAE.Z instruction to the active function. +func (c *Context) VDIVSD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VDIVSD_RZ_SAE_Z(x, x1, k, x2)) +} + +// VDIVSD_RZ_SAE_Z: Divide Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VDIVSD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VDIVSD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VDIVSD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VDIVSD_RZ_SAE_Z(x, x1, k, x2) } + +// VDIVSD_Z: Divide Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VDIVSD.Z m64 xmm k xmm +// VDIVSD.Z xmm xmm k xmm +// Construct and append a VDIVSD.Z instruction to the active function. +func (c *Context) VDIVSD_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VDIVSD_Z(mx, x, k, x1)) +} + +// VDIVSD_Z: Divide Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VDIVSD.Z m64 xmm k xmm +// VDIVSD.Z xmm xmm k xmm +// Construct and append a VDIVSD.Z instruction to the active function. +// Operates on the global context. +func VDIVSD_Z(mx, x, k, x1 operand.Op) { ctx.VDIVSD_Z(mx, x, k, x1) } + +// VDIVSS: Divide Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VDIVSS m32 xmm xmm +// VDIVSS xmm xmm xmm +// VDIVSS m32 xmm k xmm +// VDIVSS xmm xmm k xmm +// Construct and append a VDIVSS instruction to the active function. +func (c *Context) VDIVSS(ops ...operand.Op) { + c.addinstruction(x86.VDIVSS(ops...)) +} + +// VDIVSS: Divide Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VDIVSS m32 xmm xmm +// VDIVSS xmm xmm xmm +// VDIVSS m32 xmm k xmm +// VDIVSS xmm xmm k xmm +// Construct and append a VDIVSS instruction to the active function. +// Operates on the global context. +func VDIVSS(ops ...operand.Op) { ctx.VDIVSS(ops...) } + +// VDIVSS_RD_SAE: Divide Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VDIVSS.RD_SAE xmm xmm k xmm +// VDIVSS.RD_SAE xmm xmm xmm +// Construct and append a VDIVSS.RD_SAE instruction to the active function. +func (c *Context) VDIVSS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VDIVSS_RD_SAE(ops...)) +} + +// VDIVSS_RD_SAE: Divide Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VDIVSS.RD_SAE xmm xmm k xmm +// VDIVSS.RD_SAE xmm xmm xmm +// Construct and append a VDIVSS.RD_SAE instruction to the active function. +// Operates on the global context. +func VDIVSS_RD_SAE(ops ...operand.Op) { ctx.VDIVSS_RD_SAE(ops...) } + +// VDIVSS_RD_SAE_Z: Divide Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VDIVSS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VDIVSS.RD_SAE.Z instruction to the active function. +func (c *Context) VDIVSS_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VDIVSS_RD_SAE_Z(x, x1, k, x2)) +} + +// VDIVSS_RD_SAE_Z: Divide Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VDIVSS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VDIVSS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VDIVSS_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VDIVSS_RD_SAE_Z(x, x1, k, x2) } + +// VDIVSS_RN_SAE: Divide Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VDIVSS.RN_SAE xmm xmm k xmm +// VDIVSS.RN_SAE xmm xmm xmm +// Construct and append a VDIVSS.RN_SAE instruction to the active function. +func (c *Context) VDIVSS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VDIVSS_RN_SAE(ops...)) +} + +// VDIVSS_RN_SAE: Divide Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VDIVSS.RN_SAE xmm xmm k xmm +// VDIVSS.RN_SAE xmm xmm xmm +// Construct and append a VDIVSS.RN_SAE instruction to the active function. +// Operates on the global context. +func VDIVSS_RN_SAE(ops ...operand.Op) { ctx.VDIVSS_RN_SAE(ops...) } + +// VDIVSS_RN_SAE_Z: Divide Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VDIVSS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VDIVSS.RN_SAE.Z instruction to the active function. +func (c *Context) VDIVSS_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VDIVSS_RN_SAE_Z(x, x1, k, x2)) +} + +// VDIVSS_RN_SAE_Z: Divide Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VDIVSS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VDIVSS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VDIVSS_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VDIVSS_RN_SAE_Z(x, x1, k, x2) } + +// VDIVSS_RU_SAE: Divide Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VDIVSS.RU_SAE xmm xmm k xmm +// VDIVSS.RU_SAE xmm xmm xmm +// Construct and append a VDIVSS.RU_SAE instruction to the active function. +func (c *Context) VDIVSS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VDIVSS_RU_SAE(ops...)) +} + +// VDIVSS_RU_SAE: Divide Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VDIVSS.RU_SAE xmm xmm k xmm +// VDIVSS.RU_SAE xmm xmm xmm +// Construct and append a VDIVSS.RU_SAE instruction to the active function. +// Operates on the global context. +func VDIVSS_RU_SAE(ops ...operand.Op) { ctx.VDIVSS_RU_SAE(ops...) } + +// VDIVSS_RU_SAE_Z: Divide Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VDIVSS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VDIVSS.RU_SAE.Z instruction to the active function. +func (c *Context) VDIVSS_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VDIVSS_RU_SAE_Z(x, x1, k, x2)) +} + +// VDIVSS_RU_SAE_Z: Divide Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VDIVSS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VDIVSS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VDIVSS_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VDIVSS_RU_SAE_Z(x, x1, k, x2) } + +// VDIVSS_RZ_SAE: Divide Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VDIVSS.RZ_SAE xmm xmm k xmm +// VDIVSS.RZ_SAE xmm xmm xmm +// Construct and append a VDIVSS.RZ_SAE instruction to the active function. +func (c *Context) VDIVSS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VDIVSS_RZ_SAE(ops...)) +} + +// VDIVSS_RZ_SAE: Divide Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VDIVSS.RZ_SAE xmm xmm k xmm +// VDIVSS.RZ_SAE xmm xmm xmm +// Construct and append a VDIVSS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VDIVSS_RZ_SAE(ops ...operand.Op) { ctx.VDIVSS_RZ_SAE(ops...) } + +// VDIVSS_RZ_SAE_Z: Divide Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VDIVSS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VDIVSS.RZ_SAE.Z instruction to the active function. +func (c *Context) VDIVSS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VDIVSS_RZ_SAE_Z(x, x1, k, x2)) +} + +// VDIVSS_RZ_SAE_Z: Divide Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VDIVSS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VDIVSS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VDIVSS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VDIVSS_RZ_SAE_Z(x, x1, k, x2) } + +// VDIVSS_Z: Divide Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VDIVSS.Z m32 xmm k xmm +// VDIVSS.Z xmm xmm k xmm +// Construct and append a VDIVSS.Z instruction to the active function. +func (c *Context) VDIVSS_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VDIVSS_Z(mx, x, k, x1)) +} + +// VDIVSS_Z: Divide Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VDIVSS.Z m32 xmm k xmm +// VDIVSS.Z xmm xmm k xmm +// Construct and append a VDIVSS.Z instruction to the active function. +// Operates on the global context. +func VDIVSS_Z(mx, x, k, x1 operand.Op) { ctx.VDIVSS_Z(mx, x, k, x1) } + +// VDPPD: Dot Product of Packed Double Precision Floating-Point Values. +// +// Forms: +// +// VDPPD imm8 m128 xmm xmm +// VDPPD imm8 xmm xmm xmm +// Construct and append a VDPPD instruction to the active function. +func (c *Context) VDPPD(i, mx, x, x1 operand.Op) { + c.addinstruction(x86.VDPPD(i, mx, x, x1)) +} + +// VDPPD: Dot Product of Packed Double Precision Floating-Point Values. +// +// Forms: +// +// VDPPD imm8 m128 xmm xmm +// VDPPD imm8 xmm xmm xmm +// Construct and append a VDPPD instruction to the active function. +// Operates on the global context. +func VDPPD(i, mx, x, x1 operand.Op) { ctx.VDPPD(i, mx, x, x1) } + +// VDPPS: Dot Product of Packed Single Precision Floating-Point Values. +// +// Forms: +// +// VDPPS imm8 m128 xmm xmm +// VDPPS imm8 m256 ymm ymm +// VDPPS imm8 xmm xmm xmm +// VDPPS imm8 ymm ymm ymm +// Construct and append a VDPPS instruction to the active function. +func (c *Context) VDPPS(i, mxy, xy, xy1 operand.Op) { + c.addinstruction(x86.VDPPS(i, mxy, xy, xy1)) +} + +// VDPPS: Dot Product of Packed Single Precision Floating-Point Values. +// +// Forms: +// +// VDPPS imm8 m128 xmm xmm +// VDPPS imm8 m256 ymm ymm +// VDPPS imm8 xmm xmm xmm +// VDPPS imm8 ymm ymm ymm +// Construct and append a VDPPS instruction to the active function. +// Operates on the global context. +func VDPPS(i, mxy, xy, xy1 operand.Op) { ctx.VDPPS(i, mxy, xy, xy1) } + +// VEXP2PD: Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point Values with Less Than 2^-23 Relative Error. +// +// Forms: +// +// VEXP2PD m512 k zmm +// VEXP2PD m512 zmm +// VEXP2PD zmm k zmm +// VEXP2PD zmm zmm +// Construct and append a VEXP2PD instruction to the active function. +func (c *Context) VEXP2PD(ops ...operand.Op) { + c.addinstruction(x86.VEXP2PD(ops...)) +} + +// VEXP2PD: Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point Values with Less Than 2^-23 Relative Error. +// +// Forms: +// +// VEXP2PD m512 k zmm +// VEXP2PD m512 zmm +// VEXP2PD zmm k zmm +// VEXP2PD zmm zmm +// Construct and append a VEXP2PD instruction to the active function. +// Operates on the global context. +func VEXP2PD(ops ...operand.Op) { ctx.VEXP2PD(ops...) } + +// VEXP2PD_BCST: Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point Values with Less Than 2^-23 Relative Error (Broadcast). +// +// Forms: +// +// VEXP2PD.BCST m64 k zmm +// VEXP2PD.BCST m64 zmm +// Construct and append a VEXP2PD.BCST instruction to the active function. +func (c *Context) VEXP2PD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VEXP2PD_BCST(ops...)) +} + +// VEXP2PD_BCST: Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point Values with Less Than 2^-23 Relative Error (Broadcast). +// +// Forms: +// +// VEXP2PD.BCST m64 k zmm +// VEXP2PD.BCST m64 zmm +// Construct and append a VEXP2PD.BCST instruction to the active function. +// Operates on the global context. +func VEXP2PD_BCST(ops ...operand.Op) { ctx.VEXP2PD_BCST(ops...) } + +// VEXP2PD_BCST_Z: Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point Values with Less Than 2^-23 Relative Error (Broadcast, Zeroing Masking). +// +// Forms: +// +// VEXP2PD.BCST.Z m64 k zmm +// Construct and append a VEXP2PD.BCST.Z instruction to the active function. +func (c *Context) VEXP2PD_BCST_Z(m, k, z operand.Op) { + c.addinstruction(x86.VEXP2PD_BCST_Z(m, k, z)) +} + +// VEXP2PD_BCST_Z: Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point Values with Less Than 2^-23 Relative Error (Broadcast, Zeroing Masking). +// +// Forms: +// +// VEXP2PD.BCST.Z m64 k zmm +// Construct and append a VEXP2PD.BCST.Z instruction to the active function. +// Operates on the global context. +func VEXP2PD_BCST_Z(m, k, z operand.Op) { ctx.VEXP2PD_BCST_Z(m, k, z) } + +// VEXP2PD_SAE: Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point Values with Less Than 2^-23 Relative Error (Suppress All Exceptions). +// +// Forms: +// +// VEXP2PD.SAE zmm k zmm +// VEXP2PD.SAE zmm zmm +// Construct and append a VEXP2PD.SAE instruction to the active function. +func (c *Context) VEXP2PD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VEXP2PD_SAE(ops...)) +} + +// VEXP2PD_SAE: Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point Values with Less Than 2^-23 Relative Error (Suppress All Exceptions). +// +// Forms: +// +// VEXP2PD.SAE zmm k zmm +// VEXP2PD.SAE zmm zmm +// Construct and append a VEXP2PD.SAE instruction to the active function. +// Operates on the global context. +func VEXP2PD_SAE(ops ...operand.Op) { ctx.VEXP2PD_SAE(ops...) } + +// VEXP2PD_SAE_Z: Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point Values with Less Than 2^-23 Relative Error (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VEXP2PD.SAE.Z zmm k zmm +// Construct and append a VEXP2PD.SAE.Z instruction to the active function. +func (c *Context) VEXP2PD_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VEXP2PD_SAE_Z(z, k, z1)) +} + +// VEXP2PD_SAE_Z: Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point Values with Less Than 2^-23 Relative Error (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VEXP2PD.SAE.Z zmm k zmm +// Construct and append a VEXP2PD.SAE.Z instruction to the active function. +// Operates on the global context. +func VEXP2PD_SAE_Z(z, k, z1 operand.Op) { ctx.VEXP2PD_SAE_Z(z, k, z1) } + +// VEXP2PD_Z: Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point Values with Less Than 2^-23 Relative Error (Zeroing Masking). +// +// Forms: +// +// VEXP2PD.Z m512 k zmm +// VEXP2PD.Z zmm k zmm +// Construct and append a VEXP2PD.Z instruction to the active function. +func (c *Context) VEXP2PD_Z(mz, k, z operand.Op) { + c.addinstruction(x86.VEXP2PD_Z(mz, k, z)) +} + +// VEXP2PD_Z: Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point Values with Less Than 2^-23 Relative Error (Zeroing Masking). +// +// Forms: +// +// VEXP2PD.Z m512 k zmm +// VEXP2PD.Z zmm k zmm +// Construct and append a VEXP2PD.Z instruction to the active function. +// Operates on the global context. +func VEXP2PD_Z(mz, k, z operand.Op) { ctx.VEXP2PD_Z(mz, k, z) } + +// VEXP2PS: Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point Values with Less Than 2^-23 Relative Error. +// +// Forms: +// +// VEXP2PS m512 k zmm +// VEXP2PS m512 zmm +// VEXP2PS zmm k zmm +// VEXP2PS zmm zmm +// Construct and append a VEXP2PS instruction to the active function. +func (c *Context) VEXP2PS(ops ...operand.Op) { + c.addinstruction(x86.VEXP2PS(ops...)) +} + +// VEXP2PS: Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point Values with Less Than 2^-23 Relative Error. +// +// Forms: +// +// VEXP2PS m512 k zmm +// VEXP2PS m512 zmm +// VEXP2PS zmm k zmm +// VEXP2PS zmm zmm +// Construct and append a VEXP2PS instruction to the active function. +// Operates on the global context. +func VEXP2PS(ops ...operand.Op) { ctx.VEXP2PS(ops...) } + +// VEXP2PS_BCST: Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point Values with Less Than 2^-23 Relative Error (Broadcast). +// +// Forms: +// +// VEXP2PS.BCST m32 k zmm +// VEXP2PS.BCST m32 zmm +// Construct and append a VEXP2PS.BCST instruction to the active function. +func (c *Context) VEXP2PS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VEXP2PS_BCST(ops...)) +} + +// VEXP2PS_BCST: Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point Values with Less Than 2^-23 Relative Error (Broadcast). +// +// Forms: +// +// VEXP2PS.BCST m32 k zmm +// VEXP2PS.BCST m32 zmm +// Construct and append a VEXP2PS.BCST instruction to the active function. +// Operates on the global context. +func VEXP2PS_BCST(ops ...operand.Op) { ctx.VEXP2PS_BCST(ops...) } + +// VEXP2PS_BCST_Z: Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point Values with Less Than 2^-23 Relative Error (Broadcast, Zeroing Masking). +// +// Forms: +// +// VEXP2PS.BCST.Z m32 k zmm +// Construct and append a VEXP2PS.BCST.Z instruction to the active function. +func (c *Context) VEXP2PS_BCST_Z(m, k, z operand.Op) { + c.addinstruction(x86.VEXP2PS_BCST_Z(m, k, z)) +} + +// VEXP2PS_BCST_Z: Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point Values with Less Than 2^-23 Relative Error (Broadcast, Zeroing Masking). +// +// Forms: +// +// VEXP2PS.BCST.Z m32 k zmm +// Construct and append a VEXP2PS.BCST.Z instruction to the active function. +// Operates on the global context. +func VEXP2PS_BCST_Z(m, k, z operand.Op) { ctx.VEXP2PS_BCST_Z(m, k, z) } + +// VEXP2PS_SAE: Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point Values with Less Than 2^-23 Relative Error (Suppress All Exceptions). +// +// Forms: +// +// VEXP2PS.SAE zmm k zmm +// VEXP2PS.SAE zmm zmm +// Construct and append a VEXP2PS.SAE instruction to the active function. +func (c *Context) VEXP2PS_SAE(ops ...operand.Op) { + c.addinstruction(x86.VEXP2PS_SAE(ops...)) +} + +// VEXP2PS_SAE: Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point Values with Less Than 2^-23 Relative Error (Suppress All Exceptions). +// +// Forms: +// +// VEXP2PS.SAE zmm k zmm +// VEXP2PS.SAE zmm zmm +// Construct and append a VEXP2PS.SAE instruction to the active function. +// Operates on the global context. +func VEXP2PS_SAE(ops ...operand.Op) { ctx.VEXP2PS_SAE(ops...) } + +// VEXP2PS_SAE_Z: Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point Values with Less Than 2^-23 Relative Error (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VEXP2PS.SAE.Z zmm k zmm +// Construct and append a VEXP2PS.SAE.Z instruction to the active function. +func (c *Context) VEXP2PS_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VEXP2PS_SAE_Z(z, k, z1)) +} + +// VEXP2PS_SAE_Z: Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point Values with Less Than 2^-23 Relative Error (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VEXP2PS.SAE.Z zmm k zmm +// Construct and append a VEXP2PS.SAE.Z instruction to the active function. +// Operates on the global context. +func VEXP2PS_SAE_Z(z, k, z1 operand.Op) { ctx.VEXP2PS_SAE_Z(z, k, z1) } + +// VEXP2PS_Z: Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point Values with Less Than 2^-23 Relative Error (Zeroing Masking). +// +// Forms: +// +// VEXP2PS.Z m512 k zmm +// VEXP2PS.Z zmm k zmm +// Construct and append a VEXP2PS.Z instruction to the active function. +func (c *Context) VEXP2PS_Z(mz, k, z operand.Op) { + c.addinstruction(x86.VEXP2PS_Z(mz, k, z)) +} + +// VEXP2PS_Z: Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point Values with Less Than 2^-23 Relative Error (Zeroing Masking). +// +// Forms: +// +// VEXP2PS.Z m512 k zmm +// VEXP2PS.Z zmm k zmm +// Construct and append a VEXP2PS.Z instruction to the active function. +// Operates on the global context. +func VEXP2PS_Z(mz, k, z operand.Op) { ctx.VEXP2PS_Z(mz, k, z) } + +// VEXPANDPD: Load Sparse Packed Double-Precision Floating-Point Values from Dense Memory. +// +// Forms: +// +// VEXPANDPD m256 k ymm +// VEXPANDPD m256 ymm +// VEXPANDPD ymm k ymm +// VEXPANDPD ymm ymm +// VEXPANDPD m512 k zmm +// VEXPANDPD m512 zmm +// VEXPANDPD zmm k zmm +// VEXPANDPD zmm zmm +// VEXPANDPD m128 k xmm +// VEXPANDPD m128 xmm +// VEXPANDPD xmm k xmm +// VEXPANDPD xmm xmm +// Construct and append a VEXPANDPD instruction to the active function. +func (c *Context) VEXPANDPD(ops ...operand.Op) { + c.addinstruction(x86.VEXPANDPD(ops...)) +} + +// VEXPANDPD: Load Sparse Packed Double-Precision Floating-Point Values from Dense Memory. +// +// Forms: +// +// VEXPANDPD m256 k ymm +// VEXPANDPD m256 ymm +// VEXPANDPD ymm k ymm +// VEXPANDPD ymm ymm +// VEXPANDPD m512 k zmm +// VEXPANDPD m512 zmm +// VEXPANDPD zmm k zmm +// VEXPANDPD zmm zmm +// VEXPANDPD m128 k xmm +// VEXPANDPD m128 xmm +// VEXPANDPD xmm k xmm +// VEXPANDPD xmm xmm +// Construct and append a VEXPANDPD instruction to the active function. +// Operates on the global context. +func VEXPANDPD(ops ...operand.Op) { ctx.VEXPANDPD(ops...) } + +// VEXPANDPD_Z: Load Sparse Packed Double-Precision Floating-Point Values from Dense Memory (Zeroing Masking). +// +// Forms: +// +// VEXPANDPD.Z m256 k ymm +// VEXPANDPD.Z ymm k ymm +// VEXPANDPD.Z m512 k zmm +// VEXPANDPD.Z zmm k zmm +// VEXPANDPD.Z m128 k xmm +// VEXPANDPD.Z xmm k xmm +// Construct and append a VEXPANDPD.Z instruction to the active function. +func (c *Context) VEXPANDPD_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VEXPANDPD_Z(mxyz, k, xyz)) +} + +// VEXPANDPD_Z: Load Sparse Packed Double-Precision Floating-Point Values from Dense Memory (Zeroing Masking). +// +// Forms: +// +// VEXPANDPD.Z m256 k ymm +// VEXPANDPD.Z ymm k ymm +// VEXPANDPD.Z m512 k zmm +// VEXPANDPD.Z zmm k zmm +// VEXPANDPD.Z m128 k xmm +// VEXPANDPD.Z xmm k xmm +// Construct and append a VEXPANDPD.Z instruction to the active function. +// Operates on the global context. +func VEXPANDPD_Z(mxyz, k, xyz operand.Op) { ctx.VEXPANDPD_Z(mxyz, k, xyz) } + +// VEXPANDPS: Load Sparse Packed Single-Precision Floating-Point Values from Dense Memory. +// +// Forms: +// +// VEXPANDPS m128 k xmm +// VEXPANDPS m128 xmm +// VEXPANDPS m256 k ymm +// VEXPANDPS m256 ymm +// VEXPANDPS xmm k xmm +// VEXPANDPS xmm xmm +// VEXPANDPS ymm k ymm +// VEXPANDPS ymm ymm +// VEXPANDPS m512 k zmm +// VEXPANDPS m512 zmm +// VEXPANDPS zmm k zmm +// VEXPANDPS zmm zmm +// Construct and append a VEXPANDPS instruction to the active function. +func (c *Context) VEXPANDPS(ops ...operand.Op) { + c.addinstruction(x86.VEXPANDPS(ops...)) +} + +// VEXPANDPS: Load Sparse Packed Single-Precision Floating-Point Values from Dense Memory. +// +// Forms: +// +// VEXPANDPS m128 k xmm +// VEXPANDPS m128 xmm +// VEXPANDPS m256 k ymm +// VEXPANDPS m256 ymm +// VEXPANDPS xmm k xmm +// VEXPANDPS xmm xmm +// VEXPANDPS ymm k ymm +// VEXPANDPS ymm ymm +// VEXPANDPS m512 k zmm +// VEXPANDPS m512 zmm +// VEXPANDPS zmm k zmm +// VEXPANDPS zmm zmm +// Construct and append a VEXPANDPS instruction to the active function. +// Operates on the global context. +func VEXPANDPS(ops ...operand.Op) { ctx.VEXPANDPS(ops...) } + +// VEXPANDPS_Z: Load Sparse Packed Single-Precision Floating-Point Values from Dense Memory (Zeroing Masking). +// +// Forms: +// +// VEXPANDPS.Z m128 k xmm +// VEXPANDPS.Z m256 k ymm +// VEXPANDPS.Z xmm k xmm +// VEXPANDPS.Z ymm k ymm +// VEXPANDPS.Z m512 k zmm +// VEXPANDPS.Z zmm k zmm +// Construct and append a VEXPANDPS.Z instruction to the active function. +func (c *Context) VEXPANDPS_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VEXPANDPS_Z(mxyz, k, xyz)) +} + +// VEXPANDPS_Z: Load Sparse Packed Single-Precision Floating-Point Values from Dense Memory (Zeroing Masking). +// +// Forms: +// +// VEXPANDPS.Z m128 k xmm +// VEXPANDPS.Z m256 k ymm +// VEXPANDPS.Z xmm k xmm +// VEXPANDPS.Z ymm k ymm +// VEXPANDPS.Z m512 k zmm +// VEXPANDPS.Z zmm k zmm +// Construct and append a VEXPANDPS.Z instruction to the active function. +// Operates on the global context. +func VEXPANDPS_Z(mxyz, k, xyz operand.Op) { ctx.VEXPANDPS_Z(mxyz, k, xyz) } + +// VEXTRACTF128: Extract Packed Floating-Point Values. +// +// Forms: +// +// VEXTRACTF128 imm8 ymm m128 +// VEXTRACTF128 imm8 ymm xmm +// Construct and append a VEXTRACTF128 instruction to the active function. +func (c *Context) VEXTRACTF128(i, y, mx operand.Op) { + c.addinstruction(x86.VEXTRACTF128(i, y, mx)) +} + +// VEXTRACTF128: Extract Packed Floating-Point Values. +// +// Forms: +// +// VEXTRACTF128 imm8 ymm m128 +// VEXTRACTF128 imm8 ymm xmm +// Construct and append a VEXTRACTF128 instruction to the active function. +// Operates on the global context. +func VEXTRACTF128(i, y, mx operand.Op) { ctx.VEXTRACTF128(i, y, mx) } + +// VEXTRACTF32X4: Extract 128 Bits of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VEXTRACTF32X4 imm8 ymm k m128 +// VEXTRACTF32X4 imm8 ymm k xmm +// VEXTRACTF32X4 imm8 ymm m128 +// VEXTRACTF32X4 imm8 ymm xmm +// VEXTRACTF32X4 imm8 zmm k m128 +// VEXTRACTF32X4 imm8 zmm k xmm +// VEXTRACTF32X4 imm8 zmm m128 +// VEXTRACTF32X4 imm8 zmm xmm +// Construct and append a VEXTRACTF32X4 instruction to the active function. +func (c *Context) VEXTRACTF32X4(ops ...operand.Op) { + c.addinstruction(x86.VEXTRACTF32X4(ops...)) +} + +// VEXTRACTF32X4: Extract 128 Bits of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VEXTRACTF32X4 imm8 ymm k m128 +// VEXTRACTF32X4 imm8 ymm k xmm +// VEXTRACTF32X4 imm8 ymm m128 +// VEXTRACTF32X4 imm8 ymm xmm +// VEXTRACTF32X4 imm8 zmm k m128 +// VEXTRACTF32X4 imm8 zmm k xmm +// VEXTRACTF32X4 imm8 zmm m128 +// VEXTRACTF32X4 imm8 zmm xmm +// Construct and append a VEXTRACTF32X4 instruction to the active function. +// Operates on the global context. +func VEXTRACTF32X4(ops ...operand.Op) { ctx.VEXTRACTF32X4(ops...) } + +// VEXTRACTF32X4_Z: Extract 128 Bits of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VEXTRACTF32X4.Z imm8 ymm k m128 +// VEXTRACTF32X4.Z imm8 ymm k xmm +// VEXTRACTF32X4.Z imm8 zmm k m128 +// VEXTRACTF32X4.Z imm8 zmm k xmm +// Construct and append a VEXTRACTF32X4.Z instruction to the active function. +func (c *Context) VEXTRACTF32X4_Z(i, yz, k, mx operand.Op) { + c.addinstruction(x86.VEXTRACTF32X4_Z(i, yz, k, mx)) +} + +// VEXTRACTF32X4_Z: Extract 128 Bits of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VEXTRACTF32X4.Z imm8 ymm k m128 +// VEXTRACTF32X4.Z imm8 ymm k xmm +// VEXTRACTF32X4.Z imm8 zmm k m128 +// VEXTRACTF32X4.Z imm8 zmm k xmm +// Construct and append a VEXTRACTF32X4.Z instruction to the active function. +// Operates on the global context. +func VEXTRACTF32X4_Z(i, yz, k, mx operand.Op) { ctx.VEXTRACTF32X4_Z(i, yz, k, mx) } + +// VEXTRACTF32X8: Extract 256 Bits of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VEXTRACTF32X8 imm8 zmm k m256 +// VEXTRACTF32X8 imm8 zmm k ymm +// VEXTRACTF32X8 imm8 zmm m256 +// VEXTRACTF32X8 imm8 zmm ymm +// Construct and append a VEXTRACTF32X8 instruction to the active function. +func (c *Context) VEXTRACTF32X8(ops ...operand.Op) { + c.addinstruction(x86.VEXTRACTF32X8(ops...)) +} + +// VEXTRACTF32X8: Extract 256 Bits of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VEXTRACTF32X8 imm8 zmm k m256 +// VEXTRACTF32X8 imm8 zmm k ymm +// VEXTRACTF32X8 imm8 zmm m256 +// VEXTRACTF32X8 imm8 zmm ymm +// Construct and append a VEXTRACTF32X8 instruction to the active function. +// Operates on the global context. +func VEXTRACTF32X8(ops ...operand.Op) { ctx.VEXTRACTF32X8(ops...) } + +// VEXTRACTF32X8_Z: Extract 256 Bits of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VEXTRACTF32X8.Z imm8 zmm k m256 +// VEXTRACTF32X8.Z imm8 zmm k ymm +// Construct and append a VEXTRACTF32X8.Z instruction to the active function. +func (c *Context) VEXTRACTF32X8_Z(i, z, k, my operand.Op) { + c.addinstruction(x86.VEXTRACTF32X8_Z(i, z, k, my)) +} + +// VEXTRACTF32X8_Z: Extract 256 Bits of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VEXTRACTF32X8.Z imm8 zmm k m256 +// VEXTRACTF32X8.Z imm8 zmm k ymm +// Construct and append a VEXTRACTF32X8.Z instruction to the active function. +// Operates on the global context. +func VEXTRACTF32X8_Z(i, z, k, my operand.Op) { ctx.VEXTRACTF32X8_Z(i, z, k, my) } + +// VEXTRACTF64X2: Extract 128 Bits of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VEXTRACTF64X2 imm8 ymm k m128 +// VEXTRACTF64X2 imm8 ymm k xmm +// VEXTRACTF64X2 imm8 ymm m128 +// VEXTRACTF64X2 imm8 ymm xmm +// VEXTRACTF64X2 imm8 zmm k m128 +// VEXTRACTF64X2 imm8 zmm k xmm +// VEXTRACTF64X2 imm8 zmm m128 +// VEXTRACTF64X2 imm8 zmm xmm +// Construct and append a VEXTRACTF64X2 instruction to the active function. +func (c *Context) VEXTRACTF64X2(ops ...operand.Op) { + c.addinstruction(x86.VEXTRACTF64X2(ops...)) +} + +// VEXTRACTF64X2: Extract 128 Bits of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VEXTRACTF64X2 imm8 ymm k m128 +// VEXTRACTF64X2 imm8 ymm k xmm +// VEXTRACTF64X2 imm8 ymm m128 +// VEXTRACTF64X2 imm8 ymm xmm +// VEXTRACTF64X2 imm8 zmm k m128 +// VEXTRACTF64X2 imm8 zmm k xmm +// VEXTRACTF64X2 imm8 zmm m128 +// VEXTRACTF64X2 imm8 zmm xmm +// Construct and append a VEXTRACTF64X2 instruction to the active function. +// Operates on the global context. +func VEXTRACTF64X2(ops ...operand.Op) { ctx.VEXTRACTF64X2(ops...) } + +// VEXTRACTF64X2_Z: Extract 128 Bits of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VEXTRACTF64X2.Z imm8 ymm k m128 +// VEXTRACTF64X2.Z imm8 ymm k xmm +// VEXTRACTF64X2.Z imm8 zmm k m128 +// VEXTRACTF64X2.Z imm8 zmm k xmm +// Construct and append a VEXTRACTF64X2.Z instruction to the active function. +func (c *Context) VEXTRACTF64X2_Z(i, yz, k, mx operand.Op) { + c.addinstruction(x86.VEXTRACTF64X2_Z(i, yz, k, mx)) +} + +// VEXTRACTF64X2_Z: Extract 128 Bits of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VEXTRACTF64X2.Z imm8 ymm k m128 +// VEXTRACTF64X2.Z imm8 ymm k xmm +// VEXTRACTF64X2.Z imm8 zmm k m128 +// VEXTRACTF64X2.Z imm8 zmm k xmm +// Construct and append a VEXTRACTF64X2.Z instruction to the active function. +// Operates on the global context. +func VEXTRACTF64X2_Z(i, yz, k, mx operand.Op) { ctx.VEXTRACTF64X2_Z(i, yz, k, mx) } + +// VEXTRACTF64X4: Extract 256 Bits of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VEXTRACTF64X4 imm8 zmm k m256 +// VEXTRACTF64X4 imm8 zmm k ymm +// VEXTRACTF64X4 imm8 zmm m256 +// VEXTRACTF64X4 imm8 zmm ymm +// Construct and append a VEXTRACTF64X4 instruction to the active function. +func (c *Context) VEXTRACTF64X4(ops ...operand.Op) { + c.addinstruction(x86.VEXTRACTF64X4(ops...)) +} + +// VEXTRACTF64X4: Extract 256 Bits of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VEXTRACTF64X4 imm8 zmm k m256 +// VEXTRACTF64X4 imm8 zmm k ymm +// VEXTRACTF64X4 imm8 zmm m256 +// VEXTRACTF64X4 imm8 zmm ymm +// Construct and append a VEXTRACTF64X4 instruction to the active function. +// Operates on the global context. +func VEXTRACTF64X4(ops ...operand.Op) { ctx.VEXTRACTF64X4(ops...) } + +// VEXTRACTF64X4_Z: Extract 256 Bits of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VEXTRACTF64X4.Z imm8 zmm k m256 +// VEXTRACTF64X4.Z imm8 zmm k ymm +// Construct and append a VEXTRACTF64X4.Z instruction to the active function. +func (c *Context) VEXTRACTF64X4_Z(i, z, k, my operand.Op) { + c.addinstruction(x86.VEXTRACTF64X4_Z(i, z, k, my)) +} + +// VEXTRACTF64X4_Z: Extract 256 Bits of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VEXTRACTF64X4.Z imm8 zmm k m256 +// VEXTRACTF64X4.Z imm8 zmm k ymm +// Construct and append a VEXTRACTF64X4.Z instruction to the active function. +// Operates on the global context. +func VEXTRACTF64X4_Z(i, z, k, my operand.Op) { ctx.VEXTRACTF64X4_Z(i, z, k, my) } + +// VEXTRACTI128: Extract Packed Integer Values. +// +// Forms: +// +// VEXTRACTI128 imm8 ymm m128 +// VEXTRACTI128 imm8 ymm xmm +// Construct and append a VEXTRACTI128 instruction to the active function. +func (c *Context) VEXTRACTI128(i, y, mx operand.Op) { + c.addinstruction(x86.VEXTRACTI128(i, y, mx)) +} + +// VEXTRACTI128: Extract Packed Integer Values. +// +// Forms: +// +// VEXTRACTI128 imm8 ymm m128 +// VEXTRACTI128 imm8 ymm xmm +// Construct and append a VEXTRACTI128 instruction to the active function. +// Operates on the global context. +func VEXTRACTI128(i, y, mx operand.Op) { ctx.VEXTRACTI128(i, y, mx) } + +// VEXTRACTI32X4: Extract 128 Bits of Packed Doubleword Integer Values. +// +// Forms: +// +// VEXTRACTI32X4 imm8 ymm k m128 +// VEXTRACTI32X4 imm8 ymm k xmm +// VEXTRACTI32X4 imm8 ymm m128 +// VEXTRACTI32X4 imm8 ymm xmm +// VEXTRACTI32X4 imm8 zmm k m128 +// VEXTRACTI32X4 imm8 zmm k xmm +// VEXTRACTI32X4 imm8 zmm m128 +// VEXTRACTI32X4 imm8 zmm xmm +// Construct and append a VEXTRACTI32X4 instruction to the active function. +func (c *Context) VEXTRACTI32X4(ops ...operand.Op) { + c.addinstruction(x86.VEXTRACTI32X4(ops...)) +} + +// VEXTRACTI32X4: Extract 128 Bits of Packed Doubleword Integer Values. +// +// Forms: +// +// VEXTRACTI32X4 imm8 ymm k m128 +// VEXTRACTI32X4 imm8 ymm k xmm +// VEXTRACTI32X4 imm8 ymm m128 +// VEXTRACTI32X4 imm8 ymm xmm +// VEXTRACTI32X4 imm8 zmm k m128 +// VEXTRACTI32X4 imm8 zmm k xmm +// VEXTRACTI32X4 imm8 zmm m128 +// VEXTRACTI32X4 imm8 zmm xmm +// Construct and append a VEXTRACTI32X4 instruction to the active function. +// Operates on the global context. +func VEXTRACTI32X4(ops ...operand.Op) { ctx.VEXTRACTI32X4(ops...) } + +// VEXTRACTI32X4_Z: Extract 128 Bits of Packed Doubleword Integer Values (Zeroing Masking). +// +// Forms: +// +// VEXTRACTI32X4.Z imm8 ymm k m128 +// VEXTRACTI32X4.Z imm8 ymm k xmm +// VEXTRACTI32X4.Z imm8 zmm k m128 +// VEXTRACTI32X4.Z imm8 zmm k xmm +// Construct and append a VEXTRACTI32X4.Z instruction to the active function. +func (c *Context) VEXTRACTI32X4_Z(i, yz, k, mx operand.Op) { + c.addinstruction(x86.VEXTRACTI32X4_Z(i, yz, k, mx)) +} + +// VEXTRACTI32X4_Z: Extract 128 Bits of Packed Doubleword Integer Values (Zeroing Masking). +// +// Forms: +// +// VEXTRACTI32X4.Z imm8 ymm k m128 +// VEXTRACTI32X4.Z imm8 ymm k xmm +// VEXTRACTI32X4.Z imm8 zmm k m128 +// VEXTRACTI32X4.Z imm8 zmm k xmm +// Construct and append a VEXTRACTI32X4.Z instruction to the active function. +// Operates on the global context. +func VEXTRACTI32X4_Z(i, yz, k, mx operand.Op) { ctx.VEXTRACTI32X4_Z(i, yz, k, mx) } + +// VEXTRACTI32X8: Extract 256 Bits of Packed Doubleword Integer Values. +// +// Forms: +// +// VEXTRACTI32X8 imm8 zmm k m256 +// VEXTRACTI32X8 imm8 zmm k ymm +// VEXTRACTI32X8 imm8 zmm m256 +// VEXTRACTI32X8 imm8 zmm ymm +// Construct and append a VEXTRACTI32X8 instruction to the active function. +func (c *Context) VEXTRACTI32X8(ops ...operand.Op) { + c.addinstruction(x86.VEXTRACTI32X8(ops...)) +} + +// VEXTRACTI32X8: Extract 256 Bits of Packed Doubleword Integer Values. +// +// Forms: +// +// VEXTRACTI32X8 imm8 zmm k m256 +// VEXTRACTI32X8 imm8 zmm k ymm +// VEXTRACTI32X8 imm8 zmm m256 +// VEXTRACTI32X8 imm8 zmm ymm +// Construct and append a VEXTRACTI32X8 instruction to the active function. +// Operates on the global context. +func VEXTRACTI32X8(ops ...operand.Op) { ctx.VEXTRACTI32X8(ops...) } + +// VEXTRACTI32X8_Z: Extract 256 Bits of Packed Doubleword Integer Values (Zeroing Masking). +// +// Forms: +// +// VEXTRACTI32X8.Z imm8 zmm k m256 +// VEXTRACTI32X8.Z imm8 zmm k ymm +// Construct and append a VEXTRACTI32X8.Z instruction to the active function. +func (c *Context) VEXTRACTI32X8_Z(i, z, k, my operand.Op) { + c.addinstruction(x86.VEXTRACTI32X8_Z(i, z, k, my)) +} + +// VEXTRACTI32X8_Z: Extract 256 Bits of Packed Doubleword Integer Values (Zeroing Masking). +// +// Forms: +// +// VEXTRACTI32X8.Z imm8 zmm k m256 +// VEXTRACTI32X8.Z imm8 zmm k ymm +// Construct and append a VEXTRACTI32X8.Z instruction to the active function. +// Operates on the global context. +func VEXTRACTI32X8_Z(i, z, k, my operand.Op) { ctx.VEXTRACTI32X8_Z(i, z, k, my) } + +// VEXTRACTI64X2: Extract 128 Bits of Packed Quadword Integer Values. +// +// Forms: +// +// VEXTRACTI64X2 imm8 ymm k m128 +// VEXTRACTI64X2 imm8 ymm k xmm +// VEXTRACTI64X2 imm8 ymm m128 +// VEXTRACTI64X2 imm8 ymm xmm +// VEXTRACTI64X2 imm8 zmm k m128 +// VEXTRACTI64X2 imm8 zmm k xmm +// VEXTRACTI64X2 imm8 zmm m128 +// VEXTRACTI64X2 imm8 zmm xmm +// Construct and append a VEXTRACTI64X2 instruction to the active function. +func (c *Context) VEXTRACTI64X2(ops ...operand.Op) { + c.addinstruction(x86.VEXTRACTI64X2(ops...)) +} + +// VEXTRACTI64X2: Extract 128 Bits of Packed Quadword Integer Values. +// +// Forms: +// +// VEXTRACTI64X2 imm8 ymm k m128 +// VEXTRACTI64X2 imm8 ymm k xmm +// VEXTRACTI64X2 imm8 ymm m128 +// VEXTRACTI64X2 imm8 ymm xmm +// VEXTRACTI64X2 imm8 zmm k m128 +// VEXTRACTI64X2 imm8 zmm k xmm +// VEXTRACTI64X2 imm8 zmm m128 +// VEXTRACTI64X2 imm8 zmm xmm +// Construct and append a VEXTRACTI64X2 instruction to the active function. +// Operates on the global context. +func VEXTRACTI64X2(ops ...operand.Op) { ctx.VEXTRACTI64X2(ops...) } + +// VEXTRACTI64X2_Z: Extract 128 Bits of Packed Quadword Integer Values (Zeroing Masking). +// +// Forms: +// +// VEXTRACTI64X2.Z imm8 ymm k m128 +// VEXTRACTI64X2.Z imm8 ymm k xmm +// VEXTRACTI64X2.Z imm8 zmm k m128 +// VEXTRACTI64X2.Z imm8 zmm k xmm +// Construct and append a VEXTRACTI64X2.Z instruction to the active function. +func (c *Context) VEXTRACTI64X2_Z(i, yz, k, mx operand.Op) { + c.addinstruction(x86.VEXTRACTI64X2_Z(i, yz, k, mx)) +} + +// VEXTRACTI64X2_Z: Extract 128 Bits of Packed Quadword Integer Values (Zeroing Masking). +// +// Forms: +// +// VEXTRACTI64X2.Z imm8 ymm k m128 +// VEXTRACTI64X2.Z imm8 ymm k xmm +// VEXTRACTI64X2.Z imm8 zmm k m128 +// VEXTRACTI64X2.Z imm8 zmm k xmm +// Construct and append a VEXTRACTI64X2.Z instruction to the active function. +// Operates on the global context. +func VEXTRACTI64X2_Z(i, yz, k, mx operand.Op) { ctx.VEXTRACTI64X2_Z(i, yz, k, mx) } + +// VEXTRACTI64X4: Extract 256 Bits of Packed Quadword Integer Values. +// +// Forms: +// +// VEXTRACTI64X4 imm8 zmm k m256 +// VEXTRACTI64X4 imm8 zmm k ymm +// VEXTRACTI64X4 imm8 zmm m256 +// VEXTRACTI64X4 imm8 zmm ymm +// Construct and append a VEXTRACTI64X4 instruction to the active function. +func (c *Context) VEXTRACTI64X4(ops ...operand.Op) { + c.addinstruction(x86.VEXTRACTI64X4(ops...)) +} + +// VEXTRACTI64X4: Extract 256 Bits of Packed Quadword Integer Values. +// +// Forms: +// +// VEXTRACTI64X4 imm8 zmm k m256 +// VEXTRACTI64X4 imm8 zmm k ymm +// VEXTRACTI64X4 imm8 zmm m256 +// VEXTRACTI64X4 imm8 zmm ymm +// Construct and append a VEXTRACTI64X4 instruction to the active function. +// Operates on the global context. +func VEXTRACTI64X4(ops ...operand.Op) { ctx.VEXTRACTI64X4(ops...) } + +// VEXTRACTI64X4_Z: Extract 256 Bits of Packed Quadword Integer Values (Zeroing Masking). +// +// Forms: +// +// VEXTRACTI64X4.Z imm8 zmm k m256 +// VEXTRACTI64X4.Z imm8 zmm k ymm +// Construct and append a VEXTRACTI64X4.Z instruction to the active function. +func (c *Context) VEXTRACTI64X4_Z(i, z, k, my operand.Op) { + c.addinstruction(x86.VEXTRACTI64X4_Z(i, z, k, my)) +} + +// VEXTRACTI64X4_Z: Extract 256 Bits of Packed Quadword Integer Values (Zeroing Masking). +// +// Forms: +// +// VEXTRACTI64X4.Z imm8 zmm k m256 +// VEXTRACTI64X4.Z imm8 zmm k ymm +// Construct and append a VEXTRACTI64X4.Z instruction to the active function. +// Operates on the global context. +func VEXTRACTI64X4_Z(i, z, k, my operand.Op) { ctx.VEXTRACTI64X4_Z(i, z, k, my) } + +// VEXTRACTPS: Extract Packed Single Precision Floating-Point Value. +// +// Forms: +// +// VEXTRACTPS imm8 xmm m32 +// VEXTRACTPS imm8 xmm r32 +// Construct and append a VEXTRACTPS instruction to the active function. +func (c *Context) VEXTRACTPS(i, x, mr operand.Op) { + c.addinstruction(x86.VEXTRACTPS(i, x, mr)) +} + +// VEXTRACTPS: Extract Packed Single Precision Floating-Point Value. +// +// Forms: +// +// VEXTRACTPS imm8 xmm m32 +// VEXTRACTPS imm8 xmm r32 +// Construct and append a VEXTRACTPS instruction to the active function. +// Operates on the global context. +func VEXTRACTPS(i, x, mr operand.Op) { ctx.VEXTRACTPS(i, x, mr) } + +// VFIXUPIMMPD: Fix Up Special Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFIXUPIMMPD imm8 m128 xmm k xmm +// VFIXUPIMMPD imm8 m128 xmm xmm +// VFIXUPIMMPD imm8 m256 ymm k ymm +// VFIXUPIMMPD imm8 m256 ymm ymm +// VFIXUPIMMPD imm8 xmm xmm k xmm +// VFIXUPIMMPD imm8 xmm xmm xmm +// VFIXUPIMMPD imm8 ymm ymm k ymm +// VFIXUPIMMPD imm8 ymm ymm ymm +// VFIXUPIMMPD imm8 m512 zmm k zmm +// VFIXUPIMMPD imm8 m512 zmm zmm +// VFIXUPIMMPD imm8 zmm zmm k zmm +// VFIXUPIMMPD imm8 zmm zmm zmm +// Construct and append a VFIXUPIMMPD instruction to the active function. +func (c *Context) VFIXUPIMMPD(ops ...operand.Op) { + c.addinstruction(x86.VFIXUPIMMPD(ops...)) +} + +// VFIXUPIMMPD: Fix Up Special Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFIXUPIMMPD imm8 m128 xmm k xmm +// VFIXUPIMMPD imm8 m128 xmm xmm +// VFIXUPIMMPD imm8 m256 ymm k ymm +// VFIXUPIMMPD imm8 m256 ymm ymm +// VFIXUPIMMPD imm8 xmm xmm k xmm +// VFIXUPIMMPD imm8 xmm xmm xmm +// VFIXUPIMMPD imm8 ymm ymm k ymm +// VFIXUPIMMPD imm8 ymm ymm ymm +// VFIXUPIMMPD imm8 m512 zmm k zmm +// VFIXUPIMMPD imm8 m512 zmm zmm +// VFIXUPIMMPD imm8 zmm zmm k zmm +// VFIXUPIMMPD imm8 zmm zmm zmm +// Construct and append a VFIXUPIMMPD instruction to the active function. +// Operates on the global context. +func VFIXUPIMMPD(ops ...operand.Op) { ctx.VFIXUPIMMPD(ops...) } + +// VFIXUPIMMPD_BCST: Fix Up Special Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFIXUPIMMPD.BCST imm8 m64 xmm k xmm +// VFIXUPIMMPD.BCST imm8 m64 xmm xmm +// VFIXUPIMMPD.BCST imm8 m64 ymm k ymm +// VFIXUPIMMPD.BCST imm8 m64 ymm ymm +// VFIXUPIMMPD.BCST imm8 m64 zmm k zmm +// VFIXUPIMMPD.BCST imm8 m64 zmm zmm +// Construct and append a VFIXUPIMMPD.BCST instruction to the active function. +func (c *Context) VFIXUPIMMPD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFIXUPIMMPD_BCST(ops...)) +} + +// VFIXUPIMMPD_BCST: Fix Up Special Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFIXUPIMMPD.BCST imm8 m64 xmm k xmm +// VFIXUPIMMPD.BCST imm8 m64 xmm xmm +// VFIXUPIMMPD.BCST imm8 m64 ymm k ymm +// VFIXUPIMMPD.BCST imm8 m64 ymm ymm +// VFIXUPIMMPD.BCST imm8 m64 zmm k zmm +// VFIXUPIMMPD.BCST imm8 m64 zmm zmm +// Construct and append a VFIXUPIMMPD.BCST instruction to the active function. +// Operates on the global context. +func VFIXUPIMMPD_BCST(ops ...operand.Op) { ctx.VFIXUPIMMPD_BCST(ops...) } + +// VFIXUPIMMPD_BCST_Z: Fix Up Special Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFIXUPIMMPD.BCST.Z imm8 m64 xmm k xmm +// VFIXUPIMMPD.BCST.Z imm8 m64 ymm k ymm +// VFIXUPIMMPD.BCST.Z imm8 m64 zmm k zmm +// Construct and append a VFIXUPIMMPD.BCST.Z instruction to the active function. +func (c *Context) VFIXUPIMMPD_BCST_Z(i, m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFIXUPIMMPD_BCST_Z(i, m, xyz, k, xyz1)) +} + +// VFIXUPIMMPD_BCST_Z: Fix Up Special Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFIXUPIMMPD.BCST.Z imm8 m64 xmm k xmm +// VFIXUPIMMPD.BCST.Z imm8 m64 ymm k ymm +// VFIXUPIMMPD.BCST.Z imm8 m64 zmm k zmm +// Construct and append a VFIXUPIMMPD.BCST.Z instruction to the active function. +// Operates on the global context. +func VFIXUPIMMPD_BCST_Z(i, m, xyz, k, xyz1 operand.Op) { ctx.VFIXUPIMMPD_BCST_Z(i, m, xyz, k, xyz1) } + +// VFIXUPIMMPD_SAE: Fix Up Special Packed Double-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VFIXUPIMMPD.SAE imm8 zmm zmm k zmm +// VFIXUPIMMPD.SAE imm8 zmm zmm zmm +// Construct and append a VFIXUPIMMPD.SAE instruction to the active function. +func (c *Context) VFIXUPIMMPD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFIXUPIMMPD_SAE(ops...)) +} + +// VFIXUPIMMPD_SAE: Fix Up Special Packed Double-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VFIXUPIMMPD.SAE imm8 zmm zmm k zmm +// VFIXUPIMMPD.SAE imm8 zmm zmm zmm +// Construct and append a VFIXUPIMMPD.SAE instruction to the active function. +// Operates on the global context. +func VFIXUPIMMPD_SAE(ops ...operand.Op) { ctx.VFIXUPIMMPD_SAE(ops...) } + +// VFIXUPIMMPD_SAE_Z: Fix Up Special Packed Double-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VFIXUPIMMPD.SAE.Z imm8 zmm zmm k zmm +// Construct and append a VFIXUPIMMPD.SAE.Z instruction to the active function. +func (c *Context) VFIXUPIMMPD_SAE_Z(i, z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFIXUPIMMPD_SAE_Z(i, z, z1, k, z2)) +} + +// VFIXUPIMMPD_SAE_Z: Fix Up Special Packed Double-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VFIXUPIMMPD.SAE.Z imm8 zmm zmm k zmm +// Construct and append a VFIXUPIMMPD.SAE.Z instruction to the active function. +// Operates on the global context. +func VFIXUPIMMPD_SAE_Z(i, z, z1, k, z2 operand.Op) { ctx.VFIXUPIMMPD_SAE_Z(i, z, z1, k, z2) } + +// VFIXUPIMMPD_Z: Fix Up Special Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFIXUPIMMPD.Z imm8 m128 xmm k xmm +// VFIXUPIMMPD.Z imm8 m256 ymm k ymm +// VFIXUPIMMPD.Z imm8 xmm xmm k xmm +// VFIXUPIMMPD.Z imm8 ymm ymm k ymm +// VFIXUPIMMPD.Z imm8 m512 zmm k zmm +// VFIXUPIMMPD.Z imm8 zmm zmm k zmm +// Construct and append a VFIXUPIMMPD.Z instruction to the active function. +func (c *Context) VFIXUPIMMPD_Z(i, mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFIXUPIMMPD_Z(i, mxyz, xyz, k, xyz1)) +} + +// VFIXUPIMMPD_Z: Fix Up Special Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFIXUPIMMPD.Z imm8 m128 xmm k xmm +// VFIXUPIMMPD.Z imm8 m256 ymm k ymm +// VFIXUPIMMPD.Z imm8 xmm xmm k xmm +// VFIXUPIMMPD.Z imm8 ymm ymm k ymm +// VFIXUPIMMPD.Z imm8 m512 zmm k zmm +// VFIXUPIMMPD.Z imm8 zmm zmm k zmm +// Construct and append a VFIXUPIMMPD.Z instruction to the active function. +// Operates on the global context. +func VFIXUPIMMPD_Z(i, mxyz, xyz, k, xyz1 operand.Op) { ctx.VFIXUPIMMPD_Z(i, mxyz, xyz, k, xyz1) } + +// VFIXUPIMMPS: Fix Up Special Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFIXUPIMMPS imm8 m256 ymm k ymm +// VFIXUPIMMPS imm8 m256 ymm ymm +// VFIXUPIMMPS imm8 ymm ymm k ymm +// VFIXUPIMMPS imm8 ymm ymm ymm +// VFIXUPIMMPS imm8 m512 zmm k zmm +// VFIXUPIMMPS imm8 m512 zmm zmm +// VFIXUPIMMPS imm8 zmm zmm k zmm +// VFIXUPIMMPS imm8 zmm zmm zmm +// VFIXUPIMMPS imm8 m128 xmm k xmm +// VFIXUPIMMPS imm8 m128 xmm xmm +// VFIXUPIMMPS imm8 xmm xmm k xmm +// VFIXUPIMMPS imm8 xmm xmm xmm +// Construct and append a VFIXUPIMMPS instruction to the active function. +func (c *Context) VFIXUPIMMPS(ops ...operand.Op) { + c.addinstruction(x86.VFIXUPIMMPS(ops...)) +} + +// VFIXUPIMMPS: Fix Up Special Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFIXUPIMMPS imm8 m256 ymm k ymm +// VFIXUPIMMPS imm8 m256 ymm ymm +// VFIXUPIMMPS imm8 ymm ymm k ymm +// VFIXUPIMMPS imm8 ymm ymm ymm +// VFIXUPIMMPS imm8 m512 zmm k zmm +// VFIXUPIMMPS imm8 m512 zmm zmm +// VFIXUPIMMPS imm8 zmm zmm k zmm +// VFIXUPIMMPS imm8 zmm zmm zmm +// VFIXUPIMMPS imm8 m128 xmm k xmm +// VFIXUPIMMPS imm8 m128 xmm xmm +// VFIXUPIMMPS imm8 xmm xmm k xmm +// VFIXUPIMMPS imm8 xmm xmm xmm +// Construct and append a VFIXUPIMMPS instruction to the active function. +// Operates on the global context. +func VFIXUPIMMPS(ops ...operand.Op) { ctx.VFIXUPIMMPS(ops...) } + +// VFIXUPIMMPS_BCST: Fix Up Special Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFIXUPIMMPS.BCST imm8 m32 ymm k ymm +// VFIXUPIMMPS.BCST imm8 m32 ymm ymm +// VFIXUPIMMPS.BCST imm8 m32 zmm k zmm +// VFIXUPIMMPS.BCST imm8 m32 zmm zmm +// VFIXUPIMMPS.BCST imm8 m32 xmm k xmm +// VFIXUPIMMPS.BCST imm8 m32 xmm xmm +// Construct and append a VFIXUPIMMPS.BCST instruction to the active function. +func (c *Context) VFIXUPIMMPS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFIXUPIMMPS_BCST(ops...)) +} + +// VFIXUPIMMPS_BCST: Fix Up Special Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFIXUPIMMPS.BCST imm8 m32 ymm k ymm +// VFIXUPIMMPS.BCST imm8 m32 ymm ymm +// VFIXUPIMMPS.BCST imm8 m32 zmm k zmm +// VFIXUPIMMPS.BCST imm8 m32 zmm zmm +// VFIXUPIMMPS.BCST imm8 m32 xmm k xmm +// VFIXUPIMMPS.BCST imm8 m32 xmm xmm +// Construct and append a VFIXUPIMMPS.BCST instruction to the active function. +// Operates on the global context. +func VFIXUPIMMPS_BCST(ops ...operand.Op) { ctx.VFIXUPIMMPS_BCST(ops...) } + +// VFIXUPIMMPS_BCST_Z: Fix Up Special Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFIXUPIMMPS.BCST.Z imm8 m32 ymm k ymm +// VFIXUPIMMPS.BCST.Z imm8 m32 zmm k zmm +// VFIXUPIMMPS.BCST.Z imm8 m32 xmm k xmm +// Construct and append a VFIXUPIMMPS.BCST.Z instruction to the active function. +func (c *Context) VFIXUPIMMPS_BCST_Z(i, m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFIXUPIMMPS_BCST_Z(i, m, xyz, k, xyz1)) +} + +// VFIXUPIMMPS_BCST_Z: Fix Up Special Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFIXUPIMMPS.BCST.Z imm8 m32 ymm k ymm +// VFIXUPIMMPS.BCST.Z imm8 m32 zmm k zmm +// VFIXUPIMMPS.BCST.Z imm8 m32 xmm k xmm +// Construct and append a VFIXUPIMMPS.BCST.Z instruction to the active function. +// Operates on the global context. +func VFIXUPIMMPS_BCST_Z(i, m, xyz, k, xyz1 operand.Op) { ctx.VFIXUPIMMPS_BCST_Z(i, m, xyz, k, xyz1) } + +// VFIXUPIMMPS_SAE: Fix Up Special Packed Single-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VFIXUPIMMPS.SAE imm8 zmm zmm k zmm +// VFIXUPIMMPS.SAE imm8 zmm zmm zmm +// Construct and append a VFIXUPIMMPS.SAE instruction to the active function. +func (c *Context) VFIXUPIMMPS_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFIXUPIMMPS_SAE(ops...)) +} + +// VFIXUPIMMPS_SAE: Fix Up Special Packed Single-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VFIXUPIMMPS.SAE imm8 zmm zmm k zmm +// VFIXUPIMMPS.SAE imm8 zmm zmm zmm +// Construct and append a VFIXUPIMMPS.SAE instruction to the active function. +// Operates on the global context. +func VFIXUPIMMPS_SAE(ops ...operand.Op) { ctx.VFIXUPIMMPS_SAE(ops...) } + +// VFIXUPIMMPS_SAE_Z: Fix Up Special Packed Single-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VFIXUPIMMPS.SAE.Z imm8 zmm zmm k zmm +// Construct and append a VFIXUPIMMPS.SAE.Z instruction to the active function. +func (c *Context) VFIXUPIMMPS_SAE_Z(i, z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFIXUPIMMPS_SAE_Z(i, z, z1, k, z2)) +} + +// VFIXUPIMMPS_SAE_Z: Fix Up Special Packed Single-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VFIXUPIMMPS.SAE.Z imm8 zmm zmm k zmm +// Construct and append a VFIXUPIMMPS.SAE.Z instruction to the active function. +// Operates on the global context. +func VFIXUPIMMPS_SAE_Z(i, z, z1, k, z2 operand.Op) { ctx.VFIXUPIMMPS_SAE_Z(i, z, z1, k, z2) } + +// VFIXUPIMMPS_Z: Fix Up Special Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFIXUPIMMPS.Z imm8 m256 ymm k ymm +// VFIXUPIMMPS.Z imm8 ymm ymm k ymm +// VFIXUPIMMPS.Z imm8 m512 zmm k zmm +// VFIXUPIMMPS.Z imm8 zmm zmm k zmm +// VFIXUPIMMPS.Z imm8 m128 xmm k xmm +// VFIXUPIMMPS.Z imm8 xmm xmm k xmm +// Construct and append a VFIXUPIMMPS.Z instruction to the active function. +func (c *Context) VFIXUPIMMPS_Z(i, mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFIXUPIMMPS_Z(i, mxyz, xyz, k, xyz1)) +} + +// VFIXUPIMMPS_Z: Fix Up Special Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFIXUPIMMPS.Z imm8 m256 ymm k ymm +// VFIXUPIMMPS.Z imm8 ymm ymm k ymm +// VFIXUPIMMPS.Z imm8 m512 zmm k zmm +// VFIXUPIMMPS.Z imm8 zmm zmm k zmm +// VFIXUPIMMPS.Z imm8 m128 xmm k xmm +// VFIXUPIMMPS.Z imm8 xmm xmm k xmm +// Construct and append a VFIXUPIMMPS.Z instruction to the active function. +// Operates on the global context. +func VFIXUPIMMPS_Z(i, mxyz, xyz, k, xyz1 operand.Op) { ctx.VFIXUPIMMPS_Z(i, mxyz, xyz, k, xyz1) } + +// VFIXUPIMMSD: Fix Up Special Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// VFIXUPIMMSD imm8 m64 xmm k xmm +// VFIXUPIMMSD imm8 m64 xmm xmm +// VFIXUPIMMSD imm8 xmm xmm k xmm +// VFIXUPIMMSD imm8 xmm xmm xmm +// Construct and append a VFIXUPIMMSD instruction to the active function. +func (c *Context) VFIXUPIMMSD(ops ...operand.Op) { + c.addinstruction(x86.VFIXUPIMMSD(ops...)) +} + +// VFIXUPIMMSD: Fix Up Special Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// VFIXUPIMMSD imm8 m64 xmm k xmm +// VFIXUPIMMSD imm8 m64 xmm xmm +// VFIXUPIMMSD imm8 xmm xmm k xmm +// VFIXUPIMMSD imm8 xmm xmm xmm +// Construct and append a VFIXUPIMMSD instruction to the active function. +// Operates on the global context. +func VFIXUPIMMSD(ops ...operand.Op) { ctx.VFIXUPIMMSD(ops...) } + +// VFIXUPIMMSD_SAE: Fix Up Special Scalar Double-Precision Floating-Point Value (Suppress All Exceptions). +// +// Forms: +// +// VFIXUPIMMSD.SAE imm8 xmm xmm k xmm +// VFIXUPIMMSD.SAE imm8 xmm xmm xmm +// Construct and append a VFIXUPIMMSD.SAE instruction to the active function. +func (c *Context) VFIXUPIMMSD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFIXUPIMMSD_SAE(ops...)) +} + +// VFIXUPIMMSD_SAE: Fix Up Special Scalar Double-Precision Floating-Point Value (Suppress All Exceptions). +// +// Forms: +// +// VFIXUPIMMSD.SAE imm8 xmm xmm k xmm +// VFIXUPIMMSD.SAE imm8 xmm xmm xmm +// Construct and append a VFIXUPIMMSD.SAE instruction to the active function. +// Operates on the global context. +func VFIXUPIMMSD_SAE(ops ...operand.Op) { ctx.VFIXUPIMMSD_SAE(ops...) } + +// VFIXUPIMMSD_SAE_Z: Fix Up Special Scalar Double-Precision Floating-Point Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VFIXUPIMMSD.SAE.Z imm8 xmm xmm k xmm +// Construct and append a VFIXUPIMMSD.SAE.Z instruction to the active function. +func (c *Context) VFIXUPIMMSD_SAE_Z(i, x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFIXUPIMMSD_SAE_Z(i, x, x1, k, x2)) +} + +// VFIXUPIMMSD_SAE_Z: Fix Up Special Scalar Double-Precision Floating-Point Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VFIXUPIMMSD.SAE.Z imm8 xmm xmm k xmm +// Construct and append a VFIXUPIMMSD.SAE.Z instruction to the active function. +// Operates on the global context. +func VFIXUPIMMSD_SAE_Z(i, x, x1, k, x2 operand.Op) { ctx.VFIXUPIMMSD_SAE_Z(i, x, x1, k, x2) } + +// VFIXUPIMMSD_Z: Fix Up Special Scalar Double-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VFIXUPIMMSD.Z imm8 m64 xmm k xmm +// VFIXUPIMMSD.Z imm8 xmm xmm k xmm +// Construct and append a VFIXUPIMMSD.Z instruction to the active function. +func (c *Context) VFIXUPIMMSD_Z(i, mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VFIXUPIMMSD_Z(i, mx, x, k, x1)) +} + +// VFIXUPIMMSD_Z: Fix Up Special Scalar Double-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VFIXUPIMMSD.Z imm8 m64 xmm k xmm +// VFIXUPIMMSD.Z imm8 xmm xmm k xmm +// Construct and append a VFIXUPIMMSD.Z instruction to the active function. +// Operates on the global context. +func VFIXUPIMMSD_Z(i, mx, x, k, x1 operand.Op) { ctx.VFIXUPIMMSD_Z(i, mx, x, k, x1) } + +// VFIXUPIMMSS: Fix Up Special Scalar Single-Precision Floating-Point Value. +// +// Forms: +// +// VFIXUPIMMSS imm8 m32 xmm k xmm +// VFIXUPIMMSS imm8 m32 xmm xmm +// VFIXUPIMMSS imm8 xmm xmm k xmm +// VFIXUPIMMSS imm8 xmm xmm xmm +// Construct and append a VFIXUPIMMSS instruction to the active function. +func (c *Context) VFIXUPIMMSS(ops ...operand.Op) { + c.addinstruction(x86.VFIXUPIMMSS(ops...)) +} + +// VFIXUPIMMSS: Fix Up Special Scalar Single-Precision Floating-Point Value. +// +// Forms: +// +// VFIXUPIMMSS imm8 m32 xmm k xmm +// VFIXUPIMMSS imm8 m32 xmm xmm +// VFIXUPIMMSS imm8 xmm xmm k xmm +// VFIXUPIMMSS imm8 xmm xmm xmm +// Construct and append a VFIXUPIMMSS instruction to the active function. +// Operates on the global context. +func VFIXUPIMMSS(ops ...operand.Op) { ctx.VFIXUPIMMSS(ops...) } + +// VFIXUPIMMSS_SAE: Fix Up Special Scalar Single-Precision Floating-Point Value (Suppress All Exceptions). +// +// Forms: +// +// VFIXUPIMMSS.SAE imm8 xmm xmm k xmm +// VFIXUPIMMSS.SAE imm8 xmm xmm xmm +// Construct and append a VFIXUPIMMSS.SAE instruction to the active function. +func (c *Context) VFIXUPIMMSS_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFIXUPIMMSS_SAE(ops...)) +} + +// VFIXUPIMMSS_SAE: Fix Up Special Scalar Single-Precision Floating-Point Value (Suppress All Exceptions). +// +// Forms: +// +// VFIXUPIMMSS.SAE imm8 xmm xmm k xmm +// VFIXUPIMMSS.SAE imm8 xmm xmm xmm +// Construct and append a VFIXUPIMMSS.SAE instruction to the active function. +// Operates on the global context. +func VFIXUPIMMSS_SAE(ops ...operand.Op) { ctx.VFIXUPIMMSS_SAE(ops...) } + +// VFIXUPIMMSS_SAE_Z: Fix Up Special Scalar Single-Precision Floating-Point Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VFIXUPIMMSS.SAE.Z imm8 xmm xmm k xmm +// Construct and append a VFIXUPIMMSS.SAE.Z instruction to the active function. +func (c *Context) VFIXUPIMMSS_SAE_Z(i, x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFIXUPIMMSS_SAE_Z(i, x, x1, k, x2)) +} + +// VFIXUPIMMSS_SAE_Z: Fix Up Special Scalar Single-Precision Floating-Point Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VFIXUPIMMSS.SAE.Z imm8 xmm xmm k xmm +// Construct and append a VFIXUPIMMSS.SAE.Z instruction to the active function. +// Operates on the global context. +func VFIXUPIMMSS_SAE_Z(i, x, x1, k, x2 operand.Op) { ctx.VFIXUPIMMSS_SAE_Z(i, x, x1, k, x2) } + +// VFIXUPIMMSS_Z: Fix Up Special Scalar Single-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VFIXUPIMMSS.Z imm8 m32 xmm k xmm +// VFIXUPIMMSS.Z imm8 xmm xmm k xmm +// Construct and append a VFIXUPIMMSS.Z instruction to the active function. +func (c *Context) VFIXUPIMMSS_Z(i, mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VFIXUPIMMSS_Z(i, mx, x, k, x1)) +} + +// VFIXUPIMMSS_Z: Fix Up Special Scalar Single-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VFIXUPIMMSS.Z imm8 m32 xmm k xmm +// VFIXUPIMMSS.Z imm8 xmm xmm k xmm +// Construct and append a VFIXUPIMMSS.Z instruction to the active function. +// Operates on the global context. +func VFIXUPIMMSS_Z(i, mx, x, k, x1 operand.Op) { ctx.VFIXUPIMMSS_Z(i, mx, x, k, x1) } + +// VFMADD132PD: Fused Multiply-Add of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD132PD m128 xmm xmm +// VFMADD132PD m256 ymm ymm +// VFMADD132PD xmm xmm xmm +// VFMADD132PD ymm ymm ymm +// VFMADD132PD m128 xmm k xmm +// VFMADD132PD m256 ymm k ymm +// VFMADD132PD xmm xmm k xmm +// VFMADD132PD ymm ymm k ymm +// VFMADD132PD m512 zmm k zmm +// VFMADD132PD m512 zmm zmm +// VFMADD132PD zmm zmm k zmm +// VFMADD132PD zmm zmm zmm +// Construct and append a VFMADD132PD instruction to the active function. +func (c *Context) VFMADD132PD(ops ...operand.Op) { + c.addinstruction(x86.VFMADD132PD(ops...)) +} + +// VFMADD132PD: Fused Multiply-Add of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD132PD m128 xmm xmm +// VFMADD132PD m256 ymm ymm +// VFMADD132PD xmm xmm xmm +// VFMADD132PD ymm ymm ymm +// VFMADD132PD m128 xmm k xmm +// VFMADD132PD m256 ymm k ymm +// VFMADD132PD xmm xmm k xmm +// VFMADD132PD ymm ymm k ymm +// VFMADD132PD m512 zmm k zmm +// VFMADD132PD m512 zmm zmm +// VFMADD132PD zmm zmm k zmm +// VFMADD132PD zmm zmm zmm +// Construct and append a VFMADD132PD instruction to the active function. +// Operates on the global context. +func VFMADD132PD(ops ...operand.Op) { ctx.VFMADD132PD(ops...) } + +// VFMADD132PD_BCST: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADD132PD.BCST m64 xmm k xmm +// VFMADD132PD.BCST m64 xmm xmm +// VFMADD132PD.BCST m64 ymm k ymm +// VFMADD132PD.BCST m64 ymm ymm +// VFMADD132PD.BCST m64 zmm k zmm +// VFMADD132PD.BCST m64 zmm zmm +// Construct and append a VFMADD132PD.BCST instruction to the active function. +func (c *Context) VFMADD132PD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFMADD132PD_BCST(ops...)) +} + +// VFMADD132PD_BCST: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADD132PD.BCST m64 xmm k xmm +// VFMADD132PD.BCST m64 xmm xmm +// VFMADD132PD.BCST m64 ymm k ymm +// VFMADD132PD.BCST m64 ymm ymm +// VFMADD132PD.BCST m64 zmm k zmm +// VFMADD132PD.BCST m64 zmm zmm +// Construct and append a VFMADD132PD.BCST instruction to the active function. +// Operates on the global context. +func VFMADD132PD_BCST(ops ...operand.Op) { ctx.VFMADD132PD_BCST(ops...) } + +// VFMADD132PD_BCST_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADD132PD.BCST.Z m64 xmm k xmm +// VFMADD132PD.BCST.Z m64 ymm k ymm +// VFMADD132PD.BCST.Z m64 zmm k zmm +// Construct and append a VFMADD132PD.BCST.Z instruction to the active function. +func (c *Context) VFMADD132PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMADD132PD_BCST_Z(m, xyz, k, xyz1)) +} + +// VFMADD132PD_BCST_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADD132PD.BCST.Z m64 xmm k xmm +// VFMADD132PD.BCST.Z m64 ymm k ymm +// VFMADD132PD.BCST.Z m64 zmm k zmm +// Construct and append a VFMADD132PD.BCST.Z instruction to the active function. +// Operates on the global context. +func VFMADD132PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFMADD132PD_BCST_Z(m, xyz, k, xyz1) } + +// VFMADD132PD_RD_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD132PD.RD_SAE zmm zmm k zmm +// VFMADD132PD.RD_SAE zmm zmm zmm +// Construct and append a VFMADD132PD.RD_SAE instruction to the active function. +func (c *Context) VFMADD132PD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD132PD_RD_SAE(ops...)) +} + +// VFMADD132PD_RD_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD132PD.RD_SAE zmm zmm k zmm +// VFMADD132PD.RD_SAE zmm zmm zmm +// Construct and append a VFMADD132PD.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMADD132PD_RD_SAE(ops ...operand.Op) { ctx.VFMADD132PD_RD_SAE(ops...) } + +// VFMADD132PD_RD_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD132PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD132PD.RD_SAE.Z instruction to the active function. +func (c *Context) VFMADD132PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADD132PD_RD_SAE_Z(z, z1, k, z2)) +} + +// VFMADD132PD_RD_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD132PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD132PD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD132PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADD132PD_RD_SAE_Z(z, z1, k, z2) } + +// VFMADD132PD_RN_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD132PD.RN_SAE zmm zmm k zmm +// VFMADD132PD.RN_SAE zmm zmm zmm +// Construct and append a VFMADD132PD.RN_SAE instruction to the active function. +func (c *Context) VFMADD132PD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD132PD_RN_SAE(ops...)) +} + +// VFMADD132PD_RN_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD132PD.RN_SAE zmm zmm k zmm +// VFMADD132PD.RN_SAE zmm zmm zmm +// Construct and append a VFMADD132PD.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMADD132PD_RN_SAE(ops ...operand.Op) { ctx.VFMADD132PD_RN_SAE(ops...) } + +// VFMADD132PD_RN_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD132PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD132PD.RN_SAE.Z instruction to the active function. +func (c *Context) VFMADD132PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADD132PD_RN_SAE_Z(z, z1, k, z2)) +} + +// VFMADD132PD_RN_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD132PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD132PD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD132PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADD132PD_RN_SAE_Z(z, z1, k, z2) } + +// VFMADD132PD_RU_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD132PD.RU_SAE zmm zmm k zmm +// VFMADD132PD.RU_SAE zmm zmm zmm +// Construct and append a VFMADD132PD.RU_SAE instruction to the active function. +func (c *Context) VFMADD132PD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD132PD_RU_SAE(ops...)) +} + +// VFMADD132PD_RU_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD132PD.RU_SAE zmm zmm k zmm +// VFMADD132PD.RU_SAE zmm zmm zmm +// Construct and append a VFMADD132PD.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMADD132PD_RU_SAE(ops ...operand.Op) { ctx.VFMADD132PD_RU_SAE(ops...) } + +// VFMADD132PD_RU_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD132PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD132PD.RU_SAE.Z instruction to the active function. +func (c *Context) VFMADD132PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADD132PD_RU_SAE_Z(z, z1, k, z2)) +} + +// VFMADD132PD_RU_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD132PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD132PD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD132PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADD132PD_RU_SAE_Z(z, z1, k, z2) } + +// VFMADD132PD_RZ_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD132PD.RZ_SAE zmm zmm k zmm +// VFMADD132PD.RZ_SAE zmm zmm zmm +// Construct and append a VFMADD132PD.RZ_SAE instruction to the active function. +func (c *Context) VFMADD132PD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD132PD_RZ_SAE(ops...)) +} + +// VFMADD132PD_RZ_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD132PD.RZ_SAE zmm zmm k zmm +// VFMADD132PD.RZ_SAE zmm zmm zmm +// Construct and append a VFMADD132PD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMADD132PD_RZ_SAE(ops ...operand.Op) { ctx.VFMADD132PD_RZ_SAE(ops...) } + +// VFMADD132PD_RZ_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD132PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD132PD.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMADD132PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADD132PD_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFMADD132PD_RZ_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD132PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD132PD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD132PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADD132PD_RZ_SAE_Z(z, z1, k, z2) } + +// VFMADD132PD_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD132PD.Z m128 xmm k xmm +// VFMADD132PD.Z m256 ymm k ymm +// VFMADD132PD.Z xmm xmm k xmm +// VFMADD132PD.Z ymm ymm k ymm +// VFMADD132PD.Z m512 zmm k zmm +// VFMADD132PD.Z zmm zmm k zmm +// Construct and append a VFMADD132PD.Z instruction to the active function. +func (c *Context) VFMADD132PD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMADD132PD_Z(mxyz, xyz, k, xyz1)) +} + +// VFMADD132PD_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD132PD.Z m128 xmm k xmm +// VFMADD132PD.Z m256 ymm k ymm +// VFMADD132PD.Z xmm xmm k xmm +// VFMADD132PD.Z ymm ymm k ymm +// VFMADD132PD.Z m512 zmm k zmm +// VFMADD132PD.Z zmm zmm k zmm +// Construct and append a VFMADD132PD.Z instruction to the active function. +// Operates on the global context. +func VFMADD132PD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFMADD132PD_Z(mxyz, xyz, k, xyz1) } + +// VFMADD132PS: Fused Multiply-Add of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD132PS m128 xmm xmm +// VFMADD132PS m256 ymm ymm +// VFMADD132PS xmm xmm xmm +// VFMADD132PS ymm ymm ymm +// VFMADD132PS m128 xmm k xmm +// VFMADD132PS m256 ymm k ymm +// VFMADD132PS xmm xmm k xmm +// VFMADD132PS ymm ymm k ymm +// VFMADD132PS m512 zmm k zmm +// VFMADD132PS m512 zmm zmm +// VFMADD132PS zmm zmm k zmm +// VFMADD132PS zmm zmm zmm +// Construct and append a VFMADD132PS instruction to the active function. +func (c *Context) VFMADD132PS(ops ...operand.Op) { + c.addinstruction(x86.VFMADD132PS(ops...)) +} + +// VFMADD132PS: Fused Multiply-Add of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD132PS m128 xmm xmm +// VFMADD132PS m256 ymm ymm +// VFMADD132PS xmm xmm xmm +// VFMADD132PS ymm ymm ymm +// VFMADD132PS m128 xmm k xmm +// VFMADD132PS m256 ymm k ymm +// VFMADD132PS xmm xmm k xmm +// VFMADD132PS ymm ymm k ymm +// VFMADD132PS m512 zmm k zmm +// VFMADD132PS m512 zmm zmm +// VFMADD132PS zmm zmm k zmm +// VFMADD132PS zmm zmm zmm +// Construct and append a VFMADD132PS instruction to the active function. +// Operates on the global context. +func VFMADD132PS(ops ...operand.Op) { ctx.VFMADD132PS(ops...) } + +// VFMADD132PS_BCST: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADD132PS.BCST m32 xmm k xmm +// VFMADD132PS.BCST m32 xmm xmm +// VFMADD132PS.BCST m32 ymm k ymm +// VFMADD132PS.BCST m32 ymm ymm +// VFMADD132PS.BCST m32 zmm k zmm +// VFMADD132PS.BCST m32 zmm zmm +// Construct and append a VFMADD132PS.BCST instruction to the active function. +func (c *Context) VFMADD132PS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFMADD132PS_BCST(ops...)) +} + +// VFMADD132PS_BCST: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADD132PS.BCST m32 xmm k xmm +// VFMADD132PS.BCST m32 xmm xmm +// VFMADD132PS.BCST m32 ymm k ymm +// VFMADD132PS.BCST m32 ymm ymm +// VFMADD132PS.BCST m32 zmm k zmm +// VFMADD132PS.BCST m32 zmm zmm +// Construct and append a VFMADD132PS.BCST instruction to the active function. +// Operates on the global context. +func VFMADD132PS_BCST(ops ...operand.Op) { ctx.VFMADD132PS_BCST(ops...) } + +// VFMADD132PS_BCST_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADD132PS.BCST.Z m32 xmm k xmm +// VFMADD132PS.BCST.Z m32 ymm k ymm +// VFMADD132PS.BCST.Z m32 zmm k zmm +// Construct and append a VFMADD132PS.BCST.Z instruction to the active function. +func (c *Context) VFMADD132PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMADD132PS_BCST_Z(m, xyz, k, xyz1)) +} + +// VFMADD132PS_BCST_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADD132PS.BCST.Z m32 xmm k xmm +// VFMADD132PS.BCST.Z m32 ymm k ymm +// VFMADD132PS.BCST.Z m32 zmm k zmm +// Construct and append a VFMADD132PS.BCST.Z instruction to the active function. +// Operates on the global context. +func VFMADD132PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFMADD132PS_BCST_Z(m, xyz, k, xyz1) } + +// VFMADD132PS_RD_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD132PS.RD_SAE zmm zmm k zmm +// VFMADD132PS.RD_SAE zmm zmm zmm +// Construct and append a VFMADD132PS.RD_SAE instruction to the active function. +func (c *Context) VFMADD132PS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD132PS_RD_SAE(ops...)) +} + +// VFMADD132PS_RD_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD132PS.RD_SAE zmm zmm k zmm +// VFMADD132PS.RD_SAE zmm zmm zmm +// Construct and append a VFMADD132PS.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMADD132PS_RD_SAE(ops ...operand.Op) { ctx.VFMADD132PS_RD_SAE(ops...) } + +// VFMADD132PS_RD_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD132PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD132PS.RD_SAE.Z instruction to the active function. +func (c *Context) VFMADD132PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADD132PS_RD_SAE_Z(z, z1, k, z2)) +} + +// VFMADD132PS_RD_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD132PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD132PS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD132PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADD132PS_RD_SAE_Z(z, z1, k, z2) } + +// VFMADD132PS_RN_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD132PS.RN_SAE zmm zmm k zmm +// VFMADD132PS.RN_SAE zmm zmm zmm +// Construct and append a VFMADD132PS.RN_SAE instruction to the active function. +func (c *Context) VFMADD132PS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD132PS_RN_SAE(ops...)) +} + +// VFMADD132PS_RN_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD132PS.RN_SAE zmm zmm k zmm +// VFMADD132PS.RN_SAE zmm zmm zmm +// Construct and append a VFMADD132PS.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMADD132PS_RN_SAE(ops ...operand.Op) { ctx.VFMADD132PS_RN_SAE(ops...) } + +// VFMADD132PS_RN_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD132PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD132PS.RN_SAE.Z instruction to the active function. +func (c *Context) VFMADD132PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADD132PS_RN_SAE_Z(z, z1, k, z2)) +} + +// VFMADD132PS_RN_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD132PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD132PS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD132PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADD132PS_RN_SAE_Z(z, z1, k, z2) } + +// VFMADD132PS_RU_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD132PS.RU_SAE zmm zmm k zmm +// VFMADD132PS.RU_SAE zmm zmm zmm +// Construct and append a VFMADD132PS.RU_SAE instruction to the active function. +func (c *Context) VFMADD132PS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD132PS_RU_SAE(ops...)) +} + +// VFMADD132PS_RU_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD132PS.RU_SAE zmm zmm k zmm +// VFMADD132PS.RU_SAE zmm zmm zmm +// Construct and append a VFMADD132PS.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMADD132PS_RU_SAE(ops ...operand.Op) { ctx.VFMADD132PS_RU_SAE(ops...) } + +// VFMADD132PS_RU_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD132PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD132PS.RU_SAE.Z instruction to the active function. +func (c *Context) VFMADD132PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADD132PS_RU_SAE_Z(z, z1, k, z2)) +} + +// VFMADD132PS_RU_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD132PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD132PS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD132PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADD132PS_RU_SAE_Z(z, z1, k, z2) } + +// VFMADD132PS_RZ_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD132PS.RZ_SAE zmm zmm k zmm +// VFMADD132PS.RZ_SAE zmm zmm zmm +// Construct and append a VFMADD132PS.RZ_SAE instruction to the active function. +func (c *Context) VFMADD132PS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD132PS_RZ_SAE(ops...)) +} + +// VFMADD132PS_RZ_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD132PS.RZ_SAE zmm zmm k zmm +// VFMADD132PS.RZ_SAE zmm zmm zmm +// Construct and append a VFMADD132PS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMADD132PS_RZ_SAE(ops ...operand.Op) { ctx.VFMADD132PS_RZ_SAE(ops...) } + +// VFMADD132PS_RZ_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD132PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD132PS.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMADD132PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADD132PS_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFMADD132PS_RZ_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD132PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD132PS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD132PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADD132PS_RZ_SAE_Z(z, z1, k, z2) } + +// VFMADD132PS_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD132PS.Z m128 xmm k xmm +// VFMADD132PS.Z m256 ymm k ymm +// VFMADD132PS.Z xmm xmm k xmm +// VFMADD132PS.Z ymm ymm k ymm +// VFMADD132PS.Z m512 zmm k zmm +// VFMADD132PS.Z zmm zmm k zmm +// Construct and append a VFMADD132PS.Z instruction to the active function. +func (c *Context) VFMADD132PS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMADD132PS_Z(mxyz, xyz, k, xyz1)) +} + +// VFMADD132PS_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD132PS.Z m128 xmm k xmm +// VFMADD132PS.Z m256 ymm k ymm +// VFMADD132PS.Z xmm xmm k xmm +// VFMADD132PS.Z ymm ymm k ymm +// VFMADD132PS.Z m512 zmm k zmm +// VFMADD132PS.Z zmm zmm k zmm +// Construct and append a VFMADD132PS.Z instruction to the active function. +// Operates on the global context. +func VFMADD132PS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFMADD132PS_Z(mxyz, xyz, k, xyz1) } + +// VFMADD132SD: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD132SD m64 xmm xmm +// VFMADD132SD xmm xmm xmm +// VFMADD132SD m64 xmm k xmm +// VFMADD132SD xmm xmm k xmm +// Construct and append a VFMADD132SD instruction to the active function. +func (c *Context) VFMADD132SD(ops ...operand.Op) { + c.addinstruction(x86.VFMADD132SD(ops...)) +} + +// VFMADD132SD: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD132SD m64 xmm xmm +// VFMADD132SD xmm xmm xmm +// VFMADD132SD m64 xmm k xmm +// VFMADD132SD xmm xmm k xmm +// Construct and append a VFMADD132SD instruction to the active function. +// Operates on the global context. +func VFMADD132SD(ops ...operand.Op) { ctx.VFMADD132SD(ops...) } + +// VFMADD132SD_RD_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD132SD.RD_SAE xmm xmm k xmm +// VFMADD132SD.RD_SAE xmm xmm xmm +// Construct and append a VFMADD132SD.RD_SAE instruction to the active function. +func (c *Context) VFMADD132SD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD132SD_RD_SAE(ops...)) +} + +// VFMADD132SD_RD_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD132SD.RD_SAE xmm xmm k xmm +// VFMADD132SD.RD_SAE xmm xmm xmm +// Construct and append a VFMADD132SD.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMADD132SD_RD_SAE(ops ...operand.Op) { ctx.VFMADD132SD_RD_SAE(ops...) } + +// VFMADD132SD_RD_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD132SD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD132SD.RD_SAE.Z instruction to the active function. +func (c *Context) VFMADD132SD_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMADD132SD_RD_SAE_Z(x, x1, k, x2)) +} + +// VFMADD132SD_RD_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD132SD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD132SD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD132SD_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMADD132SD_RD_SAE_Z(x, x1, k, x2) } + +// VFMADD132SD_RN_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD132SD.RN_SAE xmm xmm k xmm +// VFMADD132SD.RN_SAE xmm xmm xmm +// Construct and append a VFMADD132SD.RN_SAE instruction to the active function. +func (c *Context) VFMADD132SD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD132SD_RN_SAE(ops...)) +} + +// VFMADD132SD_RN_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD132SD.RN_SAE xmm xmm k xmm +// VFMADD132SD.RN_SAE xmm xmm xmm +// Construct and append a VFMADD132SD.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMADD132SD_RN_SAE(ops ...operand.Op) { ctx.VFMADD132SD_RN_SAE(ops...) } + +// VFMADD132SD_RN_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD132SD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD132SD.RN_SAE.Z instruction to the active function. +func (c *Context) VFMADD132SD_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMADD132SD_RN_SAE_Z(x, x1, k, x2)) +} + +// VFMADD132SD_RN_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD132SD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD132SD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD132SD_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMADD132SD_RN_SAE_Z(x, x1, k, x2) } + +// VFMADD132SD_RU_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD132SD.RU_SAE xmm xmm k xmm +// VFMADD132SD.RU_SAE xmm xmm xmm +// Construct and append a VFMADD132SD.RU_SAE instruction to the active function. +func (c *Context) VFMADD132SD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD132SD_RU_SAE(ops...)) +} + +// VFMADD132SD_RU_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD132SD.RU_SAE xmm xmm k xmm +// VFMADD132SD.RU_SAE xmm xmm xmm +// Construct and append a VFMADD132SD.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMADD132SD_RU_SAE(ops ...operand.Op) { ctx.VFMADD132SD_RU_SAE(ops...) } + +// VFMADD132SD_RU_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD132SD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD132SD.RU_SAE.Z instruction to the active function. +func (c *Context) VFMADD132SD_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMADD132SD_RU_SAE_Z(x, x1, k, x2)) +} + +// VFMADD132SD_RU_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD132SD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD132SD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD132SD_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMADD132SD_RU_SAE_Z(x, x1, k, x2) } + +// VFMADD132SD_RZ_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD132SD.RZ_SAE xmm xmm k xmm +// VFMADD132SD.RZ_SAE xmm xmm xmm +// Construct and append a VFMADD132SD.RZ_SAE instruction to the active function. +func (c *Context) VFMADD132SD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD132SD_RZ_SAE(ops...)) +} + +// VFMADD132SD_RZ_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD132SD.RZ_SAE xmm xmm k xmm +// VFMADD132SD.RZ_SAE xmm xmm xmm +// Construct and append a VFMADD132SD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMADD132SD_RZ_SAE(ops ...operand.Op) { ctx.VFMADD132SD_RZ_SAE(ops...) } + +// VFMADD132SD_RZ_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD132SD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD132SD.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMADD132SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMADD132SD_RZ_SAE_Z(x, x1, k, x2)) +} + +// VFMADD132SD_RZ_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD132SD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD132SD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD132SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMADD132SD_RZ_SAE_Z(x, x1, k, x2) } + +// VFMADD132SD_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD132SD.Z m64 xmm k xmm +// VFMADD132SD.Z xmm xmm k xmm +// Construct and append a VFMADD132SD.Z instruction to the active function. +func (c *Context) VFMADD132SD_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VFMADD132SD_Z(mx, x, k, x1)) +} + +// VFMADD132SD_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD132SD.Z m64 xmm k xmm +// VFMADD132SD.Z xmm xmm k xmm +// Construct and append a VFMADD132SD.Z instruction to the active function. +// Operates on the global context. +func VFMADD132SD_Z(mx, x, k, x1 operand.Op) { ctx.VFMADD132SD_Z(mx, x, k, x1) } + +// VFMADD132SS: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD132SS m32 xmm xmm +// VFMADD132SS xmm xmm xmm +// VFMADD132SS m32 xmm k xmm +// VFMADD132SS xmm xmm k xmm +// Construct and append a VFMADD132SS instruction to the active function. +func (c *Context) VFMADD132SS(ops ...operand.Op) { + c.addinstruction(x86.VFMADD132SS(ops...)) +} + +// VFMADD132SS: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD132SS m32 xmm xmm +// VFMADD132SS xmm xmm xmm +// VFMADD132SS m32 xmm k xmm +// VFMADD132SS xmm xmm k xmm +// Construct and append a VFMADD132SS instruction to the active function. +// Operates on the global context. +func VFMADD132SS(ops ...operand.Op) { ctx.VFMADD132SS(ops...) } + +// VFMADD132SS_RD_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD132SS.RD_SAE xmm xmm k xmm +// VFMADD132SS.RD_SAE xmm xmm xmm +// Construct and append a VFMADD132SS.RD_SAE instruction to the active function. +func (c *Context) VFMADD132SS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD132SS_RD_SAE(ops...)) +} + +// VFMADD132SS_RD_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD132SS.RD_SAE xmm xmm k xmm +// VFMADD132SS.RD_SAE xmm xmm xmm +// Construct and append a VFMADD132SS.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMADD132SS_RD_SAE(ops ...operand.Op) { ctx.VFMADD132SS_RD_SAE(ops...) } + +// VFMADD132SS_RD_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD132SS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD132SS.RD_SAE.Z instruction to the active function. +func (c *Context) VFMADD132SS_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMADD132SS_RD_SAE_Z(x, x1, k, x2)) +} + +// VFMADD132SS_RD_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD132SS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD132SS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD132SS_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMADD132SS_RD_SAE_Z(x, x1, k, x2) } + +// VFMADD132SS_RN_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD132SS.RN_SAE xmm xmm k xmm +// VFMADD132SS.RN_SAE xmm xmm xmm +// Construct and append a VFMADD132SS.RN_SAE instruction to the active function. +func (c *Context) VFMADD132SS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD132SS_RN_SAE(ops...)) +} + +// VFMADD132SS_RN_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD132SS.RN_SAE xmm xmm k xmm +// VFMADD132SS.RN_SAE xmm xmm xmm +// Construct and append a VFMADD132SS.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMADD132SS_RN_SAE(ops ...operand.Op) { ctx.VFMADD132SS_RN_SAE(ops...) } + +// VFMADD132SS_RN_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD132SS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD132SS.RN_SAE.Z instruction to the active function. +func (c *Context) VFMADD132SS_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMADD132SS_RN_SAE_Z(x, x1, k, x2)) +} + +// VFMADD132SS_RN_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD132SS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD132SS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD132SS_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMADD132SS_RN_SAE_Z(x, x1, k, x2) } + +// VFMADD132SS_RU_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD132SS.RU_SAE xmm xmm k xmm +// VFMADD132SS.RU_SAE xmm xmm xmm +// Construct and append a VFMADD132SS.RU_SAE instruction to the active function. +func (c *Context) VFMADD132SS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD132SS_RU_SAE(ops...)) +} + +// VFMADD132SS_RU_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD132SS.RU_SAE xmm xmm k xmm +// VFMADD132SS.RU_SAE xmm xmm xmm +// Construct and append a VFMADD132SS.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMADD132SS_RU_SAE(ops ...operand.Op) { ctx.VFMADD132SS_RU_SAE(ops...) } + +// VFMADD132SS_RU_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD132SS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD132SS.RU_SAE.Z instruction to the active function. +func (c *Context) VFMADD132SS_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMADD132SS_RU_SAE_Z(x, x1, k, x2)) +} + +// VFMADD132SS_RU_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD132SS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD132SS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD132SS_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMADD132SS_RU_SAE_Z(x, x1, k, x2) } + +// VFMADD132SS_RZ_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD132SS.RZ_SAE xmm xmm k xmm +// VFMADD132SS.RZ_SAE xmm xmm xmm +// Construct and append a VFMADD132SS.RZ_SAE instruction to the active function. +func (c *Context) VFMADD132SS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD132SS_RZ_SAE(ops...)) +} + +// VFMADD132SS_RZ_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD132SS.RZ_SAE xmm xmm k xmm +// VFMADD132SS.RZ_SAE xmm xmm xmm +// Construct and append a VFMADD132SS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMADD132SS_RZ_SAE(ops ...operand.Op) { ctx.VFMADD132SS_RZ_SAE(ops...) } + +// VFMADD132SS_RZ_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD132SS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD132SS.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMADD132SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMADD132SS_RZ_SAE_Z(x, x1, k, x2)) +} + +// VFMADD132SS_RZ_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD132SS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD132SS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD132SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMADD132SS_RZ_SAE_Z(x, x1, k, x2) } + +// VFMADD132SS_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD132SS.Z m32 xmm k xmm +// VFMADD132SS.Z xmm xmm k xmm +// Construct and append a VFMADD132SS.Z instruction to the active function. +func (c *Context) VFMADD132SS_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VFMADD132SS_Z(mx, x, k, x1)) +} + +// VFMADD132SS_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD132SS.Z m32 xmm k xmm +// VFMADD132SS.Z xmm xmm k xmm +// Construct and append a VFMADD132SS.Z instruction to the active function. +// Operates on the global context. +func VFMADD132SS_Z(mx, x, k, x1 operand.Op) { ctx.VFMADD132SS_Z(mx, x, k, x1) } + +// VFMADD213PD: Fused Multiply-Add of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD213PD m128 xmm xmm +// VFMADD213PD m256 ymm ymm +// VFMADD213PD xmm xmm xmm +// VFMADD213PD ymm ymm ymm +// VFMADD213PD m128 xmm k xmm +// VFMADD213PD m256 ymm k ymm +// VFMADD213PD xmm xmm k xmm +// VFMADD213PD ymm ymm k ymm +// VFMADD213PD m512 zmm k zmm +// VFMADD213PD m512 zmm zmm +// VFMADD213PD zmm zmm k zmm +// VFMADD213PD zmm zmm zmm +// Construct and append a VFMADD213PD instruction to the active function. +func (c *Context) VFMADD213PD(ops ...operand.Op) { + c.addinstruction(x86.VFMADD213PD(ops...)) +} + +// VFMADD213PD: Fused Multiply-Add of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD213PD m128 xmm xmm +// VFMADD213PD m256 ymm ymm +// VFMADD213PD xmm xmm xmm +// VFMADD213PD ymm ymm ymm +// VFMADD213PD m128 xmm k xmm +// VFMADD213PD m256 ymm k ymm +// VFMADD213PD xmm xmm k xmm +// VFMADD213PD ymm ymm k ymm +// VFMADD213PD m512 zmm k zmm +// VFMADD213PD m512 zmm zmm +// VFMADD213PD zmm zmm k zmm +// VFMADD213PD zmm zmm zmm +// Construct and append a VFMADD213PD instruction to the active function. +// Operates on the global context. +func VFMADD213PD(ops ...operand.Op) { ctx.VFMADD213PD(ops...) } + +// VFMADD213PD_BCST: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADD213PD.BCST m64 xmm k xmm +// VFMADD213PD.BCST m64 xmm xmm +// VFMADD213PD.BCST m64 ymm k ymm +// VFMADD213PD.BCST m64 ymm ymm +// VFMADD213PD.BCST m64 zmm k zmm +// VFMADD213PD.BCST m64 zmm zmm +// Construct and append a VFMADD213PD.BCST instruction to the active function. +func (c *Context) VFMADD213PD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFMADD213PD_BCST(ops...)) +} + +// VFMADD213PD_BCST: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADD213PD.BCST m64 xmm k xmm +// VFMADD213PD.BCST m64 xmm xmm +// VFMADD213PD.BCST m64 ymm k ymm +// VFMADD213PD.BCST m64 ymm ymm +// VFMADD213PD.BCST m64 zmm k zmm +// VFMADD213PD.BCST m64 zmm zmm +// Construct and append a VFMADD213PD.BCST instruction to the active function. +// Operates on the global context. +func VFMADD213PD_BCST(ops ...operand.Op) { ctx.VFMADD213PD_BCST(ops...) } + +// VFMADD213PD_BCST_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADD213PD.BCST.Z m64 xmm k xmm +// VFMADD213PD.BCST.Z m64 ymm k ymm +// VFMADD213PD.BCST.Z m64 zmm k zmm +// Construct and append a VFMADD213PD.BCST.Z instruction to the active function. +func (c *Context) VFMADD213PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMADD213PD_BCST_Z(m, xyz, k, xyz1)) +} + +// VFMADD213PD_BCST_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADD213PD.BCST.Z m64 xmm k xmm +// VFMADD213PD.BCST.Z m64 ymm k ymm +// VFMADD213PD.BCST.Z m64 zmm k zmm +// Construct and append a VFMADD213PD.BCST.Z instruction to the active function. +// Operates on the global context. +func VFMADD213PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFMADD213PD_BCST_Z(m, xyz, k, xyz1) } + +// VFMADD213PD_RD_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD213PD.RD_SAE zmm zmm k zmm +// VFMADD213PD.RD_SAE zmm zmm zmm +// Construct and append a VFMADD213PD.RD_SAE instruction to the active function. +func (c *Context) VFMADD213PD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD213PD_RD_SAE(ops...)) +} + +// VFMADD213PD_RD_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD213PD.RD_SAE zmm zmm k zmm +// VFMADD213PD.RD_SAE zmm zmm zmm +// Construct and append a VFMADD213PD.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMADD213PD_RD_SAE(ops ...operand.Op) { ctx.VFMADD213PD_RD_SAE(ops...) } + +// VFMADD213PD_RD_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD213PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD213PD.RD_SAE.Z instruction to the active function. +func (c *Context) VFMADD213PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADD213PD_RD_SAE_Z(z, z1, k, z2)) +} + +// VFMADD213PD_RD_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD213PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD213PD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD213PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADD213PD_RD_SAE_Z(z, z1, k, z2) } + +// VFMADD213PD_RN_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD213PD.RN_SAE zmm zmm k zmm +// VFMADD213PD.RN_SAE zmm zmm zmm +// Construct and append a VFMADD213PD.RN_SAE instruction to the active function. +func (c *Context) VFMADD213PD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD213PD_RN_SAE(ops...)) +} + +// VFMADD213PD_RN_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD213PD.RN_SAE zmm zmm k zmm +// VFMADD213PD.RN_SAE zmm zmm zmm +// Construct and append a VFMADD213PD.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMADD213PD_RN_SAE(ops ...operand.Op) { ctx.VFMADD213PD_RN_SAE(ops...) } + +// VFMADD213PD_RN_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD213PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD213PD.RN_SAE.Z instruction to the active function. +func (c *Context) VFMADD213PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADD213PD_RN_SAE_Z(z, z1, k, z2)) +} + +// VFMADD213PD_RN_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD213PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD213PD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD213PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADD213PD_RN_SAE_Z(z, z1, k, z2) } + +// VFMADD213PD_RU_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD213PD.RU_SAE zmm zmm k zmm +// VFMADD213PD.RU_SAE zmm zmm zmm +// Construct and append a VFMADD213PD.RU_SAE instruction to the active function. +func (c *Context) VFMADD213PD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD213PD_RU_SAE(ops...)) +} + +// VFMADD213PD_RU_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD213PD.RU_SAE zmm zmm k zmm +// VFMADD213PD.RU_SAE zmm zmm zmm +// Construct and append a VFMADD213PD.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMADD213PD_RU_SAE(ops ...operand.Op) { ctx.VFMADD213PD_RU_SAE(ops...) } + +// VFMADD213PD_RU_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD213PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD213PD.RU_SAE.Z instruction to the active function. +func (c *Context) VFMADD213PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADD213PD_RU_SAE_Z(z, z1, k, z2)) +} + +// VFMADD213PD_RU_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD213PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD213PD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD213PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADD213PD_RU_SAE_Z(z, z1, k, z2) } + +// VFMADD213PD_RZ_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD213PD.RZ_SAE zmm zmm k zmm +// VFMADD213PD.RZ_SAE zmm zmm zmm +// Construct and append a VFMADD213PD.RZ_SAE instruction to the active function. +func (c *Context) VFMADD213PD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD213PD_RZ_SAE(ops...)) +} + +// VFMADD213PD_RZ_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD213PD.RZ_SAE zmm zmm k zmm +// VFMADD213PD.RZ_SAE zmm zmm zmm +// Construct and append a VFMADD213PD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMADD213PD_RZ_SAE(ops ...operand.Op) { ctx.VFMADD213PD_RZ_SAE(ops...) } + +// VFMADD213PD_RZ_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD213PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD213PD.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMADD213PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADD213PD_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFMADD213PD_RZ_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD213PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD213PD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD213PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADD213PD_RZ_SAE_Z(z, z1, k, z2) } + +// VFMADD213PD_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD213PD.Z m128 xmm k xmm +// VFMADD213PD.Z m256 ymm k ymm +// VFMADD213PD.Z xmm xmm k xmm +// VFMADD213PD.Z ymm ymm k ymm +// VFMADD213PD.Z m512 zmm k zmm +// VFMADD213PD.Z zmm zmm k zmm +// Construct and append a VFMADD213PD.Z instruction to the active function. +func (c *Context) VFMADD213PD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMADD213PD_Z(mxyz, xyz, k, xyz1)) +} + +// VFMADD213PD_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD213PD.Z m128 xmm k xmm +// VFMADD213PD.Z m256 ymm k ymm +// VFMADD213PD.Z xmm xmm k xmm +// VFMADD213PD.Z ymm ymm k ymm +// VFMADD213PD.Z m512 zmm k zmm +// VFMADD213PD.Z zmm zmm k zmm +// Construct and append a VFMADD213PD.Z instruction to the active function. +// Operates on the global context. +func VFMADD213PD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFMADD213PD_Z(mxyz, xyz, k, xyz1) } + +// VFMADD213PS: Fused Multiply-Add of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD213PS m128 xmm xmm +// VFMADD213PS m256 ymm ymm +// VFMADD213PS xmm xmm xmm +// VFMADD213PS ymm ymm ymm +// VFMADD213PS m128 xmm k xmm +// VFMADD213PS m256 ymm k ymm +// VFMADD213PS xmm xmm k xmm +// VFMADD213PS ymm ymm k ymm +// VFMADD213PS m512 zmm k zmm +// VFMADD213PS m512 zmm zmm +// VFMADD213PS zmm zmm k zmm +// VFMADD213PS zmm zmm zmm +// Construct and append a VFMADD213PS instruction to the active function. +func (c *Context) VFMADD213PS(ops ...operand.Op) { + c.addinstruction(x86.VFMADD213PS(ops...)) +} + +// VFMADD213PS: Fused Multiply-Add of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD213PS m128 xmm xmm +// VFMADD213PS m256 ymm ymm +// VFMADD213PS xmm xmm xmm +// VFMADD213PS ymm ymm ymm +// VFMADD213PS m128 xmm k xmm +// VFMADD213PS m256 ymm k ymm +// VFMADD213PS xmm xmm k xmm +// VFMADD213PS ymm ymm k ymm +// VFMADD213PS m512 zmm k zmm +// VFMADD213PS m512 zmm zmm +// VFMADD213PS zmm zmm k zmm +// VFMADD213PS zmm zmm zmm +// Construct and append a VFMADD213PS instruction to the active function. +// Operates on the global context. +func VFMADD213PS(ops ...operand.Op) { ctx.VFMADD213PS(ops...) } + +// VFMADD213PS_BCST: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADD213PS.BCST m32 xmm k xmm +// VFMADD213PS.BCST m32 xmm xmm +// VFMADD213PS.BCST m32 ymm k ymm +// VFMADD213PS.BCST m32 ymm ymm +// VFMADD213PS.BCST m32 zmm k zmm +// VFMADD213PS.BCST m32 zmm zmm +// Construct and append a VFMADD213PS.BCST instruction to the active function. +func (c *Context) VFMADD213PS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFMADD213PS_BCST(ops...)) +} + +// VFMADD213PS_BCST: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADD213PS.BCST m32 xmm k xmm +// VFMADD213PS.BCST m32 xmm xmm +// VFMADD213PS.BCST m32 ymm k ymm +// VFMADD213PS.BCST m32 ymm ymm +// VFMADD213PS.BCST m32 zmm k zmm +// VFMADD213PS.BCST m32 zmm zmm +// Construct and append a VFMADD213PS.BCST instruction to the active function. +// Operates on the global context. +func VFMADD213PS_BCST(ops ...operand.Op) { ctx.VFMADD213PS_BCST(ops...) } + +// VFMADD213PS_BCST_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADD213PS.BCST.Z m32 xmm k xmm +// VFMADD213PS.BCST.Z m32 ymm k ymm +// VFMADD213PS.BCST.Z m32 zmm k zmm +// Construct and append a VFMADD213PS.BCST.Z instruction to the active function. +func (c *Context) VFMADD213PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMADD213PS_BCST_Z(m, xyz, k, xyz1)) +} + +// VFMADD213PS_BCST_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADD213PS.BCST.Z m32 xmm k xmm +// VFMADD213PS.BCST.Z m32 ymm k ymm +// VFMADD213PS.BCST.Z m32 zmm k zmm +// Construct and append a VFMADD213PS.BCST.Z instruction to the active function. +// Operates on the global context. +func VFMADD213PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFMADD213PS_BCST_Z(m, xyz, k, xyz1) } + +// VFMADD213PS_RD_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD213PS.RD_SAE zmm zmm k zmm +// VFMADD213PS.RD_SAE zmm zmm zmm +// Construct and append a VFMADD213PS.RD_SAE instruction to the active function. +func (c *Context) VFMADD213PS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD213PS_RD_SAE(ops...)) +} + +// VFMADD213PS_RD_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD213PS.RD_SAE zmm zmm k zmm +// VFMADD213PS.RD_SAE zmm zmm zmm +// Construct and append a VFMADD213PS.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMADD213PS_RD_SAE(ops ...operand.Op) { ctx.VFMADD213PS_RD_SAE(ops...) } + +// VFMADD213PS_RD_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD213PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD213PS.RD_SAE.Z instruction to the active function. +func (c *Context) VFMADD213PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADD213PS_RD_SAE_Z(z, z1, k, z2)) +} + +// VFMADD213PS_RD_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD213PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD213PS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD213PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADD213PS_RD_SAE_Z(z, z1, k, z2) } + +// VFMADD213PS_RN_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD213PS.RN_SAE zmm zmm k zmm +// VFMADD213PS.RN_SAE zmm zmm zmm +// Construct and append a VFMADD213PS.RN_SAE instruction to the active function. +func (c *Context) VFMADD213PS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD213PS_RN_SAE(ops...)) +} + +// VFMADD213PS_RN_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD213PS.RN_SAE zmm zmm k zmm +// VFMADD213PS.RN_SAE zmm zmm zmm +// Construct and append a VFMADD213PS.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMADD213PS_RN_SAE(ops ...operand.Op) { ctx.VFMADD213PS_RN_SAE(ops...) } + +// VFMADD213PS_RN_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD213PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD213PS.RN_SAE.Z instruction to the active function. +func (c *Context) VFMADD213PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADD213PS_RN_SAE_Z(z, z1, k, z2)) +} + +// VFMADD213PS_RN_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD213PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD213PS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD213PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADD213PS_RN_SAE_Z(z, z1, k, z2) } + +// VFMADD213PS_RU_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD213PS.RU_SAE zmm zmm k zmm +// VFMADD213PS.RU_SAE zmm zmm zmm +// Construct and append a VFMADD213PS.RU_SAE instruction to the active function. +func (c *Context) VFMADD213PS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD213PS_RU_SAE(ops...)) +} + +// VFMADD213PS_RU_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD213PS.RU_SAE zmm zmm k zmm +// VFMADD213PS.RU_SAE zmm zmm zmm +// Construct and append a VFMADD213PS.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMADD213PS_RU_SAE(ops ...operand.Op) { ctx.VFMADD213PS_RU_SAE(ops...) } + +// VFMADD213PS_RU_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD213PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD213PS.RU_SAE.Z instruction to the active function. +func (c *Context) VFMADD213PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADD213PS_RU_SAE_Z(z, z1, k, z2)) +} + +// VFMADD213PS_RU_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD213PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD213PS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD213PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADD213PS_RU_SAE_Z(z, z1, k, z2) } + +// VFMADD213PS_RZ_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD213PS.RZ_SAE zmm zmm k zmm +// VFMADD213PS.RZ_SAE zmm zmm zmm +// Construct and append a VFMADD213PS.RZ_SAE instruction to the active function. +func (c *Context) VFMADD213PS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD213PS_RZ_SAE(ops...)) +} + +// VFMADD213PS_RZ_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD213PS.RZ_SAE zmm zmm k zmm +// VFMADD213PS.RZ_SAE zmm zmm zmm +// Construct and append a VFMADD213PS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMADD213PS_RZ_SAE(ops ...operand.Op) { ctx.VFMADD213PS_RZ_SAE(ops...) } + +// VFMADD213PS_RZ_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD213PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD213PS.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMADD213PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADD213PS_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFMADD213PS_RZ_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD213PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD213PS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD213PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADD213PS_RZ_SAE_Z(z, z1, k, z2) } + +// VFMADD213PS_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD213PS.Z m128 xmm k xmm +// VFMADD213PS.Z m256 ymm k ymm +// VFMADD213PS.Z xmm xmm k xmm +// VFMADD213PS.Z ymm ymm k ymm +// VFMADD213PS.Z m512 zmm k zmm +// VFMADD213PS.Z zmm zmm k zmm +// Construct and append a VFMADD213PS.Z instruction to the active function. +func (c *Context) VFMADD213PS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMADD213PS_Z(mxyz, xyz, k, xyz1)) +} + +// VFMADD213PS_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD213PS.Z m128 xmm k xmm +// VFMADD213PS.Z m256 ymm k ymm +// VFMADD213PS.Z xmm xmm k xmm +// VFMADD213PS.Z ymm ymm k ymm +// VFMADD213PS.Z m512 zmm k zmm +// VFMADD213PS.Z zmm zmm k zmm +// Construct and append a VFMADD213PS.Z instruction to the active function. +// Operates on the global context. +func VFMADD213PS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFMADD213PS_Z(mxyz, xyz, k, xyz1) } + +// VFMADD213SD: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD213SD m64 xmm xmm +// VFMADD213SD xmm xmm xmm +// VFMADD213SD m64 xmm k xmm +// VFMADD213SD xmm xmm k xmm +// Construct and append a VFMADD213SD instruction to the active function. +func (c *Context) VFMADD213SD(ops ...operand.Op) { + c.addinstruction(x86.VFMADD213SD(ops...)) +} + +// VFMADD213SD: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD213SD m64 xmm xmm +// VFMADD213SD xmm xmm xmm +// VFMADD213SD m64 xmm k xmm +// VFMADD213SD xmm xmm k xmm +// Construct and append a VFMADD213SD instruction to the active function. +// Operates on the global context. +func VFMADD213SD(ops ...operand.Op) { ctx.VFMADD213SD(ops...) } + +// VFMADD213SD_RD_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD213SD.RD_SAE xmm xmm k xmm +// VFMADD213SD.RD_SAE xmm xmm xmm +// Construct and append a VFMADD213SD.RD_SAE instruction to the active function. +func (c *Context) VFMADD213SD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD213SD_RD_SAE(ops...)) +} + +// VFMADD213SD_RD_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD213SD.RD_SAE xmm xmm k xmm +// VFMADD213SD.RD_SAE xmm xmm xmm +// Construct and append a VFMADD213SD.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMADD213SD_RD_SAE(ops ...operand.Op) { ctx.VFMADD213SD_RD_SAE(ops...) } + +// VFMADD213SD_RD_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD213SD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD213SD.RD_SAE.Z instruction to the active function. +func (c *Context) VFMADD213SD_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMADD213SD_RD_SAE_Z(x, x1, k, x2)) +} + +// VFMADD213SD_RD_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD213SD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD213SD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD213SD_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMADD213SD_RD_SAE_Z(x, x1, k, x2) } + +// VFMADD213SD_RN_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD213SD.RN_SAE xmm xmm k xmm +// VFMADD213SD.RN_SAE xmm xmm xmm +// Construct and append a VFMADD213SD.RN_SAE instruction to the active function. +func (c *Context) VFMADD213SD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD213SD_RN_SAE(ops...)) +} + +// VFMADD213SD_RN_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD213SD.RN_SAE xmm xmm k xmm +// VFMADD213SD.RN_SAE xmm xmm xmm +// Construct and append a VFMADD213SD.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMADD213SD_RN_SAE(ops ...operand.Op) { ctx.VFMADD213SD_RN_SAE(ops...) } + +// VFMADD213SD_RN_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD213SD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD213SD.RN_SAE.Z instruction to the active function. +func (c *Context) VFMADD213SD_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMADD213SD_RN_SAE_Z(x, x1, k, x2)) +} + +// VFMADD213SD_RN_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD213SD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD213SD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD213SD_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMADD213SD_RN_SAE_Z(x, x1, k, x2) } + +// VFMADD213SD_RU_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD213SD.RU_SAE xmm xmm k xmm +// VFMADD213SD.RU_SAE xmm xmm xmm +// Construct and append a VFMADD213SD.RU_SAE instruction to the active function. +func (c *Context) VFMADD213SD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD213SD_RU_SAE(ops...)) +} + +// VFMADD213SD_RU_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD213SD.RU_SAE xmm xmm k xmm +// VFMADD213SD.RU_SAE xmm xmm xmm +// Construct and append a VFMADD213SD.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMADD213SD_RU_SAE(ops ...operand.Op) { ctx.VFMADD213SD_RU_SAE(ops...) } + +// VFMADD213SD_RU_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD213SD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD213SD.RU_SAE.Z instruction to the active function. +func (c *Context) VFMADD213SD_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMADD213SD_RU_SAE_Z(x, x1, k, x2)) +} + +// VFMADD213SD_RU_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD213SD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD213SD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD213SD_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMADD213SD_RU_SAE_Z(x, x1, k, x2) } + +// VFMADD213SD_RZ_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD213SD.RZ_SAE xmm xmm k xmm +// VFMADD213SD.RZ_SAE xmm xmm xmm +// Construct and append a VFMADD213SD.RZ_SAE instruction to the active function. +func (c *Context) VFMADD213SD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD213SD_RZ_SAE(ops...)) +} + +// VFMADD213SD_RZ_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD213SD.RZ_SAE xmm xmm k xmm +// VFMADD213SD.RZ_SAE xmm xmm xmm +// Construct and append a VFMADD213SD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMADD213SD_RZ_SAE(ops ...operand.Op) { ctx.VFMADD213SD_RZ_SAE(ops...) } + +// VFMADD213SD_RZ_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD213SD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD213SD.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMADD213SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMADD213SD_RZ_SAE_Z(x, x1, k, x2)) +} + +// VFMADD213SD_RZ_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD213SD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD213SD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD213SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMADD213SD_RZ_SAE_Z(x, x1, k, x2) } + +// VFMADD213SD_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD213SD.Z m64 xmm k xmm +// VFMADD213SD.Z xmm xmm k xmm +// Construct and append a VFMADD213SD.Z instruction to the active function. +func (c *Context) VFMADD213SD_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VFMADD213SD_Z(mx, x, k, x1)) +} + +// VFMADD213SD_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD213SD.Z m64 xmm k xmm +// VFMADD213SD.Z xmm xmm k xmm +// Construct and append a VFMADD213SD.Z instruction to the active function. +// Operates on the global context. +func VFMADD213SD_Z(mx, x, k, x1 operand.Op) { ctx.VFMADD213SD_Z(mx, x, k, x1) } + +// VFMADD213SS: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD213SS m32 xmm xmm +// VFMADD213SS xmm xmm xmm +// VFMADD213SS m32 xmm k xmm +// VFMADD213SS xmm xmm k xmm +// Construct and append a VFMADD213SS instruction to the active function. +func (c *Context) VFMADD213SS(ops ...operand.Op) { + c.addinstruction(x86.VFMADD213SS(ops...)) +} + +// VFMADD213SS: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD213SS m32 xmm xmm +// VFMADD213SS xmm xmm xmm +// VFMADD213SS m32 xmm k xmm +// VFMADD213SS xmm xmm k xmm +// Construct and append a VFMADD213SS instruction to the active function. +// Operates on the global context. +func VFMADD213SS(ops ...operand.Op) { ctx.VFMADD213SS(ops...) } + +// VFMADD213SS_RD_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD213SS.RD_SAE xmm xmm k xmm +// VFMADD213SS.RD_SAE xmm xmm xmm +// Construct and append a VFMADD213SS.RD_SAE instruction to the active function. +func (c *Context) VFMADD213SS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD213SS_RD_SAE(ops...)) +} + +// VFMADD213SS_RD_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD213SS.RD_SAE xmm xmm k xmm +// VFMADD213SS.RD_SAE xmm xmm xmm +// Construct and append a VFMADD213SS.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMADD213SS_RD_SAE(ops ...operand.Op) { ctx.VFMADD213SS_RD_SAE(ops...) } + +// VFMADD213SS_RD_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD213SS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD213SS.RD_SAE.Z instruction to the active function. +func (c *Context) VFMADD213SS_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMADD213SS_RD_SAE_Z(x, x1, k, x2)) +} + +// VFMADD213SS_RD_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD213SS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD213SS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD213SS_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMADD213SS_RD_SAE_Z(x, x1, k, x2) } + +// VFMADD213SS_RN_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD213SS.RN_SAE xmm xmm k xmm +// VFMADD213SS.RN_SAE xmm xmm xmm +// Construct and append a VFMADD213SS.RN_SAE instruction to the active function. +func (c *Context) VFMADD213SS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD213SS_RN_SAE(ops...)) +} + +// VFMADD213SS_RN_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD213SS.RN_SAE xmm xmm k xmm +// VFMADD213SS.RN_SAE xmm xmm xmm +// Construct and append a VFMADD213SS.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMADD213SS_RN_SAE(ops ...operand.Op) { ctx.VFMADD213SS_RN_SAE(ops...) } + +// VFMADD213SS_RN_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD213SS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD213SS.RN_SAE.Z instruction to the active function. +func (c *Context) VFMADD213SS_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMADD213SS_RN_SAE_Z(x, x1, k, x2)) +} + +// VFMADD213SS_RN_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD213SS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD213SS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD213SS_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMADD213SS_RN_SAE_Z(x, x1, k, x2) } + +// VFMADD213SS_RU_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD213SS.RU_SAE xmm xmm k xmm +// VFMADD213SS.RU_SAE xmm xmm xmm +// Construct and append a VFMADD213SS.RU_SAE instruction to the active function. +func (c *Context) VFMADD213SS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD213SS_RU_SAE(ops...)) +} + +// VFMADD213SS_RU_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD213SS.RU_SAE xmm xmm k xmm +// VFMADD213SS.RU_SAE xmm xmm xmm +// Construct and append a VFMADD213SS.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMADD213SS_RU_SAE(ops ...operand.Op) { ctx.VFMADD213SS_RU_SAE(ops...) } + +// VFMADD213SS_RU_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD213SS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD213SS.RU_SAE.Z instruction to the active function. +func (c *Context) VFMADD213SS_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMADD213SS_RU_SAE_Z(x, x1, k, x2)) +} + +// VFMADD213SS_RU_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD213SS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD213SS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD213SS_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMADD213SS_RU_SAE_Z(x, x1, k, x2) } + +// VFMADD213SS_RZ_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD213SS.RZ_SAE xmm xmm k xmm +// VFMADD213SS.RZ_SAE xmm xmm xmm +// Construct and append a VFMADD213SS.RZ_SAE instruction to the active function. +func (c *Context) VFMADD213SS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD213SS_RZ_SAE(ops...)) +} + +// VFMADD213SS_RZ_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD213SS.RZ_SAE xmm xmm k xmm +// VFMADD213SS.RZ_SAE xmm xmm xmm +// Construct and append a VFMADD213SS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMADD213SS_RZ_SAE(ops ...operand.Op) { ctx.VFMADD213SS_RZ_SAE(ops...) } + +// VFMADD213SS_RZ_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD213SS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD213SS.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMADD213SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMADD213SS_RZ_SAE_Z(x, x1, k, x2)) +} + +// VFMADD213SS_RZ_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD213SS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD213SS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD213SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMADD213SS_RZ_SAE_Z(x, x1, k, x2) } + +// VFMADD213SS_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD213SS.Z m32 xmm k xmm +// VFMADD213SS.Z xmm xmm k xmm +// Construct and append a VFMADD213SS.Z instruction to the active function. +func (c *Context) VFMADD213SS_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VFMADD213SS_Z(mx, x, k, x1)) +} + +// VFMADD213SS_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD213SS.Z m32 xmm k xmm +// VFMADD213SS.Z xmm xmm k xmm +// Construct and append a VFMADD213SS.Z instruction to the active function. +// Operates on the global context. +func VFMADD213SS_Z(mx, x, k, x1 operand.Op) { ctx.VFMADD213SS_Z(mx, x, k, x1) } + +// VFMADD231PD: Fused Multiply-Add of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD231PD m128 xmm xmm +// VFMADD231PD m256 ymm ymm +// VFMADD231PD xmm xmm xmm +// VFMADD231PD ymm ymm ymm +// VFMADD231PD m128 xmm k xmm +// VFMADD231PD m256 ymm k ymm +// VFMADD231PD xmm xmm k xmm +// VFMADD231PD ymm ymm k ymm +// VFMADD231PD m512 zmm k zmm +// VFMADD231PD m512 zmm zmm +// VFMADD231PD zmm zmm k zmm +// VFMADD231PD zmm zmm zmm +// Construct and append a VFMADD231PD instruction to the active function. +func (c *Context) VFMADD231PD(ops ...operand.Op) { + c.addinstruction(x86.VFMADD231PD(ops...)) +} + +// VFMADD231PD: Fused Multiply-Add of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD231PD m128 xmm xmm +// VFMADD231PD m256 ymm ymm +// VFMADD231PD xmm xmm xmm +// VFMADD231PD ymm ymm ymm +// VFMADD231PD m128 xmm k xmm +// VFMADD231PD m256 ymm k ymm +// VFMADD231PD xmm xmm k xmm +// VFMADD231PD ymm ymm k ymm +// VFMADD231PD m512 zmm k zmm +// VFMADD231PD m512 zmm zmm +// VFMADD231PD zmm zmm k zmm +// VFMADD231PD zmm zmm zmm +// Construct and append a VFMADD231PD instruction to the active function. +// Operates on the global context. +func VFMADD231PD(ops ...operand.Op) { ctx.VFMADD231PD(ops...) } + +// VFMADD231PD_BCST: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADD231PD.BCST m64 xmm k xmm +// VFMADD231PD.BCST m64 xmm xmm +// VFMADD231PD.BCST m64 ymm k ymm +// VFMADD231PD.BCST m64 ymm ymm +// VFMADD231PD.BCST m64 zmm k zmm +// VFMADD231PD.BCST m64 zmm zmm +// Construct and append a VFMADD231PD.BCST instruction to the active function. +func (c *Context) VFMADD231PD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFMADD231PD_BCST(ops...)) +} + +// VFMADD231PD_BCST: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADD231PD.BCST m64 xmm k xmm +// VFMADD231PD.BCST m64 xmm xmm +// VFMADD231PD.BCST m64 ymm k ymm +// VFMADD231PD.BCST m64 ymm ymm +// VFMADD231PD.BCST m64 zmm k zmm +// VFMADD231PD.BCST m64 zmm zmm +// Construct and append a VFMADD231PD.BCST instruction to the active function. +// Operates on the global context. +func VFMADD231PD_BCST(ops ...operand.Op) { ctx.VFMADD231PD_BCST(ops...) } + +// VFMADD231PD_BCST_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADD231PD.BCST.Z m64 xmm k xmm +// VFMADD231PD.BCST.Z m64 ymm k ymm +// VFMADD231PD.BCST.Z m64 zmm k zmm +// Construct and append a VFMADD231PD.BCST.Z instruction to the active function. +func (c *Context) VFMADD231PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMADD231PD_BCST_Z(m, xyz, k, xyz1)) +} + +// VFMADD231PD_BCST_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADD231PD.BCST.Z m64 xmm k xmm +// VFMADD231PD.BCST.Z m64 ymm k ymm +// VFMADD231PD.BCST.Z m64 zmm k zmm +// Construct and append a VFMADD231PD.BCST.Z instruction to the active function. +// Operates on the global context. +func VFMADD231PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFMADD231PD_BCST_Z(m, xyz, k, xyz1) } + +// VFMADD231PD_RD_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD231PD.RD_SAE zmm zmm k zmm +// VFMADD231PD.RD_SAE zmm zmm zmm +// Construct and append a VFMADD231PD.RD_SAE instruction to the active function. +func (c *Context) VFMADD231PD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD231PD_RD_SAE(ops...)) +} + +// VFMADD231PD_RD_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD231PD.RD_SAE zmm zmm k zmm +// VFMADD231PD.RD_SAE zmm zmm zmm +// Construct and append a VFMADD231PD.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMADD231PD_RD_SAE(ops ...operand.Op) { ctx.VFMADD231PD_RD_SAE(ops...) } + +// VFMADD231PD_RD_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD231PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD231PD.RD_SAE.Z instruction to the active function. +func (c *Context) VFMADD231PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADD231PD_RD_SAE_Z(z, z1, k, z2)) +} + +// VFMADD231PD_RD_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD231PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD231PD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD231PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADD231PD_RD_SAE_Z(z, z1, k, z2) } + +// VFMADD231PD_RN_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD231PD.RN_SAE zmm zmm k zmm +// VFMADD231PD.RN_SAE zmm zmm zmm +// Construct and append a VFMADD231PD.RN_SAE instruction to the active function. +func (c *Context) VFMADD231PD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD231PD_RN_SAE(ops...)) +} + +// VFMADD231PD_RN_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD231PD.RN_SAE zmm zmm k zmm +// VFMADD231PD.RN_SAE zmm zmm zmm +// Construct and append a VFMADD231PD.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMADD231PD_RN_SAE(ops ...operand.Op) { ctx.VFMADD231PD_RN_SAE(ops...) } + +// VFMADD231PD_RN_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD231PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD231PD.RN_SAE.Z instruction to the active function. +func (c *Context) VFMADD231PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADD231PD_RN_SAE_Z(z, z1, k, z2)) +} + +// VFMADD231PD_RN_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD231PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD231PD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD231PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADD231PD_RN_SAE_Z(z, z1, k, z2) } + +// VFMADD231PD_RU_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD231PD.RU_SAE zmm zmm k zmm +// VFMADD231PD.RU_SAE zmm zmm zmm +// Construct and append a VFMADD231PD.RU_SAE instruction to the active function. +func (c *Context) VFMADD231PD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD231PD_RU_SAE(ops...)) +} + +// VFMADD231PD_RU_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD231PD.RU_SAE zmm zmm k zmm +// VFMADD231PD.RU_SAE zmm zmm zmm +// Construct and append a VFMADD231PD.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMADD231PD_RU_SAE(ops ...operand.Op) { ctx.VFMADD231PD_RU_SAE(ops...) } + +// VFMADD231PD_RU_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD231PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD231PD.RU_SAE.Z instruction to the active function. +func (c *Context) VFMADD231PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADD231PD_RU_SAE_Z(z, z1, k, z2)) +} + +// VFMADD231PD_RU_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD231PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD231PD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD231PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADD231PD_RU_SAE_Z(z, z1, k, z2) } + +// VFMADD231PD_RZ_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD231PD.RZ_SAE zmm zmm k zmm +// VFMADD231PD.RZ_SAE zmm zmm zmm +// Construct and append a VFMADD231PD.RZ_SAE instruction to the active function. +func (c *Context) VFMADD231PD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD231PD_RZ_SAE(ops...)) +} + +// VFMADD231PD_RZ_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD231PD.RZ_SAE zmm zmm k zmm +// VFMADD231PD.RZ_SAE zmm zmm zmm +// Construct and append a VFMADD231PD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMADD231PD_RZ_SAE(ops ...operand.Op) { ctx.VFMADD231PD_RZ_SAE(ops...) } + +// VFMADD231PD_RZ_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD231PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD231PD.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMADD231PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADD231PD_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFMADD231PD_RZ_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD231PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD231PD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD231PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADD231PD_RZ_SAE_Z(z, z1, k, z2) } + +// VFMADD231PD_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD231PD.Z m128 xmm k xmm +// VFMADD231PD.Z m256 ymm k ymm +// VFMADD231PD.Z xmm xmm k xmm +// VFMADD231PD.Z ymm ymm k ymm +// VFMADD231PD.Z m512 zmm k zmm +// VFMADD231PD.Z zmm zmm k zmm +// Construct and append a VFMADD231PD.Z instruction to the active function. +func (c *Context) VFMADD231PD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMADD231PD_Z(mxyz, xyz, k, xyz1)) +} + +// VFMADD231PD_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD231PD.Z m128 xmm k xmm +// VFMADD231PD.Z m256 ymm k ymm +// VFMADD231PD.Z xmm xmm k xmm +// VFMADD231PD.Z ymm ymm k ymm +// VFMADD231PD.Z m512 zmm k zmm +// VFMADD231PD.Z zmm zmm k zmm +// Construct and append a VFMADD231PD.Z instruction to the active function. +// Operates on the global context. +func VFMADD231PD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFMADD231PD_Z(mxyz, xyz, k, xyz1) } + +// VFMADD231PS: Fused Multiply-Add of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD231PS m128 xmm xmm +// VFMADD231PS m256 ymm ymm +// VFMADD231PS xmm xmm xmm +// VFMADD231PS ymm ymm ymm +// VFMADD231PS m128 xmm k xmm +// VFMADD231PS m256 ymm k ymm +// VFMADD231PS xmm xmm k xmm +// VFMADD231PS ymm ymm k ymm +// VFMADD231PS m512 zmm k zmm +// VFMADD231PS m512 zmm zmm +// VFMADD231PS zmm zmm k zmm +// VFMADD231PS zmm zmm zmm +// Construct and append a VFMADD231PS instruction to the active function. +func (c *Context) VFMADD231PS(ops ...operand.Op) { + c.addinstruction(x86.VFMADD231PS(ops...)) +} + +// VFMADD231PS: Fused Multiply-Add of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD231PS m128 xmm xmm +// VFMADD231PS m256 ymm ymm +// VFMADD231PS xmm xmm xmm +// VFMADD231PS ymm ymm ymm +// VFMADD231PS m128 xmm k xmm +// VFMADD231PS m256 ymm k ymm +// VFMADD231PS xmm xmm k xmm +// VFMADD231PS ymm ymm k ymm +// VFMADD231PS m512 zmm k zmm +// VFMADD231PS m512 zmm zmm +// VFMADD231PS zmm zmm k zmm +// VFMADD231PS zmm zmm zmm +// Construct and append a VFMADD231PS instruction to the active function. +// Operates on the global context. +func VFMADD231PS(ops ...operand.Op) { ctx.VFMADD231PS(ops...) } + +// VFMADD231PS_BCST: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADD231PS.BCST m32 xmm k xmm +// VFMADD231PS.BCST m32 xmm xmm +// VFMADD231PS.BCST m32 ymm k ymm +// VFMADD231PS.BCST m32 ymm ymm +// VFMADD231PS.BCST m32 zmm k zmm +// VFMADD231PS.BCST m32 zmm zmm +// Construct and append a VFMADD231PS.BCST instruction to the active function. +func (c *Context) VFMADD231PS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFMADD231PS_BCST(ops...)) +} + +// VFMADD231PS_BCST: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADD231PS.BCST m32 xmm k xmm +// VFMADD231PS.BCST m32 xmm xmm +// VFMADD231PS.BCST m32 ymm k ymm +// VFMADD231PS.BCST m32 ymm ymm +// VFMADD231PS.BCST m32 zmm k zmm +// VFMADD231PS.BCST m32 zmm zmm +// Construct and append a VFMADD231PS.BCST instruction to the active function. +// Operates on the global context. +func VFMADD231PS_BCST(ops ...operand.Op) { ctx.VFMADD231PS_BCST(ops...) } + +// VFMADD231PS_BCST_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADD231PS.BCST.Z m32 xmm k xmm +// VFMADD231PS.BCST.Z m32 ymm k ymm +// VFMADD231PS.BCST.Z m32 zmm k zmm +// Construct and append a VFMADD231PS.BCST.Z instruction to the active function. +func (c *Context) VFMADD231PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMADD231PS_BCST_Z(m, xyz, k, xyz1)) +} + +// VFMADD231PS_BCST_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADD231PS.BCST.Z m32 xmm k xmm +// VFMADD231PS.BCST.Z m32 ymm k ymm +// VFMADD231PS.BCST.Z m32 zmm k zmm +// Construct and append a VFMADD231PS.BCST.Z instruction to the active function. +// Operates on the global context. +func VFMADD231PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFMADD231PS_BCST_Z(m, xyz, k, xyz1) } + +// VFMADD231PS_RD_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD231PS.RD_SAE zmm zmm k zmm +// VFMADD231PS.RD_SAE zmm zmm zmm +// Construct and append a VFMADD231PS.RD_SAE instruction to the active function. +func (c *Context) VFMADD231PS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD231PS_RD_SAE(ops...)) +} + +// VFMADD231PS_RD_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD231PS.RD_SAE zmm zmm k zmm +// VFMADD231PS.RD_SAE zmm zmm zmm +// Construct and append a VFMADD231PS.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMADD231PS_RD_SAE(ops ...operand.Op) { ctx.VFMADD231PS_RD_SAE(ops...) } + +// VFMADD231PS_RD_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD231PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD231PS.RD_SAE.Z instruction to the active function. +func (c *Context) VFMADD231PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADD231PS_RD_SAE_Z(z, z1, k, z2)) +} + +// VFMADD231PS_RD_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD231PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD231PS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD231PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADD231PS_RD_SAE_Z(z, z1, k, z2) } + +// VFMADD231PS_RN_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD231PS.RN_SAE zmm zmm k zmm +// VFMADD231PS.RN_SAE zmm zmm zmm +// Construct and append a VFMADD231PS.RN_SAE instruction to the active function. +func (c *Context) VFMADD231PS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD231PS_RN_SAE(ops...)) +} + +// VFMADD231PS_RN_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD231PS.RN_SAE zmm zmm k zmm +// VFMADD231PS.RN_SAE zmm zmm zmm +// Construct and append a VFMADD231PS.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMADD231PS_RN_SAE(ops ...operand.Op) { ctx.VFMADD231PS_RN_SAE(ops...) } + +// VFMADD231PS_RN_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD231PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD231PS.RN_SAE.Z instruction to the active function. +func (c *Context) VFMADD231PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADD231PS_RN_SAE_Z(z, z1, k, z2)) +} + +// VFMADD231PS_RN_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD231PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD231PS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD231PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADD231PS_RN_SAE_Z(z, z1, k, z2) } + +// VFMADD231PS_RU_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD231PS.RU_SAE zmm zmm k zmm +// VFMADD231PS.RU_SAE zmm zmm zmm +// Construct and append a VFMADD231PS.RU_SAE instruction to the active function. +func (c *Context) VFMADD231PS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD231PS_RU_SAE(ops...)) +} + +// VFMADD231PS_RU_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD231PS.RU_SAE zmm zmm k zmm +// VFMADD231PS.RU_SAE zmm zmm zmm +// Construct and append a VFMADD231PS.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMADD231PS_RU_SAE(ops ...operand.Op) { ctx.VFMADD231PS_RU_SAE(ops...) } + +// VFMADD231PS_RU_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD231PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD231PS.RU_SAE.Z instruction to the active function. +func (c *Context) VFMADD231PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADD231PS_RU_SAE_Z(z, z1, k, z2)) +} + +// VFMADD231PS_RU_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD231PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD231PS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD231PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADD231PS_RU_SAE_Z(z, z1, k, z2) } + +// VFMADD231PS_RZ_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD231PS.RZ_SAE zmm zmm k zmm +// VFMADD231PS.RZ_SAE zmm zmm zmm +// Construct and append a VFMADD231PS.RZ_SAE instruction to the active function. +func (c *Context) VFMADD231PS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD231PS_RZ_SAE(ops...)) +} + +// VFMADD231PS_RZ_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD231PS.RZ_SAE zmm zmm k zmm +// VFMADD231PS.RZ_SAE zmm zmm zmm +// Construct and append a VFMADD231PS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMADD231PS_RZ_SAE(ops ...operand.Op) { ctx.VFMADD231PS_RZ_SAE(ops...) } + +// VFMADD231PS_RZ_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD231PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD231PS.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMADD231PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADD231PS_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFMADD231PS_RZ_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD231PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMADD231PS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD231PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADD231PS_RZ_SAE_Z(z, z1, k, z2) } + +// VFMADD231PS_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD231PS.Z m128 xmm k xmm +// VFMADD231PS.Z m256 ymm k ymm +// VFMADD231PS.Z xmm xmm k xmm +// VFMADD231PS.Z ymm ymm k ymm +// VFMADD231PS.Z m512 zmm k zmm +// VFMADD231PS.Z zmm zmm k zmm +// Construct and append a VFMADD231PS.Z instruction to the active function. +func (c *Context) VFMADD231PS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMADD231PS_Z(mxyz, xyz, k, xyz1)) +} + +// VFMADD231PS_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD231PS.Z m128 xmm k xmm +// VFMADD231PS.Z m256 ymm k ymm +// VFMADD231PS.Z xmm xmm k xmm +// VFMADD231PS.Z ymm ymm k ymm +// VFMADD231PS.Z m512 zmm k zmm +// VFMADD231PS.Z zmm zmm k zmm +// Construct and append a VFMADD231PS.Z instruction to the active function. +// Operates on the global context. +func VFMADD231PS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFMADD231PS_Z(mxyz, xyz, k, xyz1) } + +// VFMADD231SD: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD231SD m64 xmm xmm +// VFMADD231SD xmm xmm xmm +// VFMADD231SD m64 xmm k xmm +// VFMADD231SD xmm xmm k xmm +// Construct and append a VFMADD231SD instruction to the active function. +func (c *Context) VFMADD231SD(ops ...operand.Op) { + c.addinstruction(x86.VFMADD231SD(ops...)) +} + +// VFMADD231SD: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD231SD m64 xmm xmm +// VFMADD231SD xmm xmm xmm +// VFMADD231SD m64 xmm k xmm +// VFMADD231SD xmm xmm k xmm +// Construct and append a VFMADD231SD instruction to the active function. +// Operates on the global context. +func VFMADD231SD(ops ...operand.Op) { ctx.VFMADD231SD(ops...) } + +// VFMADD231SD_RD_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD231SD.RD_SAE xmm xmm k xmm +// VFMADD231SD.RD_SAE xmm xmm xmm +// Construct and append a VFMADD231SD.RD_SAE instruction to the active function. +func (c *Context) VFMADD231SD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD231SD_RD_SAE(ops...)) +} + +// VFMADD231SD_RD_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD231SD.RD_SAE xmm xmm k xmm +// VFMADD231SD.RD_SAE xmm xmm xmm +// Construct and append a VFMADD231SD.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMADD231SD_RD_SAE(ops ...operand.Op) { ctx.VFMADD231SD_RD_SAE(ops...) } + +// VFMADD231SD_RD_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD231SD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD231SD.RD_SAE.Z instruction to the active function. +func (c *Context) VFMADD231SD_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMADD231SD_RD_SAE_Z(x, x1, k, x2)) +} + +// VFMADD231SD_RD_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD231SD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD231SD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD231SD_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMADD231SD_RD_SAE_Z(x, x1, k, x2) } + +// VFMADD231SD_RN_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD231SD.RN_SAE xmm xmm k xmm +// VFMADD231SD.RN_SAE xmm xmm xmm +// Construct and append a VFMADD231SD.RN_SAE instruction to the active function. +func (c *Context) VFMADD231SD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD231SD_RN_SAE(ops...)) +} + +// VFMADD231SD_RN_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD231SD.RN_SAE xmm xmm k xmm +// VFMADD231SD.RN_SAE xmm xmm xmm +// Construct and append a VFMADD231SD.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMADD231SD_RN_SAE(ops ...operand.Op) { ctx.VFMADD231SD_RN_SAE(ops...) } + +// VFMADD231SD_RN_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD231SD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD231SD.RN_SAE.Z instruction to the active function. +func (c *Context) VFMADD231SD_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMADD231SD_RN_SAE_Z(x, x1, k, x2)) +} + +// VFMADD231SD_RN_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD231SD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD231SD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD231SD_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMADD231SD_RN_SAE_Z(x, x1, k, x2) } + +// VFMADD231SD_RU_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD231SD.RU_SAE xmm xmm k xmm +// VFMADD231SD.RU_SAE xmm xmm xmm +// Construct and append a VFMADD231SD.RU_SAE instruction to the active function. +func (c *Context) VFMADD231SD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD231SD_RU_SAE(ops...)) +} + +// VFMADD231SD_RU_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD231SD.RU_SAE xmm xmm k xmm +// VFMADD231SD.RU_SAE xmm xmm xmm +// Construct and append a VFMADD231SD.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMADD231SD_RU_SAE(ops ...operand.Op) { ctx.VFMADD231SD_RU_SAE(ops...) } + +// VFMADD231SD_RU_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD231SD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD231SD.RU_SAE.Z instruction to the active function. +func (c *Context) VFMADD231SD_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMADD231SD_RU_SAE_Z(x, x1, k, x2)) +} + +// VFMADD231SD_RU_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD231SD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD231SD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD231SD_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMADD231SD_RU_SAE_Z(x, x1, k, x2) } + +// VFMADD231SD_RZ_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD231SD.RZ_SAE xmm xmm k xmm +// VFMADD231SD.RZ_SAE xmm xmm xmm +// Construct and append a VFMADD231SD.RZ_SAE instruction to the active function. +func (c *Context) VFMADD231SD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD231SD_RZ_SAE(ops...)) +} + +// VFMADD231SD_RZ_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD231SD.RZ_SAE xmm xmm k xmm +// VFMADD231SD.RZ_SAE xmm xmm xmm +// Construct and append a VFMADD231SD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMADD231SD_RZ_SAE(ops ...operand.Op) { ctx.VFMADD231SD_RZ_SAE(ops...) } + +// VFMADD231SD_RZ_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD231SD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD231SD.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMADD231SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMADD231SD_RZ_SAE_Z(x, x1, k, x2)) +} + +// VFMADD231SD_RZ_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD231SD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD231SD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD231SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMADD231SD_RZ_SAE_Z(x, x1, k, x2) } + +// VFMADD231SD_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD231SD.Z m64 xmm k xmm +// VFMADD231SD.Z xmm xmm k xmm +// Construct and append a VFMADD231SD.Z instruction to the active function. +func (c *Context) VFMADD231SD_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VFMADD231SD_Z(mx, x, k, x1)) +} + +// VFMADD231SD_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD231SD.Z m64 xmm k xmm +// VFMADD231SD.Z xmm xmm k xmm +// Construct and append a VFMADD231SD.Z instruction to the active function. +// Operates on the global context. +func VFMADD231SD_Z(mx, x, k, x1 operand.Op) { ctx.VFMADD231SD_Z(mx, x, k, x1) } + +// VFMADD231SS: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD231SS m32 xmm xmm +// VFMADD231SS xmm xmm xmm +// VFMADD231SS m32 xmm k xmm +// VFMADD231SS xmm xmm k xmm +// Construct and append a VFMADD231SS instruction to the active function. +func (c *Context) VFMADD231SS(ops ...operand.Op) { + c.addinstruction(x86.VFMADD231SS(ops...)) +} + +// VFMADD231SS: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD231SS m32 xmm xmm +// VFMADD231SS xmm xmm xmm +// VFMADD231SS m32 xmm k xmm +// VFMADD231SS xmm xmm k xmm +// Construct and append a VFMADD231SS instruction to the active function. +// Operates on the global context. +func VFMADD231SS(ops ...operand.Op) { ctx.VFMADD231SS(ops...) } + +// VFMADD231SS_RD_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD231SS.RD_SAE xmm xmm k xmm +// VFMADD231SS.RD_SAE xmm xmm xmm +// Construct and append a VFMADD231SS.RD_SAE instruction to the active function. +func (c *Context) VFMADD231SS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD231SS_RD_SAE(ops...)) +} + +// VFMADD231SS_RD_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD231SS.RD_SAE xmm xmm k xmm +// VFMADD231SS.RD_SAE xmm xmm xmm +// Construct and append a VFMADD231SS.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMADD231SS_RD_SAE(ops ...operand.Op) { ctx.VFMADD231SS_RD_SAE(ops...) } + +// VFMADD231SS_RD_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD231SS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD231SS.RD_SAE.Z instruction to the active function. +func (c *Context) VFMADD231SS_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMADD231SS_RD_SAE_Z(x, x1, k, x2)) +} + +// VFMADD231SS_RD_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD231SS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD231SS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD231SS_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMADD231SS_RD_SAE_Z(x, x1, k, x2) } + +// VFMADD231SS_RN_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD231SS.RN_SAE xmm xmm k xmm +// VFMADD231SS.RN_SAE xmm xmm xmm +// Construct and append a VFMADD231SS.RN_SAE instruction to the active function. +func (c *Context) VFMADD231SS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD231SS_RN_SAE(ops...)) +} + +// VFMADD231SS_RN_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD231SS.RN_SAE xmm xmm k xmm +// VFMADD231SS.RN_SAE xmm xmm xmm +// Construct and append a VFMADD231SS.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMADD231SS_RN_SAE(ops ...operand.Op) { ctx.VFMADD231SS_RN_SAE(ops...) } + +// VFMADD231SS_RN_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD231SS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD231SS.RN_SAE.Z instruction to the active function. +func (c *Context) VFMADD231SS_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMADD231SS_RN_SAE_Z(x, x1, k, x2)) +} + +// VFMADD231SS_RN_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD231SS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD231SS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD231SS_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMADD231SS_RN_SAE_Z(x, x1, k, x2) } + +// VFMADD231SS_RU_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD231SS.RU_SAE xmm xmm k xmm +// VFMADD231SS.RU_SAE xmm xmm xmm +// Construct and append a VFMADD231SS.RU_SAE instruction to the active function. +func (c *Context) VFMADD231SS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD231SS_RU_SAE(ops...)) +} + +// VFMADD231SS_RU_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD231SS.RU_SAE xmm xmm k xmm +// VFMADD231SS.RU_SAE xmm xmm xmm +// Construct and append a VFMADD231SS.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMADD231SS_RU_SAE(ops ...operand.Op) { ctx.VFMADD231SS_RU_SAE(ops...) } + +// VFMADD231SS_RU_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD231SS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD231SS.RU_SAE.Z instruction to the active function. +func (c *Context) VFMADD231SS_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMADD231SS_RU_SAE_Z(x, x1, k, x2)) +} + +// VFMADD231SS_RU_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD231SS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD231SS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD231SS_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMADD231SS_RU_SAE_Z(x, x1, k, x2) } + +// VFMADD231SS_RZ_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD231SS.RZ_SAE xmm xmm k xmm +// VFMADD231SS.RZ_SAE xmm xmm xmm +// Construct and append a VFMADD231SS.RZ_SAE instruction to the active function. +func (c *Context) VFMADD231SS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADD231SS_RZ_SAE(ops...)) +} + +// VFMADD231SS_RZ_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD231SS.RZ_SAE xmm xmm k xmm +// VFMADD231SS.RZ_SAE xmm xmm xmm +// Construct and append a VFMADD231SS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMADD231SS_RZ_SAE(ops ...operand.Op) { ctx.VFMADD231SS_RZ_SAE(ops...) } + +// VFMADD231SS_RZ_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD231SS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD231SS.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMADD231SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMADD231SS_RZ_SAE_Z(x, x1, k, x2)) +} + +// VFMADD231SS_RZ_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD231SS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFMADD231SS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADD231SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMADD231SS_RZ_SAE_Z(x, x1, k, x2) } + +// VFMADD231SS_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD231SS.Z m32 xmm k xmm +// VFMADD231SS.Z xmm xmm k xmm +// Construct and append a VFMADD231SS.Z instruction to the active function. +func (c *Context) VFMADD231SS_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VFMADD231SS_Z(mx, x, k, x1)) +} + +// VFMADD231SS_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD231SS.Z m32 xmm k xmm +// VFMADD231SS.Z xmm xmm k xmm +// Construct and append a VFMADD231SS.Z instruction to the active function. +// Operates on the global context. +func VFMADD231SS_Z(mx, x, k, x1 operand.Op) { ctx.VFMADD231SS_Z(mx, x, k, x1) } + +// VFMADDSUB132PD: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMADDSUB132PD m128 xmm xmm +// VFMADDSUB132PD m256 ymm ymm +// VFMADDSUB132PD xmm xmm xmm +// VFMADDSUB132PD ymm ymm ymm +// VFMADDSUB132PD m128 xmm k xmm +// VFMADDSUB132PD m256 ymm k ymm +// VFMADDSUB132PD xmm xmm k xmm +// VFMADDSUB132PD ymm ymm k ymm +// VFMADDSUB132PD m512 zmm k zmm +// VFMADDSUB132PD m512 zmm zmm +// VFMADDSUB132PD zmm zmm k zmm +// VFMADDSUB132PD zmm zmm zmm +// Construct and append a VFMADDSUB132PD instruction to the active function. +func (c *Context) VFMADDSUB132PD(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB132PD(ops...)) +} + +// VFMADDSUB132PD: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMADDSUB132PD m128 xmm xmm +// VFMADDSUB132PD m256 ymm ymm +// VFMADDSUB132PD xmm xmm xmm +// VFMADDSUB132PD ymm ymm ymm +// VFMADDSUB132PD m128 xmm k xmm +// VFMADDSUB132PD m256 ymm k ymm +// VFMADDSUB132PD xmm xmm k xmm +// VFMADDSUB132PD ymm ymm k ymm +// VFMADDSUB132PD m512 zmm k zmm +// VFMADDSUB132PD m512 zmm zmm +// VFMADDSUB132PD zmm zmm k zmm +// VFMADDSUB132PD zmm zmm zmm +// Construct and append a VFMADDSUB132PD instruction to the active function. +// Operates on the global context. +func VFMADDSUB132PD(ops ...operand.Op) { ctx.VFMADDSUB132PD(ops...) } + +// VFMADDSUB132PD_BCST: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADDSUB132PD.BCST m64 xmm k xmm +// VFMADDSUB132PD.BCST m64 xmm xmm +// VFMADDSUB132PD.BCST m64 ymm k ymm +// VFMADDSUB132PD.BCST m64 ymm ymm +// VFMADDSUB132PD.BCST m64 zmm k zmm +// VFMADDSUB132PD.BCST m64 zmm zmm +// Construct and append a VFMADDSUB132PD.BCST instruction to the active function. +func (c *Context) VFMADDSUB132PD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB132PD_BCST(ops...)) +} + +// VFMADDSUB132PD_BCST: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADDSUB132PD.BCST m64 xmm k xmm +// VFMADDSUB132PD.BCST m64 xmm xmm +// VFMADDSUB132PD.BCST m64 ymm k ymm +// VFMADDSUB132PD.BCST m64 ymm ymm +// VFMADDSUB132PD.BCST m64 zmm k zmm +// VFMADDSUB132PD.BCST m64 zmm zmm +// Construct and append a VFMADDSUB132PD.BCST instruction to the active function. +// Operates on the global context. +func VFMADDSUB132PD_BCST(ops ...operand.Op) { ctx.VFMADDSUB132PD_BCST(ops...) } + +// VFMADDSUB132PD_BCST_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PD.BCST.Z m64 xmm k xmm +// VFMADDSUB132PD.BCST.Z m64 ymm k ymm +// VFMADDSUB132PD.BCST.Z m64 zmm k zmm +// Construct and append a VFMADDSUB132PD.BCST.Z instruction to the active function. +func (c *Context) VFMADDSUB132PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMADDSUB132PD_BCST_Z(m, xyz, k, xyz1)) +} + +// VFMADDSUB132PD_BCST_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PD.BCST.Z m64 xmm k xmm +// VFMADDSUB132PD.BCST.Z m64 ymm k ymm +// VFMADDSUB132PD.BCST.Z m64 zmm k zmm +// Construct and append a VFMADDSUB132PD.BCST.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB132PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFMADDSUB132PD_BCST_Z(m, xyz, k, xyz1) } + +// VFMADDSUB132PD_RD_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADDSUB132PD.RD_SAE zmm zmm k zmm +// VFMADDSUB132PD.RD_SAE zmm zmm zmm +// Construct and append a VFMADDSUB132PD.RD_SAE instruction to the active function. +func (c *Context) VFMADDSUB132PD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB132PD_RD_SAE(ops...)) +} + +// VFMADDSUB132PD_RD_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADDSUB132PD.RD_SAE zmm zmm k zmm +// VFMADDSUB132PD.RD_SAE zmm zmm zmm +// Construct and append a VFMADDSUB132PD.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMADDSUB132PD_RD_SAE(ops ...operand.Op) { ctx.VFMADDSUB132PD_RD_SAE(ops...) } + +// VFMADDSUB132PD_RD_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB132PD.RD_SAE.Z instruction to the active function. +func (c *Context) VFMADDSUB132PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADDSUB132PD_RD_SAE_Z(z, z1, k, z2)) +} + +// VFMADDSUB132PD_RD_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB132PD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB132PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADDSUB132PD_RD_SAE_Z(z, z1, k, z2) } + +// VFMADDSUB132PD_RN_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADDSUB132PD.RN_SAE zmm zmm k zmm +// VFMADDSUB132PD.RN_SAE zmm zmm zmm +// Construct and append a VFMADDSUB132PD.RN_SAE instruction to the active function. +func (c *Context) VFMADDSUB132PD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB132PD_RN_SAE(ops...)) +} + +// VFMADDSUB132PD_RN_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADDSUB132PD.RN_SAE zmm zmm k zmm +// VFMADDSUB132PD.RN_SAE zmm zmm zmm +// Construct and append a VFMADDSUB132PD.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMADDSUB132PD_RN_SAE(ops ...operand.Op) { ctx.VFMADDSUB132PD_RN_SAE(ops...) } + +// VFMADDSUB132PD_RN_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB132PD.RN_SAE.Z instruction to the active function. +func (c *Context) VFMADDSUB132PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADDSUB132PD_RN_SAE_Z(z, z1, k, z2)) +} + +// VFMADDSUB132PD_RN_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB132PD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB132PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADDSUB132PD_RN_SAE_Z(z, z1, k, z2) } + +// VFMADDSUB132PD_RU_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADDSUB132PD.RU_SAE zmm zmm k zmm +// VFMADDSUB132PD.RU_SAE zmm zmm zmm +// Construct and append a VFMADDSUB132PD.RU_SAE instruction to the active function. +func (c *Context) VFMADDSUB132PD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB132PD_RU_SAE(ops...)) +} + +// VFMADDSUB132PD_RU_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADDSUB132PD.RU_SAE zmm zmm k zmm +// VFMADDSUB132PD.RU_SAE zmm zmm zmm +// Construct and append a VFMADDSUB132PD.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMADDSUB132PD_RU_SAE(ops ...operand.Op) { ctx.VFMADDSUB132PD_RU_SAE(ops...) } + +// VFMADDSUB132PD_RU_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB132PD.RU_SAE.Z instruction to the active function. +func (c *Context) VFMADDSUB132PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADDSUB132PD_RU_SAE_Z(z, z1, k, z2)) +} + +// VFMADDSUB132PD_RU_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB132PD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB132PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADDSUB132PD_RU_SAE_Z(z, z1, k, z2) } + +// VFMADDSUB132PD_RZ_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADDSUB132PD.RZ_SAE zmm zmm k zmm +// VFMADDSUB132PD.RZ_SAE zmm zmm zmm +// Construct and append a VFMADDSUB132PD.RZ_SAE instruction to the active function. +func (c *Context) VFMADDSUB132PD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB132PD_RZ_SAE(ops...)) +} + +// VFMADDSUB132PD_RZ_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADDSUB132PD.RZ_SAE zmm zmm k zmm +// VFMADDSUB132PD.RZ_SAE zmm zmm zmm +// Construct and append a VFMADDSUB132PD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMADDSUB132PD_RZ_SAE(ops ...operand.Op) { ctx.VFMADDSUB132PD_RZ_SAE(ops...) } + +// VFMADDSUB132PD_RZ_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB132PD.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMADDSUB132PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADDSUB132PD_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFMADDSUB132PD_RZ_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB132PD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB132PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADDSUB132PD_RZ_SAE_Z(z, z1, k, z2) } + +// VFMADDSUB132PD_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PD.Z m128 xmm k xmm +// VFMADDSUB132PD.Z m256 ymm k ymm +// VFMADDSUB132PD.Z xmm xmm k xmm +// VFMADDSUB132PD.Z ymm ymm k ymm +// VFMADDSUB132PD.Z m512 zmm k zmm +// VFMADDSUB132PD.Z zmm zmm k zmm +// Construct and append a VFMADDSUB132PD.Z instruction to the active function. +func (c *Context) VFMADDSUB132PD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMADDSUB132PD_Z(mxyz, xyz, k, xyz1)) +} + +// VFMADDSUB132PD_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PD.Z m128 xmm k xmm +// VFMADDSUB132PD.Z m256 ymm k ymm +// VFMADDSUB132PD.Z xmm xmm k xmm +// VFMADDSUB132PD.Z ymm ymm k ymm +// VFMADDSUB132PD.Z m512 zmm k zmm +// VFMADDSUB132PD.Z zmm zmm k zmm +// Construct and append a VFMADDSUB132PD.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB132PD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFMADDSUB132PD_Z(mxyz, xyz, k, xyz1) } + +// VFMADDSUB132PS: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMADDSUB132PS m128 xmm xmm +// VFMADDSUB132PS m256 ymm ymm +// VFMADDSUB132PS xmm xmm xmm +// VFMADDSUB132PS ymm ymm ymm +// VFMADDSUB132PS m128 xmm k xmm +// VFMADDSUB132PS m256 ymm k ymm +// VFMADDSUB132PS xmm xmm k xmm +// VFMADDSUB132PS ymm ymm k ymm +// VFMADDSUB132PS m512 zmm k zmm +// VFMADDSUB132PS m512 zmm zmm +// VFMADDSUB132PS zmm zmm k zmm +// VFMADDSUB132PS zmm zmm zmm +// Construct and append a VFMADDSUB132PS instruction to the active function. +func (c *Context) VFMADDSUB132PS(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB132PS(ops...)) +} + +// VFMADDSUB132PS: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMADDSUB132PS m128 xmm xmm +// VFMADDSUB132PS m256 ymm ymm +// VFMADDSUB132PS xmm xmm xmm +// VFMADDSUB132PS ymm ymm ymm +// VFMADDSUB132PS m128 xmm k xmm +// VFMADDSUB132PS m256 ymm k ymm +// VFMADDSUB132PS xmm xmm k xmm +// VFMADDSUB132PS ymm ymm k ymm +// VFMADDSUB132PS m512 zmm k zmm +// VFMADDSUB132PS m512 zmm zmm +// VFMADDSUB132PS zmm zmm k zmm +// VFMADDSUB132PS zmm zmm zmm +// Construct and append a VFMADDSUB132PS instruction to the active function. +// Operates on the global context. +func VFMADDSUB132PS(ops ...operand.Op) { ctx.VFMADDSUB132PS(ops...) } + +// VFMADDSUB132PS_BCST: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADDSUB132PS.BCST m32 xmm k xmm +// VFMADDSUB132PS.BCST m32 xmm xmm +// VFMADDSUB132PS.BCST m32 ymm k ymm +// VFMADDSUB132PS.BCST m32 ymm ymm +// VFMADDSUB132PS.BCST m32 zmm k zmm +// VFMADDSUB132PS.BCST m32 zmm zmm +// Construct and append a VFMADDSUB132PS.BCST instruction to the active function. +func (c *Context) VFMADDSUB132PS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB132PS_BCST(ops...)) +} + +// VFMADDSUB132PS_BCST: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADDSUB132PS.BCST m32 xmm k xmm +// VFMADDSUB132PS.BCST m32 xmm xmm +// VFMADDSUB132PS.BCST m32 ymm k ymm +// VFMADDSUB132PS.BCST m32 ymm ymm +// VFMADDSUB132PS.BCST m32 zmm k zmm +// VFMADDSUB132PS.BCST m32 zmm zmm +// Construct and append a VFMADDSUB132PS.BCST instruction to the active function. +// Operates on the global context. +func VFMADDSUB132PS_BCST(ops ...operand.Op) { ctx.VFMADDSUB132PS_BCST(ops...) } + +// VFMADDSUB132PS_BCST_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PS.BCST.Z m32 xmm k xmm +// VFMADDSUB132PS.BCST.Z m32 ymm k ymm +// VFMADDSUB132PS.BCST.Z m32 zmm k zmm +// Construct and append a VFMADDSUB132PS.BCST.Z instruction to the active function. +func (c *Context) VFMADDSUB132PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMADDSUB132PS_BCST_Z(m, xyz, k, xyz1)) +} + +// VFMADDSUB132PS_BCST_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PS.BCST.Z m32 xmm k xmm +// VFMADDSUB132PS.BCST.Z m32 ymm k ymm +// VFMADDSUB132PS.BCST.Z m32 zmm k zmm +// Construct and append a VFMADDSUB132PS.BCST.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB132PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFMADDSUB132PS_BCST_Z(m, xyz, k, xyz1) } + +// VFMADDSUB132PS_RD_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADDSUB132PS.RD_SAE zmm zmm k zmm +// VFMADDSUB132PS.RD_SAE zmm zmm zmm +// Construct and append a VFMADDSUB132PS.RD_SAE instruction to the active function. +func (c *Context) VFMADDSUB132PS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB132PS_RD_SAE(ops...)) +} + +// VFMADDSUB132PS_RD_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADDSUB132PS.RD_SAE zmm zmm k zmm +// VFMADDSUB132PS.RD_SAE zmm zmm zmm +// Construct and append a VFMADDSUB132PS.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMADDSUB132PS_RD_SAE(ops ...operand.Op) { ctx.VFMADDSUB132PS_RD_SAE(ops...) } + +// VFMADDSUB132PS_RD_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB132PS.RD_SAE.Z instruction to the active function. +func (c *Context) VFMADDSUB132PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADDSUB132PS_RD_SAE_Z(z, z1, k, z2)) +} + +// VFMADDSUB132PS_RD_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB132PS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB132PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADDSUB132PS_RD_SAE_Z(z, z1, k, z2) } + +// VFMADDSUB132PS_RN_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADDSUB132PS.RN_SAE zmm zmm k zmm +// VFMADDSUB132PS.RN_SAE zmm zmm zmm +// Construct and append a VFMADDSUB132PS.RN_SAE instruction to the active function. +func (c *Context) VFMADDSUB132PS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB132PS_RN_SAE(ops...)) +} + +// VFMADDSUB132PS_RN_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADDSUB132PS.RN_SAE zmm zmm k zmm +// VFMADDSUB132PS.RN_SAE zmm zmm zmm +// Construct and append a VFMADDSUB132PS.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMADDSUB132PS_RN_SAE(ops ...operand.Op) { ctx.VFMADDSUB132PS_RN_SAE(ops...) } + +// VFMADDSUB132PS_RN_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB132PS.RN_SAE.Z instruction to the active function. +func (c *Context) VFMADDSUB132PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADDSUB132PS_RN_SAE_Z(z, z1, k, z2)) +} + +// VFMADDSUB132PS_RN_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB132PS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB132PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADDSUB132PS_RN_SAE_Z(z, z1, k, z2) } + +// VFMADDSUB132PS_RU_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADDSUB132PS.RU_SAE zmm zmm k zmm +// VFMADDSUB132PS.RU_SAE zmm zmm zmm +// Construct and append a VFMADDSUB132PS.RU_SAE instruction to the active function. +func (c *Context) VFMADDSUB132PS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB132PS_RU_SAE(ops...)) +} + +// VFMADDSUB132PS_RU_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADDSUB132PS.RU_SAE zmm zmm k zmm +// VFMADDSUB132PS.RU_SAE zmm zmm zmm +// Construct and append a VFMADDSUB132PS.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMADDSUB132PS_RU_SAE(ops ...operand.Op) { ctx.VFMADDSUB132PS_RU_SAE(ops...) } + +// VFMADDSUB132PS_RU_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB132PS.RU_SAE.Z instruction to the active function. +func (c *Context) VFMADDSUB132PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADDSUB132PS_RU_SAE_Z(z, z1, k, z2)) +} + +// VFMADDSUB132PS_RU_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB132PS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB132PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADDSUB132PS_RU_SAE_Z(z, z1, k, z2) } + +// VFMADDSUB132PS_RZ_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADDSUB132PS.RZ_SAE zmm zmm k zmm +// VFMADDSUB132PS.RZ_SAE zmm zmm zmm +// Construct and append a VFMADDSUB132PS.RZ_SAE instruction to the active function. +func (c *Context) VFMADDSUB132PS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB132PS_RZ_SAE(ops...)) +} + +// VFMADDSUB132PS_RZ_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADDSUB132PS.RZ_SAE zmm zmm k zmm +// VFMADDSUB132PS.RZ_SAE zmm zmm zmm +// Construct and append a VFMADDSUB132PS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMADDSUB132PS_RZ_SAE(ops ...operand.Op) { ctx.VFMADDSUB132PS_RZ_SAE(ops...) } + +// VFMADDSUB132PS_RZ_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB132PS.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMADDSUB132PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADDSUB132PS_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFMADDSUB132PS_RZ_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB132PS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB132PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADDSUB132PS_RZ_SAE_Z(z, z1, k, z2) } + +// VFMADDSUB132PS_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PS.Z m128 xmm k xmm +// VFMADDSUB132PS.Z m256 ymm k ymm +// VFMADDSUB132PS.Z xmm xmm k xmm +// VFMADDSUB132PS.Z ymm ymm k ymm +// VFMADDSUB132PS.Z m512 zmm k zmm +// VFMADDSUB132PS.Z zmm zmm k zmm +// Construct and append a VFMADDSUB132PS.Z instruction to the active function. +func (c *Context) VFMADDSUB132PS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMADDSUB132PS_Z(mxyz, xyz, k, xyz1)) +} + +// VFMADDSUB132PS_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PS.Z m128 xmm k xmm +// VFMADDSUB132PS.Z m256 ymm k ymm +// VFMADDSUB132PS.Z xmm xmm k xmm +// VFMADDSUB132PS.Z ymm ymm k ymm +// VFMADDSUB132PS.Z m512 zmm k zmm +// VFMADDSUB132PS.Z zmm zmm k zmm +// Construct and append a VFMADDSUB132PS.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB132PS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFMADDSUB132PS_Z(mxyz, xyz, k, xyz1) } + +// VFMADDSUB213PD: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMADDSUB213PD m128 xmm xmm +// VFMADDSUB213PD m256 ymm ymm +// VFMADDSUB213PD xmm xmm xmm +// VFMADDSUB213PD ymm ymm ymm +// VFMADDSUB213PD m128 xmm k xmm +// VFMADDSUB213PD m256 ymm k ymm +// VFMADDSUB213PD xmm xmm k xmm +// VFMADDSUB213PD ymm ymm k ymm +// VFMADDSUB213PD m512 zmm k zmm +// VFMADDSUB213PD m512 zmm zmm +// VFMADDSUB213PD zmm zmm k zmm +// VFMADDSUB213PD zmm zmm zmm +// Construct and append a VFMADDSUB213PD instruction to the active function. +func (c *Context) VFMADDSUB213PD(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB213PD(ops...)) +} + +// VFMADDSUB213PD: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMADDSUB213PD m128 xmm xmm +// VFMADDSUB213PD m256 ymm ymm +// VFMADDSUB213PD xmm xmm xmm +// VFMADDSUB213PD ymm ymm ymm +// VFMADDSUB213PD m128 xmm k xmm +// VFMADDSUB213PD m256 ymm k ymm +// VFMADDSUB213PD xmm xmm k xmm +// VFMADDSUB213PD ymm ymm k ymm +// VFMADDSUB213PD m512 zmm k zmm +// VFMADDSUB213PD m512 zmm zmm +// VFMADDSUB213PD zmm zmm k zmm +// VFMADDSUB213PD zmm zmm zmm +// Construct and append a VFMADDSUB213PD instruction to the active function. +// Operates on the global context. +func VFMADDSUB213PD(ops ...operand.Op) { ctx.VFMADDSUB213PD(ops...) } + +// VFMADDSUB213PD_BCST: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADDSUB213PD.BCST m64 xmm k xmm +// VFMADDSUB213PD.BCST m64 xmm xmm +// VFMADDSUB213PD.BCST m64 ymm k ymm +// VFMADDSUB213PD.BCST m64 ymm ymm +// VFMADDSUB213PD.BCST m64 zmm k zmm +// VFMADDSUB213PD.BCST m64 zmm zmm +// Construct and append a VFMADDSUB213PD.BCST instruction to the active function. +func (c *Context) VFMADDSUB213PD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB213PD_BCST(ops...)) +} + +// VFMADDSUB213PD_BCST: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADDSUB213PD.BCST m64 xmm k xmm +// VFMADDSUB213PD.BCST m64 xmm xmm +// VFMADDSUB213PD.BCST m64 ymm k ymm +// VFMADDSUB213PD.BCST m64 ymm ymm +// VFMADDSUB213PD.BCST m64 zmm k zmm +// VFMADDSUB213PD.BCST m64 zmm zmm +// Construct and append a VFMADDSUB213PD.BCST instruction to the active function. +// Operates on the global context. +func VFMADDSUB213PD_BCST(ops ...operand.Op) { ctx.VFMADDSUB213PD_BCST(ops...) } + +// VFMADDSUB213PD_BCST_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PD.BCST.Z m64 xmm k xmm +// VFMADDSUB213PD.BCST.Z m64 ymm k ymm +// VFMADDSUB213PD.BCST.Z m64 zmm k zmm +// Construct and append a VFMADDSUB213PD.BCST.Z instruction to the active function. +func (c *Context) VFMADDSUB213PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMADDSUB213PD_BCST_Z(m, xyz, k, xyz1)) +} + +// VFMADDSUB213PD_BCST_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PD.BCST.Z m64 xmm k xmm +// VFMADDSUB213PD.BCST.Z m64 ymm k ymm +// VFMADDSUB213PD.BCST.Z m64 zmm k zmm +// Construct and append a VFMADDSUB213PD.BCST.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB213PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFMADDSUB213PD_BCST_Z(m, xyz, k, xyz1) } + +// VFMADDSUB213PD_RD_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADDSUB213PD.RD_SAE zmm zmm k zmm +// VFMADDSUB213PD.RD_SAE zmm zmm zmm +// Construct and append a VFMADDSUB213PD.RD_SAE instruction to the active function. +func (c *Context) VFMADDSUB213PD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB213PD_RD_SAE(ops...)) +} + +// VFMADDSUB213PD_RD_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADDSUB213PD.RD_SAE zmm zmm k zmm +// VFMADDSUB213PD.RD_SAE zmm zmm zmm +// Construct and append a VFMADDSUB213PD.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMADDSUB213PD_RD_SAE(ops ...operand.Op) { ctx.VFMADDSUB213PD_RD_SAE(ops...) } + +// VFMADDSUB213PD_RD_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB213PD.RD_SAE.Z instruction to the active function. +func (c *Context) VFMADDSUB213PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADDSUB213PD_RD_SAE_Z(z, z1, k, z2)) +} + +// VFMADDSUB213PD_RD_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB213PD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB213PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADDSUB213PD_RD_SAE_Z(z, z1, k, z2) } + +// VFMADDSUB213PD_RN_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADDSUB213PD.RN_SAE zmm zmm k zmm +// VFMADDSUB213PD.RN_SAE zmm zmm zmm +// Construct and append a VFMADDSUB213PD.RN_SAE instruction to the active function. +func (c *Context) VFMADDSUB213PD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB213PD_RN_SAE(ops...)) +} + +// VFMADDSUB213PD_RN_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADDSUB213PD.RN_SAE zmm zmm k zmm +// VFMADDSUB213PD.RN_SAE zmm zmm zmm +// Construct and append a VFMADDSUB213PD.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMADDSUB213PD_RN_SAE(ops ...operand.Op) { ctx.VFMADDSUB213PD_RN_SAE(ops...) } + +// VFMADDSUB213PD_RN_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB213PD.RN_SAE.Z instruction to the active function. +func (c *Context) VFMADDSUB213PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADDSUB213PD_RN_SAE_Z(z, z1, k, z2)) +} + +// VFMADDSUB213PD_RN_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB213PD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB213PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADDSUB213PD_RN_SAE_Z(z, z1, k, z2) } + +// VFMADDSUB213PD_RU_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADDSUB213PD.RU_SAE zmm zmm k zmm +// VFMADDSUB213PD.RU_SAE zmm zmm zmm +// Construct and append a VFMADDSUB213PD.RU_SAE instruction to the active function. +func (c *Context) VFMADDSUB213PD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB213PD_RU_SAE(ops...)) +} + +// VFMADDSUB213PD_RU_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADDSUB213PD.RU_SAE zmm zmm k zmm +// VFMADDSUB213PD.RU_SAE zmm zmm zmm +// Construct and append a VFMADDSUB213PD.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMADDSUB213PD_RU_SAE(ops ...operand.Op) { ctx.VFMADDSUB213PD_RU_SAE(ops...) } + +// VFMADDSUB213PD_RU_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB213PD.RU_SAE.Z instruction to the active function. +func (c *Context) VFMADDSUB213PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADDSUB213PD_RU_SAE_Z(z, z1, k, z2)) +} + +// VFMADDSUB213PD_RU_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB213PD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB213PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADDSUB213PD_RU_SAE_Z(z, z1, k, z2) } + +// VFMADDSUB213PD_RZ_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADDSUB213PD.RZ_SAE zmm zmm k zmm +// VFMADDSUB213PD.RZ_SAE zmm zmm zmm +// Construct and append a VFMADDSUB213PD.RZ_SAE instruction to the active function. +func (c *Context) VFMADDSUB213PD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB213PD_RZ_SAE(ops...)) +} + +// VFMADDSUB213PD_RZ_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADDSUB213PD.RZ_SAE zmm zmm k zmm +// VFMADDSUB213PD.RZ_SAE zmm zmm zmm +// Construct and append a VFMADDSUB213PD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMADDSUB213PD_RZ_SAE(ops ...operand.Op) { ctx.VFMADDSUB213PD_RZ_SAE(ops...) } + +// VFMADDSUB213PD_RZ_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB213PD.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMADDSUB213PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADDSUB213PD_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFMADDSUB213PD_RZ_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB213PD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB213PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADDSUB213PD_RZ_SAE_Z(z, z1, k, z2) } + +// VFMADDSUB213PD_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PD.Z m128 xmm k xmm +// VFMADDSUB213PD.Z m256 ymm k ymm +// VFMADDSUB213PD.Z xmm xmm k xmm +// VFMADDSUB213PD.Z ymm ymm k ymm +// VFMADDSUB213PD.Z m512 zmm k zmm +// VFMADDSUB213PD.Z zmm zmm k zmm +// Construct and append a VFMADDSUB213PD.Z instruction to the active function. +func (c *Context) VFMADDSUB213PD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMADDSUB213PD_Z(mxyz, xyz, k, xyz1)) +} + +// VFMADDSUB213PD_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PD.Z m128 xmm k xmm +// VFMADDSUB213PD.Z m256 ymm k ymm +// VFMADDSUB213PD.Z xmm xmm k xmm +// VFMADDSUB213PD.Z ymm ymm k ymm +// VFMADDSUB213PD.Z m512 zmm k zmm +// VFMADDSUB213PD.Z zmm zmm k zmm +// Construct and append a VFMADDSUB213PD.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB213PD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFMADDSUB213PD_Z(mxyz, xyz, k, xyz1) } + +// VFMADDSUB213PS: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMADDSUB213PS m128 xmm xmm +// VFMADDSUB213PS m256 ymm ymm +// VFMADDSUB213PS xmm xmm xmm +// VFMADDSUB213PS ymm ymm ymm +// VFMADDSUB213PS m128 xmm k xmm +// VFMADDSUB213PS m256 ymm k ymm +// VFMADDSUB213PS xmm xmm k xmm +// VFMADDSUB213PS ymm ymm k ymm +// VFMADDSUB213PS m512 zmm k zmm +// VFMADDSUB213PS m512 zmm zmm +// VFMADDSUB213PS zmm zmm k zmm +// VFMADDSUB213PS zmm zmm zmm +// Construct and append a VFMADDSUB213PS instruction to the active function. +func (c *Context) VFMADDSUB213PS(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB213PS(ops...)) +} + +// VFMADDSUB213PS: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMADDSUB213PS m128 xmm xmm +// VFMADDSUB213PS m256 ymm ymm +// VFMADDSUB213PS xmm xmm xmm +// VFMADDSUB213PS ymm ymm ymm +// VFMADDSUB213PS m128 xmm k xmm +// VFMADDSUB213PS m256 ymm k ymm +// VFMADDSUB213PS xmm xmm k xmm +// VFMADDSUB213PS ymm ymm k ymm +// VFMADDSUB213PS m512 zmm k zmm +// VFMADDSUB213PS m512 zmm zmm +// VFMADDSUB213PS zmm zmm k zmm +// VFMADDSUB213PS zmm zmm zmm +// Construct and append a VFMADDSUB213PS instruction to the active function. +// Operates on the global context. +func VFMADDSUB213PS(ops ...operand.Op) { ctx.VFMADDSUB213PS(ops...) } + +// VFMADDSUB213PS_BCST: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADDSUB213PS.BCST m32 xmm k xmm +// VFMADDSUB213PS.BCST m32 xmm xmm +// VFMADDSUB213PS.BCST m32 ymm k ymm +// VFMADDSUB213PS.BCST m32 ymm ymm +// VFMADDSUB213PS.BCST m32 zmm k zmm +// VFMADDSUB213PS.BCST m32 zmm zmm +// Construct and append a VFMADDSUB213PS.BCST instruction to the active function. +func (c *Context) VFMADDSUB213PS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB213PS_BCST(ops...)) +} + +// VFMADDSUB213PS_BCST: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADDSUB213PS.BCST m32 xmm k xmm +// VFMADDSUB213PS.BCST m32 xmm xmm +// VFMADDSUB213PS.BCST m32 ymm k ymm +// VFMADDSUB213PS.BCST m32 ymm ymm +// VFMADDSUB213PS.BCST m32 zmm k zmm +// VFMADDSUB213PS.BCST m32 zmm zmm +// Construct and append a VFMADDSUB213PS.BCST instruction to the active function. +// Operates on the global context. +func VFMADDSUB213PS_BCST(ops ...operand.Op) { ctx.VFMADDSUB213PS_BCST(ops...) } + +// VFMADDSUB213PS_BCST_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PS.BCST.Z m32 xmm k xmm +// VFMADDSUB213PS.BCST.Z m32 ymm k ymm +// VFMADDSUB213PS.BCST.Z m32 zmm k zmm +// Construct and append a VFMADDSUB213PS.BCST.Z instruction to the active function. +func (c *Context) VFMADDSUB213PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMADDSUB213PS_BCST_Z(m, xyz, k, xyz1)) +} + +// VFMADDSUB213PS_BCST_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PS.BCST.Z m32 xmm k xmm +// VFMADDSUB213PS.BCST.Z m32 ymm k ymm +// VFMADDSUB213PS.BCST.Z m32 zmm k zmm +// Construct and append a VFMADDSUB213PS.BCST.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB213PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFMADDSUB213PS_BCST_Z(m, xyz, k, xyz1) } + +// VFMADDSUB213PS_RD_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADDSUB213PS.RD_SAE zmm zmm k zmm +// VFMADDSUB213PS.RD_SAE zmm zmm zmm +// Construct and append a VFMADDSUB213PS.RD_SAE instruction to the active function. +func (c *Context) VFMADDSUB213PS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB213PS_RD_SAE(ops...)) +} + +// VFMADDSUB213PS_RD_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADDSUB213PS.RD_SAE zmm zmm k zmm +// VFMADDSUB213PS.RD_SAE zmm zmm zmm +// Construct and append a VFMADDSUB213PS.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMADDSUB213PS_RD_SAE(ops ...operand.Op) { ctx.VFMADDSUB213PS_RD_SAE(ops...) } + +// VFMADDSUB213PS_RD_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB213PS.RD_SAE.Z instruction to the active function. +func (c *Context) VFMADDSUB213PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADDSUB213PS_RD_SAE_Z(z, z1, k, z2)) +} + +// VFMADDSUB213PS_RD_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB213PS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB213PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADDSUB213PS_RD_SAE_Z(z, z1, k, z2) } + +// VFMADDSUB213PS_RN_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADDSUB213PS.RN_SAE zmm zmm k zmm +// VFMADDSUB213PS.RN_SAE zmm zmm zmm +// Construct and append a VFMADDSUB213PS.RN_SAE instruction to the active function. +func (c *Context) VFMADDSUB213PS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB213PS_RN_SAE(ops...)) +} + +// VFMADDSUB213PS_RN_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADDSUB213PS.RN_SAE zmm zmm k zmm +// VFMADDSUB213PS.RN_SAE zmm zmm zmm +// Construct and append a VFMADDSUB213PS.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMADDSUB213PS_RN_SAE(ops ...operand.Op) { ctx.VFMADDSUB213PS_RN_SAE(ops...) } + +// VFMADDSUB213PS_RN_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB213PS.RN_SAE.Z instruction to the active function. +func (c *Context) VFMADDSUB213PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADDSUB213PS_RN_SAE_Z(z, z1, k, z2)) +} + +// VFMADDSUB213PS_RN_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB213PS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB213PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADDSUB213PS_RN_SAE_Z(z, z1, k, z2) } + +// VFMADDSUB213PS_RU_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADDSUB213PS.RU_SAE zmm zmm k zmm +// VFMADDSUB213PS.RU_SAE zmm zmm zmm +// Construct and append a VFMADDSUB213PS.RU_SAE instruction to the active function. +func (c *Context) VFMADDSUB213PS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB213PS_RU_SAE(ops...)) +} + +// VFMADDSUB213PS_RU_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADDSUB213PS.RU_SAE zmm zmm k zmm +// VFMADDSUB213PS.RU_SAE zmm zmm zmm +// Construct and append a VFMADDSUB213PS.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMADDSUB213PS_RU_SAE(ops ...operand.Op) { ctx.VFMADDSUB213PS_RU_SAE(ops...) } + +// VFMADDSUB213PS_RU_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB213PS.RU_SAE.Z instruction to the active function. +func (c *Context) VFMADDSUB213PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADDSUB213PS_RU_SAE_Z(z, z1, k, z2)) +} + +// VFMADDSUB213PS_RU_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB213PS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB213PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADDSUB213PS_RU_SAE_Z(z, z1, k, z2) } + +// VFMADDSUB213PS_RZ_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADDSUB213PS.RZ_SAE zmm zmm k zmm +// VFMADDSUB213PS.RZ_SAE zmm zmm zmm +// Construct and append a VFMADDSUB213PS.RZ_SAE instruction to the active function. +func (c *Context) VFMADDSUB213PS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB213PS_RZ_SAE(ops...)) +} + +// VFMADDSUB213PS_RZ_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADDSUB213PS.RZ_SAE zmm zmm k zmm +// VFMADDSUB213PS.RZ_SAE zmm zmm zmm +// Construct and append a VFMADDSUB213PS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMADDSUB213PS_RZ_SAE(ops ...operand.Op) { ctx.VFMADDSUB213PS_RZ_SAE(ops...) } + +// VFMADDSUB213PS_RZ_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB213PS.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMADDSUB213PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADDSUB213PS_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFMADDSUB213PS_RZ_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB213PS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB213PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADDSUB213PS_RZ_SAE_Z(z, z1, k, z2) } + +// VFMADDSUB213PS_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PS.Z m128 xmm k xmm +// VFMADDSUB213PS.Z m256 ymm k ymm +// VFMADDSUB213PS.Z xmm xmm k xmm +// VFMADDSUB213PS.Z ymm ymm k ymm +// VFMADDSUB213PS.Z m512 zmm k zmm +// VFMADDSUB213PS.Z zmm zmm k zmm +// Construct and append a VFMADDSUB213PS.Z instruction to the active function. +func (c *Context) VFMADDSUB213PS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMADDSUB213PS_Z(mxyz, xyz, k, xyz1)) +} + +// VFMADDSUB213PS_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PS.Z m128 xmm k xmm +// VFMADDSUB213PS.Z m256 ymm k ymm +// VFMADDSUB213PS.Z xmm xmm k xmm +// VFMADDSUB213PS.Z ymm ymm k ymm +// VFMADDSUB213PS.Z m512 zmm k zmm +// VFMADDSUB213PS.Z zmm zmm k zmm +// Construct and append a VFMADDSUB213PS.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB213PS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFMADDSUB213PS_Z(mxyz, xyz, k, xyz1) } + +// VFMADDSUB231PD: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMADDSUB231PD m128 xmm xmm +// VFMADDSUB231PD m256 ymm ymm +// VFMADDSUB231PD xmm xmm xmm +// VFMADDSUB231PD ymm ymm ymm +// VFMADDSUB231PD m128 xmm k xmm +// VFMADDSUB231PD m256 ymm k ymm +// VFMADDSUB231PD xmm xmm k xmm +// VFMADDSUB231PD ymm ymm k ymm +// VFMADDSUB231PD m512 zmm k zmm +// VFMADDSUB231PD m512 zmm zmm +// VFMADDSUB231PD zmm zmm k zmm +// VFMADDSUB231PD zmm zmm zmm +// Construct and append a VFMADDSUB231PD instruction to the active function. +func (c *Context) VFMADDSUB231PD(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB231PD(ops...)) +} + +// VFMADDSUB231PD: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMADDSUB231PD m128 xmm xmm +// VFMADDSUB231PD m256 ymm ymm +// VFMADDSUB231PD xmm xmm xmm +// VFMADDSUB231PD ymm ymm ymm +// VFMADDSUB231PD m128 xmm k xmm +// VFMADDSUB231PD m256 ymm k ymm +// VFMADDSUB231PD xmm xmm k xmm +// VFMADDSUB231PD ymm ymm k ymm +// VFMADDSUB231PD m512 zmm k zmm +// VFMADDSUB231PD m512 zmm zmm +// VFMADDSUB231PD zmm zmm k zmm +// VFMADDSUB231PD zmm zmm zmm +// Construct and append a VFMADDSUB231PD instruction to the active function. +// Operates on the global context. +func VFMADDSUB231PD(ops ...operand.Op) { ctx.VFMADDSUB231PD(ops...) } + +// VFMADDSUB231PD_BCST: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADDSUB231PD.BCST m64 xmm k xmm +// VFMADDSUB231PD.BCST m64 xmm xmm +// VFMADDSUB231PD.BCST m64 ymm k ymm +// VFMADDSUB231PD.BCST m64 ymm ymm +// VFMADDSUB231PD.BCST m64 zmm k zmm +// VFMADDSUB231PD.BCST m64 zmm zmm +// Construct and append a VFMADDSUB231PD.BCST instruction to the active function. +func (c *Context) VFMADDSUB231PD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB231PD_BCST(ops...)) +} + +// VFMADDSUB231PD_BCST: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADDSUB231PD.BCST m64 xmm k xmm +// VFMADDSUB231PD.BCST m64 xmm xmm +// VFMADDSUB231PD.BCST m64 ymm k ymm +// VFMADDSUB231PD.BCST m64 ymm ymm +// VFMADDSUB231PD.BCST m64 zmm k zmm +// VFMADDSUB231PD.BCST m64 zmm zmm +// Construct and append a VFMADDSUB231PD.BCST instruction to the active function. +// Operates on the global context. +func VFMADDSUB231PD_BCST(ops ...operand.Op) { ctx.VFMADDSUB231PD_BCST(ops...) } + +// VFMADDSUB231PD_BCST_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PD.BCST.Z m64 xmm k xmm +// VFMADDSUB231PD.BCST.Z m64 ymm k ymm +// VFMADDSUB231PD.BCST.Z m64 zmm k zmm +// Construct and append a VFMADDSUB231PD.BCST.Z instruction to the active function. +func (c *Context) VFMADDSUB231PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMADDSUB231PD_BCST_Z(m, xyz, k, xyz1)) +} + +// VFMADDSUB231PD_BCST_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PD.BCST.Z m64 xmm k xmm +// VFMADDSUB231PD.BCST.Z m64 ymm k ymm +// VFMADDSUB231PD.BCST.Z m64 zmm k zmm +// Construct and append a VFMADDSUB231PD.BCST.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB231PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFMADDSUB231PD_BCST_Z(m, xyz, k, xyz1) } + +// VFMADDSUB231PD_RD_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADDSUB231PD.RD_SAE zmm zmm k zmm +// VFMADDSUB231PD.RD_SAE zmm zmm zmm +// Construct and append a VFMADDSUB231PD.RD_SAE instruction to the active function. +func (c *Context) VFMADDSUB231PD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB231PD_RD_SAE(ops...)) +} + +// VFMADDSUB231PD_RD_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADDSUB231PD.RD_SAE zmm zmm k zmm +// VFMADDSUB231PD.RD_SAE zmm zmm zmm +// Construct and append a VFMADDSUB231PD.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMADDSUB231PD_RD_SAE(ops ...operand.Op) { ctx.VFMADDSUB231PD_RD_SAE(ops...) } + +// VFMADDSUB231PD_RD_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB231PD.RD_SAE.Z instruction to the active function. +func (c *Context) VFMADDSUB231PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADDSUB231PD_RD_SAE_Z(z, z1, k, z2)) +} + +// VFMADDSUB231PD_RD_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB231PD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB231PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADDSUB231PD_RD_SAE_Z(z, z1, k, z2) } + +// VFMADDSUB231PD_RN_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADDSUB231PD.RN_SAE zmm zmm k zmm +// VFMADDSUB231PD.RN_SAE zmm zmm zmm +// Construct and append a VFMADDSUB231PD.RN_SAE instruction to the active function. +func (c *Context) VFMADDSUB231PD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB231PD_RN_SAE(ops...)) +} + +// VFMADDSUB231PD_RN_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADDSUB231PD.RN_SAE zmm zmm k zmm +// VFMADDSUB231PD.RN_SAE zmm zmm zmm +// Construct and append a VFMADDSUB231PD.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMADDSUB231PD_RN_SAE(ops ...operand.Op) { ctx.VFMADDSUB231PD_RN_SAE(ops...) } + +// VFMADDSUB231PD_RN_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB231PD.RN_SAE.Z instruction to the active function. +func (c *Context) VFMADDSUB231PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADDSUB231PD_RN_SAE_Z(z, z1, k, z2)) +} + +// VFMADDSUB231PD_RN_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB231PD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB231PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADDSUB231PD_RN_SAE_Z(z, z1, k, z2) } + +// VFMADDSUB231PD_RU_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADDSUB231PD.RU_SAE zmm zmm k zmm +// VFMADDSUB231PD.RU_SAE zmm zmm zmm +// Construct and append a VFMADDSUB231PD.RU_SAE instruction to the active function. +func (c *Context) VFMADDSUB231PD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB231PD_RU_SAE(ops...)) +} + +// VFMADDSUB231PD_RU_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADDSUB231PD.RU_SAE zmm zmm k zmm +// VFMADDSUB231PD.RU_SAE zmm zmm zmm +// Construct and append a VFMADDSUB231PD.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMADDSUB231PD_RU_SAE(ops ...operand.Op) { ctx.VFMADDSUB231PD_RU_SAE(ops...) } + +// VFMADDSUB231PD_RU_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB231PD.RU_SAE.Z instruction to the active function. +func (c *Context) VFMADDSUB231PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADDSUB231PD_RU_SAE_Z(z, z1, k, z2)) +} + +// VFMADDSUB231PD_RU_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB231PD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB231PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADDSUB231PD_RU_SAE_Z(z, z1, k, z2) } + +// VFMADDSUB231PD_RZ_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADDSUB231PD.RZ_SAE zmm zmm k zmm +// VFMADDSUB231PD.RZ_SAE zmm zmm zmm +// Construct and append a VFMADDSUB231PD.RZ_SAE instruction to the active function. +func (c *Context) VFMADDSUB231PD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB231PD_RZ_SAE(ops...)) +} + +// VFMADDSUB231PD_RZ_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADDSUB231PD.RZ_SAE zmm zmm k zmm +// VFMADDSUB231PD.RZ_SAE zmm zmm zmm +// Construct and append a VFMADDSUB231PD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMADDSUB231PD_RZ_SAE(ops ...operand.Op) { ctx.VFMADDSUB231PD_RZ_SAE(ops...) } + +// VFMADDSUB231PD_RZ_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB231PD.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMADDSUB231PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADDSUB231PD_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFMADDSUB231PD_RZ_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB231PD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB231PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADDSUB231PD_RZ_SAE_Z(z, z1, k, z2) } + +// VFMADDSUB231PD_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PD.Z m128 xmm k xmm +// VFMADDSUB231PD.Z m256 ymm k ymm +// VFMADDSUB231PD.Z xmm xmm k xmm +// VFMADDSUB231PD.Z ymm ymm k ymm +// VFMADDSUB231PD.Z m512 zmm k zmm +// VFMADDSUB231PD.Z zmm zmm k zmm +// Construct and append a VFMADDSUB231PD.Z instruction to the active function. +func (c *Context) VFMADDSUB231PD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMADDSUB231PD_Z(mxyz, xyz, k, xyz1)) +} + +// VFMADDSUB231PD_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PD.Z m128 xmm k xmm +// VFMADDSUB231PD.Z m256 ymm k ymm +// VFMADDSUB231PD.Z xmm xmm k xmm +// VFMADDSUB231PD.Z ymm ymm k ymm +// VFMADDSUB231PD.Z m512 zmm k zmm +// VFMADDSUB231PD.Z zmm zmm k zmm +// Construct and append a VFMADDSUB231PD.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB231PD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFMADDSUB231PD_Z(mxyz, xyz, k, xyz1) } + +// VFMADDSUB231PS: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMADDSUB231PS m128 xmm xmm +// VFMADDSUB231PS m256 ymm ymm +// VFMADDSUB231PS xmm xmm xmm +// VFMADDSUB231PS ymm ymm ymm +// VFMADDSUB231PS m128 xmm k xmm +// VFMADDSUB231PS m256 ymm k ymm +// VFMADDSUB231PS xmm xmm k xmm +// VFMADDSUB231PS ymm ymm k ymm +// VFMADDSUB231PS m512 zmm k zmm +// VFMADDSUB231PS m512 zmm zmm +// VFMADDSUB231PS zmm zmm k zmm +// VFMADDSUB231PS zmm zmm zmm +// Construct and append a VFMADDSUB231PS instruction to the active function. +func (c *Context) VFMADDSUB231PS(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB231PS(ops...)) +} + +// VFMADDSUB231PS: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMADDSUB231PS m128 xmm xmm +// VFMADDSUB231PS m256 ymm ymm +// VFMADDSUB231PS xmm xmm xmm +// VFMADDSUB231PS ymm ymm ymm +// VFMADDSUB231PS m128 xmm k xmm +// VFMADDSUB231PS m256 ymm k ymm +// VFMADDSUB231PS xmm xmm k xmm +// VFMADDSUB231PS ymm ymm k ymm +// VFMADDSUB231PS m512 zmm k zmm +// VFMADDSUB231PS m512 zmm zmm +// VFMADDSUB231PS zmm zmm k zmm +// VFMADDSUB231PS zmm zmm zmm +// Construct and append a VFMADDSUB231PS instruction to the active function. +// Operates on the global context. +func VFMADDSUB231PS(ops ...operand.Op) { ctx.VFMADDSUB231PS(ops...) } + +// VFMADDSUB231PS_BCST: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADDSUB231PS.BCST m32 xmm k xmm +// VFMADDSUB231PS.BCST m32 xmm xmm +// VFMADDSUB231PS.BCST m32 ymm k ymm +// VFMADDSUB231PS.BCST m32 ymm ymm +// VFMADDSUB231PS.BCST m32 zmm k zmm +// VFMADDSUB231PS.BCST m32 zmm zmm +// Construct and append a VFMADDSUB231PS.BCST instruction to the active function. +func (c *Context) VFMADDSUB231PS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB231PS_BCST(ops...)) +} + +// VFMADDSUB231PS_BCST: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADDSUB231PS.BCST m32 xmm k xmm +// VFMADDSUB231PS.BCST m32 xmm xmm +// VFMADDSUB231PS.BCST m32 ymm k ymm +// VFMADDSUB231PS.BCST m32 ymm ymm +// VFMADDSUB231PS.BCST m32 zmm k zmm +// VFMADDSUB231PS.BCST m32 zmm zmm +// Construct and append a VFMADDSUB231PS.BCST instruction to the active function. +// Operates on the global context. +func VFMADDSUB231PS_BCST(ops ...operand.Op) { ctx.VFMADDSUB231PS_BCST(ops...) } + +// VFMADDSUB231PS_BCST_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PS.BCST.Z m32 xmm k xmm +// VFMADDSUB231PS.BCST.Z m32 ymm k ymm +// VFMADDSUB231PS.BCST.Z m32 zmm k zmm +// Construct and append a VFMADDSUB231PS.BCST.Z instruction to the active function. +func (c *Context) VFMADDSUB231PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMADDSUB231PS_BCST_Z(m, xyz, k, xyz1)) +} + +// VFMADDSUB231PS_BCST_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PS.BCST.Z m32 xmm k xmm +// VFMADDSUB231PS.BCST.Z m32 ymm k ymm +// VFMADDSUB231PS.BCST.Z m32 zmm k zmm +// Construct and append a VFMADDSUB231PS.BCST.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB231PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFMADDSUB231PS_BCST_Z(m, xyz, k, xyz1) } + +// VFMADDSUB231PS_RD_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADDSUB231PS.RD_SAE zmm zmm k zmm +// VFMADDSUB231PS.RD_SAE zmm zmm zmm +// Construct and append a VFMADDSUB231PS.RD_SAE instruction to the active function. +func (c *Context) VFMADDSUB231PS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB231PS_RD_SAE(ops...)) +} + +// VFMADDSUB231PS_RD_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADDSUB231PS.RD_SAE zmm zmm k zmm +// VFMADDSUB231PS.RD_SAE zmm zmm zmm +// Construct and append a VFMADDSUB231PS.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMADDSUB231PS_RD_SAE(ops ...operand.Op) { ctx.VFMADDSUB231PS_RD_SAE(ops...) } + +// VFMADDSUB231PS_RD_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB231PS.RD_SAE.Z instruction to the active function. +func (c *Context) VFMADDSUB231PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADDSUB231PS_RD_SAE_Z(z, z1, k, z2)) +} + +// VFMADDSUB231PS_RD_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB231PS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB231PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADDSUB231PS_RD_SAE_Z(z, z1, k, z2) } + +// VFMADDSUB231PS_RN_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADDSUB231PS.RN_SAE zmm zmm k zmm +// VFMADDSUB231PS.RN_SAE zmm zmm zmm +// Construct and append a VFMADDSUB231PS.RN_SAE instruction to the active function. +func (c *Context) VFMADDSUB231PS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB231PS_RN_SAE(ops...)) +} + +// VFMADDSUB231PS_RN_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADDSUB231PS.RN_SAE zmm zmm k zmm +// VFMADDSUB231PS.RN_SAE zmm zmm zmm +// Construct and append a VFMADDSUB231PS.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMADDSUB231PS_RN_SAE(ops ...operand.Op) { ctx.VFMADDSUB231PS_RN_SAE(ops...) } + +// VFMADDSUB231PS_RN_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB231PS.RN_SAE.Z instruction to the active function. +func (c *Context) VFMADDSUB231PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADDSUB231PS_RN_SAE_Z(z, z1, k, z2)) +} + +// VFMADDSUB231PS_RN_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB231PS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB231PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADDSUB231PS_RN_SAE_Z(z, z1, k, z2) } + +// VFMADDSUB231PS_RU_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADDSUB231PS.RU_SAE zmm zmm k zmm +// VFMADDSUB231PS.RU_SAE zmm zmm zmm +// Construct and append a VFMADDSUB231PS.RU_SAE instruction to the active function. +func (c *Context) VFMADDSUB231PS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB231PS_RU_SAE(ops...)) +} + +// VFMADDSUB231PS_RU_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADDSUB231PS.RU_SAE zmm zmm k zmm +// VFMADDSUB231PS.RU_SAE zmm zmm zmm +// Construct and append a VFMADDSUB231PS.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMADDSUB231PS_RU_SAE(ops ...operand.Op) { ctx.VFMADDSUB231PS_RU_SAE(ops...) } + +// VFMADDSUB231PS_RU_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB231PS.RU_SAE.Z instruction to the active function. +func (c *Context) VFMADDSUB231PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADDSUB231PS_RU_SAE_Z(z, z1, k, z2)) +} + +// VFMADDSUB231PS_RU_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB231PS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB231PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADDSUB231PS_RU_SAE_Z(z, z1, k, z2) } + +// VFMADDSUB231PS_RZ_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADDSUB231PS.RZ_SAE zmm zmm k zmm +// VFMADDSUB231PS.RZ_SAE zmm zmm zmm +// Construct and append a VFMADDSUB231PS.RZ_SAE instruction to the active function. +func (c *Context) VFMADDSUB231PS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMADDSUB231PS_RZ_SAE(ops...)) +} + +// VFMADDSUB231PS_RZ_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADDSUB231PS.RZ_SAE zmm zmm k zmm +// VFMADDSUB231PS.RZ_SAE zmm zmm zmm +// Construct and append a VFMADDSUB231PS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMADDSUB231PS_RZ_SAE(ops ...operand.Op) { ctx.VFMADDSUB231PS_RZ_SAE(ops...) } + +// VFMADDSUB231PS_RZ_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB231PS.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMADDSUB231PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMADDSUB231PS_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFMADDSUB231PS_RZ_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMADDSUB231PS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB231PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMADDSUB231PS_RZ_SAE_Z(z, z1, k, z2) } + +// VFMADDSUB231PS_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PS.Z m128 xmm k xmm +// VFMADDSUB231PS.Z m256 ymm k ymm +// VFMADDSUB231PS.Z xmm xmm k xmm +// VFMADDSUB231PS.Z ymm ymm k ymm +// VFMADDSUB231PS.Z m512 zmm k zmm +// VFMADDSUB231PS.Z zmm zmm k zmm +// Construct and append a VFMADDSUB231PS.Z instruction to the active function. +func (c *Context) VFMADDSUB231PS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMADDSUB231PS_Z(mxyz, xyz, k, xyz1)) +} + +// VFMADDSUB231PS_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PS.Z m128 xmm k xmm +// VFMADDSUB231PS.Z m256 ymm k ymm +// VFMADDSUB231PS.Z xmm xmm k xmm +// VFMADDSUB231PS.Z ymm ymm k ymm +// VFMADDSUB231PS.Z m512 zmm k zmm +// VFMADDSUB231PS.Z zmm zmm k zmm +// Construct and append a VFMADDSUB231PS.Z instruction to the active function. +// Operates on the global context. +func VFMADDSUB231PS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFMADDSUB231PS_Z(mxyz, xyz, k, xyz1) } + +// VFMSUB132PD: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB132PD m128 xmm xmm +// VFMSUB132PD m256 ymm ymm +// VFMSUB132PD xmm xmm xmm +// VFMSUB132PD ymm ymm ymm +// VFMSUB132PD m128 xmm k xmm +// VFMSUB132PD m256 ymm k ymm +// VFMSUB132PD xmm xmm k xmm +// VFMSUB132PD ymm ymm k ymm +// VFMSUB132PD m512 zmm k zmm +// VFMSUB132PD m512 zmm zmm +// VFMSUB132PD zmm zmm k zmm +// VFMSUB132PD zmm zmm zmm +// Construct and append a VFMSUB132PD instruction to the active function. +func (c *Context) VFMSUB132PD(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB132PD(ops...)) +} + +// VFMSUB132PD: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB132PD m128 xmm xmm +// VFMSUB132PD m256 ymm ymm +// VFMSUB132PD xmm xmm xmm +// VFMSUB132PD ymm ymm ymm +// VFMSUB132PD m128 xmm k xmm +// VFMSUB132PD m256 ymm k ymm +// VFMSUB132PD xmm xmm k xmm +// VFMSUB132PD ymm ymm k ymm +// VFMSUB132PD m512 zmm k zmm +// VFMSUB132PD m512 zmm zmm +// VFMSUB132PD zmm zmm k zmm +// VFMSUB132PD zmm zmm zmm +// Construct and append a VFMSUB132PD instruction to the active function. +// Operates on the global context. +func VFMSUB132PD(ops ...operand.Op) { ctx.VFMSUB132PD(ops...) } + +// VFMSUB132PD_BCST: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUB132PD.BCST m64 xmm k xmm +// VFMSUB132PD.BCST m64 xmm xmm +// VFMSUB132PD.BCST m64 ymm k ymm +// VFMSUB132PD.BCST m64 ymm ymm +// VFMSUB132PD.BCST m64 zmm k zmm +// VFMSUB132PD.BCST m64 zmm zmm +// Construct and append a VFMSUB132PD.BCST instruction to the active function. +func (c *Context) VFMSUB132PD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB132PD_BCST(ops...)) +} + +// VFMSUB132PD_BCST: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUB132PD.BCST m64 xmm k xmm +// VFMSUB132PD.BCST m64 xmm xmm +// VFMSUB132PD.BCST m64 ymm k ymm +// VFMSUB132PD.BCST m64 ymm ymm +// VFMSUB132PD.BCST m64 zmm k zmm +// VFMSUB132PD.BCST m64 zmm zmm +// Construct and append a VFMSUB132PD.BCST instruction to the active function. +// Operates on the global context. +func VFMSUB132PD_BCST(ops ...operand.Op) { ctx.VFMSUB132PD_BCST(ops...) } + +// VFMSUB132PD_BCST_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUB132PD.BCST.Z m64 xmm k xmm +// VFMSUB132PD.BCST.Z m64 ymm k ymm +// VFMSUB132PD.BCST.Z m64 zmm k zmm +// Construct and append a VFMSUB132PD.BCST.Z instruction to the active function. +func (c *Context) VFMSUB132PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMSUB132PD_BCST_Z(m, xyz, k, xyz1)) +} + +// VFMSUB132PD_BCST_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUB132PD.BCST.Z m64 xmm k xmm +// VFMSUB132PD.BCST.Z m64 ymm k ymm +// VFMSUB132PD.BCST.Z m64 zmm k zmm +// Construct and append a VFMSUB132PD.BCST.Z instruction to the active function. +// Operates on the global context. +func VFMSUB132PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFMSUB132PD_BCST_Z(m, xyz, k, xyz1) } + +// VFMSUB132PD_RD_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB132PD.RD_SAE zmm zmm k zmm +// VFMSUB132PD.RD_SAE zmm zmm zmm +// Construct and append a VFMSUB132PD.RD_SAE instruction to the active function. +func (c *Context) VFMSUB132PD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB132PD_RD_SAE(ops...)) +} + +// VFMSUB132PD_RD_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB132PD.RD_SAE zmm zmm k zmm +// VFMSUB132PD.RD_SAE zmm zmm zmm +// Construct and append a VFMSUB132PD.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB132PD_RD_SAE(ops ...operand.Op) { ctx.VFMSUB132PD_RD_SAE(ops...) } + +// VFMSUB132PD_RD_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB132PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB132PD.RD_SAE.Z instruction to the active function. +func (c *Context) VFMSUB132PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUB132PD_RD_SAE_Z(z, z1, k, z2)) +} + +// VFMSUB132PD_RD_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB132PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB132PD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB132PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUB132PD_RD_SAE_Z(z, z1, k, z2) } + +// VFMSUB132PD_RN_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB132PD.RN_SAE zmm zmm k zmm +// VFMSUB132PD.RN_SAE zmm zmm zmm +// Construct and append a VFMSUB132PD.RN_SAE instruction to the active function. +func (c *Context) VFMSUB132PD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB132PD_RN_SAE(ops...)) +} + +// VFMSUB132PD_RN_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB132PD.RN_SAE zmm zmm k zmm +// VFMSUB132PD.RN_SAE zmm zmm zmm +// Construct and append a VFMSUB132PD.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB132PD_RN_SAE(ops ...operand.Op) { ctx.VFMSUB132PD_RN_SAE(ops...) } + +// VFMSUB132PD_RN_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB132PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB132PD.RN_SAE.Z instruction to the active function. +func (c *Context) VFMSUB132PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUB132PD_RN_SAE_Z(z, z1, k, z2)) +} + +// VFMSUB132PD_RN_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB132PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB132PD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB132PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUB132PD_RN_SAE_Z(z, z1, k, z2) } + +// VFMSUB132PD_RU_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB132PD.RU_SAE zmm zmm k zmm +// VFMSUB132PD.RU_SAE zmm zmm zmm +// Construct and append a VFMSUB132PD.RU_SAE instruction to the active function. +func (c *Context) VFMSUB132PD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB132PD_RU_SAE(ops...)) +} + +// VFMSUB132PD_RU_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB132PD.RU_SAE zmm zmm k zmm +// VFMSUB132PD.RU_SAE zmm zmm zmm +// Construct and append a VFMSUB132PD.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB132PD_RU_SAE(ops ...operand.Op) { ctx.VFMSUB132PD_RU_SAE(ops...) } + +// VFMSUB132PD_RU_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB132PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB132PD.RU_SAE.Z instruction to the active function. +func (c *Context) VFMSUB132PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUB132PD_RU_SAE_Z(z, z1, k, z2)) +} + +// VFMSUB132PD_RU_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB132PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB132PD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB132PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUB132PD_RU_SAE_Z(z, z1, k, z2) } + +// VFMSUB132PD_RZ_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB132PD.RZ_SAE zmm zmm k zmm +// VFMSUB132PD.RZ_SAE zmm zmm zmm +// Construct and append a VFMSUB132PD.RZ_SAE instruction to the active function. +func (c *Context) VFMSUB132PD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB132PD_RZ_SAE(ops...)) +} + +// VFMSUB132PD_RZ_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB132PD.RZ_SAE zmm zmm k zmm +// VFMSUB132PD.RZ_SAE zmm zmm zmm +// Construct and append a VFMSUB132PD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB132PD_RZ_SAE(ops ...operand.Op) { ctx.VFMSUB132PD_RZ_SAE(ops...) } + +// VFMSUB132PD_RZ_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB132PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB132PD.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMSUB132PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUB132PD_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFMSUB132PD_RZ_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB132PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB132PD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB132PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUB132PD_RZ_SAE_Z(z, z1, k, z2) } + +// VFMSUB132PD_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB132PD.Z m128 xmm k xmm +// VFMSUB132PD.Z m256 ymm k ymm +// VFMSUB132PD.Z xmm xmm k xmm +// VFMSUB132PD.Z ymm ymm k ymm +// VFMSUB132PD.Z m512 zmm k zmm +// VFMSUB132PD.Z zmm zmm k zmm +// Construct and append a VFMSUB132PD.Z instruction to the active function. +func (c *Context) VFMSUB132PD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMSUB132PD_Z(mxyz, xyz, k, xyz1)) +} + +// VFMSUB132PD_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB132PD.Z m128 xmm k xmm +// VFMSUB132PD.Z m256 ymm k ymm +// VFMSUB132PD.Z xmm xmm k xmm +// VFMSUB132PD.Z ymm ymm k ymm +// VFMSUB132PD.Z m512 zmm k zmm +// VFMSUB132PD.Z zmm zmm k zmm +// Construct and append a VFMSUB132PD.Z instruction to the active function. +// Operates on the global context. +func VFMSUB132PD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFMSUB132PD_Z(mxyz, xyz, k, xyz1) } + +// VFMSUB132PS: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB132PS m128 xmm xmm +// VFMSUB132PS m256 ymm ymm +// VFMSUB132PS xmm xmm xmm +// VFMSUB132PS ymm ymm ymm +// VFMSUB132PS m128 xmm k xmm +// VFMSUB132PS m256 ymm k ymm +// VFMSUB132PS xmm xmm k xmm +// VFMSUB132PS ymm ymm k ymm +// VFMSUB132PS m512 zmm k zmm +// VFMSUB132PS m512 zmm zmm +// VFMSUB132PS zmm zmm k zmm +// VFMSUB132PS zmm zmm zmm +// Construct and append a VFMSUB132PS instruction to the active function. +func (c *Context) VFMSUB132PS(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB132PS(ops...)) +} + +// VFMSUB132PS: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB132PS m128 xmm xmm +// VFMSUB132PS m256 ymm ymm +// VFMSUB132PS xmm xmm xmm +// VFMSUB132PS ymm ymm ymm +// VFMSUB132PS m128 xmm k xmm +// VFMSUB132PS m256 ymm k ymm +// VFMSUB132PS xmm xmm k xmm +// VFMSUB132PS ymm ymm k ymm +// VFMSUB132PS m512 zmm k zmm +// VFMSUB132PS m512 zmm zmm +// VFMSUB132PS zmm zmm k zmm +// VFMSUB132PS zmm zmm zmm +// Construct and append a VFMSUB132PS instruction to the active function. +// Operates on the global context. +func VFMSUB132PS(ops ...operand.Op) { ctx.VFMSUB132PS(ops...) } + +// VFMSUB132PS_BCST: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUB132PS.BCST m32 xmm k xmm +// VFMSUB132PS.BCST m32 xmm xmm +// VFMSUB132PS.BCST m32 ymm k ymm +// VFMSUB132PS.BCST m32 ymm ymm +// VFMSUB132PS.BCST m32 zmm k zmm +// VFMSUB132PS.BCST m32 zmm zmm +// Construct and append a VFMSUB132PS.BCST instruction to the active function. +func (c *Context) VFMSUB132PS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB132PS_BCST(ops...)) +} + +// VFMSUB132PS_BCST: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUB132PS.BCST m32 xmm k xmm +// VFMSUB132PS.BCST m32 xmm xmm +// VFMSUB132PS.BCST m32 ymm k ymm +// VFMSUB132PS.BCST m32 ymm ymm +// VFMSUB132PS.BCST m32 zmm k zmm +// VFMSUB132PS.BCST m32 zmm zmm +// Construct and append a VFMSUB132PS.BCST instruction to the active function. +// Operates on the global context. +func VFMSUB132PS_BCST(ops ...operand.Op) { ctx.VFMSUB132PS_BCST(ops...) } + +// VFMSUB132PS_BCST_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUB132PS.BCST.Z m32 xmm k xmm +// VFMSUB132PS.BCST.Z m32 ymm k ymm +// VFMSUB132PS.BCST.Z m32 zmm k zmm +// Construct and append a VFMSUB132PS.BCST.Z instruction to the active function. +func (c *Context) VFMSUB132PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMSUB132PS_BCST_Z(m, xyz, k, xyz1)) +} + +// VFMSUB132PS_BCST_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUB132PS.BCST.Z m32 xmm k xmm +// VFMSUB132PS.BCST.Z m32 ymm k ymm +// VFMSUB132PS.BCST.Z m32 zmm k zmm +// Construct and append a VFMSUB132PS.BCST.Z instruction to the active function. +// Operates on the global context. +func VFMSUB132PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFMSUB132PS_BCST_Z(m, xyz, k, xyz1) } + +// VFMSUB132PS_RD_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB132PS.RD_SAE zmm zmm k zmm +// VFMSUB132PS.RD_SAE zmm zmm zmm +// Construct and append a VFMSUB132PS.RD_SAE instruction to the active function. +func (c *Context) VFMSUB132PS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB132PS_RD_SAE(ops...)) +} + +// VFMSUB132PS_RD_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB132PS.RD_SAE zmm zmm k zmm +// VFMSUB132PS.RD_SAE zmm zmm zmm +// Construct and append a VFMSUB132PS.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB132PS_RD_SAE(ops ...operand.Op) { ctx.VFMSUB132PS_RD_SAE(ops...) } + +// VFMSUB132PS_RD_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB132PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB132PS.RD_SAE.Z instruction to the active function. +func (c *Context) VFMSUB132PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUB132PS_RD_SAE_Z(z, z1, k, z2)) +} + +// VFMSUB132PS_RD_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB132PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB132PS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB132PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUB132PS_RD_SAE_Z(z, z1, k, z2) } + +// VFMSUB132PS_RN_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB132PS.RN_SAE zmm zmm k zmm +// VFMSUB132PS.RN_SAE zmm zmm zmm +// Construct and append a VFMSUB132PS.RN_SAE instruction to the active function. +func (c *Context) VFMSUB132PS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB132PS_RN_SAE(ops...)) +} + +// VFMSUB132PS_RN_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB132PS.RN_SAE zmm zmm k zmm +// VFMSUB132PS.RN_SAE zmm zmm zmm +// Construct and append a VFMSUB132PS.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB132PS_RN_SAE(ops ...operand.Op) { ctx.VFMSUB132PS_RN_SAE(ops...) } + +// VFMSUB132PS_RN_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB132PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB132PS.RN_SAE.Z instruction to the active function. +func (c *Context) VFMSUB132PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUB132PS_RN_SAE_Z(z, z1, k, z2)) +} + +// VFMSUB132PS_RN_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB132PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB132PS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB132PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUB132PS_RN_SAE_Z(z, z1, k, z2) } + +// VFMSUB132PS_RU_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB132PS.RU_SAE zmm zmm k zmm +// VFMSUB132PS.RU_SAE zmm zmm zmm +// Construct and append a VFMSUB132PS.RU_SAE instruction to the active function. +func (c *Context) VFMSUB132PS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB132PS_RU_SAE(ops...)) +} + +// VFMSUB132PS_RU_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB132PS.RU_SAE zmm zmm k zmm +// VFMSUB132PS.RU_SAE zmm zmm zmm +// Construct and append a VFMSUB132PS.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB132PS_RU_SAE(ops ...operand.Op) { ctx.VFMSUB132PS_RU_SAE(ops...) } + +// VFMSUB132PS_RU_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB132PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB132PS.RU_SAE.Z instruction to the active function. +func (c *Context) VFMSUB132PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUB132PS_RU_SAE_Z(z, z1, k, z2)) +} + +// VFMSUB132PS_RU_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB132PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB132PS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB132PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUB132PS_RU_SAE_Z(z, z1, k, z2) } + +// VFMSUB132PS_RZ_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB132PS.RZ_SAE zmm zmm k zmm +// VFMSUB132PS.RZ_SAE zmm zmm zmm +// Construct and append a VFMSUB132PS.RZ_SAE instruction to the active function. +func (c *Context) VFMSUB132PS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB132PS_RZ_SAE(ops...)) +} + +// VFMSUB132PS_RZ_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB132PS.RZ_SAE zmm zmm k zmm +// VFMSUB132PS.RZ_SAE zmm zmm zmm +// Construct and append a VFMSUB132PS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB132PS_RZ_SAE(ops ...operand.Op) { ctx.VFMSUB132PS_RZ_SAE(ops...) } + +// VFMSUB132PS_RZ_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB132PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB132PS.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMSUB132PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUB132PS_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFMSUB132PS_RZ_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB132PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB132PS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB132PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUB132PS_RZ_SAE_Z(z, z1, k, z2) } + +// VFMSUB132PS_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB132PS.Z m128 xmm k xmm +// VFMSUB132PS.Z m256 ymm k ymm +// VFMSUB132PS.Z xmm xmm k xmm +// VFMSUB132PS.Z ymm ymm k ymm +// VFMSUB132PS.Z m512 zmm k zmm +// VFMSUB132PS.Z zmm zmm k zmm +// Construct and append a VFMSUB132PS.Z instruction to the active function. +func (c *Context) VFMSUB132PS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMSUB132PS_Z(mxyz, xyz, k, xyz1)) +} + +// VFMSUB132PS_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB132PS.Z m128 xmm k xmm +// VFMSUB132PS.Z m256 ymm k ymm +// VFMSUB132PS.Z xmm xmm k xmm +// VFMSUB132PS.Z ymm ymm k ymm +// VFMSUB132PS.Z m512 zmm k zmm +// VFMSUB132PS.Z zmm zmm k zmm +// Construct and append a VFMSUB132PS.Z instruction to the active function. +// Operates on the global context. +func VFMSUB132PS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFMSUB132PS_Z(mxyz, xyz, k, xyz1) } + +// VFMSUB132SD: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB132SD m64 xmm xmm +// VFMSUB132SD xmm xmm xmm +// VFMSUB132SD m64 xmm k xmm +// VFMSUB132SD xmm xmm k xmm +// Construct and append a VFMSUB132SD instruction to the active function. +func (c *Context) VFMSUB132SD(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB132SD(ops...)) +} + +// VFMSUB132SD: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB132SD m64 xmm xmm +// VFMSUB132SD xmm xmm xmm +// VFMSUB132SD m64 xmm k xmm +// VFMSUB132SD xmm xmm k xmm +// Construct and append a VFMSUB132SD instruction to the active function. +// Operates on the global context. +func VFMSUB132SD(ops ...operand.Op) { ctx.VFMSUB132SD(ops...) } + +// VFMSUB132SD_RD_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB132SD.RD_SAE xmm xmm k xmm +// VFMSUB132SD.RD_SAE xmm xmm xmm +// Construct and append a VFMSUB132SD.RD_SAE instruction to the active function. +func (c *Context) VFMSUB132SD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB132SD_RD_SAE(ops...)) +} + +// VFMSUB132SD_RD_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB132SD.RD_SAE xmm xmm k xmm +// VFMSUB132SD.RD_SAE xmm xmm xmm +// Construct and append a VFMSUB132SD.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB132SD_RD_SAE(ops ...operand.Op) { ctx.VFMSUB132SD_RD_SAE(ops...) } + +// VFMSUB132SD_RD_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB132SD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB132SD.RD_SAE.Z instruction to the active function. +func (c *Context) VFMSUB132SD_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMSUB132SD_RD_SAE_Z(x, x1, k, x2)) +} + +// VFMSUB132SD_RD_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB132SD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB132SD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB132SD_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMSUB132SD_RD_SAE_Z(x, x1, k, x2) } + +// VFMSUB132SD_RN_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB132SD.RN_SAE xmm xmm k xmm +// VFMSUB132SD.RN_SAE xmm xmm xmm +// Construct and append a VFMSUB132SD.RN_SAE instruction to the active function. +func (c *Context) VFMSUB132SD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB132SD_RN_SAE(ops...)) +} + +// VFMSUB132SD_RN_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB132SD.RN_SAE xmm xmm k xmm +// VFMSUB132SD.RN_SAE xmm xmm xmm +// Construct and append a VFMSUB132SD.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB132SD_RN_SAE(ops ...operand.Op) { ctx.VFMSUB132SD_RN_SAE(ops...) } + +// VFMSUB132SD_RN_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB132SD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB132SD.RN_SAE.Z instruction to the active function. +func (c *Context) VFMSUB132SD_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMSUB132SD_RN_SAE_Z(x, x1, k, x2)) +} + +// VFMSUB132SD_RN_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB132SD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB132SD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB132SD_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMSUB132SD_RN_SAE_Z(x, x1, k, x2) } + +// VFMSUB132SD_RU_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB132SD.RU_SAE xmm xmm k xmm +// VFMSUB132SD.RU_SAE xmm xmm xmm +// Construct and append a VFMSUB132SD.RU_SAE instruction to the active function. +func (c *Context) VFMSUB132SD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB132SD_RU_SAE(ops...)) +} + +// VFMSUB132SD_RU_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB132SD.RU_SAE xmm xmm k xmm +// VFMSUB132SD.RU_SAE xmm xmm xmm +// Construct and append a VFMSUB132SD.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB132SD_RU_SAE(ops ...operand.Op) { ctx.VFMSUB132SD_RU_SAE(ops...) } + +// VFMSUB132SD_RU_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB132SD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB132SD.RU_SAE.Z instruction to the active function. +func (c *Context) VFMSUB132SD_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMSUB132SD_RU_SAE_Z(x, x1, k, x2)) +} + +// VFMSUB132SD_RU_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB132SD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB132SD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB132SD_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMSUB132SD_RU_SAE_Z(x, x1, k, x2) } + +// VFMSUB132SD_RZ_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB132SD.RZ_SAE xmm xmm k xmm +// VFMSUB132SD.RZ_SAE xmm xmm xmm +// Construct and append a VFMSUB132SD.RZ_SAE instruction to the active function. +func (c *Context) VFMSUB132SD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB132SD_RZ_SAE(ops...)) +} + +// VFMSUB132SD_RZ_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB132SD.RZ_SAE xmm xmm k xmm +// VFMSUB132SD.RZ_SAE xmm xmm xmm +// Construct and append a VFMSUB132SD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB132SD_RZ_SAE(ops ...operand.Op) { ctx.VFMSUB132SD_RZ_SAE(ops...) } + +// VFMSUB132SD_RZ_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB132SD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB132SD.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMSUB132SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMSUB132SD_RZ_SAE_Z(x, x1, k, x2)) +} + +// VFMSUB132SD_RZ_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB132SD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB132SD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB132SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMSUB132SD_RZ_SAE_Z(x, x1, k, x2) } + +// VFMSUB132SD_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB132SD.Z m64 xmm k xmm +// VFMSUB132SD.Z xmm xmm k xmm +// Construct and append a VFMSUB132SD.Z instruction to the active function. +func (c *Context) VFMSUB132SD_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VFMSUB132SD_Z(mx, x, k, x1)) +} + +// VFMSUB132SD_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB132SD.Z m64 xmm k xmm +// VFMSUB132SD.Z xmm xmm k xmm +// Construct and append a VFMSUB132SD.Z instruction to the active function. +// Operates on the global context. +func VFMSUB132SD_Z(mx, x, k, x1 operand.Op) { ctx.VFMSUB132SD_Z(mx, x, k, x1) } + +// VFMSUB132SS: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB132SS m32 xmm xmm +// VFMSUB132SS xmm xmm xmm +// VFMSUB132SS m32 xmm k xmm +// VFMSUB132SS xmm xmm k xmm +// Construct and append a VFMSUB132SS instruction to the active function. +func (c *Context) VFMSUB132SS(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB132SS(ops...)) +} + +// VFMSUB132SS: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB132SS m32 xmm xmm +// VFMSUB132SS xmm xmm xmm +// VFMSUB132SS m32 xmm k xmm +// VFMSUB132SS xmm xmm k xmm +// Construct and append a VFMSUB132SS instruction to the active function. +// Operates on the global context. +func VFMSUB132SS(ops ...operand.Op) { ctx.VFMSUB132SS(ops...) } + +// VFMSUB132SS_RD_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB132SS.RD_SAE xmm xmm k xmm +// VFMSUB132SS.RD_SAE xmm xmm xmm +// Construct and append a VFMSUB132SS.RD_SAE instruction to the active function. +func (c *Context) VFMSUB132SS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB132SS_RD_SAE(ops...)) +} + +// VFMSUB132SS_RD_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB132SS.RD_SAE xmm xmm k xmm +// VFMSUB132SS.RD_SAE xmm xmm xmm +// Construct and append a VFMSUB132SS.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB132SS_RD_SAE(ops ...operand.Op) { ctx.VFMSUB132SS_RD_SAE(ops...) } + +// VFMSUB132SS_RD_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB132SS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB132SS.RD_SAE.Z instruction to the active function. +func (c *Context) VFMSUB132SS_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMSUB132SS_RD_SAE_Z(x, x1, k, x2)) +} + +// VFMSUB132SS_RD_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB132SS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB132SS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB132SS_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMSUB132SS_RD_SAE_Z(x, x1, k, x2) } + +// VFMSUB132SS_RN_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB132SS.RN_SAE xmm xmm k xmm +// VFMSUB132SS.RN_SAE xmm xmm xmm +// Construct and append a VFMSUB132SS.RN_SAE instruction to the active function. +func (c *Context) VFMSUB132SS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB132SS_RN_SAE(ops...)) +} + +// VFMSUB132SS_RN_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB132SS.RN_SAE xmm xmm k xmm +// VFMSUB132SS.RN_SAE xmm xmm xmm +// Construct and append a VFMSUB132SS.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB132SS_RN_SAE(ops ...operand.Op) { ctx.VFMSUB132SS_RN_SAE(ops...) } + +// VFMSUB132SS_RN_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB132SS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB132SS.RN_SAE.Z instruction to the active function. +func (c *Context) VFMSUB132SS_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMSUB132SS_RN_SAE_Z(x, x1, k, x2)) +} + +// VFMSUB132SS_RN_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB132SS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB132SS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB132SS_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMSUB132SS_RN_SAE_Z(x, x1, k, x2) } + +// VFMSUB132SS_RU_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB132SS.RU_SAE xmm xmm k xmm +// VFMSUB132SS.RU_SAE xmm xmm xmm +// Construct and append a VFMSUB132SS.RU_SAE instruction to the active function. +func (c *Context) VFMSUB132SS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB132SS_RU_SAE(ops...)) +} + +// VFMSUB132SS_RU_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB132SS.RU_SAE xmm xmm k xmm +// VFMSUB132SS.RU_SAE xmm xmm xmm +// Construct and append a VFMSUB132SS.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB132SS_RU_SAE(ops ...operand.Op) { ctx.VFMSUB132SS_RU_SAE(ops...) } + +// VFMSUB132SS_RU_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB132SS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB132SS.RU_SAE.Z instruction to the active function. +func (c *Context) VFMSUB132SS_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMSUB132SS_RU_SAE_Z(x, x1, k, x2)) +} + +// VFMSUB132SS_RU_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB132SS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB132SS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB132SS_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMSUB132SS_RU_SAE_Z(x, x1, k, x2) } + +// VFMSUB132SS_RZ_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB132SS.RZ_SAE xmm xmm k xmm +// VFMSUB132SS.RZ_SAE xmm xmm xmm +// Construct and append a VFMSUB132SS.RZ_SAE instruction to the active function. +func (c *Context) VFMSUB132SS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB132SS_RZ_SAE(ops...)) +} + +// VFMSUB132SS_RZ_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB132SS.RZ_SAE xmm xmm k xmm +// VFMSUB132SS.RZ_SAE xmm xmm xmm +// Construct and append a VFMSUB132SS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB132SS_RZ_SAE(ops ...operand.Op) { ctx.VFMSUB132SS_RZ_SAE(ops...) } + +// VFMSUB132SS_RZ_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB132SS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB132SS.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMSUB132SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMSUB132SS_RZ_SAE_Z(x, x1, k, x2)) +} + +// VFMSUB132SS_RZ_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB132SS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB132SS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB132SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMSUB132SS_RZ_SAE_Z(x, x1, k, x2) } + +// VFMSUB132SS_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB132SS.Z m32 xmm k xmm +// VFMSUB132SS.Z xmm xmm k xmm +// Construct and append a VFMSUB132SS.Z instruction to the active function. +func (c *Context) VFMSUB132SS_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VFMSUB132SS_Z(mx, x, k, x1)) +} + +// VFMSUB132SS_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB132SS.Z m32 xmm k xmm +// VFMSUB132SS.Z xmm xmm k xmm +// Construct and append a VFMSUB132SS.Z instruction to the active function. +// Operates on the global context. +func VFMSUB132SS_Z(mx, x, k, x1 operand.Op) { ctx.VFMSUB132SS_Z(mx, x, k, x1) } + +// VFMSUB213PD: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB213PD m128 xmm xmm +// VFMSUB213PD m256 ymm ymm +// VFMSUB213PD xmm xmm xmm +// VFMSUB213PD ymm ymm ymm +// VFMSUB213PD m128 xmm k xmm +// VFMSUB213PD m256 ymm k ymm +// VFMSUB213PD xmm xmm k xmm +// VFMSUB213PD ymm ymm k ymm +// VFMSUB213PD m512 zmm k zmm +// VFMSUB213PD m512 zmm zmm +// VFMSUB213PD zmm zmm k zmm +// VFMSUB213PD zmm zmm zmm +// Construct and append a VFMSUB213PD instruction to the active function. +func (c *Context) VFMSUB213PD(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB213PD(ops...)) +} + +// VFMSUB213PD: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB213PD m128 xmm xmm +// VFMSUB213PD m256 ymm ymm +// VFMSUB213PD xmm xmm xmm +// VFMSUB213PD ymm ymm ymm +// VFMSUB213PD m128 xmm k xmm +// VFMSUB213PD m256 ymm k ymm +// VFMSUB213PD xmm xmm k xmm +// VFMSUB213PD ymm ymm k ymm +// VFMSUB213PD m512 zmm k zmm +// VFMSUB213PD m512 zmm zmm +// VFMSUB213PD zmm zmm k zmm +// VFMSUB213PD zmm zmm zmm +// Construct and append a VFMSUB213PD instruction to the active function. +// Operates on the global context. +func VFMSUB213PD(ops ...operand.Op) { ctx.VFMSUB213PD(ops...) } + +// VFMSUB213PD_BCST: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUB213PD.BCST m64 xmm k xmm +// VFMSUB213PD.BCST m64 xmm xmm +// VFMSUB213PD.BCST m64 ymm k ymm +// VFMSUB213PD.BCST m64 ymm ymm +// VFMSUB213PD.BCST m64 zmm k zmm +// VFMSUB213PD.BCST m64 zmm zmm +// Construct and append a VFMSUB213PD.BCST instruction to the active function. +func (c *Context) VFMSUB213PD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB213PD_BCST(ops...)) +} + +// VFMSUB213PD_BCST: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUB213PD.BCST m64 xmm k xmm +// VFMSUB213PD.BCST m64 xmm xmm +// VFMSUB213PD.BCST m64 ymm k ymm +// VFMSUB213PD.BCST m64 ymm ymm +// VFMSUB213PD.BCST m64 zmm k zmm +// VFMSUB213PD.BCST m64 zmm zmm +// Construct and append a VFMSUB213PD.BCST instruction to the active function. +// Operates on the global context. +func VFMSUB213PD_BCST(ops ...operand.Op) { ctx.VFMSUB213PD_BCST(ops...) } + +// VFMSUB213PD_BCST_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUB213PD.BCST.Z m64 xmm k xmm +// VFMSUB213PD.BCST.Z m64 ymm k ymm +// VFMSUB213PD.BCST.Z m64 zmm k zmm +// Construct and append a VFMSUB213PD.BCST.Z instruction to the active function. +func (c *Context) VFMSUB213PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMSUB213PD_BCST_Z(m, xyz, k, xyz1)) +} + +// VFMSUB213PD_BCST_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUB213PD.BCST.Z m64 xmm k xmm +// VFMSUB213PD.BCST.Z m64 ymm k ymm +// VFMSUB213PD.BCST.Z m64 zmm k zmm +// Construct and append a VFMSUB213PD.BCST.Z instruction to the active function. +// Operates on the global context. +func VFMSUB213PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFMSUB213PD_BCST_Z(m, xyz, k, xyz1) } + +// VFMSUB213PD_RD_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB213PD.RD_SAE zmm zmm k zmm +// VFMSUB213PD.RD_SAE zmm zmm zmm +// Construct and append a VFMSUB213PD.RD_SAE instruction to the active function. +func (c *Context) VFMSUB213PD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB213PD_RD_SAE(ops...)) +} + +// VFMSUB213PD_RD_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB213PD.RD_SAE zmm zmm k zmm +// VFMSUB213PD.RD_SAE zmm zmm zmm +// Construct and append a VFMSUB213PD.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB213PD_RD_SAE(ops ...operand.Op) { ctx.VFMSUB213PD_RD_SAE(ops...) } + +// VFMSUB213PD_RD_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB213PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB213PD.RD_SAE.Z instruction to the active function. +func (c *Context) VFMSUB213PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUB213PD_RD_SAE_Z(z, z1, k, z2)) +} + +// VFMSUB213PD_RD_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB213PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB213PD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB213PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUB213PD_RD_SAE_Z(z, z1, k, z2) } + +// VFMSUB213PD_RN_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB213PD.RN_SAE zmm zmm k zmm +// VFMSUB213PD.RN_SAE zmm zmm zmm +// Construct and append a VFMSUB213PD.RN_SAE instruction to the active function. +func (c *Context) VFMSUB213PD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB213PD_RN_SAE(ops...)) +} + +// VFMSUB213PD_RN_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB213PD.RN_SAE zmm zmm k zmm +// VFMSUB213PD.RN_SAE zmm zmm zmm +// Construct and append a VFMSUB213PD.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB213PD_RN_SAE(ops ...operand.Op) { ctx.VFMSUB213PD_RN_SAE(ops...) } + +// VFMSUB213PD_RN_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB213PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB213PD.RN_SAE.Z instruction to the active function. +func (c *Context) VFMSUB213PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUB213PD_RN_SAE_Z(z, z1, k, z2)) +} + +// VFMSUB213PD_RN_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB213PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB213PD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB213PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUB213PD_RN_SAE_Z(z, z1, k, z2) } + +// VFMSUB213PD_RU_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB213PD.RU_SAE zmm zmm k zmm +// VFMSUB213PD.RU_SAE zmm zmm zmm +// Construct and append a VFMSUB213PD.RU_SAE instruction to the active function. +func (c *Context) VFMSUB213PD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB213PD_RU_SAE(ops...)) +} + +// VFMSUB213PD_RU_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB213PD.RU_SAE zmm zmm k zmm +// VFMSUB213PD.RU_SAE zmm zmm zmm +// Construct and append a VFMSUB213PD.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB213PD_RU_SAE(ops ...operand.Op) { ctx.VFMSUB213PD_RU_SAE(ops...) } + +// VFMSUB213PD_RU_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB213PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB213PD.RU_SAE.Z instruction to the active function. +func (c *Context) VFMSUB213PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUB213PD_RU_SAE_Z(z, z1, k, z2)) +} + +// VFMSUB213PD_RU_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB213PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB213PD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB213PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUB213PD_RU_SAE_Z(z, z1, k, z2) } + +// VFMSUB213PD_RZ_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB213PD.RZ_SAE zmm zmm k zmm +// VFMSUB213PD.RZ_SAE zmm zmm zmm +// Construct and append a VFMSUB213PD.RZ_SAE instruction to the active function. +func (c *Context) VFMSUB213PD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB213PD_RZ_SAE(ops...)) +} + +// VFMSUB213PD_RZ_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB213PD.RZ_SAE zmm zmm k zmm +// VFMSUB213PD.RZ_SAE zmm zmm zmm +// Construct and append a VFMSUB213PD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB213PD_RZ_SAE(ops ...operand.Op) { ctx.VFMSUB213PD_RZ_SAE(ops...) } + +// VFMSUB213PD_RZ_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB213PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB213PD.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMSUB213PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUB213PD_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFMSUB213PD_RZ_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB213PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB213PD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB213PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUB213PD_RZ_SAE_Z(z, z1, k, z2) } + +// VFMSUB213PD_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB213PD.Z m128 xmm k xmm +// VFMSUB213PD.Z m256 ymm k ymm +// VFMSUB213PD.Z xmm xmm k xmm +// VFMSUB213PD.Z ymm ymm k ymm +// VFMSUB213PD.Z m512 zmm k zmm +// VFMSUB213PD.Z zmm zmm k zmm +// Construct and append a VFMSUB213PD.Z instruction to the active function. +func (c *Context) VFMSUB213PD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMSUB213PD_Z(mxyz, xyz, k, xyz1)) +} + +// VFMSUB213PD_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB213PD.Z m128 xmm k xmm +// VFMSUB213PD.Z m256 ymm k ymm +// VFMSUB213PD.Z xmm xmm k xmm +// VFMSUB213PD.Z ymm ymm k ymm +// VFMSUB213PD.Z m512 zmm k zmm +// VFMSUB213PD.Z zmm zmm k zmm +// Construct and append a VFMSUB213PD.Z instruction to the active function. +// Operates on the global context. +func VFMSUB213PD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFMSUB213PD_Z(mxyz, xyz, k, xyz1) } + +// VFMSUB213PS: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB213PS m128 xmm xmm +// VFMSUB213PS m256 ymm ymm +// VFMSUB213PS xmm xmm xmm +// VFMSUB213PS ymm ymm ymm +// VFMSUB213PS m128 xmm k xmm +// VFMSUB213PS m256 ymm k ymm +// VFMSUB213PS xmm xmm k xmm +// VFMSUB213PS ymm ymm k ymm +// VFMSUB213PS m512 zmm k zmm +// VFMSUB213PS m512 zmm zmm +// VFMSUB213PS zmm zmm k zmm +// VFMSUB213PS zmm zmm zmm +// Construct and append a VFMSUB213PS instruction to the active function. +func (c *Context) VFMSUB213PS(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB213PS(ops...)) +} + +// VFMSUB213PS: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB213PS m128 xmm xmm +// VFMSUB213PS m256 ymm ymm +// VFMSUB213PS xmm xmm xmm +// VFMSUB213PS ymm ymm ymm +// VFMSUB213PS m128 xmm k xmm +// VFMSUB213PS m256 ymm k ymm +// VFMSUB213PS xmm xmm k xmm +// VFMSUB213PS ymm ymm k ymm +// VFMSUB213PS m512 zmm k zmm +// VFMSUB213PS m512 zmm zmm +// VFMSUB213PS zmm zmm k zmm +// VFMSUB213PS zmm zmm zmm +// Construct and append a VFMSUB213PS instruction to the active function. +// Operates on the global context. +func VFMSUB213PS(ops ...operand.Op) { ctx.VFMSUB213PS(ops...) } + +// VFMSUB213PS_BCST: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUB213PS.BCST m32 xmm k xmm +// VFMSUB213PS.BCST m32 xmm xmm +// VFMSUB213PS.BCST m32 ymm k ymm +// VFMSUB213PS.BCST m32 ymm ymm +// VFMSUB213PS.BCST m32 zmm k zmm +// VFMSUB213PS.BCST m32 zmm zmm +// Construct and append a VFMSUB213PS.BCST instruction to the active function. +func (c *Context) VFMSUB213PS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB213PS_BCST(ops...)) +} + +// VFMSUB213PS_BCST: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUB213PS.BCST m32 xmm k xmm +// VFMSUB213PS.BCST m32 xmm xmm +// VFMSUB213PS.BCST m32 ymm k ymm +// VFMSUB213PS.BCST m32 ymm ymm +// VFMSUB213PS.BCST m32 zmm k zmm +// VFMSUB213PS.BCST m32 zmm zmm +// Construct and append a VFMSUB213PS.BCST instruction to the active function. +// Operates on the global context. +func VFMSUB213PS_BCST(ops ...operand.Op) { ctx.VFMSUB213PS_BCST(ops...) } + +// VFMSUB213PS_BCST_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUB213PS.BCST.Z m32 xmm k xmm +// VFMSUB213PS.BCST.Z m32 ymm k ymm +// VFMSUB213PS.BCST.Z m32 zmm k zmm +// Construct and append a VFMSUB213PS.BCST.Z instruction to the active function. +func (c *Context) VFMSUB213PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMSUB213PS_BCST_Z(m, xyz, k, xyz1)) +} + +// VFMSUB213PS_BCST_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUB213PS.BCST.Z m32 xmm k xmm +// VFMSUB213PS.BCST.Z m32 ymm k ymm +// VFMSUB213PS.BCST.Z m32 zmm k zmm +// Construct and append a VFMSUB213PS.BCST.Z instruction to the active function. +// Operates on the global context. +func VFMSUB213PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFMSUB213PS_BCST_Z(m, xyz, k, xyz1) } + +// VFMSUB213PS_RD_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB213PS.RD_SAE zmm zmm k zmm +// VFMSUB213PS.RD_SAE zmm zmm zmm +// Construct and append a VFMSUB213PS.RD_SAE instruction to the active function. +func (c *Context) VFMSUB213PS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB213PS_RD_SAE(ops...)) +} + +// VFMSUB213PS_RD_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB213PS.RD_SAE zmm zmm k zmm +// VFMSUB213PS.RD_SAE zmm zmm zmm +// Construct and append a VFMSUB213PS.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB213PS_RD_SAE(ops ...operand.Op) { ctx.VFMSUB213PS_RD_SAE(ops...) } + +// VFMSUB213PS_RD_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB213PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB213PS.RD_SAE.Z instruction to the active function. +func (c *Context) VFMSUB213PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUB213PS_RD_SAE_Z(z, z1, k, z2)) +} + +// VFMSUB213PS_RD_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB213PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB213PS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB213PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUB213PS_RD_SAE_Z(z, z1, k, z2) } + +// VFMSUB213PS_RN_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB213PS.RN_SAE zmm zmm k zmm +// VFMSUB213PS.RN_SAE zmm zmm zmm +// Construct and append a VFMSUB213PS.RN_SAE instruction to the active function. +func (c *Context) VFMSUB213PS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB213PS_RN_SAE(ops...)) +} + +// VFMSUB213PS_RN_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB213PS.RN_SAE zmm zmm k zmm +// VFMSUB213PS.RN_SAE zmm zmm zmm +// Construct and append a VFMSUB213PS.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB213PS_RN_SAE(ops ...operand.Op) { ctx.VFMSUB213PS_RN_SAE(ops...) } + +// VFMSUB213PS_RN_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB213PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB213PS.RN_SAE.Z instruction to the active function. +func (c *Context) VFMSUB213PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUB213PS_RN_SAE_Z(z, z1, k, z2)) +} + +// VFMSUB213PS_RN_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB213PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB213PS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB213PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUB213PS_RN_SAE_Z(z, z1, k, z2) } + +// VFMSUB213PS_RU_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB213PS.RU_SAE zmm zmm k zmm +// VFMSUB213PS.RU_SAE zmm zmm zmm +// Construct and append a VFMSUB213PS.RU_SAE instruction to the active function. +func (c *Context) VFMSUB213PS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB213PS_RU_SAE(ops...)) +} + +// VFMSUB213PS_RU_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB213PS.RU_SAE zmm zmm k zmm +// VFMSUB213PS.RU_SAE zmm zmm zmm +// Construct and append a VFMSUB213PS.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB213PS_RU_SAE(ops ...operand.Op) { ctx.VFMSUB213PS_RU_SAE(ops...) } + +// VFMSUB213PS_RU_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB213PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB213PS.RU_SAE.Z instruction to the active function. +func (c *Context) VFMSUB213PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUB213PS_RU_SAE_Z(z, z1, k, z2)) +} + +// VFMSUB213PS_RU_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB213PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB213PS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB213PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUB213PS_RU_SAE_Z(z, z1, k, z2) } + +// VFMSUB213PS_RZ_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB213PS.RZ_SAE zmm zmm k zmm +// VFMSUB213PS.RZ_SAE zmm zmm zmm +// Construct and append a VFMSUB213PS.RZ_SAE instruction to the active function. +func (c *Context) VFMSUB213PS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB213PS_RZ_SAE(ops...)) +} + +// VFMSUB213PS_RZ_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB213PS.RZ_SAE zmm zmm k zmm +// VFMSUB213PS.RZ_SAE zmm zmm zmm +// Construct and append a VFMSUB213PS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB213PS_RZ_SAE(ops ...operand.Op) { ctx.VFMSUB213PS_RZ_SAE(ops...) } + +// VFMSUB213PS_RZ_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB213PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB213PS.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMSUB213PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUB213PS_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFMSUB213PS_RZ_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB213PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB213PS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB213PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUB213PS_RZ_SAE_Z(z, z1, k, z2) } + +// VFMSUB213PS_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB213PS.Z m128 xmm k xmm +// VFMSUB213PS.Z m256 ymm k ymm +// VFMSUB213PS.Z xmm xmm k xmm +// VFMSUB213PS.Z ymm ymm k ymm +// VFMSUB213PS.Z m512 zmm k zmm +// VFMSUB213PS.Z zmm zmm k zmm +// Construct and append a VFMSUB213PS.Z instruction to the active function. +func (c *Context) VFMSUB213PS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMSUB213PS_Z(mxyz, xyz, k, xyz1)) +} + +// VFMSUB213PS_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB213PS.Z m128 xmm k xmm +// VFMSUB213PS.Z m256 ymm k ymm +// VFMSUB213PS.Z xmm xmm k xmm +// VFMSUB213PS.Z ymm ymm k ymm +// VFMSUB213PS.Z m512 zmm k zmm +// VFMSUB213PS.Z zmm zmm k zmm +// Construct and append a VFMSUB213PS.Z instruction to the active function. +// Operates on the global context. +func VFMSUB213PS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFMSUB213PS_Z(mxyz, xyz, k, xyz1) } + +// VFMSUB213SD: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB213SD m64 xmm xmm +// VFMSUB213SD xmm xmm xmm +// VFMSUB213SD m64 xmm k xmm +// VFMSUB213SD xmm xmm k xmm +// Construct and append a VFMSUB213SD instruction to the active function. +func (c *Context) VFMSUB213SD(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB213SD(ops...)) +} + +// VFMSUB213SD: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB213SD m64 xmm xmm +// VFMSUB213SD xmm xmm xmm +// VFMSUB213SD m64 xmm k xmm +// VFMSUB213SD xmm xmm k xmm +// Construct and append a VFMSUB213SD instruction to the active function. +// Operates on the global context. +func VFMSUB213SD(ops ...operand.Op) { ctx.VFMSUB213SD(ops...) } + +// VFMSUB213SD_RD_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB213SD.RD_SAE xmm xmm k xmm +// VFMSUB213SD.RD_SAE xmm xmm xmm +// Construct and append a VFMSUB213SD.RD_SAE instruction to the active function. +func (c *Context) VFMSUB213SD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB213SD_RD_SAE(ops...)) +} + +// VFMSUB213SD_RD_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB213SD.RD_SAE xmm xmm k xmm +// VFMSUB213SD.RD_SAE xmm xmm xmm +// Construct and append a VFMSUB213SD.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB213SD_RD_SAE(ops ...operand.Op) { ctx.VFMSUB213SD_RD_SAE(ops...) } + +// VFMSUB213SD_RD_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB213SD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB213SD.RD_SAE.Z instruction to the active function. +func (c *Context) VFMSUB213SD_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMSUB213SD_RD_SAE_Z(x, x1, k, x2)) +} + +// VFMSUB213SD_RD_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB213SD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB213SD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB213SD_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMSUB213SD_RD_SAE_Z(x, x1, k, x2) } + +// VFMSUB213SD_RN_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB213SD.RN_SAE xmm xmm k xmm +// VFMSUB213SD.RN_SAE xmm xmm xmm +// Construct and append a VFMSUB213SD.RN_SAE instruction to the active function. +func (c *Context) VFMSUB213SD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB213SD_RN_SAE(ops...)) +} + +// VFMSUB213SD_RN_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB213SD.RN_SAE xmm xmm k xmm +// VFMSUB213SD.RN_SAE xmm xmm xmm +// Construct and append a VFMSUB213SD.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB213SD_RN_SAE(ops ...operand.Op) { ctx.VFMSUB213SD_RN_SAE(ops...) } + +// VFMSUB213SD_RN_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB213SD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB213SD.RN_SAE.Z instruction to the active function. +func (c *Context) VFMSUB213SD_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMSUB213SD_RN_SAE_Z(x, x1, k, x2)) +} + +// VFMSUB213SD_RN_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB213SD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB213SD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB213SD_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMSUB213SD_RN_SAE_Z(x, x1, k, x2) } + +// VFMSUB213SD_RU_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB213SD.RU_SAE xmm xmm k xmm +// VFMSUB213SD.RU_SAE xmm xmm xmm +// Construct and append a VFMSUB213SD.RU_SAE instruction to the active function. +func (c *Context) VFMSUB213SD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB213SD_RU_SAE(ops...)) +} + +// VFMSUB213SD_RU_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB213SD.RU_SAE xmm xmm k xmm +// VFMSUB213SD.RU_SAE xmm xmm xmm +// Construct and append a VFMSUB213SD.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB213SD_RU_SAE(ops ...operand.Op) { ctx.VFMSUB213SD_RU_SAE(ops...) } + +// VFMSUB213SD_RU_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB213SD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB213SD.RU_SAE.Z instruction to the active function. +func (c *Context) VFMSUB213SD_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMSUB213SD_RU_SAE_Z(x, x1, k, x2)) +} + +// VFMSUB213SD_RU_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB213SD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB213SD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB213SD_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMSUB213SD_RU_SAE_Z(x, x1, k, x2) } + +// VFMSUB213SD_RZ_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB213SD.RZ_SAE xmm xmm k xmm +// VFMSUB213SD.RZ_SAE xmm xmm xmm +// Construct and append a VFMSUB213SD.RZ_SAE instruction to the active function. +func (c *Context) VFMSUB213SD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB213SD_RZ_SAE(ops...)) +} + +// VFMSUB213SD_RZ_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB213SD.RZ_SAE xmm xmm k xmm +// VFMSUB213SD.RZ_SAE xmm xmm xmm +// Construct and append a VFMSUB213SD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB213SD_RZ_SAE(ops ...operand.Op) { ctx.VFMSUB213SD_RZ_SAE(ops...) } + +// VFMSUB213SD_RZ_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB213SD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB213SD.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMSUB213SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMSUB213SD_RZ_SAE_Z(x, x1, k, x2)) +} + +// VFMSUB213SD_RZ_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB213SD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB213SD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB213SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMSUB213SD_RZ_SAE_Z(x, x1, k, x2) } + +// VFMSUB213SD_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB213SD.Z m64 xmm k xmm +// VFMSUB213SD.Z xmm xmm k xmm +// Construct and append a VFMSUB213SD.Z instruction to the active function. +func (c *Context) VFMSUB213SD_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VFMSUB213SD_Z(mx, x, k, x1)) +} + +// VFMSUB213SD_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB213SD.Z m64 xmm k xmm +// VFMSUB213SD.Z xmm xmm k xmm +// Construct and append a VFMSUB213SD.Z instruction to the active function. +// Operates on the global context. +func VFMSUB213SD_Z(mx, x, k, x1 operand.Op) { ctx.VFMSUB213SD_Z(mx, x, k, x1) } + +// VFMSUB213SS: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB213SS m32 xmm xmm +// VFMSUB213SS xmm xmm xmm +// VFMSUB213SS m32 xmm k xmm +// VFMSUB213SS xmm xmm k xmm +// Construct and append a VFMSUB213SS instruction to the active function. +func (c *Context) VFMSUB213SS(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB213SS(ops...)) +} + +// VFMSUB213SS: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB213SS m32 xmm xmm +// VFMSUB213SS xmm xmm xmm +// VFMSUB213SS m32 xmm k xmm +// VFMSUB213SS xmm xmm k xmm +// Construct and append a VFMSUB213SS instruction to the active function. +// Operates on the global context. +func VFMSUB213SS(ops ...operand.Op) { ctx.VFMSUB213SS(ops...) } + +// VFMSUB213SS_RD_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB213SS.RD_SAE xmm xmm k xmm +// VFMSUB213SS.RD_SAE xmm xmm xmm +// Construct and append a VFMSUB213SS.RD_SAE instruction to the active function. +func (c *Context) VFMSUB213SS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB213SS_RD_SAE(ops...)) +} + +// VFMSUB213SS_RD_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB213SS.RD_SAE xmm xmm k xmm +// VFMSUB213SS.RD_SAE xmm xmm xmm +// Construct and append a VFMSUB213SS.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB213SS_RD_SAE(ops ...operand.Op) { ctx.VFMSUB213SS_RD_SAE(ops...) } + +// VFMSUB213SS_RD_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB213SS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB213SS.RD_SAE.Z instruction to the active function. +func (c *Context) VFMSUB213SS_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMSUB213SS_RD_SAE_Z(x, x1, k, x2)) +} + +// VFMSUB213SS_RD_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB213SS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB213SS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB213SS_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMSUB213SS_RD_SAE_Z(x, x1, k, x2) } + +// VFMSUB213SS_RN_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB213SS.RN_SAE xmm xmm k xmm +// VFMSUB213SS.RN_SAE xmm xmm xmm +// Construct and append a VFMSUB213SS.RN_SAE instruction to the active function. +func (c *Context) VFMSUB213SS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB213SS_RN_SAE(ops...)) +} + +// VFMSUB213SS_RN_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB213SS.RN_SAE xmm xmm k xmm +// VFMSUB213SS.RN_SAE xmm xmm xmm +// Construct and append a VFMSUB213SS.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB213SS_RN_SAE(ops ...operand.Op) { ctx.VFMSUB213SS_RN_SAE(ops...) } + +// VFMSUB213SS_RN_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB213SS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB213SS.RN_SAE.Z instruction to the active function. +func (c *Context) VFMSUB213SS_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMSUB213SS_RN_SAE_Z(x, x1, k, x2)) +} + +// VFMSUB213SS_RN_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB213SS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB213SS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB213SS_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMSUB213SS_RN_SAE_Z(x, x1, k, x2) } + +// VFMSUB213SS_RU_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB213SS.RU_SAE xmm xmm k xmm +// VFMSUB213SS.RU_SAE xmm xmm xmm +// Construct and append a VFMSUB213SS.RU_SAE instruction to the active function. +func (c *Context) VFMSUB213SS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB213SS_RU_SAE(ops...)) +} + +// VFMSUB213SS_RU_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB213SS.RU_SAE xmm xmm k xmm +// VFMSUB213SS.RU_SAE xmm xmm xmm +// Construct and append a VFMSUB213SS.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB213SS_RU_SAE(ops ...operand.Op) { ctx.VFMSUB213SS_RU_SAE(ops...) } + +// VFMSUB213SS_RU_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB213SS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB213SS.RU_SAE.Z instruction to the active function. +func (c *Context) VFMSUB213SS_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMSUB213SS_RU_SAE_Z(x, x1, k, x2)) +} + +// VFMSUB213SS_RU_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB213SS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB213SS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB213SS_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMSUB213SS_RU_SAE_Z(x, x1, k, x2) } + +// VFMSUB213SS_RZ_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB213SS.RZ_SAE xmm xmm k xmm +// VFMSUB213SS.RZ_SAE xmm xmm xmm +// Construct and append a VFMSUB213SS.RZ_SAE instruction to the active function. +func (c *Context) VFMSUB213SS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB213SS_RZ_SAE(ops...)) +} + +// VFMSUB213SS_RZ_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB213SS.RZ_SAE xmm xmm k xmm +// VFMSUB213SS.RZ_SAE xmm xmm xmm +// Construct and append a VFMSUB213SS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB213SS_RZ_SAE(ops ...operand.Op) { ctx.VFMSUB213SS_RZ_SAE(ops...) } + +// VFMSUB213SS_RZ_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB213SS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB213SS.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMSUB213SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMSUB213SS_RZ_SAE_Z(x, x1, k, x2)) +} + +// VFMSUB213SS_RZ_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB213SS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB213SS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB213SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMSUB213SS_RZ_SAE_Z(x, x1, k, x2) } + +// VFMSUB213SS_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB213SS.Z m32 xmm k xmm +// VFMSUB213SS.Z xmm xmm k xmm +// Construct and append a VFMSUB213SS.Z instruction to the active function. +func (c *Context) VFMSUB213SS_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VFMSUB213SS_Z(mx, x, k, x1)) +} + +// VFMSUB213SS_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB213SS.Z m32 xmm k xmm +// VFMSUB213SS.Z xmm xmm k xmm +// Construct and append a VFMSUB213SS.Z instruction to the active function. +// Operates on the global context. +func VFMSUB213SS_Z(mx, x, k, x1 operand.Op) { ctx.VFMSUB213SS_Z(mx, x, k, x1) } + +// VFMSUB231PD: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB231PD m128 xmm xmm +// VFMSUB231PD m256 ymm ymm +// VFMSUB231PD xmm xmm xmm +// VFMSUB231PD ymm ymm ymm +// VFMSUB231PD m128 xmm k xmm +// VFMSUB231PD m256 ymm k ymm +// VFMSUB231PD xmm xmm k xmm +// VFMSUB231PD ymm ymm k ymm +// VFMSUB231PD m512 zmm k zmm +// VFMSUB231PD m512 zmm zmm +// VFMSUB231PD zmm zmm k zmm +// VFMSUB231PD zmm zmm zmm +// Construct and append a VFMSUB231PD instruction to the active function. +func (c *Context) VFMSUB231PD(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB231PD(ops...)) +} + +// VFMSUB231PD: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB231PD m128 xmm xmm +// VFMSUB231PD m256 ymm ymm +// VFMSUB231PD xmm xmm xmm +// VFMSUB231PD ymm ymm ymm +// VFMSUB231PD m128 xmm k xmm +// VFMSUB231PD m256 ymm k ymm +// VFMSUB231PD xmm xmm k xmm +// VFMSUB231PD ymm ymm k ymm +// VFMSUB231PD m512 zmm k zmm +// VFMSUB231PD m512 zmm zmm +// VFMSUB231PD zmm zmm k zmm +// VFMSUB231PD zmm zmm zmm +// Construct and append a VFMSUB231PD instruction to the active function. +// Operates on the global context. +func VFMSUB231PD(ops ...operand.Op) { ctx.VFMSUB231PD(ops...) } + +// VFMSUB231PD_BCST: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUB231PD.BCST m64 xmm k xmm +// VFMSUB231PD.BCST m64 xmm xmm +// VFMSUB231PD.BCST m64 ymm k ymm +// VFMSUB231PD.BCST m64 ymm ymm +// VFMSUB231PD.BCST m64 zmm k zmm +// VFMSUB231PD.BCST m64 zmm zmm +// Construct and append a VFMSUB231PD.BCST instruction to the active function. +func (c *Context) VFMSUB231PD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB231PD_BCST(ops...)) +} + +// VFMSUB231PD_BCST: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUB231PD.BCST m64 xmm k xmm +// VFMSUB231PD.BCST m64 xmm xmm +// VFMSUB231PD.BCST m64 ymm k ymm +// VFMSUB231PD.BCST m64 ymm ymm +// VFMSUB231PD.BCST m64 zmm k zmm +// VFMSUB231PD.BCST m64 zmm zmm +// Construct and append a VFMSUB231PD.BCST instruction to the active function. +// Operates on the global context. +func VFMSUB231PD_BCST(ops ...operand.Op) { ctx.VFMSUB231PD_BCST(ops...) } + +// VFMSUB231PD_BCST_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUB231PD.BCST.Z m64 xmm k xmm +// VFMSUB231PD.BCST.Z m64 ymm k ymm +// VFMSUB231PD.BCST.Z m64 zmm k zmm +// Construct and append a VFMSUB231PD.BCST.Z instruction to the active function. +func (c *Context) VFMSUB231PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMSUB231PD_BCST_Z(m, xyz, k, xyz1)) +} + +// VFMSUB231PD_BCST_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUB231PD.BCST.Z m64 xmm k xmm +// VFMSUB231PD.BCST.Z m64 ymm k ymm +// VFMSUB231PD.BCST.Z m64 zmm k zmm +// Construct and append a VFMSUB231PD.BCST.Z instruction to the active function. +// Operates on the global context. +func VFMSUB231PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFMSUB231PD_BCST_Z(m, xyz, k, xyz1) } + +// VFMSUB231PD_RD_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB231PD.RD_SAE zmm zmm k zmm +// VFMSUB231PD.RD_SAE zmm zmm zmm +// Construct and append a VFMSUB231PD.RD_SAE instruction to the active function. +func (c *Context) VFMSUB231PD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB231PD_RD_SAE(ops...)) +} + +// VFMSUB231PD_RD_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB231PD.RD_SAE zmm zmm k zmm +// VFMSUB231PD.RD_SAE zmm zmm zmm +// Construct and append a VFMSUB231PD.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB231PD_RD_SAE(ops ...operand.Op) { ctx.VFMSUB231PD_RD_SAE(ops...) } + +// VFMSUB231PD_RD_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB231PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB231PD.RD_SAE.Z instruction to the active function. +func (c *Context) VFMSUB231PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUB231PD_RD_SAE_Z(z, z1, k, z2)) +} + +// VFMSUB231PD_RD_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB231PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB231PD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB231PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUB231PD_RD_SAE_Z(z, z1, k, z2) } + +// VFMSUB231PD_RN_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB231PD.RN_SAE zmm zmm k zmm +// VFMSUB231PD.RN_SAE zmm zmm zmm +// Construct and append a VFMSUB231PD.RN_SAE instruction to the active function. +func (c *Context) VFMSUB231PD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB231PD_RN_SAE(ops...)) +} + +// VFMSUB231PD_RN_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB231PD.RN_SAE zmm zmm k zmm +// VFMSUB231PD.RN_SAE zmm zmm zmm +// Construct and append a VFMSUB231PD.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB231PD_RN_SAE(ops ...operand.Op) { ctx.VFMSUB231PD_RN_SAE(ops...) } + +// VFMSUB231PD_RN_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB231PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB231PD.RN_SAE.Z instruction to the active function. +func (c *Context) VFMSUB231PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUB231PD_RN_SAE_Z(z, z1, k, z2)) +} + +// VFMSUB231PD_RN_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB231PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB231PD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB231PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUB231PD_RN_SAE_Z(z, z1, k, z2) } + +// VFMSUB231PD_RU_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB231PD.RU_SAE zmm zmm k zmm +// VFMSUB231PD.RU_SAE zmm zmm zmm +// Construct and append a VFMSUB231PD.RU_SAE instruction to the active function. +func (c *Context) VFMSUB231PD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB231PD_RU_SAE(ops...)) +} + +// VFMSUB231PD_RU_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB231PD.RU_SAE zmm zmm k zmm +// VFMSUB231PD.RU_SAE zmm zmm zmm +// Construct and append a VFMSUB231PD.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB231PD_RU_SAE(ops ...operand.Op) { ctx.VFMSUB231PD_RU_SAE(ops...) } + +// VFMSUB231PD_RU_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB231PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB231PD.RU_SAE.Z instruction to the active function. +func (c *Context) VFMSUB231PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUB231PD_RU_SAE_Z(z, z1, k, z2)) +} + +// VFMSUB231PD_RU_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB231PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB231PD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB231PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUB231PD_RU_SAE_Z(z, z1, k, z2) } + +// VFMSUB231PD_RZ_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB231PD.RZ_SAE zmm zmm k zmm +// VFMSUB231PD.RZ_SAE zmm zmm zmm +// Construct and append a VFMSUB231PD.RZ_SAE instruction to the active function. +func (c *Context) VFMSUB231PD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB231PD_RZ_SAE(ops...)) +} + +// VFMSUB231PD_RZ_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB231PD.RZ_SAE zmm zmm k zmm +// VFMSUB231PD.RZ_SAE zmm zmm zmm +// Construct and append a VFMSUB231PD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB231PD_RZ_SAE(ops ...operand.Op) { ctx.VFMSUB231PD_RZ_SAE(ops...) } + +// VFMSUB231PD_RZ_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB231PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB231PD.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMSUB231PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUB231PD_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFMSUB231PD_RZ_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB231PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB231PD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB231PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUB231PD_RZ_SAE_Z(z, z1, k, z2) } + +// VFMSUB231PD_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB231PD.Z m128 xmm k xmm +// VFMSUB231PD.Z m256 ymm k ymm +// VFMSUB231PD.Z xmm xmm k xmm +// VFMSUB231PD.Z ymm ymm k ymm +// VFMSUB231PD.Z m512 zmm k zmm +// VFMSUB231PD.Z zmm zmm k zmm +// Construct and append a VFMSUB231PD.Z instruction to the active function. +func (c *Context) VFMSUB231PD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMSUB231PD_Z(mxyz, xyz, k, xyz1)) +} + +// VFMSUB231PD_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB231PD.Z m128 xmm k xmm +// VFMSUB231PD.Z m256 ymm k ymm +// VFMSUB231PD.Z xmm xmm k xmm +// VFMSUB231PD.Z ymm ymm k ymm +// VFMSUB231PD.Z m512 zmm k zmm +// VFMSUB231PD.Z zmm zmm k zmm +// Construct and append a VFMSUB231PD.Z instruction to the active function. +// Operates on the global context. +func VFMSUB231PD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFMSUB231PD_Z(mxyz, xyz, k, xyz1) } + +// VFMSUB231PS: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB231PS m128 xmm xmm +// VFMSUB231PS m256 ymm ymm +// VFMSUB231PS xmm xmm xmm +// VFMSUB231PS ymm ymm ymm +// VFMSUB231PS m128 xmm k xmm +// VFMSUB231PS m256 ymm k ymm +// VFMSUB231PS xmm xmm k xmm +// VFMSUB231PS ymm ymm k ymm +// VFMSUB231PS m512 zmm k zmm +// VFMSUB231PS m512 zmm zmm +// VFMSUB231PS zmm zmm k zmm +// VFMSUB231PS zmm zmm zmm +// Construct and append a VFMSUB231PS instruction to the active function. +func (c *Context) VFMSUB231PS(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB231PS(ops...)) +} + +// VFMSUB231PS: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB231PS m128 xmm xmm +// VFMSUB231PS m256 ymm ymm +// VFMSUB231PS xmm xmm xmm +// VFMSUB231PS ymm ymm ymm +// VFMSUB231PS m128 xmm k xmm +// VFMSUB231PS m256 ymm k ymm +// VFMSUB231PS xmm xmm k xmm +// VFMSUB231PS ymm ymm k ymm +// VFMSUB231PS m512 zmm k zmm +// VFMSUB231PS m512 zmm zmm +// VFMSUB231PS zmm zmm k zmm +// VFMSUB231PS zmm zmm zmm +// Construct and append a VFMSUB231PS instruction to the active function. +// Operates on the global context. +func VFMSUB231PS(ops ...operand.Op) { ctx.VFMSUB231PS(ops...) } + +// VFMSUB231PS_BCST: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUB231PS.BCST m32 xmm k xmm +// VFMSUB231PS.BCST m32 xmm xmm +// VFMSUB231PS.BCST m32 ymm k ymm +// VFMSUB231PS.BCST m32 ymm ymm +// VFMSUB231PS.BCST m32 zmm k zmm +// VFMSUB231PS.BCST m32 zmm zmm +// Construct and append a VFMSUB231PS.BCST instruction to the active function. +func (c *Context) VFMSUB231PS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB231PS_BCST(ops...)) +} + +// VFMSUB231PS_BCST: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUB231PS.BCST m32 xmm k xmm +// VFMSUB231PS.BCST m32 xmm xmm +// VFMSUB231PS.BCST m32 ymm k ymm +// VFMSUB231PS.BCST m32 ymm ymm +// VFMSUB231PS.BCST m32 zmm k zmm +// VFMSUB231PS.BCST m32 zmm zmm +// Construct and append a VFMSUB231PS.BCST instruction to the active function. +// Operates on the global context. +func VFMSUB231PS_BCST(ops ...operand.Op) { ctx.VFMSUB231PS_BCST(ops...) } + +// VFMSUB231PS_BCST_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUB231PS.BCST.Z m32 xmm k xmm +// VFMSUB231PS.BCST.Z m32 ymm k ymm +// VFMSUB231PS.BCST.Z m32 zmm k zmm +// Construct and append a VFMSUB231PS.BCST.Z instruction to the active function. +func (c *Context) VFMSUB231PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMSUB231PS_BCST_Z(m, xyz, k, xyz1)) +} + +// VFMSUB231PS_BCST_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUB231PS.BCST.Z m32 xmm k xmm +// VFMSUB231PS.BCST.Z m32 ymm k ymm +// VFMSUB231PS.BCST.Z m32 zmm k zmm +// Construct and append a VFMSUB231PS.BCST.Z instruction to the active function. +// Operates on the global context. +func VFMSUB231PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFMSUB231PS_BCST_Z(m, xyz, k, xyz1) } + +// VFMSUB231PS_RD_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB231PS.RD_SAE zmm zmm k zmm +// VFMSUB231PS.RD_SAE zmm zmm zmm +// Construct and append a VFMSUB231PS.RD_SAE instruction to the active function. +func (c *Context) VFMSUB231PS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB231PS_RD_SAE(ops...)) +} + +// VFMSUB231PS_RD_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB231PS.RD_SAE zmm zmm k zmm +// VFMSUB231PS.RD_SAE zmm zmm zmm +// Construct and append a VFMSUB231PS.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB231PS_RD_SAE(ops ...operand.Op) { ctx.VFMSUB231PS_RD_SAE(ops...) } + +// VFMSUB231PS_RD_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB231PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB231PS.RD_SAE.Z instruction to the active function. +func (c *Context) VFMSUB231PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUB231PS_RD_SAE_Z(z, z1, k, z2)) +} + +// VFMSUB231PS_RD_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB231PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB231PS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB231PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUB231PS_RD_SAE_Z(z, z1, k, z2) } + +// VFMSUB231PS_RN_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB231PS.RN_SAE zmm zmm k zmm +// VFMSUB231PS.RN_SAE zmm zmm zmm +// Construct and append a VFMSUB231PS.RN_SAE instruction to the active function. +func (c *Context) VFMSUB231PS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB231PS_RN_SAE(ops...)) +} + +// VFMSUB231PS_RN_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB231PS.RN_SAE zmm zmm k zmm +// VFMSUB231PS.RN_SAE zmm zmm zmm +// Construct and append a VFMSUB231PS.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB231PS_RN_SAE(ops ...operand.Op) { ctx.VFMSUB231PS_RN_SAE(ops...) } + +// VFMSUB231PS_RN_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB231PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB231PS.RN_SAE.Z instruction to the active function. +func (c *Context) VFMSUB231PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUB231PS_RN_SAE_Z(z, z1, k, z2)) +} + +// VFMSUB231PS_RN_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB231PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB231PS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB231PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUB231PS_RN_SAE_Z(z, z1, k, z2) } + +// VFMSUB231PS_RU_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB231PS.RU_SAE zmm zmm k zmm +// VFMSUB231PS.RU_SAE zmm zmm zmm +// Construct and append a VFMSUB231PS.RU_SAE instruction to the active function. +func (c *Context) VFMSUB231PS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB231PS_RU_SAE(ops...)) +} + +// VFMSUB231PS_RU_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB231PS.RU_SAE zmm zmm k zmm +// VFMSUB231PS.RU_SAE zmm zmm zmm +// Construct and append a VFMSUB231PS.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB231PS_RU_SAE(ops ...operand.Op) { ctx.VFMSUB231PS_RU_SAE(ops...) } + +// VFMSUB231PS_RU_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB231PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB231PS.RU_SAE.Z instruction to the active function. +func (c *Context) VFMSUB231PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUB231PS_RU_SAE_Z(z, z1, k, z2)) +} + +// VFMSUB231PS_RU_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB231PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB231PS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB231PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUB231PS_RU_SAE_Z(z, z1, k, z2) } + +// VFMSUB231PS_RZ_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB231PS.RZ_SAE zmm zmm k zmm +// VFMSUB231PS.RZ_SAE zmm zmm zmm +// Construct and append a VFMSUB231PS.RZ_SAE instruction to the active function. +func (c *Context) VFMSUB231PS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB231PS_RZ_SAE(ops...)) +} + +// VFMSUB231PS_RZ_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB231PS.RZ_SAE zmm zmm k zmm +// VFMSUB231PS.RZ_SAE zmm zmm zmm +// Construct and append a VFMSUB231PS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB231PS_RZ_SAE(ops ...operand.Op) { ctx.VFMSUB231PS_RZ_SAE(ops...) } + +// VFMSUB231PS_RZ_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB231PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB231PS.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMSUB231PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUB231PS_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFMSUB231PS_RZ_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB231PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUB231PS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB231PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUB231PS_RZ_SAE_Z(z, z1, k, z2) } + +// VFMSUB231PS_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB231PS.Z m128 xmm k xmm +// VFMSUB231PS.Z m256 ymm k ymm +// VFMSUB231PS.Z xmm xmm k xmm +// VFMSUB231PS.Z ymm ymm k ymm +// VFMSUB231PS.Z m512 zmm k zmm +// VFMSUB231PS.Z zmm zmm k zmm +// Construct and append a VFMSUB231PS.Z instruction to the active function. +func (c *Context) VFMSUB231PS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMSUB231PS_Z(mxyz, xyz, k, xyz1)) +} + +// VFMSUB231PS_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB231PS.Z m128 xmm k xmm +// VFMSUB231PS.Z m256 ymm k ymm +// VFMSUB231PS.Z xmm xmm k xmm +// VFMSUB231PS.Z ymm ymm k ymm +// VFMSUB231PS.Z m512 zmm k zmm +// VFMSUB231PS.Z zmm zmm k zmm +// Construct and append a VFMSUB231PS.Z instruction to the active function. +// Operates on the global context. +func VFMSUB231PS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFMSUB231PS_Z(mxyz, xyz, k, xyz1) } + +// VFMSUB231SD: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB231SD m64 xmm xmm +// VFMSUB231SD xmm xmm xmm +// VFMSUB231SD m64 xmm k xmm +// VFMSUB231SD xmm xmm k xmm +// Construct and append a VFMSUB231SD instruction to the active function. +func (c *Context) VFMSUB231SD(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB231SD(ops...)) +} + +// VFMSUB231SD: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB231SD m64 xmm xmm +// VFMSUB231SD xmm xmm xmm +// VFMSUB231SD m64 xmm k xmm +// VFMSUB231SD xmm xmm k xmm +// Construct and append a VFMSUB231SD instruction to the active function. +// Operates on the global context. +func VFMSUB231SD(ops ...operand.Op) { ctx.VFMSUB231SD(ops...) } + +// VFMSUB231SD_RD_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB231SD.RD_SAE xmm xmm k xmm +// VFMSUB231SD.RD_SAE xmm xmm xmm +// Construct and append a VFMSUB231SD.RD_SAE instruction to the active function. +func (c *Context) VFMSUB231SD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB231SD_RD_SAE(ops...)) +} + +// VFMSUB231SD_RD_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB231SD.RD_SAE xmm xmm k xmm +// VFMSUB231SD.RD_SAE xmm xmm xmm +// Construct and append a VFMSUB231SD.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB231SD_RD_SAE(ops ...operand.Op) { ctx.VFMSUB231SD_RD_SAE(ops...) } + +// VFMSUB231SD_RD_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB231SD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB231SD.RD_SAE.Z instruction to the active function. +func (c *Context) VFMSUB231SD_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMSUB231SD_RD_SAE_Z(x, x1, k, x2)) +} + +// VFMSUB231SD_RD_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB231SD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB231SD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB231SD_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMSUB231SD_RD_SAE_Z(x, x1, k, x2) } + +// VFMSUB231SD_RN_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB231SD.RN_SAE xmm xmm k xmm +// VFMSUB231SD.RN_SAE xmm xmm xmm +// Construct and append a VFMSUB231SD.RN_SAE instruction to the active function. +func (c *Context) VFMSUB231SD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB231SD_RN_SAE(ops...)) +} + +// VFMSUB231SD_RN_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB231SD.RN_SAE xmm xmm k xmm +// VFMSUB231SD.RN_SAE xmm xmm xmm +// Construct and append a VFMSUB231SD.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB231SD_RN_SAE(ops ...operand.Op) { ctx.VFMSUB231SD_RN_SAE(ops...) } + +// VFMSUB231SD_RN_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB231SD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB231SD.RN_SAE.Z instruction to the active function. +func (c *Context) VFMSUB231SD_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMSUB231SD_RN_SAE_Z(x, x1, k, x2)) +} + +// VFMSUB231SD_RN_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB231SD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB231SD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB231SD_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMSUB231SD_RN_SAE_Z(x, x1, k, x2) } + +// VFMSUB231SD_RU_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB231SD.RU_SAE xmm xmm k xmm +// VFMSUB231SD.RU_SAE xmm xmm xmm +// Construct and append a VFMSUB231SD.RU_SAE instruction to the active function. +func (c *Context) VFMSUB231SD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB231SD_RU_SAE(ops...)) +} + +// VFMSUB231SD_RU_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB231SD.RU_SAE xmm xmm k xmm +// VFMSUB231SD.RU_SAE xmm xmm xmm +// Construct and append a VFMSUB231SD.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB231SD_RU_SAE(ops ...operand.Op) { ctx.VFMSUB231SD_RU_SAE(ops...) } + +// VFMSUB231SD_RU_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB231SD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB231SD.RU_SAE.Z instruction to the active function. +func (c *Context) VFMSUB231SD_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMSUB231SD_RU_SAE_Z(x, x1, k, x2)) +} + +// VFMSUB231SD_RU_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB231SD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB231SD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB231SD_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMSUB231SD_RU_SAE_Z(x, x1, k, x2) } + +// VFMSUB231SD_RZ_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB231SD.RZ_SAE xmm xmm k xmm +// VFMSUB231SD.RZ_SAE xmm xmm xmm +// Construct and append a VFMSUB231SD.RZ_SAE instruction to the active function. +func (c *Context) VFMSUB231SD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB231SD_RZ_SAE(ops...)) +} + +// VFMSUB231SD_RZ_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB231SD.RZ_SAE xmm xmm k xmm +// VFMSUB231SD.RZ_SAE xmm xmm xmm +// Construct and append a VFMSUB231SD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB231SD_RZ_SAE(ops ...operand.Op) { ctx.VFMSUB231SD_RZ_SAE(ops...) } + +// VFMSUB231SD_RZ_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB231SD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB231SD.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMSUB231SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMSUB231SD_RZ_SAE_Z(x, x1, k, x2)) +} + +// VFMSUB231SD_RZ_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB231SD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB231SD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB231SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMSUB231SD_RZ_SAE_Z(x, x1, k, x2) } + +// VFMSUB231SD_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB231SD.Z m64 xmm k xmm +// VFMSUB231SD.Z xmm xmm k xmm +// Construct and append a VFMSUB231SD.Z instruction to the active function. +func (c *Context) VFMSUB231SD_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VFMSUB231SD_Z(mx, x, k, x1)) +} + +// VFMSUB231SD_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB231SD.Z m64 xmm k xmm +// VFMSUB231SD.Z xmm xmm k xmm +// Construct and append a VFMSUB231SD.Z instruction to the active function. +// Operates on the global context. +func VFMSUB231SD_Z(mx, x, k, x1 operand.Op) { ctx.VFMSUB231SD_Z(mx, x, k, x1) } + +// VFMSUB231SS: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB231SS m32 xmm xmm +// VFMSUB231SS xmm xmm xmm +// VFMSUB231SS m32 xmm k xmm +// VFMSUB231SS xmm xmm k xmm +// Construct and append a VFMSUB231SS instruction to the active function. +func (c *Context) VFMSUB231SS(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB231SS(ops...)) +} + +// VFMSUB231SS: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB231SS m32 xmm xmm +// VFMSUB231SS xmm xmm xmm +// VFMSUB231SS m32 xmm k xmm +// VFMSUB231SS xmm xmm k xmm +// Construct and append a VFMSUB231SS instruction to the active function. +// Operates on the global context. +func VFMSUB231SS(ops ...operand.Op) { ctx.VFMSUB231SS(ops...) } + +// VFMSUB231SS_RD_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB231SS.RD_SAE xmm xmm k xmm +// VFMSUB231SS.RD_SAE xmm xmm xmm +// Construct and append a VFMSUB231SS.RD_SAE instruction to the active function. +func (c *Context) VFMSUB231SS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB231SS_RD_SAE(ops...)) +} + +// VFMSUB231SS_RD_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB231SS.RD_SAE xmm xmm k xmm +// VFMSUB231SS.RD_SAE xmm xmm xmm +// Construct and append a VFMSUB231SS.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB231SS_RD_SAE(ops ...operand.Op) { ctx.VFMSUB231SS_RD_SAE(ops...) } + +// VFMSUB231SS_RD_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB231SS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB231SS.RD_SAE.Z instruction to the active function. +func (c *Context) VFMSUB231SS_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMSUB231SS_RD_SAE_Z(x, x1, k, x2)) +} + +// VFMSUB231SS_RD_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB231SS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB231SS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB231SS_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMSUB231SS_RD_SAE_Z(x, x1, k, x2) } + +// VFMSUB231SS_RN_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB231SS.RN_SAE xmm xmm k xmm +// VFMSUB231SS.RN_SAE xmm xmm xmm +// Construct and append a VFMSUB231SS.RN_SAE instruction to the active function. +func (c *Context) VFMSUB231SS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB231SS_RN_SAE(ops...)) +} + +// VFMSUB231SS_RN_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB231SS.RN_SAE xmm xmm k xmm +// VFMSUB231SS.RN_SAE xmm xmm xmm +// Construct and append a VFMSUB231SS.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB231SS_RN_SAE(ops ...operand.Op) { ctx.VFMSUB231SS_RN_SAE(ops...) } + +// VFMSUB231SS_RN_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB231SS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB231SS.RN_SAE.Z instruction to the active function. +func (c *Context) VFMSUB231SS_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMSUB231SS_RN_SAE_Z(x, x1, k, x2)) +} + +// VFMSUB231SS_RN_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB231SS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB231SS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB231SS_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMSUB231SS_RN_SAE_Z(x, x1, k, x2) } + +// VFMSUB231SS_RU_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB231SS.RU_SAE xmm xmm k xmm +// VFMSUB231SS.RU_SAE xmm xmm xmm +// Construct and append a VFMSUB231SS.RU_SAE instruction to the active function. +func (c *Context) VFMSUB231SS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB231SS_RU_SAE(ops...)) +} + +// VFMSUB231SS_RU_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB231SS.RU_SAE xmm xmm k xmm +// VFMSUB231SS.RU_SAE xmm xmm xmm +// Construct and append a VFMSUB231SS.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB231SS_RU_SAE(ops ...operand.Op) { ctx.VFMSUB231SS_RU_SAE(ops...) } + +// VFMSUB231SS_RU_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB231SS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB231SS.RU_SAE.Z instruction to the active function. +func (c *Context) VFMSUB231SS_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMSUB231SS_RU_SAE_Z(x, x1, k, x2)) +} + +// VFMSUB231SS_RU_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB231SS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB231SS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB231SS_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMSUB231SS_RU_SAE_Z(x, x1, k, x2) } + +// VFMSUB231SS_RZ_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB231SS.RZ_SAE xmm xmm k xmm +// VFMSUB231SS.RZ_SAE xmm xmm xmm +// Construct and append a VFMSUB231SS.RZ_SAE instruction to the active function. +func (c *Context) VFMSUB231SS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUB231SS_RZ_SAE(ops...)) +} + +// VFMSUB231SS_RZ_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB231SS.RZ_SAE xmm xmm k xmm +// VFMSUB231SS.RZ_SAE xmm xmm xmm +// Construct and append a VFMSUB231SS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMSUB231SS_RZ_SAE(ops ...operand.Op) { ctx.VFMSUB231SS_RZ_SAE(ops...) } + +// VFMSUB231SS_RZ_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB231SS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB231SS.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMSUB231SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFMSUB231SS_RZ_SAE_Z(x, x1, k, x2)) +} + +// VFMSUB231SS_RZ_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB231SS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFMSUB231SS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUB231SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFMSUB231SS_RZ_SAE_Z(x, x1, k, x2) } + +// VFMSUB231SS_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB231SS.Z m32 xmm k xmm +// VFMSUB231SS.Z xmm xmm k xmm +// Construct and append a VFMSUB231SS.Z instruction to the active function. +func (c *Context) VFMSUB231SS_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VFMSUB231SS_Z(mx, x, k, x1)) +} + +// VFMSUB231SS_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB231SS.Z m32 xmm k xmm +// VFMSUB231SS.Z xmm xmm k xmm +// Construct and append a VFMSUB231SS.Z instruction to the active function. +// Operates on the global context. +func VFMSUB231SS_Z(mx, x, k, x1 operand.Op) { ctx.VFMSUB231SS_Z(mx, x, k, x1) } + +// VFMSUBADD132PD: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUBADD132PD m128 xmm xmm +// VFMSUBADD132PD m256 ymm ymm +// VFMSUBADD132PD xmm xmm xmm +// VFMSUBADD132PD ymm ymm ymm +// VFMSUBADD132PD m128 xmm k xmm +// VFMSUBADD132PD m256 ymm k ymm +// VFMSUBADD132PD xmm xmm k xmm +// VFMSUBADD132PD ymm ymm k ymm +// VFMSUBADD132PD m512 zmm k zmm +// VFMSUBADD132PD m512 zmm zmm +// VFMSUBADD132PD zmm zmm k zmm +// VFMSUBADD132PD zmm zmm zmm +// Construct and append a VFMSUBADD132PD instruction to the active function. +func (c *Context) VFMSUBADD132PD(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD132PD(ops...)) +} + +// VFMSUBADD132PD: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUBADD132PD m128 xmm xmm +// VFMSUBADD132PD m256 ymm ymm +// VFMSUBADD132PD xmm xmm xmm +// VFMSUBADD132PD ymm ymm ymm +// VFMSUBADD132PD m128 xmm k xmm +// VFMSUBADD132PD m256 ymm k ymm +// VFMSUBADD132PD xmm xmm k xmm +// VFMSUBADD132PD ymm ymm k ymm +// VFMSUBADD132PD m512 zmm k zmm +// VFMSUBADD132PD m512 zmm zmm +// VFMSUBADD132PD zmm zmm k zmm +// VFMSUBADD132PD zmm zmm zmm +// Construct and append a VFMSUBADD132PD instruction to the active function. +// Operates on the global context. +func VFMSUBADD132PD(ops ...operand.Op) { ctx.VFMSUBADD132PD(ops...) } + +// VFMSUBADD132PD_BCST: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUBADD132PD.BCST m64 xmm k xmm +// VFMSUBADD132PD.BCST m64 xmm xmm +// VFMSUBADD132PD.BCST m64 ymm k ymm +// VFMSUBADD132PD.BCST m64 ymm ymm +// VFMSUBADD132PD.BCST m64 zmm k zmm +// VFMSUBADD132PD.BCST m64 zmm zmm +// Construct and append a VFMSUBADD132PD.BCST instruction to the active function. +func (c *Context) VFMSUBADD132PD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD132PD_BCST(ops...)) +} + +// VFMSUBADD132PD_BCST: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUBADD132PD.BCST m64 xmm k xmm +// VFMSUBADD132PD.BCST m64 xmm xmm +// VFMSUBADD132PD.BCST m64 ymm k ymm +// VFMSUBADD132PD.BCST m64 ymm ymm +// VFMSUBADD132PD.BCST m64 zmm k zmm +// VFMSUBADD132PD.BCST m64 zmm zmm +// Construct and append a VFMSUBADD132PD.BCST instruction to the active function. +// Operates on the global context. +func VFMSUBADD132PD_BCST(ops ...operand.Op) { ctx.VFMSUBADD132PD_BCST(ops...) } + +// VFMSUBADD132PD_BCST_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PD.BCST.Z m64 xmm k xmm +// VFMSUBADD132PD.BCST.Z m64 ymm k ymm +// VFMSUBADD132PD.BCST.Z m64 zmm k zmm +// Construct and append a VFMSUBADD132PD.BCST.Z instruction to the active function. +func (c *Context) VFMSUBADD132PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMSUBADD132PD_BCST_Z(m, xyz, k, xyz1)) +} + +// VFMSUBADD132PD_BCST_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PD.BCST.Z m64 xmm k xmm +// VFMSUBADD132PD.BCST.Z m64 ymm k ymm +// VFMSUBADD132PD.BCST.Z m64 zmm k zmm +// Construct and append a VFMSUBADD132PD.BCST.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD132PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFMSUBADD132PD_BCST_Z(m, xyz, k, xyz1) } + +// VFMSUBADD132PD_RD_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUBADD132PD.RD_SAE zmm zmm k zmm +// VFMSUBADD132PD.RD_SAE zmm zmm zmm +// Construct and append a VFMSUBADD132PD.RD_SAE instruction to the active function. +func (c *Context) VFMSUBADD132PD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD132PD_RD_SAE(ops...)) +} + +// VFMSUBADD132PD_RD_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUBADD132PD.RD_SAE zmm zmm k zmm +// VFMSUBADD132PD.RD_SAE zmm zmm zmm +// Construct and append a VFMSUBADD132PD.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMSUBADD132PD_RD_SAE(ops ...operand.Op) { ctx.VFMSUBADD132PD_RD_SAE(ops...) } + +// VFMSUBADD132PD_RD_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD132PD.RD_SAE.Z instruction to the active function. +func (c *Context) VFMSUBADD132PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUBADD132PD_RD_SAE_Z(z, z1, k, z2)) +} + +// VFMSUBADD132PD_RD_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD132PD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD132PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUBADD132PD_RD_SAE_Z(z, z1, k, z2) } + +// VFMSUBADD132PD_RN_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUBADD132PD.RN_SAE zmm zmm k zmm +// VFMSUBADD132PD.RN_SAE zmm zmm zmm +// Construct and append a VFMSUBADD132PD.RN_SAE instruction to the active function. +func (c *Context) VFMSUBADD132PD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD132PD_RN_SAE(ops...)) +} + +// VFMSUBADD132PD_RN_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUBADD132PD.RN_SAE zmm zmm k zmm +// VFMSUBADD132PD.RN_SAE zmm zmm zmm +// Construct and append a VFMSUBADD132PD.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMSUBADD132PD_RN_SAE(ops ...operand.Op) { ctx.VFMSUBADD132PD_RN_SAE(ops...) } + +// VFMSUBADD132PD_RN_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD132PD.RN_SAE.Z instruction to the active function. +func (c *Context) VFMSUBADD132PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUBADD132PD_RN_SAE_Z(z, z1, k, z2)) +} + +// VFMSUBADD132PD_RN_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD132PD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD132PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUBADD132PD_RN_SAE_Z(z, z1, k, z2) } + +// VFMSUBADD132PD_RU_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUBADD132PD.RU_SAE zmm zmm k zmm +// VFMSUBADD132PD.RU_SAE zmm zmm zmm +// Construct and append a VFMSUBADD132PD.RU_SAE instruction to the active function. +func (c *Context) VFMSUBADD132PD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD132PD_RU_SAE(ops...)) +} + +// VFMSUBADD132PD_RU_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUBADD132PD.RU_SAE zmm zmm k zmm +// VFMSUBADD132PD.RU_SAE zmm zmm zmm +// Construct and append a VFMSUBADD132PD.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMSUBADD132PD_RU_SAE(ops ...operand.Op) { ctx.VFMSUBADD132PD_RU_SAE(ops...) } + +// VFMSUBADD132PD_RU_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD132PD.RU_SAE.Z instruction to the active function. +func (c *Context) VFMSUBADD132PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUBADD132PD_RU_SAE_Z(z, z1, k, z2)) +} + +// VFMSUBADD132PD_RU_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD132PD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD132PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUBADD132PD_RU_SAE_Z(z, z1, k, z2) } + +// VFMSUBADD132PD_RZ_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUBADD132PD.RZ_SAE zmm zmm k zmm +// VFMSUBADD132PD.RZ_SAE zmm zmm zmm +// Construct and append a VFMSUBADD132PD.RZ_SAE instruction to the active function. +func (c *Context) VFMSUBADD132PD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD132PD_RZ_SAE(ops...)) +} + +// VFMSUBADD132PD_RZ_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUBADD132PD.RZ_SAE zmm zmm k zmm +// VFMSUBADD132PD.RZ_SAE zmm zmm zmm +// Construct and append a VFMSUBADD132PD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMSUBADD132PD_RZ_SAE(ops ...operand.Op) { ctx.VFMSUBADD132PD_RZ_SAE(ops...) } + +// VFMSUBADD132PD_RZ_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD132PD.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMSUBADD132PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUBADD132PD_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFMSUBADD132PD_RZ_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD132PD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD132PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUBADD132PD_RZ_SAE_Z(z, z1, k, z2) } + +// VFMSUBADD132PD_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PD.Z m128 xmm k xmm +// VFMSUBADD132PD.Z m256 ymm k ymm +// VFMSUBADD132PD.Z xmm xmm k xmm +// VFMSUBADD132PD.Z ymm ymm k ymm +// VFMSUBADD132PD.Z m512 zmm k zmm +// VFMSUBADD132PD.Z zmm zmm k zmm +// Construct and append a VFMSUBADD132PD.Z instruction to the active function. +func (c *Context) VFMSUBADD132PD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMSUBADD132PD_Z(mxyz, xyz, k, xyz1)) +} + +// VFMSUBADD132PD_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PD.Z m128 xmm k xmm +// VFMSUBADD132PD.Z m256 ymm k ymm +// VFMSUBADD132PD.Z xmm xmm k xmm +// VFMSUBADD132PD.Z ymm ymm k ymm +// VFMSUBADD132PD.Z m512 zmm k zmm +// VFMSUBADD132PD.Z zmm zmm k zmm +// Construct and append a VFMSUBADD132PD.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD132PD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFMSUBADD132PD_Z(mxyz, xyz, k, xyz1) } + +// VFMSUBADD132PS: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUBADD132PS m128 xmm xmm +// VFMSUBADD132PS m256 ymm ymm +// VFMSUBADD132PS xmm xmm xmm +// VFMSUBADD132PS ymm ymm ymm +// VFMSUBADD132PS m128 xmm k xmm +// VFMSUBADD132PS m256 ymm k ymm +// VFMSUBADD132PS xmm xmm k xmm +// VFMSUBADD132PS ymm ymm k ymm +// VFMSUBADD132PS m512 zmm k zmm +// VFMSUBADD132PS m512 zmm zmm +// VFMSUBADD132PS zmm zmm k zmm +// VFMSUBADD132PS zmm zmm zmm +// Construct and append a VFMSUBADD132PS instruction to the active function. +func (c *Context) VFMSUBADD132PS(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD132PS(ops...)) +} + +// VFMSUBADD132PS: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUBADD132PS m128 xmm xmm +// VFMSUBADD132PS m256 ymm ymm +// VFMSUBADD132PS xmm xmm xmm +// VFMSUBADD132PS ymm ymm ymm +// VFMSUBADD132PS m128 xmm k xmm +// VFMSUBADD132PS m256 ymm k ymm +// VFMSUBADD132PS xmm xmm k xmm +// VFMSUBADD132PS ymm ymm k ymm +// VFMSUBADD132PS m512 zmm k zmm +// VFMSUBADD132PS m512 zmm zmm +// VFMSUBADD132PS zmm zmm k zmm +// VFMSUBADD132PS zmm zmm zmm +// Construct and append a VFMSUBADD132PS instruction to the active function. +// Operates on the global context. +func VFMSUBADD132PS(ops ...operand.Op) { ctx.VFMSUBADD132PS(ops...) } + +// VFMSUBADD132PS_BCST: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUBADD132PS.BCST m32 xmm k xmm +// VFMSUBADD132PS.BCST m32 xmm xmm +// VFMSUBADD132PS.BCST m32 ymm k ymm +// VFMSUBADD132PS.BCST m32 ymm ymm +// VFMSUBADD132PS.BCST m32 zmm k zmm +// VFMSUBADD132PS.BCST m32 zmm zmm +// Construct and append a VFMSUBADD132PS.BCST instruction to the active function. +func (c *Context) VFMSUBADD132PS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD132PS_BCST(ops...)) +} + +// VFMSUBADD132PS_BCST: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUBADD132PS.BCST m32 xmm k xmm +// VFMSUBADD132PS.BCST m32 xmm xmm +// VFMSUBADD132PS.BCST m32 ymm k ymm +// VFMSUBADD132PS.BCST m32 ymm ymm +// VFMSUBADD132PS.BCST m32 zmm k zmm +// VFMSUBADD132PS.BCST m32 zmm zmm +// Construct and append a VFMSUBADD132PS.BCST instruction to the active function. +// Operates on the global context. +func VFMSUBADD132PS_BCST(ops ...operand.Op) { ctx.VFMSUBADD132PS_BCST(ops...) } + +// VFMSUBADD132PS_BCST_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PS.BCST.Z m32 xmm k xmm +// VFMSUBADD132PS.BCST.Z m32 ymm k ymm +// VFMSUBADD132PS.BCST.Z m32 zmm k zmm +// Construct and append a VFMSUBADD132PS.BCST.Z instruction to the active function. +func (c *Context) VFMSUBADD132PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMSUBADD132PS_BCST_Z(m, xyz, k, xyz1)) +} + +// VFMSUBADD132PS_BCST_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PS.BCST.Z m32 xmm k xmm +// VFMSUBADD132PS.BCST.Z m32 ymm k ymm +// VFMSUBADD132PS.BCST.Z m32 zmm k zmm +// Construct and append a VFMSUBADD132PS.BCST.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD132PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFMSUBADD132PS_BCST_Z(m, xyz, k, xyz1) } + +// VFMSUBADD132PS_RD_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUBADD132PS.RD_SAE zmm zmm k zmm +// VFMSUBADD132PS.RD_SAE zmm zmm zmm +// Construct and append a VFMSUBADD132PS.RD_SAE instruction to the active function. +func (c *Context) VFMSUBADD132PS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD132PS_RD_SAE(ops...)) +} + +// VFMSUBADD132PS_RD_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUBADD132PS.RD_SAE zmm zmm k zmm +// VFMSUBADD132PS.RD_SAE zmm zmm zmm +// Construct and append a VFMSUBADD132PS.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMSUBADD132PS_RD_SAE(ops ...operand.Op) { ctx.VFMSUBADD132PS_RD_SAE(ops...) } + +// VFMSUBADD132PS_RD_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD132PS.RD_SAE.Z instruction to the active function. +func (c *Context) VFMSUBADD132PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUBADD132PS_RD_SAE_Z(z, z1, k, z2)) +} + +// VFMSUBADD132PS_RD_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD132PS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD132PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUBADD132PS_RD_SAE_Z(z, z1, k, z2) } + +// VFMSUBADD132PS_RN_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUBADD132PS.RN_SAE zmm zmm k zmm +// VFMSUBADD132PS.RN_SAE zmm zmm zmm +// Construct and append a VFMSUBADD132PS.RN_SAE instruction to the active function. +func (c *Context) VFMSUBADD132PS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD132PS_RN_SAE(ops...)) +} + +// VFMSUBADD132PS_RN_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUBADD132PS.RN_SAE zmm zmm k zmm +// VFMSUBADD132PS.RN_SAE zmm zmm zmm +// Construct and append a VFMSUBADD132PS.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMSUBADD132PS_RN_SAE(ops ...operand.Op) { ctx.VFMSUBADD132PS_RN_SAE(ops...) } + +// VFMSUBADD132PS_RN_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD132PS.RN_SAE.Z instruction to the active function. +func (c *Context) VFMSUBADD132PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUBADD132PS_RN_SAE_Z(z, z1, k, z2)) +} + +// VFMSUBADD132PS_RN_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD132PS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD132PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUBADD132PS_RN_SAE_Z(z, z1, k, z2) } + +// VFMSUBADD132PS_RU_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUBADD132PS.RU_SAE zmm zmm k zmm +// VFMSUBADD132PS.RU_SAE zmm zmm zmm +// Construct and append a VFMSUBADD132PS.RU_SAE instruction to the active function. +func (c *Context) VFMSUBADD132PS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD132PS_RU_SAE(ops...)) +} + +// VFMSUBADD132PS_RU_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUBADD132PS.RU_SAE zmm zmm k zmm +// VFMSUBADD132PS.RU_SAE zmm zmm zmm +// Construct and append a VFMSUBADD132PS.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMSUBADD132PS_RU_SAE(ops ...operand.Op) { ctx.VFMSUBADD132PS_RU_SAE(ops...) } + +// VFMSUBADD132PS_RU_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD132PS.RU_SAE.Z instruction to the active function. +func (c *Context) VFMSUBADD132PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUBADD132PS_RU_SAE_Z(z, z1, k, z2)) +} + +// VFMSUBADD132PS_RU_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD132PS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD132PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUBADD132PS_RU_SAE_Z(z, z1, k, z2) } + +// VFMSUBADD132PS_RZ_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUBADD132PS.RZ_SAE zmm zmm k zmm +// VFMSUBADD132PS.RZ_SAE zmm zmm zmm +// Construct and append a VFMSUBADD132PS.RZ_SAE instruction to the active function. +func (c *Context) VFMSUBADD132PS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD132PS_RZ_SAE(ops...)) +} + +// VFMSUBADD132PS_RZ_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUBADD132PS.RZ_SAE zmm zmm k zmm +// VFMSUBADD132PS.RZ_SAE zmm zmm zmm +// Construct and append a VFMSUBADD132PS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMSUBADD132PS_RZ_SAE(ops ...operand.Op) { ctx.VFMSUBADD132PS_RZ_SAE(ops...) } + +// VFMSUBADD132PS_RZ_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD132PS.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMSUBADD132PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUBADD132PS_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFMSUBADD132PS_RZ_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD132PS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD132PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUBADD132PS_RZ_SAE_Z(z, z1, k, z2) } + +// VFMSUBADD132PS_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PS.Z m128 xmm k xmm +// VFMSUBADD132PS.Z m256 ymm k ymm +// VFMSUBADD132PS.Z xmm xmm k xmm +// VFMSUBADD132PS.Z ymm ymm k ymm +// VFMSUBADD132PS.Z m512 zmm k zmm +// VFMSUBADD132PS.Z zmm zmm k zmm +// Construct and append a VFMSUBADD132PS.Z instruction to the active function. +func (c *Context) VFMSUBADD132PS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMSUBADD132PS_Z(mxyz, xyz, k, xyz1)) +} + +// VFMSUBADD132PS_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PS.Z m128 xmm k xmm +// VFMSUBADD132PS.Z m256 ymm k ymm +// VFMSUBADD132PS.Z xmm xmm k xmm +// VFMSUBADD132PS.Z ymm ymm k ymm +// VFMSUBADD132PS.Z m512 zmm k zmm +// VFMSUBADD132PS.Z zmm zmm k zmm +// Construct and append a VFMSUBADD132PS.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD132PS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFMSUBADD132PS_Z(mxyz, xyz, k, xyz1) } + +// VFMSUBADD213PD: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUBADD213PD m128 xmm xmm +// VFMSUBADD213PD m256 ymm ymm +// VFMSUBADD213PD xmm xmm xmm +// VFMSUBADD213PD ymm ymm ymm +// VFMSUBADD213PD m128 xmm k xmm +// VFMSUBADD213PD m256 ymm k ymm +// VFMSUBADD213PD xmm xmm k xmm +// VFMSUBADD213PD ymm ymm k ymm +// VFMSUBADD213PD m512 zmm k zmm +// VFMSUBADD213PD m512 zmm zmm +// VFMSUBADD213PD zmm zmm k zmm +// VFMSUBADD213PD zmm zmm zmm +// Construct and append a VFMSUBADD213PD instruction to the active function. +func (c *Context) VFMSUBADD213PD(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD213PD(ops...)) +} + +// VFMSUBADD213PD: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUBADD213PD m128 xmm xmm +// VFMSUBADD213PD m256 ymm ymm +// VFMSUBADD213PD xmm xmm xmm +// VFMSUBADD213PD ymm ymm ymm +// VFMSUBADD213PD m128 xmm k xmm +// VFMSUBADD213PD m256 ymm k ymm +// VFMSUBADD213PD xmm xmm k xmm +// VFMSUBADD213PD ymm ymm k ymm +// VFMSUBADD213PD m512 zmm k zmm +// VFMSUBADD213PD m512 zmm zmm +// VFMSUBADD213PD zmm zmm k zmm +// VFMSUBADD213PD zmm zmm zmm +// Construct and append a VFMSUBADD213PD instruction to the active function. +// Operates on the global context. +func VFMSUBADD213PD(ops ...operand.Op) { ctx.VFMSUBADD213PD(ops...) } + +// VFMSUBADD213PD_BCST: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUBADD213PD.BCST m64 xmm k xmm +// VFMSUBADD213PD.BCST m64 xmm xmm +// VFMSUBADD213PD.BCST m64 ymm k ymm +// VFMSUBADD213PD.BCST m64 ymm ymm +// VFMSUBADD213PD.BCST m64 zmm k zmm +// VFMSUBADD213PD.BCST m64 zmm zmm +// Construct and append a VFMSUBADD213PD.BCST instruction to the active function. +func (c *Context) VFMSUBADD213PD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD213PD_BCST(ops...)) +} + +// VFMSUBADD213PD_BCST: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUBADD213PD.BCST m64 xmm k xmm +// VFMSUBADD213PD.BCST m64 xmm xmm +// VFMSUBADD213PD.BCST m64 ymm k ymm +// VFMSUBADD213PD.BCST m64 ymm ymm +// VFMSUBADD213PD.BCST m64 zmm k zmm +// VFMSUBADD213PD.BCST m64 zmm zmm +// Construct and append a VFMSUBADD213PD.BCST instruction to the active function. +// Operates on the global context. +func VFMSUBADD213PD_BCST(ops ...operand.Op) { ctx.VFMSUBADD213PD_BCST(ops...) } + +// VFMSUBADD213PD_BCST_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PD.BCST.Z m64 xmm k xmm +// VFMSUBADD213PD.BCST.Z m64 ymm k ymm +// VFMSUBADD213PD.BCST.Z m64 zmm k zmm +// Construct and append a VFMSUBADD213PD.BCST.Z instruction to the active function. +func (c *Context) VFMSUBADD213PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMSUBADD213PD_BCST_Z(m, xyz, k, xyz1)) +} + +// VFMSUBADD213PD_BCST_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PD.BCST.Z m64 xmm k xmm +// VFMSUBADD213PD.BCST.Z m64 ymm k ymm +// VFMSUBADD213PD.BCST.Z m64 zmm k zmm +// Construct and append a VFMSUBADD213PD.BCST.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD213PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFMSUBADD213PD_BCST_Z(m, xyz, k, xyz1) } + +// VFMSUBADD213PD_RD_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUBADD213PD.RD_SAE zmm zmm k zmm +// VFMSUBADD213PD.RD_SAE zmm zmm zmm +// Construct and append a VFMSUBADD213PD.RD_SAE instruction to the active function. +func (c *Context) VFMSUBADD213PD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD213PD_RD_SAE(ops...)) +} + +// VFMSUBADD213PD_RD_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUBADD213PD.RD_SAE zmm zmm k zmm +// VFMSUBADD213PD.RD_SAE zmm zmm zmm +// Construct and append a VFMSUBADD213PD.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMSUBADD213PD_RD_SAE(ops ...operand.Op) { ctx.VFMSUBADD213PD_RD_SAE(ops...) } + +// VFMSUBADD213PD_RD_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD213PD.RD_SAE.Z instruction to the active function. +func (c *Context) VFMSUBADD213PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUBADD213PD_RD_SAE_Z(z, z1, k, z2)) +} + +// VFMSUBADD213PD_RD_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD213PD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD213PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUBADD213PD_RD_SAE_Z(z, z1, k, z2) } + +// VFMSUBADD213PD_RN_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUBADD213PD.RN_SAE zmm zmm k zmm +// VFMSUBADD213PD.RN_SAE zmm zmm zmm +// Construct and append a VFMSUBADD213PD.RN_SAE instruction to the active function. +func (c *Context) VFMSUBADD213PD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD213PD_RN_SAE(ops...)) +} + +// VFMSUBADD213PD_RN_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUBADD213PD.RN_SAE zmm zmm k zmm +// VFMSUBADD213PD.RN_SAE zmm zmm zmm +// Construct and append a VFMSUBADD213PD.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMSUBADD213PD_RN_SAE(ops ...operand.Op) { ctx.VFMSUBADD213PD_RN_SAE(ops...) } + +// VFMSUBADD213PD_RN_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD213PD.RN_SAE.Z instruction to the active function. +func (c *Context) VFMSUBADD213PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUBADD213PD_RN_SAE_Z(z, z1, k, z2)) +} + +// VFMSUBADD213PD_RN_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD213PD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD213PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUBADD213PD_RN_SAE_Z(z, z1, k, z2) } + +// VFMSUBADD213PD_RU_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUBADD213PD.RU_SAE zmm zmm k zmm +// VFMSUBADD213PD.RU_SAE zmm zmm zmm +// Construct and append a VFMSUBADD213PD.RU_SAE instruction to the active function. +func (c *Context) VFMSUBADD213PD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD213PD_RU_SAE(ops...)) +} + +// VFMSUBADD213PD_RU_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUBADD213PD.RU_SAE zmm zmm k zmm +// VFMSUBADD213PD.RU_SAE zmm zmm zmm +// Construct and append a VFMSUBADD213PD.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMSUBADD213PD_RU_SAE(ops ...operand.Op) { ctx.VFMSUBADD213PD_RU_SAE(ops...) } + +// VFMSUBADD213PD_RU_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD213PD.RU_SAE.Z instruction to the active function. +func (c *Context) VFMSUBADD213PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUBADD213PD_RU_SAE_Z(z, z1, k, z2)) +} + +// VFMSUBADD213PD_RU_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD213PD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD213PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUBADD213PD_RU_SAE_Z(z, z1, k, z2) } + +// VFMSUBADD213PD_RZ_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUBADD213PD.RZ_SAE zmm zmm k zmm +// VFMSUBADD213PD.RZ_SAE zmm zmm zmm +// Construct and append a VFMSUBADD213PD.RZ_SAE instruction to the active function. +func (c *Context) VFMSUBADD213PD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD213PD_RZ_SAE(ops...)) +} + +// VFMSUBADD213PD_RZ_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUBADD213PD.RZ_SAE zmm zmm k zmm +// VFMSUBADD213PD.RZ_SAE zmm zmm zmm +// Construct and append a VFMSUBADD213PD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMSUBADD213PD_RZ_SAE(ops ...operand.Op) { ctx.VFMSUBADD213PD_RZ_SAE(ops...) } + +// VFMSUBADD213PD_RZ_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD213PD.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMSUBADD213PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUBADD213PD_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFMSUBADD213PD_RZ_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD213PD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD213PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUBADD213PD_RZ_SAE_Z(z, z1, k, z2) } + +// VFMSUBADD213PD_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PD.Z m128 xmm k xmm +// VFMSUBADD213PD.Z m256 ymm k ymm +// VFMSUBADD213PD.Z xmm xmm k xmm +// VFMSUBADD213PD.Z ymm ymm k ymm +// VFMSUBADD213PD.Z m512 zmm k zmm +// VFMSUBADD213PD.Z zmm zmm k zmm +// Construct and append a VFMSUBADD213PD.Z instruction to the active function. +func (c *Context) VFMSUBADD213PD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMSUBADD213PD_Z(mxyz, xyz, k, xyz1)) +} + +// VFMSUBADD213PD_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PD.Z m128 xmm k xmm +// VFMSUBADD213PD.Z m256 ymm k ymm +// VFMSUBADD213PD.Z xmm xmm k xmm +// VFMSUBADD213PD.Z ymm ymm k ymm +// VFMSUBADD213PD.Z m512 zmm k zmm +// VFMSUBADD213PD.Z zmm zmm k zmm +// Construct and append a VFMSUBADD213PD.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD213PD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFMSUBADD213PD_Z(mxyz, xyz, k, xyz1) } + +// VFMSUBADD213PS: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUBADD213PS m128 xmm xmm +// VFMSUBADD213PS m256 ymm ymm +// VFMSUBADD213PS xmm xmm xmm +// VFMSUBADD213PS ymm ymm ymm +// VFMSUBADD213PS m128 xmm k xmm +// VFMSUBADD213PS m256 ymm k ymm +// VFMSUBADD213PS xmm xmm k xmm +// VFMSUBADD213PS ymm ymm k ymm +// VFMSUBADD213PS m512 zmm k zmm +// VFMSUBADD213PS m512 zmm zmm +// VFMSUBADD213PS zmm zmm k zmm +// VFMSUBADD213PS zmm zmm zmm +// Construct and append a VFMSUBADD213PS instruction to the active function. +func (c *Context) VFMSUBADD213PS(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD213PS(ops...)) +} + +// VFMSUBADD213PS: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUBADD213PS m128 xmm xmm +// VFMSUBADD213PS m256 ymm ymm +// VFMSUBADD213PS xmm xmm xmm +// VFMSUBADD213PS ymm ymm ymm +// VFMSUBADD213PS m128 xmm k xmm +// VFMSUBADD213PS m256 ymm k ymm +// VFMSUBADD213PS xmm xmm k xmm +// VFMSUBADD213PS ymm ymm k ymm +// VFMSUBADD213PS m512 zmm k zmm +// VFMSUBADD213PS m512 zmm zmm +// VFMSUBADD213PS zmm zmm k zmm +// VFMSUBADD213PS zmm zmm zmm +// Construct and append a VFMSUBADD213PS instruction to the active function. +// Operates on the global context. +func VFMSUBADD213PS(ops ...operand.Op) { ctx.VFMSUBADD213PS(ops...) } + +// VFMSUBADD213PS_BCST: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUBADD213PS.BCST m32 xmm k xmm +// VFMSUBADD213PS.BCST m32 xmm xmm +// VFMSUBADD213PS.BCST m32 ymm k ymm +// VFMSUBADD213PS.BCST m32 ymm ymm +// VFMSUBADD213PS.BCST m32 zmm k zmm +// VFMSUBADD213PS.BCST m32 zmm zmm +// Construct and append a VFMSUBADD213PS.BCST instruction to the active function. +func (c *Context) VFMSUBADD213PS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD213PS_BCST(ops...)) +} + +// VFMSUBADD213PS_BCST: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUBADD213PS.BCST m32 xmm k xmm +// VFMSUBADD213PS.BCST m32 xmm xmm +// VFMSUBADD213PS.BCST m32 ymm k ymm +// VFMSUBADD213PS.BCST m32 ymm ymm +// VFMSUBADD213PS.BCST m32 zmm k zmm +// VFMSUBADD213PS.BCST m32 zmm zmm +// Construct and append a VFMSUBADD213PS.BCST instruction to the active function. +// Operates on the global context. +func VFMSUBADD213PS_BCST(ops ...operand.Op) { ctx.VFMSUBADD213PS_BCST(ops...) } + +// VFMSUBADD213PS_BCST_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PS.BCST.Z m32 xmm k xmm +// VFMSUBADD213PS.BCST.Z m32 ymm k ymm +// VFMSUBADD213PS.BCST.Z m32 zmm k zmm +// Construct and append a VFMSUBADD213PS.BCST.Z instruction to the active function. +func (c *Context) VFMSUBADD213PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMSUBADD213PS_BCST_Z(m, xyz, k, xyz1)) +} + +// VFMSUBADD213PS_BCST_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PS.BCST.Z m32 xmm k xmm +// VFMSUBADD213PS.BCST.Z m32 ymm k ymm +// VFMSUBADD213PS.BCST.Z m32 zmm k zmm +// Construct and append a VFMSUBADD213PS.BCST.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD213PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFMSUBADD213PS_BCST_Z(m, xyz, k, xyz1) } + +// VFMSUBADD213PS_RD_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUBADD213PS.RD_SAE zmm zmm k zmm +// VFMSUBADD213PS.RD_SAE zmm zmm zmm +// Construct and append a VFMSUBADD213PS.RD_SAE instruction to the active function. +func (c *Context) VFMSUBADD213PS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD213PS_RD_SAE(ops...)) +} + +// VFMSUBADD213PS_RD_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUBADD213PS.RD_SAE zmm zmm k zmm +// VFMSUBADD213PS.RD_SAE zmm zmm zmm +// Construct and append a VFMSUBADD213PS.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMSUBADD213PS_RD_SAE(ops ...operand.Op) { ctx.VFMSUBADD213PS_RD_SAE(ops...) } + +// VFMSUBADD213PS_RD_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD213PS.RD_SAE.Z instruction to the active function. +func (c *Context) VFMSUBADD213PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUBADD213PS_RD_SAE_Z(z, z1, k, z2)) +} + +// VFMSUBADD213PS_RD_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD213PS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD213PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUBADD213PS_RD_SAE_Z(z, z1, k, z2) } + +// VFMSUBADD213PS_RN_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUBADD213PS.RN_SAE zmm zmm k zmm +// VFMSUBADD213PS.RN_SAE zmm zmm zmm +// Construct and append a VFMSUBADD213PS.RN_SAE instruction to the active function. +func (c *Context) VFMSUBADD213PS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD213PS_RN_SAE(ops...)) +} + +// VFMSUBADD213PS_RN_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUBADD213PS.RN_SAE zmm zmm k zmm +// VFMSUBADD213PS.RN_SAE zmm zmm zmm +// Construct and append a VFMSUBADD213PS.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMSUBADD213PS_RN_SAE(ops ...operand.Op) { ctx.VFMSUBADD213PS_RN_SAE(ops...) } + +// VFMSUBADD213PS_RN_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD213PS.RN_SAE.Z instruction to the active function. +func (c *Context) VFMSUBADD213PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUBADD213PS_RN_SAE_Z(z, z1, k, z2)) +} + +// VFMSUBADD213PS_RN_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD213PS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD213PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUBADD213PS_RN_SAE_Z(z, z1, k, z2) } + +// VFMSUBADD213PS_RU_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUBADD213PS.RU_SAE zmm zmm k zmm +// VFMSUBADD213PS.RU_SAE zmm zmm zmm +// Construct and append a VFMSUBADD213PS.RU_SAE instruction to the active function. +func (c *Context) VFMSUBADD213PS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD213PS_RU_SAE(ops...)) +} + +// VFMSUBADD213PS_RU_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUBADD213PS.RU_SAE zmm zmm k zmm +// VFMSUBADD213PS.RU_SAE zmm zmm zmm +// Construct and append a VFMSUBADD213PS.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMSUBADD213PS_RU_SAE(ops ...operand.Op) { ctx.VFMSUBADD213PS_RU_SAE(ops...) } + +// VFMSUBADD213PS_RU_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD213PS.RU_SAE.Z instruction to the active function. +func (c *Context) VFMSUBADD213PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUBADD213PS_RU_SAE_Z(z, z1, k, z2)) +} + +// VFMSUBADD213PS_RU_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD213PS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD213PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUBADD213PS_RU_SAE_Z(z, z1, k, z2) } + +// VFMSUBADD213PS_RZ_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUBADD213PS.RZ_SAE zmm zmm k zmm +// VFMSUBADD213PS.RZ_SAE zmm zmm zmm +// Construct and append a VFMSUBADD213PS.RZ_SAE instruction to the active function. +func (c *Context) VFMSUBADD213PS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD213PS_RZ_SAE(ops...)) +} + +// VFMSUBADD213PS_RZ_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUBADD213PS.RZ_SAE zmm zmm k zmm +// VFMSUBADD213PS.RZ_SAE zmm zmm zmm +// Construct and append a VFMSUBADD213PS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMSUBADD213PS_RZ_SAE(ops ...operand.Op) { ctx.VFMSUBADD213PS_RZ_SAE(ops...) } + +// VFMSUBADD213PS_RZ_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD213PS.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMSUBADD213PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUBADD213PS_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFMSUBADD213PS_RZ_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD213PS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD213PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUBADD213PS_RZ_SAE_Z(z, z1, k, z2) } + +// VFMSUBADD213PS_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PS.Z m128 xmm k xmm +// VFMSUBADD213PS.Z m256 ymm k ymm +// VFMSUBADD213PS.Z xmm xmm k xmm +// VFMSUBADD213PS.Z ymm ymm k ymm +// VFMSUBADD213PS.Z m512 zmm k zmm +// VFMSUBADD213PS.Z zmm zmm k zmm +// Construct and append a VFMSUBADD213PS.Z instruction to the active function. +func (c *Context) VFMSUBADD213PS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMSUBADD213PS_Z(mxyz, xyz, k, xyz1)) +} + +// VFMSUBADD213PS_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PS.Z m128 xmm k xmm +// VFMSUBADD213PS.Z m256 ymm k ymm +// VFMSUBADD213PS.Z xmm xmm k xmm +// VFMSUBADD213PS.Z ymm ymm k ymm +// VFMSUBADD213PS.Z m512 zmm k zmm +// VFMSUBADD213PS.Z zmm zmm k zmm +// Construct and append a VFMSUBADD213PS.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD213PS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFMSUBADD213PS_Z(mxyz, xyz, k, xyz1) } + +// VFMSUBADD231PD: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUBADD231PD m128 xmm xmm +// VFMSUBADD231PD m256 ymm ymm +// VFMSUBADD231PD xmm xmm xmm +// VFMSUBADD231PD ymm ymm ymm +// VFMSUBADD231PD m128 xmm k xmm +// VFMSUBADD231PD m256 ymm k ymm +// VFMSUBADD231PD xmm xmm k xmm +// VFMSUBADD231PD ymm ymm k ymm +// VFMSUBADD231PD m512 zmm k zmm +// VFMSUBADD231PD m512 zmm zmm +// VFMSUBADD231PD zmm zmm k zmm +// VFMSUBADD231PD zmm zmm zmm +// Construct and append a VFMSUBADD231PD instruction to the active function. +func (c *Context) VFMSUBADD231PD(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD231PD(ops...)) +} + +// VFMSUBADD231PD: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUBADD231PD m128 xmm xmm +// VFMSUBADD231PD m256 ymm ymm +// VFMSUBADD231PD xmm xmm xmm +// VFMSUBADD231PD ymm ymm ymm +// VFMSUBADD231PD m128 xmm k xmm +// VFMSUBADD231PD m256 ymm k ymm +// VFMSUBADD231PD xmm xmm k xmm +// VFMSUBADD231PD ymm ymm k ymm +// VFMSUBADD231PD m512 zmm k zmm +// VFMSUBADD231PD m512 zmm zmm +// VFMSUBADD231PD zmm zmm k zmm +// VFMSUBADD231PD zmm zmm zmm +// Construct and append a VFMSUBADD231PD instruction to the active function. +// Operates on the global context. +func VFMSUBADD231PD(ops ...operand.Op) { ctx.VFMSUBADD231PD(ops...) } + +// VFMSUBADD231PD_BCST: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUBADD231PD.BCST m64 xmm k xmm +// VFMSUBADD231PD.BCST m64 xmm xmm +// VFMSUBADD231PD.BCST m64 ymm k ymm +// VFMSUBADD231PD.BCST m64 ymm ymm +// VFMSUBADD231PD.BCST m64 zmm k zmm +// VFMSUBADD231PD.BCST m64 zmm zmm +// Construct and append a VFMSUBADD231PD.BCST instruction to the active function. +func (c *Context) VFMSUBADD231PD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD231PD_BCST(ops...)) +} + +// VFMSUBADD231PD_BCST: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUBADD231PD.BCST m64 xmm k xmm +// VFMSUBADD231PD.BCST m64 xmm xmm +// VFMSUBADD231PD.BCST m64 ymm k ymm +// VFMSUBADD231PD.BCST m64 ymm ymm +// VFMSUBADD231PD.BCST m64 zmm k zmm +// VFMSUBADD231PD.BCST m64 zmm zmm +// Construct and append a VFMSUBADD231PD.BCST instruction to the active function. +// Operates on the global context. +func VFMSUBADD231PD_BCST(ops ...operand.Op) { ctx.VFMSUBADD231PD_BCST(ops...) } + +// VFMSUBADD231PD_BCST_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PD.BCST.Z m64 xmm k xmm +// VFMSUBADD231PD.BCST.Z m64 ymm k ymm +// VFMSUBADD231PD.BCST.Z m64 zmm k zmm +// Construct and append a VFMSUBADD231PD.BCST.Z instruction to the active function. +func (c *Context) VFMSUBADD231PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMSUBADD231PD_BCST_Z(m, xyz, k, xyz1)) +} + +// VFMSUBADD231PD_BCST_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PD.BCST.Z m64 xmm k xmm +// VFMSUBADD231PD.BCST.Z m64 ymm k ymm +// VFMSUBADD231PD.BCST.Z m64 zmm k zmm +// Construct and append a VFMSUBADD231PD.BCST.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD231PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFMSUBADD231PD_BCST_Z(m, xyz, k, xyz1) } + +// VFMSUBADD231PD_RD_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUBADD231PD.RD_SAE zmm zmm k zmm +// VFMSUBADD231PD.RD_SAE zmm zmm zmm +// Construct and append a VFMSUBADD231PD.RD_SAE instruction to the active function. +func (c *Context) VFMSUBADD231PD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD231PD_RD_SAE(ops...)) +} + +// VFMSUBADD231PD_RD_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUBADD231PD.RD_SAE zmm zmm k zmm +// VFMSUBADD231PD.RD_SAE zmm zmm zmm +// Construct and append a VFMSUBADD231PD.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMSUBADD231PD_RD_SAE(ops ...operand.Op) { ctx.VFMSUBADD231PD_RD_SAE(ops...) } + +// VFMSUBADD231PD_RD_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD231PD.RD_SAE.Z instruction to the active function. +func (c *Context) VFMSUBADD231PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUBADD231PD_RD_SAE_Z(z, z1, k, z2)) +} + +// VFMSUBADD231PD_RD_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD231PD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD231PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUBADD231PD_RD_SAE_Z(z, z1, k, z2) } + +// VFMSUBADD231PD_RN_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUBADD231PD.RN_SAE zmm zmm k zmm +// VFMSUBADD231PD.RN_SAE zmm zmm zmm +// Construct and append a VFMSUBADD231PD.RN_SAE instruction to the active function. +func (c *Context) VFMSUBADD231PD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD231PD_RN_SAE(ops...)) +} + +// VFMSUBADD231PD_RN_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUBADD231PD.RN_SAE zmm zmm k zmm +// VFMSUBADD231PD.RN_SAE zmm zmm zmm +// Construct and append a VFMSUBADD231PD.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMSUBADD231PD_RN_SAE(ops ...operand.Op) { ctx.VFMSUBADD231PD_RN_SAE(ops...) } + +// VFMSUBADD231PD_RN_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD231PD.RN_SAE.Z instruction to the active function. +func (c *Context) VFMSUBADD231PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUBADD231PD_RN_SAE_Z(z, z1, k, z2)) +} + +// VFMSUBADD231PD_RN_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD231PD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD231PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUBADD231PD_RN_SAE_Z(z, z1, k, z2) } + +// VFMSUBADD231PD_RU_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUBADD231PD.RU_SAE zmm zmm k zmm +// VFMSUBADD231PD.RU_SAE zmm zmm zmm +// Construct and append a VFMSUBADD231PD.RU_SAE instruction to the active function. +func (c *Context) VFMSUBADD231PD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD231PD_RU_SAE(ops...)) +} + +// VFMSUBADD231PD_RU_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUBADD231PD.RU_SAE zmm zmm k zmm +// VFMSUBADD231PD.RU_SAE zmm zmm zmm +// Construct and append a VFMSUBADD231PD.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMSUBADD231PD_RU_SAE(ops ...operand.Op) { ctx.VFMSUBADD231PD_RU_SAE(ops...) } + +// VFMSUBADD231PD_RU_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD231PD.RU_SAE.Z instruction to the active function. +func (c *Context) VFMSUBADD231PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUBADD231PD_RU_SAE_Z(z, z1, k, z2)) +} + +// VFMSUBADD231PD_RU_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD231PD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD231PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUBADD231PD_RU_SAE_Z(z, z1, k, z2) } + +// VFMSUBADD231PD_RZ_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUBADD231PD.RZ_SAE zmm zmm k zmm +// VFMSUBADD231PD.RZ_SAE zmm zmm zmm +// Construct and append a VFMSUBADD231PD.RZ_SAE instruction to the active function. +func (c *Context) VFMSUBADD231PD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD231PD_RZ_SAE(ops...)) +} + +// VFMSUBADD231PD_RZ_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUBADD231PD.RZ_SAE zmm zmm k zmm +// VFMSUBADD231PD.RZ_SAE zmm zmm zmm +// Construct and append a VFMSUBADD231PD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMSUBADD231PD_RZ_SAE(ops ...operand.Op) { ctx.VFMSUBADD231PD_RZ_SAE(ops...) } + +// VFMSUBADD231PD_RZ_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD231PD.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMSUBADD231PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUBADD231PD_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFMSUBADD231PD_RZ_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD231PD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD231PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUBADD231PD_RZ_SAE_Z(z, z1, k, z2) } + +// VFMSUBADD231PD_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PD.Z m128 xmm k xmm +// VFMSUBADD231PD.Z m256 ymm k ymm +// VFMSUBADD231PD.Z xmm xmm k xmm +// VFMSUBADD231PD.Z ymm ymm k ymm +// VFMSUBADD231PD.Z m512 zmm k zmm +// VFMSUBADD231PD.Z zmm zmm k zmm +// Construct and append a VFMSUBADD231PD.Z instruction to the active function. +func (c *Context) VFMSUBADD231PD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMSUBADD231PD_Z(mxyz, xyz, k, xyz1)) +} + +// VFMSUBADD231PD_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PD.Z m128 xmm k xmm +// VFMSUBADD231PD.Z m256 ymm k ymm +// VFMSUBADD231PD.Z xmm xmm k xmm +// VFMSUBADD231PD.Z ymm ymm k ymm +// VFMSUBADD231PD.Z m512 zmm k zmm +// VFMSUBADD231PD.Z zmm zmm k zmm +// Construct and append a VFMSUBADD231PD.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD231PD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFMSUBADD231PD_Z(mxyz, xyz, k, xyz1) } + +// VFMSUBADD231PS: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUBADD231PS m128 xmm xmm +// VFMSUBADD231PS m256 ymm ymm +// VFMSUBADD231PS xmm xmm xmm +// VFMSUBADD231PS ymm ymm ymm +// VFMSUBADD231PS m128 xmm k xmm +// VFMSUBADD231PS m256 ymm k ymm +// VFMSUBADD231PS xmm xmm k xmm +// VFMSUBADD231PS ymm ymm k ymm +// VFMSUBADD231PS m512 zmm k zmm +// VFMSUBADD231PS m512 zmm zmm +// VFMSUBADD231PS zmm zmm k zmm +// VFMSUBADD231PS zmm zmm zmm +// Construct and append a VFMSUBADD231PS instruction to the active function. +func (c *Context) VFMSUBADD231PS(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD231PS(ops...)) +} + +// VFMSUBADD231PS: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUBADD231PS m128 xmm xmm +// VFMSUBADD231PS m256 ymm ymm +// VFMSUBADD231PS xmm xmm xmm +// VFMSUBADD231PS ymm ymm ymm +// VFMSUBADD231PS m128 xmm k xmm +// VFMSUBADD231PS m256 ymm k ymm +// VFMSUBADD231PS xmm xmm k xmm +// VFMSUBADD231PS ymm ymm k ymm +// VFMSUBADD231PS m512 zmm k zmm +// VFMSUBADD231PS m512 zmm zmm +// VFMSUBADD231PS zmm zmm k zmm +// VFMSUBADD231PS zmm zmm zmm +// Construct and append a VFMSUBADD231PS instruction to the active function. +// Operates on the global context. +func VFMSUBADD231PS(ops ...operand.Op) { ctx.VFMSUBADD231PS(ops...) } + +// VFMSUBADD231PS_BCST: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUBADD231PS.BCST m32 xmm k xmm +// VFMSUBADD231PS.BCST m32 xmm xmm +// VFMSUBADD231PS.BCST m32 ymm k ymm +// VFMSUBADD231PS.BCST m32 ymm ymm +// VFMSUBADD231PS.BCST m32 zmm k zmm +// VFMSUBADD231PS.BCST m32 zmm zmm +// Construct and append a VFMSUBADD231PS.BCST instruction to the active function. +func (c *Context) VFMSUBADD231PS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD231PS_BCST(ops...)) +} + +// VFMSUBADD231PS_BCST: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUBADD231PS.BCST m32 xmm k xmm +// VFMSUBADD231PS.BCST m32 xmm xmm +// VFMSUBADD231PS.BCST m32 ymm k ymm +// VFMSUBADD231PS.BCST m32 ymm ymm +// VFMSUBADD231PS.BCST m32 zmm k zmm +// VFMSUBADD231PS.BCST m32 zmm zmm +// Construct and append a VFMSUBADD231PS.BCST instruction to the active function. +// Operates on the global context. +func VFMSUBADD231PS_BCST(ops ...operand.Op) { ctx.VFMSUBADD231PS_BCST(ops...) } + +// VFMSUBADD231PS_BCST_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PS.BCST.Z m32 xmm k xmm +// VFMSUBADD231PS.BCST.Z m32 ymm k ymm +// VFMSUBADD231PS.BCST.Z m32 zmm k zmm +// Construct and append a VFMSUBADD231PS.BCST.Z instruction to the active function. +func (c *Context) VFMSUBADD231PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMSUBADD231PS_BCST_Z(m, xyz, k, xyz1)) +} + +// VFMSUBADD231PS_BCST_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PS.BCST.Z m32 xmm k xmm +// VFMSUBADD231PS.BCST.Z m32 ymm k ymm +// VFMSUBADD231PS.BCST.Z m32 zmm k zmm +// Construct and append a VFMSUBADD231PS.BCST.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD231PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFMSUBADD231PS_BCST_Z(m, xyz, k, xyz1) } + +// VFMSUBADD231PS_RD_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUBADD231PS.RD_SAE zmm zmm k zmm +// VFMSUBADD231PS.RD_SAE zmm zmm zmm +// Construct and append a VFMSUBADD231PS.RD_SAE instruction to the active function. +func (c *Context) VFMSUBADD231PS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD231PS_RD_SAE(ops...)) +} + +// VFMSUBADD231PS_RD_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUBADD231PS.RD_SAE zmm zmm k zmm +// VFMSUBADD231PS.RD_SAE zmm zmm zmm +// Construct and append a VFMSUBADD231PS.RD_SAE instruction to the active function. +// Operates on the global context. +func VFMSUBADD231PS_RD_SAE(ops ...operand.Op) { ctx.VFMSUBADD231PS_RD_SAE(ops...) } + +// VFMSUBADD231PS_RD_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD231PS.RD_SAE.Z instruction to the active function. +func (c *Context) VFMSUBADD231PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUBADD231PS_RD_SAE_Z(z, z1, k, z2)) +} + +// VFMSUBADD231PS_RD_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD231PS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD231PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUBADD231PS_RD_SAE_Z(z, z1, k, z2) } + +// VFMSUBADD231PS_RN_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUBADD231PS.RN_SAE zmm zmm k zmm +// VFMSUBADD231PS.RN_SAE zmm zmm zmm +// Construct and append a VFMSUBADD231PS.RN_SAE instruction to the active function. +func (c *Context) VFMSUBADD231PS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD231PS_RN_SAE(ops...)) +} + +// VFMSUBADD231PS_RN_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUBADD231PS.RN_SAE zmm zmm k zmm +// VFMSUBADD231PS.RN_SAE zmm zmm zmm +// Construct and append a VFMSUBADD231PS.RN_SAE instruction to the active function. +// Operates on the global context. +func VFMSUBADD231PS_RN_SAE(ops ...operand.Op) { ctx.VFMSUBADD231PS_RN_SAE(ops...) } + +// VFMSUBADD231PS_RN_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD231PS.RN_SAE.Z instruction to the active function. +func (c *Context) VFMSUBADD231PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUBADD231PS_RN_SAE_Z(z, z1, k, z2)) +} + +// VFMSUBADD231PS_RN_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD231PS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD231PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUBADD231PS_RN_SAE_Z(z, z1, k, z2) } + +// VFMSUBADD231PS_RU_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUBADD231PS.RU_SAE zmm zmm k zmm +// VFMSUBADD231PS.RU_SAE zmm zmm zmm +// Construct and append a VFMSUBADD231PS.RU_SAE instruction to the active function. +func (c *Context) VFMSUBADD231PS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD231PS_RU_SAE(ops...)) +} + +// VFMSUBADD231PS_RU_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUBADD231PS.RU_SAE zmm zmm k zmm +// VFMSUBADD231PS.RU_SAE zmm zmm zmm +// Construct and append a VFMSUBADD231PS.RU_SAE instruction to the active function. +// Operates on the global context. +func VFMSUBADD231PS_RU_SAE(ops ...operand.Op) { ctx.VFMSUBADD231PS_RU_SAE(ops...) } + +// VFMSUBADD231PS_RU_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD231PS.RU_SAE.Z instruction to the active function. +func (c *Context) VFMSUBADD231PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUBADD231PS_RU_SAE_Z(z, z1, k, z2)) +} + +// VFMSUBADD231PS_RU_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD231PS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD231PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUBADD231PS_RU_SAE_Z(z, z1, k, z2) } + +// VFMSUBADD231PS_RZ_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUBADD231PS.RZ_SAE zmm zmm k zmm +// VFMSUBADD231PS.RZ_SAE zmm zmm zmm +// Construct and append a VFMSUBADD231PS.RZ_SAE instruction to the active function. +func (c *Context) VFMSUBADD231PS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFMSUBADD231PS_RZ_SAE(ops...)) +} + +// VFMSUBADD231PS_RZ_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUBADD231PS.RZ_SAE zmm zmm k zmm +// VFMSUBADD231PS.RZ_SAE zmm zmm zmm +// Construct and append a VFMSUBADD231PS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFMSUBADD231PS_RZ_SAE(ops ...operand.Op) { ctx.VFMSUBADD231PS_RZ_SAE(ops...) } + +// VFMSUBADD231PS_RZ_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD231PS.RZ_SAE.Z instruction to the active function. +func (c *Context) VFMSUBADD231PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFMSUBADD231PS_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFMSUBADD231PS_RZ_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFMSUBADD231PS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD231PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFMSUBADD231PS_RZ_SAE_Z(z, z1, k, z2) } + +// VFMSUBADD231PS_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PS.Z m128 xmm k xmm +// VFMSUBADD231PS.Z m256 ymm k ymm +// VFMSUBADD231PS.Z xmm xmm k xmm +// VFMSUBADD231PS.Z ymm ymm k ymm +// VFMSUBADD231PS.Z m512 zmm k zmm +// VFMSUBADD231PS.Z zmm zmm k zmm +// Construct and append a VFMSUBADD231PS.Z instruction to the active function. +func (c *Context) VFMSUBADD231PS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFMSUBADD231PS_Z(mxyz, xyz, k, xyz1)) +} + +// VFMSUBADD231PS_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PS.Z m128 xmm k xmm +// VFMSUBADD231PS.Z m256 ymm k ymm +// VFMSUBADD231PS.Z xmm xmm k xmm +// VFMSUBADD231PS.Z ymm ymm k ymm +// VFMSUBADD231PS.Z m512 zmm k zmm +// VFMSUBADD231PS.Z zmm zmm k zmm +// Construct and append a VFMSUBADD231PS.Z instruction to the active function. +// Operates on the global context. +func VFMSUBADD231PS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFMSUBADD231PS_Z(mxyz, xyz, k, xyz1) } + +// VFNMADD132PD: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD132PD m128 xmm xmm +// VFNMADD132PD m256 ymm ymm +// VFNMADD132PD xmm xmm xmm +// VFNMADD132PD ymm ymm ymm +// VFNMADD132PD m128 xmm k xmm +// VFNMADD132PD m256 ymm k ymm +// VFNMADD132PD xmm xmm k xmm +// VFNMADD132PD ymm ymm k ymm +// VFNMADD132PD m512 zmm k zmm +// VFNMADD132PD m512 zmm zmm +// VFNMADD132PD zmm zmm k zmm +// VFNMADD132PD zmm zmm zmm +// Construct and append a VFNMADD132PD instruction to the active function. +func (c *Context) VFNMADD132PD(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD132PD(ops...)) +} + +// VFNMADD132PD: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD132PD m128 xmm xmm +// VFNMADD132PD m256 ymm ymm +// VFNMADD132PD xmm xmm xmm +// VFNMADD132PD ymm ymm ymm +// VFNMADD132PD m128 xmm k xmm +// VFNMADD132PD m256 ymm k ymm +// VFNMADD132PD xmm xmm k xmm +// VFNMADD132PD ymm ymm k ymm +// VFNMADD132PD m512 zmm k zmm +// VFNMADD132PD m512 zmm zmm +// VFNMADD132PD zmm zmm k zmm +// VFNMADD132PD zmm zmm zmm +// Construct and append a VFNMADD132PD instruction to the active function. +// Operates on the global context. +func VFNMADD132PD(ops ...operand.Op) { ctx.VFNMADD132PD(ops...) } + +// VFNMADD132PD_BCST: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMADD132PD.BCST m64 xmm k xmm +// VFNMADD132PD.BCST m64 xmm xmm +// VFNMADD132PD.BCST m64 ymm k ymm +// VFNMADD132PD.BCST m64 ymm ymm +// VFNMADD132PD.BCST m64 zmm k zmm +// VFNMADD132PD.BCST m64 zmm zmm +// Construct and append a VFNMADD132PD.BCST instruction to the active function. +func (c *Context) VFNMADD132PD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD132PD_BCST(ops...)) +} + +// VFNMADD132PD_BCST: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMADD132PD.BCST m64 xmm k xmm +// VFNMADD132PD.BCST m64 xmm xmm +// VFNMADD132PD.BCST m64 ymm k ymm +// VFNMADD132PD.BCST m64 ymm ymm +// VFNMADD132PD.BCST m64 zmm k zmm +// VFNMADD132PD.BCST m64 zmm zmm +// Construct and append a VFNMADD132PD.BCST instruction to the active function. +// Operates on the global context. +func VFNMADD132PD_BCST(ops ...operand.Op) { ctx.VFNMADD132PD_BCST(ops...) } + +// VFNMADD132PD_BCST_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMADD132PD.BCST.Z m64 xmm k xmm +// VFNMADD132PD.BCST.Z m64 ymm k ymm +// VFNMADD132PD.BCST.Z m64 zmm k zmm +// Construct and append a VFNMADD132PD.BCST.Z instruction to the active function. +func (c *Context) VFNMADD132PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFNMADD132PD_BCST_Z(m, xyz, k, xyz1)) +} + +// VFNMADD132PD_BCST_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMADD132PD.BCST.Z m64 xmm k xmm +// VFNMADD132PD.BCST.Z m64 ymm k ymm +// VFNMADD132PD.BCST.Z m64 zmm k zmm +// Construct and append a VFNMADD132PD.BCST.Z instruction to the active function. +// Operates on the global context. +func VFNMADD132PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFNMADD132PD_BCST_Z(m, xyz, k, xyz1) } + +// VFNMADD132PD_RD_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD132PD.RD_SAE zmm zmm k zmm +// VFNMADD132PD.RD_SAE zmm zmm zmm +// Construct and append a VFNMADD132PD.RD_SAE instruction to the active function. +func (c *Context) VFNMADD132PD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD132PD_RD_SAE(ops...)) +} + +// VFNMADD132PD_RD_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD132PD.RD_SAE zmm zmm k zmm +// VFNMADD132PD.RD_SAE zmm zmm zmm +// Construct and append a VFNMADD132PD.RD_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD132PD_RD_SAE(ops ...operand.Op) { ctx.VFNMADD132PD_RD_SAE(ops...) } + +// VFNMADD132PD_RD_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD132PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD132PD.RD_SAE.Z instruction to the active function. +func (c *Context) VFNMADD132PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMADD132PD_RD_SAE_Z(z, z1, k, z2)) +} + +// VFNMADD132PD_RD_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD132PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD132PD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD132PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMADD132PD_RD_SAE_Z(z, z1, k, z2) } + +// VFNMADD132PD_RN_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD132PD.RN_SAE zmm zmm k zmm +// VFNMADD132PD.RN_SAE zmm zmm zmm +// Construct and append a VFNMADD132PD.RN_SAE instruction to the active function. +func (c *Context) VFNMADD132PD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD132PD_RN_SAE(ops...)) +} + +// VFNMADD132PD_RN_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD132PD.RN_SAE zmm zmm k zmm +// VFNMADD132PD.RN_SAE zmm zmm zmm +// Construct and append a VFNMADD132PD.RN_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD132PD_RN_SAE(ops ...operand.Op) { ctx.VFNMADD132PD_RN_SAE(ops...) } + +// VFNMADD132PD_RN_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD132PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD132PD.RN_SAE.Z instruction to the active function. +func (c *Context) VFNMADD132PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMADD132PD_RN_SAE_Z(z, z1, k, z2)) +} + +// VFNMADD132PD_RN_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD132PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD132PD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD132PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMADD132PD_RN_SAE_Z(z, z1, k, z2) } + +// VFNMADD132PD_RU_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD132PD.RU_SAE zmm zmm k zmm +// VFNMADD132PD.RU_SAE zmm zmm zmm +// Construct and append a VFNMADD132PD.RU_SAE instruction to the active function. +func (c *Context) VFNMADD132PD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD132PD_RU_SAE(ops...)) +} + +// VFNMADD132PD_RU_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD132PD.RU_SAE zmm zmm k zmm +// VFNMADD132PD.RU_SAE zmm zmm zmm +// Construct and append a VFNMADD132PD.RU_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD132PD_RU_SAE(ops ...operand.Op) { ctx.VFNMADD132PD_RU_SAE(ops...) } + +// VFNMADD132PD_RU_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD132PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD132PD.RU_SAE.Z instruction to the active function. +func (c *Context) VFNMADD132PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMADD132PD_RU_SAE_Z(z, z1, k, z2)) +} + +// VFNMADD132PD_RU_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD132PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD132PD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD132PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMADD132PD_RU_SAE_Z(z, z1, k, z2) } + +// VFNMADD132PD_RZ_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD132PD.RZ_SAE zmm zmm k zmm +// VFNMADD132PD.RZ_SAE zmm zmm zmm +// Construct and append a VFNMADD132PD.RZ_SAE instruction to the active function. +func (c *Context) VFNMADD132PD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD132PD_RZ_SAE(ops...)) +} + +// VFNMADD132PD_RZ_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD132PD.RZ_SAE zmm zmm k zmm +// VFNMADD132PD.RZ_SAE zmm zmm zmm +// Construct and append a VFNMADD132PD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD132PD_RZ_SAE(ops ...operand.Op) { ctx.VFNMADD132PD_RZ_SAE(ops...) } + +// VFNMADD132PD_RZ_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD132PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD132PD.RZ_SAE.Z instruction to the active function. +func (c *Context) VFNMADD132PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMADD132PD_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFNMADD132PD_RZ_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD132PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD132PD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD132PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMADD132PD_RZ_SAE_Z(z, z1, k, z2) } + +// VFNMADD132PD_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD132PD.Z m128 xmm k xmm +// VFNMADD132PD.Z m256 ymm k ymm +// VFNMADD132PD.Z xmm xmm k xmm +// VFNMADD132PD.Z ymm ymm k ymm +// VFNMADD132PD.Z m512 zmm k zmm +// VFNMADD132PD.Z zmm zmm k zmm +// Construct and append a VFNMADD132PD.Z instruction to the active function. +func (c *Context) VFNMADD132PD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFNMADD132PD_Z(mxyz, xyz, k, xyz1)) +} + +// VFNMADD132PD_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD132PD.Z m128 xmm k xmm +// VFNMADD132PD.Z m256 ymm k ymm +// VFNMADD132PD.Z xmm xmm k xmm +// VFNMADD132PD.Z ymm ymm k ymm +// VFNMADD132PD.Z m512 zmm k zmm +// VFNMADD132PD.Z zmm zmm k zmm +// Construct and append a VFNMADD132PD.Z instruction to the active function. +// Operates on the global context. +func VFNMADD132PD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFNMADD132PD_Z(mxyz, xyz, k, xyz1) } + +// VFNMADD132PS: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD132PS m128 xmm xmm +// VFNMADD132PS m256 ymm ymm +// VFNMADD132PS xmm xmm xmm +// VFNMADD132PS ymm ymm ymm +// VFNMADD132PS m128 xmm k xmm +// VFNMADD132PS m256 ymm k ymm +// VFNMADD132PS xmm xmm k xmm +// VFNMADD132PS ymm ymm k ymm +// VFNMADD132PS m512 zmm k zmm +// VFNMADD132PS m512 zmm zmm +// VFNMADD132PS zmm zmm k zmm +// VFNMADD132PS zmm zmm zmm +// Construct and append a VFNMADD132PS instruction to the active function. +func (c *Context) VFNMADD132PS(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD132PS(ops...)) +} + +// VFNMADD132PS: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD132PS m128 xmm xmm +// VFNMADD132PS m256 ymm ymm +// VFNMADD132PS xmm xmm xmm +// VFNMADD132PS ymm ymm ymm +// VFNMADD132PS m128 xmm k xmm +// VFNMADD132PS m256 ymm k ymm +// VFNMADD132PS xmm xmm k xmm +// VFNMADD132PS ymm ymm k ymm +// VFNMADD132PS m512 zmm k zmm +// VFNMADD132PS m512 zmm zmm +// VFNMADD132PS zmm zmm k zmm +// VFNMADD132PS zmm zmm zmm +// Construct and append a VFNMADD132PS instruction to the active function. +// Operates on the global context. +func VFNMADD132PS(ops ...operand.Op) { ctx.VFNMADD132PS(ops...) } + +// VFNMADD132PS_BCST: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMADD132PS.BCST m32 xmm k xmm +// VFNMADD132PS.BCST m32 xmm xmm +// VFNMADD132PS.BCST m32 ymm k ymm +// VFNMADD132PS.BCST m32 ymm ymm +// VFNMADD132PS.BCST m32 zmm k zmm +// VFNMADD132PS.BCST m32 zmm zmm +// Construct and append a VFNMADD132PS.BCST instruction to the active function. +func (c *Context) VFNMADD132PS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD132PS_BCST(ops...)) +} + +// VFNMADD132PS_BCST: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMADD132PS.BCST m32 xmm k xmm +// VFNMADD132PS.BCST m32 xmm xmm +// VFNMADD132PS.BCST m32 ymm k ymm +// VFNMADD132PS.BCST m32 ymm ymm +// VFNMADD132PS.BCST m32 zmm k zmm +// VFNMADD132PS.BCST m32 zmm zmm +// Construct and append a VFNMADD132PS.BCST instruction to the active function. +// Operates on the global context. +func VFNMADD132PS_BCST(ops ...operand.Op) { ctx.VFNMADD132PS_BCST(ops...) } + +// VFNMADD132PS_BCST_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMADD132PS.BCST.Z m32 xmm k xmm +// VFNMADD132PS.BCST.Z m32 ymm k ymm +// VFNMADD132PS.BCST.Z m32 zmm k zmm +// Construct and append a VFNMADD132PS.BCST.Z instruction to the active function. +func (c *Context) VFNMADD132PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFNMADD132PS_BCST_Z(m, xyz, k, xyz1)) +} + +// VFNMADD132PS_BCST_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMADD132PS.BCST.Z m32 xmm k xmm +// VFNMADD132PS.BCST.Z m32 ymm k ymm +// VFNMADD132PS.BCST.Z m32 zmm k zmm +// Construct and append a VFNMADD132PS.BCST.Z instruction to the active function. +// Operates on the global context. +func VFNMADD132PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFNMADD132PS_BCST_Z(m, xyz, k, xyz1) } + +// VFNMADD132PS_RD_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD132PS.RD_SAE zmm zmm k zmm +// VFNMADD132PS.RD_SAE zmm zmm zmm +// Construct and append a VFNMADD132PS.RD_SAE instruction to the active function. +func (c *Context) VFNMADD132PS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD132PS_RD_SAE(ops...)) +} + +// VFNMADD132PS_RD_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD132PS.RD_SAE zmm zmm k zmm +// VFNMADD132PS.RD_SAE zmm zmm zmm +// Construct and append a VFNMADD132PS.RD_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD132PS_RD_SAE(ops ...operand.Op) { ctx.VFNMADD132PS_RD_SAE(ops...) } + +// VFNMADD132PS_RD_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD132PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD132PS.RD_SAE.Z instruction to the active function. +func (c *Context) VFNMADD132PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMADD132PS_RD_SAE_Z(z, z1, k, z2)) +} + +// VFNMADD132PS_RD_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD132PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD132PS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD132PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMADD132PS_RD_SAE_Z(z, z1, k, z2) } + +// VFNMADD132PS_RN_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD132PS.RN_SAE zmm zmm k zmm +// VFNMADD132PS.RN_SAE zmm zmm zmm +// Construct and append a VFNMADD132PS.RN_SAE instruction to the active function. +func (c *Context) VFNMADD132PS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD132PS_RN_SAE(ops...)) +} + +// VFNMADD132PS_RN_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD132PS.RN_SAE zmm zmm k zmm +// VFNMADD132PS.RN_SAE zmm zmm zmm +// Construct and append a VFNMADD132PS.RN_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD132PS_RN_SAE(ops ...operand.Op) { ctx.VFNMADD132PS_RN_SAE(ops...) } + +// VFNMADD132PS_RN_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD132PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD132PS.RN_SAE.Z instruction to the active function. +func (c *Context) VFNMADD132PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMADD132PS_RN_SAE_Z(z, z1, k, z2)) +} + +// VFNMADD132PS_RN_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD132PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD132PS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD132PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMADD132PS_RN_SAE_Z(z, z1, k, z2) } + +// VFNMADD132PS_RU_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD132PS.RU_SAE zmm zmm k zmm +// VFNMADD132PS.RU_SAE zmm zmm zmm +// Construct and append a VFNMADD132PS.RU_SAE instruction to the active function. +func (c *Context) VFNMADD132PS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD132PS_RU_SAE(ops...)) +} + +// VFNMADD132PS_RU_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD132PS.RU_SAE zmm zmm k zmm +// VFNMADD132PS.RU_SAE zmm zmm zmm +// Construct and append a VFNMADD132PS.RU_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD132PS_RU_SAE(ops ...operand.Op) { ctx.VFNMADD132PS_RU_SAE(ops...) } + +// VFNMADD132PS_RU_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD132PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD132PS.RU_SAE.Z instruction to the active function. +func (c *Context) VFNMADD132PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMADD132PS_RU_SAE_Z(z, z1, k, z2)) +} + +// VFNMADD132PS_RU_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD132PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD132PS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD132PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMADD132PS_RU_SAE_Z(z, z1, k, z2) } + +// VFNMADD132PS_RZ_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD132PS.RZ_SAE zmm zmm k zmm +// VFNMADD132PS.RZ_SAE zmm zmm zmm +// Construct and append a VFNMADD132PS.RZ_SAE instruction to the active function. +func (c *Context) VFNMADD132PS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD132PS_RZ_SAE(ops...)) +} + +// VFNMADD132PS_RZ_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD132PS.RZ_SAE zmm zmm k zmm +// VFNMADD132PS.RZ_SAE zmm zmm zmm +// Construct and append a VFNMADD132PS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD132PS_RZ_SAE(ops ...operand.Op) { ctx.VFNMADD132PS_RZ_SAE(ops...) } + +// VFNMADD132PS_RZ_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD132PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD132PS.RZ_SAE.Z instruction to the active function. +func (c *Context) VFNMADD132PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMADD132PS_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFNMADD132PS_RZ_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD132PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD132PS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD132PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMADD132PS_RZ_SAE_Z(z, z1, k, z2) } + +// VFNMADD132PS_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD132PS.Z m128 xmm k xmm +// VFNMADD132PS.Z m256 ymm k ymm +// VFNMADD132PS.Z xmm xmm k xmm +// VFNMADD132PS.Z ymm ymm k ymm +// VFNMADD132PS.Z m512 zmm k zmm +// VFNMADD132PS.Z zmm zmm k zmm +// Construct and append a VFNMADD132PS.Z instruction to the active function. +func (c *Context) VFNMADD132PS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFNMADD132PS_Z(mxyz, xyz, k, xyz1)) +} + +// VFNMADD132PS_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD132PS.Z m128 xmm k xmm +// VFNMADD132PS.Z m256 ymm k ymm +// VFNMADD132PS.Z xmm xmm k xmm +// VFNMADD132PS.Z ymm ymm k ymm +// VFNMADD132PS.Z m512 zmm k zmm +// VFNMADD132PS.Z zmm zmm k zmm +// Construct and append a VFNMADD132PS.Z instruction to the active function. +// Operates on the global context. +func VFNMADD132PS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFNMADD132PS_Z(mxyz, xyz, k, xyz1) } + +// VFNMADD132SD: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD132SD m64 xmm xmm +// VFNMADD132SD xmm xmm xmm +// VFNMADD132SD m64 xmm k xmm +// VFNMADD132SD xmm xmm k xmm +// Construct and append a VFNMADD132SD instruction to the active function. +func (c *Context) VFNMADD132SD(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD132SD(ops...)) +} + +// VFNMADD132SD: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD132SD m64 xmm xmm +// VFNMADD132SD xmm xmm xmm +// VFNMADD132SD m64 xmm k xmm +// VFNMADD132SD xmm xmm k xmm +// Construct and append a VFNMADD132SD instruction to the active function. +// Operates on the global context. +func VFNMADD132SD(ops ...operand.Op) { ctx.VFNMADD132SD(ops...) } + +// VFNMADD132SD_RD_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD132SD.RD_SAE xmm xmm k xmm +// VFNMADD132SD.RD_SAE xmm xmm xmm +// Construct and append a VFNMADD132SD.RD_SAE instruction to the active function. +func (c *Context) VFNMADD132SD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD132SD_RD_SAE(ops...)) +} + +// VFNMADD132SD_RD_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD132SD.RD_SAE xmm xmm k xmm +// VFNMADD132SD.RD_SAE xmm xmm xmm +// Construct and append a VFNMADD132SD.RD_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD132SD_RD_SAE(ops ...operand.Op) { ctx.VFNMADD132SD_RD_SAE(ops...) } + +// VFNMADD132SD_RD_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD132SD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD132SD.RD_SAE.Z instruction to the active function. +func (c *Context) VFNMADD132SD_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMADD132SD_RD_SAE_Z(x, x1, k, x2)) +} + +// VFNMADD132SD_RD_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD132SD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD132SD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD132SD_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMADD132SD_RD_SAE_Z(x, x1, k, x2) } + +// VFNMADD132SD_RN_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD132SD.RN_SAE xmm xmm k xmm +// VFNMADD132SD.RN_SAE xmm xmm xmm +// Construct and append a VFNMADD132SD.RN_SAE instruction to the active function. +func (c *Context) VFNMADD132SD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD132SD_RN_SAE(ops...)) +} + +// VFNMADD132SD_RN_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD132SD.RN_SAE xmm xmm k xmm +// VFNMADD132SD.RN_SAE xmm xmm xmm +// Construct and append a VFNMADD132SD.RN_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD132SD_RN_SAE(ops ...operand.Op) { ctx.VFNMADD132SD_RN_SAE(ops...) } + +// VFNMADD132SD_RN_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD132SD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD132SD.RN_SAE.Z instruction to the active function. +func (c *Context) VFNMADD132SD_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMADD132SD_RN_SAE_Z(x, x1, k, x2)) +} + +// VFNMADD132SD_RN_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD132SD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD132SD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD132SD_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMADD132SD_RN_SAE_Z(x, x1, k, x2) } + +// VFNMADD132SD_RU_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD132SD.RU_SAE xmm xmm k xmm +// VFNMADD132SD.RU_SAE xmm xmm xmm +// Construct and append a VFNMADD132SD.RU_SAE instruction to the active function. +func (c *Context) VFNMADD132SD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD132SD_RU_SAE(ops...)) +} + +// VFNMADD132SD_RU_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD132SD.RU_SAE xmm xmm k xmm +// VFNMADD132SD.RU_SAE xmm xmm xmm +// Construct and append a VFNMADD132SD.RU_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD132SD_RU_SAE(ops ...operand.Op) { ctx.VFNMADD132SD_RU_SAE(ops...) } + +// VFNMADD132SD_RU_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD132SD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD132SD.RU_SAE.Z instruction to the active function. +func (c *Context) VFNMADD132SD_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMADD132SD_RU_SAE_Z(x, x1, k, x2)) +} + +// VFNMADD132SD_RU_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD132SD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD132SD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD132SD_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMADD132SD_RU_SAE_Z(x, x1, k, x2) } + +// VFNMADD132SD_RZ_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD132SD.RZ_SAE xmm xmm k xmm +// VFNMADD132SD.RZ_SAE xmm xmm xmm +// Construct and append a VFNMADD132SD.RZ_SAE instruction to the active function. +func (c *Context) VFNMADD132SD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD132SD_RZ_SAE(ops...)) +} + +// VFNMADD132SD_RZ_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD132SD.RZ_SAE xmm xmm k xmm +// VFNMADD132SD.RZ_SAE xmm xmm xmm +// Construct and append a VFNMADD132SD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD132SD_RZ_SAE(ops ...operand.Op) { ctx.VFNMADD132SD_RZ_SAE(ops...) } + +// VFNMADD132SD_RZ_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD132SD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD132SD.RZ_SAE.Z instruction to the active function. +func (c *Context) VFNMADD132SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMADD132SD_RZ_SAE_Z(x, x1, k, x2)) +} + +// VFNMADD132SD_RZ_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD132SD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD132SD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD132SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMADD132SD_RZ_SAE_Z(x, x1, k, x2) } + +// VFNMADD132SD_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD132SD.Z m64 xmm k xmm +// VFNMADD132SD.Z xmm xmm k xmm +// Construct and append a VFNMADD132SD.Z instruction to the active function. +func (c *Context) VFNMADD132SD_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VFNMADD132SD_Z(mx, x, k, x1)) +} + +// VFNMADD132SD_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD132SD.Z m64 xmm k xmm +// VFNMADD132SD.Z xmm xmm k xmm +// Construct and append a VFNMADD132SD.Z instruction to the active function. +// Operates on the global context. +func VFNMADD132SD_Z(mx, x, k, x1 operand.Op) { ctx.VFNMADD132SD_Z(mx, x, k, x1) } + +// VFNMADD132SS: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD132SS m32 xmm xmm +// VFNMADD132SS xmm xmm xmm +// VFNMADD132SS m32 xmm k xmm +// VFNMADD132SS xmm xmm k xmm +// Construct and append a VFNMADD132SS instruction to the active function. +func (c *Context) VFNMADD132SS(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD132SS(ops...)) +} + +// VFNMADD132SS: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD132SS m32 xmm xmm +// VFNMADD132SS xmm xmm xmm +// VFNMADD132SS m32 xmm k xmm +// VFNMADD132SS xmm xmm k xmm +// Construct and append a VFNMADD132SS instruction to the active function. +// Operates on the global context. +func VFNMADD132SS(ops ...operand.Op) { ctx.VFNMADD132SS(ops...) } + +// VFNMADD132SS_RD_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD132SS.RD_SAE xmm xmm k xmm +// VFNMADD132SS.RD_SAE xmm xmm xmm +// Construct and append a VFNMADD132SS.RD_SAE instruction to the active function. +func (c *Context) VFNMADD132SS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD132SS_RD_SAE(ops...)) +} + +// VFNMADD132SS_RD_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD132SS.RD_SAE xmm xmm k xmm +// VFNMADD132SS.RD_SAE xmm xmm xmm +// Construct and append a VFNMADD132SS.RD_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD132SS_RD_SAE(ops ...operand.Op) { ctx.VFNMADD132SS_RD_SAE(ops...) } + +// VFNMADD132SS_RD_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD132SS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD132SS.RD_SAE.Z instruction to the active function. +func (c *Context) VFNMADD132SS_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMADD132SS_RD_SAE_Z(x, x1, k, x2)) +} + +// VFNMADD132SS_RD_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD132SS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD132SS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD132SS_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMADD132SS_RD_SAE_Z(x, x1, k, x2) } + +// VFNMADD132SS_RN_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD132SS.RN_SAE xmm xmm k xmm +// VFNMADD132SS.RN_SAE xmm xmm xmm +// Construct and append a VFNMADD132SS.RN_SAE instruction to the active function. +func (c *Context) VFNMADD132SS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD132SS_RN_SAE(ops...)) +} + +// VFNMADD132SS_RN_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD132SS.RN_SAE xmm xmm k xmm +// VFNMADD132SS.RN_SAE xmm xmm xmm +// Construct and append a VFNMADD132SS.RN_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD132SS_RN_SAE(ops ...operand.Op) { ctx.VFNMADD132SS_RN_SAE(ops...) } + +// VFNMADD132SS_RN_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD132SS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD132SS.RN_SAE.Z instruction to the active function. +func (c *Context) VFNMADD132SS_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMADD132SS_RN_SAE_Z(x, x1, k, x2)) +} + +// VFNMADD132SS_RN_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD132SS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD132SS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD132SS_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMADD132SS_RN_SAE_Z(x, x1, k, x2) } + +// VFNMADD132SS_RU_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD132SS.RU_SAE xmm xmm k xmm +// VFNMADD132SS.RU_SAE xmm xmm xmm +// Construct and append a VFNMADD132SS.RU_SAE instruction to the active function. +func (c *Context) VFNMADD132SS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD132SS_RU_SAE(ops...)) +} + +// VFNMADD132SS_RU_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD132SS.RU_SAE xmm xmm k xmm +// VFNMADD132SS.RU_SAE xmm xmm xmm +// Construct and append a VFNMADD132SS.RU_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD132SS_RU_SAE(ops ...operand.Op) { ctx.VFNMADD132SS_RU_SAE(ops...) } + +// VFNMADD132SS_RU_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD132SS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD132SS.RU_SAE.Z instruction to the active function. +func (c *Context) VFNMADD132SS_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMADD132SS_RU_SAE_Z(x, x1, k, x2)) +} + +// VFNMADD132SS_RU_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD132SS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD132SS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD132SS_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMADD132SS_RU_SAE_Z(x, x1, k, x2) } + +// VFNMADD132SS_RZ_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD132SS.RZ_SAE xmm xmm k xmm +// VFNMADD132SS.RZ_SAE xmm xmm xmm +// Construct and append a VFNMADD132SS.RZ_SAE instruction to the active function. +func (c *Context) VFNMADD132SS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD132SS_RZ_SAE(ops...)) +} + +// VFNMADD132SS_RZ_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD132SS.RZ_SAE xmm xmm k xmm +// VFNMADD132SS.RZ_SAE xmm xmm xmm +// Construct and append a VFNMADD132SS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD132SS_RZ_SAE(ops ...operand.Op) { ctx.VFNMADD132SS_RZ_SAE(ops...) } + +// VFNMADD132SS_RZ_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD132SS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD132SS.RZ_SAE.Z instruction to the active function. +func (c *Context) VFNMADD132SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMADD132SS_RZ_SAE_Z(x, x1, k, x2)) +} + +// VFNMADD132SS_RZ_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD132SS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD132SS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD132SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMADD132SS_RZ_SAE_Z(x, x1, k, x2) } + +// VFNMADD132SS_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD132SS.Z m32 xmm k xmm +// VFNMADD132SS.Z xmm xmm k xmm +// Construct and append a VFNMADD132SS.Z instruction to the active function. +func (c *Context) VFNMADD132SS_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VFNMADD132SS_Z(mx, x, k, x1)) +} + +// VFNMADD132SS_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD132SS.Z m32 xmm k xmm +// VFNMADD132SS.Z xmm xmm k xmm +// Construct and append a VFNMADD132SS.Z instruction to the active function. +// Operates on the global context. +func VFNMADD132SS_Z(mx, x, k, x1 operand.Op) { ctx.VFNMADD132SS_Z(mx, x, k, x1) } + +// VFNMADD213PD: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD213PD m128 xmm xmm +// VFNMADD213PD m256 ymm ymm +// VFNMADD213PD xmm xmm xmm +// VFNMADD213PD ymm ymm ymm +// VFNMADD213PD m128 xmm k xmm +// VFNMADD213PD m256 ymm k ymm +// VFNMADD213PD xmm xmm k xmm +// VFNMADD213PD ymm ymm k ymm +// VFNMADD213PD m512 zmm k zmm +// VFNMADD213PD m512 zmm zmm +// VFNMADD213PD zmm zmm k zmm +// VFNMADD213PD zmm zmm zmm +// Construct and append a VFNMADD213PD instruction to the active function. +func (c *Context) VFNMADD213PD(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD213PD(ops...)) +} + +// VFNMADD213PD: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD213PD m128 xmm xmm +// VFNMADD213PD m256 ymm ymm +// VFNMADD213PD xmm xmm xmm +// VFNMADD213PD ymm ymm ymm +// VFNMADD213PD m128 xmm k xmm +// VFNMADD213PD m256 ymm k ymm +// VFNMADD213PD xmm xmm k xmm +// VFNMADD213PD ymm ymm k ymm +// VFNMADD213PD m512 zmm k zmm +// VFNMADD213PD m512 zmm zmm +// VFNMADD213PD zmm zmm k zmm +// VFNMADD213PD zmm zmm zmm +// Construct and append a VFNMADD213PD instruction to the active function. +// Operates on the global context. +func VFNMADD213PD(ops ...operand.Op) { ctx.VFNMADD213PD(ops...) } + +// VFNMADD213PD_BCST: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMADD213PD.BCST m64 xmm k xmm +// VFNMADD213PD.BCST m64 xmm xmm +// VFNMADD213PD.BCST m64 ymm k ymm +// VFNMADD213PD.BCST m64 ymm ymm +// VFNMADD213PD.BCST m64 zmm k zmm +// VFNMADD213PD.BCST m64 zmm zmm +// Construct and append a VFNMADD213PD.BCST instruction to the active function. +func (c *Context) VFNMADD213PD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD213PD_BCST(ops...)) +} + +// VFNMADD213PD_BCST: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMADD213PD.BCST m64 xmm k xmm +// VFNMADD213PD.BCST m64 xmm xmm +// VFNMADD213PD.BCST m64 ymm k ymm +// VFNMADD213PD.BCST m64 ymm ymm +// VFNMADD213PD.BCST m64 zmm k zmm +// VFNMADD213PD.BCST m64 zmm zmm +// Construct and append a VFNMADD213PD.BCST instruction to the active function. +// Operates on the global context. +func VFNMADD213PD_BCST(ops ...operand.Op) { ctx.VFNMADD213PD_BCST(ops...) } + +// VFNMADD213PD_BCST_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMADD213PD.BCST.Z m64 xmm k xmm +// VFNMADD213PD.BCST.Z m64 ymm k ymm +// VFNMADD213PD.BCST.Z m64 zmm k zmm +// Construct and append a VFNMADD213PD.BCST.Z instruction to the active function. +func (c *Context) VFNMADD213PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFNMADD213PD_BCST_Z(m, xyz, k, xyz1)) +} + +// VFNMADD213PD_BCST_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMADD213PD.BCST.Z m64 xmm k xmm +// VFNMADD213PD.BCST.Z m64 ymm k ymm +// VFNMADD213PD.BCST.Z m64 zmm k zmm +// Construct and append a VFNMADD213PD.BCST.Z instruction to the active function. +// Operates on the global context. +func VFNMADD213PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFNMADD213PD_BCST_Z(m, xyz, k, xyz1) } + +// VFNMADD213PD_RD_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD213PD.RD_SAE zmm zmm k zmm +// VFNMADD213PD.RD_SAE zmm zmm zmm +// Construct and append a VFNMADD213PD.RD_SAE instruction to the active function. +func (c *Context) VFNMADD213PD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD213PD_RD_SAE(ops...)) +} + +// VFNMADD213PD_RD_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD213PD.RD_SAE zmm zmm k zmm +// VFNMADD213PD.RD_SAE zmm zmm zmm +// Construct and append a VFNMADD213PD.RD_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD213PD_RD_SAE(ops ...operand.Op) { ctx.VFNMADD213PD_RD_SAE(ops...) } + +// VFNMADD213PD_RD_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD213PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD213PD.RD_SAE.Z instruction to the active function. +func (c *Context) VFNMADD213PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMADD213PD_RD_SAE_Z(z, z1, k, z2)) +} + +// VFNMADD213PD_RD_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD213PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD213PD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD213PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMADD213PD_RD_SAE_Z(z, z1, k, z2) } + +// VFNMADD213PD_RN_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD213PD.RN_SAE zmm zmm k zmm +// VFNMADD213PD.RN_SAE zmm zmm zmm +// Construct and append a VFNMADD213PD.RN_SAE instruction to the active function. +func (c *Context) VFNMADD213PD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD213PD_RN_SAE(ops...)) +} + +// VFNMADD213PD_RN_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD213PD.RN_SAE zmm zmm k zmm +// VFNMADD213PD.RN_SAE zmm zmm zmm +// Construct and append a VFNMADD213PD.RN_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD213PD_RN_SAE(ops ...operand.Op) { ctx.VFNMADD213PD_RN_SAE(ops...) } + +// VFNMADD213PD_RN_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD213PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD213PD.RN_SAE.Z instruction to the active function. +func (c *Context) VFNMADD213PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMADD213PD_RN_SAE_Z(z, z1, k, z2)) +} + +// VFNMADD213PD_RN_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD213PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD213PD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD213PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMADD213PD_RN_SAE_Z(z, z1, k, z2) } + +// VFNMADD213PD_RU_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD213PD.RU_SAE zmm zmm k zmm +// VFNMADD213PD.RU_SAE zmm zmm zmm +// Construct and append a VFNMADD213PD.RU_SAE instruction to the active function. +func (c *Context) VFNMADD213PD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD213PD_RU_SAE(ops...)) +} + +// VFNMADD213PD_RU_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD213PD.RU_SAE zmm zmm k zmm +// VFNMADD213PD.RU_SAE zmm zmm zmm +// Construct and append a VFNMADD213PD.RU_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD213PD_RU_SAE(ops ...operand.Op) { ctx.VFNMADD213PD_RU_SAE(ops...) } + +// VFNMADD213PD_RU_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD213PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD213PD.RU_SAE.Z instruction to the active function. +func (c *Context) VFNMADD213PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMADD213PD_RU_SAE_Z(z, z1, k, z2)) +} + +// VFNMADD213PD_RU_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD213PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD213PD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD213PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMADD213PD_RU_SAE_Z(z, z1, k, z2) } + +// VFNMADD213PD_RZ_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD213PD.RZ_SAE zmm zmm k zmm +// VFNMADD213PD.RZ_SAE zmm zmm zmm +// Construct and append a VFNMADD213PD.RZ_SAE instruction to the active function. +func (c *Context) VFNMADD213PD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD213PD_RZ_SAE(ops...)) +} + +// VFNMADD213PD_RZ_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD213PD.RZ_SAE zmm zmm k zmm +// VFNMADD213PD.RZ_SAE zmm zmm zmm +// Construct and append a VFNMADD213PD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD213PD_RZ_SAE(ops ...operand.Op) { ctx.VFNMADD213PD_RZ_SAE(ops...) } + +// VFNMADD213PD_RZ_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD213PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD213PD.RZ_SAE.Z instruction to the active function. +func (c *Context) VFNMADD213PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMADD213PD_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFNMADD213PD_RZ_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD213PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD213PD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD213PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMADD213PD_RZ_SAE_Z(z, z1, k, z2) } + +// VFNMADD213PD_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD213PD.Z m128 xmm k xmm +// VFNMADD213PD.Z m256 ymm k ymm +// VFNMADD213PD.Z xmm xmm k xmm +// VFNMADD213PD.Z ymm ymm k ymm +// VFNMADD213PD.Z m512 zmm k zmm +// VFNMADD213PD.Z zmm zmm k zmm +// Construct and append a VFNMADD213PD.Z instruction to the active function. +func (c *Context) VFNMADD213PD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFNMADD213PD_Z(mxyz, xyz, k, xyz1)) +} + +// VFNMADD213PD_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD213PD.Z m128 xmm k xmm +// VFNMADD213PD.Z m256 ymm k ymm +// VFNMADD213PD.Z xmm xmm k xmm +// VFNMADD213PD.Z ymm ymm k ymm +// VFNMADD213PD.Z m512 zmm k zmm +// VFNMADD213PD.Z zmm zmm k zmm +// Construct and append a VFNMADD213PD.Z instruction to the active function. +// Operates on the global context. +func VFNMADD213PD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFNMADD213PD_Z(mxyz, xyz, k, xyz1) } + +// VFNMADD213PS: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD213PS m128 xmm xmm +// VFNMADD213PS m256 ymm ymm +// VFNMADD213PS xmm xmm xmm +// VFNMADD213PS ymm ymm ymm +// VFNMADD213PS m128 xmm k xmm +// VFNMADD213PS m256 ymm k ymm +// VFNMADD213PS xmm xmm k xmm +// VFNMADD213PS ymm ymm k ymm +// VFNMADD213PS m512 zmm k zmm +// VFNMADD213PS m512 zmm zmm +// VFNMADD213PS zmm zmm k zmm +// VFNMADD213PS zmm zmm zmm +// Construct and append a VFNMADD213PS instruction to the active function. +func (c *Context) VFNMADD213PS(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD213PS(ops...)) +} + +// VFNMADD213PS: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD213PS m128 xmm xmm +// VFNMADD213PS m256 ymm ymm +// VFNMADD213PS xmm xmm xmm +// VFNMADD213PS ymm ymm ymm +// VFNMADD213PS m128 xmm k xmm +// VFNMADD213PS m256 ymm k ymm +// VFNMADD213PS xmm xmm k xmm +// VFNMADD213PS ymm ymm k ymm +// VFNMADD213PS m512 zmm k zmm +// VFNMADD213PS m512 zmm zmm +// VFNMADD213PS zmm zmm k zmm +// VFNMADD213PS zmm zmm zmm +// Construct and append a VFNMADD213PS instruction to the active function. +// Operates on the global context. +func VFNMADD213PS(ops ...operand.Op) { ctx.VFNMADD213PS(ops...) } + +// VFNMADD213PS_BCST: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMADD213PS.BCST m32 xmm k xmm +// VFNMADD213PS.BCST m32 xmm xmm +// VFNMADD213PS.BCST m32 ymm k ymm +// VFNMADD213PS.BCST m32 ymm ymm +// VFNMADD213PS.BCST m32 zmm k zmm +// VFNMADD213PS.BCST m32 zmm zmm +// Construct and append a VFNMADD213PS.BCST instruction to the active function. +func (c *Context) VFNMADD213PS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD213PS_BCST(ops...)) +} + +// VFNMADD213PS_BCST: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMADD213PS.BCST m32 xmm k xmm +// VFNMADD213PS.BCST m32 xmm xmm +// VFNMADD213PS.BCST m32 ymm k ymm +// VFNMADD213PS.BCST m32 ymm ymm +// VFNMADD213PS.BCST m32 zmm k zmm +// VFNMADD213PS.BCST m32 zmm zmm +// Construct and append a VFNMADD213PS.BCST instruction to the active function. +// Operates on the global context. +func VFNMADD213PS_BCST(ops ...operand.Op) { ctx.VFNMADD213PS_BCST(ops...) } + +// VFNMADD213PS_BCST_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMADD213PS.BCST.Z m32 xmm k xmm +// VFNMADD213PS.BCST.Z m32 ymm k ymm +// VFNMADD213PS.BCST.Z m32 zmm k zmm +// Construct and append a VFNMADD213PS.BCST.Z instruction to the active function. +func (c *Context) VFNMADD213PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFNMADD213PS_BCST_Z(m, xyz, k, xyz1)) +} + +// VFNMADD213PS_BCST_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMADD213PS.BCST.Z m32 xmm k xmm +// VFNMADD213PS.BCST.Z m32 ymm k ymm +// VFNMADD213PS.BCST.Z m32 zmm k zmm +// Construct and append a VFNMADD213PS.BCST.Z instruction to the active function. +// Operates on the global context. +func VFNMADD213PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFNMADD213PS_BCST_Z(m, xyz, k, xyz1) } + +// VFNMADD213PS_RD_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD213PS.RD_SAE zmm zmm k zmm +// VFNMADD213PS.RD_SAE zmm zmm zmm +// Construct and append a VFNMADD213PS.RD_SAE instruction to the active function. +func (c *Context) VFNMADD213PS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD213PS_RD_SAE(ops...)) +} + +// VFNMADD213PS_RD_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD213PS.RD_SAE zmm zmm k zmm +// VFNMADD213PS.RD_SAE zmm zmm zmm +// Construct and append a VFNMADD213PS.RD_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD213PS_RD_SAE(ops ...operand.Op) { ctx.VFNMADD213PS_RD_SAE(ops...) } + +// VFNMADD213PS_RD_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD213PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD213PS.RD_SAE.Z instruction to the active function. +func (c *Context) VFNMADD213PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMADD213PS_RD_SAE_Z(z, z1, k, z2)) +} + +// VFNMADD213PS_RD_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD213PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD213PS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD213PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMADD213PS_RD_SAE_Z(z, z1, k, z2) } + +// VFNMADD213PS_RN_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD213PS.RN_SAE zmm zmm k zmm +// VFNMADD213PS.RN_SAE zmm zmm zmm +// Construct and append a VFNMADD213PS.RN_SAE instruction to the active function. +func (c *Context) VFNMADD213PS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD213PS_RN_SAE(ops...)) +} + +// VFNMADD213PS_RN_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD213PS.RN_SAE zmm zmm k zmm +// VFNMADD213PS.RN_SAE zmm zmm zmm +// Construct and append a VFNMADD213PS.RN_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD213PS_RN_SAE(ops ...operand.Op) { ctx.VFNMADD213PS_RN_SAE(ops...) } + +// VFNMADD213PS_RN_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD213PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD213PS.RN_SAE.Z instruction to the active function. +func (c *Context) VFNMADD213PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMADD213PS_RN_SAE_Z(z, z1, k, z2)) +} + +// VFNMADD213PS_RN_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD213PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD213PS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD213PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMADD213PS_RN_SAE_Z(z, z1, k, z2) } + +// VFNMADD213PS_RU_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD213PS.RU_SAE zmm zmm k zmm +// VFNMADD213PS.RU_SAE zmm zmm zmm +// Construct and append a VFNMADD213PS.RU_SAE instruction to the active function. +func (c *Context) VFNMADD213PS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD213PS_RU_SAE(ops...)) +} + +// VFNMADD213PS_RU_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD213PS.RU_SAE zmm zmm k zmm +// VFNMADD213PS.RU_SAE zmm zmm zmm +// Construct and append a VFNMADD213PS.RU_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD213PS_RU_SAE(ops ...operand.Op) { ctx.VFNMADD213PS_RU_SAE(ops...) } + +// VFNMADD213PS_RU_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD213PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD213PS.RU_SAE.Z instruction to the active function. +func (c *Context) VFNMADD213PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMADD213PS_RU_SAE_Z(z, z1, k, z2)) +} + +// VFNMADD213PS_RU_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD213PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD213PS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD213PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMADD213PS_RU_SAE_Z(z, z1, k, z2) } + +// VFNMADD213PS_RZ_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD213PS.RZ_SAE zmm zmm k zmm +// VFNMADD213PS.RZ_SAE zmm zmm zmm +// Construct and append a VFNMADD213PS.RZ_SAE instruction to the active function. +func (c *Context) VFNMADD213PS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD213PS_RZ_SAE(ops...)) +} + +// VFNMADD213PS_RZ_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD213PS.RZ_SAE zmm zmm k zmm +// VFNMADD213PS.RZ_SAE zmm zmm zmm +// Construct and append a VFNMADD213PS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD213PS_RZ_SAE(ops ...operand.Op) { ctx.VFNMADD213PS_RZ_SAE(ops...) } + +// VFNMADD213PS_RZ_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD213PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD213PS.RZ_SAE.Z instruction to the active function. +func (c *Context) VFNMADD213PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMADD213PS_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFNMADD213PS_RZ_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD213PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD213PS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD213PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMADD213PS_RZ_SAE_Z(z, z1, k, z2) } + +// VFNMADD213PS_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD213PS.Z m128 xmm k xmm +// VFNMADD213PS.Z m256 ymm k ymm +// VFNMADD213PS.Z xmm xmm k xmm +// VFNMADD213PS.Z ymm ymm k ymm +// VFNMADD213PS.Z m512 zmm k zmm +// VFNMADD213PS.Z zmm zmm k zmm +// Construct and append a VFNMADD213PS.Z instruction to the active function. +func (c *Context) VFNMADD213PS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFNMADD213PS_Z(mxyz, xyz, k, xyz1)) +} + +// VFNMADD213PS_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD213PS.Z m128 xmm k xmm +// VFNMADD213PS.Z m256 ymm k ymm +// VFNMADD213PS.Z xmm xmm k xmm +// VFNMADD213PS.Z ymm ymm k ymm +// VFNMADD213PS.Z m512 zmm k zmm +// VFNMADD213PS.Z zmm zmm k zmm +// Construct and append a VFNMADD213PS.Z instruction to the active function. +// Operates on the global context. +func VFNMADD213PS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFNMADD213PS_Z(mxyz, xyz, k, xyz1) } + +// VFNMADD213SD: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD213SD m64 xmm xmm +// VFNMADD213SD xmm xmm xmm +// VFNMADD213SD m64 xmm k xmm +// VFNMADD213SD xmm xmm k xmm +// Construct and append a VFNMADD213SD instruction to the active function. +func (c *Context) VFNMADD213SD(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD213SD(ops...)) +} + +// VFNMADD213SD: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD213SD m64 xmm xmm +// VFNMADD213SD xmm xmm xmm +// VFNMADD213SD m64 xmm k xmm +// VFNMADD213SD xmm xmm k xmm +// Construct and append a VFNMADD213SD instruction to the active function. +// Operates on the global context. +func VFNMADD213SD(ops ...operand.Op) { ctx.VFNMADD213SD(ops...) } + +// VFNMADD213SD_RD_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD213SD.RD_SAE xmm xmm k xmm +// VFNMADD213SD.RD_SAE xmm xmm xmm +// Construct and append a VFNMADD213SD.RD_SAE instruction to the active function. +func (c *Context) VFNMADD213SD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD213SD_RD_SAE(ops...)) +} + +// VFNMADD213SD_RD_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD213SD.RD_SAE xmm xmm k xmm +// VFNMADD213SD.RD_SAE xmm xmm xmm +// Construct and append a VFNMADD213SD.RD_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD213SD_RD_SAE(ops ...operand.Op) { ctx.VFNMADD213SD_RD_SAE(ops...) } + +// VFNMADD213SD_RD_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD213SD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD213SD.RD_SAE.Z instruction to the active function. +func (c *Context) VFNMADD213SD_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMADD213SD_RD_SAE_Z(x, x1, k, x2)) +} + +// VFNMADD213SD_RD_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD213SD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD213SD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD213SD_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMADD213SD_RD_SAE_Z(x, x1, k, x2) } + +// VFNMADD213SD_RN_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD213SD.RN_SAE xmm xmm k xmm +// VFNMADD213SD.RN_SAE xmm xmm xmm +// Construct and append a VFNMADD213SD.RN_SAE instruction to the active function. +func (c *Context) VFNMADD213SD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD213SD_RN_SAE(ops...)) +} + +// VFNMADD213SD_RN_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD213SD.RN_SAE xmm xmm k xmm +// VFNMADD213SD.RN_SAE xmm xmm xmm +// Construct and append a VFNMADD213SD.RN_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD213SD_RN_SAE(ops ...operand.Op) { ctx.VFNMADD213SD_RN_SAE(ops...) } + +// VFNMADD213SD_RN_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD213SD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD213SD.RN_SAE.Z instruction to the active function. +func (c *Context) VFNMADD213SD_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMADD213SD_RN_SAE_Z(x, x1, k, x2)) +} + +// VFNMADD213SD_RN_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD213SD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD213SD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD213SD_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMADD213SD_RN_SAE_Z(x, x1, k, x2) } + +// VFNMADD213SD_RU_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD213SD.RU_SAE xmm xmm k xmm +// VFNMADD213SD.RU_SAE xmm xmm xmm +// Construct and append a VFNMADD213SD.RU_SAE instruction to the active function. +func (c *Context) VFNMADD213SD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD213SD_RU_SAE(ops...)) +} + +// VFNMADD213SD_RU_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD213SD.RU_SAE xmm xmm k xmm +// VFNMADD213SD.RU_SAE xmm xmm xmm +// Construct and append a VFNMADD213SD.RU_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD213SD_RU_SAE(ops ...operand.Op) { ctx.VFNMADD213SD_RU_SAE(ops...) } + +// VFNMADD213SD_RU_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD213SD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD213SD.RU_SAE.Z instruction to the active function. +func (c *Context) VFNMADD213SD_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMADD213SD_RU_SAE_Z(x, x1, k, x2)) +} + +// VFNMADD213SD_RU_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD213SD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD213SD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD213SD_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMADD213SD_RU_SAE_Z(x, x1, k, x2) } + +// VFNMADD213SD_RZ_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD213SD.RZ_SAE xmm xmm k xmm +// VFNMADD213SD.RZ_SAE xmm xmm xmm +// Construct and append a VFNMADD213SD.RZ_SAE instruction to the active function. +func (c *Context) VFNMADD213SD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD213SD_RZ_SAE(ops...)) +} + +// VFNMADD213SD_RZ_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD213SD.RZ_SAE xmm xmm k xmm +// VFNMADD213SD.RZ_SAE xmm xmm xmm +// Construct and append a VFNMADD213SD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD213SD_RZ_SAE(ops ...operand.Op) { ctx.VFNMADD213SD_RZ_SAE(ops...) } + +// VFNMADD213SD_RZ_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD213SD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD213SD.RZ_SAE.Z instruction to the active function. +func (c *Context) VFNMADD213SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMADD213SD_RZ_SAE_Z(x, x1, k, x2)) +} + +// VFNMADD213SD_RZ_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD213SD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD213SD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD213SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMADD213SD_RZ_SAE_Z(x, x1, k, x2) } + +// VFNMADD213SD_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD213SD.Z m64 xmm k xmm +// VFNMADD213SD.Z xmm xmm k xmm +// Construct and append a VFNMADD213SD.Z instruction to the active function. +func (c *Context) VFNMADD213SD_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VFNMADD213SD_Z(mx, x, k, x1)) +} + +// VFNMADD213SD_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD213SD.Z m64 xmm k xmm +// VFNMADD213SD.Z xmm xmm k xmm +// Construct and append a VFNMADD213SD.Z instruction to the active function. +// Operates on the global context. +func VFNMADD213SD_Z(mx, x, k, x1 operand.Op) { ctx.VFNMADD213SD_Z(mx, x, k, x1) } + +// VFNMADD213SS: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD213SS m32 xmm xmm +// VFNMADD213SS xmm xmm xmm +// VFNMADD213SS m32 xmm k xmm +// VFNMADD213SS xmm xmm k xmm +// Construct and append a VFNMADD213SS instruction to the active function. +func (c *Context) VFNMADD213SS(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD213SS(ops...)) +} + +// VFNMADD213SS: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD213SS m32 xmm xmm +// VFNMADD213SS xmm xmm xmm +// VFNMADD213SS m32 xmm k xmm +// VFNMADD213SS xmm xmm k xmm +// Construct and append a VFNMADD213SS instruction to the active function. +// Operates on the global context. +func VFNMADD213SS(ops ...operand.Op) { ctx.VFNMADD213SS(ops...) } + +// VFNMADD213SS_RD_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD213SS.RD_SAE xmm xmm k xmm +// VFNMADD213SS.RD_SAE xmm xmm xmm +// Construct and append a VFNMADD213SS.RD_SAE instruction to the active function. +func (c *Context) VFNMADD213SS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD213SS_RD_SAE(ops...)) +} + +// VFNMADD213SS_RD_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD213SS.RD_SAE xmm xmm k xmm +// VFNMADD213SS.RD_SAE xmm xmm xmm +// Construct and append a VFNMADD213SS.RD_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD213SS_RD_SAE(ops ...operand.Op) { ctx.VFNMADD213SS_RD_SAE(ops...) } + +// VFNMADD213SS_RD_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD213SS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD213SS.RD_SAE.Z instruction to the active function. +func (c *Context) VFNMADD213SS_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMADD213SS_RD_SAE_Z(x, x1, k, x2)) +} + +// VFNMADD213SS_RD_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD213SS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD213SS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD213SS_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMADD213SS_RD_SAE_Z(x, x1, k, x2) } + +// VFNMADD213SS_RN_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD213SS.RN_SAE xmm xmm k xmm +// VFNMADD213SS.RN_SAE xmm xmm xmm +// Construct and append a VFNMADD213SS.RN_SAE instruction to the active function. +func (c *Context) VFNMADD213SS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD213SS_RN_SAE(ops...)) +} + +// VFNMADD213SS_RN_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD213SS.RN_SAE xmm xmm k xmm +// VFNMADD213SS.RN_SAE xmm xmm xmm +// Construct and append a VFNMADD213SS.RN_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD213SS_RN_SAE(ops ...operand.Op) { ctx.VFNMADD213SS_RN_SAE(ops...) } + +// VFNMADD213SS_RN_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD213SS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD213SS.RN_SAE.Z instruction to the active function. +func (c *Context) VFNMADD213SS_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMADD213SS_RN_SAE_Z(x, x1, k, x2)) +} + +// VFNMADD213SS_RN_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD213SS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD213SS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD213SS_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMADD213SS_RN_SAE_Z(x, x1, k, x2) } + +// VFNMADD213SS_RU_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD213SS.RU_SAE xmm xmm k xmm +// VFNMADD213SS.RU_SAE xmm xmm xmm +// Construct and append a VFNMADD213SS.RU_SAE instruction to the active function. +func (c *Context) VFNMADD213SS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD213SS_RU_SAE(ops...)) +} + +// VFNMADD213SS_RU_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD213SS.RU_SAE xmm xmm k xmm +// VFNMADD213SS.RU_SAE xmm xmm xmm +// Construct and append a VFNMADD213SS.RU_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD213SS_RU_SAE(ops ...operand.Op) { ctx.VFNMADD213SS_RU_SAE(ops...) } + +// VFNMADD213SS_RU_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD213SS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD213SS.RU_SAE.Z instruction to the active function. +func (c *Context) VFNMADD213SS_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMADD213SS_RU_SAE_Z(x, x1, k, x2)) +} + +// VFNMADD213SS_RU_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD213SS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD213SS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD213SS_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMADD213SS_RU_SAE_Z(x, x1, k, x2) } + +// VFNMADD213SS_RZ_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD213SS.RZ_SAE xmm xmm k xmm +// VFNMADD213SS.RZ_SAE xmm xmm xmm +// Construct and append a VFNMADD213SS.RZ_SAE instruction to the active function. +func (c *Context) VFNMADD213SS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD213SS_RZ_SAE(ops...)) +} + +// VFNMADD213SS_RZ_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD213SS.RZ_SAE xmm xmm k xmm +// VFNMADD213SS.RZ_SAE xmm xmm xmm +// Construct and append a VFNMADD213SS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD213SS_RZ_SAE(ops ...operand.Op) { ctx.VFNMADD213SS_RZ_SAE(ops...) } + +// VFNMADD213SS_RZ_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD213SS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD213SS.RZ_SAE.Z instruction to the active function. +func (c *Context) VFNMADD213SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMADD213SS_RZ_SAE_Z(x, x1, k, x2)) +} + +// VFNMADD213SS_RZ_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD213SS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD213SS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD213SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMADD213SS_RZ_SAE_Z(x, x1, k, x2) } + +// VFNMADD213SS_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD213SS.Z m32 xmm k xmm +// VFNMADD213SS.Z xmm xmm k xmm +// Construct and append a VFNMADD213SS.Z instruction to the active function. +func (c *Context) VFNMADD213SS_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VFNMADD213SS_Z(mx, x, k, x1)) +} + +// VFNMADD213SS_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD213SS.Z m32 xmm k xmm +// VFNMADD213SS.Z xmm xmm k xmm +// Construct and append a VFNMADD213SS.Z instruction to the active function. +// Operates on the global context. +func VFNMADD213SS_Z(mx, x, k, x1 operand.Op) { ctx.VFNMADD213SS_Z(mx, x, k, x1) } + +// VFNMADD231PD: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD231PD m128 xmm xmm +// VFNMADD231PD m256 ymm ymm +// VFNMADD231PD xmm xmm xmm +// VFNMADD231PD ymm ymm ymm +// VFNMADD231PD m128 xmm k xmm +// VFNMADD231PD m256 ymm k ymm +// VFNMADD231PD xmm xmm k xmm +// VFNMADD231PD ymm ymm k ymm +// VFNMADD231PD m512 zmm k zmm +// VFNMADD231PD m512 zmm zmm +// VFNMADD231PD zmm zmm k zmm +// VFNMADD231PD zmm zmm zmm +// Construct and append a VFNMADD231PD instruction to the active function. +func (c *Context) VFNMADD231PD(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD231PD(ops...)) +} + +// VFNMADD231PD: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD231PD m128 xmm xmm +// VFNMADD231PD m256 ymm ymm +// VFNMADD231PD xmm xmm xmm +// VFNMADD231PD ymm ymm ymm +// VFNMADD231PD m128 xmm k xmm +// VFNMADD231PD m256 ymm k ymm +// VFNMADD231PD xmm xmm k xmm +// VFNMADD231PD ymm ymm k ymm +// VFNMADD231PD m512 zmm k zmm +// VFNMADD231PD m512 zmm zmm +// VFNMADD231PD zmm zmm k zmm +// VFNMADD231PD zmm zmm zmm +// Construct and append a VFNMADD231PD instruction to the active function. +// Operates on the global context. +func VFNMADD231PD(ops ...operand.Op) { ctx.VFNMADD231PD(ops...) } + +// VFNMADD231PD_BCST: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMADD231PD.BCST m64 xmm k xmm +// VFNMADD231PD.BCST m64 xmm xmm +// VFNMADD231PD.BCST m64 ymm k ymm +// VFNMADD231PD.BCST m64 ymm ymm +// VFNMADD231PD.BCST m64 zmm k zmm +// VFNMADD231PD.BCST m64 zmm zmm +// Construct and append a VFNMADD231PD.BCST instruction to the active function. +func (c *Context) VFNMADD231PD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD231PD_BCST(ops...)) +} + +// VFNMADD231PD_BCST: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMADD231PD.BCST m64 xmm k xmm +// VFNMADD231PD.BCST m64 xmm xmm +// VFNMADD231PD.BCST m64 ymm k ymm +// VFNMADD231PD.BCST m64 ymm ymm +// VFNMADD231PD.BCST m64 zmm k zmm +// VFNMADD231PD.BCST m64 zmm zmm +// Construct and append a VFNMADD231PD.BCST instruction to the active function. +// Operates on the global context. +func VFNMADD231PD_BCST(ops ...operand.Op) { ctx.VFNMADD231PD_BCST(ops...) } + +// VFNMADD231PD_BCST_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMADD231PD.BCST.Z m64 xmm k xmm +// VFNMADD231PD.BCST.Z m64 ymm k ymm +// VFNMADD231PD.BCST.Z m64 zmm k zmm +// Construct and append a VFNMADD231PD.BCST.Z instruction to the active function. +func (c *Context) VFNMADD231PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFNMADD231PD_BCST_Z(m, xyz, k, xyz1)) +} + +// VFNMADD231PD_BCST_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMADD231PD.BCST.Z m64 xmm k xmm +// VFNMADD231PD.BCST.Z m64 ymm k ymm +// VFNMADD231PD.BCST.Z m64 zmm k zmm +// Construct and append a VFNMADD231PD.BCST.Z instruction to the active function. +// Operates on the global context. +func VFNMADD231PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFNMADD231PD_BCST_Z(m, xyz, k, xyz1) } + +// VFNMADD231PD_RD_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD231PD.RD_SAE zmm zmm k zmm +// VFNMADD231PD.RD_SAE zmm zmm zmm +// Construct and append a VFNMADD231PD.RD_SAE instruction to the active function. +func (c *Context) VFNMADD231PD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD231PD_RD_SAE(ops...)) +} + +// VFNMADD231PD_RD_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD231PD.RD_SAE zmm zmm k zmm +// VFNMADD231PD.RD_SAE zmm zmm zmm +// Construct and append a VFNMADD231PD.RD_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD231PD_RD_SAE(ops ...operand.Op) { ctx.VFNMADD231PD_RD_SAE(ops...) } + +// VFNMADD231PD_RD_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD231PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD231PD.RD_SAE.Z instruction to the active function. +func (c *Context) VFNMADD231PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMADD231PD_RD_SAE_Z(z, z1, k, z2)) +} + +// VFNMADD231PD_RD_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD231PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD231PD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD231PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMADD231PD_RD_SAE_Z(z, z1, k, z2) } + +// VFNMADD231PD_RN_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD231PD.RN_SAE zmm zmm k zmm +// VFNMADD231PD.RN_SAE zmm zmm zmm +// Construct and append a VFNMADD231PD.RN_SAE instruction to the active function. +func (c *Context) VFNMADD231PD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD231PD_RN_SAE(ops...)) +} + +// VFNMADD231PD_RN_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD231PD.RN_SAE zmm zmm k zmm +// VFNMADD231PD.RN_SAE zmm zmm zmm +// Construct and append a VFNMADD231PD.RN_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD231PD_RN_SAE(ops ...operand.Op) { ctx.VFNMADD231PD_RN_SAE(ops...) } + +// VFNMADD231PD_RN_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD231PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD231PD.RN_SAE.Z instruction to the active function. +func (c *Context) VFNMADD231PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMADD231PD_RN_SAE_Z(z, z1, k, z2)) +} + +// VFNMADD231PD_RN_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD231PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD231PD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD231PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMADD231PD_RN_SAE_Z(z, z1, k, z2) } + +// VFNMADD231PD_RU_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD231PD.RU_SAE zmm zmm k zmm +// VFNMADD231PD.RU_SAE zmm zmm zmm +// Construct and append a VFNMADD231PD.RU_SAE instruction to the active function. +func (c *Context) VFNMADD231PD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD231PD_RU_SAE(ops...)) +} + +// VFNMADD231PD_RU_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD231PD.RU_SAE zmm zmm k zmm +// VFNMADD231PD.RU_SAE zmm zmm zmm +// Construct and append a VFNMADD231PD.RU_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD231PD_RU_SAE(ops ...operand.Op) { ctx.VFNMADD231PD_RU_SAE(ops...) } + +// VFNMADD231PD_RU_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD231PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD231PD.RU_SAE.Z instruction to the active function. +func (c *Context) VFNMADD231PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMADD231PD_RU_SAE_Z(z, z1, k, z2)) +} + +// VFNMADD231PD_RU_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD231PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD231PD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD231PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMADD231PD_RU_SAE_Z(z, z1, k, z2) } + +// VFNMADD231PD_RZ_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD231PD.RZ_SAE zmm zmm k zmm +// VFNMADD231PD.RZ_SAE zmm zmm zmm +// Construct and append a VFNMADD231PD.RZ_SAE instruction to the active function. +func (c *Context) VFNMADD231PD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD231PD_RZ_SAE(ops...)) +} + +// VFNMADD231PD_RZ_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD231PD.RZ_SAE zmm zmm k zmm +// VFNMADD231PD.RZ_SAE zmm zmm zmm +// Construct and append a VFNMADD231PD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD231PD_RZ_SAE(ops ...operand.Op) { ctx.VFNMADD231PD_RZ_SAE(ops...) } + +// VFNMADD231PD_RZ_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD231PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD231PD.RZ_SAE.Z instruction to the active function. +func (c *Context) VFNMADD231PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMADD231PD_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFNMADD231PD_RZ_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD231PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD231PD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD231PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMADD231PD_RZ_SAE_Z(z, z1, k, z2) } + +// VFNMADD231PD_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD231PD.Z m128 xmm k xmm +// VFNMADD231PD.Z m256 ymm k ymm +// VFNMADD231PD.Z xmm xmm k xmm +// VFNMADD231PD.Z ymm ymm k ymm +// VFNMADD231PD.Z m512 zmm k zmm +// VFNMADD231PD.Z zmm zmm k zmm +// Construct and append a VFNMADD231PD.Z instruction to the active function. +func (c *Context) VFNMADD231PD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFNMADD231PD_Z(mxyz, xyz, k, xyz1)) +} + +// VFNMADD231PD_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD231PD.Z m128 xmm k xmm +// VFNMADD231PD.Z m256 ymm k ymm +// VFNMADD231PD.Z xmm xmm k xmm +// VFNMADD231PD.Z ymm ymm k ymm +// VFNMADD231PD.Z m512 zmm k zmm +// VFNMADD231PD.Z zmm zmm k zmm +// Construct and append a VFNMADD231PD.Z instruction to the active function. +// Operates on the global context. +func VFNMADD231PD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFNMADD231PD_Z(mxyz, xyz, k, xyz1) } + +// VFNMADD231PS: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD231PS m128 xmm xmm +// VFNMADD231PS m256 ymm ymm +// VFNMADD231PS xmm xmm xmm +// VFNMADD231PS ymm ymm ymm +// VFNMADD231PS m128 xmm k xmm +// VFNMADD231PS m256 ymm k ymm +// VFNMADD231PS xmm xmm k xmm +// VFNMADD231PS ymm ymm k ymm +// VFNMADD231PS m512 zmm k zmm +// VFNMADD231PS m512 zmm zmm +// VFNMADD231PS zmm zmm k zmm +// VFNMADD231PS zmm zmm zmm +// Construct and append a VFNMADD231PS instruction to the active function. +func (c *Context) VFNMADD231PS(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD231PS(ops...)) +} + +// VFNMADD231PS: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD231PS m128 xmm xmm +// VFNMADD231PS m256 ymm ymm +// VFNMADD231PS xmm xmm xmm +// VFNMADD231PS ymm ymm ymm +// VFNMADD231PS m128 xmm k xmm +// VFNMADD231PS m256 ymm k ymm +// VFNMADD231PS xmm xmm k xmm +// VFNMADD231PS ymm ymm k ymm +// VFNMADD231PS m512 zmm k zmm +// VFNMADD231PS m512 zmm zmm +// VFNMADD231PS zmm zmm k zmm +// VFNMADD231PS zmm zmm zmm +// Construct and append a VFNMADD231PS instruction to the active function. +// Operates on the global context. +func VFNMADD231PS(ops ...operand.Op) { ctx.VFNMADD231PS(ops...) } + +// VFNMADD231PS_BCST: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMADD231PS.BCST m32 xmm k xmm +// VFNMADD231PS.BCST m32 xmm xmm +// VFNMADD231PS.BCST m32 ymm k ymm +// VFNMADD231PS.BCST m32 ymm ymm +// VFNMADD231PS.BCST m32 zmm k zmm +// VFNMADD231PS.BCST m32 zmm zmm +// Construct and append a VFNMADD231PS.BCST instruction to the active function. +func (c *Context) VFNMADD231PS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD231PS_BCST(ops...)) +} + +// VFNMADD231PS_BCST: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMADD231PS.BCST m32 xmm k xmm +// VFNMADD231PS.BCST m32 xmm xmm +// VFNMADD231PS.BCST m32 ymm k ymm +// VFNMADD231PS.BCST m32 ymm ymm +// VFNMADD231PS.BCST m32 zmm k zmm +// VFNMADD231PS.BCST m32 zmm zmm +// Construct and append a VFNMADD231PS.BCST instruction to the active function. +// Operates on the global context. +func VFNMADD231PS_BCST(ops ...operand.Op) { ctx.VFNMADD231PS_BCST(ops...) } + +// VFNMADD231PS_BCST_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMADD231PS.BCST.Z m32 xmm k xmm +// VFNMADD231PS.BCST.Z m32 ymm k ymm +// VFNMADD231PS.BCST.Z m32 zmm k zmm +// Construct and append a VFNMADD231PS.BCST.Z instruction to the active function. +func (c *Context) VFNMADD231PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFNMADD231PS_BCST_Z(m, xyz, k, xyz1)) +} + +// VFNMADD231PS_BCST_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMADD231PS.BCST.Z m32 xmm k xmm +// VFNMADD231PS.BCST.Z m32 ymm k ymm +// VFNMADD231PS.BCST.Z m32 zmm k zmm +// Construct and append a VFNMADD231PS.BCST.Z instruction to the active function. +// Operates on the global context. +func VFNMADD231PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFNMADD231PS_BCST_Z(m, xyz, k, xyz1) } + +// VFNMADD231PS_RD_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD231PS.RD_SAE zmm zmm k zmm +// VFNMADD231PS.RD_SAE zmm zmm zmm +// Construct and append a VFNMADD231PS.RD_SAE instruction to the active function. +func (c *Context) VFNMADD231PS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD231PS_RD_SAE(ops...)) +} + +// VFNMADD231PS_RD_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD231PS.RD_SAE zmm zmm k zmm +// VFNMADD231PS.RD_SAE zmm zmm zmm +// Construct and append a VFNMADD231PS.RD_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD231PS_RD_SAE(ops ...operand.Op) { ctx.VFNMADD231PS_RD_SAE(ops...) } + +// VFNMADD231PS_RD_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD231PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD231PS.RD_SAE.Z instruction to the active function. +func (c *Context) VFNMADD231PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMADD231PS_RD_SAE_Z(z, z1, k, z2)) +} + +// VFNMADD231PS_RD_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD231PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD231PS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD231PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMADD231PS_RD_SAE_Z(z, z1, k, z2) } + +// VFNMADD231PS_RN_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD231PS.RN_SAE zmm zmm k zmm +// VFNMADD231PS.RN_SAE zmm zmm zmm +// Construct and append a VFNMADD231PS.RN_SAE instruction to the active function. +func (c *Context) VFNMADD231PS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD231PS_RN_SAE(ops...)) +} + +// VFNMADD231PS_RN_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD231PS.RN_SAE zmm zmm k zmm +// VFNMADD231PS.RN_SAE zmm zmm zmm +// Construct and append a VFNMADD231PS.RN_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD231PS_RN_SAE(ops ...operand.Op) { ctx.VFNMADD231PS_RN_SAE(ops...) } + +// VFNMADD231PS_RN_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD231PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD231PS.RN_SAE.Z instruction to the active function. +func (c *Context) VFNMADD231PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMADD231PS_RN_SAE_Z(z, z1, k, z2)) +} + +// VFNMADD231PS_RN_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD231PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD231PS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD231PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMADD231PS_RN_SAE_Z(z, z1, k, z2) } + +// VFNMADD231PS_RU_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD231PS.RU_SAE zmm zmm k zmm +// VFNMADD231PS.RU_SAE zmm zmm zmm +// Construct and append a VFNMADD231PS.RU_SAE instruction to the active function. +func (c *Context) VFNMADD231PS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD231PS_RU_SAE(ops...)) +} + +// VFNMADD231PS_RU_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD231PS.RU_SAE zmm zmm k zmm +// VFNMADD231PS.RU_SAE zmm zmm zmm +// Construct and append a VFNMADD231PS.RU_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD231PS_RU_SAE(ops ...operand.Op) { ctx.VFNMADD231PS_RU_SAE(ops...) } + +// VFNMADD231PS_RU_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD231PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD231PS.RU_SAE.Z instruction to the active function. +func (c *Context) VFNMADD231PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMADD231PS_RU_SAE_Z(z, z1, k, z2)) +} + +// VFNMADD231PS_RU_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD231PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD231PS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD231PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMADD231PS_RU_SAE_Z(z, z1, k, z2) } + +// VFNMADD231PS_RZ_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD231PS.RZ_SAE zmm zmm k zmm +// VFNMADD231PS.RZ_SAE zmm zmm zmm +// Construct and append a VFNMADD231PS.RZ_SAE instruction to the active function. +func (c *Context) VFNMADD231PS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD231PS_RZ_SAE(ops...)) +} + +// VFNMADD231PS_RZ_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD231PS.RZ_SAE zmm zmm k zmm +// VFNMADD231PS.RZ_SAE zmm zmm zmm +// Construct and append a VFNMADD231PS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD231PS_RZ_SAE(ops ...operand.Op) { ctx.VFNMADD231PS_RZ_SAE(ops...) } + +// VFNMADD231PS_RZ_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD231PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD231PS.RZ_SAE.Z instruction to the active function. +func (c *Context) VFNMADD231PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMADD231PS_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFNMADD231PS_RZ_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD231PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFNMADD231PS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD231PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMADD231PS_RZ_SAE_Z(z, z1, k, z2) } + +// VFNMADD231PS_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD231PS.Z m128 xmm k xmm +// VFNMADD231PS.Z m256 ymm k ymm +// VFNMADD231PS.Z xmm xmm k xmm +// VFNMADD231PS.Z ymm ymm k ymm +// VFNMADD231PS.Z m512 zmm k zmm +// VFNMADD231PS.Z zmm zmm k zmm +// Construct and append a VFNMADD231PS.Z instruction to the active function. +func (c *Context) VFNMADD231PS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFNMADD231PS_Z(mxyz, xyz, k, xyz1)) +} + +// VFNMADD231PS_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD231PS.Z m128 xmm k xmm +// VFNMADD231PS.Z m256 ymm k ymm +// VFNMADD231PS.Z xmm xmm k xmm +// VFNMADD231PS.Z ymm ymm k ymm +// VFNMADD231PS.Z m512 zmm k zmm +// VFNMADD231PS.Z zmm zmm k zmm +// Construct and append a VFNMADD231PS.Z instruction to the active function. +// Operates on the global context. +func VFNMADD231PS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFNMADD231PS_Z(mxyz, xyz, k, xyz1) } + +// VFNMADD231SD: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD231SD m64 xmm xmm +// VFNMADD231SD xmm xmm xmm +// VFNMADD231SD m64 xmm k xmm +// VFNMADD231SD xmm xmm k xmm +// Construct and append a VFNMADD231SD instruction to the active function. +func (c *Context) VFNMADD231SD(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD231SD(ops...)) +} + +// VFNMADD231SD: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD231SD m64 xmm xmm +// VFNMADD231SD xmm xmm xmm +// VFNMADD231SD m64 xmm k xmm +// VFNMADD231SD xmm xmm k xmm +// Construct and append a VFNMADD231SD instruction to the active function. +// Operates on the global context. +func VFNMADD231SD(ops ...operand.Op) { ctx.VFNMADD231SD(ops...) } + +// VFNMADD231SD_RD_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD231SD.RD_SAE xmm xmm k xmm +// VFNMADD231SD.RD_SAE xmm xmm xmm +// Construct and append a VFNMADD231SD.RD_SAE instruction to the active function. +func (c *Context) VFNMADD231SD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD231SD_RD_SAE(ops...)) +} + +// VFNMADD231SD_RD_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD231SD.RD_SAE xmm xmm k xmm +// VFNMADD231SD.RD_SAE xmm xmm xmm +// Construct and append a VFNMADD231SD.RD_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD231SD_RD_SAE(ops ...operand.Op) { ctx.VFNMADD231SD_RD_SAE(ops...) } + +// VFNMADD231SD_RD_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD231SD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD231SD.RD_SAE.Z instruction to the active function. +func (c *Context) VFNMADD231SD_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMADD231SD_RD_SAE_Z(x, x1, k, x2)) +} + +// VFNMADD231SD_RD_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD231SD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD231SD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD231SD_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMADD231SD_RD_SAE_Z(x, x1, k, x2) } + +// VFNMADD231SD_RN_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD231SD.RN_SAE xmm xmm k xmm +// VFNMADD231SD.RN_SAE xmm xmm xmm +// Construct and append a VFNMADD231SD.RN_SAE instruction to the active function. +func (c *Context) VFNMADD231SD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD231SD_RN_SAE(ops...)) +} + +// VFNMADD231SD_RN_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD231SD.RN_SAE xmm xmm k xmm +// VFNMADD231SD.RN_SAE xmm xmm xmm +// Construct and append a VFNMADD231SD.RN_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD231SD_RN_SAE(ops ...operand.Op) { ctx.VFNMADD231SD_RN_SAE(ops...) } + +// VFNMADD231SD_RN_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD231SD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD231SD.RN_SAE.Z instruction to the active function. +func (c *Context) VFNMADD231SD_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMADD231SD_RN_SAE_Z(x, x1, k, x2)) +} + +// VFNMADD231SD_RN_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD231SD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD231SD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD231SD_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMADD231SD_RN_SAE_Z(x, x1, k, x2) } + +// VFNMADD231SD_RU_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD231SD.RU_SAE xmm xmm k xmm +// VFNMADD231SD.RU_SAE xmm xmm xmm +// Construct and append a VFNMADD231SD.RU_SAE instruction to the active function. +func (c *Context) VFNMADD231SD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD231SD_RU_SAE(ops...)) +} + +// VFNMADD231SD_RU_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD231SD.RU_SAE xmm xmm k xmm +// VFNMADD231SD.RU_SAE xmm xmm xmm +// Construct and append a VFNMADD231SD.RU_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD231SD_RU_SAE(ops ...operand.Op) { ctx.VFNMADD231SD_RU_SAE(ops...) } + +// VFNMADD231SD_RU_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD231SD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD231SD.RU_SAE.Z instruction to the active function. +func (c *Context) VFNMADD231SD_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMADD231SD_RU_SAE_Z(x, x1, k, x2)) +} + +// VFNMADD231SD_RU_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD231SD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD231SD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD231SD_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMADD231SD_RU_SAE_Z(x, x1, k, x2) } + +// VFNMADD231SD_RZ_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD231SD.RZ_SAE xmm xmm k xmm +// VFNMADD231SD.RZ_SAE xmm xmm xmm +// Construct and append a VFNMADD231SD.RZ_SAE instruction to the active function. +func (c *Context) VFNMADD231SD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD231SD_RZ_SAE(ops...)) +} + +// VFNMADD231SD_RZ_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD231SD.RZ_SAE xmm xmm k xmm +// VFNMADD231SD.RZ_SAE xmm xmm xmm +// Construct and append a VFNMADD231SD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD231SD_RZ_SAE(ops ...operand.Op) { ctx.VFNMADD231SD_RZ_SAE(ops...) } + +// VFNMADD231SD_RZ_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD231SD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD231SD.RZ_SAE.Z instruction to the active function. +func (c *Context) VFNMADD231SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMADD231SD_RZ_SAE_Z(x, x1, k, x2)) +} + +// VFNMADD231SD_RZ_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD231SD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD231SD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD231SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMADD231SD_RZ_SAE_Z(x, x1, k, x2) } + +// VFNMADD231SD_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD231SD.Z m64 xmm k xmm +// VFNMADD231SD.Z xmm xmm k xmm +// Construct and append a VFNMADD231SD.Z instruction to the active function. +func (c *Context) VFNMADD231SD_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VFNMADD231SD_Z(mx, x, k, x1)) +} + +// VFNMADD231SD_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD231SD.Z m64 xmm k xmm +// VFNMADD231SD.Z xmm xmm k xmm +// Construct and append a VFNMADD231SD.Z instruction to the active function. +// Operates on the global context. +func VFNMADD231SD_Z(mx, x, k, x1 operand.Op) { ctx.VFNMADD231SD_Z(mx, x, k, x1) } + +// VFNMADD231SS: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD231SS m32 xmm xmm +// VFNMADD231SS xmm xmm xmm +// VFNMADD231SS m32 xmm k xmm +// VFNMADD231SS xmm xmm k xmm +// Construct and append a VFNMADD231SS instruction to the active function. +func (c *Context) VFNMADD231SS(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD231SS(ops...)) +} + +// VFNMADD231SS: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD231SS m32 xmm xmm +// VFNMADD231SS xmm xmm xmm +// VFNMADD231SS m32 xmm k xmm +// VFNMADD231SS xmm xmm k xmm +// Construct and append a VFNMADD231SS instruction to the active function. +// Operates on the global context. +func VFNMADD231SS(ops ...operand.Op) { ctx.VFNMADD231SS(ops...) } + +// VFNMADD231SS_RD_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD231SS.RD_SAE xmm xmm k xmm +// VFNMADD231SS.RD_SAE xmm xmm xmm +// Construct and append a VFNMADD231SS.RD_SAE instruction to the active function. +func (c *Context) VFNMADD231SS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD231SS_RD_SAE(ops...)) +} + +// VFNMADD231SS_RD_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD231SS.RD_SAE xmm xmm k xmm +// VFNMADD231SS.RD_SAE xmm xmm xmm +// Construct and append a VFNMADD231SS.RD_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD231SS_RD_SAE(ops ...operand.Op) { ctx.VFNMADD231SS_RD_SAE(ops...) } + +// VFNMADD231SS_RD_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD231SS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD231SS.RD_SAE.Z instruction to the active function. +func (c *Context) VFNMADD231SS_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMADD231SS_RD_SAE_Z(x, x1, k, x2)) +} + +// VFNMADD231SS_RD_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD231SS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD231SS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD231SS_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMADD231SS_RD_SAE_Z(x, x1, k, x2) } + +// VFNMADD231SS_RN_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD231SS.RN_SAE xmm xmm k xmm +// VFNMADD231SS.RN_SAE xmm xmm xmm +// Construct and append a VFNMADD231SS.RN_SAE instruction to the active function. +func (c *Context) VFNMADD231SS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD231SS_RN_SAE(ops...)) +} + +// VFNMADD231SS_RN_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD231SS.RN_SAE xmm xmm k xmm +// VFNMADD231SS.RN_SAE xmm xmm xmm +// Construct and append a VFNMADD231SS.RN_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD231SS_RN_SAE(ops ...operand.Op) { ctx.VFNMADD231SS_RN_SAE(ops...) } + +// VFNMADD231SS_RN_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD231SS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD231SS.RN_SAE.Z instruction to the active function. +func (c *Context) VFNMADD231SS_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMADD231SS_RN_SAE_Z(x, x1, k, x2)) +} + +// VFNMADD231SS_RN_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD231SS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD231SS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD231SS_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMADD231SS_RN_SAE_Z(x, x1, k, x2) } + +// VFNMADD231SS_RU_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD231SS.RU_SAE xmm xmm k xmm +// VFNMADD231SS.RU_SAE xmm xmm xmm +// Construct and append a VFNMADD231SS.RU_SAE instruction to the active function. +func (c *Context) VFNMADD231SS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD231SS_RU_SAE(ops...)) +} + +// VFNMADD231SS_RU_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD231SS.RU_SAE xmm xmm k xmm +// VFNMADD231SS.RU_SAE xmm xmm xmm +// Construct and append a VFNMADD231SS.RU_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD231SS_RU_SAE(ops ...operand.Op) { ctx.VFNMADD231SS_RU_SAE(ops...) } + +// VFNMADD231SS_RU_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD231SS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD231SS.RU_SAE.Z instruction to the active function. +func (c *Context) VFNMADD231SS_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMADD231SS_RU_SAE_Z(x, x1, k, x2)) +} + +// VFNMADD231SS_RU_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD231SS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD231SS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD231SS_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMADD231SS_RU_SAE_Z(x, x1, k, x2) } + +// VFNMADD231SS_RZ_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD231SS.RZ_SAE xmm xmm k xmm +// VFNMADD231SS.RZ_SAE xmm xmm xmm +// Construct and append a VFNMADD231SS.RZ_SAE instruction to the active function. +func (c *Context) VFNMADD231SS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMADD231SS_RZ_SAE(ops...)) +} + +// VFNMADD231SS_RZ_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD231SS.RZ_SAE xmm xmm k xmm +// VFNMADD231SS.RZ_SAE xmm xmm xmm +// Construct and append a VFNMADD231SS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFNMADD231SS_RZ_SAE(ops ...operand.Op) { ctx.VFNMADD231SS_RZ_SAE(ops...) } + +// VFNMADD231SS_RZ_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD231SS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD231SS.RZ_SAE.Z instruction to the active function. +func (c *Context) VFNMADD231SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMADD231SS_RZ_SAE_Z(x, x1, k, x2)) +} + +// VFNMADD231SS_RZ_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD231SS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFNMADD231SS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMADD231SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMADD231SS_RZ_SAE_Z(x, x1, k, x2) } + +// VFNMADD231SS_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD231SS.Z m32 xmm k xmm +// VFNMADD231SS.Z xmm xmm k xmm +// Construct and append a VFNMADD231SS.Z instruction to the active function. +func (c *Context) VFNMADD231SS_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VFNMADD231SS_Z(mx, x, k, x1)) +} + +// VFNMADD231SS_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD231SS.Z m32 xmm k xmm +// VFNMADD231SS.Z xmm xmm k xmm +// Construct and append a VFNMADD231SS.Z instruction to the active function. +// Operates on the global context. +func VFNMADD231SS_Z(mx, x, k, x1 operand.Op) { ctx.VFNMADD231SS_Z(mx, x, k, x1) } + +// VFNMSUB132PD: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB132PD m128 xmm xmm +// VFNMSUB132PD m256 ymm ymm +// VFNMSUB132PD xmm xmm xmm +// VFNMSUB132PD ymm ymm ymm +// VFNMSUB132PD m128 xmm k xmm +// VFNMSUB132PD m256 ymm k ymm +// VFNMSUB132PD xmm xmm k xmm +// VFNMSUB132PD ymm ymm k ymm +// VFNMSUB132PD m512 zmm k zmm +// VFNMSUB132PD m512 zmm zmm +// VFNMSUB132PD zmm zmm k zmm +// VFNMSUB132PD zmm zmm zmm +// Construct and append a VFNMSUB132PD instruction to the active function. +func (c *Context) VFNMSUB132PD(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB132PD(ops...)) +} + +// VFNMSUB132PD: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB132PD m128 xmm xmm +// VFNMSUB132PD m256 ymm ymm +// VFNMSUB132PD xmm xmm xmm +// VFNMSUB132PD ymm ymm ymm +// VFNMSUB132PD m128 xmm k xmm +// VFNMSUB132PD m256 ymm k ymm +// VFNMSUB132PD xmm xmm k xmm +// VFNMSUB132PD ymm ymm k ymm +// VFNMSUB132PD m512 zmm k zmm +// VFNMSUB132PD m512 zmm zmm +// VFNMSUB132PD zmm zmm k zmm +// VFNMSUB132PD zmm zmm zmm +// Construct and append a VFNMSUB132PD instruction to the active function. +// Operates on the global context. +func VFNMSUB132PD(ops ...operand.Op) { ctx.VFNMSUB132PD(ops...) } + +// VFNMSUB132PD_BCST: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMSUB132PD.BCST m64 xmm k xmm +// VFNMSUB132PD.BCST m64 xmm xmm +// VFNMSUB132PD.BCST m64 ymm k ymm +// VFNMSUB132PD.BCST m64 ymm ymm +// VFNMSUB132PD.BCST m64 zmm k zmm +// VFNMSUB132PD.BCST m64 zmm zmm +// Construct and append a VFNMSUB132PD.BCST instruction to the active function. +func (c *Context) VFNMSUB132PD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB132PD_BCST(ops...)) +} + +// VFNMSUB132PD_BCST: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMSUB132PD.BCST m64 xmm k xmm +// VFNMSUB132PD.BCST m64 xmm xmm +// VFNMSUB132PD.BCST m64 ymm k ymm +// VFNMSUB132PD.BCST m64 ymm ymm +// VFNMSUB132PD.BCST m64 zmm k zmm +// VFNMSUB132PD.BCST m64 zmm zmm +// Construct and append a VFNMSUB132PD.BCST instruction to the active function. +// Operates on the global context. +func VFNMSUB132PD_BCST(ops ...operand.Op) { ctx.VFNMSUB132PD_BCST(ops...) } + +// VFNMSUB132PD_BCST_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PD.BCST.Z m64 xmm k xmm +// VFNMSUB132PD.BCST.Z m64 ymm k ymm +// VFNMSUB132PD.BCST.Z m64 zmm k zmm +// Construct and append a VFNMSUB132PD.BCST.Z instruction to the active function. +func (c *Context) VFNMSUB132PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFNMSUB132PD_BCST_Z(m, xyz, k, xyz1)) +} + +// VFNMSUB132PD_BCST_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PD.BCST.Z m64 xmm k xmm +// VFNMSUB132PD.BCST.Z m64 ymm k ymm +// VFNMSUB132PD.BCST.Z m64 zmm k zmm +// Construct and append a VFNMSUB132PD.BCST.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB132PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFNMSUB132PD_BCST_Z(m, xyz, k, xyz1) } + +// VFNMSUB132PD_RD_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB132PD.RD_SAE zmm zmm k zmm +// VFNMSUB132PD.RD_SAE zmm zmm zmm +// Construct and append a VFNMSUB132PD.RD_SAE instruction to the active function. +func (c *Context) VFNMSUB132PD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB132PD_RD_SAE(ops...)) +} + +// VFNMSUB132PD_RD_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB132PD.RD_SAE zmm zmm k zmm +// VFNMSUB132PD.RD_SAE zmm zmm zmm +// Construct and append a VFNMSUB132PD.RD_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB132PD_RD_SAE(ops ...operand.Op) { ctx.VFNMSUB132PD_RD_SAE(ops...) } + +// VFNMSUB132PD_RD_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB132PD.RD_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB132PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMSUB132PD_RD_SAE_Z(z, z1, k, z2)) +} + +// VFNMSUB132PD_RD_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB132PD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB132PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMSUB132PD_RD_SAE_Z(z, z1, k, z2) } + +// VFNMSUB132PD_RN_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB132PD.RN_SAE zmm zmm k zmm +// VFNMSUB132PD.RN_SAE zmm zmm zmm +// Construct and append a VFNMSUB132PD.RN_SAE instruction to the active function. +func (c *Context) VFNMSUB132PD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB132PD_RN_SAE(ops...)) +} + +// VFNMSUB132PD_RN_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB132PD.RN_SAE zmm zmm k zmm +// VFNMSUB132PD.RN_SAE zmm zmm zmm +// Construct and append a VFNMSUB132PD.RN_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB132PD_RN_SAE(ops ...operand.Op) { ctx.VFNMSUB132PD_RN_SAE(ops...) } + +// VFNMSUB132PD_RN_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB132PD.RN_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB132PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMSUB132PD_RN_SAE_Z(z, z1, k, z2)) +} + +// VFNMSUB132PD_RN_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB132PD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB132PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMSUB132PD_RN_SAE_Z(z, z1, k, z2) } + +// VFNMSUB132PD_RU_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB132PD.RU_SAE zmm zmm k zmm +// VFNMSUB132PD.RU_SAE zmm zmm zmm +// Construct and append a VFNMSUB132PD.RU_SAE instruction to the active function. +func (c *Context) VFNMSUB132PD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB132PD_RU_SAE(ops...)) +} + +// VFNMSUB132PD_RU_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB132PD.RU_SAE zmm zmm k zmm +// VFNMSUB132PD.RU_SAE zmm zmm zmm +// Construct and append a VFNMSUB132PD.RU_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB132PD_RU_SAE(ops ...operand.Op) { ctx.VFNMSUB132PD_RU_SAE(ops...) } + +// VFNMSUB132PD_RU_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB132PD.RU_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB132PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMSUB132PD_RU_SAE_Z(z, z1, k, z2)) +} + +// VFNMSUB132PD_RU_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB132PD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB132PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMSUB132PD_RU_SAE_Z(z, z1, k, z2) } + +// VFNMSUB132PD_RZ_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB132PD.RZ_SAE zmm zmm k zmm +// VFNMSUB132PD.RZ_SAE zmm zmm zmm +// Construct and append a VFNMSUB132PD.RZ_SAE instruction to the active function. +func (c *Context) VFNMSUB132PD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB132PD_RZ_SAE(ops...)) +} + +// VFNMSUB132PD_RZ_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB132PD.RZ_SAE zmm zmm k zmm +// VFNMSUB132PD.RZ_SAE zmm zmm zmm +// Construct and append a VFNMSUB132PD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB132PD_RZ_SAE(ops ...operand.Op) { ctx.VFNMSUB132PD_RZ_SAE(ops...) } + +// VFNMSUB132PD_RZ_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB132PD.RZ_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB132PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMSUB132PD_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFNMSUB132PD_RZ_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB132PD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB132PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMSUB132PD_RZ_SAE_Z(z, z1, k, z2) } + +// VFNMSUB132PD_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PD.Z m128 xmm k xmm +// VFNMSUB132PD.Z m256 ymm k ymm +// VFNMSUB132PD.Z xmm xmm k xmm +// VFNMSUB132PD.Z ymm ymm k ymm +// VFNMSUB132PD.Z m512 zmm k zmm +// VFNMSUB132PD.Z zmm zmm k zmm +// Construct and append a VFNMSUB132PD.Z instruction to the active function. +func (c *Context) VFNMSUB132PD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFNMSUB132PD_Z(mxyz, xyz, k, xyz1)) +} + +// VFNMSUB132PD_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PD.Z m128 xmm k xmm +// VFNMSUB132PD.Z m256 ymm k ymm +// VFNMSUB132PD.Z xmm xmm k xmm +// VFNMSUB132PD.Z ymm ymm k ymm +// VFNMSUB132PD.Z m512 zmm k zmm +// VFNMSUB132PD.Z zmm zmm k zmm +// Construct and append a VFNMSUB132PD.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB132PD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFNMSUB132PD_Z(mxyz, xyz, k, xyz1) } + +// VFNMSUB132PS: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB132PS m128 xmm xmm +// VFNMSUB132PS m256 ymm ymm +// VFNMSUB132PS xmm xmm xmm +// VFNMSUB132PS ymm ymm ymm +// VFNMSUB132PS m128 xmm k xmm +// VFNMSUB132PS m256 ymm k ymm +// VFNMSUB132PS xmm xmm k xmm +// VFNMSUB132PS ymm ymm k ymm +// VFNMSUB132PS m512 zmm k zmm +// VFNMSUB132PS m512 zmm zmm +// VFNMSUB132PS zmm zmm k zmm +// VFNMSUB132PS zmm zmm zmm +// Construct and append a VFNMSUB132PS instruction to the active function. +func (c *Context) VFNMSUB132PS(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB132PS(ops...)) +} + +// VFNMSUB132PS: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB132PS m128 xmm xmm +// VFNMSUB132PS m256 ymm ymm +// VFNMSUB132PS xmm xmm xmm +// VFNMSUB132PS ymm ymm ymm +// VFNMSUB132PS m128 xmm k xmm +// VFNMSUB132PS m256 ymm k ymm +// VFNMSUB132PS xmm xmm k xmm +// VFNMSUB132PS ymm ymm k ymm +// VFNMSUB132PS m512 zmm k zmm +// VFNMSUB132PS m512 zmm zmm +// VFNMSUB132PS zmm zmm k zmm +// VFNMSUB132PS zmm zmm zmm +// Construct and append a VFNMSUB132PS instruction to the active function. +// Operates on the global context. +func VFNMSUB132PS(ops ...operand.Op) { ctx.VFNMSUB132PS(ops...) } + +// VFNMSUB132PS_BCST: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMSUB132PS.BCST m32 xmm k xmm +// VFNMSUB132PS.BCST m32 xmm xmm +// VFNMSUB132PS.BCST m32 ymm k ymm +// VFNMSUB132PS.BCST m32 ymm ymm +// VFNMSUB132PS.BCST m32 zmm k zmm +// VFNMSUB132PS.BCST m32 zmm zmm +// Construct and append a VFNMSUB132PS.BCST instruction to the active function. +func (c *Context) VFNMSUB132PS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB132PS_BCST(ops...)) +} + +// VFNMSUB132PS_BCST: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMSUB132PS.BCST m32 xmm k xmm +// VFNMSUB132PS.BCST m32 xmm xmm +// VFNMSUB132PS.BCST m32 ymm k ymm +// VFNMSUB132PS.BCST m32 ymm ymm +// VFNMSUB132PS.BCST m32 zmm k zmm +// VFNMSUB132PS.BCST m32 zmm zmm +// Construct and append a VFNMSUB132PS.BCST instruction to the active function. +// Operates on the global context. +func VFNMSUB132PS_BCST(ops ...operand.Op) { ctx.VFNMSUB132PS_BCST(ops...) } + +// VFNMSUB132PS_BCST_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PS.BCST.Z m32 xmm k xmm +// VFNMSUB132PS.BCST.Z m32 ymm k ymm +// VFNMSUB132PS.BCST.Z m32 zmm k zmm +// Construct and append a VFNMSUB132PS.BCST.Z instruction to the active function. +func (c *Context) VFNMSUB132PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFNMSUB132PS_BCST_Z(m, xyz, k, xyz1)) +} + +// VFNMSUB132PS_BCST_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PS.BCST.Z m32 xmm k xmm +// VFNMSUB132PS.BCST.Z m32 ymm k ymm +// VFNMSUB132PS.BCST.Z m32 zmm k zmm +// Construct and append a VFNMSUB132PS.BCST.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB132PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFNMSUB132PS_BCST_Z(m, xyz, k, xyz1) } + +// VFNMSUB132PS_RD_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB132PS.RD_SAE zmm zmm k zmm +// VFNMSUB132PS.RD_SAE zmm zmm zmm +// Construct and append a VFNMSUB132PS.RD_SAE instruction to the active function. +func (c *Context) VFNMSUB132PS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB132PS_RD_SAE(ops...)) +} + +// VFNMSUB132PS_RD_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB132PS.RD_SAE zmm zmm k zmm +// VFNMSUB132PS.RD_SAE zmm zmm zmm +// Construct and append a VFNMSUB132PS.RD_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB132PS_RD_SAE(ops ...operand.Op) { ctx.VFNMSUB132PS_RD_SAE(ops...) } + +// VFNMSUB132PS_RD_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB132PS.RD_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB132PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMSUB132PS_RD_SAE_Z(z, z1, k, z2)) +} + +// VFNMSUB132PS_RD_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB132PS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB132PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMSUB132PS_RD_SAE_Z(z, z1, k, z2) } + +// VFNMSUB132PS_RN_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB132PS.RN_SAE zmm zmm k zmm +// VFNMSUB132PS.RN_SAE zmm zmm zmm +// Construct and append a VFNMSUB132PS.RN_SAE instruction to the active function. +func (c *Context) VFNMSUB132PS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB132PS_RN_SAE(ops...)) +} + +// VFNMSUB132PS_RN_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB132PS.RN_SAE zmm zmm k zmm +// VFNMSUB132PS.RN_SAE zmm zmm zmm +// Construct and append a VFNMSUB132PS.RN_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB132PS_RN_SAE(ops ...operand.Op) { ctx.VFNMSUB132PS_RN_SAE(ops...) } + +// VFNMSUB132PS_RN_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB132PS.RN_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB132PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMSUB132PS_RN_SAE_Z(z, z1, k, z2)) +} + +// VFNMSUB132PS_RN_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB132PS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB132PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMSUB132PS_RN_SAE_Z(z, z1, k, z2) } + +// VFNMSUB132PS_RU_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB132PS.RU_SAE zmm zmm k zmm +// VFNMSUB132PS.RU_SAE zmm zmm zmm +// Construct and append a VFNMSUB132PS.RU_SAE instruction to the active function. +func (c *Context) VFNMSUB132PS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB132PS_RU_SAE(ops...)) +} + +// VFNMSUB132PS_RU_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB132PS.RU_SAE zmm zmm k zmm +// VFNMSUB132PS.RU_SAE zmm zmm zmm +// Construct and append a VFNMSUB132PS.RU_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB132PS_RU_SAE(ops ...operand.Op) { ctx.VFNMSUB132PS_RU_SAE(ops...) } + +// VFNMSUB132PS_RU_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB132PS.RU_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB132PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMSUB132PS_RU_SAE_Z(z, z1, k, z2)) +} + +// VFNMSUB132PS_RU_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB132PS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB132PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMSUB132PS_RU_SAE_Z(z, z1, k, z2) } + +// VFNMSUB132PS_RZ_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB132PS.RZ_SAE zmm zmm k zmm +// VFNMSUB132PS.RZ_SAE zmm zmm zmm +// Construct and append a VFNMSUB132PS.RZ_SAE instruction to the active function. +func (c *Context) VFNMSUB132PS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB132PS_RZ_SAE(ops...)) +} + +// VFNMSUB132PS_RZ_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB132PS.RZ_SAE zmm zmm k zmm +// VFNMSUB132PS.RZ_SAE zmm zmm zmm +// Construct and append a VFNMSUB132PS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB132PS_RZ_SAE(ops ...operand.Op) { ctx.VFNMSUB132PS_RZ_SAE(ops...) } + +// VFNMSUB132PS_RZ_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB132PS.RZ_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB132PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMSUB132PS_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFNMSUB132PS_RZ_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB132PS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB132PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMSUB132PS_RZ_SAE_Z(z, z1, k, z2) } + +// VFNMSUB132PS_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PS.Z m128 xmm k xmm +// VFNMSUB132PS.Z m256 ymm k ymm +// VFNMSUB132PS.Z xmm xmm k xmm +// VFNMSUB132PS.Z ymm ymm k ymm +// VFNMSUB132PS.Z m512 zmm k zmm +// VFNMSUB132PS.Z zmm zmm k zmm +// Construct and append a VFNMSUB132PS.Z instruction to the active function. +func (c *Context) VFNMSUB132PS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFNMSUB132PS_Z(mxyz, xyz, k, xyz1)) +} + +// VFNMSUB132PS_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PS.Z m128 xmm k xmm +// VFNMSUB132PS.Z m256 ymm k ymm +// VFNMSUB132PS.Z xmm xmm k xmm +// VFNMSUB132PS.Z ymm ymm k ymm +// VFNMSUB132PS.Z m512 zmm k zmm +// VFNMSUB132PS.Z zmm zmm k zmm +// Construct and append a VFNMSUB132PS.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB132PS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFNMSUB132PS_Z(mxyz, xyz, k, xyz1) } + +// VFNMSUB132SD: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB132SD m64 xmm xmm +// VFNMSUB132SD xmm xmm xmm +// VFNMSUB132SD m64 xmm k xmm +// VFNMSUB132SD xmm xmm k xmm +// Construct and append a VFNMSUB132SD instruction to the active function. +func (c *Context) VFNMSUB132SD(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB132SD(ops...)) +} + +// VFNMSUB132SD: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB132SD m64 xmm xmm +// VFNMSUB132SD xmm xmm xmm +// VFNMSUB132SD m64 xmm k xmm +// VFNMSUB132SD xmm xmm k xmm +// Construct and append a VFNMSUB132SD instruction to the active function. +// Operates on the global context. +func VFNMSUB132SD(ops ...operand.Op) { ctx.VFNMSUB132SD(ops...) } + +// VFNMSUB132SD_RD_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB132SD.RD_SAE xmm xmm k xmm +// VFNMSUB132SD.RD_SAE xmm xmm xmm +// Construct and append a VFNMSUB132SD.RD_SAE instruction to the active function. +func (c *Context) VFNMSUB132SD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB132SD_RD_SAE(ops...)) +} + +// VFNMSUB132SD_RD_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB132SD.RD_SAE xmm xmm k xmm +// VFNMSUB132SD.RD_SAE xmm xmm xmm +// Construct and append a VFNMSUB132SD.RD_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB132SD_RD_SAE(ops ...operand.Op) { ctx.VFNMSUB132SD_RD_SAE(ops...) } + +// VFNMSUB132SD_RD_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132SD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB132SD.RD_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB132SD_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMSUB132SD_RD_SAE_Z(x, x1, k, x2)) +} + +// VFNMSUB132SD_RD_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132SD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB132SD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB132SD_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMSUB132SD_RD_SAE_Z(x, x1, k, x2) } + +// VFNMSUB132SD_RN_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB132SD.RN_SAE xmm xmm k xmm +// VFNMSUB132SD.RN_SAE xmm xmm xmm +// Construct and append a VFNMSUB132SD.RN_SAE instruction to the active function. +func (c *Context) VFNMSUB132SD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB132SD_RN_SAE(ops...)) +} + +// VFNMSUB132SD_RN_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB132SD.RN_SAE xmm xmm k xmm +// VFNMSUB132SD.RN_SAE xmm xmm xmm +// Construct and append a VFNMSUB132SD.RN_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB132SD_RN_SAE(ops ...operand.Op) { ctx.VFNMSUB132SD_RN_SAE(ops...) } + +// VFNMSUB132SD_RN_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132SD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB132SD.RN_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB132SD_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMSUB132SD_RN_SAE_Z(x, x1, k, x2)) +} + +// VFNMSUB132SD_RN_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132SD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB132SD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB132SD_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMSUB132SD_RN_SAE_Z(x, x1, k, x2) } + +// VFNMSUB132SD_RU_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB132SD.RU_SAE xmm xmm k xmm +// VFNMSUB132SD.RU_SAE xmm xmm xmm +// Construct and append a VFNMSUB132SD.RU_SAE instruction to the active function. +func (c *Context) VFNMSUB132SD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB132SD_RU_SAE(ops...)) +} + +// VFNMSUB132SD_RU_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB132SD.RU_SAE xmm xmm k xmm +// VFNMSUB132SD.RU_SAE xmm xmm xmm +// Construct and append a VFNMSUB132SD.RU_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB132SD_RU_SAE(ops ...operand.Op) { ctx.VFNMSUB132SD_RU_SAE(ops...) } + +// VFNMSUB132SD_RU_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132SD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB132SD.RU_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB132SD_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMSUB132SD_RU_SAE_Z(x, x1, k, x2)) +} + +// VFNMSUB132SD_RU_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132SD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB132SD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB132SD_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMSUB132SD_RU_SAE_Z(x, x1, k, x2) } + +// VFNMSUB132SD_RZ_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB132SD.RZ_SAE xmm xmm k xmm +// VFNMSUB132SD.RZ_SAE xmm xmm xmm +// Construct and append a VFNMSUB132SD.RZ_SAE instruction to the active function. +func (c *Context) VFNMSUB132SD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB132SD_RZ_SAE(ops...)) +} + +// VFNMSUB132SD_RZ_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB132SD.RZ_SAE xmm xmm k xmm +// VFNMSUB132SD.RZ_SAE xmm xmm xmm +// Construct and append a VFNMSUB132SD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB132SD_RZ_SAE(ops ...operand.Op) { ctx.VFNMSUB132SD_RZ_SAE(ops...) } + +// VFNMSUB132SD_RZ_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132SD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB132SD.RZ_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB132SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMSUB132SD_RZ_SAE_Z(x, x1, k, x2)) +} + +// VFNMSUB132SD_RZ_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132SD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB132SD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB132SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMSUB132SD_RZ_SAE_Z(x, x1, k, x2) } + +// VFNMSUB132SD_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB132SD.Z m64 xmm k xmm +// VFNMSUB132SD.Z xmm xmm k xmm +// Construct and append a VFNMSUB132SD.Z instruction to the active function. +func (c *Context) VFNMSUB132SD_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VFNMSUB132SD_Z(mx, x, k, x1)) +} + +// VFNMSUB132SD_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB132SD.Z m64 xmm k xmm +// VFNMSUB132SD.Z xmm xmm k xmm +// Construct and append a VFNMSUB132SD.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB132SD_Z(mx, x, k, x1 operand.Op) { ctx.VFNMSUB132SD_Z(mx, x, k, x1) } + +// VFNMSUB132SS: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB132SS m32 xmm xmm +// VFNMSUB132SS xmm xmm xmm +// VFNMSUB132SS m32 xmm k xmm +// VFNMSUB132SS xmm xmm k xmm +// Construct and append a VFNMSUB132SS instruction to the active function. +func (c *Context) VFNMSUB132SS(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB132SS(ops...)) +} + +// VFNMSUB132SS: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB132SS m32 xmm xmm +// VFNMSUB132SS xmm xmm xmm +// VFNMSUB132SS m32 xmm k xmm +// VFNMSUB132SS xmm xmm k xmm +// Construct and append a VFNMSUB132SS instruction to the active function. +// Operates on the global context. +func VFNMSUB132SS(ops ...operand.Op) { ctx.VFNMSUB132SS(ops...) } + +// VFNMSUB132SS_RD_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB132SS.RD_SAE xmm xmm k xmm +// VFNMSUB132SS.RD_SAE xmm xmm xmm +// Construct and append a VFNMSUB132SS.RD_SAE instruction to the active function. +func (c *Context) VFNMSUB132SS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB132SS_RD_SAE(ops...)) +} + +// VFNMSUB132SS_RD_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB132SS.RD_SAE xmm xmm k xmm +// VFNMSUB132SS.RD_SAE xmm xmm xmm +// Construct and append a VFNMSUB132SS.RD_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB132SS_RD_SAE(ops ...operand.Op) { ctx.VFNMSUB132SS_RD_SAE(ops...) } + +// VFNMSUB132SS_RD_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132SS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB132SS.RD_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB132SS_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMSUB132SS_RD_SAE_Z(x, x1, k, x2)) +} + +// VFNMSUB132SS_RD_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132SS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB132SS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB132SS_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMSUB132SS_RD_SAE_Z(x, x1, k, x2) } + +// VFNMSUB132SS_RN_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB132SS.RN_SAE xmm xmm k xmm +// VFNMSUB132SS.RN_SAE xmm xmm xmm +// Construct and append a VFNMSUB132SS.RN_SAE instruction to the active function. +func (c *Context) VFNMSUB132SS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB132SS_RN_SAE(ops...)) +} + +// VFNMSUB132SS_RN_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB132SS.RN_SAE xmm xmm k xmm +// VFNMSUB132SS.RN_SAE xmm xmm xmm +// Construct and append a VFNMSUB132SS.RN_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB132SS_RN_SAE(ops ...operand.Op) { ctx.VFNMSUB132SS_RN_SAE(ops...) } + +// VFNMSUB132SS_RN_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132SS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB132SS.RN_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB132SS_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMSUB132SS_RN_SAE_Z(x, x1, k, x2)) +} + +// VFNMSUB132SS_RN_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132SS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB132SS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB132SS_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMSUB132SS_RN_SAE_Z(x, x1, k, x2) } + +// VFNMSUB132SS_RU_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB132SS.RU_SAE xmm xmm k xmm +// VFNMSUB132SS.RU_SAE xmm xmm xmm +// Construct and append a VFNMSUB132SS.RU_SAE instruction to the active function. +func (c *Context) VFNMSUB132SS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB132SS_RU_SAE(ops...)) +} + +// VFNMSUB132SS_RU_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB132SS.RU_SAE xmm xmm k xmm +// VFNMSUB132SS.RU_SAE xmm xmm xmm +// Construct and append a VFNMSUB132SS.RU_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB132SS_RU_SAE(ops ...operand.Op) { ctx.VFNMSUB132SS_RU_SAE(ops...) } + +// VFNMSUB132SS_RU_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132SS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB132SS.RU_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB132SS_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMSUB132SS_RU_SAE_Z(x, x1, k, x2)) +} + +// VFNMSUB132SS_RU_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132SS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB132SS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB132SS_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMSUB132SS_RU_SAE_Z(x, x1, k, x2) } + +// VFNMSUB132SS_RZ_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB132SS.RZ_SAE xmm xmm k xmm +// VFNMSUB132SS.RZ_SAE xmm xmm xmm +// Construct and append a VFNMSUB132SS.RZ_SAE instruction to the active function. +func (c *Context) VFNMSUB132SS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB132SS_RZ_SAE(ops...)) +} + +// VFNMSUB132SS_RZ_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB132SS.RZ_SAE xmm xmm k xmm +// VFNMSUB132SS.RZ_SAE xmm xmm xmm +// Construct and append a VFNMSUB132SS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB132SS_RZ_SAE(ops ...operand.Op) { ctx.VFNMSUB132SS_RZ_SAE(ops...) } + +// VFNMSUB132SS_RZ_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132SS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB132SS.RZ_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB132SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMSUB132SS_RZ_SAE_Z(x, x1, k, x2)) +} + +// VFNMSUB132SS_RZ_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132SS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB132SS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB132SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMSUB132SS_RZ_SAE_Z(x, x1, k, x2) } + +// VFNMSUB132SS_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB132SS.Z m32 xmm k xmm +// VFNMSUB132SS.Z xmm xmm k xmm +// Construct and append a VFNMSUB132SS.Z instruction to the active function. +func (c *Context) VFNMSUB132SS_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VFNMSUB132SS_Z(mx, x, k, x1)) +} + +// VFNMSUB132SS_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB132SS.Z m32 xmm k xmm +// VFNMSUB132SS.Z xmm xmm k xmm +// Construct and append a VFNMSUB132SS.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB132SS_Z(mx, x, k, x1 operand.Op) { ctx.VFNMSUB132SS_Z(mx, x, k, x1) } + +// VFNMSUB213PD: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB213PD m128 xmm xmm +// VFNMSUB213PD m256 ymm ymm +// VFNMSUB213PD xmm xmm xmm +// VFNMSUB213PD ymm ymm ymm +// VFNMSUB213PD m128 xmm k xmm +// VFNMSUB213PD m256 ymm k ymm +// VFNMSUB213PD xmm xmm k xmm +// VFNMSUB213PD ymm ymm k ymm +// VFNMSUB213PD m512 zmm k zmm +// VFNMSUB213PD m512 zmm zmm +// VFNMSUB213PD zmm zmm k zmm +// VFNMSUB213PD zmm zmm zmm +// Construct and append a VFNMSUB213PD instruction to the active function. +func (c *Context) VFNMSUB213PD(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB213PD(ops...)) +} + +// VFNMSUB213PD: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB213PD m128 xmm xmm +// VFNMSUB213PD m256 ymm ymm +// VFNMSUB213PD xmm xmm xmm +// VFNMSUB213PD ymm ymm ymm +// VFNMSUB213PD m128 xmm k xmm +// VFNMSUB213PD m256 ymm k ymm +// VFNMSUB213PD xmm xmm k xmm +// VFNMSUB213PD ymm ymm k ymm +// VFNMSUB213PD m512 zmm k zmm +// VFNMSUB213PD m512 zmm zmm +// VFNMSUB213PD zmm zmm k zmm +// VFNMSUB213PD zmm zmm zmm +// Construct and append a VFNMSUB213PD instruction to the active function. +// Operates on the global context. +func VFNMSUB213PD(ops ...operand.Op) { ctx.VFNMSUB213PD(ops...) } + +// VFNMSUB213PD_BCST: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMSUB213PD.BCST m64 xmm k xmm +// VFNMSUB213PD.BCST m64 xmm xmm +// VFNMSUB213PD.BCST m64 ymm k ymm +// VFNMSUB213PD.BCST m64 ymm ymm +// VFNMSUB213PD.BCST m64 zmm k zmm +// VFNMSUB213PD.BCST m64 zmm zmm +// Construct and append a VFNMSUB213PD.BCST instruction to the active function. +func (c *Context) VFNMSUB213PD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB213PD_BCST(ops...)) +} + +// VFNMSUB213PD_BCST: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMSUB213PD.BCST m64 xmm k xmm +// VFNMSUB213PD.BCST m64 xmm xmm +// VFNMSUB213PD.BCST m64 ymm k ymm +// VFNMSUB213PD.BCST m64 ymm ymm +// VFNMSUB213PD.BCST m64 zmm k zmm +// VFNMSUB213PD.BCST m64 zmm zmm +// Construct and append a VFNMSUB213PD.BCST instruction to the active function. +// Operates on the global context. +func VFNMSUB213PD_BCST(ops ...operand.Op) { ctx.VFNMSUB213PD_BCST(ops...) } + +// VFNMSUB213PD_BCST_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PD.BCST.Z m64 xmm k xmm +// VFNMSUB213PD.BCST.Z m64 ymm k ymm +// VFNMSUB213PD.BCST.Z m64 zmm k zmm +// Construct and append a VFNMSUB213PD.BCST.Z instruction to the active function. +func (c *Context) VFNMSUB213PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFNMSUB213PD_BCST_Z(m, xyz, k, xyz1)) +} + +// VFNMSUB213PD_BCST_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PD.BCST.Z m64 xmm k xmm +// VFNMSUB213PD.BCST.Z m64 ymm k ymm +// VFNMSUB213PD.BCST.Z m64 zmm k zmm +// Construct and append a VFNMSUB213PD.BCST.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB213PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFNMSUB213PD_BCST_Z(m, xyz, k, xyz1) } + +// VFNMSUB213PD_RD_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB213PD.RD_SAE zmm zmm k zmm +// VFNMSUB213PD.RD_SAE zmm zmm zmm +// Construct and append a VFNMSUB213PD.RD_SAE instruction to the active function. +func (c *Context) VFNMSUB213PD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB213PD_RD_SAE(ops...)) +} + +// VFNMSUB213PD_RD_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB213PD.RD_SAE zmm zmm k zmm +// VFNMSUB213PD.RD_SAE zmm zmm zmm +// Construct and append a VFNMSUB213PD.RD_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB213PD_RD_SAE(ops ...operand.Op) { ctx.VFNMSUB213PD_RD_SAE(ops...) } + +// VFNMSUB213PD_RD_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB213PD.RD_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB213PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMSUB213PD_RD_SAE_Z(z, z1, k, z2)) +} + +// VFNMSUB213PD_RD_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB213PD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB213PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMSUB213PD_RD_SAE_Z(z, z1, k, z2) } + +// VFNMSUB213PD_RN_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB213PD.RN_SAE zmm zmm k zmm +// VFNMSUB213PD.RN_SAE zmm zmm zmm +// Construct and append a VFNMSUB213PD.RN_SAE instruction to the active function. +func (c *Context) VFNMSUB213PD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB213PD_RN_SAE(ops...)) +} + +// VFNMSUB213PD_RN_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB213PD.RN_SAE zmm zmm k zmm +// VFNMSUB213PD.RN_SAE zmm zmm zmm +// Construct and append a VFNMSUB213PD.RN_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB213PD_RN_SAE(ops ...operand.Op) { ctx.VFNMSUB213PD_RN_SAE(ops...) } + +// VFNMSUB213PD_RN_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB213PD.RN_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB213PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMSUB213PD_RN_SAE_Z(z, z1, k, z2)) +} + +// VFNMSUB213PD_RN_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB213PD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB213PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMSUB213PD_RN_SAE_Z(z, z1, k, z2) } + +// VFNMSUB213PD_RU_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB213PD.RU_SAE zmm zmm k zmm +// VFNMSUB213PD.RU_SAE zmm zmm zmm +// Construct and append a VFNMSUB213PD.RU_SAE instruction to the active function. +func (c *Context) VFNMSUB213PD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB213PD_RU_SAE(ops...)) +} + +// VFNMSUB213PD_RU_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB213PD.RU_SAE zmm zmm k zmm +// VFNMSUB213PD.RU_SAE zmm zmm zmm +// Construct and append a VFNMSUB213PD.RU_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB213PD_RU_SAE(ops ...operand.Op) { ctx.VFNMSUB213PD_RU_SAE(ops...) } + +// VFNMSUB213PD_RU_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB213PD.RU_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB213PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMSUB213PD_RU_SAE_Z(z, z1, k, z2)) +} + +// VFNMSUB213PD_RU_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB213PD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB213PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMSUB213PD_RU_SAE_Z(z, z1, k, z2) } + +// VFNMSUB213PD_RZ_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB213PD.RZ_SAE zmm zmm k zmm +// VFNMSUB213PD.RZ_SAE zmm zmm zmm +// Construct and append a VFNMSUB213PD.RZ_SAE instruction to the active function. +func (c *Context) VFNMSUB213PD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB213PD_RZ_SAE(ops...)) +} + +// VFNMSUB213PD_RZ_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB213PD.RZ_SAE zmm zmm k zmm +// VFNMSUB213PD.RZ_SAE zmm zmm zmm +// Construct and append a VFNMSUB213PD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB213PD_RZ_SAE(ops ...operand.Op) { ctx.VFNMSUB213PD_RZ_SAE(ops...) } + +// VFNMSUB213PD_RZ_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB213PD.RZ_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB213PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMSUB213PD_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFNMSUB213PD_RZ_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB213PD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB213PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMSUB213PD_RZ_SAE_Z(z, z1, k, z2) } + +// VFNMSUB213PD_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PD.Z m128 xmm k xmm +// VFNMSUB213PD.Z m256 ymm k ymm +// VFNMSUB213PD.Z xmm xmm k xmm +// VFNMSUB213PD.Z ymm ymm k ymm +// VFNMSUB213PD.Z m512 zmm k zmm +// VFNMSUB213PD.Z zmm zmm k zmm +// Construct and append a VFNMSUB213PD.Z instruction to the active function. +func (c *Context) VFNMSUB213PD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFNMSUB213PD_Z(mxyz, xyz, k, xyz1)) +} + +// VFNMSUB213PD_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PD.Z m128 xmm k xmm +// VFNMSUB213PD.Z m256 ymm k ymm +// VFNMSUB213PD.Z xmm xmm k xmm +// VFNMSUB213PD.Z ymm ymm k ymm +// VFNMSUB213PD.Z m512 zmm k zmm +// VFNMSUB213PD.Z zmm zmm k zmm +// Construct and append a VFNMSUB213PD.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB213PD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFNMSUB213PD_Z(mxyz, xyz, k, xyz1) } + +// VFNMSUB213PS: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB213PS m128 xmm xmm +// VFNMSUB213PS m256 ymm ymm +// VFNMSUB213PS xmm xmm xmm +// VFNMSUB213PS ymm ymm ymm +// VFNMSUB213PS m128 xmm k xmm +// VFNMSUB213PS m256 ymm k ymm +// VFNMSUB213PS xmm xmm k xmm +// VFNMSUB213PS ymm ymm k ymm +// VFNMSUB213PS m512 zmm k zmm +// VFNMSUB213PS m512 zmm zmm +// VFNMSUB213PS zmm zmm k zmm +// VFNMSUB213PS zmm zmm zmm +// Construct and append a VFNMSUB213PS instruction to the active function. +func (c *Context) VFNMSUB213PS(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB213PS(ops...)) +} + +// VFNMSUB213PS: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB213PS m128 xmm xmm +// VFNMSUB213PS m256 ymm ymm +// VFNMSUB213PS xmm xmm xmm +// VFNMSUB213PS ymm ymm ymm +// VFNMSUB213PS m128 xmm k xmm +// VFNMSUB213PS m256 ymm k ymm +// VFNMSUB213PS xmm xmm k xmm +// VFNMSUB213PS ymm ymm k ymm +// VFNMSUB213PS m512 zmm k zmm +// VFNMSUB213PS m512 zmm zmm +// VFNMSUB213PS zmm zmm k zmm +// VFNMSUB213PS zmm zmm zmm +// Construct and append a VFNMSUB213PS instruction to the active function. +// Operates on the global context. +func VFNMSUB213PS(ops ...operand.Op) { ctx.VFNMSUB213PS(ops...) } + +// VFNMSUB213PS_BCST: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMSUB213PS.BCST m32 xmm k xmm +// VFNMSUB213PS.BCST m32 xmm xmm +// VFNMSUB213PS.BCST m32 ymm k ymm +// VFNMSUB213PS.BCST m32 ymm ymm +// VFNMSUB213PS.BCST m32 zmm k zmm +// VFNMSUB213PS.BCST m32 zmm zmm +// Construct and append a VFNMSUB213PS.BCST instruction to the active function. +func (c *Context) VFNMSUB213PS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB213PS_BCST(ops...)) +} + +// VFNMSUB213PS_BCST: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMSUB213PS.BCST m32 xmm k xmm +// VFNMSUB213PS.BCST m32 xmm xmm +// VFNMSUB213PS.BCST m32 ymm k ymm +// VFNMSUB213PS.BCST m32 ymm ymm +// VFNMSUB213PS.BCST m32 zmm k zmm +// VFNMSUB213PS.BCST m32 zmm zmm +// Construct and append a VFNMSUB213PS.BCST instruction to the active function. +// Operates on the global context. +func VFNMSUB213PS_BCST(ops ...operand.Op) { ctx.VFNMSUB213PS_BCST(ops...) } + +// VFNMSUB213PS_BCST_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PS.BCST.Z m32 xmm k xmm +// VFNMSUB213PS.BCST.Z m32 ymm k ymm +// VFNMSUB213PS.BCST.Z m32 zmm k zmm +// Construct and append a VFNMSUB213PS.BCST.Z instruction to the active function. +func (c *Context) VFNMSUB213PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFNMSUB213PS_BCST_Z(m, xyz, k, xyz1)) +} + +// VFNMSUB213PS_BCST_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PS.BCST.Z m32 xmm k xmm +// VFNMSUB213PS.BCST.Z m32 ymm k ymm +// VFNMSUB213PS.BCST.Z m32 zmm k zmm +// Construct and append a VFNMSUB213PS.BCST.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB213PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFNMSUB213PS_BCST_Z(m, xyz, k, xyz1) } + +// VFNMSUB213PS_RD_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB213PS.RD_SAE zmm zmm k zmm +// VFNMSUB213PS.RD_SAE zmm zmm zmm +// Construct and append a VFNMSUB213PS.RD_SAE instruction to the active function. +func (c *Context) VFNMSUB213PS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB213PS_RD_SAE(ops...)) +} + +// VFNMSUB213PS_RD_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB213PS.RD_SAE zmm zmm k zmm +// VFNMSUB213PS.RD_SAE zmm zmm zmm +// Construct and append a VFNMSUB213PS.RD_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB213PS_RD_SAE(ops ...operand.Op) { ctx.VFNMSUB213PS_RD_SAE(ops...) } + +// VFNMSUB213PS_RD_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB213PS.RD_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB213PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMSUB213PS_RD_SAE_Z(z, z1, k, z2)) +} + +// VFNMSUB213PS_RD_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB213PS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB213PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMSUB213PS_RD_SAE_Z(z, z1, k, z2) } + +// VFNMSUB213PS_RN_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB213PS.RN_SAE zmm zmm k zmm +// VFNMSUB213PS.RN_SAE zmm zmm zmm +// Construct and append a VFNMSUB213PS.RN_SAE instruction to the active function. +func (c *Context) VFNMSUB213PS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB213PS_RN_SAE(ops...)) +} + +// VFNMSUB213PS_RN_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB213PS.RN_SAE zmm zmm k zmm +// VFNMSUB213PS.RN_SAE zmm zmm zmm +// Construct and append a VFNMSUB213PS.RN_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB213PS_RN_SAE(ops ...operand.Op) { ctx.VFNMSUB213PS_RN_SAE(ops...) } + +// VFNMSUB213PS_RN_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB213PS.RN_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB213PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMSUB213PS_RN_SAE_Z(z, z1, k, z2)) +} + +// VFNMSUB213PS_RN_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB213PS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB213PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMSUB213PS_RN_SAE_Z(z, z1, k, z2) } + +// VFNMSUB213PS_RU_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB213PS.RU_SAE zmm zmm k zmm +// VFNMSUB213PS.RU_SAE zmm zmm zmm +// Construct and append a VFNMSUB213PS.RU_SAE instruction to the active function. +func (c *Context) VFNMSUB213PS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB213PS_RU_SAE(ops...)) +} + +// VFNMSUB213PS_RU_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB213PS.RU_SAE zmm zmm k zmm +// VFNMSUB213PS.RU_SAE zmm zmm zmm +// Construct and append a VFNMSUB213PS.RU_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB213PS_RU_SAE(ops ...operand.Op) { ctx.VFNMSUB213PS_RU_SAE(ops...) } + +// VFNMSUB213PS_RU_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB213PS.RU_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB213PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMSUB213PS_RU_SAE_Z(z, z1, k, z2)) +} + +// VFNMSUB213PS_RU_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB213PS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB213PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMSUB213PS_RU_SAE_Z(z, z1, k, z2) } + +// VFNMSUB213PS_RZ_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB213PS.RZ_SAE zmm zmm k zmm +// VFNMSUB213PS.RZ_SAE zmm zmm zmm +// Construct and append a VFNMSUB213PS.RZ_SAE instruction to the active function. +func (c *Context) VFNMSUB213PS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB213PS_RZ_SAE(ops...)) +} + +// VFNMSUB213PS_RZ_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB213PS.RZ_SAE zmm zmm k zmm +// VFNMSUB213PS.RZ_SAE zmm zmm zmm +// Construct and append a VFNMSUB213PS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB213PS_RZ_SAE(ops ...operand.Op) { ctx.VFNMSUB213PS_RZ_SAE(ops...) } + +// VFNMSUB213PS_RZ_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB213PS.RZ_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB213PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMSUB213PS_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFNMSUB213PS_RZ_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB213PS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB213PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMSUB213PS_RZ_SAE_Z(z, z1, k, z2) } + +// VFNMSUB213PS_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PS.Z m128 xmm k xmm +// VFNMSUB213PS.Z m256 ymm k ymm +// VFNMSUB213PS.Z xmm xmm k xmm +// VFNMSUB213PS.Z ymm ymm k ymm +// VFNMSUB213PS.Z m512 zmm k zmm +// VFNMSUB213PS.Z zmm zmm k zmm +// Construct and append a VFNMSUB213PS.Z instruction to the active function. +func (c *Context) VFNMSUB213PS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFNMSUB213PS_Z(mxyz, xyz, k, xyz1)) +} + +// VFNMSUB213PS_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PS.Z m128 xmm k xmm +// VFNMSUB213PS.Z m256 ymm k ymm +// VFNMSUB213PS.Z xmm xmm k xmm +// VFNMSUB213PS.Z ymm ymm k ymm +// VFNMSUB213PS.Z m512 zmm k zmm +// VFNMSUB213PS.Z zmm zmm k zmm +// Construct and append a VFNMSUB213PS.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB213PS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFNMSUB213PS_Z(mxyz, xyz, k, xyz1) } + +// VFNMSUB213SD: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB213SD m64 xmm xmm +// VFNMSUB213SD xmm xmm xmm +// VFNMSUB213SD m64 xmm k xmm +// VFNMSUB213SD xmm xmm k xmm +// Construct and append a VFNMSUB213SD instruction to the active function. +func (c *Context) VFNMSUB213SD(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB213SD(ops...)) +} + +// VFNMSUB213SD: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB213SD m64 xmm xmm +// VFNMSUB213SD xmm xmm xmm +// VFNMSUB213SD m64 xmm k xmm +// VFNMSUB213SD xmm xmm k xmm +// Construct and append a VFNMSUB213SD instruction to the active function. +// Operates on the global context. +func VFNMSUB213SD(ops ...operand.Op) { ctx.VFNMSUB213SD(ops...) } + +// VFNMSUB213SD_RD_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB213SD.RD_SAE xmm xmm k xmm +// VFNMSUB213SD.RD_SAE xmm xmm xmm +// Construct and append a VFNMSUB213SD.RD_SAE instruction to the active function. +func (c *Context) VFNMSUB213SD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB213SD_RD_SAE(ops...)) +} + +// VFNMSUB213SD_RD_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB213SD.RD_SAE xmm xmm k xmm +// VFNMSUB213SD.RD_SAE xmm xmm xmm +// Construct and append a VFNMSUB213SD.RD_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB213SD_RD_SAE(ops ...operand.Op) { ctx.VFNMSUB213SD_RD_SAE(ops...) } + +// VFNMSUB213SD_RD_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213SD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB213SD.RD_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB213SD_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMSUB213SD_RD_SAE_Z(x, x1, k, x2)) +} + +// VFNMSUB213SD_RD_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213SD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB213SD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB213SD_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMSUB213SD_RD_SAE_Z(x, x1, k, x2) } + +// VFNMSUB213SD_RN_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB213SD.RN_SAE xmm xmm k xmm +// VFNMSUB213SD.RN_SAE xmm xmm xmm +// Construct and append a VFNMSUB213SD.RN_SAE instruction to the active function. +func (c *Context) VFNMSUB213SD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB213SD_RN_SAE(ops...)) +} + +// VFNMSUB213SD_RN_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB213SD.RN_SAE xmm xmm k xmm +// VFNMSUB213SD.RN_SAE xmm xmm xmm +// Construct and append a VFNMSUB213SD.RN_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB213SD_RN_SAE(ops ...operand.Op) { ctx.VFNMSUB213SD_RN_SAE(ops...) } + +// VFNMSUB213SD_RN_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213SD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB213SD.RN_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB213SD_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMSUB213SD_RN_SAE_Z(x, x1, k, x2)) +} + +// VFNMSUB213SD_RN_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213SD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB213SD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB213SD_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMSUB213SD_RN_SAE_Z(x, x1, k, x2) } + +// VFNMSUB213SD_RU_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB213SD.RU_SAE xmm xmm k xmm +// VFNMSUB213SD.RU_SAE xmm xmm xmm +// Construct and append a VFNMSUB213SD.RU_SAE instruction to the active function. +func (c *Context) VFNMSUB213SD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB213SD_RU_SAE(ops...)) +} + +// VFNMSUB213SD_RU_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB213SD.RU_SAE xmm xmm k xmm +// VFNMSUB213SD.RU_SAE xmm xmm xmm +// Construct and append a VFNMSUB213SD.RU_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB213SD_RU_SAE(ops ...operand.Op) { ctx.VFNMSUB213SD_RU_SAE(ops...) } + +// VFNMSUB213SD_RU_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213SD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB213SD.RU_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB213SD_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMSUB213SD_RU_SAE_Z(x, x1, k, x2)) +} + +// VFNMSUB213SD_RU_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213SD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB213SD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB213SD_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMSUB213SD_RU_SAE_Z(x, x1, k, x2) } + +// VFNMSUB213SD_RZ_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB213SD.RZ_SAE xmm xmm k xmm +// VFNMSUB213SD.RZ_SAE xmm xmm xmm +// Construct and append a VFNMSUB213SD.RZ_SAE instruction to the active function. +func (c *Context) VFNMSUB213SD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB213SD_RZ_SAE(ops...)) +} + +// VFNMSUB213SD_RZ_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB213SD.RZ_SAE xmm xmm k xmm +// VFNMSUB213SD.RZ_SAE xmm xmm xmm +// Construct and append a VFNMSUB213SD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB213SD_RZ_SAE(ops ...operand.Op) { ctx.VFNMSUB213SD_RZ_SAE(ops...) } + +// VFNMSUB213SD_RZ_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213SD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB213SD.RZ_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB213SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMSUB213SD_RZ_SAE_Z(x, x1, k, x2)) +} + +// VFNMSUB213SD_RZ_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213SD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB213SD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB213SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMSUB213SD_RZ_SAE_Z(x, x1, k, x2) } + +// VFNMSUB213SD_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB213SD.Z m64 xmm k xmm +// VFNMSUB213SD.Z xmm xmm k xmm +// Construct and append a VFNMSUB213SD.Z instruction to the active function. +func (c *Context) VFNMSUB213SD_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VFNMSUB213SD_Z(mx, x, k, x1)) +} + +// VFNMSUB213SD_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB213SD.Z m64 xmm k xmm +// VFNMSUB213SD.Z xmm xmm k xmm +// Construct and append a VFNMSUB213SD.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB213SD_Z(mx, x, k, x1 operand.Op) { ctx.VFNMSUB213SD_Z(mx, x, k, x1) } + +// VFNMSUB213SS: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB213SS m32 xmm xmm +// VFNMSUB213SS xmm xmm xmm +// VFNMSUB213SS m32 xmm k xmm +// VFNMSUB213SS xmm xmm k xmm +// Construct and append a VFNMSUB213SS instruction to the active function. +func (c *Context) VFNMSUB213SS(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB213SS(ops...)) +} + +// VFNMSUB213SS: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB213SS m32 xmm xmm +// VFNMSUB213SS xmm xmm xmm +// VFNMSUB213SS m32 xmm k xmm +// VFNMSUB213SS xmm xmm k xmm +// Construct and append a VFNMSUB213SS instruction to the active function. +// Operates on the global context. +func VFNMSUB213SS(ops ...operand.Op) { ctx.VFNMSUB213SS(ops...) } + +// VFNMSUB213SS_RD_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB213SS.RD_SAE xmm xmm k xmm +// VFNMSUB213SS.RD_SAE xmm xmm xmm +// Construct and append a VFNMSUB213SS.RD_SAE instruction to the active function. +func (c *Context) VFNMSUB213SS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB213SS_RD_SAE(ops...)) +} + +// VFNMSUB213SS_RD_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB213SS.RD_SAE xmm xmm k xmm +// VFNMSUB213SS.RD_SAE xmm xmm xmm +// Construct and append a VFNMSUB213SS.RD_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB213SS_RD_SAE(ops ...operand.Op) { ctx.VFNMSUB213SS_RD_SAE(ops...) } + +// VFNMSUB213SS_RD_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213SS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB213SS.RD_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB213SS_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMSUB213SS_RD_SAE_Z(x, x1, k, x2)) +} + +// VFNMSUB213SS_RD_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213SS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB213SS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB213SS_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMSUB213SS_RD_SAE_Z(x, x1, k, x2) } + +// VFNMSUB213SS_RN_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB213SS.RN_SAE xmm xmm k xmm +// VFNMSUB213SS.RN_SAE xmm xmm xmm +// Construct and append a VFNMSUB213SS.RN_SAE instruction to the active function. +func (c *Context) VFNMSUB213SS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB213SS_RN_SAE(ops...)) +} + +// VFNMSUB213SS_RN_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB213SS.RN_SAE xmm xmm k xmm +// VFNMSUB213SS.RN_SAE xmm xmm xmm +// Construct and append a VFNMSUB213SS.RN_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB213SS_RN_SAE(ops ...operand.Op) { ctx.VFNMSUB213SS_RN_SAE(ops...) } + +// VFNMSUB213SS_RN_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213SS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB213SS.RN_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB213SS_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMSUB213SS_RN_SAE_Z(x, x1, k, x2)) +} + +// VFNMSUB213SS_RN_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213SS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB213SS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB213SS_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMSUB213SS_RN_SAE_Z(x, x1, k, x2) } + +// VFNMSUB213SS_RU_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB213SS.RU_SAE xmm xmm k xmm +// VFNMSUB213SS.RU_SAE xmm xmm xmm +// Construct and append a VFNMSUB213SS.RU_SAE instruction to the active function. +func (c *Context) VFNMSUB213SS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB213SS_RU_SAE(ops...)) +} + +// VFNMSUB213SS_RU_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB213SS.RU_SAE xmm xmm k xmm +// VFNMSUB213SS.RU_SAE xmm xmm xmm +// Construct and append a VFNMSUB213SS.RU_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB213SS_RU_SAE(ops ...operand.Op) { ctx.VFNMSUB213SS_RU_SAE(ops...) } + +// VFNMSUB213SS_RU_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213SS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB213SS.RU_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB213SS_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMSUB213SS_RU_SAE_Z(x, x1, k, x2)) +} + +// VFNMSUB213SS_RU_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213SS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB213SS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB213SS_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMSUB213SS_RU_SAE_Z(x, x1, k, x2) } + +// VFNMSUB213SS_RZ_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB213SS.RZ_SAE xmm xmm k xmm +// VFNMSUB213SS.RZ_SAE xmm xmm xmm +// Construct and append a VFNMSUB213SS.RZ_SAE instruction to the active function. +func (c *Context) VFNMSUB213SS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB213SS_RZ_SAE(ops...)) +} + +// VFNMSUB213SS_RZ_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB213SS.RZ_SAE xmm xmm k xmm +// VFNMSUB213SS.RZ_SAE xmm xmm xmm +// Construct and append a VFNMSUB213SS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB213SS_RZ_SAE(ops ...operand.Op) { ctx.VFNMSUB213SS_RZ_SAE(ops...) } + +// VFNMSUB213SS_RZ_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213SS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB213SS.RZ_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB213SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMSUB213SS_RZ_SAE_Z(x, x1, k, x2)) +} + +// VFNMSUB213SS_RZ_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213SS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB213SS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB213SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMSUB213SS_RZ_SAE_Z(x, x1, k, x2) } + +// VFNMSUB213SS_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB213SS.Z m32 xmm k xmm +// VFNMSUB213SS.Z xmm xmm k xmm +// Construct and append a VFNMSUB213SS.Z instruction to the active function. +func (c *Context) VFNMSUB213SS_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VFNMSUB213SS_Z(mx, x, k, x1)) +} + +// VFNMSUB213SS_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB213SS.Z m32 xmm k xmm +// VFNMSUB213SS.Z xmm xmm k xmm +// Construct and append a VFNMSUB213SS.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB213SS_Z(mx, x, k, x1 operand.Op) { ctx.VFNMSUB213SS_Z(mx, x, k, x1) } + +// VFNMSUB231PD: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB231PD m128 xmm xmm +// VFNMSUB231PD m256 ymm ymm +// VFNMSUB231PD xmm xmm xmm +// VFNMSUB231PD ymm ymm ymm +// VFNMSUB231PD m128 xmm k xmm +// VFNMSUB231PD m256 ymm k ymm +// VFNMSUB231PD xmm xmm k xmm +// VFNMSUB231PD ymm ymm k ymm +// VFNMSUB231PD m512 zmm k zmm +// VFNMSUB231PD m512 zmm zmm +// VFNMSUB231PD zmm zmm k zmm +// VFNMSUB231PD zmm zmm zmm +// Construct and append a VFNMSUB231PD instruction to the active function. +func (c *Context) VFNMSUB231PD(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB231PD(ops...)) +} + +// VFNMSUB231PD: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB231PD m128 xmm xmm +// VFNMSUB231PD m256 ymm ymm +// VFNMSUB231PD xmm xmm xmm +// VFNMSUB231PD ymm ymm ymm +// VFNMSUB231PD m128 xmm k xmm +// VFNMSUB231PD m256 ymm k ymm +// VFNMSUB231PD xmm xmm k xmm +// VFNMSUB231PD ymm ymm k ymm +// VFNMSUB231PD m512 zmm k zmm +// VFNMSUB231PD m512 zmm zmm +// VFNMSUB231PD zmm zmm k zmm +// VFNMSUB231PD zmm zmm zmm +// Construct and append a VFNMSUB231PD instruction to the active function. +// Operates on the global context. +func VFNMSUB231PD(ops ...operand.Op) { ctx.VFNMSUB231PD(ops...) } + +// VFNMSUB231PD_BCST: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMSUB231PD.BCST m64 xmm k xmm +// VFNMSUB231PD.BCST m64 xmm xmm +// VFNMSUB231PD.BCST m64 ymm k ymm +// VFNMSUB231PD.BCST m64 ymm ymm +// VFNMSUB231PD.BCST m64 zmm k zmm +// VFNMSUB231PD.BCST m64 zmm zmm +// Construct and append a VFNMSUB231PD.BCST instruction to the active function. +func (c *Context) VFNMSUB231PD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB231PD_BCST(ops...)) +} + +// VFNMSUB231PD_BCST: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMSUB231PD.BCST m64 xmm k xmm +// VFNMSUB231PD.BCST m64 xmm xmm +// VFNMSUB231PD.BCST m64 ymm k ymm +// VFNMSUB231PD.BCST m64 ymm ymm +// VFNMSUB231PD.BCST m64 zmm k zmm +// VFNMSUB231PD.BCST m64 zmm zmm +// Construct and append a VFNMSUB231PD.BCST instruction to the active function. +// Operates on the global context. +func VFNMSUB231PD_BCST(ops ...operand.Op) { ctx.VFNMSUB231PD_BCST(ops...) } + +// VFNMSUB231PD_BCST_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PD.BCST.Z m64 xmm k xmm +// VFNMSUB231PD.BCST.Z m64 ymm k ymm +// VFNMSUB231PD.BCST.Z m64 zmm k zmm +// Construct and append a VFNMSUB231PD.BCST.Z instruction to the active function. +func (c *Context) VFNMSUB231PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFNMSUB231PD_BCST_Z(m, xyz, k, xyz1)) +} + +// VFNMSUB231PD_BCST_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PD.BCST.Z m64 xmm k xmm +// VFNMSUB231PD.BCST.Z m64 ymm k ymm +// VFNMSUB231PD.BCST.Z m64 zmm k zmm +// Construct and append a VFNMSUB231PD.BCST.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB231PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFNMSUB231PD_BCST_Z(m, xyz, k, xyz1) } + +// VFNMSUB231PD_RD_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB231PD.RD_SAE zmm zmm k zmm +// VFNMSUB231PD.RD_SAE zmm zmm zmm +// Construct and append a VFNMSUB231PD.RD_SAE instruction to the active function. +func (c *Context) VFNMSUB231PD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB231PD_RD_SAE(ops...)) +} + +// VFNMSUB231PD_RD_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB231PD.RD_SAE zmm zmm k zmm +// VFNMSUB231PD.RD_SAE zmm zmm zmm +// Construct and append a VFNMSUB231PD.RD_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB231PD_RD_SAE(ops ...operand.Op) { ctx.VFNMSUB231PD_RD_SAE(ops...) } + +// VFNMSUB231PD_RD_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB231PD.RD_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB231PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMSUB231PD_RD_SAE_Z(z, z1, k, z2)) +} + +// VFNMSUB231PD_RD_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB231PD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB231PD_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMSUB231PD_RD_SAE_Z(z, z1, k, z2) } + +// VFNMSUB231PD_RN_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB231PD.RN_SAE zmm zmm k zmm +// VFNMSUB231PD.RN_SAE zmm zmm zmm +// Construct and append a VFNMSUB231PD.RN_SAE instruction to the active function. +func (c *Context) VFNMSUB231PD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB231PD_RN_SAE(ops...)) +} + +// VFNMSUB231PD_RN_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB231PD.RN_SAE zmm zmm k zmm +// VFNMSUB231PD.RN_SAE zmm zmm zmm +// Construct and append a VFNMSUB231PD.RN_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB231PD_RN_SAE(ops ...operand.Op) { ctx.VFNMSUB231PD_RN_SAE(ops...) } + +// VFNMSUB231PD_RN_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB231PD.RN_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB231PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMSUB231PD_RN_SAE_Z(z, z1, k, z2)) +} + +// VFNMSUB231PD_RN_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB231PD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB231PD_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMSUB231PD_RN_SAE_Z(z, z1, k, z2) } + +// VFNMSUB231PD_RU_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB231PD.RU_SAE zmm zmm k zmm +// VFNMSUB231PD.RU_SAE zmm zmm zmm +// Construct and append a VFNMSUB231PD.RU_SAE instruction to the active function. +func (c *Context) VFNMSUB231PD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB231PD_RU_SAE(ops...)) +} + +// VFNMSUB231PD_RU_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB231PD.RU_SAE zmm zmm k zmm +// VFNMSUB231PD.RU_SAE zmm zmm zmm +// Construct and append a VFNMSUB231PD.RU_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB231PD_RU_SAE(ops ...operand.Op) { ctx.VFNMSUB231PD_RU_SAE(ops...) } + +// VFNMSUB231PD_RU_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB231PD.RU_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB231PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMSUB231PD_RU_SAE_Z(z, z1, k, z2)) +} + +// VFNMSUB231PD_RU_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB231PD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB231PD_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMSUB231PD_RU_SAE_Z(z, z1, k, z2) } + +// VFNMSUB231PD_RZ_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB231PD.RZ_SAE zmm zmm k zmm +// VFNMSUB231PD.RZ_SAE zmm zmm zmm +// Construct and append a VFNMSUB231PD.RZ_SAE instruction to the active function. +func (c *Context) VFNMSUB231PD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB231PD_RZ_SAE(ops...)) +} + +// VFNMSUB231PD_RZ_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB231PD.RZ_SAE zmm zmm k zmm +// VFNMSUB231PD.RZ_SAE zmm zmm zmm +// Construct and append a VFNMSUB231PD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB231PD_RZ_SAE(ops ...operand.Op) { ctx.VFNMSUB231PD_RZ_SAE(ops...) } + +// VFNMSUB231PD_RZ_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB231PD.RZ_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB231PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMSUB231PD_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFNMSUB231PD_RZ_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB231PD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB231PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMSUB231PD_RZ_SAE_Z(z, z1, k, z2) } + +// VFNMSUB231PD_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PD.Z m128 xmm k xmm +// VFNMSUB231PD.Z m256 ymm k ymm +// VFNMSUB231PD.Z xmm xmm k xmm +// VFNMSUB231PD.Z ymm ymm k ymm +// VFNMSUB231PD.Z m512 zmm k zmm +// VFNMSUB231PD.Z zmm zmm k zmm +// Construct and append a VFNMSUB231PD.Z instruction to the active function. +func (c *Context) VFNMSUB231PD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFNMSUB231PD_Z(mxyz, xyz, k, xyz1)) +} + +// VFNMSUB231PD_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PD.Z m128 xmm k xmm +// VFNMSUB231PD.Z m256 ymm k ymm +// VFNMSUB231PD.Z xmm xmm k xmm +// VFNMSUB231PD.Z ymm ymm k ymm +// VFNMSUB231PD.Z m512 zmm k zmm +// VFNMSUB231PD.Z zmm zmm k zmm +// Construct and append a VFNMSUB231PD.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB231PD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFNMSUB231PD_Z(mxyz, xyz, k, xyz1) } + +// VFNMSUB231PS: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB231PS m128 xmm xmm +// VFNMSUB231PS m256 ymm ymm +// VFNMSUB231PS xmm xmm xmm +// VFNMSUB231PS ymm ymm ymm +// VFNMSUB231PS m128 xmm k xmm +// VFNMSUB231PS m256 ymm k ymm +// VFNMSUB231PS xmm xmm k xmm +// VFNMSUB231PS ymm ymm k ymm +// VFNMSUB231PS m512 zmm k zmm +// VFNMSUB231PS m512 zmm zmm +// VFNMSUB231PS zmm zmm k zmm +// VFNMSUB231PS zmm zmm zmm +// Construct and append a VFNMSUB231PS instruction to the active function. +func (c *Context) VFNMSUB231PS(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB231PS(ops...)) +} + +// VFNMSUB231PS: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB231PS m128 xmm xmm +// VFNMSUB231PS m256 ymm ymm +// VFNMSUB231PS xmm xmm xmm +// VFNMSUB231PS ymm ymm ymm +// VFNMSUB231PS m128 xmm k xmm +// VFNMSUB231PS m256 ymm k ymm +// VFNMSUB231PS xmm xmm k xmm +// VFNMSUB231PS ymm ymm k ymm +// VFNMSUB231PS m512 zmm k zmm +// VFNMSUB231PS m512 zmm zmm +// VFNMSUB231PS zmm zmm k zmm +// VFNMSUB231PS zmm zmm zmm +// Construct and append a VFNMSUB231PS instruction to the active function. +// Operates on the global context. +func VFNMSUB231PS(ops ...operand.Op) { ctx.VFNMSUB231PS(ops...) } + +// VFNMSUB231PS_BCST: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMSUB231PS.BCST m32 xmm k xmm +// VFNMSUB231PS.BCST m32 xmm xmm +// VFNMSUB231PS.BCST m32 ymm k ymm +// VFNMSUB231PS.BCST m32 ymm ymm +// VFNMSUB231PS.BCST m32 zmm k zmm +// VFNMSUB231PS.BCST m32 zmm zmm +// Construct and append a VFNMSUB231PS.BCST instruction to the active function. +func (c *Context) VFNMSUB231PS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB231PS_BCST(ops...)) +} + +// VFNMSUB231PS_BCST: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMSUB231PS.BCST m32 xmm k xmm +// VFNMSUB231PS.BCST m32 xmm xmm +// VFNMSUB231PS.BCST m32 ymm k ymm +// VFNMSUB231PS.BCST m32 ymm ymm +// VFNMSUB231PS.BCST m32 zmm k zmm +// VFNMSUB231PS.BCST m32 zmm zmm +// Construct and append a VFNMSUB231PS.BCST instruction to the active function. +// Operates on the global context. +func VFNMSUB231PS_BCST(ops ...operand.Op) { ctx.VFNMSUB231PS_BCST(ops...) } + +// VFNMSUB231PS_BCST_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PS.BCST.Z m32 xmm k xmm +// VFNMSUB231PS.BCST.Z m32 ymm k ymm +// VFNMSUB231PS.BCST.Z m32 zmm k zmm +// Construct and append a VFNMSUB231PS.BCST.Z instruction to the active function. +func (c *Context) VFNMSUB231PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFNMSUB231PS_BCST_Z(m, xyz, k, xyz1)) +} + +// VFNMSUB231PS_BCST_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PS.BCST.Z m32 xmm k xmm +// VFNMSUB231PS.BCST.Z m32 ymm k ymm +// VFNMSUB231PS.BCST.Z m32 zmm k zmm +// Construct and append a VFNMSUB231PS.BCST.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB231PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VFNMSUB231PS_BCST_Z(m, xyz, k, xyz1) } + +// VFNMSUB231PS_RD_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB231PS.RD_SAE zmm zmm k zmm +// VFNMSUB231PS.RD_SAE zmm zmm zmm +// Construct and append a VFNMSUB231PS.RD_SAE instruction to the active function. +func (c *Context) VFNMSUB231PS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB231PS_RD_SAE(ops...)) +} + +// VFNMSUB231PS_RD_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB231PS.RD_SAE zmm zmm k zmm +// VFNMSUB231PS.RD_SAE zmm zmm zmm +// Construct and append a VFNMSUB231PS.RD_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB231PS_RD_SAE(ops ...operand.Op) { ctx.VFNMSUB231PS_RD_SAE(ops...) } + +// VFNMSUB231PS_RD_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB231PS.RD_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB231PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMSUB231PS_RD_SAE_Z(z, z1, k, z2)) +} + +// VFNMSUB231PS_RD_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB231PS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB231PS_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMSUB231PS_RD_SAE_Z(z, z1, k, z2) } + +// VFNMSUB231PS_RN_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB231PS.RN_SAE zmm zmm k zmm +// VFNMSUB231PS.RN_SAE zmm zmm zmm +// Construct and append a VFNMSUB231PS.RN_SAE instruction to the active function. +func (c *Context) VFNMSUB231PS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB231PS_RN_SAE(ops...)) +} + +// VFNMSUB231PS_RN_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB231PS.RN_SAE zmm zmm k zmm +// VFNMSUB231PS.RN_SAE zmm zmm zmm +// Construct and append a VFNMSUB231PS.RN_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB231PS_RN_SAE(ops ...operand.Op) { ctx.VFNMSUB231PS_RN_SAE(ops...) } + +// VFNMSUB231PS_RN_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB231PS.RN_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB231PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMSUB231PS_RN_SAE_Z(z, z1, k, z2)) +} + +// VFNMSUB231PS_RN_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB231PS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB231PS_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMSUB231PS_RN_SAE_Z(z, z1, k, z2) } + +// VFNMSUB231PS_RU_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB231PS.RU_SAE zmm zmm k zmm +// VFNMSUB231PS.RU_SAE zmm zmm zmm +// Construct and append a VFNMSUB231PS.RU_SAE instruction to the active function. +func (c *Context) VFNMSUB231PS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB231PS_RU_SAE(ops...)) +} + +// VFNMSUB231PS_RU_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB231PS.RU_SAE zmm zmm k zmm +// VFNMSUB231PS.RU_SAE zmm zmm zmm +// Construct and append a VFNMSUB231PS.RU_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB231PS_RU_SAE(ops ...operand.Op) { ctx.VFNMSUB231PS_RU_SAE(ops...) } + +// VFNMSUB231PS_RU_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB231PS.RU_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB231PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMSUB231PS_RU_SAE_Z(z, z1, k, z2)) +} + +// VFNMSUB231PS_RU_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB231PS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB231PS_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMSUB231PS_RU_SAE_Z(z, z1, k, z2) } + +// VFNMSUB231PS_RZ_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB231PS.RZ_SAE zmm zmm k zmm +// VFNMSUB231PS.RZ_SAE zmm zmm zmm +// Construct and append a VFNMSUB231PS.RZ_SAE instruction to the active function. +func (c *Context) VFNMSUB231PS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB231PS_RZ_SAE(ops...)) +} + +// VFNMSUB231PS_RZ_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB231PS.RZ_SAE zmm zmm k zmm +// VFNMSUB231PS.RZ_SAE zmm zmm zmm +// Construct and append a VFNMSUB231PS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB231PS_RZ_SAE(ops ...operand.Op) { ctx.VFNMSUB231PS_RZ_SAE(ops...) } + +// VFNMSUB231PS_RZ_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB231PS.RZ_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB231PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VFNMSUB231PS_RZ_SAE_Z(z, z1, k, z2)) +} + +// VFNMSUB231PS_RZ_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VFNMSUB231PS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB231PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VFNMSUB231PS_RZ_SAE_Z(z, z1, k, z2) } + +// VFNMSUB231PS_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PS.Z m128 xmm k xmm +// VFNMSUB231PS.Z m256 ymm k ymm +// VFNMSUB231PS.Z xmm xmm k xmm +// VFNMSUB231PS.Z ymm ymm k ymm +// VFNMSUB231PS.Z m512 zmm k zmm +// VFNMSUB231PS.Z zmm zmm k zmm +// Construct and append a VFNMSUB231PS.Z instruction to the active function. +func (c *Context) VFNMSUB231PS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VFNMSUB231PS_Z(mxyz, xyz, k, xyz1)) +} + +// VFNMSUB231PS_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PS.Z m128 xmm k xmm +// VFNMSUB231PS.Z m256 ymm k ymm +// VFNMSUB231PS.Z xmm xmm k xmm +// VFNMSUB231PS.Z ymm ymm k ymm +// VFNMSUB231PS.Z m512 zmm k zmm +// VFNMSUB231PS.Z zmm zmm k zmm +// Construct and append a VFNMSUB231PS.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB231PS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VFNMSUB231PS_Z(mxyz, xyz, k, xyz1) } + +// VFNMSUB231SD: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB231SD m64 xmm xmm +// VFNMSUB231SD xmm xmm xmm +// VFNMSUB231SD m64 xmm k xmm +// VFNMSUB231SD xmm xmm k xmm +// Construct and append a VFNMSUB231SD instruction to the active function. +func (c *Context) VFNMSUB231SD(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB231SD(ops...)) +} + +// VFNMSUB231SD: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB231SD m64 xmm xmm +// VFNMSUB231SD xmm xmm xmm +// VFNMSUB231SD m64 xmm k xmm +// VFNMSUB231SD xmm xmm k xmm +// Construct and append a VFNMSUB231SD instruction to the active function. +// Operates on the global context. +func VFNMSUB231SD(ops ...operand.Op) { ctx.VFNMSUB231SD(ops...) } + +// VFNMSUB231SD_RD_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB231SD.RD_SAE xmm xmm k xmm +// VFNMSUB231SD.RD_SAE xmm xmm xmm +// Construct and append a VFNMSUB231SD.RD_SAE instruction to the active function. +func (c *Context) VFNMSUB231SD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB231SD_RD_SAE(ops...)) +} + +// VFNMSUB231SD_RD_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB231SD.RD_SAE xmm xmm k xmm +// VFNMSUB231SD.RD_SAE xmm xmm xmm +// Construct and append a VFNMSUB231SD.RD_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB231SD_RD_SAE(ops ...operand.Op) { ctx.VFNMSUB231SD_RD_SAE(ops...) } + +// VFNMSUB231SD_RD_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231SD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB231SD.RD_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB231SD_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMSUB231SD_RD_SAE_Z(x, x1, k, x2)) +} + +// VFNMSUB231SD_RD_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231SD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB231SD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB231SD_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMSUB231SD_RD_SAE_Z(x, x1, k, x2) } + +// VFNMSUB231SD_RN_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB231SD.RN_SAE xmm xmm k xmm +// VFNMSUB231SD.RN_SAE xmm xmm xmm +// Construct and append a VFNMSUB231SD.RN_SAE instruction to the active function. +func (c *Context) VFNMSUB231SD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB231SD_RN_SAE(ops...)) +} + +// VFNMSUB231SD_RN_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB231SD.RN_SAE xmm xmm k xmm +// VFNMSUB231SD.RN_SAE xmm xmm xmm +// Construct and append a VFNMSUB231SD.RN_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB231SD_RN_SAE(ops ...operand.Op) { ctx.VFNMSUB231SD_RN_SAE(ops...) } + +// VFNMSUB231SD_RN_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231SD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB231SD.RN_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB231SD_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMSUB231SD_RN_SAE_Z(x, x1, k, x2)) +} + +// VFNMSUB231SD_RN_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231SD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB231SD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB231SD_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMSUB231SD_RN_SAE_Z(x, x1, k, x2) } + +// VFNMSUB231SD_RU_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB231SD.RU_SAE xmm xmm k xmm +// VFNMSUB231SD.RU_SAE xmm xmm xmm +// Construct and append a VFNMSUB231SD.RU_SAE instruction to the active function. +func (c *Context) VFNMSUB231SD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB231SD_RU_SAE(ops...)) +} + +// VFNMSUB231SD_RU_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB231SD.RU_SAE xmm xmm k xmm +// VFNMSUB231SD.RU_SAE xmm xmm xmm +// Construct and append a VFNMSUB231SD.RU_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB231SD_RU_SAE(ops ...operand.Op) { ctx.VFNMSUB231SD_RU_SAE(ops...) } + +// VFNMSUB231SD_RU_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231SD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB231SD.RU_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB231SD_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMSUB231SD_RU_SAE_Z(x, x1, k, x2)) +} + +// VFNMSUB231SD_RU_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231SD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB231SD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB231SD_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMSUB231SD_RU_SAE_Z(x, x1, k, x2) } + +// VFNMSUB231SD_RZ_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB231SD.RZ_SAE xmm xmm k xmm +// VFNMSUB231SD.RZ_SAE xmm xmm xmm +// Construct and append a VFNMSUB231SD.RZ_SAE instruction to the active function. +func (c *Context) VFNMSUB231SD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB231SD_RZ_SAE(ops...)) +} + +// VFNMSUB231SD_RZ_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB231SD.RZ_SAE xmm xmm k xmm +// VFNMSUB231SD.RZ_SAE xmm xmm xmm +// Construct and append a VFNMSUB231SD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB231SD_RZ_SAE(ops ...operand.Op) { ctx.VFNMSUB231SD_RZ_SAE(ops...) } + +// VFNMSUB231SD_RZ_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231SD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB231SD.RZ_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB231SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMSUB231SD_RZ_SAE_Z(x, x1, k, x2)) +} + +// VFNMSUB231SD_RZ_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231SD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB231SD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB231SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMSUB231SD_RZ_SAE_Z(x, x1, k, x2) } + +// VFNMSUB231SD_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB231SD.Z m64 xmm k xmm +// VFNMSUB231SD.Z xmm xmm k xmm +// Construct and append a VFNMSUB231SD.Z instruction to the active function. +func (c *Context) VFNMSUB231SD_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VFNMSUB231SD_Z(mx, x, k, x1)) +} + +// VFNMSUB231SD_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB231SD.Z m64 xmm k xmm +// VFNMSUB231SD.Z xmm xmm k xmm +// Construct and append a VFNMSUB231SD.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB231SD_Z(mx, x, k, x1 operand.Op) { ctx.VFNMSUB231SD_Z(mx, x, k, x1) } + +// VFNMSUB231SS: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB231SS m32 xmm xmm +// VFNMSUB231SS xmm xmm xmm +// VFNMSUB231SS m32 xmm k xmm +// VFNMSUB231SS xmm xmm k xmm +// Construct and append a VFNMSUB231SS instruction to the active function. +func (c *Context) VFNMSUB231SS(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB231SS(ops...)) +} + +// VFNMSUB231SS: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB231SS m32 xmm xmm +// VFNMSUB231SS xmm xmm xmm +// VFNMSUB231SS m32 xmm k xmm +// VFNMSUB231SS xmm xmm k xmm +// Construct and append a VFNMSUB231SS instruction to the active function. +// Operates on the global context. +func VFNMSUB231SS(ops ...operand.Op) { ctx.VFNMSUB231SS(ops...) } + +// VFNMSUB231SS_RD_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB231SS.RD_SAE xmm xmm k xmm +// VFNMSUB231SS.RD_SAE xmm xmm xmm +// Construct and append a VFNMSUB231SS.RD_SAE instruction to the active function. +func (c *Context) VFNMSUB231SS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB231SS_RD_SAE(ops...)) +} + +// VFNMSUB231SS_RD_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB231SS.RD_SAE xmm xmm k xmm +// VFNMSUB231SS.RD_SAE xmm xmm xmm +// Construct and append a VFNMSUB231SS.RD_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB231SS_RD_SAE(ops ...operand.Op) { ctx.VFNMSUB231SS_RD_SAE(ops...) } + +// VFNMSUB231SS_RD_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231SS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB231SS.RD_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB231SS_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMSUB231SS_RD_SAE_Z(x, x1, k, x2)) +} + +// VFNMSUB231SS_RD_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231SS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB231SS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB231SS_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMSUB231SS_RD_SAE_Z(x, x1, k, x2) } + +// VFNMSUB231SS_RN_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB231SS.RN_SAE xmm xmm k xmm +// VFNMSUB231SS.RN_SAE xmm xmm xmm +// Construct and append a VFNMSUB231SS.RN_SAE instruction to the active function. +func (c *Context) VFNMSUB231SS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB231SS_RN_SAE(ops...)) +} + +// VFNMSUB231SS_RN_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB231SS.RN_SAE xmm xmm k xmm +// VFNMSUB231SS.RN_SAE xmm xmm xmm +// Construct and append a VFNMSUB231SS.RN_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB231SS_RN_SAE(ops ...operand.Op) { ctx.VFNMSUB231SS_RN_SAE(ops...) } + +// VFNMSUB231SS_RN_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231SS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB231SS.RN_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB231SS_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMSUB231SS_RN_SAE_Z(x, x1, k, x2)) +} + +// VFNMSUB231SS_RN_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231SS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB231SS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB231SS_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMSUB231SS_RN_SAE_Z(x, x1, k, x2) } + +// VFNMSUB231SS_RU_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB231SS.RU_SAE xmm xmm k xmm +// VFNMSUB231SS.RU_SAE xmm xmm xmm +// Construct and append a VFNMSUB231SS.RU_SAE instruction to the active function. +func (c *Context) VFNMSUB231SS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB231SS_RU_SAE(ops...)) +} + +// VFNMSUB231SS_RU_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB231SS.RU_SAE xmm xmm k xmm +// VFNMSUB231SS.RU_SAE xmm xmm xmm +// Construct and append a VFNMSUB231SS.RU_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB231SS_RU_SAE(ops ...operand.Op) { ctx.VFNMSUB231SS_RU_SAE(ops...) } + +// VFNMSUB231SS_RU_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231SS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB231SS.RU_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB231SS_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMSUB231SS_RU_SAE_Z(x, x1, k, x2)) +} + +// VFNMSUB231SS_RU_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231SS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB231SS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB231SS_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMSUB231SS_RU_SAE_Z(x, x1, k, x2) } + +// VFNMSUB231SS_RZ_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB231SS.RZ_SAE xmm xmm k xmm +// VFNMSUB231SS.RZ_SAE xmm xmm xmm +// Construct and append a VFNMSUB231SS.RZ_SAE instruction to the active function. +func (c *Context) VFNMSUB231SS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VFNMSUB231SS_RZ_SAE(ops...)) +} + +// VFNMSUB231SS_RZ_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB231SS.RZ_SAE xmm xmm k xmm +// VFNMSUB231SS.RZ_SAE xmm xmm xmm +// Construct and append a VFNMSUB231SS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VFNMSUB231SS_RZ_SAE(ops ...operand.Op) { ctx.VFNMSUB231SS_RZ_SAE(ops...) } + +// VFNMSUB231SS_RZ_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231SS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB231SS.RZ_SAE.Z instruction to the active function. +func (c *Context) VFNMSUB231SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VFNMSUB231SS_RZ_SAE_Z(x, x1, k, x2)) +} + +// VFNMSUB231SS_RZ_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231SS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VFNMSUB231SS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB231SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VFNMSUB231SS_RZ_SAE_Z(x, x1, k, x2) } + +// VFNMSUB231SS_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB231SS.Z m32 xmm k xmm +// VFNMSUB231SS.Z xmm xmm k xmm +// Construct and append a VFNMSUB231SS.Z instruction to the active function. +func (c *Context) VFNMSUB231SS_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VFNMSUB231SS_Z(mx, x, k, x1)) +} + +// VFNMSUB231SS_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB231SS.Z m32 xmm k xmm +// VFNMSUB231SS.Z xmm xmm k xmm +// Construct and append a VFNMSUB231SS.Z instruction to the active function. +// Operates on the global context. +func VFNMSUB231SS_Z(mx, x, k, x1 operand.Op) { ctx.VFNMSUB231SS_Z(mx, x, k, x1) } + +// VFPCLASSPDX: Test Class of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFPCLASSPDX imm8 m128 k k +// VFPCLASSPDX imm8 m128 k +// VFPCLASSPDX imm8 xmm k k +// VFPCLASSPDX imm8 xmm k +// Construct and append a VFPCLASSPDX instruction to the active function. +func (c *Context) VFPCLASSPDX(ops ...operand.Op) { + c.addinstruction(x86.VFPCLASSPDX(ops...)) +} + +// VFPCLASSPDX: Test Class of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFPCLASSPDX imm8 m128 k k +// VFPCLASSPDX imm8 m128 k +// VFPCLASSPDX imm8 xmm k k +// VFPCLASSPDX imm8 xmm k +// Construct and append a VFPCLASSPDX instruction to the active function. +// Operates on the global context. +func VFPCLASSPDX(ops ...operand.Op) { ctx.VFPCLASSPDX(ops...) } + +// VFPCLASSPDX_BCST: Test Class of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFPCLASSPDX.BCST imm8 m64 k k +// VFPCLASSPDX.BCST imm8 m64 k +// Construct and append a VFPCLASSPDX.BCST instruction to the active function. +func (c *Context) VFPCLASSPDX_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFPCLASSPDX_BCST(ops...)) +} + +// VFPCLASSPDX_BCST: Test Class of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFPCLASSPDX.BCST imm8 m64 k k +// VFPCLASSPDX.BCST imm8 m64 k +// Construct and append a VFPCLASSPDX.BCST instruction to the active function. +// Operates on the global context. +func VFPCLASSPDX_BCST(ops ...operand.Op) { ctx.VFPCLASSPDX_BCST(ops...) } + +// VFPCLASSPDY: Test Class of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFPCLASSPDY imm8 m256 k k +// VFPCLASSPDY imm8 m256 k +// VFPCLASSPDY imm8 ymm k k +// VFPCLASSPDY imm8 ymm k +// Construct and append a VFPCLASSPDY instruction to the active function. +func (c *Context) VFPCLASSPDY(ops ...operand.Op) { + c.addinstruction(x86.VFPCLASSPDY(ops...)) +} + +// VFPCLASSPDY: Test Class of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFPCLASSPDY imm8 m256 k k +// VFPCLASSPDY imm8 m256 k +// VFPCLASSPDY imm8 ymm k k +// VFPCLASSPDY imm8 ymm k +// Construct and append a VFPCLASSPDY instruction to the active function. +// Operates on the global context. +func VFPCLASSPDY(ops ...operand.Op) { ctx.VFPCLASSPDY(ops...) } + +// VFPCLASSPDY_BCST: Test Class of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFPCLASSPDY.BCST imm8 m64 k k +// VFPCLASSPDY.BCST imm8 m64 k +// Construct and append a VFPCLASSPDY.BCST instruction to the active function. +func (c *Context) VFPCLASSPDY_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFPCLASSPDY_BCST(ops...)) +} + +// VFPCLASSPDY_BCST: Test Class of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFPCLASSPDY.BCST imm8 m64 k k +// VFPCLASSPDY.BCST imm8 m64 k +// Construct and append a VFPCLASSPDY.BCST instruction to the active function. +// Operates on the global context. +func VFPCLASSPDY_BCST(ops ...operand.Op) { ctx.VFPCLASSPDY_BCST(ops...) } + +// VFPCLASSPDZ: Test Class of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFPCLASSPDZ imm8 m512 k k +// VFPCLASSPDZ imm8 m512 k +// VFPCLASSPDZ imm8 zmm k k +// VFPCLASSPDZ imm8 zmm k +// Construct and append a VFPCLASSPDZ instruction to the active function. +func (c *Context) VFPCLASSPDZ(ops ...operand.Op) { + c.addinstruction(x86.VFPCLASSPDZ(ops...)) +} + +// VFPCLASSPDZ: Test Class of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFPCLASSPDZ imm8 m512 k k +// VFPCLASSPDZ imm8 m512 k +// VFPCLASSPDZ imm8 zmm k k +// VFPCLASSPDZ imm8 zmm k +// Construct and append a VFPCLASSPDZ instruction to the active function. +// Operates on the global context. +func VFPCLASSPDZ(ops ...operand.Op) { ctx.VFPCLASSPDZ(ops...) } + +// VFPCLASSPDZ_BCST: Test Class of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFPCLASSPDZ.BCST imm8 m64 k k +// VFPCLASSPDZ.BCST imm8 m64 k +// Construct and append a VFPCLASSPDZ.BCST instruction to the active function. +func (c *Context) VFPCLASSPDZ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFPCLASSPDZ_BCST(ops...)) +} + +// VFPCLASSPDZ_BCST: Test Class of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFPCLASSPDZ.BCST imm8 m64 k k +// VFPCLASSPDZ.BCST imm8 m64 k +// Construct and append a VFPCLASSPDZ.BCST instruction to the active function. +// Operates on the global context. +func VFPCLASSPDZ_BCST(ops ...operand.Op) { ctx.VFPCLASSPDZ_BCST(ops...) } + +// VFPCLASSPSX: Test Class of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFPCLASSPSX imm8 m128 k k +// VFPCLASSPSX imm8 m128 k +// VFPCLASSPSX imm8 xmm k k +// VFPCLASSPSX imm8 xmm k +// Construct and append a VFPCLASSPSX instruction to the active function. +func (c *Context) VFPCLASSPSX(ops ...operand.Op) { + c.addinstruction(x86.VFPCLASSPSX(ops...)) +} + +// VFPCLASSPSX: Test Class of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFPCLASSPSX imm8 m128 k k +// VFPCLASSPSX imm8 m128 k +// VFPCLASSPSX imm8 xmm k k +// VFPCLASSPSX imm8 xmm k +// Construct and append a VFPCLASSPSX instruction to the active function. +// Operates on the global context. +func VFPCLASSPSX(ops ...operand.Op) { ctx.VFPCLASSPSX(ops...) } + +// VFPCLASSPSX_BCST: Test Class of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFPCLASSPSX.BCST imm8 m32 k k +// VFPCLASSPSX.BCST imm8 m32 k +// Construct and append a VFPCLASSPSX.BCST instruction to the active function. +func (c *Context) VFPCLASSPSX_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFPCLASSPSX_BCST(ops...)) +} + +// VFPCLASSPSX_BCST: Test Class of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFPCLASSPSX.BCST imm8 m32 k k +// VFPCLASSPSX.BCST imm8 m32 k +// Construct and append a VFPCLASSPSX.BCST instruction to the active function. +// Operates on the global context. +func VFPCLASSPSX_BCST(ops ...operand.Op) { ctx.VFPCLASSPSX_BCST(ops...) } + +// VFPCLASSPSY: Test Class of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFPCLASSPSY imm8 m256 k k +// VFPCLASSPSY imm8 m256 k +// VFPCLASSPSY imm8 ymm k k +// VFPCLASSPSY imm8 ymm k +// Construct and append a VFPCLASSPSY instruction to the active function. +func (c *Context) VFPCLASSPSY(ops ...operand.Op) { + c.addinstruction(x86.VFPCLASSPSY(ops...)) +} + +// VFPCLASSPSY: Test Class of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFPCLASSPSY imm8 m256 k k +// VFPCLASSPSY imm8 m256 k +// VFPCLASSPSY imm8 ymm k k +// VFPCLASSPSY imm8 ymm k +// Construct and append a VFPCLASSPSY instruction to the active function. +// Operates on the global context. +func VFPCLASSPSY(ops ...operand.Op) { ctx.VFPCLASSPSY(ops...) } + +// VFPCLASSPSY_BCST: Test Class of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFPCLASSPSY.BCST imm8 m32 k k +// VFPCLASSPSY.BCST imm8 m32 k +// Construct and append a VFPCLASSPSY.BCST instruction to the active function. +func (c *Context) VFPCLASSPSY_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFPCLASSPSY_BCST(ops...)) +} + +// VFPCLASSPSY_BCST: Test Class of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFPCLASSPSY.BCST imm8 m32 k k +// VFPCLASSPSY.BCST imm8 m32 k +// Construct and append a VFPCLASSPSY.BCST instruction to the active function. +// Operates on the global context. +func VFPCLASSPSY_BCST(ops ...operand.Op) { ctx.VFPCLASSPSY_BCST(ops...) } + +// VFPCLASSPSZ: Test Class of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFPCLASSPSZ imm8 m512 k k +// VFPCLASSPSZ imm8 m512 k +// VFPCLASSPSZ imm8 zmm k k +// VFPCLASSPSZ imm8 zmm k +// Construct and append a VFPCLASSPSZ instruction to the active function. +func (c *Context) VFPCLASSPSZ(ops ...operand.Op) { + c.addinstruction(x86.VFPCLASSPSZ(ops...)) +} + +// VFPCLASSPSZ: Test Class of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFPCLASSPSZ imm8 m512 k k +// VFPCLASSPSZ imm8 m512 k +// VFPCLASSPSZ imm8 zmm k k +// VFPCLASSPSZ imm8 zmm k +// Construct and append a VFPCLASSPSZ instruction to the active function. +// Operates on the global context. +func VFPCLASSPSZ(ops ...operand.Op) { ctx.VFPCLASSPSZ(ops...) } + +// VFPCLASSPSZ_BCST: Test Class of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFPCLASSPSZ.BCST imm8 m32 k k +// VFPCLASSPSZ.BCST imm8 m32 k +// Construct and append a VFPCLASSPSZ.BCST instruction to the active function. +func (c *Context) VFPCLASSPSZ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VFPCLASSPSZ_BCST(ops...)) +} + +// VFPCLASSPSZ_BCST: Test Class of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFPCLASSPSZ.BCST imm8 m32 k k +// VFPCLASSPSZ.BCST imm8 m32 k +// Construct and append a VFPCLASSPSZ.BCST instruction to the active function. +// Operates on the global context. +func VFPCLASSPSZ_BCST(ops ...operand.Op) { ctx.VFPCLASSPSZ_BCST(ops...) } + +// VFPCLASSSD: Test Class of Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// VFPCLASSSD imm8 m64 k k +// VFPCLASSSD imm8 m64 k +// VFPCLASSSD imm8 xmm k k +// VFPCLASSSD imm8 xmm k +// Construct and append a VFPCLASSSD instruction to the active function. +func (c *Context) VFPCLASSSD(ops ...operand.Op) { + c.addinstruction(x86.VFPCLASSSD(ops...)) +} + +// VFPCLASSSD: Test Class of Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// VFPCLASSSD imm8 m64 k k +// VFPCLASSSD imm8 m64 k +// VFPCLASSSD imm8 xmm k k +// VFPCLASSSD imm8 xmm k +// Construct and append a VFPCLASSSD instruction to the active function. +// Operates on the global context. +func VFPCLASSSD(ops ...operand.Op) { ctx.VFPCLASSSD(ops...) } + +// VFPCLASSSS: Test Class of Scalar Single-Precision Floating-Point Value. +// +// Forms: +// +// VFPCLASSSS imm8 m32 k k +// VFPCLASSSS imm8 m32 k +// VFPCLASSSS imm8 xmm k k +// VFPCLASSSS imm8 xmm k +// Construct and append a VFPCLASSSS instruction to the active function. +func (c *Context) VFPCLASSSS(ops ...operand.Op) { + c.addinstruction(x86.VFPCLASSSS(ops...)) +} + +// VFPCLASSSS: Test Class of Scalar Single-Precision Floating-Point Value. +// +// Forms: +// +// VFPCLASSSS imm8 m32 k k +// VFPCLASSSS imm8 m32 k +// VFPCLASSSS imm8 xmm k k +// VFPCLASSSS imm8 xmm k +// Construct and append a VFPCLASSSS instruction to the active function. +// Operates on the global context. +func VFPCLASSSS(ops ...operand.Op) { ctx.VFPCLASSSS(ops...) } + +// VGATHERDPD: Gather Packed Double-Precision Floating-Point Values Using Signed Doubleword Indices. +// +// Forms: +// +// VGATHERDPD xmm vm32x xmm +// VGATHERDPD ymm vm32x ymm +// VGATHERDPD vm32x k xmm +// VGATHERDPD vm32x k ymm +// VGATHERDPD vm32y k zmm +// Construct and append a VGATHERDPD instruction to the active function. +func (c *Context) VGATHERDPD(vxy, kv, xyz operand.Op) { + c.addinstruction(x86.VGATHERDPD(vxy, kv, xyz)) +} + +// VGATHERDPD: Gather Packed Double-Precision Floating-Point Values Using Signed Doubleword Indices. +// +// Forms: +// +// VGATHERDPD xmm vm32x xmm +// VGATHERDPD ymm vm32x ymm +// VGATHERDPD vm32x k xmm +// VGATHERDPD vm32x k ymm +// VGATHERDPD vm32y k zmm +// Construct and append a VGATHERDPD instruction to the active function. +// Operates on the global context. +func VGATHERDPD(vxy, kv, xyz operand.Op) { ctx.VGATHERDPD(vxy, kv, xyz) } + +// VGATHERDPS: Gather Packed Single-Precision Floating-Point Values Using Signed Doubleword Indices. +// +// Forms: +// +// VGATHERDPS xmm vm32x xmm +// VGATHERDPS ymm vm32y ymm +// VGATHERDPS vm32x k xmm +// VGATHERDPS vm32y k ymm +// VGATHERDPS vm32z k zmm +// Construct and append a VGATHERDPS instruction to the active function. +func (c *Context) VGATHERDPS(vxy, kv, xyz operand.Op) { + c.addinstruction(x86.VGATHERDPS(vxy, kv, xyz)) +} + +// VGATHERDPS: Gather Packed Single-Precision Floating-Point Values Using Signed Doubleword Indices. +// +// Forms: +// +// VGATHERDPS xmm vm32x xmm +// VGATHERDPS ymm vm32y ymm +// VGATHERDPS vm32x k xmm +// VGATHERDPS vm32y k ymm +// VGATHERDPS vm32z k zmm +// Construct and append a VGATHERDPS instruction to the active function. +// Operates on the global context. +func VGATHERDPS(vxy, kv, xyz operand.Op) { ctx.VGATHERDPS(vxy, kv, xyz) } + +// VGATHERQPD: Gather Packed Double-Precision Floating-Point Values Using Signed Quadword Indices. +// +// Forms: +// +// VGATHERQPD xmm vm64x xmm +// VGATHERQPD ymm vm64y ymm +// VGATHERQPD vm64x k xmm +// VGATHERQPD vm64y k ymm +// VGATHERQPD vm64z k zmm +// Construct and append a VGATHERQPD instruction to the active function. +func (c *Context) VGATHERQPD(vxy, kv, xyz operand.Op) { + c.addinstruction(x86.VGATHERQPD(vxy, kv, xyz)) +} + +// VGATHERQPD: Gather Packed Double-Precision Floating-Point Values Using Signed Quadword Indices. +// +// Forms: +// +// VGATHERQPD xmm vm64x xmm +// VGATHERQPD ymm vm64y ymm +// VGATHERQPD vm64x k xmm +// VGATHERQPD vm64y k ymm +// VGATHERQPD vm64z k zmm +// Construct and append a VGATHERQPD instruction to the active function. +// Operates on the global context. +func VGATHERQPD(vxy, kv, xyz operand.Op) { ctx.VGATHERQPD(vxy, kv, xyz) } + +// VGATHERQPS: Gather Packed Single-Precision Floating-Point Values Using Signed Quadword Indices. +// +// Forms: +// +// VGATHERQPS xmm vm64x xmm +// VGATHERQPS xmm vm64y xmm +// VGATHERQPS vm64x k xmm +// VGATHERQPS vm64y k xmm +// VGATHERQPS vm64z k ymm +// Construct and append a VGATHERQPS instruction to the active function. +func (c *Context) VGATHERQPS(vx, kv, xy operand.Op) { + c.addinstruction(x86.VGATHERQPS(vx, kv, xy)) +} + +// VGATHERQPS: Gather Packed Single-Precision Floating-Point Values Using Signed Quadword Indices. +// +// Forms: +// +// VGATHERQPS xmm vm64x xmm +// VGATHERQPS xmm vm64y xmm +// VGATHERQPS vm64x k xmm +// VGATHERQPS vm64y k xmm +// VGATHERQPS vm64z k ymm +// Construct and append a VGATHERQPS instruction to the active function. +// Operates on the global context. +func VGATHERQPS(vx, kv, xy operand.Op) { ctx.VGATHERQPS(vx, kv, xy) } + +// VGETEXPPD: Extract Exponents of Packed Double-Precision Floating-Point Values as Double-Precision Floating-Point Values. +// +// Forms: +// +// VGETEXPPD m128 k xmm +// VGETEXPPD m128 xmm +// VGETEXPPD m256 k ymm +// VGETEXPPD m256 ymm +// VGETEXPPD xmm k xmm +// VGETEXPPD xmm xmm +// VGETEXPPD ymm k ymm +// VGETEXPPD ymm ymm +// VGETEXPPD m512 k zmm +// VGETEXPPD m512 zmm +// VGETEXPPD zmm k zmm +// VGETEXPPD zmm zmm +// Construct and append a VGETEXPPD instruction to the active function. +func (c *Context) VGETEXPPD(ops ...operand.Op) { + c.addinstruction(x86.VGETEXPPD(ops...)) +} + +// VGETEXPPD: Extract Exponents of Packed Double-Precision Floating-Point Values as Double-Precision Floating-Point Values. +// +// Forms: +// +// VGETEXPPD m128 k xmm +// VGETEXPPD m128 xmm +// VGETEXPPD m256 k ymm +// VGETEXPPD m256 ymm +// VGETEXPPD xmm k xmm +// VGETEXPPD xmm xmm +// VGETEXPPD ymm k ymm +// VGETEXPPD ymm ymm +// VGETEXPPD m512 k zmm +// VGETEXPPD m512 zmm +// VGETEXPPD zmm k zmm +// VGETEXPPD zmm zmm +// Construct and append a VGETEXPPD instruction to the active function. +// Operates on the global context. +func VGETEXPPD(ops ...operand.Op) { ctx.VGETEXPPD(ops...) } + +// VGETEXPPD_BCST: Extract Exponents of Packed Double-Precision Floating-Point Values as Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VGETEXPPD.BCST m64 k xmm +// VGETEXPPD.BCST m64 k ymm +// VGETEXPPD.BCST m64 xmm +// VGETEXPPD.BCST m64 ymm +// VGETEXPPD.BCST m64 k zmm +// VGETEXPPD.BCST m64 zmm +// Construct and append a VGETEXPPD.BCST instruction to the active function. +func (c *Context) VGETEXPPD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VGETEXPPD_BCST(ops...)) +} + +// VGETEXPPD_BCST: Extract Exponents of Packed Double-Precision Floating-Point Values as Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VGETEXPPD.BCST m64 k xmm +// VGETEXPPD.BCST m64 k ymm +// VGETEXPPD.BCST m64 xmm +// VGETEXPPD.BCST m64 ymm +// VGETEXPPD.BCST m64 k zmm +// VGETEXPPD.BCST m64 zmm +// Construct and append a VGETEXPPD.BCST instruction to the active function. +// Operates on the global context. +func VGETEXPPD_BCST(ops ...operand.Op) { ctx.VGETEXPPD_BCST(ops...) } + +// VGETEXPPD_BCST_Z: Extract Exponents of Packed Double-Precision Floating-Point Values as Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VGETEXPPD.BCST.Z m64 k xmm +// VGETEXPPD.BCST.Z m64 k ymm +// VGETEXPPD.BCST.Z m64 k zmm +// Construct and append a VGETEXPPD.BCST.Z instruction to the active function. +func (c *Context) VGETEXPPD_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VGETEXPPD_BCST_Z(m, k, xyz)) +} + +// VGETEXPPD_BCST_Z: Extract Exponents of Packed Double-Precision Floating-Point Values as Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VGETEXPPD.BCST.Z m64 k xmm +// VGETEXPPD.BCST.Z m64 k ymm +// VGETEXPPD.BCST.Z m64 k zmm +// Construct and append a VGETEXPPD.BCST.Z instruction to the active function. +// Operates on the global context. +func VGETEXPPD_BCST_Z(m, k, xyz operand.Op) { ctx.VGETEXPPD_BCST_Z(m, k, xyz) } + +// VGETEXPPD_SAE: Extract Exponents of Packed Double-Precision Floating-Point Values as Double-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VGETEXPPD.SAE zmm k zmm +// VGETEXPPD.SAE zmm zmm +// Construct and append a VGETEXPPD.SAE instruction to the active function. +func (c *Context) VGETEXPPD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VGETEXPPD_SAE(ops...)) +} + +// VGETEXPPD_SAE: Extract Exponents of Packed Double-Precision Floating-Point Values as Double-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VGETEXPPD.SAE zmm k zmm +// VGETEXPPD.SAE zmm zmm +// Construct and append a VGETEXPPD.SAE instruction to the active function. +// Operates on the global context. +func VGETEXPPD_SAE(ops ...operand.Op) { ctx.VGETEXPPD_SAE(ops...) } + +// VGETEXPPD_SAE_Z: Extract Exponents of Packed Double-Precision Floating-Point Values as Double-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VGETEXPPD.SAE.Z zmm k zmm +// Construct and append a VGETEXPPD.SAE.Z instruction to the active function. +func (c *Context) VGETEXPPD_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VGETEXPPD_SAE_Z(z, k, z1)) +} + +// VGETEXPPD_SAE_Z: Extract Exponents of Packed Double-Precision Floating-Point Values as Double-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VGETEXPPD.SAE.Z zmm k zmm +// Construct and append a VGETEXPPD.SAE.Z instruction to the active function. +// Operates on the global context. +func VGETEXPPD_SAE_Z(z, k, z1 operand.Op) { ctx.VGETEXPPD_SAE_Z(z, k, z1) } + +// VGETEXPPD_Z: Extract Exponents of Packed Double-Precision Floating-Point Values as Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VGETEXPPD.Z m128 k xmm +// VGETEXPPD.Z m256 k ymm +// VGETEXPPD.Z xmm k xmm +// VGETEXPPD.Z ymm k ymm +// VGETEXPPD.Z m512 k zmm +// VGETEXPPD.Z zmm k zmm +// Construct and append a VGETEXPPD.Z instruction to the active function. +func (c *Context) VGETEXPPD_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VGETEXPPD_Z(mxyz, k, xyz)) +} + +// VGETEXPPD_Z: Extract Exponents of Packed Double-Precision Floating-Point Values as Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VGETEXPPD.Z m128 k xmm +// VGETEXPPD.Z m256 k ymm +// VGETEXPPD.Z xmm k xmm +// VGETEXPPD.Z ymm k ymm +// VGETEXPPD.Z m512 k zmm +// VGETEXPPD.Z zmm k zmm +// Construct and append a VGETEXPPD.Z instruction to the active function. +// Operates on the global context. +func VGETEXPPD_Z(mxyz, k, xyz operand.Op) { ctx.VGETEXPPD_Z(mxyz, k, xyz) } + +// VGETEXPPS: Extract Exponents of Packed Single-Precision Floating-Point Values as Single-Precision Floating-Point Values. +// +// Forms: +// +// VGETEXPPS m128 k xmm +// VGETEXPPS m128 xmm +// VGETEXPPS m256 k ymm +// VGETEXPPS m256 ymm +// VGETEXPPS xmm k xmm +// VGETEXPPS xmm xmm +// VGETEXPPS ymm k ymm +// VGETEXPPS ymm ymm +// VGETEXPPS m512 k zmm +// VGETEXPPS m512 zmm +// VGETEXPPS zmm k zmm +// VGETEXPPS zmm zmm +// Construct and append a VGETEXPPS instruction to the active function. +func (c *Context) VGETEXPPS(ops ...operand.Op) { + c.addinstruction(x86.VGETEXPPS(ops...)) +} + +// VGETEXPPS: Extract Exponents of Packed Single-Precision Floating-Point Values as Single-Precision Floating-Point Values. +// +// Forms: +// +// VGETEXPPS m128 k xmm +// VGETEXPPS m128 xmm +// VGETEXPPS m256 k ymm +// VGETEXPPS m256 ymm +// VGETEXPPS xmm k xmm +// VGETEXPPS xmm xmm +// VGETEXPPS ymm k ymm +// VGETEXPPS ymm ymm +// VGETEXPPS m512 k zmm +// VGETEXPPS m512 zmm +// VGETEXPPS zmm k zmm +// VGETEXPPS zmm zmm +// Construct and append a VGETEXPPS instruction to the active function. +// Operates on the global context. +func VGETEXPPS(ops ...operand.Op) { ctx.VGETEXPPS(ops...) } + +// VGETEXPPS_BCST: Extract Exponents of Packed Single-Precision Floating-Point Values as Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VGETEXPPS.BCST m32 k xmm +// VGETEXPPS.BCST m32 k ymm +// VGETEXPPS.BCST m32 xmm +// VGETEXPPS.BCST m32 ymm +// VGETEXPPS.BCST m32 k zmm +// VGETEXPPS.BCST m32 zmm +// Construct and append a VGETEXPPS.BCST instruction to the active function. +func (c *Context) VGETEXPPS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VGETEXPPS_BCST(ops...)) +} + +// VGETEXPPS_BCST: Extract Exponents of Packed Single-Precision Floating-Point Values as Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VGETEXPPS.BCST m32 k xmm +// VGETEXPPS.BCST m32 k ymm +// VGETEXPPS.BCST m32 xmm +// VGETEXPPS.BCST m32 ymm +// VGETEXPPS.BCST m32 k zmm +// VGETEXPPS.BCST m32 zmm +// Construct and append a VGETEXPPS.BCST instruction to the active function. +// Operates on the global context. +func VGETEXPPS_BCST(ops ...operand.Op) { ctx.VGETEXPPS_BCST(ops...) } + +// VGETEXPPS_BCST_Z: Extract Exponents of Packed Single-Precision Floating-Point Values as Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VGETEXPPS.BCST.Z m32 k xmm +// VGETEXPPS.BCST.Z m32 k ymm +// VGETEXPPS.BCST.Z m32 k zmm +// Construct and append a VGETEXPPS.BCST.Z instruction to the active function. +func (c *Context) VGETEXPPS_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VGETEXPPS_BCST_Z(m, k, xyz)) +} + +// VGETEXPPS_BCST_Z: Extract Exponents of Packed Single-Precision Floating-Point Values as Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VGETEXPPS.BCST.Z m32 k xmm +// VGETEXPPS.BCST.Z m32 k ymm +// VGETEXPPS.BCST.Z m32 k zmm +// Construct and append a VGETEXPPS.BCST.Z instruction to the active function. +// Operates on the global context. +func VGETEXPPS_BCST_Z(m, k, xyz operand.Op) { ctx.VGETEXPPS_BCST_Z(m, k, xyz) } + +// VGETEXPPS_SAE: Extract Exponents of Packed Single-Precision Floating-Point Values as Single-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VGETEXPPS.SAE zmm k zmm +// VGETEXPPS.SAE zmm zmm +// Construct and append a VGETEXPPS.SAE instruction to the active function. +func (c *Context) VGETEXPPS_SAE(ops ...operand.Op) { + c.addinstruction(x86.VGETEXPPS_SAE(ops...)) +} + +// VGETEXPPS_SAE: Extract Exponents of Packed Single-Precision Floating-Point Values as Single-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VGETEXPPS.SAE zmm k zmm +// VGETEXPPS.SAE zmm zmm +// Construct and append a VGETEXPPS.SAE instruction to the active function. +// Operates on the global context. +func VGETEXPPS_SAE(ops ...operand.Op) { ctx.VGETEXPPS_SAE(ops...) } + +// VGETEXPPS_SAE_Z: Extract Exponents of Packed Single-Precision Floating-Point Values as Single-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VGETEXPPS.SAE.Z zmm k zmm +// Construct and append a VGETEXPPS.SAE.Z instruction to the active function. +func (c *Context) VGETEXPPS_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VGETEXPPS_SAE_Z(z, k, z1)) +} + +// VGETEXPPS_SAE_Z: Extract Exponents of Packed Single-Precision Floating-Point Values as Single-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VGETEXPPS.SAE.Z zmm k zmm +// Construct and append a VGETEXPPS.SAE.Z instruction to the active function. +// Operates on the global context. +func VGETEXPPS_SAE_Z(z, k, z1 operand.Op) { ctx.VGETEXPPS_SAE_Z(z, k, z1) } + +// VGETEXPPS_Z: Extract Exponents of Packed Single-Precision Floating-Point Values as Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VGETEXPPS.Z m128 k xmm +// VGETEXPPS.Z m256 k ymm +// VGETEXPPS.Z xmm k xmm +// VGETEXPPS.Z ymm k ymm +// VGETEXPPS.Z m512 k zmm +// VGETEXPPS.Z zmm k zmm +// Construct and append a VGETEXPPS.Z instruction to the active function. +func (c *Context) VGETEXPPS_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VGETEXPPS_Z(mxyz, k, xyz)) +} + +// VGETEXPPS_Z: Extract Exponents of Packed Single-Precision Floating-Point Values as Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VGETEXPPS.Z m128 k xmm +// VGETEXPPS.Z m256 k ymm +// VGETEXPPS.Z xmm k xmm +// VGETEXPPS.Z ymm k ymm +// VGETEXPPS.Z m512 k zmm +// VGETEXPPS.Z zmm k zmm +// Construct and append a VGETEXPPS.Z instruction to the active function. +// Operates on the global context. +func VGETEXPPS_Z(mxyz, k, xyz operand.Op) { ctx.VGETEXPPS_Z(mxyz, k, xyz) } + +// VGETEXPSD: Extract Exponent of Scalar Double-Precision Floating-Point Value as Double-Precision Floating-Point Value. +// +// Forms: +// +// VGETEXPSD m64 xmm k xmm +// VGETEXPSD m64 xmm xmm +// VGETEXPSD xmm xmm k xmm +// VGETEXPSD xmm xmm xmm +// Construct and append a VGETEXPSD instruction to the active function. +func (c *Context) VGETEXPSD(ops ...operand.Op) { + c.addinstruction(x86.VGETEXPSD(ops...)) +} + +// VGETEXPSD: Extract Exponent of Scalar Double-Precision Floating-Point Value as Double-Precision Floating-Point Value. +// +// Forms: +// +// VGETEXPSD m64 xmm k xmm +// VGETEXPSD m64 xmm xmm +// VGETEXPSD xmm xmm k xmm +// VGETEXPSD xmm xmm xmm +// Construct and append a VGETEXPSD instruction to the active function. +// Operates on the global context. +func VGETEXPSD(ops ...operand.Op) { ctx.VGETEXPSD(ops...) } + +// VGETEXPSD_SAE: Extract Exponent of Scalar Double-Precision Floating-Point Value as Double-Precision Floating-Point Value (Suppress All Exceptions). +// +// Forms: +// +// VGETEXPSD.SAE xmm xmm k xmm +// VGETEXPSD.SAE xmm xmm xmm +// Construct and append a VGETEXPSD.SAE instruction to the active function. +func (c *Context) VGETEXPSD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VGETEXPSD_SAE(ops...)) +} + +// VGETEXPSD_SAE: Extract Exponent of Scalar Double-Precision Floating-Point Value as Double-Precision Floating-Point Value (Suppress All Exceptions). +// +// Forms: +// +// VGETEXPSD.SAE xmm xmm k xmm +// VGETEXPSD.SAE xmm xmm xmm +// Construct and append a VGETEXPSD.SAE instruction to the active function. +// Operates on the global context. +func VGETEXPSD_SAE(ops ...operand.Op) { ctx.VGETEXPSD_SAE(ops...) } + +// VGETEXPSD_SAE_Z: Extract Exponent of Scalar Double-Precision Floating-Point Value as Double-Precision Floating-Point Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VGETEXPSD.SAE.Z xmm xmm k xmm +// Construct and append a VGETEXPSD.SAE.Z instruction to the active function. +func (c *Context) VGETEXPSD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VGETEXPSD_SAE_Z(x, x1, k, x2)) +} + +// VGETEXPSD_SAE_Z: Extract Exponent of Scalar Double-Precision Floating-Point Value as Double-Precision Floating-Point Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VGETEXPSD.SAE.Z xmm xmm k xmm +// Construct and append a VGETEXPSD.SAE.Z instruction to the active function. +// Operates on the global context. +func VGETEXPSD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VGETEXPSD_SAE_Z(x, x1, k, x2) } + +// VGETEXPSD_Z: Extract Exponent of Scalar Double-Precision Floating-Point Value as Double-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VGETEXPSD.Z m64 xmm k xmm +// VGETEXPSD.Z xmm xmm k xmm +// Construct and append a VGETEXPSD.Z instruction to the active function. +func (c *Context) VGETEXPSD_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VGETEXPSD_Z(mx, x, k, x1)) +} + +// VGETEXPSD_Z: Extract Exponent of Scalar Double-Precision Floating-Point Value as Double-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VGETEXPSD.Z m64 xmm k xmm +// VGETEXPSD.Z xmm xmm k xmm +// Construct and append a VGETEXPSD.Z instruction to the active function. +// Operates on the global context. +func VGETEXPSD_Z(mx, x, k, x1 operand.Op) { ctx.VGETEXPSD_Z(mx, x, k, x1) } + +// VGETEXPSS: Extract Exponent of Scalar Single-Precision Floating-Point Value as Single-Precision Floating-Point Value. +// +// Forms: +// +// VGETEXPSS m32 xmm k xmm +// VGETEXPSS m32 xmm xmm +// VGETEXPSS xmm xmm k xmm +// VGETEXPSS xmm xmm xmm +// Construct and append a VGETEXPSS instruction to the active function. +func (c *Context) VGETEXPSS(ops ...operand.Op) { + c.addinstruction(x86.VGETEXPSS(ops...)) +} + +// VGETEXPSS: Extract Exponent of Scalar Single-Precision Floating-Point Value as Single-Precision Floating-Point Value. +// +// Forms: +// +// VGETEXPSS m32 xmm k xmm +// VGETEXPSS m32 xmm xmm +// VGETEXPSS xmm xmm k xmm +// VGETEXPSS xmm xmm xmm +// Construct and append a VGETEXPSS instruction to the active function. +// Operates on the global context. +func VGETEXPSS(ops ...operand.Op) { ctx.VGETEXPSS(ops...) } + +// VGETEXPSS_SAE: Extract Exponent of Scalar Single-Precision Floating-Point Value as Single-Precision Floating-Point Value (Suppress All Exceptions). +// +// Forms: +// +// VGETEXPSS.SAE xmm xmm k xmm +// VGETEXPSS.SAE xmm xmm xmm +// Construct and append a VGETEXPSS.SAE instruction to the active function. +func (c *Context) VGETEXPSS_SAE(ops ...operand.Op) { + c.addinstruction(x86.VGETEXPSS_SAE(ops...)) +} + +// VGETEXPSS_SAE: Extract Exponent of Scalar Single-Precision Floating-Point Value as Single-Precision Floating-Point Value (Suppress All Exceptions). +// +// Forms: +// +// VGETEXPSS.SAE xmm xmm k xmm +// VGETEXPSS.SAE xmm xmm xmm +// Construct and append a VGETEXPSS.SAE instruction to the active function. +// Operates on the global context. +func VGETEXPSS_SAE(ops ...operand.Op) { ctx.VGETEXPSS_SAE(ops...) } + +// VGETEXPSS_SAE_Z: Extract Exponent of Scalar Single-Precision Floating-Point Value as Single-Precision Floating-Point Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VGETEXPSS.SAE.Z xmm xmm k xmm +// Construct and append a VGETEXPSS.SAE.Z instruction to the active function. +func (c *Context) VGETEXPSS_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VGETEXPSS_SAE_Z(x, x1, k, x2)) +} + +// VGETEXPSS_SAE_Z: Extract Exponent of Scalar Single-Precision Floating-Point Value as Single-Precision Floating-Point Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VGETEXPSS.SAE.Z xmm xmm k xmm +// Construct and append a VGETEXPSS.SAE.Z instruction to the active function. +// Operates on the global context. +func VGETEXPSS_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VGETEXPSS_SAE_Z(x, x1, k, x2) } + +// VGETEXPSS_Z: Extract Exponent of Scalar Single-Precision Floating-Point Value as Single-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VGETEXPSS.Z m32 xmm k xmm +// VGETEXPSS.Z xmm xmm k xmm +// Construct and append a VGETEXPSS.Z instruction to the active function. +func (c *Context) VGETEXPSS_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VGETEXPSS_Z(mx, x, k, x1)) +} + +// VGETEXPSS_Z: Extract Exponent of Scalar Single-Precision Floating-Point Value as Single-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VGETEXPSS.Z m32 xmm k xmm +// VGETEXPSS.Z xmm xmm k xmm +// Construct and append a VGETEXPSS.Z instruction to the active function. +// Operates on the global context. +func VGETEXPSS_Z(mx, x, k, x1 operand.Op) { ctx.VGETEXPSS_Z(mx, x, k, x1) } + +// VGETMANTPD: Extract Normalized Mantissas from Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VGETMANTPD imm8 m128 k xmm +// VGETMANTPD imm8 m128 xmm +// VGETMANTPD imm8 m256 k ymm +// VGETMANTPD imm8 m256 ymm +// VGETMANTPD imm8 xmm k xmm +// VGETMANTPD imm8 xmm xmm +// VGETMANTPD imm8 ymm k ymm +// VGETMANTPD imm8 ymm ymm +// VGETMANTPD imm8 m512 k zmm +// VGETMANTPD imm8 m512 zmm +// VGETMANTPD imm8 zmm k zmm +// VGETMANTPD imm8 zmm zmm +// Construct and append a VGETMANTPD instruction to the active function. +func (c *Context) VGETMANTPD(ops ...operand.Op) { + c.addinstruction(x86.VGETMANTPD(ops...)) +} + +// VGETMANTPD: Extract Normalized Mantissas from Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VGETMANTPD imm8 m128 k xmm +// VGETMANTPD imm8 m128 xmm +// VGETMANTPD imm8 m256 k ymm +// VGETMANTPD imm8 m256 ymm +// VGETMANTPD imm8 xmm k xmm +// VGETMANTPD imm8 xmm xmm +// VGETMANTPD imm8 ymm k ymm +// VGETMANTPD imm8 ymm ymm +// VGETMANTPD imm8 m512 k zmm +// VGETMANTPD imm8 m512 zmm +// VGETMANTPD imm8 zmm k zmm +// VGETMANTPD imm8 zmm zmm +// Construct and append a VGETMANTPD instruction to the active function. +// Operates on the global context. +func VGETMANTPD(ops ...operand.Op) { ctx.VGETMANTPD(ops...) } + +// VGETMANTPD_BCST: Extract Normalized Mantissas from Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VGETMANTPD.BCST imm8 m64 k xmm +// VGETMANTPD.BCST imm8 m64 k ymm +// VGETMANTPD.BCST imm8 m64 xmm +// VGETMANTPD.BCST imm8 m64 ymm +// VGETMANTPD.BCST imm8 m64 k zmm +// VGETMANTPD.BCST imm8 m64 zmm +// Construct and append a VGETMANTPD.BCST instruction to the active function. +func (c *Context) VGETMANTPD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VGETMANTPD_BCST(ops...)) +} + +// VGETMANTPD_BCST: Extract Normalized Mantissas from Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VGETMANTPD.BCST imm8 m64 k xmm +// VGETMANTPD.BCST imm8 m64 k ymm +// VGETMANTPD.BCST imm8 m64 xmm +// VGETMANTPD.BCST imm8 m64 ymm +// VGETMANTPD.BCST imm8 m64 k zmm +// VGETMANTPD.BCST imm8 m64 zmm +// Construct and append a VGETMANTPD.BCST instruction to the active function. +// Operates on the global context. +func VGETMANTPD_BCST(ops ...operand.Op) { ctx.VGETMANTPD_BCST(ops...) } + +// VGETMANTPD_BCST_Z: Extract Normalized Mantissas from Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VGETMANTPD.BCST.Z imm8 m64 k xmm +// VGETMANTPD.BCST.Z imm8 m64 k ymm +// VGETMANTPD.BCST.Z imm8 m64 k zmm +// Construct and append a VGETMANTPD.BCST.Z instruction to the active function. +func (c *Context) VGETMANTPD_BCST_Z(i, m, k, xyz operand.Op) { + c.addinstruction(x86.VGETMANTPD_BCST_Z(i, m, k, xyz)) +} + +// VGETMANTPD_BCST_Z: Extract Normalized Mantissas from Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VGETMANTPD.BCST.Z imm8 m64 k xmm +// VGETMANTPD.BCST.Z imm8 m64 k ymm +// VGETMANTPD.BCST.Z imm8 m64 k zmm +// Construct and append a VGETMANTPD.BCST.Z instruction to the active function. +// Operates on the global context. +func VGETMANTPD_BCST_Z(i, m, k, xyz operand.Op) { ctx.VGETMANTPD_BCST_Z(i, m, k, xyz) } + +// VGETMANTPD_SAE: Extract Normalized Mantissas from Packed Double-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VGETMANTPD.SAE imm8 zmm k zmm +// VGETMANTPD.SAE imm8 zmm zmm +// Construct and append a VGETMANTPD.SAE instruction to the active function. +func (c *Context) VGETMANTPD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VGETMANTPD_SAE(ops...)) +} + +// VGETMANTPD_SAE: Extract Normalized Mantissas from Packed Double-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VGETMANTPD.SAE imm8 zmm k zmm +// VGETMANTPD.SAE imm8 zmm zmm +// Construct and append a VGETMANTPD.SAE instruction to the active function. +// Operates on the global context. +func VGETMANTPD_SAE(ops ...operand.Op) { ctx.VGETMANTPD_SAE(ops...) } + +// VGETMANTPD_SAE_Z: Extract Normalized Mantissas from Packed Double-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VGETMANTPD.SAE.Z imm8 zmm k zmm +// Construct and append a VGETMANTPD.SAE.Z instruction to the active function. +func (c *Context) VGETMANTPD_SAE_Z(i, z, k, z1 operand.Op) { + c.addinstruction(x86.VGETMANTPD_SAE_Z(i, z, k, z1)) +} + +// VGETMANTPD_SAE_Z: Extract Normalized Mantissas from Packed Double-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VGETMANTPD.SAE.Z imm8 zmm k zmm +// Construct and append a VGETMANTPD.SAE.Z instruction to the active function. +// Operates on the global context. +func VGETMANTPD_SAE_Z(i, z, k, z1 operand.Op) { ctx.VGETMANTPD_SAE_Z(i, z, k, z1) } + +// VGETMANTPD_Z: Extract Normalized Mantissas from Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VGETMANTPD.Z imm8 m128 k xmm +// VGETMANTPD.Z imm8 m256 k ymm +// VGETMANTPD.Z imm8 xmm k xmm +// VGETMANTPD.Z imm8 ymm k ymm +// VGETMANTPD.Z imm8 m512 k zmm +// VGETMANTPD.Z imm8 zmm k zmm +// Construct and append a VGETMANTPD.Z instruction to the active function. +func (c *Context) VGETMANTPD_Z(i, mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VGETMANTPD_Z(i, mxyz, k, xyz)) +} + +// VGETMANTPD_Z: Extract Normalized Mantissas from Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VGETMANTPD.Z imm8 m128 k xmm +// VGETMANTPD.Z imm8 m256 k ymm +// VGETMANTPD.Z imm8 xmm k xmm +// VGETMANTPD.Z imm8 ymm k ymm +// VGETMANTPD.Z imm8 m512 k zmm +// VGETMANTPD.Z imm8 zmm k zmm +// Construct and append a VGETMANTPD.Z instruction to the active function. +// Operates on the global context. +func VGETMANTPD_Z(i, mxyz, k, xyz operand.Op) { ctx.VGETMANTPD_Z(i, mxyz, k, xyz) } + +// VGETMANTPS: Extract Normalized Mantissas from Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VGETMANTPS imm8 m128 k xmm +// VGETMANTPS imm8 m128 xmm +// VGETMANTPS imm8 m256 k ymm +// VGETMANTPS imm8 m256 ymm +// VGETMANTPS imm8 xmm k xmm +// VGETMANTPS imm8 xmm xmm +// VGETMANTPS imm8 ymm k ymm +// VGETMANTPS imm8 ymm ymm +// VGETMANTPS imm8 m512 k zmm +// VGETMANTPS imm8 m512 zmm +// VGETMANTPS imm8 zmm k zmm +// VGETMANTPS imm8 zmm zmm +// Construct and append a VGETMANTPS instruction to the active function. +func (c *Context) VGETMANTPS(ops ...operand.Op) { + c.addinstruction(x86.VGETMANTPS(ops...)) +} + +// VGETMANTPS: Extract Normalized Mantissas from Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VGETMANTPS imm8 m128 k xmm +// VGETMANTPS imm8 m128 xmm +// VGETMANTPS imm8 m256 k ymm +// VGETMANTPS imm8 m256 ymm +// VGETMANTPS imm8 xmm k xmm +// VGETMANTPS imm8 xmm xmm +// VGETMANTPS imm8 ymm k ymm +// VGETMANTPS imm8 ymm ymm +// VGETMANTPS imm8 m512 k zmm +// VGETMANTPS imm8 m512 zmm +// VGETMANTPS imm8 zmm k zmm +// VGETMANTPS imm8 zmm zmm +// Construct and append a VGETMANTPS instruction to the active function. +// Operates on the global context. +func VGETMANTPS(ops ...operand.Op) { ctx.VGETMANTPS(ops...) } + +// VGETMANTPS_BCST: Extract Normalized Mantissas from Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VGETMANTPS.BCST imm8 m32 k xmm +// VGETMANTPS.BCST imm8 m32 k ymm +// VGETMANTPS.BCST imm8 m32 xmm +// VGETMANTPS.BCST imm8 m32 ymm +// VGETMANTPS.BCST imm8 m32 k zmm +// VGETMANTPS.BCST imm8 m32 zmm +// Construct and append a VGETMANTPS.BCST instruction to the active function. +func (c *Context) VGETMANTPS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VGETMANTPS_BCST(ops...)) +} + +// VGETMANTPS_BCST: Extract Normalized Mantissas from Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VGETMANTPS.BCST imm8 m32 k xmm +// VGETMANTPS.BCST imm8 m32 k ymm +// VGETMANTPS.BCST imm8 m32 xmm +// VGETMANTPS.BCST imm8 m32 ymm +// VGETMANTPS.BCST imm8 m32 k zmm +// VGETMANTPS.BCST imm8 m32 zmm +// Construct and append a VGETMANTPS.BCST instruction to the active function. +// Operates on the global context. +func VGETMANTPS_BCST(ops ...operand.Op) { ctx.VGETMANTPS_BCST(ops...) } + +// VGETMANTPS_BCST_Z: Extract Normalized Mantissas from Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VGETMANTPS.BCST.Z imm8 m32 k xmm +// VGETMANTPS.BCST.Z imm8 m32 k ymm +// VGETMANTPS.BCST.Z imm8 m32 k zmm +// Construct and append a VGETMANTPS.BCST.Z instruction to the active function. +func (c *Context) VGETMANTPS_BCST_Z(i, m, k, xyz operand.Op) { + c.addinstruction(x86.VGETMANTPS_BCST_Z(i, m, k, xyz)) +} + +// VGETMANTPS_BCST_Z: Extract Normalized Mantissas from Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VGETMANTPS.BCST.Z imm8 m32 k xmm +// VGETMANTPS.BCST.Z imm8 m32 k ymm +// VGETMANTPS.BCST.Z imm8 m32 k zmm +// Construct and append a VGETMANTPS.BCST.Z instruction to the active function. +// Operates on the global context. +func VGETMANTPS_BCST_Z(i, m, k, xyz operand.Op) { ctx.VGETMANTPS_BCST_Z(i, m, k, xyz) } + +// VGETMANTPS_SAE: Extract Normalized Mantissas from Packed Single-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VGETMANTPS.SAE imm8 zmm k zmm +// VGETMANTPS.SAE imm8 zmm zmm +// Construct and append a VGETMANTPS.SAE instruction to the active function. +func (c *Context) VGETMANTPS_SAE(ops ...operand.Op) { + c.addinstruction(x86.VGETMANTPS_SAE(ops...)) +} + +// VGETMANTPS_SAE: Extract Normalized Mantissas from Packed Single-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VGETMANTPS.SAE imm8 zmm k zmm +// VGETMANTPS.SAE imm8 zmm zmm +// Construct and append a VGETMANTPS.SAE instruction to the active function. +// Operates on the global context. +func VGETMANTPS_SAE(ops ...operand.Op) { ctx.VGETMANTPS_SAE(ops...) } + +// VGETMANTPS_SAE_Z: Extract Normalized Mantissas from Packed Single-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VGETMANTPS.SAE.Z imm8 zmm k zmm +// Construct and append a VGETMANTPS.SAE.Z instruction to the active function. +func (c *Context) VGETMANTPS_SAE_Z(i, z, k, z1 operand.Op) { + c.addinstruction(x86.VGETMANTPS_SAE_Z(i, z, k, z1)) +} + +// VGETMANTPS_SAE_Z: Extract Normalized Mantissas from Packed Single-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VGETMANTPS.SAE.Z imm8 zmm k zmm +// Construct and append a VGETMANTPS.SAE.Z instruction to the active function. +// Operates on the global context. +func VGETMANTPS_SAE_Z(i, z, k, z1 operand.Op) { ctx.VGETMANTPS_SAE_Z(i, z, k, z1) } + +// VGETMANTPS_Z: Extract Normalized Mantissas from Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VGETMANTPS.Z imm8 m128 k xmm +// VGETMANTPS.Z imm8 m256 k ymm +// VGETMANTPS.Z imm8 xmm k xmm +// VGETMANTPS.Z imm8 ymm k ymm +// VGETMANTPS.Z imm8 m512 k zmm +// VGETMANTPS.Z imm8 zmm k zmm +// Construct and append a VGETMANTPS.Z instruction to the active function. +func (c *Context) VGETMANTPS_Z(i, mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VGETMANTPS_Z(i, mxyz, k, xyz)) +} + +// VGETMANTPS_Z: Extract Normalized Mantissas from Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VGETMANTPS.Z imm8 m128 k xmm +// VGETMANTPS.Z imm8 m256 k ymm +// VGETMANTPS.Z imm8 xmm k xmm +// VGETMANTPS.Z imm8 ymm k ymm +// VGETMANTPS.Z imm8 m512 k zmm +// VGETMANTPS.Z imm8 zmm k zmm +// Construct and append a VGETMANTPS.Z instruction to the active function. +// Operates on the global context. +func VGETMANTPS_Z(i, mxyz, k, xyz operand.Op) { ctx.VGETMANTPS_Z(i, mxyz, k, xyz) } + +// VGETMANTSD: Extract Normalized Mantissa from Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// VGETMANTSD imm8 m64 xmm k xmm +// VGETMANTSD imm8 m64 xmm xmm +// VGETMANTSD imm8 xmm xmm k xmm +// VGETMANTSD imm8 xmm xmm xmm +// Construct and append a VGETMANTSD instruction to the active function. +func (c *Context) VGETMANTSD(ops ...operand.Op) { + c.addinstruction(x86.VGETMANTSD(ops...)) +} + +// VGETMANTSD: Extract Normalized Mantissa from Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// VGETMANTSD imm8 m64 xmm k xmm +// VGETMANTSD imm8 m64 xmm xmm +// VGETMANTSD imm8 xmm xmm k xmm +// VGETMANTSD imm8 xmm xmm xmm +// Construct and append a VGETMANTSD instruction to the active function. +// Operates on the global context. +func VGETMANTSD(ops ...operand.Op) { ctx.VGETMANTSD(ops...) } + +// VGETMANTSD_SAE: Extract Normalized Mantissa from Scalar Double-Precision Floating-Point Value (Suppress All Exceptions). +// +// Forms: +// +// VGETMANTSD.SAE imm8 xmm xmm k xmm +// VGETMANTSD.SAE imm8 xmm xmm xmm +// Construct and append a VGETMANTSD.SAE instruction to the active function. +func (c *Context) VGETMANTSD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VGETMANTSD_SAE(ops...)) +} + +// VGETMANTSD_SAE: Extract Normalized Mantissa from Scalar Double-Precision Floating-Point Value (Suppress All Exceptions). +// +// Forms: +// +// VGETMANTSD.SAE imm8 xmm xmm k xmm +// VGETMANTSD.SAE imm8 xmm xmm xmm +// Construct and append a VGETMANTSD.SAE instruction to the active function. +// Operates on the global context. +func VGETMANTSD_SAE(ops ...operand.Op) { ctx.VGETMANTSD_SAE(ops...) } + +// VGETMANTSD_SAE_Z: Extract Normalized Mantissa from Scalar Double-Precision Floating-Point Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VGETMANTSD.SAE.Z imm8 xmm xmm k xmm +// Construct and append a VGETMANTSD.SAE.Z instruction to the active function. +func (c *Context) VGETMANTSD_SAE_Z(i, x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VGETMANTSD_SAE_Z(i, x, x1, k, x2)) +} + +// VGETMANTSD_SAE_Z: Extract Normalized Mantissa from Scalar Double-Precision Floating-Point Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VGETMANTSD.SAE.Z imm8 xmm xmm k xmm +// Construct and append a VGETMANTSD.SAE.Z instruction to the active function. +// Operates on the global context. +func VGETMANTSD_SAE_Z(i, x, x1, k, x2 operand.Op) { ctx.VGETMANTSD_SAE_Z(i, x, x1, k, x2) } + +// VGETMANTSD_Z: Extract Normalized Mantissa from Scalar Double-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VGETMANTSD.Z imm8 m64 xmm k xmm +// VGETMANTSD.Z imm8 xmm xmm k xmm +// Construct and append a VGETMANTSD.Z instruction to the active function. +func (c *Context) VGETMANTSD_Z(i, mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VGETMANTSD_Z(i, mx, x, k, x1)) +} + +// VGETMANTSD_Z: Extract Normalized Mantissa from Scalar Double-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VGETMANTSD.Z imm8 m64 xmm k xmm +// VGETMANTSD.Z imm8 xmm xmm k xmm +// Construct and append a VGETMANTSD.Z instruction to the active function. +// Operates on the global context. +func VGETMANTSD_Z(i, mx, x, k, x1 operand.Op) { ctx.VGETMANTSD_Z(i, mx, x, k, x1) } + +// VGETMANTSS: Extract Normalized Mantissa from Scalar Single-Precision Floating-Point Value. +// +// Forms: +// +// VGETMANTSS imm8 m32 xmm k xmm +// VGETMANTSS imm8 m32 xmm xmm +// VGETMANTSS imm8 xmm xmm k xmm +// VGETMANTSS imm8 xmm xmm xmm +// Construct and append a VGETMANTSS instruction to the active function. +func (c *Context) VGETMANTSS(ops ...operand.Op) { + c.addinstruction(x86.VGETMANTSS(ops...)) +} + +// VGETMANTSS: Extract Normalized Mantissa from Scalar Single-Precision Floating-Point Value. +// +// Forms: +// +// VGETMANTSS imm8 m32 xmm k xmm +// VGETMANTSS imm8 m32 xmm xmm +// VGETMANTSS imm8 xmm xmm k xmm +// VGETMANTSS imm8 xmm xmm xmm +// Construct and append a VGETMANTSS instruction to the active function. +// Operates on the global context. +func VGETMANTSS(ops ...operand.Op) { ctx.VGETMANTSS(ops...) } + +// VGETMANTSS_SAE: Extract Normalized Mantissa from Scalar Single-Precision Floating-Point Value (Suppress All Exceptions). +// +// Forms: +// +// VGETMANTSS.SAE imm8 xmm xmm k xmm +// VGETMANTSS.SAE imm8 xmm xmm xmm +// Construct and append a VGETMANTSS.SAE instruction to the active function. +func (c *Context) VGETMANTSS_SAE(ops ...operand.Op) { + c.addinstruction(x86.VGETMANTSS_SAE(ops...)) +} + +// VGETMANTSS_SAE: Extract Normalized Mantissa from Scalar Single-Precision Floating-Point Value (Suppress All Exceptions). +// +// Forms: +// +// VGETMANTSS.SAE imm8 xmm xmm k xmm +// VGETMANTSS.SAE imm8 xmm xmm xmm +// Construct and append a VGETMANTSS.SAE instruction to the active function. +// Operates on the global context. +func VGETMANTSS_SAE(ops ...operand.Op) { ctx.VGETMANTSS_SAE(ops...) } + +// VGETMANTSS_SAE_Z: Extract Normalized Mantissa from Scalar Single-Precision Floating-Point Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VGETMANTSS.SAE.Z imm8 xmm xmm k xmm +// Construct and append a VGETMANTSS.SAE.Z instruction to the active function. +func (c *Context) VGETMANTSS_SAE_Z(i, x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VGETMANTSS_SAE_Z(i, x, x1, k, x2)) +} + +// VGETMANTSS_SAE_Z: Extract Normalized Mantissa from Scalar Single-Precision Floating-Point Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VGETMANTSS.SAE.Z imm8 xmm xmm k xmm +// Construct and append a VGETMANTSS.SAE.Z instruction to the active function. +// Operates on the global context. +func VGETMANTSS_SAE_Z(i, x, x1, k, x2 operand.Op) { ctx.VGETMANTSS_SAE_Z(i, x, x1, k, x2) } + +// VGETMANTSS_Z: Extract Normalized Mantissa from Scalar Single-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VGETMANTSS.Z imm8 m32 xmm k xmm +// VGETMANTSS.Z imm8 xmm xmm k xmm +// Construct and append a VGETMANTSS.Z instruction to the active function. +func (c *Context) VGETMANTSS_Z(i, mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VGETMANTSS_Z(i, mx, x, k, x1)) +} + +// VGETMANTSS_Z: Extract Normalized Mantissa from Scalar Single-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VGETMANTSS.Z imm8 m32 xmm k xmm +// VGETMANTSS.Z imm8 xmm xmm k xmm +// Construct and append a VGETMANTSS.Z instruction to the active function. +// Operates on the global context. +func VGETMANTSS_Z(i, mx, x, k, x1 operand.Op) { ctx.VGETMANTSS_Z(i, mx, x, k, x1) } + +// VHADDPD: Packed Double-FP Horizontal Add. +// +// Forms: +// +// VHADDPD m128 xmm xmm +// VHADDPD m256 ymm ymm +// VHADDPD xmm xmm xmm +// VHADDPD ymm ymm ymm +// Construct and append a VHADDPD instruction to the active function. +func (c *Context) VHADDPD(mxy, xy, xy1 operand.Op) { + c.addinstruction(x86.VHADDPD(mxy, xy, xy1)) +} + +// VHADDPD: Packed Double-FP Horizontal Add. +// +// Forms: +// +// VHADDPD m128 xmm xmm +// VHADDPD m256 ymm ymm +// VHADDPD xmm xmm xmm +// VHADDPD ymm ymm ymm +// Construct and append a VHADDPD instruction to the active function. +// Operates on the global context. +func VHADDPD(mxy, xy, xy1 operand.Op) { ctx.VHADDPD(mxy, xy, xy1) } + +// VHADDPS: Packed Single-FP Horizontal Add. +// +// Forms: +// +// VHADDPS m128 xmm xmm +// VHADDPS m256 ymm ymm +// VHADDPS xmm xmm xmm +// VHADDPS ymm ymm ymm +// Construct and append a VHADDPS instruction to the active function. +func (c *Context) VHADDPS(mxy, xy, xy1 operand.Op) { + c.addinstruction(x86.VHADDPS(mxy, xy, xy1)) +} + +// VHADDPS: Packed Single-FP Horizontal Add. +// +// Forms: +// +// VHADDPS m128 xmm xmm +// VHADDPS m256 ymm ymm +// VHADDPS xmm xmm xmm +// VHADDPS ymm ymm ymm +// Construct and append a VHADDPS instruction to the active function. +// Operates on the global context. +func VHADDPS(mxy, xy, xy1 operand.Op) { ctx.VHADDPS(mxy, xy, xy1) } + +// VHSUBPD: Packed Double-FP Horizontal Subtract. +// +// Forms: +// +// VHSUBPD m128 xmm xmm +// VHSUBPD m256 ymm ymm +// VHSUBPD xmm xmm xmm +// VHSUBPD ymm ymm ymm +// Construct and append a VHSUBPD instruction to the active function. +func (c *Context) VHSUBPD(mxy, xy, xy1 operand.Op) { + c.addinstruction(x86.VHSUBPD(mxy, xy, xy1)) +} + +// VHSUBPD: Packed Double-FP Horizontal Subtract. +// +// Forms: +// +// VHSUBPD m128 xmm xmm +// VHSUBPD m256 ymm ymm +// VHSUBPD xmm xmm xmm +// VHSUBPD ymm ymm ymm +// Construct and append a VHSUBPD instruction to the active function. +// Operates on the global context. +func VHSUBPD(mxy, xy, xy1 operand.Op) { ctx.VHSUBPD(mxy, xy, xy1) } + +// VHSUBPS: Packed Single-FP Horizontal Subtract. +// +// Forms: +// +// VHSUBPS m128 xmm xmm +// VHSUBPS m256 ymm ymm +// VHSUBPS xmm xmm xmm +// VHSUBPS ymm ymm ymm +// Construct and append a VHSUBPS instruction to the active function. +func (c *Context) VHSUBPS(mxy, xy, xy1 operand.Op) { + c.addinstruction(x86.VHSUBPS(mxy, xy, xy1)) +} + +// VHSUBPS: Packed Single-FP Horizontal Subtract. +// +// Forms: +// +// VHSUBPS m128 xmm xmm +// VHSUBPS m256 ymm ymm +// VHSUBPS xmm xmm xmm +// VHSUBPS ymm ymm ymm +// Construct and append a VHSUBPS instruction to the active function. +// Operates on the global context. +func VHSUBPS(mxy, xy, xy1 operand.Op) { ctx.VHSUBPS(mxy, xy, xy1) } + +// VINSERTF128: Insert Packed Floating-Point Values. +// +// Forms: +// +// VINSERTF128 imm8 m128 ymm ymm +// VINSERTF128 imm8 xmm ymm ymm +// Construct and append a VINSERTF128 instruction to the active function. +func (c *Context) VINSERTF128(i, mx, y, y1 operand.Op) { + c.addinstruction(x86.VINSERTF128(i, mx, y, y1)) +} + +// VINSERTF128: Insert Packed Floating-Point Values. +// +// Forms: +// +// VINSERTF128 imm8 m128 ymm ymm +// VINSERTF128 imm8 xmm ymm ymm +// Construct and append a VINSERTF128 instruction to the active function. +// Operates on the global context. +func VINSERTF128(i, mx, y, y1 operand.Op) { ctx.VINSERTF128(i, mx, y, y1) } + +// VINSERTF32X4: Insert 128 Bits of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VINSERTF32X4 imm8 m128 ymm k ymm +// VINSERTF32X4 imm8 m128 ymm ymm +// VINSERTF32X4 imm8 xmm ymm k ymm +// VINSERTF32X4 imm8 xmm ymm ymm +// VINSERTF32X4 imm8 m128 zmm k zmm +// VINSERTF32X4 imm8 m128 zmm zmm +// VINSERTF32X4 imm8 xmm zmm k zmm +// VINSERTF32X4 imm8 xmm zmm zmm +// Construct and append a VINSERTF32X4 instruction to the active function. +func (c *Context) VINSERTF32X4(ops ...operand.Op) { + c.addinstruction(x86.VINSERTF32X4(ops...)) +} + +// VINSERTF32X4: Insert 128 Bits of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VINSERTF32X4 imm8 m128 ymm k ymm +// VINSERTF32X4 imm8 m128 ymm ymm +// VINSERTF32X4 imm8 xmm ymm k ymm +// VINSERTF32X4 imm8 xmm ymm ymm +// VINSERTF32X4 imm8 m128 zmm k zmm +// VINSERTF32X4 imm8 m128 zmm zmm +// VINSERTF32X4 imm8 xmm zmm k zmm +// VINSERTF32X4 imm8 xmm zmm zmm +// Construct and append a VINSERTF32X4 instruction to the active function. +// Operates on the global context. +func VINSERTF32X4(ops ...operand.Op) { ctx.VINSERTF32X4(ops...) } + +// VINSERTF32X4_Z: Insert 128 Bits of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VINSERTF32X4.Z imm8 m128 ymm k ymm +// VINSERTF32X4.Z imm8 xmm ymm k ymm +// VINSERTF32X4.Z imm8 m128 zmm k zmm +// VINSERTF32X4.Z imm8 xmm zmm k zmm +// Construct and append a VINSERTF32X4.Z instruction to the active function. +func (c *Context) VINSERTF32X4_Z(i, mx, yz, k, yz1 operand.Op) { + c.addinstruction(x86.VINSERTF32X4_Z(i, mx, yz, k, yz1)) +} + +// VINSERTF32X4_Z: Insert 128 Bits of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VINSERTF32X4.Z imm8 m128 ymm k ymm +// VINSERTF32X4.Z imm8 xmm ymm k ymm +// VINSERTF32X4.Z imm8 m128 zmm k zmm +// VINSERTF32X4.Z imm8 xmm zmm k zmm +// Construct and append a VINSERTF32X4.Z instruction to the active function. +// Operates on the global context. +func VINSERTF32X4_Z(i, mx, yz, k, yz1 operand.Op) { ctx.VINSERTF32X4_Z(i, mx, yz, k, yz1) } + +// VINSERTF32X8: Insert 256 Bits of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VINSERTF32X8 imm8 m256 zmm k zmm +// VINSERTF32X8 imm8 m256 zmm zmm +// VINSERTF32X8 imm8 ymm zmm k zmm +// VINSERTF32X8 imm8 ymm zmm zmm +// Construct and append a VINSERTF32X8 instruction to the active function. +func (c *Context) VINSERTF32X8(ops ...operand.Op) { + c.addinstruction(x86.VINSERTF32X8(ops...)) +} + +// VINSERTF32X8: Insert 256 Bits of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VINSERTF32X8 imm8 m256 zmm k zmm +// VINSERTF32X8 imm8 m256 zmm zmm +// VINSERTF32X8 imm8 ymm zmm k zmm +// VINSERTF32X8 imm8 ymm zmm zmm +// Construct and append a VINSERTF32X8 instruction to the active function. +// Operates on the global context. +func VINSERTF32X8(ops ...operand.Op) { ctx.VINSERTF32X8(ops...) } + +// VINSERTF32X8_Z: Insert 256 Bits of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VINSERTF32X8.Z imm8 m256 zmm k zmm +// VINSERTF32X8.Z imm8 ymm zmm k zmm +// Construct and append a VINSERTF32X8.Z instruction to the active function. +func (c *Context) VINSERTF32X8_Z(i, my, z, k, z1 operand.Op) { + c.addinstruction(x86.VINSERTF32X8_Z(i, my, z, k, z1)) +} + +// VINSERTF32X8_Z: Insert 256 Bits of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VINSERTF32X8.Z imm8 m256 zmm k zmm +// VINSERTF32X8.Z imm8 ymm zmm k zmm +// Construct and append a VINSERTF32X8.Z instruction to the active function. +// Operates on the global context. +func VINSERTF32X8_Z(i, my, z, k, z1 operand.Op) { ctx.VINSERTF32X8_Z(i, my, z, k, z1) } + +// VINSERTF64X2: Insert 128 Bits of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VINSERTF64X2 imm8 m128 ymm k ymm +// VINSERTF64X2 imm8 m128 ymm ymm +// VINSERTF64X2 imm8 xmm ymm k ymm +// VINSERTF64X2 imm8 xmm ymm ymm +// VINSERTF64X2 imm8 m128 zmm k zmm +// VINSERTF64X2 imm8 m128 zmm zmm +// VINSERTF64X2 imm8 xmm zmm k zmm +// VINSERTF64X2 imm8 xmm zmm zmm +// Construct and append a VINSERTF64X2 instruction to the active function. +func (c *Context) VINSERTF64X2(ops ...operand.Op) { + c.addinstruction(x86.VINSERTF64X2(ops...)) +} + +// VINSERTF64X2: Insert 128 Bits of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VINSERTF64X2 imm8 m128 ymm k ymm +// VINSERTF64X2 imm8 m128 ymm ymm +// VINSERTF64X2 imm8 xmm ymm k ymm +// VINSERTF64X2 imm8 xmm ymm ymm +// VINSERTF64X2 imm8 m128 zmm k zmm +// VINSERTF64X2 imm8 m128 zmm zmm +// VINSERTF64X2 imm8 xmm zmm k zmm +// VINSERTF64X2 imm8 xmm zmm zmm +// Construct and append a VINSERTF64X2 instruction to the active function. +// Operates on the global context. +func VINSERTF64X2(ops ...operand.Op) { ctx.VINSERTF64X2(ops...) } + +// VINSERTF64X2_Z: Insert 128 Bits of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VINSERTF64X2.Z imm8 m128 ymm k ymm +// VINSERTF64X2.Z imm8 xmm ymm k ymm +// VINSERTF64X2.Z imm8 m128 zmm k zmm +// VINSERTF64X2.Z imm8 xmm zmm k zmm +// Construct and append a VINSERTF64X2.Z instruction to the active function. +func (c *Context) VINSERTF64X2_Z(i, mx, yz, k, yz1 operand.Op) { + c.addinstruction(x86.VINSERTF64X2_Z(i, mx, yz, k, yz1)) +} + +// VINSERTF64X2_Z: Insert 128 Bits of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VINSERTF64X2.Z imm8 m128 ymm k ymm +// VINSERTF64X2.Z imm8 xmm ymm k ymm +// VINSERTF64X2.Z imm8 m128 zmm k zmm +// VINSERTF64X2.Z imm8 xmm zmm k zmm +// Construct and append a VINSERTF64X2.Z instruction to the active function. +// Operates on the global context. +func VINSERTF64X2_Z(i, mx, yz, k, yz1 operand.Op) { ctx.VINSERTF64X2_Z(i, mx, yz, k, yz1) } + +// VINSERTF64X4: Insert 256 Bits of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VINSERTF64X4 imm8 m256 zmm k zmm +// VINSERTF64X4 imm8 m256 zmm zmm +// VINSERTF64X4 imm8 ymm zmm k zmm +// VINSERTF64X4 imm8 ymm zmm zmm +// Construct and append a VINSERTF64X4 instruction to the active function. +func (c *Context) VINSERTF64X4(ops ...operand.Op) { + c.addinstruction(x86.VINSERTF64X4(ops...)) +} + +// VINSERTF64X4: Insert 256 Bits of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VINSERTF64X4 imm8 m256 zmm k zmm +// VINSERTF64X4 imm8 m256 zmm zmm +// VINSERTF64X4 imm8 ymm zmm k zmm +// VINSERTF64X4 imm8 ymm zmm zmm +// Construct and append a VINSERTF64X4 instruction to the active function. +// Operates on the global context. +func VINSERTF64X4(ops ...operand.Op) { ctx.VINSERTF64X4(ops...) } + +// VINSERTF64X4_Z: Insert 256 Bits of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VINSERTF64X4.Z imm8 m256 zmm k zmm +// VINSERTF64X4.Z imm8 ymm zmm k zmm +// Construct and append a VINSERTF64X4.Z instruction to the active function. +func (c *Context) VINSERTF64X4_Z(i, my, z, k, z1 operand.Op) { + c.addinstruction(x86.VINSERTF64X4_Z(i, my, z, k, z1)) +} + +// VINSERTF64X4_Z: Insert 256 Bits of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VINSERTF64X4.Z imm8 m256 zmm k zmm +// VINSERTF64X4.Z imm8 ymm zmm k zmm +// Construct and append a VINSERTF64X4.Z instruction to the active function. +// Operates on the global context. +func VINSERTF64X4_Z(i, my, z, k, z1 operand.Op) { ctx.VINSERTF64X4_Z(i, my, z, k, z1) } + +// VINSERTI128: Insert Packed Integer Values. +// +// Forms: +// +// VINSERTI128 imm8 m128 ymm ymm +// VINSERTI128 imm8 xmm ymm ymm +// Construct and append a VINSERTI128 instruction to the active function. +func (c *Context) VINSERTI128(i, mx, y, y1 operand.Op) { + c.addinstruction(x86.VINSERTI128(i, mx, y, y1)) +} + +// VINSERTI128: Insert Packed Integer Values. +// +// Forms: +// +// VINSERTI128 imm8 m128 ymm ymm +// VINSERTI128 imm8 xmm ymm ymm +// Construct and append a VINSERTI128 instruction to the active function. +// Operates on the global context. +func VINSERTI128(i, mx, y, y1 operand.Op) { ctx.VINSERTI128(i, mx, y, y1) } + +// VINSERTI32X4: Insert 128 Bits of Packed Doubleword Integer Values. +// +// Forms: +// +// VINSERTI32X4 imm8 m128 ymm k ymm +// VINSERTI32X4 imm8 m128 ymm ymm +// VINSERTI32X4 imm8 xmm ymm k ymm +// VINSERTI32X4 imm8 xmm ymm ymm +// VINSERTI32X4 imm8 m128 zmm k zmm +// VINSERTI32X4 imm8 m128 zmm zmm +// VINSERTI32X4 imm8 xmm zmm k zmm +// VINSERTI32X4 imm8 xmm zmm zmm +// Construct and append a VINSERTI32X4 instruction to the active function. +func (c *Context) VINSERTI32X4(ops ...operand.Op) { + c.addinstruction(x86.VINSERTI32X4(ops...)) +} + +// VINSERTI32X4: Insert 128 Bits of Packed Doubleword Integer Values. +// +// Forms: +// +// VINSERTI32X4 imm8 m128 ymm k ymm +// VINSERTI32X4 imm8 m128 ymm ymm +// VINSERTI32X4 imm8 xmm ymm k ymm +// VINSERTI32X4 imm8 xmm ymm ymm +// VINSERTI32X4 imm8 m128 zmm k zmm +// VINSERTI32X4 imm8 m128 zmm zmm +// VINSERTI32X4 imm8 xmm zmm k zmm +// VINSERTI32X4 imm8 xmm zmm zmm +// Construct and append a VINSERTI32X4 instruction to the active function. +// Operates on the global context. +func VINSERTI32X4(ops ...operand.Op) { ctx.VINSERTI32X4(ops...) } + +// VINSERTI32X4_Z: Insert 128 Bits of Packed Doubleword Integer Values (Zeroing Masking). +// +// Forms: +// +// VINSERTI32X4.Z imm8 m128 ymm k ymm +// VINSERTI32X4.Z imm8 xmm ymm k ymm +// VINSERTI32X4.Z imm8 m128 zmm k zmm +// VINSERTI32X4.Z imm8 xmm zmm k zmm +// Construct and append a VINSERTI32X4.Z instruction to the active function. +func (c *Context) VINSERTI32X4_Z(i, mx, yz, k, yz1 operand.Op) { + c.addinstruction(x86.VINSERTI32X4_Z(i, mx, yz, k, yz1)) +} + +// VINSERTI32X4_Z: Insert 128 Bits of Packed Doubleword Integer Values (Zeroing Masking). +// +// Forms: +// +// VINSERTI32X4.Z imm8 m128 ymm k ymm +// VINSERTI32X4.Z imm8 xmm ymm k ymm +// VINSERTI32X4.Z imm8 m128 zmm k zmm +// VINSERTI32X4.Z imm8 xmm zmm k zmm +// Construct and append a VINSERTI32X4.Z instruction to the active function. +// Operates on the global context. +func VINSERTI32X4_Z(i, mx, yz, k, yz1 operand.Op) { ctx.VINSERTI32X4_Z(i, mx, yz, k, yz1) } + +// VINSERTI32X8: Insert 256 Bits of Packed Doubleword Integer Values. +// +// Forms: +// +// VINSERTI32X8 imm8 m256 zmm k zmm +// VINSERTI32X8 imm8 m256 zmm zmm +// VINSERTI32X8 imm8 ymm zmm k zmm +// VINSERTI32X8 imm8 ymm zmm zmm +// Construct and append a VINSERTI32X8 instruction to the active function. +func (c *Context) VINSERTI32X8(ops ...operand.Op) { + c.addinstruction(x86.VINSERTI32X8(ops...)) +} + +// VINSERTI32X8: Insert 256 Bits of Packed Doubleword Integer Values. +// +// Forms: +// +// VINSERTI32X8 imm8 m256 zmm k zmm +// VINSERTI32X8 imm8 m256 zmm zmm +// VINSERTI32X8 imm8 ymm zmm k zmm +// VINSERTI32X8 imm8 ymm zmm zmm +// Construct and append a VINSERTI32X8 instruction to the active function. +// Operates on the global context. +func VINSERTI32X8(ops ...operand.Op) { ctx.VINSERTI32X8(ops...) } + +// VINSERTI32X8_Z: Insert 256 Bits of Packed Doubleword Integer Values (Zeroing Masking). +// +// Forms: +// +// VINSERTI32X8.Z imm8 m256 zmm k zmm +// VINSERTI32X8.Z imm8 ymm zmm k zmm +// Construct and append a VINSERTI32X8.Z instruction to the active function. +func (c *Context) VINSERTI32X8_Z(i, my, z, k, z1 operand.Op) { + c.addinstruction(x86.VINSERTI32X8_Z(i, my, z, k, z1)) +} + +// VINSERTI32X8_Z: Insert 256 Bits of Packed Doubleword Integer Values (Zeroing Masking). +// +// Forms: +// +// VINSERTI32X8.Z imm8 m256 zmm k zmm +// VINSERTI32X8.Z imm8 ymm zmm k zmm +// Construct and append a VINSERTI32X8.Z instruction to the active function. +// Operates on the global context. +func VINSERTI32X8_Z(i, my, z, k, z1 operand.Op) { ctx.VINSERTI32X8_Z(i, my, z, k, z1) } + +// VINSERTI64X2: Insert 128 Bits of Packed Quadword Integer Values. +// +// Forms: +// +// VINSERTI64X2 imm8 m128 ymm k ymm +// VINSERTI64X2 imm8 m128 ymm ymm +// VINSERTI64X2 imm8 xmm ymm k ymm +// VINSERTI64X2 imm8 xmm ymm ymm +// VINSERTI64X2 imm8 m128 zmm k zmm +// VINSERTI64X2 imm8 m128 zmm zmm +// VINSERTI64X2 imm8 xmm zmm k zmm +// VINSERTI64X2 imm8 xmm zmm zmm +// Construct and append a VINSERTI64X2 instruction to the active function. +func (c *Context) VINSERTI64X2(ops ...operand.Op) { + c.addinstruction(x86.VINSERTI64X2(ops...)) +} + +// VINSERTI64X2: Insert 128 Bits of Packed Quadword Integer Values. +// +// Forms: +// +// VINSERTI64X2 imm8 m128 ymm k ymm +// VINSERTI64X2 imm8 m128 ymm ymm +// VINSERTI64X2 imm8 xmm ymm k ymm +// VINSERTI64X2 imm8 xmm ymm ymm +// VINSERTI64X2 imm8 m128 zmm k zmm +// VINSERTI64X2 imm8 m128 zmm zmm +// VINSERTI64X2 imm8 xmm zmm k zmm +// VINSERTI64X2 imm8 xmm zmm zmm +// Construct and append a VINSERTI64X2 instruction to the active function. +// Operates on the global context. +func VINSERTI64X2(ops ...operand.Op) { ctx.VINSERTI64X2(ops...) } + +// VINSERTI64X2_Z: Insert 128 Bits of Packed Quadword Integer Values (Zeroing Masking). +// +// Forms: +// +// VINSERTI64X2.Z imm8 m128 ymm k ymm +// VINSERTI64X2.Z imm8 xmm ymm k ymm +// VINSERTI64X2.Z imm8 m128 zmm k zmm +// VINSERTI64X2.Z imm8 xmm zmm k zmm +// Construct and append a VINSERTI64X2.Z instruction to the active function. +func (c *Context) VINSERTI64X2_Z(i, mx, yz, k, yz1 operand.Op) { + c.addinstruction(x86.VINSERTI64X2_Z(i, mx, yz, k, yz1)) +} + +// VINSERTI64X2_Z: Insert 128 Bits of Packed Quadword Integer Values (Zeroing Masking). +// +// Forms: +// +// VINSERTI64X2.Z imm8 m128 ymm k ymm +// VINSERTI64X2.Z imm8 xmm ymm k ymm +// VINSERTI64X2.Z imm8 m128 zmm k zmm +// VINSERTI64X2.Z imm8 xmm zmm k zmm +// Construct and append a VINSERTI64X2.Z instruction to the active function. +// Operates on the global context. +func VINSERTI64X2_Z(i, mx, yz, k, yz1 operand.Op) { ctx.VINSERTI64X2_Z(i, mx, yz, k, yz1) } + +// VINSERTI64X4: Insert 256 Bits of Packed Quadword Integer Values. +// +// Forms: +// +// VINSERTI64X4 imm8 m256 zmm k zmm +// VINSERTI64X4 imm8 m256 zmm zmm +// VINSERTI64X4 imm8 ymm zmm k zmm +// VINSERTI64X4 imm8 ymm zmm zmm +// Construct and append a VINSERTI64X4 instruction to the active function. +func (c *Context) VINSERTI64X4(ops ...operand.Op) { + c.addinstruction(x86.VINSERTI64X4(ops...)) +} + +// VINSERTI64X4: Insert 256 Bits of Packed Quadword Integer Values. +// +// Forms: +// +// VINSERTI64X4 imm8 m256 zmm k zmm +// VINSERTI64X4 imm8 m256 zmm zmm +// VINSERTI64X4 imm8 ymm zmm k zmm +// VINSERTI64X4 imm8 ymm zmm zmm +// Construct and append a VINSERTI64X4 instruction to the active function. +// Operates on the global context. +func VINSERTI64X4(ops ...operand.Op) { ctx.VINSERTI64X4(ops...) } + +// VINSERTI64X4_Z: Insert 256 Bits of Packed Quadword Integer Values (Zeroing Masking). +// +// Forms: +// +// VINSERTI64X4.Z imm8 m256 zmm k zmm +// VINSERTI64X4.Z imm8 ymm zmm k zmm +// Construct and append a VINSERTI64X4.Z instruction to the active function. +func (c *Context) VINSERTI64X4_Z(i, my, z, k, z1 operand.Op) { + c.addinstruction(x86.VINSERTI64X4_Z(i, my, z, k, z1)) +} + +// VINSERTI64X4_Z: Insert 256 Bits of Packed Quadword Integer Values (Zeroing Masking). +// +// Forms: +// +// VINSERTI64X4.Z imm8 m256 zmm k zmm +// VINSERTI64X4.Z imm8 ymm zmm k zmm +// Construct and append a VINSERTI64X4.Z instruction to the active function. +// Operates on the global context. +func VINSERTI64X4_Z(i, my, z, k, z1 operand.Op) { ctx.VINSERTI64X4_Z(i, my, z, k, z1) } + +// VINSERTPS: Insert Packed Single Precision Floating-Point Value. +// +// Forms: +// +// VINSERTPS imm8 m32 xmm xmm +// VINSERTPS imm8 xmm xmm xmm +// Construct and append a VINSERTPS instruction to the active function. +func (c *Context) VINSERTPS(i, mx, x, x1 operand.Op) { + c.addinstruction(x86.VINSERTPS(i, mx, x, x1)) +} + +// VINSERTPS: Insert Packed Single Precision Floating-Point Value. +// +// Forms: +// +// VINSERTPS imm8 m32 xmm xmm +// VINSERTPS imm8 xmm xmm xmm +// Construct and append a VINSERTPS instruction to the active function. +// Operates on the global context. +func VINSERTPS(i, mx, x, x1 operand.Op) { ctx.VINSERTPS(i, mx, x, x1) } + +// VLDDQU: Load Unaligned Integer 128 Bits. +// +// Forms: +// +// VLDDQU m128 xmm +// VLDDQU m256 ymm +// Construct and append a VLDDQU instruction to the active function. +func (c *Context) VLDDQU(m, xy operand.Op) { + c.addinstruction(x86.VLDDQU(m, xy)) +} + +// VLDDQU: Load Unaligned Integer 128 Bits. +// +// Forms: +// +// VLDDQU m128 xmm +// VLDDQU m256 ymm +// Construct and append a VLDDQU instruction to the active function. +// Operates on the global context. +func VLDDQU(m, xy operand.Op) { ctx.VLDDQU(m, xy) } + +// VLDMXCSR: Load MXCSR Register. +// +// Forms: +// +// VLDMXCSR m32 +// Construct and append a VLDMXCSR instruction to the active function. +func (c *Context) VLDMXCSR(m operand.Op) { + c.addinstruction(x86.VLDMXCSR(m)) +} + +// VLDMXCSR: Load MXCSR Register. +// +// Forms: +// +// VLDMXCSR m32 +// Construct and append a VLDMXCSR instruction to the active function. +// Operates on the global context. +func VLDMXCSR(m operand.Op) { ctx.VLDMXCSR(m) } + +// VMASKMOVDQU: Store Selected Bytes of Double Quadword. +// +// Forms: +// +// VMASKMOVDQU xmm xmm +// Construct and append a VMASKMOVDQU instruction to the active function. +func (c *Context) VMASKMOVDQU(x, x1 operand.Op) { + c.addinstruction(x86.VMASKMOVDQU(x, x1)) +} + +// VMASKMOVDQU: Store Selected Bytes of Double Quadword. +// +// Forms: +// +// VMASKMOVDQU xmm xmm +// Construct and append a VMASKMOVDQU instruction to the active function. +// Operates on the global context. +func VMASKMOVDQU(x, x1 operand.Op) { ctx.VMASKMOVDQU(x, x1) } + +// VMASKMOVPD: Conditional Move Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VMASKMOVPD m128 xmm xmm +// VMASKMOVPD m256 ymm ymm +// VMASKMOVPD xmm xmm m128 +// VMASKMOVPD ymm ymm m256 +// Construct and append a VMASKMOVPD instruction to the active function. +func (c *Context) VMASKMOVPD(mxy, xy, mxy1 operand.Op) { + c.addinstruction(x86.VMASKMOVPD(mxy, xy, mxy1)) +} + +// VMASKMOVPD: Conditional Move Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VMASKMOVPD m128 xmm xmm +// VMASKMOVPD m256 ymm ymm +// VMASKMOVPD xmm xmm m128 +// VMASKMOVPD ymm ymm m256 +// Construct and append a VMASKMOVPD instruction to the active function. +// Operates on the global context. +func VMASKMOVPD(mxy, xy, mxy1 operand.Op) { ctx.VMASKMOVPD(mxy, xy, mxy1) } + +// VMASKMOVPS: Conditional Move Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VMASKMOVPS m128 xmm xmm +// VMASKMOVPS m256 ymm ymm +// VMASKMOVPS xmm xmm m128 +// VMASKMOVPS ymm ymm m256 +// Construct and append a VMASKMOVPS instruction to the active function. +func (c *Context) VMASKMOVPS(mxy, xy, mxy1 operand.Op) { + c.addinstruction(x86.VMASKMOVPS(mxy, xy, mxy1)) +} + +// VMASKMOVPS: Conditional Move Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VMASKMOVPS m128 xmm xmm +// VMASKMOVPS m256 ymm ymm +// VMASKMOVPS xmm xmm m128 +// VMASKMOVPS ymm ymm m256 +// Construct and append a VMASKMOVPS instruction to the active function. +// Operates on the global context. +func VMASKMOVPS(mxy, xy, mxy1 operand.Op) { ctx.VMASKMOVPS(mxy, xy, mxy1) } + +// VMAXPD: Return Maximum Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VMAXPD m128 xmm xmm +// VMAXPD m256 ymm ymm +// VMAXPD xmm xmm xmm +// VMAXPD ymm ymm ymm +// VMAXPD m128 xmm k xmm +// VMAXPD m256 ymm k ymm +// VMAXPD xmm xmm k xmm +// VMAXPD ymm ymm k ymm +// VMAXPD m512 zmm k zmm +// VMAXPD m512 zmm zmm +// VMAXPD zmm zmm k zmm +// VMAXPD zmm zmm zmm +// Construct and append a VMAXPD instruction to the active function. +func (c *Context) VMAXPD(ops ...operand.Op) { + c.addinstruction(x86.VMAXPD(ops...)) +} + +// VMAXPD: Return Maximum Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VMAXPD m128 xmm xmm +// VMAXPD m256 ymm ymm +// VMAXPD xmm xmm xmm +// VMAXPD ymm ymm ymm +// VMAXPD m128 xmm k xmm +// VMAXPD m256 ymm k ymm +// VMAXPD xmm xmm k xmm +// VMAXPD ymm ymm k ymm +// VMAXPD m512 zmm k zmm +// VMAXPD m512 zmm zmm +// VMAXPD zmm zmm k zmm +// VMAXPD zmm zmm zmm +// Construct and append a VMAXPD instruction to the active function. +// Operates on the global context. +func VMAXPD(ops ...operand.Op) { ctx.VMAXPD(ops...) } + +// VMAXPD_BCST: Return Maximum Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VMAXPD.BCST m64 xmm k xmm +// VMAXPD.BCST m64 xmm xmm +// VMAXPD.BCST m64 ymm k ymm +// VMAXPD.BCST m64 ymm ymm +// VMAXPD.BCST m64 zmm k zmm +// VMAXPD.BCST m64 zmm zmm +// Construct and append a VMAXPD.BCST instruction to the active function. +func (c *Context) VMAXPD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VMAXPD_BCST(ops...)) +} + +// VMAXPD_BCST: Return Maximum Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VMAXPD.BCST m64 xmm k xmm +// VMAXPD.BCST m64 xmm xmm +// VMAXPD.BCST m64 ymm k ymm +// VMAXPD.BCST m64 ymm ymm +// VMAXPD.BCST m64 zmm k zmm +// VMAXPD.BCST m64 zmm zmm +// Construct and append a VMAXPD.BCST instruction to the active function. +// Operates on the global context. +func VMAXPD_BCST(ops ...operand.Op) { ctx.VMAXPD_BCST(ops...) } + +// VMAXPD_BCST_Z: Return Maximum Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VMAXPD.BCST.Z m64 xmm k xmm +// VMAXPD.BCST.Z m64 ymm k ymm +// VMAXPD.BCST.Z m64 zmm k zmm +// Construct and append a VMAXPD.BCST.Z instruction to the active function. +func (c *Context) VMAXPD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VMAXPD_BCST_Z(m, xyz, k, xyz1)) +} + +// VMAXPD_BCST_Z: Return Maximum Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VMAXPD.BCST.Z m64 xmm k xmm +// VMAXPD.BCST.Z m64 ymm k ymm +// VMAXPD.BCST.Z m64 zmm k zmm +// Construct and append a VMAXPD.BCST.Z instruction to the active function. +// Operates on the global context. +func VMAXPD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VMAXPD_BCST_Z(m, xyz, k, xyz1) } + +// VMAXPD_SAE: Return Maximum Packed Double-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VMAXPD.SAE zmm zmm k zmm +// VMAXPD.SAE zmm zmm zmm +// Construct and append a VMAXPD.SAE instruction to the active function. +func (c *Context) VMAXPD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VMAXPD_SAE(ops...)) +} + +// VMAXPD_SAE: Return Maximum Packed Double-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VMAXPD.SAE zmm zmm k zmm +// VMAXPD.SAE zmm zmm zmm +// Construct and append a VMAXPD.SAE instruction to the active function. +// Operates on the global context. +func VMAXPD_SAE(ops ...operand.Op) { ctx.VMAXPD_SAE(ops...) } + +// VMAXPD_SAE_Z: Return Maximum Packed Double-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VMAXPD.SAE.Z zmm zmm k zmm +// Construct and append a VMAXPD.SAE.Z instruction to the active function. +func (c *Context) VMAXPD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VMAXPD_SAE_Z(z, z1, k, z2)) +} + +// VMAXPD_SAE_Z: Return Maximum Packed Double-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VMAXPD.SAE.Z zmm zmm k zmm +// Construct and append a VMAXPD.SAE.Z instruction to the active function. +// Operates on the global context. +func VMAXPD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VMAXPD_SAE_Z(z, z1, k, z2) } + +// VMAXPD_Z: Return Maximum Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMAXPD.Z m128 xmm k xmm +// VMAXPD.Z m256 ymm k ymm +// VMAXPD.Z xmm xmm k xmm +// VMAXPD.Z ymm ymm k ymm +// VMAXPD.Z m512 zmm k zmm +// VMAXPD.Z zmm zmm k zmm +// Construct and append a VMAXPD.Z instruction to the active function. +func (c *Context) VMAXPD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VMAXPD_Z(mxyz, xyz, k, xyz1)) +} + +// VMAXPD_Z: Return Maximum Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMAXPD.Z m128 xmm k xmm +// VMAXPD.Z m256 ymm k ymm +// VMAXPD.Z xmm xmm k xmm +// VMAXPD.Z ymm ymm k ymm +// VMAXPD.Z m512 zmm k zmm +// VMAXPD.Z zmm zmm k zmm +// Construct and append a VMAXPD.Z instruction to the active function. +// Operates on the global context. +func VMAXPD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VMAXPD_Z(mxyz, xyz, k, xyz1) } + +// VMAXPS: Return Maximum Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VMAXPS m128 xmm xmm +// VMAXPS m256 ymm ymm +// VMAXPS xmm xmm xmm +// VMAXPS ymm ymm ymm +// VMAXPS m128 xmm k xmm +// VMAXPS m256 ymm k ymm +// VMAXPS xmm xmm k xmm +// VMAXPS ymm ymm k ymm +// VMAXPS m512 zmm k zmm +// VMAXPS m512 zmm zmm +// VMAXPS zmm zmm k zmm +// VMAXPS zmm zmm zmm +// Construct and append a VMAXPS instruction to the active function. +func (c *Context) VMAXPS(ops ...operand.Op) { + c.addinstruction(x86.VMAXPS(ops...)) +} + +// VMAXPS: Return Maximum Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VMAXPS m128 xmm xmm +// VMAXPS m256 ymm ymm +// VMAXPS xmm xmm xmm +// VMAXPS ymm ymm ymm +// VMAXPS m128 xmm k xmm +// VMAXPS m256 ymm k ymm +// VMAXPS xmm xmm k xmm +// VMAXPS ymm ymm k ymm +// VMAXPS m512 zmm k zmm +// VMAXPS m512 zmm zmm +// VMAXPS zmm zmm k zmm +// VMAXPS zmm zmm zmm +// Construct and append a VMAXPS instruction to the active function. +// Operates on the global context. +func VMAXPS(ops ...operand.Op) { ctx.VMAXPS(ops...) } + +// VMAXPS_BCST: Return Maximum Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VMAXPS.BCST m32 xmm k xmm +// VMAXPS.BCST m32 xmm xmm +// VMAXPS.BCST m32 ymm k ymm +// VMAXPS.BCST m32 ymm ymm +// VMAXPS.BCST m32 zmm k zmm +// VMAXPS.BCST m32 zmm zmm +// Construct and append a VMAXPS.BCST instruction to the active function. +func (c *Context) VMAXPS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VMAXPS_BCST(ops...)) +} + +// VMAXPS_BCST: Return Maximum Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VMAXPS.BCST m32 xmm k xmm +// VMAXPS.BCST m32 xmm xmm +// VMAXPS.BCST m32 ymm k ymm +// VMAXPS.BCST m32 ymm ymm +// VMAXPS.BCST m32 zmm k zmm +// VMAXPS.BCST m32 zmm zmm +// Construct and append a VMAXPS.BCST instruction to the active function. +// Operates on the global context. +func VMAXPS_BCST(ops ...operand.Op) { ctx.VMAXPS_BCST(ops...) } + +// VMAXPS_BCST_Z: Return Maximum Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VMAXPS.BCST.Z m32 xmm k xmm +// VMAXPS.BCST.Z m32 ymm k ymm +// VMAXPS.BCST.Z m32 zmm k zmm +// Construct and append a VMAXPS.BCST.Z instruction to the active function. +func (c *Context) VMAXPS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VMAXPS_BCST_Z(m, xyz, k, xyz1)) +} + +// VMAXPS_BCST_Z: Return Maximum Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VMAXPS.BCST.Z m32 xmm k xmm +// VMAXPS.BCST.Z m32 ymm k ymm +// VMAXPS.BCST.Z m32 zmm k zmm +// Construct and append a VMAXPS.BCST.Z instruction to the active function. +// Operates on the global context. +func VMAXPS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VMAXPS_BCST_Z(m, xyz, k, xyz1) } + +// VMAXPS_SAE: Return Maximum Packed Single-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VMAXPS.SAE zmm zmm k zmm +// VMAXPS.SAE zmm zmm zmm +// Construct and append a VMAXPS.SAE instruction to the active function. +func (c *Context) VMAXPS_SAE(ops ...operand.Op) { + c.addinstruction(x86.VMAXPS_SAE(ops...)) +} + +// VMAXPS_SAE: Return Maximum Packed Single-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VMAXPS.SAE zmm zmm k zmm +// VMAXPS.SAE zmm zmm zmm +// Construct and append a VMAXPS.SAE instruction to the active function. +// Operates on the global context. +func VMAXPS_SAE(ops ...operand.Op) { ctx.VMAXPS_SAE(ops...) } + +// VMAXPS_SAE_Z: Return Maximum Packed Single-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VMAXPS.SAE.Z zmm zmm k zmm +// Construct and append a VMAXPS.SAE.Z instruction to the active function. +func (c *Context) VMAXPS_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VMAXPS_SAE_Z(z, z1, k, z2)) +} + +// VMAXPS_SAE_Z: Return Maximum Packed Single-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VMAXPS.SAE.Z zmm zmm k zmm +// Construct and append a VMAXPS.SAE.Z instruction to the active function. +// Operates on the global context. +func VMAXPS_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VMAXPS_SAE_Z(z, z1, k, z2) } + +// VMAXPS_Z: Return Maximum Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMAXPS.Z m128 xmm k xmm +// VMAXPS.Z m256 ymm k ymm +// VMAXPS.Z xmm xmm k xmm +// VMAXPS.Z ymm ymm k ymm +// VMAXPS.Z m512 zmm k zmm +// VMAXPS.Z zmm zmm k zmm +// Construct and append a VMAXPS.Z instruction to the active function. +func (c *Context) VMAXPS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VMAXPS_Z(mxyz, xyz, k, xyz1)) +} + +// VMAXPS_Z: Return Maximum Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMAXPS.Z m128 xmm k xmm +// VMAXPS.Z m256 ymm k ymm +// VMAXPS.Z xmm xmm k xmm +// VMAXPS.Z ymm ymm k ymm +// VMAXPS.Z m512 zmm k zmm +// VMAXPS.Z zmm zmm k zmm +// Construct and append a VMAXPS.Z instruction to the active function. +// Operates on the global context. +func VMAXPS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VMAXPS_Z(mxyz, xyz, k, xyz1) } + +// VMAXSD: Return Maximum Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// VMAXSD m64 xmm xmm +// VMAXSD xmm xmm xmm +// VMAXSD m64 xmm k xmm +// VMAXSD xmm xmm k xmm +// Construct and append a VMAXSD instruction to the active function. +func (c *Context) VMAXSD(ops ...operand.Op) { + c.addinstruction(x86.VMAXSD(ops...)) +} + +// VMAXSD: Return Maximum Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// VMAXSD m64 xmm xmm +// VMAXSD xmm xmm xmm +// VMAXSD m64 xmm k xmm +// VMAXSD xmm xmm k xmm +// Construct and append a VMAXSD instruction to the active function. +// Operates on the global context. +func VMAXSD(ops ...operand.Op) { ctx.VMAXSD(ops...) } + +// VMAXSD_SAE: Return Maximum Scalar Double-Precision Floating-Point Value (Suppress All Exceptions). +// +// Forms: +// +// VMAXSD.SAE xmm xmm k xmm +// VMAXSD.SAE xmm xmm xmm +// Construct and append a VMAXSD.SAE instruction to the active function. +func (c *Context) VMAXSD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VMAXSD_SAE(ops...)) +} + +// VMAXSD_SAE: Return Maximum Scalar Double-Precision Floating-Point Value (Suppress All Exceptions). +// +// Forms: +// +// VMAXSD.SAE xmm xmm k xmm +// VMAXSD.SAE xmm xmm xmm +// Construct and append a VMAXSD.SAE instruction to the active function. +// Operates on the global context. +func VMAXSD_SAE(ops ...operand.Op) { ctx.VMAXSD_SAE(ops...) } + +// VMAXSD_SAE_Z: Return Maximum Scalar Double-Precision Floating-Point Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VMAXSD.SAE.Z xmm xmm k xmm +// Construct and append a VMAXSD.SAE.Z instruction to the active function. +func (c *Context) VMAXSD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VMAXSD_SAE_Z(x, x1, k, x2)) +} + +// VMAXSD_SAE_Z: Return Maximum Scalar Double-Precision Floating-Point Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VMAXSD.SAE.Z xmm xmm k xmm +// Construct and append a VMAXSD.SAE.Z instruction to the active function. +// Operates on the global context. +func VMAXSD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VMAXSD_SAE_Z(x, x1, k, x2) } + +// VMAXSD_Z: Return Maximum Scalar Double-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VMAXSD.Z m64 xmm k xmm +// VMAXSD.Z xmm xmm k xmm +// Construct and append a VMAXSD.Z instruction to the active function. +func (c *Context) VMAXSD_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VMAXSD_Z(mx, x, k, x1)) +} + +// VMAXSD_Z: Return Maximum Scalar Double-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VMAXSD.Z m64 xmm k xmm +// VMAXSD.Z xmm xmm k xmm +// Construct and append a VMAXSD.Z instruction to the active function. +// Operates on the global context. +func VMAXSD_Z(mx, x, k, x1 operand.Op) { ctx.VMAXSD_Z(mx, x, k, x1) } + +// VMAXSS: Return Maximum Scalar Single-Precision Floating-Point Value. +// +// Forms: +// +// VMAXSS m32 xmm xmm +// VMAXSS xmm xmm xmm +// VMAXSS m32 xmm k xmm +// VMAXSS xmm xmm k xmm +// Construct and append a VMAXSS instruction to the active function. +func (c *Context) VMAXSS(ops ...operand.Op) { + c.addinstruction(x86.VMAXSS(ops...)) +} + +// VMAXSS: Return Maximum Scalar Single-Precision Floating-Point Value. +// +// Forms: +// +// VMAXSS m32 xmm xmm +// VMAXSS xmm xmm xmm +// VMAXSS m32 xmm k xmm +// VMAXSS xmm xmm k xmm +// Construct and append a VMAXSS instruction to the active function. +// Operates on the global context. +func VMAXSS(ops ...operand.Op) { ctx.VMAXSS(ops...) } + +// VMAXSS_SAE: Return Maximum Scalar Single-Precision Floating-Point Value (Suppress All Exceptions). +// +// Forms: +// +// VMAXSS.SAE xmm xmm k xmm +// VMAXSS.SAE xmm xmm xmm +// Construct and append a VMAXSS.SAE instruction to the active function. +func (c *Context) VMAXSS_SAE(ops ...operand.Op) { + c.addinstruction(x86.VMAXSS_SAE(ops...)) +} + +// VMAXSS_SAE: Return Maximum Scalar Single-Precision Floating-Point Value (Suppress All Exceptions). +// +// Forms: +// +// VMAXSS.SAE xmm xmm k xmm +// VMAXSS.SAE xmm xmm xmm +// Construct and append a VMAXSS.SAE instruction to the active function. +// Operates on the global context. +func VMAXSS_SAE(ops ...operand.Op) { ctx.VMAXSS_SAE(ops...) } + +// VMAXSS_SAE_Z: Return Maximum Scalar Single-Precision Floating-Point Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VMAXSS.SAE.Z xmm xmm k xmm +// Construct and append a VMAXSS.SAE.Z instruction to the active function. +func (c *Context) VMAXSS_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VMAXSS_SAE_Z(x, x1, k, x2)) +} + +// VMAXSS_SAE_Z: Return Maximum Scalar Single-Precision Floating-Point Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VMAXSS.SAE.Z xmm xmm k xmm +// Construct and append a VMAXSS.SAE.Z instruction to the active function. +// Operates on the global context. +func VMAXSS_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VMAXSS_SAE_Z(x, x1, k, x2) } + +// VMAXSS_Z: Return Maximum Scalar Single-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VMAXSS.Z m32 xmm k xmm +// VMAXSS.Z xmm xmm k xmm +// Construct and append a VMAXSS.Z instruction to the active function. +func (c *Context) VMAXSS_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VMAXSS_Z(mx, x, k, x1)) +} + +// VMAXSS_Z: Return Maximum Scalar Single-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VMAXSS.Z m32 xmm k xmm +// VMAXSS.Z xmm xmm k xmm +// Construct and append a VMAXSS.Z instruction to the active function. +// Operates on the global context. +func VMAXSS_Z(mx, x, k, x1 operand.Op) { ctx.VMAXSS_Z(mx, x, k, x1) } + +// VMINPD: Return Minimum Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VMINPD m128 xmm xmm +// VMINPD m256 ymm ymm +// VMINPD xmm xmm xmm +// VMINPD ymm ymm ymm +// VMINPD m128 xmm k xmm +// VMINPD m256 ymm k ymm +// VMINPD xmm xmm k xmm +// VMINPD ymm ymm k ymm +// VMINPD m512 zmm k zmm +// VMINPD m512 zmm zmm +// VMINPD zmm zmm k zmm +// VMINPD zmm zmm zmm +// Construct and append a VMINPD instruction to the active function. +func (c *Context) VMINPD(ops ...operand.Op) { + c.addinstruction(x86.VMINPD(ops...)) +} + +// VMINPD: Return Minimum Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VMINPD m128 xmm xmm +// VMINPD m256 ymm ymm +// VMINPD xmm xmm xmm +// VMINPD ymm ymm ymm +// VMINPD m128 xmm k xmm +// VMINPD m256 ymm k ymm +// VMINPD xmm xmm k xmm +// VMINPD ymm ymm k ymm +// VMINPD m512 zmm k zmm +// VMINPD m512 zmm zmm +// VMINPD zmm zmm k zmm +// VMINPD zmm zmm zmm +// Construct and append a VMINPD instruction to the active function. +// Operates on the global context. +func VMINPD(ops ...operand.Op) { ctx.VMINPD(ops...) } + +// VMINPD_BCST: Return Minimum Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VMINPD.BCST m64 xmm k xmm +// VMINPD.BCST m64 xmm xmm +// VMINPD.BCST m64 ymm k ymm +// VMINPD.BCST m64 ymm ymm +// VMINPD.BCST m64 zmm k zmm +// VMINPD.BCST m64 zmm zmm +// Construct and append a VMINPD.BCST instruction to the active function. +func (c *Context) VMINPD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VMINPD_BCST(ops...)) +} + +// VMINPD_BCST: Return Minimum Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VMINPD.BCST m64 xmm k xmm +// VMINPD.BCST m64 xmm xmm +// VMINPD.BCST m64 ymm k ymm +// VMINPD.BCST m64 ymm ymm +// VMINPD.BCST m64 zmm k zmm +// VMINPD.BCST m64 zmm zmm +// Construct and append a VMINPD.BCST instruction to the active function. +// Operates on the global context. +func VMINPD_BCST(ops ...operand.Op) { ctx.VMINPD_BCST(ops...) } + +// VMINPD_BCST_Z: Return Minimum Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VMINPD.BCST.Z m64 xmm k xmm +// VMINPD.BCST.Z m64 ymm k ymm +// VMINPD.BCST.Z m64 zmm k zmm +// Construct and append a VMINPD.BCST.Z instruction to the active function. +func (c *Context) VMINPD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VMINPD_BCST_Z(m, xyz, k, xyz1)) +} + +// VMINPD_BCST_Z: Return Minimum Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VMINPD.BCST.Z m64 xmm k xmm +// VMINPD.BCST.Z m64 ymm k ymm +// VMINPD.BCST.Z m64 zmm k zmm +// Construct and append a VMINPD.BCST.Z instruction to the active function. +// Operates on the global context. +func VMINPD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VMINPD_BCST_Z(m, xyz, k, xyz1) } + +// VMINPD_SAE: Return Minimum Packed Double-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VMINPD.SAE zmm zmm k zmm +// VMINPD.SAE zmm zmm zmm +// Construct and append a VMINPD.SAE instruction to the active function. +func (c *Context) VMINPD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VMINPD_SAE(ops...)) +} + +// VMINPD_SAE: Return Minimum Packed Double-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VMINPD.SAE zmm zmm k zmm +// VMINPD.SAE zmm zmm zmm +// Construct and append a VMINPD.SAE instruction to the active function. +// Operates on the global context. +func VMINPD_SAE(ops ...operand.Op) { ctx.VMINPD_SAE(ops...) } + +// VMINPD_SAE_Z: Return Minimum Packed Double-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VMINPD.SAE.Z zmm zmm k zmm +// Construct and append a VMINPD.SAE.Z instruction to the active function. +func (c *Context) VMINPD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VMINPD_SAE_Z(z, z1, k, z2)) +} + +// VMINPD_SAE_Z: Return Minimum Packed Double-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VMINPD.SAE.Z zmm zmm k zmm +// Construct and append a VMINPD.SAE.Z instruction to the active function. +// Operates on the global context. +func VMINPD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VMINPD_SAE_Z(z, z1, k, z2) } + +// VMINPD_Z: Return Minimum Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMINPD.Z m128 xmm k xmm +// VMINPD.Z m256 ymm k ymm +// VMINPD.Z xmm xmm k xmm +// VMINPD.Z ymm ymm k ymm +// VMINPD.Z m512 zmm k zmm +// VMINPD.Z zmm zmm k zmm +// Construct and append a VMINPD.Z instruction to the active function. +func (c *Context) VMINPD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VMINPD_Z(mxyz, xyz, k, xyz1)) +} + +// VMINPD_Z: Return Minimum Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMINPD.Z m128 xmm k xmm +// VMINPD.Z m256 ymm k ymm +// VMINPD.Z xmm xmm k xmm +// VMINPD.Z ymm ymm k ymm +// VMINPD.Z m512 zmm k zmm +// VMINPD.Z zmm zmm k zmm +// Construct and append a VMINPD.Z instruction to the active function. +// Operates on the global context. +func VMINPD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VMINPD_Z(mxyz, xyz, k, xyz1) } + +// VMINPS: Return Minimum Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VMINPS m128 xmm xmm +// VMINPS m256 ymm ymm +// VMINPS xmm xmm xmm +// VMINPS ymm ymm ymm +// VMINPS m128 xmm k xmm +// VMINPS m256 ymm k ymm +// VMINPS xmm xmm k xmm +// VMINPS ymm ymm k ymm +// VMINPS m512 zmm k zmm +// VMINPS m512 zmm zmm +// VMINPS zmm zmm k zmm +// VMINPS zmm zmm zmm +// Construct and append a VMINPS instruction to the active function. +func (c *Context) VMINPS(ops ...operand.Op) { + c.addinstruction(x86.VMINPS(ops...)) +} + +// VMINPS: Return Minimum Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VMINPS m128 xmm xmm +// VMINPS m256 ymm ymm +// VMINPS xmm xmm xmm +// VMINPS ymm ymm ymm +// VMINPS m128 xmm k xmm +// VMINPS m256 ymm k ymm +// VMINPS xmm xmm k xmm +// VMINPS ymm ymm k ymm +// VMINPS m512 zmm k zmm +// VMINPS m512 zmm zmm +// VMINPS zmm zmm k zmm +// VMINPS zmm zmm zmm +// Construct and append a VMINPS instruction to the active function. +// Operates on the global context. +func VMINPS(ops ...operand.Op) { ctx.VMINPS(ops...) } + +// VMINPS_BCST: Return Minimum Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VMINPS.BCST m32 xmm k xmm +// VMINPS.BCST m32 xmm xmm +// VMINPS.BCST m32 ymm k ymm +// VMINPS.BCST m32 ymm ymm +// VMINPS.BCST m32 zmm k zmm +// VMINPS.BCST m32 zmm zmm +// Construct and append a VMINPS.BCST instruction to the active function. +func (c *Context) VMINPS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VMINPS_BCST(ops...)) +} + +// VMINPS_BCST: Return Minimum Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VMINPS.BCST m32 xmm k xmm +// VMINPS.BCST m32 xmm xmm +// VMINPS.BCST m32 ymm k ymm +// VMINPS.BCST m32 ymm ymm +// VMINPS.BCST m32 zmm k zmm +// VMINPS.BCST m32 zmm zmm +// Construct and append a VMINPS.BCST instruction to the active function. +// Operates on the global context. +func VMINPS_BCST(ops ...operand.Op) { ctx.VMINPS_BCST(ops...) } + +// VMINPS_BCST_Z: Return Minimum Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VMINPS.BCST.Z m32 xmm k xmm +// VMINPS.BCST.Z m32 ymm k ymm +// VMINPS.BCST.Z m32 zmm k zmm +// Construct and append a VMINPS.BCST.Z instruction to the active function. +func (c *Context) VMINPS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VMINPS_BCST_Z(m, xyz, k, xyz1)) +} + +// VMINPS_BCST_Z: Return Minimum Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VMINPS.BCST.Z m32 xmm k xmm +// VMINPS.BCST.Z m32 ymm k ymm +// VMINPS.BCST.Z m32 zmm k zmm +// Construct and append a VMINPS.BCST.Z instruction to the active function. +// Operates on the global context. +func VMINPS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VMINPS_BCST_Z(m, xyz, k, xyz1) } + +// VMINPS_SAE: Return Minimum Packed Single-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VMINPS.SAE zmm zmm k zmm +// VMINPS.SAE zmm zmm zmm +// Construct and append a VMINPS.SAE instruction to the active function. +func (c *Context) VMINPS_SAE(ops ...operand.Op) { + c.addinstruction(x86.VMINPS_SAE(ops...)) +} + +// VMINPS_SAE: Return Minimum Packed Single-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VMINPS.SAE zmm zmm k zmm +// VMINPS.SAE zmm zmm zmm +// Construct and append a VMINPS.SAE instruction to the active function. +// Operates on the global context. +func VMINPS_SAE(ops ...operand.Op) { ctx.VMINPS_SAE(ops...) } + +// VMINPS_SAE_Z: Return Minimum Packed Single-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VMINPS.SAE.Z zmm zmm k zmm +// Construct and append a VMINPS.SAE.Z instruction to the active function. +func (c *Context) VMINPS_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VMINPS_SAE_Z(z, z1, k, z2)) +} + +// VMINPS_SAE_Z: Return Minimum Packed Single-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VMINPS.SAE.Z zmm zmm k zmm +// Construct and append a VMINPS.SAE.Z instruction to the active function. +// Operates on the global context. +func VMINPS_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VMINPS_SAE_Z(z, z1, k, z2) } + +// VMINPS_Z: Return Minimum Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMINPS.Z m128 xmm k xmm +// VMINPS.Z m256 ymm k ymm +// VMINPS.Z xmm xmm k xmm +// VMINPS.Z ymm ymm k ymm +// VMINPS.Z m512 zmm k zmm +// VMINPS.Z zmm zmm k zmm +// Construct and append a VMINPS.Z instruction to the active function. +func (c *Context) VMINPS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VMINPS_Z(mxyz, xyz, k, xyz1)) +} + +// VMINPS_Z: Return Minimum Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMINPS.Z m128 xmm k xmm +// VMINPS.Z m256 ymm k ymm +// VMINPS.Z xmm xmm k xmm +// VMINPS.Z ymm ymm k ymm +// VMINPS.Z m512 zmm k zmm +// VMINPS.Z zmm zmm k zmm +// Construct and append a VMINPS.Z instruction to the active function. +// Operates on the global context. +func VMINPS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VMINPS_Z(mxyz, xyz, k, xyz1) } + +// VMINSD: Return Minimum Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// VMINSD m64 xmm xmm +// VMINSD xmm xmm xmm +// VMINSD m64 xmm k xmm +// VMINSD xmm xmm k xmm +// Construct and append a VMINSD instruction to the active function. +func (c *Context) VMINSD(ops ...operand.Op) { + c.addinstruction(x86.VMINSD(ops...)) +} + +// VMINSD: Return Minimum Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// VMINSD m64 xmm xmm +// VMINSD xmm xmm xmm +// VMINSD m64 xmm k xmm +// VMINSD xmm xmm k xmm +// Construct and append a VMINSD instruction to the active function. +// Operates on the global context. +func VMINSD(ops ...operand.Op) { ctx.VMINSD(ops...) } + +// VMINSD_SAE: Return Minimum Scalar Double-Precision Floating-Point Value (Suppress All Exceptions). +// +// Forms: +// +// VMINSD.SAE xmm xmm k xmm +// VMINSD.SAE xmm xmm xmm +// Construct and append a VMINSD.SAE instruction to the active function. +func (c *Context) VMINSD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VMINSD_SAE(ops...)) +} + +// VMINSD_SAE: Return Minimum Scalar Double-Precision Floating-Point Value (Suppress All Exceptions). +// +// Forms: +// +// VMINSD.SAE xmm xmm k xmm +// VMINSD.SAE xmm xmm xmm +// Construct and append a VMINSD.SAE instruction to the active function. +// Operates on the global context. +func VMINSD_SAE(ops ...operand.Op) { ctx.VMINSD_SAE(ops...) } + +// VMINSD_SAE_Z: Return Minimum Scalar Double-Precision Floating-Point Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VMINSD.SAE.Z xmm xmm k xmm +// Construct and append a VMINSD.SAE.Z instruction to the active function. +func (c *Context) VMINSD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VMINSD_SAE_Z(x, x1, k, x2)) +} + +// VMINSD_SAE_Z: Return Minimum Scalar Double-Precision Floating-Point Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VMINSD.SAE.Z xmm xmm k xmm +// Construct and append a VMINSD.SAE.Z instruction to the active function. +// Operates on the global context. +func VMINSD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VMINSD_SAE_Z(x, x1, k, x2) } + +// VMINSD_Z: Return Minimum Scalar Double-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VMINSD.Z m64 xmm k xmm +// VMINSD.Z xmm xmm k xmm +// Construct and append a VMINSD.Z instruction to the active function. +func (c *Context) VMINSD_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VMINSD_Z(mx, x, k, x1)) +} + +// VMINSD_Z: Return Minimum Scalar Double-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VMINSD.Z m64 xmm k xmm +// VMINSD.Z xmm xmm k xmm +// Construct and append a VMINSD.Z instruction to the active function. +// Operates on the global context. +func VMINSD_Z(mx, x, k, x1 operand.Op) { ctx.VMINSD_Z(mx, x, k, x1) } + +// VMINSS: Return Minimum Scalar Single-Precision Floating-Point Value. +// +// Forms: +// +// VMINSS m32 xmm xmm +// VMINSS xmm xmm xmm +// VMINSS m32 xmm k xmm +// VMINSS xmm xmm k xmm +// Construct and append a VMINSS instruction to the active function. +func (c *Context) VMINSS(ops ...operand.Op) { + c.addinstruction(x86.VMINSS(ops...)) +} + +// VMINSS: Return Minimum Scalar Single-Precision Floating-Point Value. +// +// Forms: +// +// VMINSS m32 xmm xmm +// VMINSS xmm xmm xmm +// VMINSS m32 xmm k xmm +// VMINSS xmm xmm k xmm +// Construct and append a VMINSS instruction to the active function. +// Operates on the global context. +func VMINSS(ops ...operand.Op) { ctx.VMINSS(ops...) } + +// VMINSS_SAE: Return Minimum Scalar Single-Precision Floating-Point Value (Suppress All Exceptions). +// +// Forms: +// +// VMINSS.SAE xmm xmm k xmm +// VMINSS.SAE xmm xmm xmm +// Construct and append a VMINSS.SAE instruction to the active function. +func (c *Context) VMINSS_SAE(ops ...operand.Op) { + c.addinstruction(x86.VMINSS_SAE(ops...)) +} + +// VMINSS_SAE: Return Minimum Scalar Single-Precision Floating-Point Value (Suppress All Exceptions). +// +// Forms: +// +// VMINSS.SAE xmm xmm k xmm +// VMINSS.SAE xmm xmm xmm +// Construct and append a VMINSS.SAE instruction to the active function. +// Operates on the global context. +func VMINSS_SAE(ops ...operand.Op) { ctx.VMINSS_SAE(ops...) } + +// VMINSS_SAE_Z: Return Minimum Scalar Single-Precision Floating-Point Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VMINSS.SAE.Z xmm xmm k xmm +// Construct and append a VMINSS.SAE.Z instruction to the active function. +func (c *Context) VMINSS_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VMINSS_SAE_Z(x, x1, k, x2)) +} + +// VMINSS_SAE_Z: Return Minimum Scalar Single-Precision Floating-Point Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VMINSS.SAE.Z xmm xmm k xmm +// Construct and append a VMINSS.SAE.Z instruction to the active function. +// Operates on the global context. +func VMINSS_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VMINSS_SAE_Z(x, x1, k, x2) } + +// VMINSS_Z: Return Minimum Scalar Single-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VMINSS.Z m32 xmm k xmm +// VMINSS.Z xmm xmm k xmm +// Construct and append a VMINSS.Z instruction to the active function. +func (c *Context) VMINSS_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VMINSS_Z(mx, x, k, x1)) +} + +// VMINSS_Z: Return Minimum Scalar Single-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VMINSS.Z m32 xmm k xmm +// VMINSS.Z xmm xmm k xmm +// Construct and append a VMINSS.Z instruction to the active function. +// Operates on the global context. +func VMINSS_Z(mx, x, k, x1 operand.Op) { ctx.VMINSS_Z(mx, x, k, x1) } + +// VMOVAPD: Move Aligned Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VMOVAPD m128 xmm +// VMOVAPD m256 ymm +// VMOVAPD xmm m128 +// VMOVAPD xmm xmm +// VMOVAPD ymm m256 +// VMOVAPD ymm ymm +// VMOVAPD m128 k xmm +// VMOVAPD m256 k ymm +// VMOVAPD xmm k m128 +// VMOVAPD xmm k xmm +// VMOVAPD ymm k m256 +// VMOVAPD ymm k ymm +// VMOVAPD m512 k zmm +// VMOVAPD m512 zmm +// VMOVAPD zmm k m512 +// VMOVAPD zmm k zmm +// VMOVAPD zmm m512 +// VMOVAPD zmm zmm +// Construct and append a VMOVAPD instruction to the active function. +func (c *Context) VMOVAPD(ops ...operand.Op) { + c.addinstruction(x86.VMOVAPD(ops...)) +} + +// VMOVAPD: Move Aligned Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VMOVAPD m128 xmm +// VMOVAPD m256 ymm +// VMOVAPD xmm m128 +// VMOVAPD xmm xmm +// VMOVAPD ymm m256 +// VMOVAPD ymm ymm +// VMOVAPD m128 k xmm +// VMOVAPD m256 k ymm +// VMOVAPD xmm k m128 +// VMOVAPD xmm k xmm +// VMOVAPD ymm k m256 +// VMOVAPD ymm k ymm +// VMOVAPD m512 k zmm +// VMOVAPD m512 zmm +// VMOVAPD zmm k m512 +// VMOVAPD zmm k zmm +// VMOVAPD zmm m512 +// VMOVAPD zmm zmm +// Construct and append a VMOVAPD instruction to the active function. +// Operates on the global context. +func VMOVAPD(ops ...operand.Op) { ctx.VMOVAPD(ops...) } + +// VMOVAPD_Z: Move Aligned Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMOVAPD.Z m128 k xmm +// VMOVAPD.Z m256 k ymm +// VMOVAPD.Z xmm k m128 +// VMOVAPD.Z xmm k xmm +// VMOVAPD.Z ymm k m256 +// VMOVAPD.Z ymm k ymm +// VMOVAPD.Z m512 k zmm +// VMOVAPD.Z zmm k m512 +// VMOVAPD.Z zmm k zmm +// Construct and append a VMOVAPD.Z instruction to the active function. +func (c *Context) VMOVAPD_Z(mxyz, k, mxyz1 operand.Op) { + c.addinstruction(x86.VMOVAPD_Z(mxyz, k, mxyz1)) +} + +// VMOVAPD_Z: Move Aligned Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMOVAPD.Z m128 k xmm +// VMOVAPD.Z m256 k ymm +// VMOVAPD.Z xmm k m128 +// VMOVAPD.Z xmm k xmm +// VMOVAPD.Z ymm k m256 +// VMOVAPD.Z ymm k ymm +// VMOVAPD.Z m512 k zmm +// VMOVAPD.Z zmm k m512 +// VMOVAPD.Z zmm k zmm +// Construct and append a VMOVAPD.Z instruction to the active function. +// Operates on the global context. +func VMOVAPD_Z(mxyz, k, mxyz1 operand.Op) { ctx.VMOVAPD_Z(mxyz, k, mxyz1) } + +// VMOVAPS: Move Aligned Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VMOVAPS m128 xmm +// VMOVAPS m256 ymm +// VMOVAPS xmm m128 +// VMOVAPS xmm xmm +// VMOVAPS ymm m256 +// VMOVAPS ymm ymm +// VMOVAPS m128 k xmm +// VMOVAPS m256 k ymm +// VMOVAPS xmm k m128 +// VMOVAPS xmm k xmm +// VMOVAPS ymm k m256 +// VMOVAPS ymm k ymm +// VMOVAPS m512 k zmm +// VMOVAPS m512 zmm +// VMOVAPS zmm k m512 +// VMOVAPS zmm k zmm +// VMOVAPS zmm m512 +// VMOVAPS zmm zmm +// Construct and append a VMOVAPS instruction to the active function. +func (c *Context) VMOVAPS(ops ...operand.Op) { + c.addinstruction(x86.VMOVAPS(ops...)) +} + +// VMOVAPS: Move Aligned Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VMOVAPS m128 xmm +// VMOVAPS m256 ymm +// VMOVAPS xmm m128 +// VMOVAPS xmm xmm +// VMOVAPS ymm m256 +// VMOVAPS ymm ymm +// VMOVAPS m128 k xmm +// VMOVAPS m256 k ymm +// VMOVAPS xmm k m128 +// VMOVAPS xmm k xmm +// VMOVAPS ymm k m256 +// VMOVAPS ymm k ymm +// VMOVAPS m512 k zmm +// VMOVAPS m512 zmm +// VMOVAPS zmm k m512 +// VMOVAPS zmm k zmm +// VMOVAPS zmm m512 +// VMOVAPS zmm zmm +// Construct and append a VMOVAPS instruction to the active function. +// Operates on the global context. +func VMOVAPS(ops ...operand.Op) { ctx.VMOVAPS(ops...) } + +// VMOVAPS_Z: Move Aligned Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMOVAPS.Z m128 k xmm +// VMOVAPS.Z m256 k ymm +// VMOVAPS.Z xmm k m128 +// VMOVAPS.Z xmm k xmm +// VMOVAPS.Z ymm k m256 +// VMOVAPS.Z ymm k ymm +// VMOVAPS.Z m512 k zmm +// VMOVAPS.Z zmm k m512 +// VMOVAPS.Z zmm k zmm +// Construct and append a VMOVAPS.Z instruction to the active function. +func (c *Context) VMOVAPS_Z(mxyz, k, mxyz1 operand.Op) { + c.addinstruction(x86.VMOVAPS_Z(mxyz, k, mxyz1)) +} + +// VMOVAPS_Z: Move Aligned Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMOVAPS.Z m128 k xmm +// VMOVAPS.Z m256 k ymm +// VMOVAPS.Z xmm k m128 +// VMOVAPS.Z xmm k xmm +// VMOVAPS.Z ymm k m256 +// VMOVAPS.Z ymm k ymm +// VMOVAPS.Z m512 k zmm +// VMOVAPS.Z zmm k m512 +// VMOVAPS.Z zmm k zmm +// Construct and append a VMOVAPS.Z instruction to the active function. +// Operates on the global context. +func VMOVAPS_Z(mxyz, k, mxyz1 operand.Op) { ctx.VMOVAPS_Z(mxyz, k, mxyz1) } + +// VMOVD: Move Doubleword. +// +// Forms: +// +// VMOVD m32 xmm +// VMOVD r32 xmm +// VMOVD xmm m32 +// VMOVD xmm r32 +// Construct and append a VMOVD instruction to the active function. +func (c *Context) VMOVD(mrx, mrx1 operand.Op) { + c.addinstruction(x86.VMOVD(mrx, mrx1)) +} + +// VMOVD: Move Doubleword. +// +// Forms: +// +// VMOVD m32 xmm +// VMOVD r32 xmm +// VMOVD xmm m32 +// VMOVD xmm r32 +// Construct and append a VMOVD instruction to the active function. +// Operates on the global context. +func VMOVD(mrx, mrx1 operand.Op) { ctx.VMOVD(mrx, mrx1) } + +// VMOVDDUP: Move One Double-FP and Duplicate. +// +// Forms: +// +// VMOVDDUP m256 ymm +// VMOVDDUP m64 xmm +// VMOVDDUP xmm xmm +// VMOVDDUP ymm ymm +// VMOVDDUP m256 k ymm +// VMOVDDUP m64 k xmm +// VMOVDDUP xmm k xmm +// VMOVDDUP ymm k ymm +// VMOVDDUP m512 k zmm +// VMOVDDUP m512 zmm +// VMOVDDUP zmm k zmm +// VMOVDDUP zmm zmm +// Construct and append a VMOVDDUP instruction to the active function. +func (c *Context) VMOVDDUP(ops ...operand.Op) { + c.addinstruction(x86.VMOVDDUP(ops...)) +} + +// VMOVDDUP: Move One Double-FP and Duplicate. +// +// Forms: +// +// VMOVDDUP m256 ymm +// VMOVDDUP m64 xmm +// VMOVDDUP xmm xmm +// VMOVDDUP ymm ymm +// VMOVDDUP m256 k ymm +// VMOVDDUP m64 k xmm +// VMOVDDUP xmm k xmm +// VMOVDDUP ymm k ymm +// VMOVDDUP m512 k zmm +// VMOVDDUP m512 zmm +// VMOVDDUP zmm k zmm +// VMOVDDUP zmm zmm +// Construct and append a VMOVDDUP instruction to the active function. +// Operates on the global context. +func VMOVDDUP(ops ...operand.Op) { ctx.VMOVDDUP(ops...) } + +// VMOVDDUP_Z: Move One Double-FP and Duplicate (Zeroing Masking). +// +// Forms: +// +// VMOVDDUP.Z m256 k ymm +// VMOVDDUP.Z m64 k xmm +// VMOVDDUP.Z xmm k xmm +// VMOVDDUP.Z ymm k ymm +// VMOVDDUP.Z m512 k zmm +// VMOVDDUP.Z zmm k zmm +// Construct and append a VMOVDDUP.Z instruction to the active function. +func (c *Context) VMOVDDUP_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VMOVDDUP_Z(mxyz, k, xyz)) +} + +// VMOVDDUP_Z: Move One Double-FP and Duplicate (Zeroing Masking). +// +// Forms: +// +// VMOVDDUP.Z m256 k ymm +// VMOVDDUP.Z m64 k xmm +// VMOVDDUP.Z xmm k xmm +// VMOVDDUP.Z ymm k ymm +// VMOVDDUP.Z m512 k zmm +// VMOVDDUP.Z zmm k zmm +// Construct and append a VMOVDDUP.Z instruction to the active function. +// Operates on the global context. +func VMOVDDUP_Z(mxyz, k, xyz operand.Op) { ctx.VMOVDDUP_Z(mxyz, k, xyz) } + +// VMOVDQA: Move Aligned Double Quadword. +// +// Forms: +// +// VMOVDQA m128 xmm +// VMOVDQA m256 ymm +// VMOVDQA xmm m128 +// VMOVDQA xmm xmm +// VMOVDQA ymm m256 +// VMOVDQA ymm ymm +// Construct and append a VMOVDQA instruction to the active function. +func (c *Context) VMOVDQA(mxy, mxy1 operand.Op) { + c.addinstruction(x86.VMOVDQA(mxy, mxy1)) +} + +// VMOVDQA: Move Aligned Double Quadword. +// +// Forms: +// +// VMOVDQA m128 xmm +// VMOVDQA m256 ymm +// VMOVDQA xmm m128 +// VMOVDQA xmm xmm +// VMOVDQA ymm m256 +// VMOVDQA ymm ymm +// Construct and append a VMOVDQA instruction to the active function. +// Operates on the global context. +func VMOVDQA(mxy, mxy1 operand.Op) { ctx.VMOVDQA(mxy, mxy1) } + +// VMOVDQA32: Move Aligned Doubleword Values. +// +// Forms: +// +// VMOVDQA32 m128 k xmm +// VMOVDQA32 m128 xmm +// VMOVDQA32 m256 k ymm +// VMOVDQA32 m256 ymm +// VMOVDQA32 xmm k m128 +// VMOVDQA32 xmm k xmm +// VMOVDQA32 xmm m128 +// VMOVDQA32 xmm xmm +// VMOVDQA32 ymm k m256 +// VMOVDQA32 ymm k ymm +// VMOVDQA32 ymm m256 +// VMOVDQA32 ymm ymm +// VMOVDQA32 m512 k zmm +// VMOVDQA32 m512 zmm +// VMOVDQA32 zmm k m512 +// VMOVDQA32 zmm k zmm +// VMOVDQA32 zmm m512 +// VMOVDQA32 zmm zmm +// Construct and append a VMOVDQA32 instruction to the active function. +func (c *Context) VMOVDQA32(ops ...operand.Op) { + c.addinstruction(x86.VMOVDQA32(ops...)) +} + +// VMOVDQA32: Move Aligned Doubleword Values. +// +// Forms: +// +// VMOVDQA32 m128 k xmm +// VMOVDQA32 m128 xmm +// VMOVDQA32 m256 k ymm +// VMOVDQA32 m256 ymm +// VMOVDQA32 xmm k m128 +// VMOVDQA32 xmm k xmm +// VMOVDQA32 xmm m128 +// VMOVDQA32 xmm xmm +// VMOVDQA32 ymm k m256 +// VMOVDQA32 ymm k ymm +// VMOVDQA32 ymm m256 +// VMOVDQA32 ymm ymm +// VMOVDQA32 m512 k zmm +// VMOVDQA32 m512 zmm +// VMOVDQA32 zmm k m512 +// VMOVDQA32 zmm k zmm +// VMOVDQA32 zmm m512 +// VMOVDQA32 zmm zmm +// Construct and append a VMOVDQA32 instruction to the active function. +// Operates on the global context. +func VMOVDQA32(ops ...operand.Op) { ctx.VMOVDQA32(ops...) } + +// VMOVDQA32_Z: Move Aligned Doubleword Values (Zeroing Masking). +// +// Forms: +// +// VMOVDQA32.Z m128 k xmm +// VMOVDQA32.Z m256 k ymm +// VMOVDQA32.Z xmm k m128 +// VMOVDQA32.Z xmm k xmm +// VMOVDQA32.Z ymm k m256 +// VMOVDQA32.Z ymm k ymm +// VMOVDQA32.Z m512 k zmm +// VMOVDQA32.Z zmm k m512 +// VMOVDQA32.Z zmm k zmm +// Construct and append a VMOVDQA32.Z instruction to the active function. +func (c *Context) VMOVDQA32_Z(mxyz, k, mxyz1 operand.Op) { + c.addinstruction(x86.VMOVDQA32_Z(mxyz, k, mxyz1)) +} + +// VMOVDQA32_Z: Move Aligned Doubleword Values (Zeroing Masking). +// +// Forms: +// +// VMOVDQA32.Z m128 k xmm +// VMOVDQA32.Z m256 k ymm +// VMOVDQA32.Z xmm k m128 +// VMOVDQA32.Z xmm k xmm +// VMOVDQA32.Z ymm k m256 +// VMOVDQA32.Z ymm k ymm +// VMOVDQA32.Z m512 k zmm +// VMOVDQA32.Z zmm k m512 +// VMOVDQA32.Z zmm k zmm +// Construct and append a VMOVDQA32.Z instruction to the active function. +// Operates on the global context. +func VMOVDQA32_Z(mxyz, k, mxyz1 operand.Op) { ctx.VMOVDQA32_Z(mxyz, k, mxyz1) } + +// VMOVDQA64: Move Aligned Quadword Values. +// +// Forms: +// +// VMOVDQA64 m128 k xmm +// VMOVDQA64 m128 xmm +// VMOVDQA64 m256 k ymm +// VMOVDQA64 m256 ymm +// VMOVDQA64 xmm k m128 +// VMOVDQA64 xmm k xmm +// VMOVDQA64 xmm m128 +// VMOVDQA64 xmm xmm +// VMOVDQA64 ymm k m256 +// VMOVDQA64 ymm k ymm +// VMOVDQA64 ymm m256 +// VMOVDQA64 ymm ymm +// VMOVDQA64 m512 k zmm +// VMOVDQA64 m512 zmm +// VMOVDQA64 zmm k m512 +// VMOVDQA64 zmm k zmm +// VMOVDQA64 zmm m512 +// VMOVDQA64 zmm zmm +// Construct and append a VMOVDQA64 instruction to the active function. +func (c *Context) VMOVDQA64(ops ...operand.Op) { + c.addinstruction(x86.VMOVDQA64(ops...)) +} + +// VMOVDQA64: Move Aligned Quadword Values. +// +// Forms: +// +// VMOVDQA64 m128 k xmm +// VMOVDQA64 m128 xmm +// VMOVDQA64 m256 k ymm +// VMOVDQA64 m256 ymm +// VMOVDQA64 xmm k m128 +// VMOVDQA64 xmm k xmm +// VMOVDQA64 xmm m128 +// VMOVDQA64 xmm xmm +// VMOVDQA64 ymm k m256 +// VMOVDQA64 ymm k ymm +// VMOVDQA64 ymm m256 +// VMOVDQA64 ymm ymm +// VMOVDQA64 m512 k zmm +// VMOVDQA64 m512 zmm +// VMOVDQA64 zmm k m512 +// VMOVDQA64 zmm k zmm +// VMOVDQA64 zmm m512 +// VMOVDQA64 zmm zmm +// Construct and append a VMOVDQA64 instruction to the active function. +// Operates on the global context. +func VMOVDQA64(ops ...operand.Op) { ctx.VMOVDQA64(ops...) } + +// VMOVDQA64_Z: Move Aligned Quadword Values (Zeroing Masking). +// +// Forms: +// +// VMOVDQA64.Z m128 k xmm +// VMOVDQA64.Z m256 k ymm +// VMOVDQA64.Z xmm k m128 +// VMOVDQA64.Z xmm k xmm +// VMOVDQA64.Z ymm k m256 +// VMOVDQA64.Z ymm k ymm +// VMOVDQA64.Z m512 k zmm +// VMOVDQA64.Z zmm k m512 +// VMOVDQA64.Z zmm k zmm +// Construct and append a VMOVDQA64.Z instruction to the active function. +func (c *Context) VMOVDQA64_Z(mxyz, k, mxyz1 operand.Op) { + c.addinstruction(x86.VMOVDQA64_Z(mxyz, k, mxyz1)) +} + +// VMOVDQA64_Z: Move Aligned Quadword Values (Zeroing Masking). +// +// Forms: +// +// VMOVDQA64.Z m128 k xmm +// VMOVDQA64.Z m256 k ymm +// VMOVDQA64.Z xmm k m128 +// VMOVDQA64.Z xmm k xmm +// VMOVDQA64.Z ymm k m256 +// VMOVDQA64.Z ymm k ymm +// VMOVDQA64.Z m512 k zmm +// VMOVDQA64.Z zmm k m512 +// VMOVDQA64.Z zmm k zmm +// Construct and append a VMOVDQA64.Z instruction to the active function. +// Operates on the global context. +func VMOVDQA64_Z(mxyz, k, mxyz1 operand.Op) { ctx.VMOVDQA64_Z(mxyz, k, mxyz1) } + +// VMOVDQU: Move Unaligned Double Quadword. +// +// Forms: +// +// VMOVDQU m128 xmm +// VMOVDQU m256 ymm +// VMOVDQU xmm m128 +// VMOVDQU xmm xmm +// VMOVDQU ymm m256 +// VMOVDQU ymm ymm +// Construct and append a VMOVDQU instruction to the active function. +func (c *Context) VMOVDQU(mxy, mxy1 operand.Op) { + c.addinstruction(x86.VMOVDQU(mxy, mxy1)) +} + +// VMOVDQU: Move Unaligned Double Quadword. +// +// Forms: +// +// VMOVDQU m128 xmm +// VMOVDQU m256 ymm +// VMOVDQU xmm m128 +// VMOVDQU xmm xmm +// VMOVDQU ymm m256 +// VMOVDQU ymm ymm +// Construct and append a VMOVDQU instruction to the active function. +// Operates on the global context. +func VMOVDQU(mxy, mxy1 operand.Op) { ctx.VMOVDQU(mxy, mxy1) } + +// VMOVDQU16: Move Unaligned Word Values. +// +// Forms: +// +// VMOVDQU16 m128 k xmm +// VMOVDQU16 m128 xmm +// VMOVDQU16 m256 k ymm +// VMOVDQU16 m256 ymm +// VMOVDQU16 xmm k m128 +// VMOVDQU16 xmm k xmm +// VMOVDQU16 xmm m128 +// VMOVDQU16 xmm xmm +// VMOVDQU16 ymm k m256 +// VMOVDQU16 ymm k ymm +// VMOVDQU16 ymm m256 +// VMOVDQU16 ymm ymm +// VMOVDQU16 m512 k zmm +// VMOVDQU16 m512 zmm +// VMOVDQU16 zmm k m512 +// VMOVDQU16 zmm k zmm +// VMOVDQU16 zmm m512 +// VMOVDQU16 zmm zmm +// Construct and append a VMOVDQU16 instruction to the active function. +func (c *Context) VMOVDQU16(ops ...operand.Op) { + c.addinstruction(x86.VMOVDQU16(ops...)) +} + +// VMOVDQU16: Move Unaligned Word Values. +// +// Forms: +// +// VMOVDQU16 m128 k xmm +// VMOVDQU16 m128 xmm +// VMOVDQU16 m256 k ymm +// VMOVDQU16 m256 ymm +// VMOVDQU16 xmm k m128 +// VMOVDQU16 xmm k xmm +// VMOVDQU16 xmm m128 +// VMOVDQU16 xmm xmm +// VMOVDQU16 ymm k m256 +// VMOVDQU16 ymm k ymm +// VMOVDQU16 ymm m256 +// VMOVDQU16 ymm ymm +// VMOVDQU16 m512 k zmm +// VMOVDQU16 m512 zmm +// VMOVDQU16 zmm k m512 +// VMOVDQU16 zmm k zmm +// VMOVDQU16 zmm m512 +// VMOVDQU16 zmm zmm +// Construct and append a VMOVDQU16 instruction to the active function. +// Operates on the global context. +func VMOVDQU16(ops ...operand.Op) { ctx.VMOVDQU16(ops...) } + +// VMOVDQU16_Z: Move Unaligned Word Values (Zeroing Masking). +// +// Forms: +// +// VMOVDQU16.Z m128 k xmm +// VMOVDQU16.Z m256 k ymm +// VMOVDQU16.Z xmm k m128 +// VMOVDQU16.Z xmm k xmm +// VMOVDQU16.Z ymm k m256 +// VMOVDQU16.Z ymm k ymm +// VMOVDQU16.Z m512 k zmm +// VMOVDQU16.Z zmm k m512 +// VMOVDQU16.Z zmm k zmm +// Construct and append a VMOVDQU16.Z instruction to the active function. +func (c *Context) VMOVDQU16_Z(mxyz, k, mxyz1 operand.Op) { + c.addinstruction(x86.VMOVDQU16_Z(mxyz, k, mxyz1)) +} + +// VMOVDQU16_Z: Move Unaligned Word Values (Zeroing Masking). +// +// Forms: +// +// VMOVDQU16.Z m128 k xmm +// VMOVDQU16.Z m256 k ymm +// VMOVDQU16.Z xmm k m128 +// VMOVDQU16.Z xmm k xmm +// VMOVDQU16.Z ymm k m256 +// VMOVDQU16.Z ymm k ymm +// VMOVDQU16.Z m512 k zmm +// VMOVDQU16.Z zmm k m512 +// VMOVDQU16.Z zmm k zmm +// Construct and append a VMOVDQU16.Z instruction to the active function. +// Operates on the global context. +func VMOVDQU16_Z(mxyz, k, mxyz1 operand.Op) { ctx.VMOVDQU16_Z(mxyz, k, mxyz1) } + +// VMOVDQU32: Move Unaligned Doubleword Values. +// +// Forms: +// +// VMOVDQU32 m128 k xmm +// VMOVDQU32 m128 xmm +// VMOVDQU32 m256 k ymm +// VMOVDQU32 m256 ymm +// VMOVDQU32 xmm k m128 +// VMOVDQU32 xmm k xmm +// VMOVDQU32 xmm m128 +// VMOVDQU32 xmm xmm +// VMOVDQU32 ymm k m256 +// VMOVDQU32 ymm k ymm +// VMOVDQU32 ymm m256 +// VMOVDQU32 ymm ymm +// VMOVDQU32 m512 k zmm +// VMOVDQU32 m512 zmm +// VMOVDQU32 zmm k m512 +// VMOVDQU32 zmm k zmm +// VMOVDQU32 zmm m512 +// VMOVDQU32 zmm zmm +// Construct and append a VMOVDQU32 instruction to the active function. +func (c *Context) VMOVDQU32(ops ...operand.Op) { + c.addinstruction(x86.VMOVDQU32(ops...)) +} + +// VMOVDQU32: Move Unaligned Doubleword Values. +// +// Forms: +// +// VMOVDQU32 m128 k xmm +// VMOVDQU32 m128 xmm +// VMOVDQU32 m256 k ymm +// VMOVDQU32 m256 ymm +// VMOVDQU32 xmm k m128 +// VMOVDQU32 xmm k xmm +// VMOVDQU32 xmm m128 +// VMOVDQU32 xmm xmm +// VMOVDQU32 ymm k m256 +// VMOVDQU32 ymm k ymm +// VMOVDQU32 ymm m256 +// VMOVDQU32 ymm ymm +// VMOVDQU32 m512 k zmm +// VMOVDQU32 m512 zmm +// VMOVDQU32 zmm k m512 +// VMOVDQU32 zmm k zmm +// VMOVDQU32 zmm m512 +// VMOVDQU32 zmm zmm +// Construct and append a VMOVDQU32 instruction to the active function. +// Operates on the global context. +func VMOVDQU32(ops ...operand.Op) { ctx.VMOVDQU32(ops...) } + +// VMOVDQU32_Z: Move Unaligned Doubleword Values (Zeroing Masking). +// +// Forms: +// +// VMOVDQU32.Z m128 k xmm +// VMOVDQU32.Z m256 k ymm +// VMOVDQU32.Z xmm k m128 +// VMOVDQU32.Z xmm k xmm +// VMOVDQU32.Z ymm k m256 +// VMOVDQU32.Z ymm k ymm +// VMOVDQU32.Z m512 k zmm +// VMOVDQU32.Z zmm k m512 +// VMOVDQU32.Z zmm k zmm +// Construct and append a VMOVDQU32.Z instruction to the active function. +func (c *Context) VMOVDQU32_Z(mxyz, k, mxyz1 operand.Op) { + c.addinstruction(x86.VMOVDQU32_Z(mxyz, k, mxyz1)) +} + +// VMOVDQU32_Z: Move Unaligned Doubleword Values (Zeroing Masking). +// +// Forms: +// +// VMOVDQU32.Z m128 k xmm +// VMOVDQU32.Z m256 k ymm +// VMOVDQU32.Z xmm k m128 +// VMOVDQU32.Z xmm k xmm +// VMOVDQU32.Z ymm k m256 +// VMOVDQU32.Z ymm k ymm +// VMOVDQU32.Z m512 k zmm +// VMOVDQU32.Z zmm k m512 +// VMOVDQU32.Z zmm k zmm +// Construct and append a VMOVDQU32.Z instruction to the active function. +// Operates on the global context. +func VMOVDQU32_Z(mxyz, k, mxyz1 operand.Op) { ctx.VMOVDQU32_Z(mxyz, k, mxyz1) } + +// VMOVDQU64: Move Unaligned Quadword Values. +// +// Forms: +// +// VMOVDQU64 m128 k xmm +// VMOVDQU64 m128 xmm +// VMOVDQU64 m256 k ymm +// VMOVDQU64 m256 ymm +// VMOVDQU64 xmm k m128 +// VMOVDQU64 xmm k xmm +// VMOVDQU64 xmm m128 +// VMOVDQU64 xmm xmm +// VMOVDQU64 ymm k m256 +// VMOVDQU64 ymm k ymm +// VMOVDQU64 ymm m256 +// VMOVDQU64 ymm ymm +// VMOVDQU64 m512 k zmm +// VMOVDQU64 m512 zmm +// VMOVDQU64 zmm k m512 +// VMOVDQU64 zmm k zmm +// VMOVDQU64 zmm m512 +// VMOVDQU64 zmm zmm +// Construct and append a VMOVDQU64 instruction to the active function. +func (c *Context) VMOVDQU64(ops ...operand.Op) { + c.addinstruction(x86.VMOVDQU64(ops...)) +} + +// VMOVDQU64: Move Unaligned Quadword Values. +// +// Forms: +// +// VMOVDQU64 m128 k xmm +// VMOVDQU64 m128 xmm +// VMOVDQU64 m256 k ymm +// VMOVDQU64 m256 ymm +// VMOVDQU64 xmm k m128 +// VMOVDQU64 xmm k xmm +// VMOVDQU64 xmm m128 +// VMOVDQU64 xmm xmm +// VMOVDQU64 ymm k m256 +// VMOVDQU64 ymm k ymm +// VMOVDQU64 ymm m256 +// VMOVDQU64 ymm ymm +// VMOVDQU64 m512 k zmm +// VMOVDQU64 m512 zmm +// VMOVDQU64 zmm k m512 +// VMOVDQU64 zmm k zmm +// VMOVDQU64 zmm m512 +// VMOVDQU64 zmm zmm +// Construct and append a VMOVDQU64 instruction to the active function. +// Operates on the global context. +func VMOVDQU64(ops ...operand.Op) { ctx.VMOVDQU64(ops...) } + +// VMOVDQU64_Z: Move Unaligned Quadword Values (Zeroing Masking). +// +// Forms: +// +// VMOVDQU64.Z m128 k xmm +// VMOVDQU64.Z m256 k ymm +// VMOVDQU64.Z xmm k m128 +// VMOVDQU64.Z xmm k xmm +// VMOVDQU64.Z ymm k m256 +// VMOVDQU64.Z ymm k ymm +// VMOVDQU64.Z m512 k zmm +// VMOVDQU64.Z zmm k m512 +// VMOVDQU64.Z zmm k zmm +// Construct and append a VMOVDQU64.Z instruction to the active function. +func (c *Context) VMOVDQU64_Z(mxyz, k, mxyz1 operand.Op) { + c.addinstruction(x86.VMOVDQU64_Z(mxyz, k, mxyz1)) +} + +// VMOVDQU64_Z: Move Unaligned Quadword Values (Zeroing Masking). +// +// Forms: +// +// VMOVDQU64.Z m128 k xmm +// VMOVDQU64.Z m256 k ymm +// VMOVDQU64.Z xmm k m128 +// VMOVDQU64.Z xmm k xmm +// VMOVDQU64.Z ymm k m256 +// VMOVDQU64.Z ymm k ymm +// VMOVDQU64.Z m512 k zmm +// VMOVDQU64.Z zmm k m512 +// VMOVDQU64.Z zmm k zmm +// Construct and append a VMOVDQU64.Z instruction to the active function. +// Operates on the global context. +func VMOVDQU64_Z(mxyz, k, mxyz1 operand.Op) { ctx.VMOVDQU64_Z(mxyz, k, mxyz1) } + +// VMOVDQU8: Move Unaligned Byte Values. +// +// Forms: +// +// VMOVDQU8 m128 k xmm +// VMOVDQU8 m128 xmm +// VMOVDQU8 m256 k ymm +// VMOVDQU8 m256 ymm +// VMOVDQU8 xmm k m128 +// VMOVDQU8 xmm k xmm +// VMOVDQU8 xmm m128 +// VMOVDQU8 xmm xmm +// VMOVDQU8 ymm k m256 +// VMOVDQU8 ymm k ymm +// VMOVDQU8 ymm m256 +// VMOVDQU8 ymm ymm +// VMOVDQU8 m512 k zmm +// VMOVDQU8 m512 zmm +// VMOVDQU8 zmm k m512 +// VMOVDQU8 zmm k zmm +// VMOVDQU8 zmm m512 +// VMOVDQU8 zmm zmm +// Construct and append a VMOVDQU8 instruction to the active function. +func (c *Context) VMOVDQU8(ops ...operand.Op) { + c.addinstruction(x86.VMOVDQU8(ops...)) +} + +// VMOVDQU8: Move Unaligned Byte Values. +// +// Forms: +// +// VMOVDQU8 m128 k xmm +// VMOVDQU8 m128 xmm +// VMOVDQU8 m256 k ymm +// VMOVDQU8 m256 ymm +// VMOVDQU8 xmm k m128 +// VMOVDQU8 xmm k xmm +// VMOVDQU8 xmm m128 +// VMOVDQU8 xmm xmm +// VMOVDQU8 ymm k m256 +// VMOVDQU8 ymm k ymm +// VMOVDQU8 ymm m256 +// VMOVDQU8 ymm ymm +// VMOVDQU8 m512 k zmm +// VMOVDQU8 m512 zmm +// VMOVDQU8 zmm k m512 +// VMOVDQU8 zmm k zmm +// VMOVDQU8 zmm m512 +// VMOVDQU8 zmm zmm +// Construct and append a VMOVDQU8 instruction to the active function. +// Operates on the global context. +func VMOVDQU8(ops ...operand.Op) { ctx.VMOVDQU8(ops...) } + +// VMOVDQU8_Z: Move Unaligned Byte Values (Zeroing Masking). +// +// Forms: +// +// VMOVDQU8.Z m128 k xmm +// VMOVDQU8.Z m256 k ymm +// VMOVDQU8.Z xmm k m128 +// VMOVDQU8.Z xmm k xmm +// VMOVDQU8.Z ymm k m256 +// VMOVDQU8.Z ymm k ymm +// VMOVDQU8.Z m512 k zmm +// VMOVDQU8.Z zmm k m512 +// VMOVDQU8.Z zmm k zmm +// Construct and append a VMOVDQU8.Z instruction to the active function. +func (c *Context) VMOVDQU8_Z(mxyz, k, mxyz1 operand.Op) { + c.addinstruction(x86.VMOVDQU8_Z(mxyz, k, mxyz1)) +} + +// VMOVDQU8_Z: Move Unaligned Byte Values (Zeroing Masking). +// +// Forms: +// +// VMOVDQU8.Z m128 k xmm +// VMOVDQU8.Z m256 k ymm +// VMOVDQU8.Z xmm k m128 +// VMOVDQU8.Z xmm k xmm +// VMOVDQU8.Z ymm k m256 +// VMOVDQU8.Z ymm k ymm +// VMOVDQU8.Z m512 k zmm +// VMOVDQU8.Z zmm k m512 +// VMOVDQU8.Z zmm k zmm +// Construct and append a VMOVDQU8.Z instruction to the active function. +// Operates on the global context. +func VMOVDQU8_Z(mxyz, k, mxyz1 operand.Op) { ctx.VMOVDQU8_Z(mxyz, k, mxyz1) } + +// VMOVHLPS: Move Packed Single-Precision Floating-Point Values High to Low. +// +// Forms: +// +// VMOVHLPS xmm xmm xmm +// Construct and append a VMOVHLPS instruction to the active function. +func (c *Context) VMOVHLPS(x, x1, x2 operand.Op) { + c.addinstruction(x86.VMOVHLPS(x, x1, x2)) +} + +// VMOVHLPS: Move Packed Single-Precision Floating-Point Values High to Low. +// +// Forms: +// +// VMOVHLPS xmm xmm xmm +// Construct and append a VMOVHLPS instruction to the active function. +// Operates on the global context. +func VMOVHLPS(x, x1, x2 operand.Op) { ctx.VMOVHLPS(x, x1, x2) } + +// VMOVHPD: Move High Packed Double-Precision Floating-Point Value. +// +// Forms: +// +// VMOVHPD m64 xmm xmm +// VMOVHPD xmm m64 +// Construct and append a VMOVHPD instruction to the active function. +func (c *Context) VMOVHPD(ops ...operand.Op) { + c.addinstruction(x86.VMOVHPD(ops...)) +} + +// VMOVHPD: Move High Packed Double-Precision Floating-Point Value. +// +// Forms: +// +// VMOVHPD m64 xmm xmm +// VMOVHPD xmm m64 +// Construct and append a VMOVHPD instruction to the active function. +// Operates on the global context. +func VMOVHPD(ops ...operand.Op) { ctx.VMOVHPD(ops...) } + +// VMOVHPS: Move High Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VMOVHPS m64 xmm xmm +// VMOVHPS xmm m64 +// Construct and append a VMOVHPS instruction to the active function. +func (c *Context) VMOVHPS(ops ...operand.Op) { + c.addinstruction(x86.VMOVHPS(ops...)) +} + +// VMOVHPS: Move High Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VMOVHPS m64 xmm xmm +// VMOVHPS xmm m64 +// Construct and append a VMOVHPS instruction to the active function. +// Operates on the global context. +func VMOVHPS(ops ...operand.Op) { ctx.VMOVHPS(ops...) } + +// VMOVLHPS: Move Packed Single-Precision Floating-Point Values Low to High. +// +// Forms: +// +// VMOVLHPS xmm xmm xmm +// Construct and append a VMOVLHPS instruction to the active function. +func (c *Context) VMOVLHPS(x, x1, x2 operand.Op) { + c.addinstruction(x86.VMOVLHPS(x, x1, x2)) +} + +// VMOVLHPS: Move Packed Single-Precision Floating-Point Values Low to High. +// +// Forms: +// +// VMOVLHPS xmm xmm xmm +// Construct and append a VMOVLHPS instruction to the active function. +// Operates on the global context. +func VMOVLHPS(x, x1, x2 operand.Op) { ctx.VMOVLHPS(x, x1, x2) } + +// VMOVLPD: Move Low Packed Double-Precision Floating-Point Value. +// +// Forms: +// +// VMOVLPD m64 xmm xmm +// VMOVLPD xmm m64 +// Construct and append a VMOVLPD instruction to the active function. +func (c *Context) VMOVLPD(ops ...operand.Op) { + c.addinstruction(x86.VMOVLPD(ops...)) +} + +// VMOVLPD: Move Low Packed Double-Precision Floating-Point Value. +// +// Forms: +// +// VMOVLPD m64 xmm xmm +// VMOVLPD xmm m64 +// Construct and append a VMOVLPD instruction to the active function. +// Operates on the global context. +func VMOVLPD(ops ...operand.Op) { ctx.VMOVLPD(ops...) } + +// VMOVLPS: Move Low Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VMOVLPS m64 xmm xmm +// VMOVLPS xmm m64 +// Construct and append a VMOVLPS instruction to the active function. +func (c *Context) VMOVLPS(ops ...operand.Op) { + c.addinstruction(x86.VMOVLPS(ops...)) +} + +// VMOVLPS: Move Low Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VMOVLPS m64 xmm xmm +// VMOVLPS xmm m64 +// Construct and append a VMOVLPS instruction to the active function. +// Operates on the global context. +func VMOVLPS(ops ...operand.Op) { ctx.VMOVLPS(ops...) } + +// VMOVMSKPD: Extract Packed Double-Precision Floating-Point Sign Mask. +// +// Forms: +// +// VMOVMSKPD xmm r32 +// VMOVMSKPD ymm r32 +// Construct and append a VMOVMSKPD instruction to the active function. +func (c *Context) VMOVMSKPD(xy, r operand.Op) { + c.addinstruction(x86.VMOVMSKPD(xy, r)) +} + +// VMOVMSKPD: Extract Packed Double-Precision Floating-Point Sign Mask. +// +// Forms: +// +// VMOVMSKPD xmm r32 +// VMOVMSKPD ymm r32 +// Construct and append a VMOVMSKPD instruction to the active function. +// Operates on the global context. +func VMOVMSKPD(xy, r operand.Op) { ctx.VMOVMSKPD(xy, r) } + +// VMOVMSKPS: Extract Packed Single-Precision Floating-Point Sign Mask. +// +// Forms: +// +// VMOVMSKPS xmm r32 +// VMOVMSKPS ymm r32 +// Construct and append a VMOVMSKPS instruction to the active function. +func (c *Context) VMOVMSKPS(xy, r operand.Op) { + c.addinstruction(x86.VMOVMSKPS(xy, r)) +} + +// VMOVMSKPS: Extract Packed Single-Precision Floating-Point Sign Mask. +// +// Forms: +// +// VMOVMSKPS xmm r32 +// VMOVMSKPS ymm r32 +// Construct and append a VMOVMSKPS instruction to the active function. +// Operates on the global context. +func VMOVMSKPS(xy, r operand.Op) { ctx.VMOVMSKPS(xy, r) } + +// VMOVNTDQ: Store Double Quadword Using Non-Temporal Hint. +// +// Forms: +// +// VMOVNTDQ xmm m128 +// VMOVNTDQ ymm m256 +// VMOVNTDQ zmm m512 +// Construct and append a VMOVNTDQ instruction to the active function. +func (c *Context) VMOVNTDQ(xyz, m operand.Op) { + c.addinstruction(x86.VMOVNTDQ(xyz, m)) +} + +// VMOVNTDQ: Store Double Quadword Using Non-Temporal Hint. +// +// Forms: +// +// VMOVNTDQ xmm m128 +// VMOVNTDQ ymm m256 +// VMOVNTDQ zmm m512 +// Construct and append a VMOVNTDQ instruction to the active function. +// Operates on the global context. +func VMOVNTDQ(xyz, m operand.Op) { ctx.VMOVNTDQ(xyz, m) } + +// VMOVNTDQA: Load Double Quadword Non-Temporal Aligned Hint. +// +// Forms: +// +// VMOVNTDQA m256 ymm +// VMOVNTDQA m128 xmm +// VMOVNTDQA m512 zmm +// Construct and append a VMOVNTDQA instruction to the active function. +func (c *Context) VMOVNTDQA(m, xyz operand.Op) { + c.addinstruction(x86.VMOVNTDQA(m, xyz)) +} + +// VMOVNTDQA: Load Double Quadword Non-Temporal Aligned Hint. +// +// Forms: +// +// VMOVNTDQA m256 ymm +// VMOVNTDQA m128 xmm +// VMOVNTDQA m512 zmm +// Construct and append a VMOVNTDQA instruction to the active function. +// Operates on the global context. +func VMOVNTDQA(m, xyz operand.Op) { ctx.VMOVNTDQA(m, xyz) } + +// VMOVNTPD: Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint. +// +// Forms: +// +// VMOVNTPD xmm m128 +// VMOVNTPD ymm m256 +// VMOVNTPD zmm m512 +// Construct and append a VMOVNTPD instruction to the active function. +func (c *Context) VMOVNTPD(xyz, m operand.Op) { + c.addinstruction(x86.VMOVNTPD(xyz, m)) +} + +// VMOVNTPD: Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint. +// +// Forms: +// +// VMOVNTPD xmm m128 +// VMOVNTPD ymm m256 +// VMOVNTPD zmm m512 +// Construct and append a VMOVNTPD instruction to the active function. +// Operates on the global context. +func VMOVNTPD(xyz, m operand.Op) { ctx.VMOVNTPD(xyz, m) } + +// VMOVNTPS: Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint. +// +// Forms: +// +// VMOVNTPS xmm m128 +// VMOVNTPS ymm m256 +// VMOVNTPS zmm m512 +// Construct and append a VMOVNTPS instruction to the active function. +func (c *Context) VMOVNTPS(xyz, m operand.Op) { + c.addinstruction(x86.VMOVNTPS(xyz, m)) +} + +// VMOVNTPS: Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint. +// +// Forms: +// +// VMOVNTPS xmm m128 +// VMOVNTPS ymm m256 +// VMOVNTPS zmm m512 +// Construct and append a VMOVNTPS instruction to the active function. +// Operates on the global context. +func VMOVNTPS(xyz, m operand.Op) { ctx.VMOVNTPS(xyz, m) } + +// VMOVQ: Move Quadword. +// +// Forms: +// +// VMOVQ m64 xmm +// VMOVQ r64 xmm +// VMOVQ xmm m64 +// VMOVQ xmm r64 +// VMOVQ xmm xmm +// Construct and append a VMOVQ instruction to the active function. +func (c *Context) VMOVQ(mrx, mrx1 operand.Op) { + c.addinstruction(x86.VMOVQ(mrx, mrx1)) +} + +// VMOVQ: Move Quadword. +// +// Forms: +// +// VMOVQ m64 xmm +// VMOVQ r64 xmm +// VMOVQ xmm m64 +// VMOVQ xmm r64 +// VMOVQ xmm xmm +// Construct and append a VMOVQ instruction to the active function. +// Operates on the global context. +func VMOVQ(mrx, mrx1 operand.Op) { ctx.VMOVQ(mrx, mrx1) } + +// VMOVSD: Move Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// VMOVSD m64 xmm +// VMOVSD xmm m64 +// VMOVSD xmm xmm xmm +// VMOVSD m64 k xmm +// VMOVSD xmm k m64 +// VMOVSD xmm xmm k xmm +// Construct and append a VMOVSD instruction to the active function. +func (c *Context) VMOVSD(ops ...operand.Op) { + c.addinstruction(x86.VMOVSD(ops...)) +} + +// VMOVSD: Move Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// VMOVSD m64 xmm +// VMOVSD xmm m64 +// VMOVSD xmm xmm xmm +// VMOVSD m64 k xmm +// VMOVSD xmm k m64 +// VMOVSD xmm xmm k xmm +// Construct and append a VMOVSD instruction to the active function. +// Operates on the global context. +func VMOVSD(ops ...operand.Op) { ctx.VMOVSD(ops...) } + +// VMOVSD_Z: Move Scalar Double-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VMOVSD.Z m64 k xmm +// VMOVSD.Z xmm xmm k xmm +// Construct and append a VMOVSD.Z instruction to the active function. +func (c *Context) VMOVSD_Z(ops ...operand.Op) { + c.addinstruction(x86.VMOVSD_Z(ops...)) +} + +// VMOVSD_Z: Move Scalar Double-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VMOVSD.Z m64 k xmm +// VMOVSD.Z xmm xmm k xmm +// Construct and append a VMOVSD.Z instruction to the active function. +// Operates on the global context. +func VMOVSD_Z(ops ...operand.Op) { ctx.VMOVSD_Z(ops...) } + +// VMOVSHDUP: Move Packed Single-FP High and Duplicate. +// +// Forms: +// +// VMOVSHDUP m128 xmm +// VMOVSHDUP m256 ymm +// VMOVSHDUP xmm xmm +// VMOVSHDUP ymm ymm +// VMOVSHDUP m128 k xmm +// VMOVSHDUP m256 k ymm +// VMOVSHDUP xmm k xmm +// VMOVSHDUP ymm k ymm +// VMOVSHDUP m512 k zmm +// VMOVSHDUP m512 zmm +// VMOVSHDUP zmm k zmm +// VMOVSHDUP zmm zmm +// Construct and append a VMOVSHDUP instruction to the active function. +func (c *Context) VMOVSHDUP(ops ...operand.Op) { + c.addinstruction(x86.VMOVSHDUP(ops...)) +} + +// VMOVSHDUP: Move Packed Single-FP High and Duplicate. +// +// Forms: +// +// VMOVSHDUP m128 xmm +// VMOVSHDUP m256 ymm +// VMOVSHDUP xmm xmm +// VMOVSHDUP ymm ymm +// VMOVSHDUP m128 k xmm +// VMOVSHDUP m256 k ymm +// VMOVSHDUP xmm k xmm +// VMOVSHDUP ymm k ymm +// VMOVSHDUP m512 k zmm +// VMOVSHDUP m512 zmm +// VMOVSHDUP zmm k zmm +// VMOVSHDUP zmm zmm +// Construct and append a VMOVSHDUP instruction to the active function. +// Operates on the global context. +func VMOVSHDUP(ops ...operand.Op) { ctx.VMOVSHDUP(ops...) } + +// VMOVSHDUP_Z: Move Packed Single-FP High and Duplicate (Zeroing Masking). +// +// Forms: +// +// VMOVSHDUP.Z m128 k xmm +// VMOVSHDUP.Z m256 k ymm +// VMOVSHDUP.Z xmm k xmm +// VMOVSHDUP.Z ymm k ymm +// VMOVSHDUP.Z m512 k zmm +// VMOVSHDUP.Z zmm k zmm +// Construct and append a VMOVSHDUP.Z instruction to the active function. +func (c *Context) VMOVSHDUP_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VMOVSHDUP_Z(mxyz, k, xyz)) +} + +// VMOVSHDUP_Z: Move Packed Single-FP High and Duplicate (Zeroing Masking). +// +// Forms: +// +// VMOVSHDUP.Z m128 k xmm +// VMOVSHDUP.Z m256 k ymm +// VMOVSHDUP.Z xmm k xmm +// VMOVSHDUP.Z ymm k ymm +// VMOVSHDUP.Z m512 k zmm +// VMOVSHDUP.Z zmm k zmm +// Construct and append a VMOVSHDUP.Z instruction to the active function. +// Operates on the global context. +func VMOVSHDUP_Z(mxyz, k, xyz operand.Op) { ctx.VMOVSHDUP_Z(mxyz, k, xyz) } + +// VMOVSLDUP: Move Packed Single-FP Low and Duplicate. +// +// Forms: +// +// VMOVSLDUP m128 xmm +// VMOVSLDUP m256 ymm +// VMOVSLDUP xmm xmm +// VMOVSLDUP ymm ymm +// VMOVSLDUP m128 k xmm +// VMOVSLDUP m256 k ymm +// VMOVSLDUP xmm k xmm +// VMOVSLDUP ymm k ymm +// VMOVSLDUP m512 k zmm +// VMOVSLDUP m512 zmm +// VMOVSLDUP zmm k zmm +// VMOVSLDUP zmm zmm +// Construct and append a VMOVSLDUP instruction to the active function. +func (c *Context) VMOVSLDUP(ops ...operand.Op) { + c.addinstruction(x86.VMOVSLDUP(ops...)) +} + +// VMOVSLDUP: Move Packed Single-FP Low and Duplicate. +// +// Forms: +// +// VMOVSLDUP m128 xmm +// VMOVSLDUP m256 ymm +// VMOVSLDUP xmm xmm +// VMOVSLDUP ymm ymm +// VMOVSLDUP m128 k xmm +// VMOVSLDUP m256 k ymm +// VMOVSLDUP xmm k xmm +// VMOVSLDUP ymm k ymm +// VMOVSLDUP m512 k zmm +// VMOVSLDUP m512 zmm +// VMOVSLDUP zmm k zmm +// VMOVSLDUP zmm zmm +// Construct and append a VMOVSLDUP instruction to the active function. +// Operates on the global context. +func VMOVSLDUP(ops ...operand.Op) { ctx.VMOVSLDUP(ops...) } + +// VMOVSLDUP_Z: Move Packed Single-FP Low and Duplicate (Zeroing Masking). +// +// Forms: +// +// VMOVSLDUP.Z m128 k xmm +// VMOVSLDUP.Z m256 k ymm +// VMOVSLDUP.Z xmm k xmm +// VMOVSLDUP.Z ymm k ymm +// VMOVSLDUP.Z m512 k zmm +// VMOVSLDUP.Z zmm k zmm +// Construct and append a VMOVSLDUP.Z instruction to the active function. +func (c *Context) VMOVSLDUP_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VMOVSLDUP_Z(mxyz, k, xyz)) +} + +// VMOVSLDUP_Z: Move Packed Single-FP Low and Duplicate (Zeroing Masking). +// +// Forms: +// +// VMOVSLDUP.Z m128 k xmm +// VMOVSLDUP.Z m256 k ymm +// VMOVSLDUP.Z xmm k xmm +// VMOVSLDUP.Z ymm k ymm +// VMOVSLDUP.Z m512 k zmm +// VMOVSLDUP.Z zmm k zmm +// Construct and append a VMOVSLDUP.Z instruction to the active function. +// Operates on the global context. +func VMOVSLDUP_Z(mxyz, k, xyz operand.Op) { ctx.VMOVSLDUP_Z(mxyz, k, xyz) } + +// VMOVSS: Move Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VMOVSS m32 xmm +// VMOVSS xmm m32 +// VMOVSS xmm xmm xmm +// VMOVSS m32 k xmm +// VMOVSS xmm k m32 +// VMOVSS xmm xmm k xmm +// Construct and append a VMOVSS instruction to the active function. +func (c *Context) VMOVSS(ops ...operand.Op) { + c.addinstruction(x86.VMOVSS(ops...)) +} + +// VMOVSS: Move Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VMOVSS m32 xmm +// VMOVSS xmm m32 +// VMOVSS xmm xmm xmm +// VMOVSS m32 k xmm +// VMOVSS xmm k m32 +// VMOVSS xmm xmm k xmm +// Construct and append a VMOVSS instruction to the active function. +// Operates on the global context. +func VMOVSS(ops ...operand.Op) { ctx.VMOVSS(ops...) } + +// VMOVSS_Z: Move Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMOVSS.Z m32 k xmm +// VMOVSS.Z xmm xmm k xmm +// Construct and append a VMOVSS.Z instruction to the active function. +func (c *Context) VMOVSS_Z(ops ...operand.Op) { + c.addinstruction(x86.VMOVSS_Z(ops...)) +} + +// VMOVSS_Z: Move Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMOVSS.Z m32 k xmm +// VMOVSS.Z xmm xmm k xmm +// Construct and append a VMOVSS.Z instruction to the active function. +// Operates on the global context. +func VMOVSS_Z(ops ...operand.Op) { ctx.VMOVSS_Z(ops...) } + +// VMOVUPD: Move Unaligned Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VMOVUPD m128 xmm +// VMOVUPD m256 ymm +// VMOVUPD xmm m128 +// VMOVUPD xmm xmm +// VMOVUPD ymm m256 +// VMOVUPD ymm ymm +// VMOVUPD m128 k xmm +// VMOVUPD m256 k ymm +// VMOVUPD xmm k m128 +// VMOVUPD xmm k xmm +// VMOVUPD ymm k m256 +// VMOVUPD ymm k ymm +// VMOVUPD m512 k zmm +// VMOVUPD m512 zmm +// VMOVUPD zmm k m512 +// VMOVUPD zmm k zmm +// VMOVUPD zmm m512 +// VMOVUPD zmm zmm +// Construct and append a VMOVUPD instruction to the active function. +func (c *Context) VMOVUPD(ops ...operand.Op) { + c.addinstruction(x86.VMOVUPD(ops...)) +} + +// VMOVUPD: Move Unaligned Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VMOVUPD m128 xmm +// VMOVUPD m256 ymm +// VMOVUPD xmm m128 +// VMOVUPD xmm xmm +// VMOVUPD ymm m256 +// VMOVUPD ymm ymm +// VMOVUPD m128 k xmm +// VMOVUPD m256 k ymm +// VMOVUPD xmm k m128 +// VMOVUPD xmm k xmm +// VMOVUPD ymm k m256 +// VMOVUPD ymm k ymm +// VMOVUPD m512 k zmm +// VMOVUPD m512 zmm +// VMOVUPD zmm k m512 +// VMOVUPD zmm k zmm +// VMOVUPD zmm m512 +// VMOVUPD zmm zmm +// Construct and append a VMOVUPD instruction to the active function. +// Operates on the global context. +func VMOVUPD(ops ...operand.Op) { ctx.VMOVUPD(ops...) } + +// VMOVUPD_Z: Move Unaligned Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMOVUPD.Z m128 k xmm +// VMOVUPD.Z m256 k ymm +// VMOVUPD.Z xmm k m128 +// VMOVUPD.Z xmm k xmm +// VMOVUPD.Z ymm k m256 +// VMOVUPD.Z ymm k ymm +// VMOVUPD.Z m512 k zmm +// VMOVUPD.Z zmm k m512 +// VMOVUPD.Z zmm k zmm +// Construct and append a VMOVUPD.Z instruction to the active function. +func (c *Context) VMOVUPD_Z(mxyz, k, mxyz1 operand.Op) { + c.addinstruction(x86.VMOVUPD_Z(mxyz, k, mxyz1)) +} + +// VMOVUPD_Z: Move Unaligned Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMOVUPD.Z m128 k xmm +// VMOVUPD.Z m256 k ymm +// VMOVUPD.Z xmm k m128 +// VMOVUPD.Z xmm k xmm +// VMOVUPD.Z ymm k m256 +// VMOVUPD.Z ymm k ymm +// VMOVUPD.Z m512 k zmm +// VMOVUPD.Z zmm k m512 +// VMOVUPD.Z zmm k zmm +// Construct and append a VMOVUPD.Z instruction to the active function. +// Operates on the global context. +func VMOVUPD_Z(mxyz, k, mxyz1 operand.Op) { ctx.VMOVUPD_Z(mxyz, k, mxyz1) } + +// VMOVUPS: Move Unaligned Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VMOVUPS m128 xmm +// VMOVUPS m256 ymm +// VMOVUPS xmm m128 +// VMOVUPS xmm xmm +// VMOVUPS ymm m256 +// VMOVUPS ymm ymm +// VMOVUPS m128 k xmm +// VMOVUPS m256 k ymm +// VMOVUPS xmm k m128 +// VMOVUPS xmm k xmm +// VMOVUPS ymm k m256 +// VMOVUPS ymm k ymm +// VMOVUPS m512 k zmm +// VMOVUPS m512 zmm +// VMOVUPS zmm k m512 +// VMOVUPS zmm k zmm +// VMOVUPS zmm m512 +// VMOVUPS zmm zmm +// Construct and append a VMOVUPS instruction to the active function. +func (c *Context) VMOVUPS(ops ...operand.Op) { + c.addinstruction(x86.VMOVUPS(ops...)) +} + +// VMOVUPS: Move Unaligned Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VMOVUPS m128 xmm +// VMOVUPS m256 ymm +// VMOVUPS xmm m128 +// VMOVUPS xmm xmm +// VMOVUPS ymm m256 +// VMOVUPS ymm ymm +// VMOVUPS m128 k xmm +// VMOVUPS m256 k ymm +// VMOVUPS xmm k m128 +// VMOVUPS xmm k xmm +// VMOVUPS ymm k m256 +// VMOVUPS ymm k ymm +// VMOVUPS m512 k zmm +// VMOVUPS m512 zmm +// VMOVUPS zmm k m512 +// VMOVUPS zmm k zmm +// VMOVUPS zmm m512 +// VMOVUPS zmm zmm +// Construct and append a VMOVUPS instruction to the active function. +// Operates on the global context. +func VMOVUPS(ops ...operand.Op) { ctx.VMOVUPS(ops...) } + +// VMOVUPS_Z: Move Unaligned Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMOVUPS.Z m128 k xmm +// VMOVUPS.Z m256 k ymm +// VMOVUPS.Z xmm k m128 +// VMOVUPS.Z xmm k xmm +// VMOVUPS.Z ymm k m256 +// VMOVUPS.Z ymm k ymm +// VMOVUPS.Z m512 k zmm +// VMOVUPS.Z zmm k m512 +// VMOVUPS.Z zmm k zmm +// Construct and append a VMOVUPS.Z instruction to the active function. +func (c *Context) VMOVUPS_Z(mxyz, k, mxyz1 operand.Op) { + c.addinstruction(x86.VMOVUPS_Z(mxyz, k, mxyz1)) +} + +// VMOVUPS_Z: Move Unaligned Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMOVUPS.Z m128 k xmm +// VMOVUPS.Z m256 k ymm +// VMOVUPS.Z xmm k m128 +// VMOVUPS.Z xmm k xmm +// VMOVUPS.Z ymm k m256 +// VMOVUPS.Z ymm k ymm +// VMOVUPS.Z m512 k zmm +// VMOVUPS.Z zmm k m512 +// VMOVUPS.Z zmm k zmm +// Construct and append a VMOVUPS.Z instruction to the active function. +// Operates on the global context. +func VMOVUPS_Z(mxyz, k, mxyz1 operand.Op) { ctx.VMOVUPS_Z(mxyz, k, mxyz1) } + +// VMPSADBW: Compute Multiple Packed Sums of Absolute Difference. +// +// Forms: +// +// VMPSADBW imm8 m256 ymm ymm +// VMPSADBW imm8 ymm ymm ymm +// VMPSADBW imm8 m128 xmm xmm +// VMPSADBW imm8 xmm xmm xmm +// Construct and append a VMPSADBW instruction to the active function. +func (c *Context) VMPSADBW(i, mxy, xy, xy1 operand.Op) { + c.addinstruction(x86.VMPSADBW(i, mxy, xy, xy1)) +} + +// VMPSADBW: Compute Multiple Packed Sums of Absolute Difference. +// +// Forms: +// +// VMPSADBW imm8 m256 ymm ymm +// VMPSADBW imm8 ymm ymm ymm +// VMPSADBW imm8 m128 xmm xmm +// VMPSADBW imm8 xmm xmm xmm +// Construct and append a VMPSADBW instruction to the active function. +// Operates on the global context. +func VMPSADBW(i, mxy, xy, xy1 operand.Op) { ctx.VMPSADBW(i, mxy, xy, xy1) } + +// VMULPD: Multiply Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VMULPD m128 xmm xmm +// VMULPD m256 ymm ymm +// VMULPD xmm xmm xmm +// VMULPD ymm ymm ymm +// VMULPD m128 xmm k xmm +// VMULPD m256 ymm k ymm +// VMULPD xmm xmm k xmm +// VMULPD ymm ymm k ymm +// VMULPD m512 zmm k zmm +// VMULPD m512 zmm zmm +// VMULPD zmm zmm k zmm +// VMULPD zmm zmm zmm +// Construct and append a VMULPD instruction to the active function. +func (c *Context) VMULPD(ops ...operand.Op) { + c.addinstruction(x86.VMULPD(ops...)) +} + +// VMULPD: Multiply Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VMULPD m128 xmm xmm +// VMULPD m256 ymm ymm +// VMULPD xmm xmm xmm +// VMULPD ymm ymm ymm +// VMULPD m128 xmm k xmm +// VMULPD m256 ymm k ymm +// VMULPD xmm xmm k xmm +// VMULPD ymm ymm k ymm +// VMULPD m512 zmm k zmm +// VMULPD m512 zmm zmm +// VMULPD zmm zmm k zmm +// VMULPD zmm zmm zmm +// Construct and append a VMULPD instruction to the active function. +// Operates on the global context. +func VMULPD(ops ...operand.Op) { ctx.VMULPD(ops...) } + +// VMULPD_BCST: Multiply Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VMULPD.BCST m64 xmm k xmm +// VMULPD.BCST m64 xmm xmm +// VMULPD.BCST m64 ymm k ymm +// VMULPD.BCST m64 ymm ymm +// VMULPD.BCST m64 zmm k zmm +// VMULPD.BCST m64 zmm zmm +// Construct and append a VMULPD.BCST instruction to the active function. +func (c *Context) VMULPD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VMULPD_BCST(ops...)) +} + +// VMULPD_BCST: Multiply Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VMULPD.BCST m64 xmm k xmm +// VMULPD.BCST m64 xmm xmm +// VMULPD.BCST m64 ymm k ymm +// VMULPD.BCST m64 ymm ymm +// VMULPD.BCST m64 zmm k zmm +// VMULPD.BCST m64 zmm zmm +// Construct and append a VMULPD.BCST instruction to the active function. +// Operates on the global context. +func VMULPD_BCST(ops ...operand.Op) { ctx.VMULPD_BCST(ops...) } + +// VMULPD_BCST_Z: Multiply Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VMULPD.BCST.Z m64 xmm k xmm +// VMULPD.BCST.Z m64 ymm k ymm +// VMULPD.BCST.Z m64 zmm k zmm +// Construct and append a VMULPD.BCST.Z instruction to the active function. +func (c *Context) VMULPD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VMULPD_BCST_Z(m, xyz, k, xyz1)) +} + +// VMULPD_BCST_Z: Multiply Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VMULPD.BCST.Z m64 xmm k xmm +// VMULPD.BCST.Z m64 ymm k ymm +// VMULPD.BCST.Z m64 zmm k zmm +// Construct and append a VMULPD.BCST.Z instruction to the active function. +// Operates on the global context. +func VMULPD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VMULPD_BCST_Z(m, xyz, k, xyz1) } + +// VMULPD_RD_SAE: Multiply Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VMULPD.RD_SAE zmm zmm k zmm +// VMULPD.RD_SAE zmm zmm zmm +// Construct and append a VMULPD.RD_SAE instruction to the active function. +func (c *Context) VMULPD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VMULPD_RD_SAE(ops...)) +} + +// VMULPD_RD_SAE: Multiply Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VMULPD.RD_SAE zmm zmm k zmm +// VMULPD.RD_SAE zmm zmm zmm +// Construct and append a VMULPD.RD_SAE instruction to the active function. +// Operates on the global context. +func VMULPD_RD_SAE(ops ...operand.Op) { ctx.VMULPD_RD_SAE(ops...) } + +// VMULPD_RD_SAE_Z: Multiply Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VMULPD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VMULPD.RD_SAE.Z instruction to the active function. +func (c *Context) VMULPD_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VMULPD_RD_SAE_Z(z, z1, k, z2)) +} + +// VMULPD_RD_SAE_Z: Multiply Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VMULPD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VMULPD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VMULPD_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VMULPD_RD_SAE_Z(z, z1, k, z2) } + +// VMULPD_RN_SAE: Multiply Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VMULPD.RN_SAE zmm zmm k zmm +// VMULPD.RN_SAE zmm zmm zmm +// Construct and append a VMULPD.RN_SAE instruction to the active function. +func (c *Context) VMULPD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VMULPD_RN_SAE(ops...)) +} + +// VMULPD_RN_SAE: Multiply Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VMULPD.RN_SAE zmm zmm k zmm +// VMULPD.RN_SAE zmm zmm zmm +// Construct and append a VMULPD.RN_SAE instruction to the active function. +// Operates on the global context. +func VMULPD_RN_SAE(ops ...operand.Op) { ctx.VMULPD_RN_SAE(ops...) } + +// VMULPD_RN_SAE_Z: Multiply Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VMULPD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VMULPD.RN_SAE.Z instruction to the active function. +func (c *Context) VMULPD_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VMULPD_RN_SAE_Z(z, z1, k, z2)) +} + +// VMULPD_RN_SAE_Z: Multiply Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VMULPD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VMULPD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VMULPD_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VMULPD_RN_SAE_Z(z, z1, k, z2) } + +// VMULPD_RU_SAE: Multiply Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VMULPD.RU_SAE zmm zmm k zmm +// VMULPD.RU_SAE zmm zmm zmm +// Construct and append a VMULPD.RU_SAE instruction to the active function. +func (c *Context) VMULPD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VMULPD_RU_SAE(ops...)) +} + +// VMULPD_RU_SAE: Multiply Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VMULPD.RU_SAE zmm zmm k zmm +// VMULPD.RU_SAE zmm zmm zmm +// Construct and append a VMULPD.RU_SAE instruction to the active function. +// Operates on the global context. +func VMULPD_RU_SAE(ops ...operand.Op) { ctx.VMULPD_RU_SAE(ops...) } + +// VMULPD_RU_SAE_Z: Multiply Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VMULPD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VMULPD.RU_SAE.Z instruction to the active function. +func (c *Context) VMULPD_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VMULPD_RU_SAE_Z(z, z1, k, z2)) +} + +// VMULPD_RU_SAE_Z: Multiply Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VMULPD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VMULPD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VMULPD_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VMULPD_RU_SAE_Z(z, z1, k, z2) } + +// VMULPD_RZ_SAE: Multiply Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VMULPD.RZ_SAE zmm zmm k zmm +// VMULPD.RZ_SAE zmm zmm zmm +// Construct and append a VMULPD.RZ_SAE instruction to the active function. +func (c *Context) VMULPD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VMULPD_RZ_SAE(ops...)) +} + +// VMULPD_RZ_SAE: Multiply Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VMULPD.RZ_SAE zmm zmm k zmm +// VMULPD.RZ_SAE zmm zmm zmm +// Construct and append a VMULPD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VMULPD_RZ_SAE(ops ...operand.Op) { ctx.VMULPD_RZ_SAE(ops...) } + +// VMULPD_RZ_SAE_Z: Multiply Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VMULPD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VMULPD.RZ_SAE.Z instruction to the active function. +func (c *Context) VMULPD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VMULPD_RZ_SAE_Z(z, z1, k, z2)) +} + +// VMULPD_RZ_SAE_Z: Multiply Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VMULPD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VMULPD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VMULPD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VMULPD_RZ_SAE_Z(z, z1, k, z2) } + +// VMULPD_Z: Multiply Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMULPD.Z m128 xmm k xmm +// VMULPD.Z m256 ymm k ymm +// VMULPD.Z xmm xmm k xmm +// VMULPD.Z ymm ymm k ymm +// VMULPD.Z m512 zmm k zmm +// VMULPD.Z zmm zmm k zmm +// Construct and append a VMULPD.Z instruction to the active function. +func (c *Context) VMULPD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VMULPD_Z(mxyz, xyz, k, xyz1)) +} + +// VMULPD_Z: Multiply Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMULPD.Z m128 xmm k xmm +// VMULPD.Z m256 ymm k ymm +// VMULPD.Z xmm xmm k xmm +// VMULPD.Z ymm ymm k ymm +// VMULPD.Z m512 zmm k zmm +// VMULPD.Z zmm zmm k zmm +// Construct and append a VMULPD.Z instruction to the active function. +// Operates on the global context. +func VMULPD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VMULPD_Z(mxyz, xyz, k, xyz1) } + +// VMULPS: Multiply Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VMULPS m128 xmm xmm +// VMULPS m256 ymm ymm +// VMULPS xmm xmm xmm +// VMULPS ymm ymm ymm +// VMULPS m128 xmm k xmm +// VMULPS m256 ymm k ymm +// VMULPS xmm xmm k xmm +// VMULPS ymm ymm k ymm +// VMULPS m512 zmm k zmm +// VMULPS m512 zmm zmm +// VMULPS zmm zmm k zmm +// VMULPS zmm zmm zmm +// Construct and append a VMULPS instruction to the active function. +func (c *Context) VMULPS(ops ...operand.Op) { + c.addinstruction(x86.VMULPS(ops...)) +} + +// VMULPS: Multiply Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VMULPS m128 xmm xmm +// VMULPS m256 ymm ymm +// VMULPS xmm xmm xmm +// VMULPS ymm ymm ymm +// VMULPS m128 xmm k xmm +// VMULPS m256 ymm k ymm +// VMULPS xmm xmm k xmm +// VMULPS ymm ymm k ymm +// VMULPS m512 zmm k zmm +// VMULPS m512 zmm zmm +// VMULPS zmm zmm k zmm +// VMULPS zmm zmm zmm +// Construct and append a VMULPS instruction to the active function. +// Operates on the global context. +func VMULPS(ops ...operand.Op) { ctx.VMULPS(ops...) } + +// VMULPS_BCST: Multiply Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VMULPS.BCST m32 xmm k xmm +// VMULPS.BCST m32 xmm xmm +// VMULPS.BCST m32 ymm k ymm +// VMULPS.BCST m32 ymm ymm +// VMULPS.BCST m32 zmm k zmm +// VMULPS.BCST m32 zmm zmm +// Construct and append a VMULPS.BCST instruction to the active function. +func (c *Context) VMULPS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VMULPS_BCST(ops...)) +} + +// VMULPS_BCST: Multiply Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VMULPS.BCST m32 xmm k xmm +// VMULPS.BCST m32 xmm xmm +// VMULPS.BCST m32 ymm k ymm +// VMULPS.BCST m32 ymm ymm +// VMULPS.BCST m32 zmm k zmm +// VMULPS.BCST m32 zmm zmm +// Construct and append a VMULPS.BCST instruction to the active function. +// Operates on the global context. +func VMULPS_BCST(ops ...operand.Op) { ctx.VMULPS_BCST(ops...) } + +// VMULPS_BCST_Z: Multiply Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VMULPS.BCST.Z m32 xmm k xmm +// VMULPS.BCST.Z m32 ymm k ymm +// VMULPS.BCST.Z m32 zmm k zmm +// Construct and append a VMULPS.BCST.Z instruction to the active function. +func (c *Context) VMULPS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VMULPS_BCST_Z(m, xyz, k, xyz1)) +} + +// VMULPS_BCST_Z: Multiply Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VMULPS.BCST.Z m32 xmm k xmm +// VMULPS.BCST.Z m32 ymm k ymm +// VMULPS.BCST.Z m32 zmm k zmm +// Construct and append a VMULPS.BCST.Z instruction to the active function. +// Operates on the global context. +func VMULPS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VMULPS_BCST_Z(m, xyz, k, xyz1) } + +// VMULPS_RD_SAE: Multiply Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VMULPS.RD_SAE zmm zmm k zmm +// VMULPS.RD_SAE zmm zmm zmm +// Construct and append a VMULPS.RD_SAE instruction to the active function. +func (c *Context) VMULPS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VMULPS_RD_SAE(ops...)) +} + +// VMULPS_RD_SAE: Multiply Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VMULPS.RD_SAE zmm zmm k zmm +// VMULPS.RD_SAE zmm zmm zmm +// Construct and append a VMULPS.RD_SAE instruction to the active function. +// Operates on the global context. +func VMULPS_RD_SAE(ops ...operand.Op) { ctx.VMULPS_RD_SAE(ops...) } + +// VMULPS_RD_SAE_Z: Multiply Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VMULPS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VMULPS.RD_SAE.Z instruction to the active function. +func (c *Context) VMULPS_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VMULPS_RD_SAE_Z(z, z1, k, z2)) +} + +// VMULPS_RD_SAE_Z: Multiply Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VMULPS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VMULPS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VMULPS_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VMULPS_RD_SAE_Z(z, z1, k, z2) } + +// VMULPS_RN_SAE: Multiply Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VMULPS.RN_SAE zmm zmm k zmm +// VMULPS.RN_SAE zmm zmm zmm +// Construct and append a VMULPS.RN_SAE instruction to the active function. +func (c *Context) VMULPS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VMULPS_RN_SAE(ops...)) +} + +// VMULPS_RN_SAE: Multiply Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VMULPS.RN_SAE zmm zmm k zmm +// VMULPS.RN_SAE zmm zmm zmm +// Construct and append a VMULPS.RN_SAE instruction to the active function. +// Operates on the global context. +func VMULPS_RN_SAE(ops ...operand.Op) { ctx.VMULPS_RN_SAE(ops...) } + +// VMULPS_RN_SAE_Z: Multiply Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VMULPS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VMULPS.RN_SAE.Z instruction to the active function. +func (c *Context) VMULPS_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VMULPS_RN_SAE_Z(z, z1, k, z2)) +} + +// VMULPS_RN_SAE_Z: Multiply Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VMULPS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VMULPS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VMULPS_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VMULPS_RN_SAE_Z(z, z1, k, z2) } + +// VMULPS_RU_SAE: Multiply Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VMULPS.RU_SAE zmm zmm k zmm +// VMULPS.RU_SAE zmm zmm zmm +// Construct and append a VMULPS.RU_SAE instruction to the active function. +func (c *Context) VMULPS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VMULPS_RU_SAE(ops...)) +} + +// VMULPS_RU_SAE: Multiply Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VMULPS.RU_SAE zmm zmm k zmm +// VMULPS.RU_SAE zmm zmm zmm +// Construct and append a VMULPS.RU_SAE instruction to the active function. +// Operates on the global context. +func VMULPS_RU_SAE(ops ...operand.Op) { ctx.VMULPS_RU_SAE(ops...) } + +// VMULPS_RU_SAE_Z: Multiply Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VMULPS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VMULPS.RU_SAE.Z instruction to the active function. +func (c *Context) VMULPS_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VMULPS_RU_SAE_Z(z, z1, k, z2)) +} + +// VMULPS_RU_SAE_Z: Multiply Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VMULPS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VMULPS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VMULPS_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VMULPS_RU_SAE_Z(z, z1, k, z2) } + +// VMULPS_RZ_SAE: Multiply Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VMULPS.RZ_SAE zmm zmm k zmm +// VMULPS.RZ_SAE zmm zmm zmm +// Construct and append a VMULPS.RZ_SAE instruction to the active function. +func (c *Context) VMULPS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VMULPS_RZ_SAE(ops...)) +} + +// VMULPS_RZ_SAE: Multiply Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VMULPS.RZ_SAE zmm zmm k zmm +// VMULPS.RZ_SAE zmm zmm zmm +// Construct and append a VMULPS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VMULPS_RZ_SAE(ops ...operand.Op) { ctx.VMULPS_RZ_SAE(ops...) } + +// VMULPS_RZ_SAE_Z: Multiply Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VMULPS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VMULPS.RZ_SAE.Z instruction to the active function. +func (c *Context) VMULPS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VMULPS_RZ_SAE_Z(z, z1, k, z2)) +} + +// VMULPS_RZ_SAE_Z: Multiply Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VMULPS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VMULPS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VMULPS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VMULPS_RZ_SAE_Z(z, z1, k, z2) } + +// VMULPS_Z: Multiply Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMULPS.Z m128 xmm k xmm +// VMULPS.Z m256 ymm k ymm +// VMULPS.Z xmm xmm k xmm +// VMULPS.Z ymm ymm k ymm +// VMULPS.Z m512 zmm k zmm +// VMULPS.Z zmm zmm k zmm +// Construct and append a VMULPS.Z instruction to the active function. +func (c *Context) VMULPS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VMULPS_Z(mxyz, xyz, k, xyz1)) +} + +// VMULPS_Z: Multiply Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMULPS.Z m128 xmm k xmm +// VMULPS.Z m256 ymm k ymm +// VMULPS.Z xmm xmm k xmm +// VMULPS.Z ymm ymm k ymm +// VMULPS.Z m512 zmm k zmm +// VMULPS.Z zmm zmm k zmm +// Construct and append a VMULPS.Z instruction to the active function. +// Operates on the global context. +func VMULPS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VMULPS_Z(mxyz, xyz, k, xyz1) } + +// VMULSD: Multiply Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VMULSD m64 xmm xmm +// VMULSD xmm xmm xmm +// VMULSD m64 xmm k xmm +// VMULSD xmm xmm k xmm +// Construct and append a VMULSD instruction to the active function. +func (c *Context) VMULSD(ops ...operand.Op) { + c.addinstruction(x86.VMULSD(ops...)) +} + +// VMULSD: Multiply Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VMULSD m64 xmm xmm +// VMULSD xmm xmm xmm +// VMULSD m64 xmm k xmm +// VMULSD xmm xmm k xmm +// Construct and append a VMULSD instruction to the active function. +// Operates on the global context. +func VMULSD(ops ...operand.Op) { ctx.VMULSD(ops...) } + +// VMULSD_RD_SAE: Multiply Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VMULSD.RD_SAE xmm xmm k xmm +// VMULSD.RD_SAE xmm xmm xmm +// Construct and append a VMULSD.RD_SAE instruction to the active function. +func (c *Context) VMULSD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VMULSD_RD_SAE(ops...)) +} + +// VMULSD_RD_SAE: Multiply Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VMULSD.RD_SAE xmm xmm k xmm +// VMULSD.RD_SAE xmm xmm xmm +// Construct and append a VMULSD.RD_SAE instruction to the active function. +// Operates on the global context. +func VMULSD_RD_SAE(ops ...operand.Op) { ctx.VMULSD_RD_SAE(ops...) } + +// VMULSD_RD_SAE_Z: Multiply Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VMULSD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VMULSD.RD_SAE.Z instruction to the active function. +func (c *Context) VMULSD_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VMULSD_RD_SAE_Z(x, x1, k, x2)) +} + +// VMULSD_RD_SAE_Z: Multiply Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VMULSD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VMULSD.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VMULSD_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VMULSD_RD_SAE_Z(x, x1, k, x2) } + +// VMULSD_RN_SAE: Multiply Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VMULSD.RN_SAE xmm xmm k xmm +// VMULSD.RN_SAE xmm xmm xmm +// Construct and append a VMULSD.RN_SAE instruction to the active function. +func (c *Context) VMULSD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VMULSD_RN_SAE(ops...)) +} + +// VMULSD_RN_SAE: Multiply Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VMULSD.RN_SAE xmm xmm k xmm +// VMULSD.RN_SAE xmm xmm xmm +// Construct and append a VMULSD.RN_SAE instruction to the active function. +// Operates on the global context. +func VMULSD_RN_SAE(ops ...operand.Op) { ctx.VMULSD_RN_SAE(ops...) } + +// VMULSD_RN_SAE_Z: Multiply Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VMULSD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VMULSD.RN_SAE.Z instruction to the active function. +func (c *Context) VMULSD_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VMULSD_RN_SAE_Z(x, x1, k, x2)) +} + +// VMULSD_RN_SAE_Z: Multiply Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VMULSD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VMULSD.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VMULSD_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VMULSD_RN_SAE_Z(x, x1, k, x2) } + +// VMULSD_RU_SAE: Multiply Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VMULSD.RU_SAE xmm xmm k xmm +// VMULSD.RU_SAE xmm xmm xmm +// Construct and append a VMULSD.RU_SAE instruction to the active function. +func (c *Context) VMULSD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VMULSD_RU_SAE(ops...)) +} + +// VMULSD_RU_SAE: Multiply Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VMULSD.RU_SAE xmm xmm k xmm +// VMULSD.RU_SAE xmm xmm xmm +// Construct and append a VMULSD.RU_SAE instruction to the active function. +// Operates on the global context. +func VMULSD_RU_SAE(ops ...operand.Op) { ctx.VMULSD_RU_SAE(ops...) } + +// VMULSD_RU_SAE_Z: Multiply Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VMULSD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VMULSD.RU_SAE.Z instruction to the active function. +func (c *Context) VMULSD_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VMULSD_RU_SAE_Z(x, x1, k, x2)) +} + +// VMULSD_RU_SAE_Z: Multiply Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VMULSD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VMULSD.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VMULSD_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VMULSD_RU_SAE_Z(x, x1, k, x2) } + +// VMULSD_RZ_SAE: Multiply Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VMULSD.RZ_SAE xmm xmm k xmm +// VMULSD.RZ_SAE xmm xmm xmm +// Construct and append a VMULSD.RZ_SAE instruction to the active function. +func (c *Context) VMULSD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VMULSD_RZ_SAE(ops...)) +} + +// VMULSD_RZ_SAE: Multiply Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VMULSD.RZ_SAE xmm xmm k xmm +// VMULSD.RZ_SAE xmm xmm xmm +// Construct and append a VMULSD.RZ_SAE instruction to the active function. +// Operates on the global context. +func VMULSD_RZ_SAE(ops ...operand.Op) { ctx.VMULSD_RZ_SAE(ops...) } + +// VMULSD_RZ_SAE_Z: Multiply Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VMULSD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VMULSD.RZ_SAE.Z instruction to the active function. +func (c *Context) VMULSD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VMULSD_RZ_SAE_Z(x, x1, k, x2)) +} + +// VMULSD_RZ_SAE_Z: Multiply Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VMULSD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VMULSD.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VMULSD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VMULSD_RZ_SAE_Z(x, x1, k, x2) } + +// VMULSD_Z: Multiply Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMULSD.Z m64 xmm k xmm +// VMULSD.Z xmm xmm k xmm +// Construct and append a VMULSD.Z instruction to the active function. +func (c *Context) VMULSD_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VMULSD_Z(mx, x, k, x1)) +} + +// VMULSD_Z: Multiply Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMULSD.Z m64 xmm k xmm +// VMULSD.Z xmm xmm k xmm +// Construct and append a VMULSD.Z instruction to the active function. +// Operates on the global context. +func VMULSD_Z(mx, x, k, x1 operand.Op) { ctx.VMULSD_Z(mx, x, k, x1) } + +// VMULSS: Multiply Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VMULSS m32 xmm xmm +// VMULSS xmm xmm xmm +// VMULSS m32 xmm k xmm +// VMULSS xmm xmm k xmm +// Construct and append a VMULSS instruction to the active function. +func (c *Context) VMULSS(ops ...operand.Op) { + c.addinstruction(x86.VMULSS(ops...)) +} + +// VMULSS: Multiply Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VMULSS m32 xmm xmm +// VMULSS xmm xmm xmm +// VMULSS m32 xmm k xmm +// VMULSS xmm xmm k xmm +// Construct and append a VMULSS instruction to the active function. +// Operates on the global context. +func VMULSS(ops ...operand.Op) { ctx.VMULSS(ops...) } + +// VMULSS_RD_SAE: Multiply Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VMULSS.RD_SAE xmm xmm k xmm +// VMULSS.RD_SAE xmm xmm xmm +// Construct and append a VMULSS.RD_SAE instruction to the active function. +func (c *Context) VMULSS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VMULSS_RD_SAE(ops...)) +} + +// VMULSS_RD_SAE: Multiply Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VMULSS.RD_SAE xmm xmm k xmm +// VMULSS.RD_SAE xmm xmm xmm +// Construct and append a VMULSS.RD_SAE instruction to the active function. +// Operates on the global context. +func VMULSS_RD_SAE(ops ...operand.Op) { ctx.VMULSS_RD_SAE(ops...) } + +// VMULSS_RD_SAE_Z: Multiply Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VMULSS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VMULSS.RD_SAE.Z instruction to the active function. +func (c *Context) VMULSS_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VMULSS_RD_SAE_Z(x, x1, k, x2)) +} + +// VMULSS_RD_SAE_Z: Multiply Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VMULSS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VMULSS.RD_SAE.Z instruction to the active function. +// Operates on the global context. +func VMULSS_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VMULSS_RD_SAE_Z(x, x1, k, x2) } + +// VMULSS_RN_SAE: Multiply Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VMULSS.RN_SAE xmm xmm k xmm +// VMULSS.RN_SAE xmm xmm xmm +// Construct and append a VMULSS.RN_SAE instruction to the active function. +func (c *Context) VMULSS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VMULSS_RN_SAE(ops...)) +} + +// VMULSS_RN_SAE: Multiply Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VMULSS.RN_SAE xmm xmm k xmm +// VMULSS.RN_SAE xmm xmm xmm +// Construct and append a VMULSS.RN_SAE instruction to the active function. +// Operates on the global context. +func VMULSS_RN_SAE(ops ...operand.Op) { ctx.VMULSS_RN_SAE(ops...) } + +// VMULSS_RN_SAE_Z: Multiply Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VMULSS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VMULSS.RN_SAE.Z instruction to the active function. +func (c *Context) VMULSS_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VMULSS_RN_SAE_Z(x, x1, k, x2)) +} + +// VMULSS_RN_SAE_Z: Multiply Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VMULSS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VMULSS.RN_SAE.Z instruction to the active function. +// Operates on the global context. +func VMULSS_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VMULSS_RN_SAE_Z(x, x1, k, x2) } + +// VMULSS_RU_SAE: Multiply Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VMULSS.RU_SAE xmm xmm k xmm +// VMULSS.RU_SAE xmm xmm xmm +// Construct and append a VMULSS.RU_SAE instruction to the active function. +func (c *Context) VMULSS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VMULSS_RU_SAE(ops...)) +} + +// VMULSS_RU_SAE: Multiply Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VMULSS.RU_SAE xmm xmm k xmm +// VMULSS.RU_SAE xmm xmm xmm +// Construct and append a VMULSS.RU_SAE instruction to the active function. +// Operates on the global context. +func VMULSS_RU_SAE(ops ...operand.Op) { ctx.VMULSS_RU_SAE(ops...) } + +// VMULSS_RU_SAE_Z: Multiply Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VMULSS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VMULSS.RU_SAE.Z instruction to the active function. +func (c *Context) VMULSS_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VMULSS_RU_SAE_Z(x, x1, k, x2)) +} + +// VMULSS_RU_SAE_Z: Multiply Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VMULSS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VMULSS.RU_SAE.Z instruction to the active function. +// Operates on the global context. +func VMULSS_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VMULSS_RU_SAE_Z(x, x1, k, x2) } + +// VMULSS_RZ_SAE: Multiply Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VMULSS.RZ_SAE xmm xmm k xmm +// VMULSS.RZ_SAE xmm xmm xmm +// Construct and append a VMULSS.RZ_SAE instruction to the active function. +func (c *Context) VMULSS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VMULSS_RZ_SAE(ops...)) +} + +// VMULSS_RZ_SAE: Multiply Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VMULSS.RZ_SAE xmm xmm k xmm +// VMULSS.RZ_SAE xmm xmm xmm +// Construct and append a VMULSS.RZ_SAE instruction to the active function. +// Operates on the global context. +func VMULSS_RZ_SAE(ops ...operand.Op) { ctx.VMULSS_RZ_SAE(ops...) } + +// VMULSS_RZ_SAE_Z: Multiply Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VMULSS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VMULSS.RZ_SAE.Z instruction to the active function. +func (c *Context) VMULSS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VMULSS_RZ_SAE_Z(x, x1, k, x2)) +} + +// VMULSS_RZ_SAE_Z: Multiply Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VMULSS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VMULSS.RZ_SAE.Z instruction to the active function. +// Operates on the global context. +func VMULSS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VMULSS_RZ_SAE_Z(x, x1, k, x2) } + +// VMULSS_Z: Multiply Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMULSS.Z m32 xmm k xmm +// VMULSS.Z xmm xmm k xmm +// Construct and append a VMULSS.Z instruction to the active function. +func (c *Context) VMULSS_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VMULSS_Z(mx, x, k, x1)) +} + +// VMULSS_Z: Multiply Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMULSS.Z m32 xmm k xmm +// VMULSS.Z xmm xmm k xmm +// Construct and append a VMULSS.Z instruction to the active function. +// Operates on the global context. +func VMULSS_Z(mx, x, k, x1 operand.Op) { ctx.VMULSS_Z(mx, x, k, x1) } + +// VORPD: Bitwise Logical OR of Double-Precision Floating-Point Values. +// +// Forms: +// +// VORPD m128 xmm xmm +// VORPD m256 ymm ymm +// VORPD xmm xmm xmm +// VORPD ymm ymm ymm +// VORPD m128 xmm k xmm +// VORPD m256 ymm k ymm +// VORPD xmm xmm k xmm +// VORPD ymm ymm k ymm +// VORPD m512 zmm k zmm +// VORPD m512 zmm zmm +// VORPD zmm zmm k zmm +// VORPD zmm zmm zmm +// Construct and append a VORPD instruction to the active function. +func (c *Context) VORPD(ops ...operand.Op) { + c.addinstruction(x86.VORPD(ops...)) +} + +// VORPD: Bitwise Logical OR of Double-Precision Floating-Point Values. +// +// Forms: +// +// VORPD m128 xmm xmm +// VORPD m256 ymm ymm +// VORPD xmm xmm xmm +// VORPD ymm ymm ymm +// VORPD m128 xmm k xmm +// VORPD m256 ymm k ymm +// VORPD xmm xmm k xmm +// VORPD ymm ymm k ymm +// VORPD m512 zmm k zmm +// VORPD m512 zmm zmm +// VORPD zmm zmm k zmm +// VORPD zmm zmm zmm +// Construct and append a VORPD instruction to the active function. +// Operates on the global context. +func VORPD(ops ...operand.Op) { ctx.VORPD(ops...) } + +// VORPD_BCST: Bitwise Logical OR of Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VORPD.BCST m64 xmm k xmm +// VORPD.BCST m64 xmm xmm +// VORPD.BCST m64 ymm k ymm +// VORPD.BCST m64 ymm ymm +// VORPD.BCST m64 zmm k zmm +// VORPD.BCST m64 zmm zmm +// Construct and append a VORPD.BCST instruction to the active function. +func (c *Context) VORPD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VORPD_BCST(ops...)) +} + +// VORPD_BCST: Bitwise Logical OR of Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VORPD.BCST m64 xmm k xmm +// VORPD.BCST m64 xmm xmm +// VORPD.BCST m64 ymm k ymm +// VORPD.BCST m64 ymm ymm +// VORPD.BCST m64 zmm k zmm +// VORPD.BCST m64 zmm zmm +// Construct and append a VORPD.BCST instruction to the active function. +// Operates on the global context. +func VORPD_BCST(ops ...operand.Op) { ctx.VORPD_BCST(ops...) } + +// VORPD_BCST_Z: Bitwise Logical OR of Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VORPD.BCST.Z m64 xmm k xmm +// VORPD.BCST.Z m64 ymm k ymm +// VORPD.BCST.Z m64 zmm k zmm +// Construct and append a VORPD.BCST.Z instruction to the active function. +func (c *Context) VORPD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VORPD_BCST_Z(m, xyz, k, xyz1)) +} + +// VORPD_BCST_Z: Bitwise Logical OR of Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VORPD.BCST.Z m64 xmm k xmm +// VORPD.BCST.Z m64 ymm k ymm +// VORPD.BCST.Z m64 zmm k zmm +// Construct and append a VORPD.BCST.Z instruction to the active function. +// Operates on the global context. +func VORPD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VORPD_BCST_Z(m, xyz, k, xyz1) } + +// VORPD_Z: Bitwise Logical OR of Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VORPD.Z m128 xmm k xmm +// VORPD.Z m256 ymm k ymm +// VORPD.Z xmm xmm k xmm +// VORPD.Z ymm ymm k ymm +// VORPD.Z m512 zmm k zmm +// VORPD.Z zmm zmm k zmm +// Construct and append a VORPD.Z instruction to the active function. +func (c *Context) VORPD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VORPD_Z(mxyz, xyz, k, xyz1)) +} + +// VORPD_Z: Bitwise Logical OR of Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VORPD.Z m128 xmm k xmm +// VORPD.Z m256 ymm k ymm +// VORPD.Z xmm xmm k xmm +// VORPD.Z ymm ymm k ymm +// VORPD.Z m512 zmm k zmm +// VORPD.Z zmm zmm k zmm +// Construct and append a VORPD.Z instruction to the active function. +// Operates on the global context. +func VORPD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VORPD_Z(mxyz, xyz, k, xyz1) } + +// VORPS: Bitwise Logical OR of Single-Precision Floating-Point Values. +// +// Forms: +// +// VORPS m128 xmm xmm +// VORPS m256 ymm ymm +// VORPS xmm xmm xmm +// VORPS ymm ymm ymm +// VORPS m128 xmm k xmm +// VORPS m256 ymm k ymm +// VORPS xmm xmm k xmm +// VORPS ymm ymm k ymm +// VORPS m512 zmm k zmm +// VORPS m512 zmm zmm +// VORPS zmm zmm k zmm +// VORPS zmm zmm zmm +// Construct and append a VORPS instruction to the active function. +func (c *Context) VORPS(ops ...operand.Op) { + c.addinstruction(x86.VORPS(ops...)) +} + +// VORPS: Bitwise Logical OR of Single-Precision Floating-Point Values. +// +// Forms: +// +// VORPS m128 xmm xmm +// VORPS m256 ymm ymm +// VORPS xmm xmm xmm +// VORPS ymm ymm ymm +// VORPS m128 xmm k xmm +// VORPS m256 ymm k ymm +// VORPS xmm xmm k xmm +// VORPS ymm ymm k ymm +// VORPS m512 zmm k zmm +// VORPS m512 zmm zmm +// VORPS zmm zmm k zmm +// VORPS zmm zmm zmm +// Construct and append a VORPS instruction to the active function. +// Operates on the global context. +func VORPS(ops ...operand.Op) { ctx.VORPS(ops...) } + +// VORPS_BCST: Bitwise Logical OR of Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VORPS.BCST m32 xmm k xmm +// VORPS.BCST m32 xmm xmm +// VORPS.BCST m32 ymm k ymm +// VORPS.BCST m32 ymm ymm +// VORPS.BCST m32 zmm k zmm +// VORPS.BCST m32 zmm zmm +// Construct and append a VORPS.BCST instruction to the active function. +func (c *Context) VORPS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VORPS_BCST(ops...)) +} + +// VORPS_BCST: Bitwise Logical OR of Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VORPS.BCST m32 xmm k xmm +// VORPS.BCST m32 xmm xmm +// VORPS.BCST m32 ymm k ymm +// VORPS.BCST m32 ymm ymm +// VORPS.BCST m32 zmm k zmm +// VORPS.BCST m32 zmm zmm +// Construct and append a VORPS.BCST instruction to the active function. +// Operates on the global context. +func VORPS_BCST(ops ...operand.Op) { ctx.VORPS_BCST(ops...) } + +// VORPS_BCST_Z: Bitwise Logical OR of Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VORPS.BCST.Z m32 xmm k xmm +// VORPS.BCST.Z m32 ymm k ymm +// VORPS.BCST.Z m32 zmm k zmm +// Construct and append a VORPS.BCST.Z instruction to the active function. +func (c *Context) VORPS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VORPS_BCST_Z(m, xyz, k, xyz1)) +} + +// VORPS_BCST_Z: Bitwise Logical OR of Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VORPS.BCST.Z m32 xmm k xmm +// VORPS.BCST.Z m32 ymm k ymm +// VORPS.BCST.Z m32 zmm k zmm +// Construct and append a VORPS.BCST.Z instruction to the active function. +// Operates on the global context. +func VORPS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VORPS_BCST_Z(m, xyz, k, xyz1) } + +// VORPS_Z: Bitwise Logical OR of Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VORPS.Z m128 xmm k xmm +// VORPS.Z m256 ymm k ymm +// VORPS.Z xmm xmm k xmm +// VORPS.Z ymm ymm k ymm +// VORPS.Z m512 zmm k zmm +// VORPS.Z zmm zmm k zmm +// Construct and append a VORPS.Z instruction to the active function. +func (c *Context) VORPS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VORPS_Z(mxyz, xyz, k, xyz1)) +} + +// VORPS_Z: Bitwise Logical OR of Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VORPS.Z m128 xmm k xmm +// VORPS.Z m256 ymm k ymm +// VORPS.Z xmm xmm k xmm +// VORPS.Z ymm ymm k ymm +// VORPS.Z m512 zmm k zmm +// VORPS.Z zmm zmm k zmm +// Construct and append a VORPS.Z instruction to the active function. +// Operates on the global context. +func VORPS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VORPS_Z(mxyz, xyz, k, xyz1) } + +// VPABSB: Packed Absolute Value of Byte Integers. +// +// Forms: +// +// VPABSB m256 ymm +// VPABSB ymm ymm +// VPABSB m128 xmm +// VPABSB xmm xmm +// VPABSB m128 k xmm +// VPABSB m256 k ymm +// VPABSB xmm k xmm +// VPABSB ymm k ymm +// VPABSB m512 k zmm +// VPABSB m512 zmm +// VPABSB zmm k zmm +// VPABSB zmm zmm +// Construct and append a VPABSB instruction to the active function. +func (c *Context) VPABSB(ops ...operand.Op) { + c.addinstruction(x86.VPABSB(ops...)) +} + +// VPABSB: Packed Absolute Value of Byte Integers. +// +// Forms: +// +// VPABSB m256 ymm +// VPABSB ymm ymm +// VPABSB m128 xmm +// VPABSB xmm xmm +// VPABSB m128 k xmm +// VPABSB m256 k ymm +// VPABSB xmm k xmm +// VPABSB ymm k ymm +// VPABSB m512 k zmm +// VPABSB m512 zmm +// VPABSB zmm k zmm +// VPABSB zmm zmm +// Construct and append a VPABSB instruction to the active function. +// Operates on the global context. +func VPABSB(ops ...operand.Op) { ctx.VPABSB(ops...) } + +// VPABSB_Z: Packed Absolute Value of Byte Integers (Zeroing Masking). +// +// Forms: +// +// VPABSB.Z m128 k xmm +// VPABSB.Z m256 k ymm +// VPABSB.Z xmm k xmm +// VPABSB.Z ymm k ymm +// VPABSB.Z m512 k zmm +// VPABSB.Z zmm k zmm +// Construct and append a VPABSB.Z instruction to the active function. +func (c *Context) VPABSB_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPABSB_Z(mxyz, k, xyz)) +} + +// VPABSB_Z: Packed Absolute Value of Byte Integers (Zeroing Masking). +// +// Forms: +// +// VPABSB.Z m128 k xmm +// VPABSB.Z m256 k ymm +// VPABSB.Z xmm k xmm +// VPABSB.Z ymm k ymm +// VPABSB.Z m512 k zmm +// VPABSB.Z zmm k zmm +// Construct and append a VPABSB.Z instruction to the active function. +// Operates on the global context. +func VPABSB_Z(mxyz, k, xyz operand.Op) { ctx.VPABSB_Z(mxyz, k, xyz) } + +// VPABSD: Packed Absolute Value of Doubleword Integers. +// +// Forms: +// +// VPABSD m256 ymm +// VPABSD ymm ymm +// VPABSD m128 xmm +// VPABSD xmm xmm +// VPABSD m128 k xmm +// VPABSD m256 k ymm +// VPABSD xmm k xmm +// VPABSD ymm k ymm +// VPABSD m512 k zmm +// VPABSD m512 zmm +// VPABSD zmm k zmm +// VPABSD zmm zmm +// Construct and append a VPABSD instruction to the active function. +func (c *Context) VPABSD(ops ...operand.Op) { + c.addinstruction(x86.VPABSD(ops...)) +} + +// VPABSD: Packed Absolute Value of Doubleword Integers. +// +// Forms: +// +// VPABSD m256 ymm +// VPABSD ymm ymm +// VPABSD m128 xmm +// VPABSD xmm xmm +// VPABSD m128 k xmm +// VPABSD m256 k ymm +// VPABSD xmm k xmm +// VPABSD ymm k ymm +// VPABSD m512 k zmm +// VPABSD m512 zmm +// VPABSD zmm k zmm +// VPABSD zmm zmm +// Construct and append a VPABSD instruction to the active function. +// Operates on the global context. +func VPABSD(ops ...operand.Op) { ctx.VPABSD(ops...) } + +// VPABSD_BCST: Packed Absolute Value of Doubleword Integers (Broadcast). +// +// Forms: +// +// VPABSD.BCST m32 k xmm +// VPABSD.BCST m32 k ymm +// VPABSD.BCST m32 xmm +// VPABSD.BCST m32 ymm +// VPABSD.BCST m32 k zmm +// VPABSD.BCST m32 zmm +// Construct and append a VPABSD.BCST instruction to the active function. +func (c *Context) VPABSD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPABSD_BCST(ops...)) +} + +// VPABSD_BCST: Packed Absolute Value of Doubleword Integers (Broadcast). +// +// Forms: +// +// VPABSD.BCST m32 k xmm +// VPABSD.BCST m32 k ymm +// VPABSD.BCST m32 xmm +// VPABSD.BCST m32 ymm +// VPABSD.BCST m32 k zmm +// VPABSD.BCST m32 zmm +// Construct and append a VPABSD.BCST instruction to the active function. +// Operates on the global context. +func VPABSD_BCST(ops ...operand.Op) { ctx.VPABSD_BCST(ops...) } + +// VPABSD_BCST_Z: Packed Absolute Value of Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPABSD.BCST.Z m32 k xmm +// VPABSD.BCST.Z m32 k ymm +// VPABSD.BCST.Z m32 k zmm +// Construct and append a VPABSD.BCST.Z instruction to the active function. +func (c *Context) VPABSD_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VPABSD_BCST_Z(m, k, xyz)) +} + +// VPABSD_BCST_Z: Packed Absolute Value of Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPABSD.BCST.Z m32 k xmm +// VPABSD.BCST.Z m32 k ymm +// VPABSD.BCST.Z m32 k zmm +// Construct and append a VPABSD.BCST.Z instruction to the active function. +// Operates on the global context. +func VPABSD_BCST_Z(m, k, xyz operand.Op) { ctx.VPABSD_BCST_Z(m, k, xyz) } + +// VPABSD_Z: Packed Absolute Value of Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VPABSD.Z m128 k xmm +// VPABSD.Z m256 k ymm +// VPABSD.Z xmm k xmm +// VPABSD.Z ymm k ymm +// VPABSD.Z m512 k zmm +// VPABSD.Z zmm k zmm +// Construct and append a VPABSD.Z instruction to the active function. +func (c *Context) VPABSD_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPABSD_Z(mxyz, k, xyz)) +} + +// VPABSD_Z: Packed Absolute Value of Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VPABSD.Z m128 k xmm +// VPABSD.Z m256 k ymm +// VPABSD.Z xmm k xmm +// VPABSD.Z ymm k ymm +// VPABSD.Z m512 k zmm +// VPABSD.Z zmm k zmm +// Construct and append a VPABSD.Z instruction to the active function. +// Operates on the global context. +func VPABSD_Z(mxyz, k, xyz operand.Op) { ctx.VPABSD_Z(mxyz, k, xyz) } + +// VPABSQ: Packed Absolute Value of Quadword Integers. +// +// Forms: +// +// VPABSQ m128 k xmm +// VPABSQ m128 xmm +// VPABSQ m256 k ymm +// VPABSQ m256 ymm +// VPABSQ xmm k xmm +// VPABSQ xmm xmm +// VPABSQ ymm k ymm +// VPABSQ ymm ymm +// VPABSQ m512 k zmm +// VPABSQ m512 zmm +// VPABSQ zmm k zmm +// VPABSQ zmm zmm +// Construct and append a VPABSQ instruction to the active function. +func (c *Context) VPABSQ(ops ...operand.Op) { + c.addinstruction(x86.VPABSQ(ops...)) +} + +// VPABSQ: Packed Absolute Value of Quadword Integers. +// +// Forms: +// +// VPABSQ m128 k xmm +// VPABSQ m128 xmm +// VPABSQ m256 k ymm +// VPABSQ m256 ymm +// VPABSQ xmm k xmm +// VPABSQ xmm xmm +// VPABSQ ymm k ymm +// VPABSQ ymm ymm +// VPABSQ m512 k zmm +// VPABSQ m512 zmm +// VPABSQ zmm k zmm +// VPABSQ zmm zmm +// Construct and append a VPABSQ instruction to the active function. +// Operates on the global context. +func VPABSQ(ops ...operand.Op) { ctx.VPABSQ(ops...) } + +// VPABSQ_BCST: Packed Absolute Value of Quadword Integers (Broadcast). +// +// Forms: +// +// VPABSQ.BCST m64 k xmm +// VPABSQ.BCST m64 k ymm +// VPABSQ.BCST m64 xmm +// VPABSQ.BCST m64 ymm +// VPABSQ.BCST m64 k zmm +// VPABSQ.BCST m64 zmm +// Construct and append a VPABSQ.BCST instruction to the active function. +func (c *Context) VPABSQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPABSQ_BCST(ops...)) +} + +// VPABSQ_BCST: Packed Absolute Value of Quadword Integers (Broadcast). +// +// Forms: +// +// VPABSQ.BCST m64 k xmm +// VPABSQ.BCST m64 k ymm +// VPABSQ.BCST m64 xmm +// VPABSQ.BCST m64 ymm +// VPABSQ.BCST m64 k zmm +// VPABSQ.BCST m64 zmm +// Construct and append a VPABSQ.BCST instruction to the active function. +// Operates on the global context. +func VPABSQ_BCST(ops ...operand.Op) { ctx.VPABSQ_BCST(ops...) } + +// VPABSQ_BCST_Z: Packed Absolute Value of Quadword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPABSQ.BCST.Z m64 k xmm +// VPABSQ.BCST.Z m64 k ymm +// VPABSQ.BCST.Z m64 k zmm +// Construct and append a VPABSQ.BCST.Z instruction to the active function. +func (c *Context) VPABSQ_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VPABSQ_BCST_Z(m, k, xyz)) +} + +// VPABSQ_BCST_Z: Packed Absolute Value of Quadword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPABSQ.BCST.Z m64 k xmm +// VPABSQ.BCST.Z m64 k ymm +// VPABSQ.BCST.Z m64 k zmm +// Construct and append a VPABSQ.BCST.Z instruction to the active function. +// Operates on the global context. +func VPABSQ_BCST_Z(m, k, xyz operand.Op) { ctx.VPABSQ_BCST_Z(m, k, xyz) } + +// VPABSQ_Z: Packed Absolute Value of Quadword Integers (Zeroing Masking). +// +// Forms: +// +// VPABSQ.Z m128 k xmm +// VPABSQ.Z m256 k ymm +// VPABSQ.Z xmm k xmm +// VPABSQ.Z ymm k ymm +// VPABSQ.Z m512 k zmm +// VPABSQ.Z zmm k zmm +// Construct and append a VPABSQ.Z instruction to the active function. +func (c *Context) VPABSQ_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPABSQ_Z(mxyz, k, xyz)) +} + +// VPABSQ_Z: Packed Absolute Value of Quadword Integers (Zeroing Masking). +// +// Forms: +// +// VPABSQ.Z m128 k xmm +// VPABSQ.Z m256 k ymm +// VPABSQ.Z xmm k xmm +// VPABSQ.Z ymm k ymm +// VPABSQ.Z m512 k zmm +// VPABSQ.Z zmm k zmm +// Construct and append a VPABSQ.Z instruction to the active function. +// Operates on the global context. +func VPABSQ_Z(mxyz, k, xyz operand.Op) { ctx.VPABSQ_Z(mxyz, k, xyz) } + +// VPABSW: Packed Absolute Value of Word Integers. +// +// Forms: +// +// VPABSW m256 ymm +// VPABSW ymm ymm +// VPABSW m128 xmm +// VPABSW xmm xmm +// VPABSW m128 k xmm +// VPABSW m256 k ymm +// VPABSW xmm k xmm +// VPABSW ymm k ymm +// VPABSW m512 k zmm +// VPABSW m512 zmm +// VPABSW zmm k zmm +// VPABSW zmm zmm +// Construct and append a VPABSW instruction to the active function. +func (c *Context) VPABSW(ops ...operand.Op) { + c.addinstruction(x86.VPABSW(ops...)) +} + +// VPABSW: Packed Absolute Value of Word Integers. +// +// Forms: +// +// VPABSW m256 ymm +// VPABSW ymm ymm +// VPABSW m128 xmm +// VPABSW xmm xmm +// VPABSW m128 k xmm +// VPABSW m256 k ymm +// VPABSW xmm k xmm +// VPABSW ymm k ymm +// VPABSW m512 k zmm +// VPABSW m512 zmm +// VPABSW zmm k zmm +// VPABSW zmm zmm +// Construct and append a VPABSW instruction to the active function. +// Operates on the global context. +func VPABSW(ops ...operand.Op) { ctx.VPABSW(ops...) } + +// VPABSW_Z: Packed Absolute Value of Word Integers (Zeroing Masking). +// +// Forms: +// +// VPABSW.Z m128 k xmm +// VPABSW.Z m256 k ymm +// VPABSW.Z xmm k xmm +// VPABSW.Z ymm k ymm +// VPABSW.Z m512 k zmm +// VPABSW.Z zmm k zmm +// Construct and append a VPABSW.Z instruction to the active function. +func (c *Context) VPABSW_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPABSW_Z(mxyz, k, xyz)) +} + +// VPABSW_Z: Packed Absolute Value of Word Integers (Zeroing Masking). +// +// Forms: +// +// VPABSW.Z m128 k xmm +// VPABSW.Z m256 k ymm +// VPABSW.Z xmm k xmm +// VPABSW.Z ymm k ymm +// VPABSW.Z m512 k zmm +// VPABSW.Z zmm k zmm +// Construct and append a VPABSW.Z instruction to the active function. +// Operates on the global context. +func VPABSW_Z(mxyz, k, xyz operand.Op) { ctx.VPABSW_Z(mxyz, k, xyz) } + +// VPACKSSDW: Pack Doublewords into Words with Signed Saturation. +// +// Forms: +// +// VPACKSSDW m256 ymm ymm +// VPACKSSDW ymm ymm ymm +// VPACKSSDW m128 xmm xmm +// VPACKSSDW xmm xmm xmm +// VPACKSSDW m128 xmm k xmm +// VPACKSSDW m256 ymm k ymm +// VPACKSSDW xmm xmm k xmm +// VPACKSSDW ymm ymm k ymm +// VPACKSSDW m512 zmm k zmm +// VPACKSSDW m512 zmm zmm +// VPACKSSDW zmm zmm k zmm +// VPACKSSDW zmm zmm zmm +// Construct and append a VPACKSSDW instruction to the active function. +func (c *Context) VPACKSSDW(ops ...operand.Op) { + c.addinstruction(x86.VPACKSSDW(ops...)) +} + +// VPACKSSDW: Pack Doublewords into Words with Signed Saturation. +// +// Forms: +// +// VPACKSSDW m256 ymm ymm +// VPACKSSDW ymm ymm ymm +// VPACKSSDW m128 xmm xmm +// VPACKSSDW xmm xmm xmm +// VPACKSSDW m128 xmm k xmm +// VPACKSSDW m256 ymm k ymm +// VPACKSSDW xmm xmm k xmm +// VPACKSSDW ymm ymm k ymm +// VPACKSSDW m512 zmm k zmm +// VPACKSSDW m512 zmm zmm +// VPACKSSDW zmm zmm k zmm +// VPACKSSDW zmm zmm zmm +// Construct and append a VPACKSSDW instruction to the active function. +// Operates on the global context. +func VPACKSSDW(ops ...operand.Op) { ctx.VPACKSSDW(ops...) } + +// VPACKSSDW_BCST: Pack Doublewords into Words with Signed Saturation (Broadcast). +// +// Forms: +// +// VPACKSSDW.BCST m32 xmm k xmm +// VPACKSSDW.BCST m32 xmm xmm +// VPACKSSDW.BCST m32 ymm k ymm +// VPACKSSDW.BCST m32 ymm ymm +// VPACKSSDW.BCST m32 zmm k zmm +// VPACKSSDW.BCST m32 zmm zmm +// Construct and append a VPACKSSDW.BCST instruction to the active function. +func (c *Context) VPACKSSDW_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPACKSSDW_BCST(ops...)) +} + +// VPACKSSDW_BCST: Pack Doublewords into Words with Signed Saturation (Broadcast). +// +// Forms: +// +// VPACKSSDW.BCST m32 xmm k xmm +// VPACKSSDW.BCST m32 xmm xmm +// VPACKSSDW.BCST m32 ymm k ymm +// VPACKSSDW.BCST m32 ymm ymm +// VPACKSSDW.BCST m32 zmm k zmm +// VPACKSSDW.BCST m32 zmm zmm +// Construct and append a VPACKSSDW.BCST instruction to the active function. +// Operates on the global context. +func VPACKSSDW_BCST(ops ...operand.Op) { ctx.VPACKSSDW_BCST(ops...) } + +// VPACKSSDW_BCST_Z: Pack Doublewords into Words with Signed Saturation (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPACKSSDW.BCST.Z m32 xmm k xmm +// VPACKSSDW.BCST.Z m32 ymm k ymm +// VPACKSSDW.BCST.Z m32 zmm k zmm +// Construct and append a VPACKSSDW.BCST.Z instruction to the active function. +func (c *Context) VPACKSSDW_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPACKSSDW_BCST_Z(m, xyz, k, xyz1)) +} + +// VPACKSSDW_BCST_Z: Pack Doublewords into Words with Signed Saturation (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPACKSSDW.BCST.Z m32 xmm k xmm +// VPACKSSDW.BCST.Z m32 ymm k ymm +// VPACKSSDW.BCST.Z m32 zmm k zmm +// Construct and append a VPACKSSDW.BCST.Z instruction to the active function. +// Operates on the global context. +func VPACKSSDW_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPACKSSDW_BCST_Z(m, xyz, k, xyz1) } + +// VPACKSSDW_Z: Pack Doublewords into Words with Signed Saturation (Zeroing Masking). +// +// Forms: +// +// VPACKSSDW.Z m128 xmm k xmm +// VPACKSSDW.Z m256 ymm k ymm +// VPACKSSDW.Z xmm xmm k xmm +// VPACKSSDW.Z ymm ymm k ymm +// VPACKSSDW.Z m512 zmm k zmm +// VPACKSSDW.Z zmm zmm k zmm +// Construct and append a VPACKSSDW.Z instruction to the active function. +func (c *Context) VPACKSSDW_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPACKSSDW_Z(mxyz, xyz, k, xyz1)) +} + +// VPACKSSDW_Z: Pack Doublewords into Words with Signed Saturation (Zeroing Masking). +// +// Forms: +// +// VPACKSSDW.Z m128 xmm k xmm +// VPACKSSDW.Z m256 ymm k ymm +// VPACKSSDW.Z xmm xmm k xmm +// VPACKSSDW.Z ymm ymm k ymm +// VPACKSSDW.Z m512 zmm k zmm +// VPACKSSDW.Z zmm zmm k zmm +// Construct and append a VPACKSSDW.Z instruction to the active function. +// Operates on the global context. +func VPACKSSDW_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPACKSSDW_Z(mxyz, xyz, k, xyz1) } + +// VPACKSSWB: Pack Words into Bytes with Signed Saturation. +// +// Forms: +// +// VPACKSSWB m256 ymm ymm +// VPACKSSWB ymm ymm ymm +// VPACKSSWB m128 xmm xmm +// VPACKSSWB xmm xmm xmm +// VPACKSSWB m128 xmm k xmm +// VPACKSSWB m256 ymm k ymm +// VPACKSSWB xmm xmm k xmm +// VPACKSSWB ymm ymm k ymm +// VPACKSSWB m512 zmm k zmm +// VPACKSSWB m512 zmm zmm +// VPACKSSWB zmm zmm k zmm +// VPACKSSWB zmm zmm zmm +// Construct and append a VPACKSSWB instruction to the active function. +func (c *Context) VPACKSSWB(ops ...operand.Op) { + c.addinstruction(x86.VPACKSSWB(ops...)) +} + +// VPACKSSWB: Pack Words into Bytes with Signed Saturation. +// +// Forms: +// +// VPACKSSWB m256 ymm ymm +// VPACKSSWB ymm ymm ymm +// VPACKSSWB m128 xmm xmm +// VPACKSSWB xmm xmm xmm +// VPACKSSWB m128 xmm k xmm +// VPACKSSWB m256 ymm k ymm +// VPACKSSWB xmm xmm k xmm +// VPACKSSWB ymm ymm k ymm +// VPACKSSWB m512 zmm k zmm +// VPACKSSWB m512 zmm zmm +// VPACKSSWB zmm zmm k zmm +// VPACKSSWB zmm zmm zmm +// Construct and append a VPACKSSWB instruction to the active function. +// Operates on the global context. +func VPACKSSWB(ops ...operand.Op) { ctx.VPACKSSWB(ops...) } + +// VPACKSSWB_Z: Pack Words into Bytes with Signed Saturation (Zeroing Masking). +// +// Forms: +// +// VPACKSSWB.Z m128 xmm k xmm +// VPACKSSWB.Z m256 ymm k ymm +// VPACKSSWB.Z xmm xmm k xmm +// VPACKSSWB.Z ymm ymm k ymm +// VPACKSSWB.Z m512 zmm k zmm +// VPACKSSWB.Z zmm zmm k zmm +// Construct and append a VPACKSSWB.Z instruction to the active function. +func (c *Context) VPACKSSWB_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPACKSSWB_Z(mxyz, xyz, k, xyz1)) +} + +// VPACKSSWB_Z: Pack Words into Bytes with Signed Saturation (Zeroing Masking). +// +// Forms: +// +// VPACKSSWB.Z m128 xmm k xmm +// VPACKSSWB.Z m256 ymm k ymm +// VPACKSSWB.Z xmm xmm k xmm +// VPACKSSWB.Z ymm ymm k ymm +// VPACKSSWB.Z m512 zmm k zmm +// VPACKSSWB.Z zmm zmm k zmm +// Construct and append a VPACKSSWB.Z instruction to the active function. +// Operates on the global context. +func VPACKSSWB_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPACKSSWB_Z(mxyz, xyz, k, xyz1) } + +// VPACKUSDW: Pack Doublewords into Words with Unsigned Saturation. +// +// Forms: +// +// VPACKUSDW m256 ymm ymm +// VPACKUSDW ymm ymm ymm +// VPACKUSDW m128 xmm xmm +// VPACKUSDW xmm xmm xmm +// VPACKUSDW m128 xmm k xmm +// VPACKUSDW m256 ymm k ymm +// VPACKUSDW xmm xmm k xmm +// VPACKUSDW ymm ymm k ymm +// VPACKUSDW m512 zmm k zmm +// VPACKUSDW m512 zmm zmm +// VPACKUSDW zmm zmm k zmm +// VPACKUSDW zmm zmm zmm +// Construct and append a VPACKUSDW instruction to the active function. +func (c *Context) VPACKUSDW(ops ...operand.Op) { + c.addinstruction(x86.VPACKUSDW(ops...)) +} + +// VPACKUSDW: Pack Doublewords into Words with Unsigned Saturation. +// +// Forms: +// +// VPACKUSDW m256 ymm ymm +// VPACKUSDW ymm ymm ymm +// VPACKUSDW m128 xmm xmm +// VPACKUSDW xmm xmm xmm +// VPACKUSDW m128 xmm k xmm +// VPACKUSDW m256 ymm k ymm +// VPACKUSDW xmm xmm k xmm +// VPACKUSDW ymm ymm k ymm +// VPACKUSDW m512 zmm k zmm +// VPACKUSDW m512 zmm zmm +// VPACKUSDW zmm zmm k zmm +// VPACKUSDW zmm zmm zmm +// Construct and append a VPACKUSDW instruction to the active function. +// Operates on the global context. +func VPACKUSDW(ops ...operand.Op) { ctx.VPACKUSDW(ops...) } + +// VPACKUSDW_BCST: Pack Doublewords into Words with Unsigned Saturation (Broadcast). +// +// Forms: +// +// VPACKUSDW.BCST m32 xmm k xmm +// VPACKUSDW.BCST m32 xmm xmm +// VPACKUSDW.BCST m32 ymm k ymm +// VPACKUSDW.BCST m32 ymm ymm +// VPACKUSDW.BCST m32 zmm k zmm +// VPACKUSDW.BCST m32 zmm zmm +// Construct and append a VPACKUSDW.BCST instruction to the active function. +func (c *Context) VPACKUSDW_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPACKUSDW_BCST(ops...)) +} + +// VPACKUSDW_BCST: Pack Doublewords into Words with Unsigned Saturation (Broadcast). +// +// Forms: +// +// VPACKUSDW.BCST m32 xmm k xmm +// VPACKUSDW.BCST m32 xmm xmm +// VPACKUSDW.BCST m32 ymm k ymm +// VPACKUSDW.BCST m32 ymm ymm +// VPACKUSDW.BCST m32 zmm k zmm +// VPACKUSDW.BCST m32 zmm zmm +// Construct and append a VPACKUSDW.BCST instruction to the active function. +// Operates on the global context. +func VPACKUSDW_BCST(ops ...operand.Op) { ctx.VPACKUSDW_BCST(ops...) } + +// VPACKUSDW_BCST_Z: Pack Doublewords into Words with Unsigned Saturation (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPACKUSDW.BCST.Z m32 xmm k xmm +// VPACKUSDW.BCST.Z m32 ymm k ymm +// VPACKUSDW.BCST.Z m32 zmm k zmm +// Construct and append a VPACKUSDW.BCST.Z instruction to the active function. +func (c *Context) VPACKUSDW_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPACKUSDW_BCST_Z(m, xyz, k, xyz1)) +} + +// VPACKUSDW_BCST_Z: Pack Doublewords into Words with Unsigned Saturation (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPACKUSDW.BCST.Z m32 xmm k xmm +// VPACKUSDW.BCST.Z m32 ymm k ymm +// VPACKUSDW.BCST.Z m32 zmm k zmm +// Construct and append a VPACKUSDW.BCST.Z instruction to the active function. +// Operates on the global context. +func VPACKUSDW_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPACKUSDW_BCST_Z(m, xyz, k, xyz1) } + +// VPACKUSDW_Z: Pack Doublewords into Words with Unsigned Saturation (Zeroing Masking). +// +// Forms: +// +// VPACKUSDW.Z m128 xmm k xmm +// VPACKUSDW.Z m256 ymm k ymm +// VPACKUSDW.Z xmm xmm k xmm +// VPACKUSDW.Z ymm ymm k ymm +// VPACKUSDW.Z m512 zmm k zmm +// VPACKUSDW.Z zmm zmm k zmm +// Construct and append a VPACKUSDW.Z instruction to the active function. +func (c *Context) VPACKUSDW_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPACKUSDW_Z(mxyz, xyz, k, xyz1)) +} + +// VPACKUSDW_Z: Pack Doublewords into Words with Unsigned Saturation (Zeroing Masking). +// +// Forms: +// +// VPACKUSDW.Z m128 xmm k xmm +// VPACKUSDW.Z m256 ymm k ymm +// VPACKUSDW.Z xmm xmm k xmm +// VPACKUSDW.Z ymm ymm k ymm +// VPACKUSDW.Z m512 zmm k zmm +// VPACKUSDW.Z zmm zmm k zmm +// Construct and append a VPACKUSDW.Z instruction to the active function. +// Operates on the global context. +func VPACKUSDW_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPACKUSDW_Z(mxyz, xyz, k, xyz1) } + +// VPACKUSWB: Pack Words into Bytes with Unsigned Saturation. +// +// Forms: +// +// VPACKUSWB m256 ymm ymm +// VPACKUSWB ymm ymm ymm +// VPACKUSWB m128 xmm xmm +// VPACKUSWB xmm xmm xmm +// VPACKUSWB m128 xmm k xmm +// VPACKUSWB m256 ymm k ymm +// VPACKUSWB xmm xmm k xmm +// VPACKUSWB ymm ymm k ymm +// VPACKUSWB m512 zmm k zmm +// VPACKUSWB m512 zmm zmm +// VPACKUSWB zmm zmm k zmm +// VPACKUSWB zmm zmm zmm +// Construct and append a VPACKUSWB instruction to the active function. +func (c *Context) VPACKUSWB(ops ...operand.Op) { + c.addinstruction(x86.VPACKUSWB(ops...)) +} + +// VPACKUSWB: Pack Words into Bytes with Unsigned Saturation. +// +// Forms: +// +// VPACKUSWB m256 ymm ymm +// VPACKUSWB ymm ymm ymm +// VPACKUSWB m128 xmm xmm +// VPACKUSWB xmm xmm xmm +// VPACKUSWB m128 xmm k xmm +// VPACKUSWB m256 ymm k ymm +// VPACKUSWB xmm xmm k xmm +// VPACKUSWB ymm ymm k ymm +// VPACKUSWB m512 zmm k zmm +// VPACKUSWB m512 zmm zmm +// VPACKUSWB zmm zmm k zmm +// VPACKUSWB zmm zmm zmm +// Construct and append a VPACKUSWB instruction to the active function. +// Operates on the global context. +func VPACKUSWB(ops ...operand.Op) { ctx.VPACKUSWB(ops...) } + +// VPACKUSWB_Z: Pack Words into Bytes with Unsigned Saturation (Zeroing Masking). +// +// Forms: +// +// VPACKUSWB.Z m128 xmm k xmm +// VPACKUSWB.Z m256 ymm k ymm +// VPACKUSWB.Z xmm xmm k xmm +// VPACKUSWB.Z ymm ymm k ymm +// VPACKUSWB.Z m512 zmm k zmm +// VPACKUSWB.Z zmm zmm k zmm +// Construct and append a VPACKUSWB.Z instruction to the active function. +func (c *Context) VPACKUSWB_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPACKUSWB_Z(mxyz, xyz, k, xyz1)) +} + +// VPACKUSWB_Z: Pack Words into Bytes with Unsigned Saturation (Zeroing Masking). +// +// Forms: +// +// VPACKUSWB.Z m128 xmm k xmm +// VPACKUSWB.Z m256 ymm k ymm +// VPACKUSWB.Z xmm xmm k xmm +// VPACKUSWB.Z ymm ymm k ymm +// VPACKUSWB.Z m512 zmm k zmm +// VPACKUSWB.Z zmm zmm k zmm +// Construct and append a VPACKUSWB.Z instruction to the active function. +// Operates on the global context. +func VPACKUSWB_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPACKUSWB_Z(mxyz, xyz, k, xyz1) } + +// VPADDB: Add Packed Byte Integers. +// +// Forms: +// +// VPADDB m256 ymm ymm +// VPADDB ymm ymm ymm +// VPADDB m128 xmm xmm +// VPADDB xmm xmm xmm +// VPADDB m128 xmm k xmm +// VPADDB m256 ymm k ymm +// VPADDB xmm xmm k xmm +// VPADDB ymm ymm k ymm +// VPADDB m512 zmm k zmm +// VPADDB m512 zmm zmm +// VPADDB zmm zmm k zmm +// VPADDB zmm zmm zmm +// Construct and append a VPADDB instruction to the active function. +func (c *Context) VPADDB(ops ...operand.Op) { + c.addinstruction(x86.VPADDB(ops...)) +} + +// VPADDB: Add Packed Byte Integers. +// +// Forms: +// +// VPADDB m256 ymm ymm +// VPADDB ymm ymm ymm +// VPADDB m128 xmm xmm +// VPADDB xmm xmm xmm +// VPADDB m128 xmm k xmm +// VPADDB m256 ymm k ymm +// VPADDB xmm xmm k xmm +// VPADDB ymm ymm k ymm +// VPADDB m512 zmm k zmm +// VPADDB m512 zmm zmm +// VPADDB zmm zmm k zmm +// VPADDB zmm zmm zmm +// Construct and append a VPADDB instruction to the active function. +// Operates on the global context. +func VPADDB(ops ...operand.Op) { ctx.VPADDB(ops...) } + +// VPADDB_Z: Add Packed Byte Integers (Zeroing Masking). +// +// Forms: +// +// VPADDB.Z m128 xmm k xmm +// VPADDB.Z m256 ymm k ymm +// VPADDB.Z xmm xmm k xmm +// VPADDB.Z ymm ymm k ymm +// VPADDB.Z m512 zmm k zmm +// VPADDB.Z zmm zmm k zmm +// Construct and append a VPADDB.Z instruction to the active function. +func (c *Context) VPADDB_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPADDB_Z(mxyz, xyz, k, xyz1)) +} + +// VPADDB_Z: Add Packed Byte Integers (Zeroing Masking). +// +// Forms: +// +// VPADDB.Z m128 xmm k xmm +// VPADDB.Z m256 ymm k ymm +// VPADDB.Z xmm xmm k xmm +// VPADDB.Z ymm ymm k ymm +// VPADDB.Z m512 zmm k zmm +// VPADDB.Z zmm zmm k zmm +// Construct and append a VPADDB.Z instruction to the active function. +// Operates on the global context. +func VPADDB_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPADDB_Z(mxyz, xyz, k, xyz1) } + +// VPADDD: Add Packed Doubleword Integers. +// +// Forms: +// +// VPADDD m256 ymm ymm +// VPADDD ymm ymm ymm +// VPADDD m128 xmm xmm +// VPADDD xmm xmm xmm +// VPADDD m128 xmm k xmm +// VPADDD m256 ymm k ymm +// VPADDD xmm xmm k xmm +// VPADDD ymm ymm k ymm +// VPADDD m512 zmm k zmm +// VPADDD m512 zmm zmm +// VPADDD zmm zmm k zmm +// VPADDD zmm zmm zmm +// Construct and append a VPADDD instruction to the active function. +func (c *Context) VPADDD(ops ...operand.Op) { + c.addinstruction(x86.VPADDD(ops...)) +} + +// VPADDD: Add Packed Doubleword Integers. +// +// Forms: +// +// VPADDD m256 ymm ymm +// VPADDD ymm ymm ymm +// VPADDD m128 xmm xmm +// VPADDD xmm xmm xmm +// VPADDD m128 xmm k xmm +// VPADDD m256 ymm k ymm +// VPADDD xmm xmm k xmm +// VPADDD ymm ymm k ymm +// VPADDD m512 zmm k zmm +// VPADDD m512 zmm zmm +// VPADDD zmm zmm k zmm +// VPADDD zmm zmm zmm +// Construct and append a VPADDD instruction to the active function. +// Operates on the global context. +func VPADDD(ops ...operand.Op) { ctx.VPADDD(ops...) } + +// VPADDD_BCST: Add Packed Doubleword Integers (Broadcast). +// +// Forms: +// +// VPADDD.BCST m32 xmm k xmm +// VPADDD.BCST m32 xmm xmm +// VPADDD.BCST m32 ymm k ymm +// VPADDD.BCST m32 ymm ymm +// VPADDD.BCST m32 zmm k zmm +// VPADDD.BCST m32 zmm zmm +// Construct and append a VPADDD.BCST instruction to the active function. +func (c *Context) VPADDD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPADDD_BCST(ops...)) +} + +// VPADDD_BCST: Add Packed Doubleword Integers (Broadcast). +// +// Forms: +// +// VPADDD.BCST m32 xmm k xmm +// VPADDD.BCST m32 xmm xmm +// VPADDD.BCST m32 ymm k ymm +// VPADDD.BCST m32 ymm ymm +// VPADDD.BCST m32 zmm k zmm +// VPADDD.BCST m32 zmm zmm +// Construct and append a VPADDD.BCST instruction to the active function. +// Operates on the global context. +func VPADDD_BCST(ops ...operand.Op) { ctx.VPADDD_BCST(ops...) } + +// VPADDD_BCST_Z: Add Packed Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPADDD.BCST.Z m32 xmm k xmm +// VPADDD.BCST.Z m32 ymm k ymm +// VPADDD.BCST.Z m32 zmm k zmm +// Construct and append a VPADDD.BCST.Z instruction to the active function. +func (c *Context) VPADDD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPADDD_BCST_Z(m, xyz, k, xyz1)) +} + +// VPADDD_BCST_Z: Add Packed Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPADDD.BCST.Z m32 xmm k xmm +// VPADDD.BCST.Z m32 ymm k ymm +// VPADDD.BCST.Z m32 zmm k zmm +// Construct and append a VPADDD.BCST.Z instruction to the active function. +// Operates on the global context. +func VPADDD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPADDD_BCST_Z(m, xyz, k, xyz1) } + +// VPADDD_Z: Add Packed Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VPADDD.Z m128 xmm k xmm +// VPADDD.Z m256 ymm k ymm +// VPADDD.Z xmm xmm k xmm +// VPADDD.Z ymm ymm k ymm +// VPADDD.Z m512 zmm k zmm +// VPADDD.Z zmm zmm k zmm +// Construct and append a VPADDD.Z instruction to the active function. +func (c *Context) VPADDD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPADDD_Z(mxyz, xyz, k, xyz1)) +} + +// VPADDD_Z: Add Packed Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VPADDD.Z m128 xmm k xmm +// VPADDD.Z m256 ymm k ymm +// VPADDD.Z xmm xmm k xmm +// VPADDD.Z ymm ymm k ymm +// VPADDD.Z m512 zmm k zmm +// VPADDD.Z zmm zmm k zmm +// Construct and append a VPADDD.Z instruction to the active function. +// Operates on the global context. +func VPADDD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPADDD_Z(mxyz, xyz, k, xyz1) } + +// VPADDQ: Add Packed Quadword Integers. +// +// Forms: +// +// VPADDQ m256 ymm ymm +// VPADDQ ymm ymm ymm +// VPADDQ m128 xmm xmm +// VPADDQ xmm xmm xmm +// VPADDQ m128 xmm k xmm +// VPADDQ m256 ymm k ymm +// VPADDQ xmm xmm k xmm +// VPADDQ ymm ymm k ymm +// VPADDQ m512 zmm k zmm +// VPADDQ m512 zmm zmm +// VPADDQ zmm zmm k zmm +// VPADDQ zmm zmm zmm +// Construct and append a VPADDQ instruction to the active function. +func (c *Context) VPADDQ(ops ...operand.Op) { + c.addinstruction(x86.VPADDQ(ops...)) +} + +// VPADDQ: Add Packed Quadword Integers. +// +// Forms: +// +// VPADDQ m256 ymm ymm +// VPADDQ ymm ymm ymm +// VPADDQ m128 xmm xmm +// VPADDQ xmm xmm xmm +// VPADDQ m128 xmm k xmm +// VPADDQ m256 ymm k ymm +// VPADDQ xmm xmm k xmm +// VPADDQ ymm ymm k ymm +// VPADDQ m512 zmm k zmm +// VPADDQ m512 zmm zmm +// VPADDQ zmm zmm k zmm +// VPADDQ zmm zmm zmm +// Construct and append a VPADDQ instruction to the active function. +// Operates on the global context. +func VPADDQ(ops ...operand.Op) { ctx.VPADDQ(ops...) } + +// VPADDQ_BCST: Add Packed Quadword Integers (Broadcast). +// +// Forms: +// +// VPADDQ.BCST m64 xmm k xmm +// VPADDQ.BCST m64 xmm xmm +// VPADDQ.BCST m64 ymm k ymm +// VPADDQ.BCST m64 ymm ymm +// VPADDQ.BCST m64 zmm k zmm +// VPADDQ.BCST m64 zmm zmm +// Construct and append a VPADDQ.BCST instruction to the active function. +func (c *Context) VPADDQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPADDQ_BCST(ops...)) +} + +// VPADDQ_BCST: Add Packed Quadword Integers (Broadcast). +// +// Forms: +// +// VPADDQ.BCST m64 xmm k xmm +// VPADDQ.BCST m64 xmm xmm +// VPADDQ.BCST m64 ymm k ymm +// VPADDQ.BCST m64 ymm ymm +// VPADDQ.BCST m64 zmm k zmm +// VPADDQ.BCST m64 zmm zmm +// Construct and append a VPADDQ.BCST instruction to the active function. +// Operates on the global context. +func VPADDQ_BCST(ops ...operand.Op) { ctx.VPADDQ_BCST(ops...) } + +// VPADDQ_BCST_Z: Add Packed Quadword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPADDQ.BCST.Z m64 xmm k xmm +// VPADDQ.BCST.Z m64 ymm k ymm +// VPADDQ.BCST.Z m64 zmm k zmm +// Construct and append a VPADDQ.BCST.Z instruction to the active function. +func (c *Context) VPADDQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPADDQ_BCST_Z(m, xyz, k, xyz1)) +} + +// VPADDQ_BCST_Z: Add Packed Quadword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPADDQ.BCST.Z m64 xmm k xmm +// VPADDQ.BCST.Z m64 ymm k ymm +// VPADDQ.BCST.Z m64 zmm k zmm +// Construct and append a VPADDQ.BCST.Z instruction to the active function. +// Operates on the global context. +func VPADDQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPADDQ_BCST_Z(m, xyz, k, xyz1) } + +// VPADDQ_Z: Add Packed Quadword Integers (Zeroing Masking). +// +// Forms: +// +// VPADDQ.Z m128 xmm k xmm +// VPADDQ.Z m256 ymm k ymm +// VPADDQ.Z xmm xmm k xmm +// VPADDQ.Z ymm ymm k ymm +// VPADDQ.Z m512 zmm k zmm +// VPADDQ.Z zmm zmm k zmm +// Construct and append a VPADDQ.Z instruction to the active function. +func (c *Context) VPADDQ_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPADDQ_Z(mxyz, xyz, k, xyz1)) +} + +// VPADDQ_Z: Add Packed Quadword Integers (Zeroing Masking). +// +// Forms: +// +// VPADDQ.Z m128 xmm k xmm +// VPADDQ.Z m256 ymm k ymm +// VPADDQ.Z xmm xmm k xmm +// VPADDQ.Z ymm ymm k ymm +// VPADDQ.Z m512 zmm k zmm +// VPADDQ.Z zmm zmm k zmm +// Construct and append a VPADDQ.Z instruction to the active function. +// Operates on the global context. +func VPADDQ_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPADDQ_Z(mxyz, xyz, k, xyz1) } + +// VPADDSB: Add Packed Signed Byte Integers with Signed Saturation. +// +// Forms: +// +// VPADDSB m256 ymm ymm +// VPADDSB ymm ymm ymm +// VPADDSB m128 xmm xmm +// VPADDSB xmm xmm xmm +// VPADDSB m128 xmm k xmm +// VPADDSB m256 ymm k ymm +// VPADDSB xmm xmm k xmm +// VPADDSB ymm ymm k ymm +// VPADDSB m512 zmm k zmm +// VPADDSB m512 zmm zmm +// VPADDSB zmm zmm k zmm +// VPADDSB zmm zmm zmm +// Construct and append a VPADDSB instruction to the active function. +func (c *Context) VPADDSB(ops ...operand.Op) { + c.addinstruction(x86.VPADDSB(ops...)) +} + +// VPADDSB: Add Packed Signed Byte Integers with Signed Saturation. +// +// Forms: +// +// VPADDSB m256 ymm ymm +// VPADDSB ymm ymm ymm +// VPADDSB m128 xmm xmm +// VPADDSB xmm xmm xmm +// VPADDSB m128 xmm k xmm +// VPADDSB m256 ymm k ymm +// VPADDSB xmm xmm k xmm +// VPADDSB ymm ymm k ymm +// VPADDSB m512 zmm k zmm +// VPADDSB m512 zmm zmm +// VPADDSB zmm zmm k zmm +// VPADDSB zmm zmm zmm +// Construct and append a VPADDSB instruction to the active function. +// Operates on the global context. +func VPADDSB(ops ...operand.Op) { ctx.VPADDSB(ops...) } + +// VPADDSB_Z: Add Packed Signed Byte Integers with Signed Saturation (Zeroing Masking). +// +// Forms: +// +// VPADDSB.Z m128 xmm k xmm +// VPADDSB.Z m256 ymm k ymm +// VPADDSB.Z xmm xmm k xmm +// VPADDSB.Z ymm ymm k ymm +// VPADDSB.Z m512 zmm k zmm +// VPADDSB.Z zmm zmm k zmm +// Construct and append a VPADDSB.Z instruction to the active function. +func (c *Context) VPADDSB_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPADDSB_Z(mxyz, xyz, k, xyz1)) +} + +// VPADDSB_Z: Add Packed Signed Byte Integers with Signed Saturation (Zeroing Masking). +// +// Forms: +// +// VPADDSB.Z m128 xmm k xmm +// VPADDSB.Z m256 ymm k ymm +// VPADDSB.Z xmm xmm k xmm +// VPADDSB.Z ymm ymm k ymm +// VPADDSB.Z m512 zmm k zmm +// VPADDSB.Z zmm zmm k zmm +// Construct and append a VPADDSB.Z instruction to the active function. +// Operates on the global context. +func VPADDSB_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPADDSB_Z(mxyz, xyz, k, xyz1) } + +// VPADDSW: Add Packed Signed Word Integers with Signed Saturation. +// +// Forms: +// +// VPADDSW m256 ymm ymm +// VPADDSW ymm ymm ymm +// VPADDSW m128 xmm xmm +// VPADDSW xmm xmm xmm +// VPADDSW m128 xmm k xmm +// VPADDSW m256 ymm k ymm +// VPADDSW xmm xmm k xmm +// VPADDSW ymm ymm k ymm +// VPADDSW m512 zmm k zmm +// VPADDSW m512 zmm zmm +// VPADDSW zmm zmm k zmm +// VPADDSW zmm zmm zmm +// Construct and append a VPADDSW instruction to the active function. +func (c *Context) VPADDSW(ops ...operand.Op) { + c.addinstruction(x86.VPADDSW(ops...)) +} + +// VPADDSW: Add Packed Signed Word Integers with Signed Saturation. +// +// Forms: +// +// VPADDSW m256 ymm ymm +// VPADDSW ymm ymm ymm +// VPADDSW m128 xmm xmm +// VPADDSW xmm xmm xmm +// VPADDSW m128 xmm k xmm +// VPADDSW m256 ymm k ymm +// VPADDSW xmm xmm k xmm +// VPADDSW ymm ymm k ymm +// VPADDSW m512 zmm k zmm +// VPADDSW m512 zmm zmm +// VPADDSW zmm zmm k zmm +// VPADDSW zmm zmm zmm +// Construct and append a VPADDSW instruction to the active function. +// Operates on the global context. +func VPADDSW(ops ...operand.Op) { ctx.VPADDSW(ops...) } + +// VPADDSW_Z: Add Packed Signed Word Integers with Signed Saturation (Zeroing Masking). +// +// Forms: +// +// VPADDSW.Z m128 xmm k xmm +// VPADDSW.Z m256 ymm k ymm +// VPADDSW.Z xmm xmm k xmm +// VPADDSW.Z ymm ymm k ymm +// VPADDSW.Z m512 zmm k zmm +// VPADDSW.Z zmm zmm k zmm +// Construct and append a VPADDSW.Z instruction to the active function. +func (c *Context) VPADDSW_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPADDSW_Z(mxyz, xyz, k, xyz1)) +} + +// VPADDSW_Z: Add Packed Signed Word Integers with Signed Saturation (Zeroing Masking). +// +// Forms: +// +// VPADDSW.Z m128 xmm k xmm +// VPADDSW.Z m256 ymm k ymm +// VPADDSW.Z xmm xmm k xmm +// VPADDSW.Z ymm ymm k ymm +// VPADDSW.Z m512 zmm k zmm +// VPADDSW.Z zmm zmm k zmm +// Construct and append a VPADDSW.Z instruction to the active function. +// Operates on the global context. +func VPADDSW_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPADDSW_Z(mxyz, xyz, k, xyz1) } + +// VPADDUSB: Add Packed Unsigned Byte Integers with Unsigned Saturation. +// +// Forms: +// +// VPADDUSB m256 ymm ymm +// VPADDUSB ymm ymm ymm +// VPADDUSB m128 xmm xmm +// VPADDUSB xmm xmm xmm +// VPADDUSB m128 xmm k xmm +// VPADDUSB m256 ymm k ymm +// VPADDUSB xmm xmm k xmm +// VPADDUSB ymm ymm k ymm +// VPADDUSB m512 zmm k zmm +// VPADDUSB m512 zmm zmm +// VPADDUSB zmm zmm k zmm +// VPADDUSB zmm zmm zmm +// Construct and append a VPADDUSB instruction to the active function. +func (c *Context) VPADDUSB(ops ...operand.Op) { + c.addinstruction(x86.VPADDUSB(ops...)) +} + +// VPADDUSB: Add Packed Unsigned Byte Integers with Unsigned Saturation. +// +// Forms: +// +// VPADDUSB m256 ymm ymm +// VPADDUSB ymm ymm ymm +// VPADDUSB m128 xmm xmm +// VPADDUSB xmm xmm xmm +// VPADDUSB m128 xmm k xmm +// VPADDUSB m256 ymm k ymm +// VPADDUSB xmm xmm k xmm +// VPADDUSB ymm ymm k ymm +// VPADDUSB m512 zmm k zmm +// VPADDUSB m512 zmm zmm +// VPADDUSB zmm zmm k zmm +// VPADDUSB zmm zmm zmm +// Construct and append a VPADDUSB instruction to the active function. +// Operates on the global context. +func VPADDUSB(ops ...operand.Op) { ctx.VPADDUSB(ops...) } + +// VPADDUSB_Z: Add Packed Unsigned Byte Integers with Unsigned Saturation (Zeroing Masking). +// +// Forms: +// +// VPADDUSB.Z m128 xmm k xmm +// VPADDUSB.Z m256 ymm k ymm +// VPADDUSB.Z xmm xmm k xmm +// VPADDUSB.Z ymm ymm k ymm +// VPADDUSB.Z m512 zmm k zmm +// VPADDUSB.Z zmm zmm k zmm +// Construct and append a VPADDUSB.Z instruction to the active function. +func (c *Context) VPADDUSB_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPADDUSB_Z(mxyz, xyz, k, xyz1)) +} + +// VPADDUSB_Z: Add Packed Unsigned Byte Integers with Unsigned Saturation (Zeroing Masking). +// +// Forms: +// +// VPADDUSB.Z m128 xmm k xmm +// VPADDUSB.Z m256 ymm k ymm +// VPADDUSB.Z xmm xmm k xmm +// VPADDUSB.Z ymm ymm k ymm +// VPADDUSB.Z m512 zmm k zmm +// VPADDUSB.Z zmm zmm k zmm +// Construct and append a VPADDUSB.Z instruction to the active function. +// Operates on the global context. +func VPADDUSB_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPADDUSB_Z(mxyz, xyz, k, xyz1) } + +// VPADDUSW: Add Packed Unsigned Word Integers with Unsigned Saturation. +// +// Forms: +// +// VPADDUSW m256 ymm ymm +// VPADDUSW ymm ymm ymm +// VPADDUSW m128 xmm xmm +// VPADDUSW xmm xmm xmm +// VPADDUSW m128 xmm k xmm +// VPADDUSW m256 ymm k ymm +// VPADDUSW xmm xmm k xmm +// VPADDUSW ymm ymm k ymm +// VPADDUSW m512 zmm k zmm +// VPADDUSW m512 zmm zmm +// VPADDUSW zmm zmm k zmm +// VPADDUSW zmm zmm zmm +// Construct and append a VPADDUSW instruction to the active function. +func (c *Context) VPADDUSW(ops ...operand.Op) { + c.addinstruction(x86.VPADDUSW(ops...)) +} + +// VPADDUSW: Add Packed Unsigned Word Integers with Unsigned Saturation. +// +// Forms: +// +// VPADDUSW m256 ymm ymm +// VPADDUSW ymm ymm ymm +// VPADDUSW m128 xmm xmm +// VPADDUSW xmm xmm xmm +// VPADDUSW m128 xmm k xmm +// VPADDUSW m256 ymm k ymm +// VPADDUSW xmm xmm k xmm +// VPADDUSW ymm ymm k ymm +// VPADDUSW m512 zmm k zmm +// VPADDUSW m512 zmm zmm +// VPADDUSW zmm zmm k zmm +// VPADDUSW zmm zmm zmm +// Construct and append a VPADDUSW instruction to the active function. +// Operates on the global context. +func VPADDUSW(ops ...operand.Op) { ctx.VPADDUSW(ops...) } + +// VPADDUSW_Z: Add Packed Unsigned Word Integers with Unsigned Saturation (Zeroing Masking). +// +// Forms: +// +// VPADDUSW.Z m128 xmm k xmm +// VPADDUSW.Z m256 ymm k ymm +// VPADDUSW.Z xmm xmm k xmm +// VPADDUSW.Z ymm ymm k ymm +// VPADDUSW.Z m512 zmm k zmm +// VPADDUSW.Z zmm zmm k zmm +// Construct and append a VPADDUSW.Z instruction to the active function. +func (c *Context) VPADDUSW_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPADDUSW_Z(mxyz, xyz, k, xyz1)) +} + +// VPADDUSW_Z: Add Packed Unsigned Word Integers with Unsigned Saturation (Zeroing Masking). +// +// Forms: +// +// VPADDUSW.Z m128 xmm k xmm +// VPADDUSW.Z m256 ymm k ymm +// VPADDUSW.Z xmm xmm k xmm +// VPADDUSW.Z ymm ymm k ymm +// VPADDUSW.Z m512 zmm k zmm +// VPADDUSW.Z zmm zmm k zmm +// Construct and append a VPADDUSW.Z instruction to the active function. +// Operates on the global context. +func VPADDUSW_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPADDUSW_Z(mxyz, xyz, k, xyz1) } + +// VPADDW: Add Packed Word Integers. +// +// Forms: +// +// VPADDW m256 ymm ymm +// VPADDW ymm ymm ymm +// VPADDW m128 xmm xmm +// VPADDW xmm xmm xmm +// VPADDW m128 xmm k xmm +// VPADDW m256 ymm k ymm +// VPADDW xmm xmm k xmm +// VPADDW ymm ymm k ymm +// VPADDW m512 zmm k zmm +// VPADDW m512 zmm zmm +// VPADDW zmm zmm k zmm +// VPADDW zmm zmm zmm +// Construct and append a VPADDW instruction to the active function. +func (c *Context) VPADDW(ops ...operand.Op) { + c.addinstruction(x86.VPADDW(ops...)) +} + +// VPADDW: Add Packed Word Integers. +// +// Forms: +// +// VPADDW m256 ymm ymm +// VPADDW ymm ymm ymm +// VPADDW m128 xmm xmm +// VPADDW xmm xmm xmm +// VPADDW m128 xmm k xmm +// VPADDW m256 ymm k ymm +// VPADDW xmm xmm k xmm +// VPADDW ymm ymm k ymm +// VPADDW m512 zmm k zmm +// VPADDW m512 zmm zmm +// VPADDW zmm zmm k zmm +// VPADDW zmm zmm zmm +// Construct and append a VPADDW instruction to the active function. +// Operates on the global context. +func VPADDW(ops ...operand.Op) { ctx.VPADDW(ops...) } + +// VPADDW_Z: Add Packed Word Integers (Zeroing Masking). +// +// Forms: +// +// VPADDW.Z m128 xmm k xmm +// VPADDW.Z m256 ymm k ymm +// VPADDW.Z xmm xmm k xmm +// VPADDW.Z ymm ymm k ymm +// VPADDW.Z m512 zmm k zmm +// VPADDW.Z zmm zmm k zmm +// Construct and append a VPADDW.Z instruction to the active function. +func (c *Context) VPADDW_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPADDW_Z(mxyz, xyz, k, xyz1)) +} + +// VPADDW_Z: Add Packed Word Integers (Zeroing Masking). +// +// Forms: +// +// VPADDW.Z m128 xmm k xmm +// VPADDW.Z m256 ymm k ymm +// VPADDW.Z xmm xmm k xmm +// VPADDW.Z ymm ymm k ymm +// VPADDW.Z m512 zmm k zmm +// VPADDW.Z zmm zmm k zmm +// Construct and append a VPADDW.Z instruction to the active function. +// Operates on the global context. +func VPADDW_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPADDW_Z(mxyz, xyz, k, xyz1) } + +// VPALIGNR: Packed Align Right. +// +// Forms: +// +// VPALIGNR imm8 m256 ymm ymm +// VPALIGNR imm8 ymm ymm ymm +// VPALIGNR imm8 m128 xmm xmm +// VPALIGNR imm8 xmm xmm xmm +// VPALIGNR imm8 m128 xmm k xmm +// VPALIGNR imm8 m256 ymm k ymm +// VPALIGNR imm8 xmm xmm k xmm +// VPALIGNR imm8 ymm ymm k ymm +// VPALIGNR imm8 m512 zmm k zmm +// VPALIGNR imm8 m512 zmm zmm +// VPALIGNR imm8 zmm zmm k zmm +// VPALIGNR imm8 zmm zmm zmm +// Construct and append a VPALIGNR instruction to the active function. +func (c *Context) VPALIGNR(ops ...operand.Op) { + c.addinstruction(x86.VPALIGNR(ops...)) +} + +// VPALIGNR: Packed Align Right. +// +// Forms: +// +// VPALIGNR imm8 m256 ymm ymm +// VPALIGNR imm8 ymm ymm ymm +// VPALIGNR imm8 m128 xmm xmm +// VPALIGNR imm8 xmm xmm xmm +// VPALIGNR imm8 m128 xmm k xmm +// VPALIGNR imm8 m256 ymm k ymm +// VPALIGNR imm8 xmm xmm k xmm +// VPALIGNR imm8 ymm ymm k ymm +// VPALIGNR imm8 m512 zmm k zmm +// VPALIGNR imm8 m512 zmm zmm +// VPALIGNR imm8 zmm zmm k zmm +// VPALIGNR imm8 zmm zmm zmm +// Construct and append a VPALIGNR instruction to the active function. +// Operates on the global context. +func VPALIGNR(ops ...operand.Op) { ctx.VPALIGNR(ops...) } + +// VPALIGNR_Z: Packed Align Right (Zeroing Masking). +// +// Forms: +// +// VPALIGNR.Z imm8 m128 xmm k xmm +// VPALIGNR.Z imm8 m256 ymm k ymm +// VPALIGNR.Z imm8 xmm xmm k xmm +// VPALIGNR.Z imm8 ymm ymm k ymm +// VPALIGNR.Z imm8 m512 zmm k zmm +// VPALIGNR.Z imm8 zmm zmm k zmm +// Construct and append a VPALIGNR.Z instruction to the active function. +func (c *Context) VPALIGNR_Z(i, mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPALIGNR_Z(i, mxyz, xyz, k, xyz1)) +} + +// VPALIGNR_Z: Packed Align Right (Zeroing Masking). +// +// Forms: +// +// VPALIGNR.Z imm8 m128 xmm k xmm +// VPALIGNR.Z imm8 m256 ymm k ymm +// VPALIGNR.Z imm8 xmm xmm k xmm +// VPALIGNR.Z imm8 ymm ymm k ymm +// VPALIGNR.Z imm8 m512 zmm k zmm +// VPALIGNR.Z imm8 zmm zmm k zmm +// Construct and append a VPALIGNR.Z instruction to the active function. +// Operates on the global context. +func VPALIGNR_Z(i, mxyz, xyz, k, xyz1 operand.Op) { ctx.VPALIGNR_Z(i, mxyz, xyz, k, xyz1) } + +// VPAND: Packed Bitwise Logical AND. +// +// Forms: +// +// VPAND m256 ymm ymm +// VPAND ymm ymm ymm +// VPAND m128 xmm xmm +// VPAND xmm xmm xmm +// Construct and append a VPAND instruction to the active function. +func (c *Context) VPAND(mxy, xy, xy1 operand.Op) { + c.addinstruction(x86.VPAND(mxy, xy, xy1)) +} + +// VPAND: Packed Bitwise Logical AND. +// +// Forms: +// +// VPAND m256 ymm ymm +// VPAND ymm ymm ymm +// VPAND m128 xmm xmm +// VPAND xmm xmm xmm +// Construct and append a VPAND instruction to the active function. +// Operates on the global context. +func VPAND(mxy, xy, xy1 operand.Op) { ctx.VPAND(mxy, xy, xy1) } + +// VPANDD: Bitwise Logical AND of Packed Doubleword Integers. +// +// Forms: +// +// VPANDD m128 xmm k xmm +// VPANDD m128 xmm xmm +// VPANDD m256 ymm k ymm +// VPANDD m256 ymm ymm +// VPANDD xmm xmm k xmm +// VPANDD xmm xmm xmm +// VPANDD ymm ymm k ymm +// VPANDD ymm ymm ymm +// VPANDD m512 zmm k zmm +// VPANDD m512 zmm zmm +// VPANDD zmm zmm k zmm +// VPANDD zmm zmm zmm +// Construct and append a VPANDD instruction to the active function. +func (c *Context) VPANDD(ops ...operand.Op) { + c.addinstruction(x86.VPANDD(ops...)) +} + +// VPANDD: Bitwise Logical AND of Packed Doubleword Integers. +// +// Forms: +// +// VPANDD m128 xmm k xmm +// VPANDD m128 xmm xmm +// VPANDD m256 ymm k ymm +// VPANDD m256 ymm ymm +// VPANDD xmm xmm k xmm +// VPANDD xmm xmm xmm +// VPANDD ymm ymm k ymm +// VPANDD ymm ymm ymm +// VPANDD m512 zmm k zmm +// VPANDD m512 zmm zmm +// VPANDD zmm zmm k zmm +// VPANDD zmm zmm zmm +// Construct and append a VPANDD instruction to the active function. +// Operates on the global context. +func VPANDD(ops ...operand.Op) { ctx.VPANDD(ops...) } + +// VPANDD_BCST: Bitwise Logical AND of Packed Doubleword Integers (Broadcast). +// +// Forms: +// +// VPANDD.BCST m32 xmm k xmm +// VPANDD.BCST m32 xmm xmm +// VPANDD.BCST m32 ymm k ymm +// VPANDD.BCST m32 ymm ymm +// VPANDD.BCST m32 zmm k zmm +// VPANDD.BCST m32 zmm zmm +// Construct and append a VPANDD.BCST instruction to the active function. +func (c *Context) VPANDD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPANDD_BCST(ops...)) +} + +// VPANDD_BCST: Bitwise Logical AND of Packed Doubleword Integers (Broadcast). +// +// Forms: +// +// VPANDD.BCST m32 xmm k xmm +// VPANDD.BCST m32 xmm xmm +// VPANDD.BCST m32 ymm k ymm +// VPANDD.BCST m32 ymm ymm +// VPANDD.BCST m32 zmm k zmm +// VPANDD.BCST m32 zmm zmm +// Construct and append a VPANDD.BCST instruction to the active function. +// Operates on the global context. +func VPANDD_BCST(ops ...operand.Op) { ctx.VPANDD_BCST(ops...) } + +// VPANDD_BCST_Z: Bitwise Logical AND of Packed Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPANDD.BCST.Z m32 xmm k xmm +// VPANDD.BCST.Z m32 ymm k ymm +// VPANDD.BCST.Z m32 zmm k zmm +// Construct and append a VPANDD.BCST.Z instruction to the active function. +func (c *Context) VPANDD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPANDD_BCST_Z(m, xyz, k, xyz1)) +} + +// VPANDD_BCST_Z: Bitwise Logical AND of Packed Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPANDD.BCST.Z m32 xmm k xmm +// VPANDD.BCST.Z m32 ymm k ymm +// VPANDD.BCST.Z m32 zmm k zmm +// Construct and append a VPANDD.BCST.Z instruction to the active function. +// Operates on the global context. +func VPANDD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPANDD_BCST_Z(m, xyz, k, xyz1) } + +// VPANDD_Z: Bitwise Logical AND of Packed Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VPANDD.Z m128 xmm k xmm +// VPANDD.Z m256 ymm k ymm +// VPANDD.Z xmm xmm k xmm +// VPANDD.Z ymm ymm k ymm +// VPANDD.Z m512 zmm k zmm +// VPANDD.Z zmm zmm k zmm +// Construct and append a VPANDD.Z instruction to the active function. +func (c *Context) VPANDD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPANDD_Z(mxyz, xyz, k, xyz1)) +} + +// VPANDD_Z: Bitwise Logical AND of Packed Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VPANDD.Z m128 xmm k xmm +// VPANDD.Z m256 ymm k ymm +// VPANDD.Z xmm xmm k xmm +// VPANDD.Z ymm ymm k ymm +// VPANDD.Z m512 zmm k zmm +// VPANDD.Z zmm zmm k zmm +// Construct and append a VPANDD.Z instruction to the active function. +// Operates on the global context. +func VPANDD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPANDD_Z(mxyz, xyz, k, xyz1) } + +// VPANDN: Packed Bitwise Logical AND NOT. +// +// Forms: +// +// VPANDN m256 ymm ymm +// VPANDN ymm ymm ymm +// VPANDN m128 xmm xmm +// VPANDN xmm xmm xmm +// Construct and append a VPANDN instruction to the active function. +func (c *Context) VPANDN(mxy, xy, xy1 operand.Op) { + c.addinstruction(x86.VPANDN(mxy, xy, xy1)) +} + +// VPANDN: Packed Bitwise Logical AND NOT. +// +// Forms: +// +// VPANDN m256 ymm ymm +// VPANDN ymm ymm ymm +// VPANDN m128 xmm xmm +// VPANDN xmm xmm xmm +// Construct and append a VPANDN instruction to the active function. +// Operates on the global context. +func VPANDN(mxy, xy, xy1 operand.Op) { ctx.VPANDN(mxy, xy, xy1) } + +// VPANDND: Bitwise Logical AND NOT of Packed Doubleword Integers. +// +// Forms: +// +// VPANDND m128 xmm k xmm +// VPANDND m128 xmm xmm +// VPANDND m256 ymm k ymm +// VPANDND m256 ymm ymm +// VPANDND xmm xmm k xmm +// VPANDND xmm xmm xmm +// VPANDND ymm ymm k ymm +// VPANDND ymm ymm ymm +// VPANDND m512 zmm k zmm +// VPANDND m512 zmm zmm +// VPANDND zmm zmm k zmm +// VPANDND zmm zmm zmm +// Construct and append a VPANDND instruction to the active function. +func (c *Context) VPANDND(ops ...operand.Op) { + c.addinstruction(x86.VPANDND(ops...)) +} + +// VPANDND: Bitwise Logical AND NOT of Packed Doubleword Integers. +// +// Forms: +// +// VPANDND m128 xmm k xmm +// VPANDND m128 xmm xmm +// VPANDND m256 ymm k ymm +// VPANDND m256 ymm ymm +// VPANDND xmm xmm k xmm +// VPANDND xmm xmm xmm +// VPANDND ymm ymm k ymm +// VPANDND ymm ymm ymm +// VPANDND m512 zmm k zmm +// VPANDND m512 zmm zmm +// VPANDND zmm zmm k zmm +// VPANDND zmm zmm zmm +// Construct and append a VPANDND instruction to the active function. +// Operates on the global context. +func VPANDND(ops ...operand.Op) { ctx.VPANDND(ops...) } + +// VPANDND_BCST: Bitwise Logical AND NOT of Packed Doubleword Integers (Broadcast). +// +// Forms: +// +// VPANDND.BCST m32 xmm k xmm +// VPANDND.BCST m32 xmm xmm +// VPANDND.BCST m32 ymm k ymm +// VPANDND.BCST m32 ymm ymm +// VPANDND.BCST m32 zmm k zmm +// VPANDND.BCST m32 zmm zmm +// Construct and append a VPANDND.BCST instruction to the active function. +func (c *Context) VPANDND_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPANDND_BCST(ops...)) +} + +// VPANDND_BCST: Bitwise Logical AND NOT of Packed Doubleword Integers (Broadcast). +// +// Forms: +// +// VPANDND.BCST m32 xmm k xmm +// VPANDND.BCST m32 xmm xmm +// VPANDND.BCST m32 ymm k ymm +// VPANDND.BCST m32 ymm ymm +// VPANDND.BCST m32 zmm k zmm +// VPANDND.BCST m32 zmm zmm +// Construct and append a VPANDND.BCST instruction to the active function. +// Operates on the global context. +func VPANDND_BCST(ops ...operand.Op) { ctx.VPANDND_BCST(ops...) } + +// VPANDND_BCST_Z: Bitwise Logical AND NOT of Packed Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPANDND.BCST.Z m32 xmm k xmm +// VPANDND.BCST.Z m32 ymm k ymm +// VPANDND.BCST.Z m32 zmm k zmm +// Construct and append a VPANDND.BCST.Z instruction to the active function. +func (c *Context) VPANDND_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPANDND_BCST_Z(m, xyz, k, xyz1)) +} + +// VPANDND_BCST_Z: Bitwise Logical AND NOT of Packed Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPANDND.BCST.Z m32 xmm k xmm +// VPANDND.BCST.Z m32 ymm k ymm +// VPANDND.BCST.Z m32 zmm k zmm +// Construct and append a VPANDND.BCST.Z instruction to the active function. +// Operates on the global context. +func VPANDND_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPANDND_BCST_Z(m, xyz, k, xyz1) } + +// VPANDND_Z: Bitwise Logical AND NOT of Packed Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VPANDND.Z m128 xmm k xmm +// VPANDND.Z m256 ymm k ymm +// VPANDND.Z xmm xmm k xmm +// VPANDND.Z ymm ymm k ymm +// VPANDND.Z m512 zmm k zmm +// VPANDND.Z zmm zmm k zmm +// Construct and append a VPANDND.Z instruction to the active function. +func (c *Context) VPANDND_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPANDND_Z(mxyz, xyz, k, xyz1)) +} + +// VPANDND_Z: Bitwise Logical AND NOT of Packed Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VPANDND.Z m128 xmm k xmm +// VPANDND.Z m256 ymm k ymm +// VPANDND.Z xmm xmm k xmm +// VPANDND.Z ymm ymm k ymm +// VPANDND.Z m512 zmm k zmm +// VPANDND.Z zmm zmm k zmm +// Construct and append a VPANDND.Z instruction to the active function. +// Operates on the global context. +func VPANDND_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPANDND_Z(mxyz, xyz, k, xyz1) } + +// VPANDNQ: Bitwise Logical AND NOT of Packed Quadword Integers. +// +// Forms: +// +// VPANDNQ m128 xmm k xmm +// VPANDNQ m128 xmm xmm +// VPANDNQ m256 ymm k ymm +// VPANDNQ m256 ymm ymm +// VPANDNQ xmm xmm k xmm +// VPANDNQ xmm xmm xmm +// VPANDNQ ymm ymm k ymm +// VPANDNQ ymm ymm ymm +// VPANDNQ m512 zmm k zmm +// VPANDNQ m512 zmm zmm +// VPANDNQ zmm zmm k zmm +// VPANDNQ zmm zmm zmm +// Construct and append a VPANDNQ instruction to the active function. +func (c *Context) VPANDNQ(ops ...operand.Op) { + c.addinstruction(x86.VPANDNQ(ops...)) +} + +// VPANDNQ: Bitwise Logical AND NOT of Packed Quadword Integers. +// +// Forms: +// +// VPANDNQ m128 xmm k xmm +// VPANDNQ m128 xmm xmm +// VPANDNQ m256 ymm k ymm +// VPANDNQ m256 ymm ymm +// VPANDNQ xmm xmm k xmm +// VPANDNQ xmm xmm xmm +// VPANDNQ ymm ymm k ymm +// VPANDNQ ymm ymm ymm +// VPANDNQ m512 zmm k zmm +// VPANDNQ m512 zmm zmm +// VPANDNQ zmm zmm k zmm +// VPANDNQ zmm zmm zmm +// Construct and append a VPANDNQ instruction to the active function. +// Operates on the global context. +func VPANDNQ(ops ...operand.Op) { ctx.VPANDNQ(ops...) } + +// VPANDNQ_BCST: Bitwise Logical AND NOT of Packed Quadword Integers (Broadcast). +// +// Forms: +// +// VPANDNQ.BCST m64 xmm k xmm +// VPANDNQ.BCST m64 xmm xmm +// VPANDNQ.BCST m64 ymm k ymm +// VPANDNQ.BCST m64 ymm ymm +// VPANDNQ.BCST m64 zmm k zmm +// VPANDNQ.BCST m64 zmm zmm +// Construct and append a VPANDNQ.BCST instruction to the active function. +func (c *Context) VPANDNQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPANDNQ_BCST(ops...)) +} + +// VPANDNQ_BCST: Bitwise Logical AND NOT of Packed Quadword Integers (Broadcast). +// +// Forms: +// +// VPANDNQ.BCST m64 xmm k xmm +// VPANDNQ.BCST m64 xmm xmm +// VPANDNQ.BCST m64 ymm k ymm +// VPANDNQ.BCST m64 ymm ymm +// VPANDNQ.BCST m64 zmm k zmm +// VPANDNQ.BCST m64 zmm zmm +// Construct and append a VPANDNQ.BCST instruction to the active function. +// Operates on the global context. +func VPANDNQ_BCST(ops ...operand.Op) { ctx.VPANDNQ_BCST(ops...) } + +// VPANDNQ_BCST_Z: Bitwise Logical AND NOT of Packed Quadword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPANDNQ.BCST.Z m64 xmm k xmm +// VPANDNQ.BCST.Z m64 ymm k ymm +// VPANDNQ.BCST.Z m64 zmm k zmm +// Construct and append a VPANDNQ.BCST.Z instruction to the active function. +func (c *Context) VPANDNQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPANDNQ_BCST_Z(m, xyz, k, xyz1)) +} + +// VPANDNQ_BCST_Z: Bitwise Logical AND NOT of Packed Quadword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPANDNQ.BCST.Z m64 xmm k xmm +// VPANDNQ.BCST.Z m64 ymm k ymm +// VPANDNQ.BCST.Z m64 zmm k zmm +// Construct and append a VPANDNQ.BCST.Z instruction to the active function. +// Operates on the global context. +func VPANDNQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPANDNQ_BCST_Z(m, xyz, k, xyz1) } + +// VPANDNQ_Z: Bitwise Logical AND NOT of Packed Quadword Integers (Zeroing Masking). +// +// Forms: +// +// VPANDNQ.Z m128 xmm k xmm +// VPANDNQ.Z m256 ymm k ymm +// VPANDNQ.Z xmm xmm k xmm +// VPANDNQ.Z ymm ymm k ymm +// VPANDNQ.Z m512 zmm k zmm +// VPANDNQ.Z zmm zmm k zmm +// Construct and append a VPANDNQ.Z instruction to the active function. +func (c *Context) VPANDNQ_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPANDNQ_Z(mxyz, xyz, k, xyz1)) +} + +// VPANDNQ_Z: Bitwise Logical AND NOT of Packed Quadword Integers (Zeroing Masking). +// +// Forms: +// +// VPANDNQ.Z m128 xmm k xmm +// VPANDNQ.Z m256 ymm k ymm +// VPANDNQ.Z xmm xmm k xmm +// VPANDNQ.Z ymm ymm k ymm +// VPANDNQ.Z m512 zmm k zmm +// VPANDNQ.Z zmm zmm k zmm +// Construct and append a VPANDNQ.Z instruction to the active function. +// Operates on the global context. +func VPANDNQ_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPANDNQ_Z(mxyz, xyz, k, xyz1) } + +// VPANDQ: Bitwise Logical AND of Packed Quadword Integers. +// +// Forms: +// +// VPANDQ m128 xmm k xmm +// VPANDQ m128 xmm xmm +// VPANDQ m256 ymm k ymm +// VPANDQ m256 ymm ymm +// VPANDQ xmm xmm k xmm +// VPANDQ xmm xmm xmm +// VPANDQ ymm ymm k ymm +// VPANDQ ymm ymm ymm +// VPANDQ m512 zmm k zmm +// VPANDQ m512 zmm zmm +// VPANDQ zmm zmm k zmm +// VPANDQ zmm zmm zmm +// Construct and append a VPANDQ instruction to the active function. +func (c *Context) VPANDQ(ops ...operand.Op) { + c.addinstruction(x86.VPANDQ(ops...)) +} + +// VPANDQ: Bitwise Logical AND of Packed Quadword Integers. +// +// Forms: +// +// VPANDQ m128 xmm k xmm +// VPANDQ m128 xmm xmm +// VPANDQ m256 ymm k ymm +// VPANDQ m256 ymm ymm +// VPANDQ xmm xmm k xmm +// VPANDQ xmm xmm xmm +// VPANDQ ymm ymm k ymm +// VPANDQ ymm ymm ymm +// VPANDQ m512 zmm k zmm +// VPANDQ m512 zmm zmm +// VPANDQ zmm zmm k zmm +// VPANDQ zmm zmm zmm +// Construct and append a VPANDQ instruction to the active function. +// Operates on the global context. +func VPANDQ(ops ...operand.Op) { ctx.VPANDQ(ops...) } + +// VPANDQ_BCST: Bitwise Logical AND of Packed Quadword Integers (Broadcast). +// +// Forms: +// +// VPANDQ.BCST m64 xmm k xmm +// VPANDQ.BCST m64 xmm xmm +// VPANDQ.BCST m64 ymm k ymm +// VPANDQ.BCST m64 ymm ymm +// VPANDQ.BCST m64 zmm k zmm +// VPANDQ.BCST m64 zmm zmm +// Construct and append a VPANDQ.BCST instruction to the active function. +func (c *Context) VPANDQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPANDQ_BCST(ops...)) +} + +// VPANDQ_BCST: Bitwise Logical AND of Packed Quadword Integers (Broadcast). +// +// Forms: +// +// VPANDQ.BCST m64 xmm k xmm +// VPANDQ.BCST m64 xmm xmm +// VPANDQ.BCST m64 ymm k ymm +// VPANDQ.BCST m64 ymm ymm +// VPANDQ.BCST m64 zmm k zmm +// VPANDQ.BCST m64 zmm zmm +// Construct and append a VPANDQ.BCST instruction to the active function. +// Operates on the global context. +func VPANDQ_BCST(ops ...operand.Op) { ctx.VPANDQ_BCST(ops...) } + +// VPANDQ_BCST_Z: Bitwise Logical AND of Packed Quadword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPANDQ.BCST.Z m64 xmm k xmm +// VPANDQ.BCST.Z m64 ymm k ymm +// VPANDQ.BCST.Z m64 zmm k zmm +// Construct and append a VPANDQ.BCST.Z instruction to the active function. +func (c *Context) VPANDQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPANDQ_BCST_Z(m, xyz, k, xyz1)) +} + +// VPANDQ_BCST_Z: Bitwise Logical AND of Packed Quadword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPANDQ.BCST.Z m64 xmm k xmm +// VPANDQ.BCST.Z m64 ymm k ymm +// VPANDQ.BCST.Z m64 zmm k zmm +// Construct and append a VPANDQ.BCST.Z instruction to the active function. +// Operates on the global context. +func VPANDQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPANDQ_BCST_Z(m, xyz, k, xyz1) } + +// VPANDQ_Z: Bitwise Logical AND of Packed Quadword Integers (Zeroing Masking). +// +// Forms: +// +// VPANDQ.Z m128 xmm k xmm +// VPANDQ.Z m256 ymm k ymm +// VPANDQ.Z xmm xmm k xmm +// VPANDQ.Z ymm ymm k ymm +// VPANDQ.Z m512 zmm k zmm +// VPANDQ.Z zmm zmm k zmm +// Construct and append a VPANDQ.Z instruction to the active function. +func (c *Context) VPANDQ_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPANDQ_Z(mxyz, xyz, k, xyz1)) +} + +// VPANDQ_Z: Bitwise Logical AND of Packed Quadword Integers (Zeroing Masking). +// +// Forms: +// +// VPANDQ.Z m128 xmm k xmm +// VPANDQ.Z m256 ymm k ymm +// VPANDQ.Z xmm xmm k xmm +// VPANDQ.Z ymm ymm k ymm +// VPANDQ.Z m512 zmm k zmm +// VPANDQ.Z zmm zmm k zmm +// Construct and append a VPANDQ.Z instruction to the active function. +// Operates on the global context. +func VPANDQ_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPANDQ_Z(mxyz, xyz, k, xyz1) } + +// VPAVGB: Average Packed Byte Integers. +// +// Forms: +// +// VPAVGB m256 ymm ymm +// VPAVGB ymm ymm ymm +// VPAVGB m128 xmm xmm +// VPAVGB xmm xmm xmm +// VPAVGB m128 xmm k xmm +// VPAVGB m256 ymm k ymm +// VPAVGB xmm xmm k xmm +// VPAVGB ymm ymm k ymm +// VPAVGB m512 zmm k zmm +// VPAVGB m512 zmm zmm +// VPAVGB zmm zmm k zmm +// VPAVGB zmm zmm zmm +// Construct and append a VPAVGB instruction to the active function. +func (c *Context) VPAVGB(ops ...operand.Op) { + c.addinstruction(x86.VPAVGB(ops...)) +} + +// VPAVGB: Average Packed Byte Integers. +// +// Forms: +// +// VPAVGB m256 ymm ymm +// VPAVGB ymm ymm ymm +// VPAVGB m128 xmm xmm +// VPAVGB xmm xmm xmm +// VPAVGB m128 xmm k xmm +// VPAVGB m256 ymm k ymm +// VPAVGB xmm xmm k xmm +// VPAVGB ymm ymm k ymm +// VPAVGB m512 zmm k zmm +// VPAVGB m512 zmm zmm +// VPAVGB zmm zmm k zmm +// VPAVGB zmm zmm zmm +// Construct and append a VPAVGB instruction to the active function. +// Operates on the global context. +func VPAVGB(ops ...operand.Op) { ctx.VPAVGB(ops...) } + +// VPAVGB_Z: Average Packed Byte Integers (Zeroing Masking). +// +// Forms: +// +// VPAVGB.Z m128 xmm k xmm +// VPAVGB.Z m256 ymm k ymm +// VPAVGB.Z xmm xmm k xmm +// VPAVGB.Z ymm ymm k ymm +// VPAVGB.Z m512 zmm k zmm +// VPAVGB.Z zmm zmm k zmm +// Construct and append a VPAVGB.Z instruction to the active function. +func (c *Context) VPAVGB_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPAVGB_Z(mxyz, xyz, k, xyz1)) +} + +// VPAVGB_Z: Average Packed Byte Integers (Zeroing Masking). +// +// Forms: +// +// VPAVGB.Z m128 xmm k xmm +// VPAVGB.Z m256 ymm k ymm +// VPAVGB.Z xmm xmm k xmm +// VPAVGB.Z ymm ymm k ymm +// VPAVGB.Z m512 zmm k zmm +// VPAVGB.Z zmm zmm k zmm +// Construct and append a VPAVGB.Z instruction to the active function. +// Operates on the global context. +func VPAVGB_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPAVGB_Z(mxyz, xyz, k, xyz1) } + +// VPAVGW: Average Packed Word Integers. +// +// Forms: +// +// VPAVGW m256 ymm ymm +// VPAVGW ymm ymm ymm +// VPAVGW m128 xmm xmm +// VPAVGW xmm xmm xmm +// VPAVGW m128 xmm k xmm +// VPAVGW m256 ymm k ymm +// VPAVGW xmm xmm k xmm +// VPAVGW ymm ymm k ymm +// VPAVGW m512 zmm k zmm +// VPAVGW m512 zmm zmm +// VPAVGW zmm zmm k zmm +// VPAVGW zmm zmm zmm +// Construct and append a VPAVGW instruction to the active function. +func (c *Context) VPAVGW(ops ...operand.Op) { + c.addinstruction(x86.VPAVGW(ops...)) +} + +// VPAVGW: Average Packed Word Integers. +// +// Forms: +// +// VPAVGW m256 ymm ymm +// VPAVGW ymm ymm ymm +// VPAVGW m128 xmm xmm +// VPAVGW xmm xmm xmm +// VPAVGW m128 xmm k xmm +// VPAVGW m256 ymm k ymm +// VPAVGW xmm xmm k xmm +// VPAVGW ymm ymm k ymm +// VPAVGW m512 zmm k zmm +// VPAVGW m512 zmm zmm +// VPAVGW zmm zmm k zmm +// VPAVGW zmm zmm zmm +// Construct and append a VPAVGW instruction to the active function. +// Operates on the global context. +func VPAVGW(ops ...operand.Op) { ctx.VPAVGW(ops...) } + +// VPAVGW_Z: Average Packed Word Integers (Zeroing Masking). +// +// Forms: +// +// VPAVGW.Z m128 xmm k xmm +// VPAVGW.Z m256 ymm k ymm +// VPAVGW.Z xmm xmm k xmm +// VPAVGW.Z ymm ymm k ymm +// VPAVGW.Z m512 zmm k zmm +// VPAVGW.Z zmm zmm k zmm +// Construct and append a VPAVGW.Z instruction to the active function. +func (c *Context) VPAVGW_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPAVGW_Z(mxyz, xyz, k, xyz1)) +} + +// VPAVGW_Z: Average Packed Word Integers (Zeroing Masking). +// +// Forms: +// +// VPAVGW.Z m128 xmm k xmm +// VPAVGW.Z m256 ymm k ymm +// VPAVGW.Z xmm xmm k xmm +// VPAVGW.Z ymm ymm k ymm +// VPAVGW.Z m512 zmm k zmm +// VPAVGW.Z zmm zmm k zmm +// Construct and append a VPAVGW.Z instruction to the active function. +// Operates on the global context. +func VPAVGW_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPAVGW_Z(mxyz, xyz, k, xyz1) } + +// VPBLENDD: Blend Packed Doublewords. +// +// Forms: +// +// VPBLENDD imm8 m128 xmm xmm +// VPBLENDD imm8 m256 ymm ymm +// VPBLENDD imm8 xmm xmm xmm +// VPBLENDD imm8 ymm ymm ymm +// Construct and append a VPBLENDD instruction to the active function. +func (c *Context) VPBLENDD(i, mxy, xy, xy1 operand.Op) { + c.addinstruction(x86.VPBLENDD(i, mxy, xy, xy1)) +} + +// VPBLENDD: Blend Packed Doublewords. +// +// Forms: +// +// VPBLENDD imm8 m128 xmm xmm +// VPBLENDD imm8 m256 ymm ymm +// VPBLENDD imm8 xmm xmm xmm +// VPBLENDD imm8 ymm ymm ymm +// Construct and append a VPBLENDD instruction to the active function. +// Operates on the global context. +func VPBLENDD(i, mxy, xy, xy1 operand.Op) { ctx.VPBLENDD(i, mxy, xy, xy1) } + +// VPBLENDMB: Blend Byte Vectors Using an OpMask Control. +// +// Forms: +// +// VPBLENDMB m128 xmm k xmm +// VPBLENDMB m128 xmm xmm +// VPBLENDMB m256 ymm k ymm +// VPBLENDMB m256 ymm ymm +// VPBLENDMB xmm xmm k xmm +// VPBLENDMB xmm xmm xmm +// VPBLENDMB ymm ymm k ymm +// VPBLENDMB ymm ymm ymm +// VPBLENDMB m512 zmm k zmm +// VPBLENDMB m512 zmm zmm +// VPBLENDMB zmm zmm k zmm +// VPBLENDMB zmm zmm zmm +// Construct and append a VPBLENDMB instruction to the active function. +func (c *Context) VPBLENDMB(ops ...operand.Op) { + c.addinstruction(x86.VPBLENDMB(ops...)) +} + +// VPBLENDMB: Blend Byte Vectors Using an OpMask Control. +// +// Forms: +// +// VPBLENDMB m128 xmm k xmm +// VPBLENDMB m128 xmm xmm +// VPBLENDMB m256 ymm k ymm +// VPBLENDMB m256 ymm ymm +// VPBLENDMB xmm xmm k xmm +// VPBLENDMB xmm xmm xmm +// VPBLENDMB ymm ymm k ymm +// VPBLENDMB ymm ymm ymm +// VPBLENDMB m512 zmm k zmm +// VPBLENDMB m512 zmm zmm +// VPBLENDMB zmm zmm k zmm +// VPBLENDMB zmm zmm zmm +// Construct and append a VPBLENDMB instruction to the active function. +// Operates on the global context. +func VPBLENDMB(ops ...operand.Op) { ctx.VPBLENDMB(ops...) } + +// VPBLENDMB_Z: Blend Byte Vectors Using an OpMask Control (Zeroing Masking). +// +// Forms: +// +// VPBLENDMB.Z m128 xmm k xmm +// VPBLENDMB.Z m256 ymm k ymm +// VPBLENDMB.Z xmm xmm k xmm +// VPBLENDMB.Z ymm ymm k ymm +// VPBLENDMB.Z m512 zmm k zmm +// VPBLENDMB.Z zmm zmm k zmm +// Construct and append a VPBLENDMB.Z instruction to the active function. +func (c *Context) VPBLENDMB_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPBLENDMB_Z(mxyz, xyz, k, xyz1)) +} + +// VPBLENDMB_Z: Blend Byte Vectors Using an OpMask Control (Zeroing Masking). +// +// Forms: +// +// VPBLENDMB.Z m128 xmm k xmm +// VPBLENDMB.Z m256 ymm k ymm +// VPBLENDMB.Z xmm xmm k xmm +// VPBLENDMB.Z ymm ymm k ymm +// VPBLENDMB.Z m512 zmm k zmm +// VPBLENDMB.Z zmm zmm k zmm +// Construct and append a VPBLENDMB.Z instruction to the active function. +// Operates on the global context. +func VPBLENDMB_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPBLENDMB_Z(mxyz, xyz, k, xyz1) } + +// VPBLENDMD: Blend Doubleword Vectors Using an OpMask Control. +// +// Forms: +// +// VPBLENDMD m128 xmm k xmm +// VPBLENDMD m128 xmm xmm +// VPBLENDMD m256 ymm k ymm +// VPBLENDMD m256 ymm ymm +// VPBLENDMD xmm xmm k xmm +// VPBLENDMD xmm xmm xmm +// VPBLENDMD ymm ymm k ymm +// VPBLENDMD ymm ymm ymm +// VPBLENDMD m512 zmm k zmm +// VPBLENDMD m512 zmm zmm +// VPBLENDMD zmm zmm k zmm +// VPBLENDMD zmm zmm zmm +// Construct and append a VPBLENDMD instruction to the active function. +func (c *Context) VPBLENDMD(ops ...operand.Op) { + c.addinstruction(x86.VPBLENDMD(ops...)) +} + +// VPBLENDMD: Blend Doubleword Vectors Using an OpMask Control. +// +// Forms: +// +// VPBLENDMD m128 xmm k xmm +// VPBLENDMD m128 xmm xmm +// VPBLENDMD m256 ymm k ymm +// VPBLENDMD m256 ymm ymm +// VPBLENDMD xmm xmm k xmm +// VPBLENDMD xmm xmm xmm +// VPBLENDMD ymm ymm k ymm +// VPBLENDMD ymm ymm ymm +// VPBLENDMD m512 zmm k zmm +// VPBLENDMD m512 zmm zmm +// VPBLENDMD zmm zmm k zmm +// VPBLENDMD zmm zmm zmm +// Construct and append a VPBLENDMD instruction to the active function. +// Operates on the global context. +func VPBLENDMD(ops ...operand.Op) { ctx.VPBLENDMD(ops...) } + +// VPBLENDMD_BCST: Blend Doubleword Vectors Using an OpMask Control (Broadcast). +// +// Forms: +// +// VPBLENDMD.BCST m32 xmm k xmm +// VPBLENDMD.BCST m32 xmm xmm +// VPBLENDMD.BCST m32 ymm k ymm +// VPBLENDMD.BCST m32 ymm ymm +// VPBLENDMD.BCST m32 zmm k zmm +// VPBLENDMD.BCST m32 zmm zmm +// Construct and append a VPBLENDMD.BCST instruction to the active function. +func (c *Context) VPBLENDMD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPBLENDMD_BCST(ops...)) +} + +// VPBLENDMD_BCST: Blend Doubleword Vectors Using an OpMask Control (Broadcast). +// +// Forms: +// +// VPBLENDMD.BCST m32 xmm k xmm +// VPBLENDMD.BCST m32 xmm xmm +// VPBLENDMD.BCST m32 ymm k ymm +// VPBLENDMD.BCST m32 ymm ymm +// VPBLENDMD.BCST m32 zmm k zmm +// VPBLENDMD.BCST m32 zmm zmm +// Construct and append a VPBLENDMD.BCST instruction to the active function. +// Operates on the global context. +func VPBLENDMD_BCST(ops ...operand.Op) { ctx.VPBLENDMD_BCST(ops...) } + +// VPBLENDMD_BCST_Z: Blend Doubleword Vectors Using an OpMask Control (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPBLENDMD.BCST.Z m32 xmm k xmm +// VPBLENDMD.BCST.Z m32 ymm k ymm +// VPBLENDMD.BCST.Z m32 zmm k zmm +// Construct and append a VPBLENDMD.BCST.Z instruction to the active function. +func (c *Context) VPBLENDMD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPBLENDMD_BCST_Z(m, xyz, k, xyz1)) +} + +// VPBLENDMD_BCST_Z: Blend Doubleword Vectors Using an OpMask Control (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPBLENDMD.BCST.Z m32 xmm k xmm +// VPBLENDMD.BCST.Z m32 ymm k ymm +// VPBLENDMD.BCST.Z m32 zmm k zmm +// Construct and append a VPBLENDMD.BCST.Z instruction to the active function. +// Operates on the global context. +func VPBLENDMD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPBLENDMD_BCST_Z(m, xyz, k, xyz1) } + +// VPBLENDMD_Z: Blend Doubleword Vectors Using an OpMask Control (Zeroing Masking). +// +// Forms: +// +// VPBLENDMD.Z m128 xmm k xmm +// VPBLENDMD.Z m256 ymm k ymm +// VPBLENDMD.Z xmm xmm k xmm +// VPBLENDMD.Z ymm ymm k ymm +// VPBLENDMD.Z m512 zmm k zmm +// VPBLENDMD.Z zmm zmm k zmm +// Construct and append a VPBLENDMD.Z instruction to the active function. +func (c *Context) VPBLENDMD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPBLENDMD_Z(mxyz, xyz, k, xyz1)) +} + +// VPBLENDMD_Z: Blend Doubleword Vectors Using an OpMask Control (Zeroing Masking). +// +// Forms: +// +// VPBLENDMD.Z m128 xmm k xmm +// VPBLENDMD.Z m256 ymm k ymm +// VPBLENDMD.Z xmm xmm k xmm +// VPBLENDMD.Z ymm ymm k ymm +// VPBLENDMD.Z m512 zmm k zmm +// VPBLENDMD.Z zmm zmm k zmm +// Construct and append a VPBLENDMD.Z instruction to the active function. +// Operates on the global context. +func VPBLENDMD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPBLENDMD_Z(mxyz, xyz, k, xyz1) } + +// VPBLENDMQ: Blend Quadword Vectors Using an OpMask Control. +// +// Forms: +// +// VPBLENDMQ m128 xmm k xmm +// VPBLENDMQ m128 xmm xmm +// VPBLENDMQ m256 ymm k ymm +// VPBLENDMQ m256 ymm ymm +// VPBLENDMQ xmm xmm k xmm +// VPBLENDMQ xmm xmm xmm +// VPBLENDMQ ymm ymm k ymm +// VPBLENDMQ ymm ymm ymm +// VPBLENDMQ m512 zmm k zmm +// VPBLENDMQ m512 zmm zmm +// VPBLENDMQ zmm zmm k zmm +// VPBLENDMQ zmm zmm zmm +// Construct and append a VPBLENDMQ instruction to the active function. +func (c *Context) VPBLENDMQ(ops ...operand.Op) { + c.addinstruction(x86.VPBLENDMQ(ops...)) +} + +// VPBLENDMQ: Blend Quadword Vectors Using an OpMask Control. +// +// Forms: +// +// VPBLENDMQ m128 xmm k xmm +// VPBLENDMQ m128 xmm xmm +// VPBLENDMQ m256 ymm k ymm +// VPBLENDMQ m256 ymm ymm +// VPBLENDMQ xmm xmm k xmm +// VPBLENDMQ xmm xmm xmm +// VPBLENDMQ ymm ymm k ymm +// VPBLENDMQ ymm ymm ymm +// VPBLENDMQ m512 zmm k zmm +// VPBLENDMQ m512 zmm zmm +// VPBLENDMQ zmm zmm k zmm +// VPBLENDMQ zmm zmm zmm +// Construct and append a VPBLENDMQ instruction to the active function. +// Operates on the global context. +func VPBLENDMQ(ops ...operand.Op) { ctx.VPBLENDMQ(ops...) } + +// VPBLENDMQ_BCST: Blend Quadword Vectors Using an OpMask Control (Broadcast). +// +// Forms: +// +// VPBLENDMQ.BCST m64 xmm k xmm +// VPBLENDMQ.BCST m64 xmm xmm +// VPBLENDMQ.BCST m64 ymm k ymm +// VPBLENDMQ.BCST m64 ymm ymm +// VPBLENDMQ.BCST m64 zmm k zmm +// VPBLENDMQ.BCST m64 zmm zmm +// Construct and append a VPBLENDMQ.BCST instruction to the active function. +func (c *Context) VPBLENDMQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPBLENDMQ_BCST(ops...)) +} + +// VPBLENDMQ_BCST: Blend Quadword Vectors Using an OpMask Control (Broadcast). +// +// Forms: +// +// VPBLENDMQ.BCST m64 xmm k xmm +// VPBLENDMQ.BCST m64 xmm xmm +// VPBLENDMQ.BCST m64 ymm k ymm +// VPBLENDMQ.BCST m64 ymm ymm +// VPBLENDMQ.BCST m64 zmm k zmm +// VPBLENDMQ.BCST m64 zmm zmm +// Construct and append a VPBLENDMQ.BCST instruction to the active function. +// Operates on the global context. +func VPBLENDMQ_BCST(ops ...operand.Op) { ctx.VPBLENDMQ_BCST(ops...) } + +// VPBLENDMQ_BCST_Z: Blend Quadword Vectors Using an OpMask Control (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPBLENDMQ.BCST.Z m64 xmm k xmm +// VPBLENDMQ.BCST.Z m64 ymm k ymm +// VPBLENDMQ.BCST.Z m64 zmm k zmm +// Construct and append a VPBLENDMQ.BCST.Z instruction to the active function. +func (c *Context) VPBLENDMQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPBLENDMQ_BCST_Z(m, xyz, k, xyz1)) +} + +// VPBLENDMQ_BCST_Z: Blend Quadword Vectors Using an OpMask Control (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPBLENDMQ.BCST.Z m64 xmm k xmm +// VPBLENDMQ.BCST.Z m64 ymm k ymm +// VPBLENDMQ.BCST.Z m64 zmm k zmm +// Construct and append a VPBLENDMQ.BCST.Z instruction to the active function. +// Operates on the global context. +func VPBLENDMQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPBLENDMQ_BCST_Z(m, xyz, k, xyz1) } + +// VPBLENDMQ_Z: Blend Quadword Vectors Using an OpMask Control (Zeroing Masking). +// +// Forms: +// +// VPBLENDMQ.Z m128 xmm k xmm +// VPBLENDMQ.Z m256 ymm k ymm +// VPBLENDMQ.Z xmm xmm k xmm +// VPBLENDMQ.Z ymm ymm k ymm +// VPBLENDMQ.Z m512 zmm k zmm +// VPBLENDMQ.Z zmm zmm k zmm +// Construct and append a VPBLENDMQ.Z instruction to the active function. +func (c *Context) VPBLENDMQ_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPBLENDMQ_Z(mxyz, xyz, k, xyz1)) +} + +// VPBLENDMQ_Z: Blend Quadword Vectors Using an OpMask Control (Zeroing Masking). +// +// Forms: +// +// VPBLENDMQ.Z m128 xmm k xmm +// VPBLENDMQ.Z m256 ymm k ymm +// VPBLENDMQ.Z xmm xmm k xmm +// VPBLENDMQ.Z ymm ymm k ymm +// VPBLENDMQ.Z m512 zmm k zmm +// VPBLENDMQ.Z zmm zmm k zmm +// Construct and append a VPBLENDMQ.Z instruction to the active function. +// Operates on the global context. +func VPBLENDMQ_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPBLENDMQ_Z(mxyz, xyz, k, xyz1) } + +// VPBLENDMW: Blend Word Vectors Using an OpMask Control. +// +// Forms: +// +// VPBLENDMW m128 xmm k xmm +// VPBLENDMW m128 xmm xmm +// VPBLENDMW m256 ymm k ymm +// VPBLENDMW m256 ymm ymm +// VPBLENDMW xmm xmm k xmm +// VPBLENDMW xmm xmm xmm +// VPBLENDMW ymm ymm k ymm +// VPBLENDMW ymm ymm ymm +// VPBLENDMW m512 zmm k zmm +// VPBLENDMW m512 zmm zmm +// VPBLENDMW zmm zmm k zmm +// VPBLENDMW zmm zmm zmm +// Construct and append a VPBLENDMW instruction to the active function. +func (c *Context) VPBLENDMW(ops ...operand.Op) { + c.addinstruction(x86.VPBLENDMW(ops...)) +} + +// VPBLENDMW: Blend Word Vectors Using an OpMask Control. +// +// Forms: +// +// VPBLENDMW m128 xmm k xmm +// VPBLENDMW m128 xmm xmm +// VPBLENDMW m256 ymm k ymm +// VPBLENDMW m256 ymm ymm +// VPBLENDMW xmm xmm k xmm +// VPBLENDMW xmm xmm xmm +// VPBLENDMW ymm ymm k ymm +// VPBLENDMW ymm ymm ymm +// VPBLENDMW m512 zmm k zmm +// VPBLENDMW m512 zmm zmm +// VPBLENDMW zmm zmm k zmm +// VPBLENDMW zmm zmm zmm +// Construct and append a VPBLENDMW instruction to the active function. +// Operates on the global context. +func VPBLENDMW(ops ...operand.Op) { ctx.VPBLENDMW(ops...) } + +// VPBLENDMW_Z: Blend Word Vectors Using an OpMask Control (Zeroing Masking). +// +// Forms: +// +// VPBLENDMW.Z m128 xmm k xmm +// VPBLENDMW.Z m256 ymm k ymm +// VPBLENDMW.Z xmm xmm k xmm +// VPBLENDMW.Z ymm ymm k ymm +// VPBLENDMW.Z m512 zmm k zmm +// VPBLENDMW.Z zmm zmm k zmm +// Construct and append a VPBLENDMW.Z instruction to the active function. +func (c *Context) VPBLENDMW_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPBLENDMW_Z(mxyz, xyz, k, xyz1)) +} + +// VPBLENDMW_Z: Blend Word Vectors Using an OpMask Control (Zeroing Masking). +// +// Forms: +// +// VPBLENDMW.Z m128 xmm k xmm +// VPBLENDMW.Z m256 ymm k ymm +// VPBLENDMW.Z xmm xmm k xmm +// VPBLENDMW.Z ymm ymm k ymm +// VPBLENDMW.Z m512 zmm k zmm +// VPBLENDMW.Z zmm zmm k zmm +// Construct and append a VPBLENDMW.Z instruction to the active function. +// Operates on the global context. +func VPBLENDMW_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPBLENDMW_Z(mxyz, xyz, k, xyz1) } + +// VPBLENDVB: Variable Blend Packed Bytes. +// +// Forms: +// +// VPBLENDVB ymm m256 ymm ymm +// VPBLENDVB ymm ymm ymm ymm +// VPBLENDVB xmm m128 xmm xmm +// VPBLENDVB xmm xmm xmm xmm +// Construct and append a VPBLENDVB instruction to the active function. +func (c *Context) VPBLENDVB(xy, mxy, xy1, xy2 operand.Op) { + c.addinstruction(x86.VPBLENDVB(xy, mxy, xy1, xy2)) +} + +// VPBLENDVB: Variable Blend Packed Bytes. +// +// Forms: +// +// VPBLENDVB ymm m256 ymm ymm +// VPBLENDVB ymm ymm ymm ymm +// VPBLENDVB xmm m128 xmm xmm +// VPBLENDVB xmm xmm xmm xmm +// Construct and append a VPBLENDVB instruction to the active function. +// Operates on the global context. +func VPBLENDVB(xy, mxy, xy1, xy2 operand.Op) { ctx.VPBLENDVB(xy, mxy, xy1, xy2) } + +// VPBLENDW: Blend Packed Words. +// +// Forms: +// +// VPBLENDW imm8 m256 ymm ymm +// VPBLENDW imm8 ymm ymm ymm +// VPBLENDW imm8 m128 xmm xmm +// VPBLENDW imm8 xmm xmm xmm +// Construct and append a VPBLENDW instruction to the active function. +func (c *Context) VPBLENDW(i, mxy, xy, xy1 operand.Op) { + c.addinstruction(x86.VPBLENDW(i, mxy, xy, xy1)) +} + +// VPBLENDW: Blend Packed Words. +// +// Forms: +// +// VPBLENDW imm8 m256 ymm ymm +// VPBLENDW imm8 ymm ymm ymm +// VPBLENDW imm8 m128 xmm xmm +// VPBLENDW imm8 xmm xmm xmm +// Construct and append a VPBLENDW instruction to the active function. +// Operates on the global context. +func VPBLENDW(i, mxy, xy, xy1 operand.Op) { ctx.VPBLENDW(i, mxy, xy, xy1) } + +// VPBROADCASTB: Broadcast Byte Integer. +// +// Forms: +// +// VPBROADCASTB m8 xmm +// VPBROADCASTB m8 ymm +// VPBROADCASTB xmm xmm +// VPBROADCASTB xmm ymm +// VPBROADCASTB m8 k xmm +// VPBROADCASTB m8 k ymm +// VPBROADCASTB r32 k xmm +// VPBROADCASTB r32 k ymm +// VPBROADCASTB r32 xmm +// VPBROADCASTB r32 ymm +// VPBROADCASTB xmm k xmm +// VPBROADCASTB xmm k ymm +// VPBROADCASTB m8 k zmm +// VPBROADCASTB m8 zmm +// VPBROADCASTB r32 k zmm +// VPBROADCASTB r32 zmm +// VPBROADCASTB xmm k zmm +// VPBROADCASTB xmm zmm +// Construct and append a VPBROADCASTB instruction to the active function. +func (c *Context) VPBROADCASTB(ops ...operand.Op) { + c.addinstruction(x86.VPBROADCASTB(ops...)) +} + +// VPBROADCASTB: Broadcast Byte Integer. +// +// Forms: +// +// VPBROADCASTB m8 xmm +// VPBROADCASTB m8 ymm +// VPBROADCASTB xmm xmm +// VPBROADCASTB xmm ymm +// VPBROADCASTB m8 k xmm +// VPBROADCASTB m8 k ymm +// VPBROADCASTB r32 k xmm +// VPBROADCASTB r32 k ymm +// VPBROADCASTB r32 xmm +// VPBROADCASTB r32 ymm +// VPBROADCASTB xmm k xmm +// VPBROADCASTB xmm k ymm +// VPBROADCASTB m8 k zmm +// VPBROADCASTB m8 zmm +// VPBROADCASTB r32 k zmm +// VPBROADCASTB r32 zmm +// VPBROADCASTB xmm k zmm +// VPBROADCASTB xmm zmm +// Construct and append a VPBROADCASTB instruction to the active function. +// Operates on the global context. +func VPBROADCASTB(ops ...operand.Op) { ctx.VPBROADCASTB(ops...) } + +// VPBROADCASTB_Z: Broadcast Byte Integer (Zeroing Masking). +// +// Forms: +// +// VPBROADCASTB.Z m8 k xmm +// VPBROADCASTB.Z m8 k ymm +// VPBROADCASTB.Z r32 k xmm +// VPBROADCASTB.Z r32 k ymm +// VPBROADCASTB.Z xmm k xmm +// VPBROADCASTB.Z xmm k ymm +// VPBROADCASTB.Z m8 k zmm +// VPBROADCASTB.Z r32 k zmm +// VPBROADCASTB.Z xmm k zmm +// Construct and append a VPBROADCASTB.Z instruction to the active function. +func (c *Context) VPBROADCASTB_Z(mrx, k, xyz operand.Op) { + c.addinstruction(x86.VPBROADCASTB_Z(mrx, k, xyz)) +} + +// VPBROADCASTB_Z: Broadcast Byte Integer (Zeroing Masking). +// +// Forms: +// +// VPBROADCASTB.Z m8 k xmm +// VPBROADCASTB.Z m8 k ymm +// VPBROADCASTB.Z r32 k xmm +// VPBROADCASTB.Z r32 k ymm +// VPBROADCASTB.Z xmm k xmm +// VPBROADCASTB.Z xmm k ymm +// VPBROADCASTB.Z m8 k zmm +// VPBROADCASTB.Z r32 k zmm +// VPBROADCASTB.Z xmm k zmm +// Construct and append a VPBROADCASTB.Z instruction to the active function. +// Operates on the global context. +func VPBROADCASTB_Z(mrx, k, xyz operand.Op) { ctx.VPBROADCASTB_Z(mrx, k, xyz) } + +// VPBROADCASTD: Broadcast Doubleword Integer. +// +// Forms: +// +// VPBROADCASTD m32 xmm +// VPBROADCASTD m32 ymm +// VPBROADCASTD xmm xmm +// VPBROADCASTD xmm ymm +// VPBROADCASTD m32 k xmm +// VPBROADCASTD m32 k ymm +// VPBROADCASTD r32 k xmm +// VPBROADCASTD r32 k ymm +// VPBROADCASTD r32 xmm +// VPBROADCASTD r32 ymm +// VPBROADCASTD xmm k xmm +// VPBROADCASTD xmm k ymm +// VPBROADCASTD m32 k zmm +// VPBROADCASTD m32 zmm +// VPBROADCASTD r32 k zmm +// VPBROADCASTD r32 zmm +// VPBROADCASTD xmm k zmm +// VPBROADCASTD xmm zmm +// Construct and append a VPBROADCASTD instruction to the active function. +func (c *Context) VPBROADCASTD(ops ...operand.Op) { + c.addinstruction(x86.VPBROADCASTD(ops...)) +} + +// VPBROADCASTD: Broadcast Doubleword Integer. +// +// Forms: +// +// VPBROADCASTD m32 xmm +// VPBROADCASTD m32 ymm +// VPBROADCASTD xmm xmm +// VPBROADCASTD xmm ymm +// VPBROADCASTD m32 k xmm +// VPBROADCASTD m32 k ymm +// VPBROADCASTD r32 k xmm +// VPBROADCASTD r32 k ymm +// VPBROADCASTD r32 xmm +// VPBROADCASTD r32 ymm +// VPBROADCASTD xmm k xmm +// VPBROADCASTD xmm k ymm +// VPBROADCASTD m32 k zmm +// VPBROADCASTD m32 zmm +// VPBROADCASTD r32 k zmm +// VPBROADCASTD r32 zmm +// VPBROADCASTD xmm k zmm +// VPBROADCASTD xmm zmm +// Construct and append a VPBROADCASTD instruction to the active function. +// Operates on the global context. +func VPBROADCASTD(ops ...operand.Op) { ctx.VPBROADCASTD(ops...) } + +// VPBROADCASTD_Z: Broadcast Doubleword Integer (Zeroing Masking). +// +// Forms: +// +// VPBROADCASTD.Z m32 k xmm +// VPBROADCASTD.Z m32 k ymm +// VPBROADCASTD.Z r32 k xmm +// VPBROADCASTD.Z r32 k ymm +// VPBROADCASTD.Z xmm k xmm +// VPBROADCASTD.Z xmm k ymm +// VPBROADCASTD.Z m32 k zmm +// VPBROADCASTD.Z r32 k zmm +// VPBROADCASTD.Z xmm k zmm +// Construct and append a VPBROADCASTD.Z instruction to the active function. +func (c *Context) VPBROADCASTD_Z(mrx, k, xyz operand.Op) { + c.addinstruction(x86.VPBROADCASTD_Z(mrx, k, xyz)) +} + +// VPBROADCASTD_Z: Broadcast Doubleword Integer (Zeroing Masking). +// +// Forms: +// +// VPBROADCASTD.Z m32 k xmm +// VPBROADCASTD.Z m32 k ymm +// VPBROADCASTD.Z r32 k xmm +// VPBROADCASTD.Z r32 k ymm +// VPBROADCASTD.Z xmm k xmm +// VPBROADCASTD.Z xmm k ymm +// VPBROADCASTD.Z m32 k zmm +// VPBROADCASTD.Z r32 k zmm +// VPBROADCASTD.Z xmm k zmm +// Construct and append a VPBROADCASTD.Z instruction to the active function. +// Operates on the global context. +func VPBROADCASTD_Z(mrx, k, xyz operand.Op) { ctx.VPBROADCASTD_Z(mrx, k, xyz) } + +// VPBROADCASTMB2Q: Broadcast Low Byte of Mask Register to Packed Quadword Values. +// +// Forms: +// +// VPBROADCASTMB2Q k xmm +// VPBROADCASTMB2Q k ymm +// VPBROADCASTMB2Q k zmm +// Construct and append a VPBROADCASTMB2Q instruction to the active function. +func (c *Context) VPBROADCASTMB2Q(k, xyz operand.Op) { + c.addinstruction(x86.VPBROADCASTMB2Q(k, xyz)) +} + +// VPBROADCASTMB2Q: Broadcast Low Byte of Mask Register to Packed Quadword Values. +// +// Forms: +// +// VPBROADCASTMB2Q k xmm +// VPBROADCASTMB2Q k ymm +// VPBROADCASTMB2Q k zmm +// Construct and append a VPBROADCASTMB2Q instruction to the active function. +// Operates on the global context. +func VPBROADCASTMB2Q(k, xyz operand.Op) { ctx.VPBROADCASTMB2Q(k, xyz) } + +// VPBROADCASTMW2D: Broadcast Low Word of Mask Register to Packed Doubleword Values. +// +// Forms: +// +// VPBROADCASTMW2D k xmm +// VPBROADCASTMW2D k ymm +// VPBROADCASTMW2D k zmm +// Construct and append a VPBROADCASTMW2D instruction to the active function. +func (c *Context) VPBROADCASTMW2D(k, xyz operand.Op) { + c.addinstruction(x86.VPBROADCASTMW2D(k, xyz)) +} + +// VPBROADCASTMW2D: Broadcast Low Word of Mask Register to Packed Doubleword Values. +// +// Forms: +// +// VPBROADCASTMW2D k xmm +// VPBROADCASTMW2D k ymm +// VPBROADCASTMW2D k zmm +// Construct and append a VPBROADCASTMW2D instruction to the active function. +// Operates on the global context. +func VPBROADCASTMW2D(k, xyz operand.Op) { ctx.VPBROADCASTMW2D(k, xyz) } + +// VPBROADCASTQ: Broadcast Quadword Integer. +// +// Forms: +// +// VPBROADCASTQ m64 xmm +// VPBROADCASTQ m64 ymm +// VPBROADCASTQ xmm xmm +// VPBROADCASTQ xmm ymm +// VPBROADCASTQ m64 k xmm +// VPBROADCASTQ m64 k ymm +// VPBROADCASTQ r64 k xmm +// VPBROADCASTQ r64 k ymm +// VPBROADCASTQ r64 xmm +// VPBROADCASTQ r64 ymm +// VPBROADCASTQ xmm k xmm +// VPBROADCASTQ xmm k ymm +// VPBROADCASTQ m64 k zmm +// VPBROADCASTQ m64 zmm +// VPBROADCASTQ r64 k zmm +// VPBROADCASTQ r64 zmm +// VPBROADCASTQ xmm k zmm +// VPBROADCASTQ xmm zmm +// Construct and append a VPBROADCASTQ instruction to the active function. +func (c *Context) VPBROADCASTQ(ops ...operand.Op) { + c.addinstruction(x86.VPBROADCASTQ(ops...)) +} + +// VPBROADCASTQ: Broadcast Quadword Integer. +// +// Forms: +// +// VPBROADCASTQ m64 xmm +// VPBROADCASTQ m64 ymm +// VPBROADCASTQ xmm xmm +// VPBROADCASTQ xmm ymm +// VPBROADCASTQ m64 k xmm +// VPBROADCASTQ m64 k ymm +// VPBROADCASTQ r64 k xmm +// VPBROADCASTQ r64 k ymm +// VPBROADCASTQ r64 xmm +// VPBROADCASTQ r64 ymm +// VPBROADCASTQ xmm k xmm +// VPBROADCASTQ xmm k ymm +// VPBROADCASTQ m64 k zmm +// VPBROADCASTQ m64 zmm +// VPBROADCASTQ r64 k zmm +// VPBROADCASTQ r64 zmm +// VPBROADCASTQ xmm k zmm +// VPBROADCASTQ xmm zmm +// Construct and append a VPBROADCASTQ instruction to the active function. +// Operates on the global context. +func VPBROADCASTQ(ops ...operand.Op) { ctx.VPBROADCASTQ(ops...) } + +// VPBROADCASTQ_Z: Broadcast Quadword Integer (Zeroing Masking). +// +// Forms: +// +// VPBROADCASTQ.Z m64 k xmm +// VPBROADCASTQ.Z m64 k ymm +// VPBROADCASTQ.Z r64 k xmm +// VPBROADCASTQ.Z r64 k ymm +// VPBROADCASTQ.Z xmm k xmm +// VPBROADCASTQ.Z xmm k ymm +// VPBROADCASTQ.Z m64 k zmm +// VPBROADCASTQ.Z r64 k zmm +// VPBROADCASTQ.Z xmm k zmm +// Construct and append a VPBROADCASTQ.Z instruction to the active function. +func (c *Context) VPBROADCASTQ_Z(mrx, k, xyz operand.Op) { + c.addinstruction(x86.VPBROADCASTQ_Z(mrx, k, xyz)) +} + +// VPBROADCASTQ_Z: Broadcast Quadword Integer (Zeroing Masking). +// +// Forms: +// +// VPBROADCASTQ.Z m64 k xmm +// VPBROADCASTQ.Z m64 k ymm +// VPBROADCASTQ.Z r64 k xmm +// VPBROADCASTQ.Z r64 k ymm +// VPBROADCASTQ.Z xmm k xmm +// VPBROADCASTQ.Z xmm k ymm +// VPBROADCASTQ.Z m64 k zmm +// VPBROADCASTQ.Z r64 k zmm +// VPBROADCASTQ.Z xmm k zmm +// Construct and append a VPBROADCASTQ.Z instruction to the active function. +// Operates on the global context. +func VPBROADCASTQ_Z(mrx, k, xyz operand.Op) { ctx.VPBROADCASTQ_Z(mrx, k, xyz) } + +// VPBROADCASTW: Broadcast Word Integer. +// +// Forms: +// +// VPBROADCASTW m16 xmm +// VPBROADCASTW m16 ymm +// VPBROADCASTW xmm xmm +// VPBROADCASTW xmm ymm +// VPBROADCASTW m16 k xmm +// VPBROADCASTW m16 k ymm +// VPBROADCASTW r32 k xmm +// VPBROADCASTW r32 k ymm +// VPBROADCASTW r32 xmm +// VPBROADCASTW r32 ymm +// VPBROADCASTW xmm k xmm +// VPBROADCASTW xmm k ymm +// VPBROADCASTW m16 k zmm +// VPBROADCASTW m16 zmm +// VPBROADCASTW r32 k zmm +// VPBROADCASTW r32 zmm +// VPBROADCASTW xmm k zmm +// VPBROADCASTW xmm zmm +// Construct and append a VPBROADCASTW instruction to the active function. +func (c *Context) VPBROADCASTW(ops ...operand.Op) { + c.addinstruction(x86.VPBROADCASTW(ops...)) +} + +// VPBROADCASTW: Broadcast Word Integer. +// +// Forms: +// +// VPBROADCASTW m16 xmm +// VPBROADCASTW m16 ymm +// VPBROADCASTW xmm xmm +// VPBROADCASTW xmm ymm +// VPBROADCASTW m16 k xmm +// VPBROADCASTW m16 k ymm +// VPBROADCASTW r32 k xmm +// VPBROADCASTW r32 k ymm +// VPBROADCASTW r32 xmm +// VPBROADCASTW r32 ymm +// VPBROADCASTW xmm k xmm +// VPBROADCASTW xmm k ymm +// VPBROADCASTW m16 k zmm +// VPBROADCASTW m16 zmm +// VPBROADCASTW r32 k zmm +// VPBROADCASTW r32 zmm +// VPBROADCASTW xmm k zmm +// VPBROADCASTW xmm zmm +// Construct and append a VPBROADCASTW instruction to the active function. +// Operates on the global context. +func VPBROADCASTW(ops ...operand.Op) { ctx.VPBROADCASTW(ops...) } + +// VPBROADCASTW_Z: Broadcast Word Integer (Zeroing Masking). +// +// Forms: +// +// VPBROADCASTW.Z m16 k xmm +// VPBROADCASTW.Z m16 k ymm +// VPBROADCASTW.Z r32 k xmm +// VPBROADCASTW.Z r32 k ymm +// VPBROADCASTW.Z xmm k xmm +// VPBROADCASTW.Z xmm k ymm +// VPBROADCASTW.Z m16 k zmm +// VPBROADCASTW.Z r32 k zmm +// VPBROADCASTW.Z xmm k zmm +// Construct and append a VPBROADCASTW.Z instruction to the active function. +func (c *Context) VPBROADCASTW_Z(mrx, k, xyz operand.Op) { + c.addinstruction(x86.VPBROADCASTW_Z(mrx, k, xyz)) +} + +// VPBROADCASTW_Z: Broadcast Word Integer (Zeroing Masking). +// +// Forms: +// +// VPBROADCASTW.Z m16 k xmm +// VPBROADCASTW.Z m16 k ymm +// VPBROADCASTW.Z r32 k xmm +// VPBROADCASTW.Z r32 k ymm +// VPBROADCASTW.Z xmm k xmm +// VPBROADCASTW.Z xmm k ymm +// VPBROADCASTW.Z m16 k zmm +// VPBROADCASTW.Z r32 k zmm +// VPBROADCASTW.Z xmm k zmm +// Construct and append a VPBROADCASTW.Z instruction to the active function. +// Operates on the global context. +func VPBROADCASTW_Z(mrx, k, xyz operand.Op) { ctx.VPBROADCASTW_Z(mrx, k, xyz) } + +// VPCLMULQDQ: Carry-Less Quadword Multiplication. +// +// Forms: +// +// VPCLMULQDQ imm8 m128 xmm xmm +// VPCLMULQDQ imm8 xmm xmm xmm +// Construct and append a VPCLMULQDQ instruction to the active function. +func (c *Context) VPCLMULQDQ(i, mx, x, x1 operand.Op) { + c.addinstruction(x86.VPCLMULQDQ(i, mx, x, x1)) +} + +// VPCLMULQDQ: Carry-Less Quadword Multiplication. +// +// Forms: +// +// VPCLMULQDQ imm8 m128 xmm xmm +// VPCLMULQDQ imm8 xmm xmm xmm +// Construct and append a VPCLMULQDQ instruction to the active function. +// Operates on the global context. +func VPCLMULQDQ(i, mx, x, x1 operand.Op) { ctx.VPCLMULQDQ(i, mx, x, x1) } + +// VPCMPB: Compare Packed Signed Byte Values. +// +// Forms: +// +// VPCMPB imm8 m128 xmm k k +// VPCMPB imm8 m128 xmm k +// VPCMPB imm8 m256 ymm k k +// VPCMPB imm8 m256 ymm k +// VPCMPB imm8 xmm xmm k k +// VPCMPB imm8 xmm xmm k +// VPCMPB imm8 ymm ymm k k +// VPCMPB imm8 ymm ymm k +// VPCMPB imm8 m512 zmm k k +// VPCMPB imm8 m512 zmm k +// VPCMPB imm8 zmm zmm k k +// VPCMPB imm8 zmm zmm k +// Construct and append a VPCMPB instruction to the active function. +func (c *Context) VPCMPB(ops ...operand.Op) { + c.addinstruction(x86.VPCMPB(ops...)) +} + +// VPCMPB: Compare Packed Signed Byte Values. +// +// Forms: +// +// VPCMPB imm8 m128 xmm k k +// VPCMPB imm8 m128 xmm k +// VPCMPB imm8 m256 ymm k k +// VPCMPB imm8 m256 ymm k +// VPCMPB imm8 xmm xmm k k +// VPCMPB imm8 xmm xmm k +// VPCMPB imm8 ymm ymm k k +// VPCMPB imm8 ymm ymm k +// VPCMPB imm8 m512 zmm k k +// VPCMPB imm8 m512 zmm k +// VPCMPB imm8 zmm zmm k k +// VPCMPB imm8 zmm zmm k +// Construct and append a VPCMPB instruction to the active function. +// Operates on the global context. +func VPCMPB(ops ...operand.Op) { ctx.VPCMPB(ops...) } + +// VPCMPD: Compare Packed Signed Doubleword Values. +// +// Forms: +// +// VPCMPD imm8 m128 xmm k k +// VPCMPD imm8 m128 xmm k +// VPCMPD imm8 m256 ymm k k +// VPCMPD imm8 m256 ymm k +// VPCMPD imm8 xmm xmm k k +// VPCMPD imm8 xmm xmm k +// VPCMPD imm8 ymm ymm k k +// VPCMPD imm8 ymm ymm k +// VPCMPD imm8 m512 zmm k k +// VPCMPD imm8 m512 zmm k +// VPCMPD imm8 zmm zmm k k +// VPCMPD imm8 zmm zmm k +// Construct and append a VPCMPD instruction to the active function. +func (c *Context) VPCMPD(ops ...operand.Op) { + c.addinstruction(x86.VPCMPD(ops...)) +} + +// VPCMPD: Compare Packed Signed Doubleword Values. +// +// Forms: +// +// VPCMPD imm8 m128 xmm k k +// VPCMPD imm8 m128 xmm k +// VPCMPD imm8 m256 ymm k k +// VPCMPD imm8 m256 ymm k +// VPCMPD imm8 xmm xmm k k +// VPCMPD imm8 xmm xmm k +// VPCMPD imm8 ymm ymm k k +// VPCMPD imm8 ymm ymm k +// VPCMPD imm8 m512 zmm k k +// VPCMPD imm8 m512 zmm k +// VPCMPD imm8 zmm zmm k k +// VPCMPD imm8 zmm zmm k +// Construct and append a VPCMPD instruction to the active function. +// Operates on the global context. +func VPCMPD(ops ...operand.Op) { ctx.VPCMPD(ops...) } + +// VPCMPD_BCST: Compare Packed Signed Doubleword Values (Broadcast). +// +// Forms: +// +// VPCMPD.BCST imm8 m32 xmm k k +// VPCMPD.BCST imm8 m32 xmm k +// VPCMPD.BCST imm8 m32 ymm k k +// VPCMPD.BCST imm8 m32 ymm k +// VPCMPD.BCST imm8 m32 zmm k k +// VPCMPD.BCST imm8 m32 zmm k +// Construct and append a VPCMPD.BCST instruction to the active function. +func (c *Context) VPCMPD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPCMPD_BCST(ops...)) +} + +// VPCMPD_BCST: Compare Packed Signed Doubleword Values (Broadcast). +// +// Forms: +// +// VPCMPD.BCST imm8 m32 xmm k k +// VPCMPD.BCST imm8 m32 xmm k +// VPCMPD.BCST imm8 m32 ymm k k +// VPCMPD.BCST imm8 m32 ymm k +// VPCMPD.BCST imm8 m32 zmm k k +// VPCMPD.BCST imm8 m32 zmm k +// Construct and append a VPCMPD.BCST instruction to the active function. +// Operates on the global context. +func VPCMPD_BCST(ops ...operand.Op) { ctx.VPCMPD_BCST(ops...) } + +// VPCMPEQB: Compare Packed Byte Data for Equality. +// +// Forms: +// +// VPCMPEQB m256 ymm ymm +// VPCMPEQB ymm ymm ymm +// VPCMPEQB m128 xmm xmm +// VPCMPEQB xmm xmm xmm +// VPCMPEQB m128 xmm k k +// VPCMPEQB m128 xmm k +// VPCMPEQB m256 ymm k k +// VPCMPEQB m256 ymm k +// VPCMPEQB xmm xmm k k +// VPCMPEQB xmm xmm k +// VPCMPEQB ymm ymm k k +// VPCMPEQB ymm ymm k +// VPCMPEQB m512 zmm k k +// VPCMPEQB m512 zmm k +// VPCMPEQB zmm zmm k k +// VPCMPEQB zmm zmm k +// Construct and append a VPCMPEQB instruction to the active function. +func (c *Context) VPCMPEQB(ops ...operand.Op) { + c.addinstruction(x86.VPCMPEQB(ops...)) +} + +// VPCMPEQB: Compare Packed Byte Data for Equality. +// +// Forms: +// +// VPCMPEQB m256 ymm ymm +// VPCMPEQB ymm ymm ymm +// VPCMPEQB m128 xmm xmm +// VPCMPEQB xmm xmm xmm +// VPCMPEQB m128 xmm k k +// VPCMPEQB m128 xmm k +// VPCMPEQB m256 ymm k k +// VPCMPEQB m256 ymm k +// VPCMPEQB xmm xmm k k +// VPCMPEQB xmm xmm k +// VPCMPEQB ymm ymm k k +// VPCMPEQB ymm ymm k +// VPCMPEQB m512 zmm k k +// VPCMPEQB m512 zmm k +// VPCMPEQB zmm zmm k k +// VPCMPEQB zmm zmm k +// Construct and append a VPCMPEQB instruction to the active function. +// Operates on the global context. +func VPCMPEQB(ops ...operand.Op) { ctx.VPCMPEQB(ops...) } + +// VPCMPEQD: Compare Packed Doubleword Data for Equality. +// +// Forms: +// +// VPCMPEQD m256 ymm ymm +// VPCMPEQD ymm ymm ymm +// VPCMPEQD m128 xmm xmm +// VPCMPEQD xmm xmm xmm +// VPCMPEQD m128 xmm k k +// VPCMPEQD m128 xmm k +// VPCMPEQD m256 ymm k k +// VPCMPEQD m256 ymm k +// VPCMPEQD xmm xmm k k +// VPCMPEQD xmm xmm k +// VPCMPEQD ymm ymm k k +// VPCMPEQD ymm ymm k +// VPCMPEQD m512 zmm k k +// VPCMPEQD m512 zmm k +// VPCMPEQD zmm zmm k k +// VPCMPEQD zmm zmm k +// Construct and append a VPCMPEQD instruction to the active function. +func (c *Context) VPCMPEQD(ops ...operand.Op) { + c.addinstruction(x86.VPCMPEQD(ops...)) +} + +// VPCMPEQD: Compare Packed Doubleword Data for Equality. +// +// Forms: +// +// VPCMPEQD m256 ymm ymm +// VPCMPEQD ymm ymm ymm +// VPCMPEQD m128 xmm xmm +// VPCMPEQD xmm xmm xmm +// VPCMPEQD m128 xmm k k +// VPCMPEQD m128 xmm k +// VPCMPEQD m256 ymm k k +// VPCMPEQD m256 ymm k +// VPCMPEQD xmm xmm k k +// VPCMPEQD xmm xmm k +// VPCMPEQD ymm ymm k k +// VPCMPEQD ymm ymm k +// VPCMPEQD m512 zmm k k +// VPCMPEQD m512 zmm k +// VPCMPEQD zmm zmm k k +// VPCMPEQD zmm zmm k +// Construct and append a VPCMPEQD instruction to the active function. +// Operates on the global context. +func VPCMPEQD(ops ...operand.Op) { ctx.VPCMPEQD(ops...) } + +// VPCMPEQD_BCST: Compare Packed Doubleword Data for Equality (Broadcast). +// +// Forms: +// +// VPCMPEQD.BCST m32 xmm k k +// VPCMPEQD.BCST m32 xmm k +// VPCMPEQD.BCST m32 ymm k k +// VPCMPEQD.BCST m32 ymm k +// VPCMPEQD.BCST m32 zmm k k +// VPCMPEQD.BCST m32 zmm k +// Construct and append a VPCMPEQD.BCST instruction to the active function. +func (c *Context) VPCMPEQD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPCMPEQD_BCST(ops...)) +} + +// VPCMPEQD_BCST: Compare Packed Doubleword Data for Equality (Broadcast). +// +// Forms: +// +// VPCMPEQD.BCST m32 xmm k k +// VPCMPEQD.BCST m32 xmm k +// VPCMPEQD.BCST m32 ymm k k +// VPCMPEQD.BCST m32 ymm k +// VPCMPEQD.BCST m32 zmm k k +// VPCMPEQD.BCST m32 zmm k +// Construct and append a VPCMPEQD.BCST instruction to the active function. +// Operates on the global context. +func VPCMPEQD_BCST(ops ...operand.Op) { ctx.VPCMPEQD_BCST(ops...) } + +// VPCMPEQQ: Compare Packed Quadword Data for Equality. +// +// Forms: +// +// VPCMPEQQ m256 ymm ymm +// VPCMPEQQ ymm ymm ymm +// VPCMPEQQ m128 xmm xmm +// VPCMPEQQ xmm xmm xmm +// VPCMPEQQ m128 xmm k k +// VPCMPEQQ m128 xmm k +// VPCMPEQQ m256 ymm k k +// VPCMPEQQ m256 ymm k +// VPCMPEQQ xmm xmm k k +// VPCMPEQQ xmm xmm k +// VPCMPEQQ ymm ymm k k +// VPCMPEQQ ymm ymm k +// VPCMPEQQ m512 zmm k k +// VPCMPEQQ m512 zmm k +// VPCMPEQQ zmm zmm k k +// VPCMPEQQ zmm zmm k +// Construct and append a VPCMPEQQ instruction to the active function. +func (c *Context) VPCMPEQQ(ops ...operand.Op) { + c.addinstruction(x86.VPCMPEQQ(ops...)) +} + +// VPCMPEQQ: Compare Packed Quadword Data for Equality. +// +// Forms: +// +// VPCMPEQQ m256 ymm ymm +// VPCMPEQQ ymm ymm ymm +// VPCMPEQQ m128 xmm xmm +// VPCMPEQQ xmm xmm xmm +// VPCMPEQQ m128 xmm k k +// VPCMPEQQ m128 xmm k +// VPCMPEQQ m256 ymm k k +// VPCMPEQQ m256 ymm k +// VPCMPEQQ xmm xmm k k +// VPCMPEQQ xmm xmm k +// VPCMPEQQ ymm ymm k k +// VPCMPEQQ ymm ymm k +// VPCMPEQQ m512 zmm k k +// VPCMPEQQ m512 zmm k +// VPCMPEQQ zmm zmm k k +// VPCMPEQQ zmm zmm k +// Construct and append a VPCMPEQQ instruction to the active function. +// Operates on the global context. +func VPCMPEQQ(ops ...operand.Op) { ctx.VPCMPEQQ(ops...) } + +// VPCMPEQQ_BCST: Compare Packed Quadword Data for Equality (Broadcast). +// +// Forms: +// +// VPCMPEQQ.BCST m64 xmm k k +// VPCMPEQQ.BCST m64 xmm k +// VPCMPEQQ.BCST m64 ymm k k +// VPCMPEQQ.BCST m64 ymm k +// VPCMPEQQ.BCST m64 zmm k k +// VPCMPEQQ.BCST m64 zmm k +// Construct and append a VPCMPEQQ.BCST instruction to the active function. +func (c *Context) VPCMPEQQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPCMPEQQ_BCST(ops...)) +} + +// VPCMPEQQ_BCST: Compare Packed Quadword Data for Equality (Broadcast). +// +// Forms: +// +// VPCMPEQQ.BCST m64 xmm k k +// VPCMPEQQ.BCST m64 xmm k +// VPCMPEQQ.BCST m64 ymm k k +// VPCMPEQQ.BCST m64 ymm k +// VPCMPEQQ.BCST m64 zmm k k +// VPCMPEQQ.BCST m64 zmm k +// Construct and append a VPCMPEQQ.BCST instruction to the active function. +// Operates on the global context. +func VPCMPEQQ_BCST(ops ...operand.Op) { ctx.VPCMPEQQ_BCST(ops...) } + +// VPCMPEQW: Compare Packed Word Data for Equality. +// +// Forms: +// +// VPCMPEQW m256 ymm ymm +// VPCMPEQW ymm ymm ymm +// VPCMPEQW m128 xmm xmm +// VPCMPEQW xmm xmm xmm +// VPCMPEQW m128 xmm k k +// VPCMPEQW m128 xmm k +// VPCMPEQW m256 ymm k k +// VPCMPEQW m256 ymm k +// VPCMPEQW xmm xmm k k +// VPCMPEQW xmm xmm k +// VPCMPEQW ymm ymm k k +// VPCMPEQW ymm ymm k +// VPCMPEQW m512 zmm k k +// VPCMPEQW m512 zmm k +// VPCMPEQW zmm zmm k k +// VPCMPEQW zmm zmm k +// Construct and append a VPCMPEQW instruction to the active function. +func (c *Context) VPCMPEQW(ops ...operand.Op) { + c.addinstruction(x86.VPCMPEQW(ops...)) +} + +// VPCMPEQW: Compare Packed Word Data for Equality. +// +// Forms: +// +// VPCMPEQW m256 ymm ymm +// VPCMPEQW ymm ymm ymm +// VPCMPEQW m128 xmm xmm +// VPCMPEQW xmm xmm xmm +// VPCMPEQW m128 xmm k k +// VPCMPEQW m128 xmm k +// VPCMPEQW m256 ymm k k +// VPCMPEQW m256 ymm k +// VPCMPEQW xmm xmm k k +// VPCMPEQW xmm xmm k +// VPCMPEQW ymm ymm k k +// VPCMPEQW ymm ymm k +// VPCMPEQW m512 zmm k k +// VPCMPEQW m512 zmm k +// VPCMPEQW zmm zmm k k +// VPCMPEQW zmm zmm k +// Construct and append a VPCMPEQW instruction to the active function. +// Operates on the global context. +func VPCMPEQW(ops ...operand.Op) { ctx.VPCMPEQW(ops...) } + +// VPCMPESTRI: Packed Compare Explicit Length Strings, Return Index. +// +// Forms: +// +// VPCMPESTRI imm8 m128 xmm +// VPCMPESTRI imm8 xmm xmm +// Construct and append a VPCMPESTRI instruction to the active function. +func (c *Context) VPCMPESTRI(i, mx, x operand.Op) { + c.addinstruction(x86.VPCMPESTRI(i, mx, x)) +} + +// VPCMPESTRI: Packed Compare Explicit Length Strings, Return Index. +// +// Forms: +// +// VPCMPESTRI imm8 m128 xmm +// VPCMPESTRI imm8 xmm xmm +// Construct and append a VPCMPESTRI instruction to the active function. +// Operates on the global context. +func VPCMPESTRI(i, mx, x operand.Op) { ctx.VPCMPESTRI(i, mx, x) } + +// VPCMPESTRM: Packed Compare Explicit Length Strings, Return Mask. +// +// Forms: +// +// VPCMPESTRM imm8 m128 xmm +// VPCMPESTRM imm8 xmm xmm +// Construct and append a VPCMPESTRM instruction to the active function. +func (c *Context) VPCMPESTRM(i, mx, x operand.Op) { + c.addinstruction(x86.VPCMPESTRM(i, mx, x)) +} + +// VPCMPESTRM: Packed Compare Explicit Length Strings, Return Mask. +// +// Forms: +// +// VPCMPESTRM imm8 m128 xmm +// VPCMPESTRM imm8 xmm xmm +// Construct and append a VPCMPESTRM instruction to the active function. +// Operates on the global context. +func VPCMPESTRM(i, mx, x operand.Op) { ctx.VPCMPESTRM(i, mx, x) } + +// VPCMPGTB: Compare Packed Signed Byte Integers for Greater Than. +// +// Forms: +// +// VPCMPGTB m256 ymm ymm +// VPCMPGTB ymm ymm ymm +// VPCMPGTB m128 xmm xmm +// VPCMPGTB xmm xmm xmm +// VPCMPGTB m128 xmm k k +// VPCMPGTB m128 xmm k +// VPCMPGTB m256 ymm k k +// VPCMPGTB m256 ymm k +// VPCMPGTB xmm xmm k k +// VPCMPGTB xmm xmm k +// VPCMPGTB ymm ymm k k +// VPCMPGTB ymm ymm k +// VPCMPGTB m512 zmm k k +// VPCMPGTB m512 zmm k +// VPCMPGTB zmm zmm k k +// VPCMPGTB zmm zmm k +// Construct and append a VPCMPGTB instruction to the active function. +func (c *Context) VPCMPGTB(ops ...operand.Op) { + c.addinstruction(x86.VPCMPGTB(ops...)) +} + +// VPCMPGTB: Compare Packed Signed Byte Integers for Greater Than. +// +// Forms: +// +// VPCMPGTB m256 ymm ymm +// VPCMPGTB ymm ymm ymm +// VPCMPGTB m128 xmm xmm +// VPCMPGTB xmm xmm xmm +// VPCMPGTB m128 xmm k k +// VPCMPGTB m128 xmm k +// VPCMPGTB m256 ymm k k +// VPCMPGTB m256 ymm k +// VPCMPGTB xmm xmm k k +// VPCMPGTB xmm xmm k +// VPCMPGTB ymm ymm k k +// VPCMPGTB ymm ymm k +// VPCMPGTB m512 zmm k k +// VPCMPGTB m512 zmm k +// VPCMPGTB zmm zmm k k +// VPCMPGTB zmm zmm k +// Construct and append a VPCMPGTB instruction to the active function. +// Operates on the global context. +func VPCMPGTB(ops ...operand.Op) { ctx.VPCMPGTB(ops...) } + +// VPCMPGTD: Compare Packed Signed Doubleword Integers for Greater Than. +// +// Forms: +// +// VPCMPGTD m256 ymm ymm +// VPCMPGTD ymm ymm ymm +// VPCMPGTD m128 xmm xmm +// VPCMPGTD xmm xmm xmm +// VPCMPGTD m128 xmm k k +// VPCMPGTD m128 xmm k +// VPCMPGTD m256 ymm k k +// VPCMPGTD m256 ymm k +// VPCMPGTD xmm xmm k k +// VPCMPGTD xmm xmm k +// VPCMPGTD ymm ymm k k +// VPCMPGTD ymm ymm k +// VPCMPGTD m512 zmm k k +// VPCMPGTD m512 zmm k +// VPCMPGTD zmm zmm k k +// VPCMPGTD zmm zmm k +// Construct and append a VPCMPGTD instruction to the active function. +func (c *Context) VPCMPGTD(ops ...operand.Op) { + c.addinstruction(x86.VPCMPGTD(ops...)) +} + +// VPCMPGTD: Compare Packed Signed Doubleword Integers for Greater Than. +// +// Forms: +// +// VPCMPGTD m256 ymm ymm +// VPCMPGTD ymm ymm ymm +// VPCMPGTD m128 xmm xmm +// VPCMPGTD xmm xmm xmm +// VPCMPGTD m128 xmm k k +// VPCMPGTD m128 xmm k +// VPCMPGTD m256 ymm k k +// VPCMPGTD m256 ymm k +// VPCMPGTD xmm xmm k k +// VPCMPGTD xmm xmm k +// VPCMPGTD ymm ymm k k +// VPCMPGTD ymm ymm k +// VPCMPGTD m512 zmm k k +// VPCMPGTD m512 zmm k +// VPCMPGTD zmm zmm k k +// VPCMPGTD zmm zmm k +// Construct and append a VPCMPGTD instruction to the active function. +// Operates on the global context. +func VPCMPGTD(ops ...operand.Op) { ctx.VPCMPGTD(ops...) } + +// VPCMPGTD_BCST: Compare Packed Signed Doubleword Integers for Greater Than (Broadcast). +// +// Forms: +// +// VPCMPGTD.BCST m32 xmm k k +// VPCMPGTD.BCST m32 xmm k +// VPCMPGTD.BCST m32 ymm k k +// VPCMPGTD.BCST m32 ymm k +// VPCMPGTD.BCST m32 zmm k k +// VPCMPGTD.BCST m32 zmm k +// Construct and append a VPCMPGTD.BCST instruction to the active function. +func (c *Context) VPCMPGTD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPCMPGTD_BCST(ops...)) +} + +// VPCMPGTD_BCST: Compare Packed Signed Doubleword Integers for Greater Than (Broadcast). +// +// Forms: +// +// VPCMPGTD.BCST m32 xmm k k +// VPCMPGTD.BCST m32 xmm k +// VPCMPGTD.BCST m32 ymm k k +// VPCMPGTD.BCST m32 ymm k +// VPCMPGTD.BCST m32 zmm k k +// VPCMPGTD.BCST m32 zmm k +// Construct and append a VPCMPGTD.BCST instruction to the active function. +// Operates on the global context. +func VPCMPGTD_BCST(ops ...operand.Op) { ctx.VPCMPGTD_BCST(ops...) } + +// VPCMPGTQ: Compare Packed Data for Greater Than. +// +// Forms: +// +// VPCMPGTQ m256 ymm ymm +// VPCMPGTQ ymm ymm ymm +// VPCMPGTQ m128 xmm xmm +// VPCMPGTQ xmm xmm xmm +// VPCMPGTQ m128 xmm k k +// VPCMPGTQ m128 xmm k +// VPCMPGTQ m256 ymm k k +// VPCMPGTQ m256 ymm k +// VPCMPGTQ xmm xmm k k +// VPCMPGTQ xmm xmm k +// VPCMPGTQ ymm ymm k k +// VPCMPGTQ ymm ymm k +// VPCMPGTQ m512 zmm k k +// VPCMPGTQ m512 zmm k +// VPCMPGTQ zmm zmm k k +// VPCMPGTQ zmm zmm k +// Construct and append a VPCMPGTQ instruction to the active function. +func (c *Context) VPCMPGTQ(ops ...operand.Op) { + c.addinstruction(x86.VPCMPGTQ(ops...)) +} + +// VPCMPGTQ: Compare Packed Data for Greater Than. +// +// Forms: +// +// VPCMPGTQ m256 ymm ymm +// VPCMPGTQ ymm ymm ymm +// VPCMPGTQ m128 xmm xmm +// VPCMPGTQ xmm xmm xmm +// VPCMPGTQ m128 xmm k k +// VPCMPGTQ m128 xmm k +// VPCMPGTQ m256 ymm k k +// VPCMPGTQ m256 ymm k +// VPCMPGTQ xmm xmm k k +// VPCMPGTQ xmm xmm k +// VPCMPGTQ ymm ymm k k +// VPCMPGTQ ymm ymm k +// VPCMPGTQ m512 zmm k k +// VPCMPGTQ m512 zmm k +// VPCMPGTQ zmm zmm k k +// VPCMPGTQ zmm zmm k +// Construct and append a VPCMPGTQ instruction to the active function. +// Operates on the global context. +func VPCMPGTQ(ops ...operand.Op) { ctx.VPCMPGTQ(ops...) } + +// VPCMPGTQ_BCST: Compare Packed Data for Greater Than (Broadcast). +// +// Forms: +// +// VPCMPGTQ.BCST m64 xmm k k +// VPCMPGTQ.BCST m64 xmm k +// VPCMPGTQ.BCST m64 ymm k k +// VPCMPGTQ.BCST m64 ymm k +// VPCMPGTQ.BCST m64 zmm k k +// VPCMPGTQ.BCST m64 zmm k +// Construct and append a VPCMPGTQ.BCST instruction to the active function. +func (c *Context) VPCMPGTQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPCMPGTQ_BCST(ops...)) +} + +// VPCMPGTQ_BCST: Compare Packed Data for Greater Than (Broadcast). +// +// Forms: +// +// VPCMPGTQ.BCST m64 xmm k k +// VPCMPGTQ.BCST m64 xmm k +// VPCMPGTQ.BCST m64 ymm k k +// VPCMPGTQ.BCST m64 ymm k +// VPCMPGTQ.BCST m64 zmm k k +// VPCMPGTQ.BCST m64 zmm k +// Construct and append a VPCMPGTQ.BCST instruction to the active function. +// Operates on the global context. +func VPCMPGTQ_BCST(ops ...operand.Op) { ctx.VPCMPGTQ_BCST(ops...) } + +// VPCMPGTW: Compare Packed Signed Word Integers for Greater Than. +// +// Forms: +// +// VPCMPGTW m256 ymm ymm +// VPCMPGTW ymm ymm ymm +// VPCMPGTW m128 xmm xmm +// VPCMPGTW xmm xmm xmm +// VPCMPGTW m128 xmm k k +// VPCMPGTW m128 xmm k +// VPCMPGTW m256 ymm k k +// VPCMPGTW m256 ymm k +// VPCMPGTW xmm xmm k k +// VPCMPGTW xmm xmm k +// VPCMPGTW ymm ymm k k +// VPCMPGTW ymm ymm k +// VPCMPGTW m512 zmm k k +// VPCMPGTW m512 zmm k +// VPCMPGTW zmm zmm k k +// VPCMPGTW zmm zmm k +// Construct and append a VPCMPGTW instruction to the active function. +func (c *Context) VPCMPGTW(ops ...operand.Op) { + c.addinstruction(x86.VPCMPGTW(ops...)) +} + +// VPCMPGTW: Compare Packed Signed Word Integers for Greater Than. +// +// Forms: +// +// VPCMPGTW m256 ymm ymm +// VPCMPGTW ymm ymm ymm +// VPCMPGTW m128 xmm xmm +// VPCMPGTW xmm xmm xmm +// VPCMPGTW m128 xmm k k +// VPCMPGTW m128 xmm k +// VPCMPGTW m256 ymm k k +// VPCMPGTW m256 ymm k +// VPCMPGTW xmm xmm k k +// VPCMPGTW xmm xmm k +// VPCMPGTW ymm ymm k k +// VPCMPGTW ymm ymm k +// VPCMPGTW m512 zmm k k +// VPCMPGTW m512 zmm k +// VPCMPGTW zmm zmm k k +// VPCMPGTW zmm zmm k +// Construct and append a VPCMPGTW instruction to the active function. +// Operates on the global context. +func VPCMPGTW(ops ...operand.Op) { ctx.VPCMPGTW(ops...) } + +// VPCMPISTRI: Packed Compare Implicit Length Strings, Return Index. +// +// Forms: +// +// VPCMPISTRI imm8 m128 xmm +// VPCMPISTRI imm8 xmm xmm +// Construct and append a VPCMPISTRI instruction to the active function. +func (c *Context) VPCMPISTRI(i, mx, x operand.Op) { + c.addinstruction(x86.VPCMPISTRI(i, mx, x)) +} + +// VPCMPISTRI: Packed Compare Implicit Length Strings, Return Index. +// +// Forms: +// +// VPCMPISTRI imm8 m128 xmm +// VPCMPISTRI imm8 xmm xmm +// Construct and append a VPCMPISTRI instruction to the active function. +// Operates on the global context. +func VPCMPISTRI(i, mx, x operand.Op) { ctx.VPCMPISTRI(i, mx, x) } + +// VPCMPISTRM: Packed Compare Implicit Length Strings, Return Mask. +// +// Forms: +// +// VPCMPISTRM imm8 m128 xmm +// VPCMPISTRM imm8 xmm xmm +// Construct and append a VPCMPISTRM instruction to the active function. +func (c *Context) VPCMPISTRM(i, mx, x operand.Op) { + c.addinstruction(x86.VPCMPISTRM(i, mx, x)) +} + +// VPCMPISTRM: Packed Compare Implicit Length Strings, Return Mask. +// +// Forms: +// +// VPCMPISTRM imm8 m128 xmm +// VPCMPISTRM imm8 xmm xmm +// Construct and append a VPCMPISTRM instruction to the active function. +// Operates on the global context. +func VPCMPISTRM(i, mx, x operand.Op) { ctx.VPCMPISTRM(i, mx, x) } + +// VPCMPQ: Compare Packed Signed Quadword Values. +// +// Forms: +// +// VPCMPQ imm8 m128 xmm k k +// VPCMPQ imm8 m128 xmm k +// VPCMPQ imm8 m256 ymm k k +// VPCMPQ imm8 m256 ymm k +// VPCMPQ imm8 xmm xmm k k +// VPCMPQ imm8 xmm xmm k +// VPCMPQ imm8 ymm ymm k k +// VPCMPQ imm8 ymm ymm k +// VPCMPQ imm8 m512 zmm k k +// VPCMPQ imm8 m512 zmm k +// VPCMPQ imm8 zmm zmm k k +// VPCMPQ imm8 zmm zmm k +// Construct and append a VPCMPQ instruction to the active function. +func (c *Context) VPCMPQ(ops ...operand.Op) { + c.addinstruction(x86.VPCMPQ(ops...)) +} + +// VPCMPQ: Compare Packed Signed Quadword Values. +// +// Forms: +// +// VPCMPQ imm8 m128 xmm k k +// VPCMPQ imm8 m128 xmm k +// VPCMPQ imm8 m256 ymm k k +// VPCMPQ imm8 m256 ymm k +// VPCMPQ imm8 xmm xmm k k +// VPCMPQ imm8 xmm xmm k +// VPCMPQ imm8 ymm ymm k k +// VPCMPQ imm8 ymm ymm k +// VPCMPQ imm8 m512 zmm k k +// VPCMPQ imm8 m512 zmm k +// VPCMPQ imm8 zmm zmm k k +// VPCMPQ imm8 zmm zmm k +// Construct and append a VPCMPQ instruction to the active function. +// Operates on the global context. +func VPCMPQ(ops ...operand.Op) { ctx.VPCMPQ(ops...) } + +// VPCMPQ_BCST: Compare Packed Signed Quadword Values (Broadcast). +// +// Forms: +// +// VPCMPQ.BCST imm8 m64 xmm k k +// VPCMPQ.BCST imm8 m64 xmm k +// VPCMPQ.BCST imm8 m64 ymm k k +// VPCMPQ.BCST imm8 m64 ymm k +// VPCMPQ.BCST imm8 m64 zmm k k +// VPCMPQ.BCST imm8 m64 zmm k +// Construct and append a VPCMPQ.BCST instruction to the active function. +func (c *Context) VPCMPQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPCMPQ_BCST(ops...)) +} + +// VPCMPQ_BCST: Compare Packed Signed Quadword Values (Broadcast). +// +// Forms: +// +// VPCMPQ.BCST imm8 m64 xmm k k +// VPCMPQ.BCST imm8 m64 xmm k +// VPCMPQ.BCST imm8 m64 ymm k k +// VPCMPQ.BCST imm8 m64 ymm k +// VPCMPQ.BCST imm8 m64 zmm k k +// VPCMPQ.BCST imm8 m64 zmm k +// Construct and append a VPCMPQ.BCST instruction to the active function. +// Operates on the global context. +func VPCMPQ_BCST(ops ...operand.Op) { ctx.VPCMPQ_BCST(ops...) } + +// VPCMPUB: Compare Packed Unsigned Byte Values. +// +// Forms: +// +// VPCMPUB imm8 m128 xmm k k +// VPCMPUB imm8 m128 xmm k +// VPCMPUB imm8 m256 ymm k k +// VPCMPUB imm8 m256 ymm k +// VPCMPUB imm8 xmm xmm k k +// VPCMPUB imm8 xmm xmm k +// VPCMPUB imm8 ymm ymm k k +// VPCMPUB imm8 ymm ymm k +// VPCMPUB imm8 m512 zmm k k +// VPCMPUB imm8 m512 zmm k +// VPCMPUB imm8 zmm zmm k k +// VPCMPUB imm8 zmm zmm k +// Construct and append a VPCMPUB instruction to the active function. +func (c *Context) VPCMPUB(ops ...operand.Op) { + c.addinstruction(x86.VPCMPUB(ops...)) +} + +// VPCMPUB: Compare Packed Unsigned Byte Values. +// +// Forms: +// +// VPCMPUB imm8 m128 xmm k k +// VPCMPUB imm8 m128 xmm k +// VPCMPUB imm8 m256 ymm k k +// VPCMPUB imm8 m256 ymm k +// VPCMPUB imm8 xmm xmm k k +// VPCMPUB imm8 xmm xmm k +// VPCMPUB imm8 ymm ymm k k +// VPCMPUB imm8 ymm ymm k +// VPCMPUB imm8 m512 zmm k k +// VPCMPUB imm8 m512 zmm k +// VPCMPUB imm8 zmm zmm k k +// VPCMPUB imm8 zmm zmm k +// Construct and append a VPCMPUB instruction to the active function. +// Operates on the global context. +func VPCMPUB(ops ...operand.Op) { ctx.VPCMPUB(ops...) } + +// VPCMPUD: Compare Packed Unsigned Doubleword Values. +// +// Forms: +// +// VPCMPUD imm8 m128 xmm k k +// VPCMPUD imm8 m128 xmm k +// VPCMPUD imm8 m256 ymm k k +// VPCMPUD imm8 m256 ymm k +// VPCMPUD imm8 xmm xmm k k +// VPCMPUD imm8 xmm xmm k +// VPCMPUD imm8 ymm ymm k k +// VPCMPUD imm8 ymm ymm k +// VPCMPUD imm8 m512 zmm k k +// VPCMPUD imm8 m512 zmm k +// VPCMPUD imm8 zmm zmm k k +// VPCMPUD imm8 zmm zmm k +// Construct and append a VPCMPUD instruction to the active function. +func (c *Context) VPCMPUD(ops ...operand.Op) { + c.addinstruction(x86.VPCMPUD(ops...)) +} + +// VPCMPUD: Compare Packed Unsigned Doubleword Values. +// +// Forms: +// +// VPCMPUD imm8 m128 xmm k k +// VPCMPUD imm8 m128 xmm k +// VPCMPUD imm8 m256 ymm k k +// VPCMPUD imm8 m256 ymm k +// VPCMPUD imm8 xmm xmm k k +// VPCMPUD imm8 xmm xmm k +// VPCMPUD imm8 ymm ymm k k +// VPCMPUD imm8 ymm ymm k +// VPCMPUD imm8 m512 zmm k k +// VPCMPUD imm8 m512 zmm k +// VPCMPUD imm8 zmm zmm k k +// VPCMPUD imm8 zmm zmm k +// Construct and append a VPCMPUD instruction to the active function. +// Operates on the global context. +func VPCMPUD(ops ...operand.Op) { ctx.VPCMPUD(ops...) } + +// VPCMPUD_BCST: Compare Packed Unsigned Doubleword Values (Broadcast). +// +// Forms: +// +// VPCMPUD.BCST imm8 m32 xmm k k +// VPCMPUD.BCST imm8 m32 xmm k +// VPCMPUD.BCST imm8 m32 ymm k k +// VPCMPUD.BCST imm8 m32 ymm k +// VPCMPUD.BCST imm8 m32 zmm k k +// VPCMPUD.BCST imm8 m32 zmm k +// Construct and append a VPCMPUD.BCST instruction to the active function. +func (c *Context) VPCMPUD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPCMPUD_BCST(ops...)) +} + +// VPCMPUD_BCST: Compare Packed Unsigned Doubleword Values (Broadcast). +// +// Forms: +// +// VPCMPUD.BCST imm8 m32 xmm k k +// VPCMPUD.BCST imm8 m32 xmm k +// VPCMPUD.BCST imm8 m32 ymm k k +// VPCMPUD.BCST imm8 m32 ymm k +// VPCMPUD.BCST imm8 m32 zmm k k +// VPCMPUD.BCST imm8 m32 zmm k +// Construct and append a VPCMPUD.BCST instruction to the active function. +// Operates on the global context. +func VPCMPUD_BCST(ops ...operand.Op) { ctx.VPCMPUD_BCST(ops...) } + +// VPCMPUQ: Compare Packed Unsigned Quadword Values. +// +// Forms: +// +// VPCMPUQ imm8 m128 xmm k k +// VPCMPUQ imm8 m128 xmm k +// VPCMPUQ imm8 m256 ymm k k +// VPCMPUQ imm8 m256 ymm k +// VPCMPUQ imm8 xmm xmm k k +// VPCMPUQ imm8 xmm xmm k +// VPCMPUQ imm8 ymm ymm k k +// VPCMPUQ imm8 ymm ymm k +// VPCMPUQ imm8 m512 zmm k k +// VPCMPUQ imm8 m512 zmm k +// VPCMPUQ imm8 zmm zmm k k +// VPCMPUQ imm8 zmm zmm k +// Construct and append a VPCMPUQ instruction to the active function. +func (c *Context) VPCMPUQ(ops ...operand.Op) { + c.addinstruction(x86.VPCMPUQ(ops...)) +} + +// VPCMPUQ: Compare Packed Unsigned Quadword Values. +// +// Forms: +// +// VPCMPUQ imm8 m128 xmm k k +// VPCMPUQ imm8 m128 xmm k +// VPCMPUQ imm8 m256 ymm k k +// VPCMPUQ imm8 m256 ymm k +// VPCMPUQ imm8 xmm xmm k k +// VPCMPUQ imm8 xmm xmm k +// VPCMPUQ imm8 ymm ymm k k +// VPCMPUQ imm8 ymm ymm k +// VPCMPUQ imm8 m512 zmm k k +// VPCMPUQ imm8 m512 zmm k +// VPCMPUQ imm8 zmm zmm k k +// VPCMPUQ imm8 zmm zmm k +// Construct and append a VPCMPUQ instruction to the active function. +// Operates on the global context. +func VPCMPUQ(ops ...operand.Op) { ctx.VPCMPUQ(ops...) } + +// VPCMPUQ_BCST: Compare Packed Unsigned Quadword Values (Broadcast). +// +// Forms: +// +// VPCMPUQ.BCST imm8 m64 xmm k k +// VPCMPUQ.BCST imm8 m64 xmm k +// VPCMPUQ.BCST imm8 m64 ymm k k +// VPCMPUQ.BCST imm8 m64 ymm k +// VPCMPUQ.BCST imm8 m64 zmm k k +// VPCMPUQ.BCST imm8 m64 zmm k +// Construct and append a VPCMPUQ.BCST instruction to the active function. +func (c *Context) VPCMPUQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPCMPUQ_BCST(ops...)) +} + +// VPCMPUQ_BCST: Compare Packed Unsigned Quadword Values (Broadcast). +// +// Forms: +// +// VPCMPUQ.BCST imm8 m64 xmm k k +// VPCMPUQ.BCST imm8 m64 xmm k +// VPCMPUQ.BCST imm8 m64 ymm k k +// VPCMPUQ.BCST imm8 m64 ymm k +// VPCMPUQ.BCST imm8 m64 zmm k k +// VPCMPUQ.BCST imm8 m64 zmm k +// Construct and append a VPCMPUQ.BCST instruction to the active function. +// Operates on the global context. +func VPCMPUQ_BCST(ops ...operand.Op) { ctx.VPCMPUQ_BCST(ops...) } + +// VPCMPUW: Compare Packed Unsigned Word Values. +// +// Forms: +// +// VPCMPUW imm8 m128 xmm k k +// VPCMPUW imm8 m128 xmm k +// VPCMPUW imm8 m256 ymm k k +// VPCMPUW imm8 m256 ymm k +// VPCMPUW imm8 xmm xmm k k +// VPCMPUW imm8 xmm xmm k +// VPCMPUW imm8 ymm ymm k k +// VPCMPUW imm8 ymm ymm k +// VPCMPUW imm8 m512 zmm k k +// VPCMPUW imm8 m512 zmm k +// VPCMPUW imm8 zmm zmm k k +// VPCMPUW imm8 zmm zmm k +// Construct and append a VPCMPUW instruction to the active function. +func (c *Context) VPCMPUW(ops ...operand.Op) { + c.addinstruction(x86.VPCMPUW(ops...)) +} + +// VPCMPUW: Compare Packed Unsigned Word Values. +// +// Forms: +// +// VPCMPUW imm8 m128 xmm k k +// VPCMPUW imm8 m128 xmm k +// VPCMPUW imm8 m256 ymm k k +// VPCMPUW imm8 m256 ymm k +// VPCMPUW imm8 xmm xmm k k +// VPCMPUW imm8 xmm xmm k +// VPCMPUW imm8 ymm ymm k k +// VPCMPUW imm8 ymm ymm k +// VPCMPUW imm8 m512 zmm k k +// VPCMPUW imm8 m512 zmm k +// VPCMPUW imm8 zmm zmm k k +// VPCMPUW imm8 zmm zmm k +// Construct and append a VPCMPUW instruction to the active function. +// Operates on the global context. +func VPCMPUW(ops ...operand.Op) { ctx.VPCMPUW(ops...) } + +// VPCMPW: Compare Packed Signed Word Values. +// +// Forms: +// +// VPCMPW imm8 m128 xmm k k +// VPCMPW imm8 m128 xmm k +// VPCMPW imm8 m256 ymm k k +// VPCMPW imm8 m256 ymm k +// VPCMPW imm8 xmm xmm k k +// VPCMPW imm8 xmm xmm k +// VPCMPW imm8 ymm ymm k k +// VPCMPW imm8 ymm ymm k +// VPCMPW imm8 m512 zmm k k +// VPCMPW imm8 m512 zmm k +// VPCMPW imm8 zmm zmm k k +// VPCMPW imm8 zmm zmm k +// Construct and append a VPCMPW instruction to the active function. +func (c *Context) VPCMPW(ops ...operand.Op) { + c.addinstruction(x86.VPCMPW(ops...)) +} + +// VPCMPW: Compare Packed Signed Word Values. +// +// Forms: +// +// VPCMPW imm8 m128 xmm k k +// VPCMPW imm8 m128 xmm k +// VPCMPW imm8 m256 ymm k k +// VPCMPW imm8 m256 ymm k +// VPCMPW imm8 xmm xmm k k +// VPCMPW imm8 xmm xmm k +// VPCMPW imm8 ymm ymm k k +// VPCMPW imm8 ymm ymm k +// VPCMPW imm8 m512 zmm k k +// VPCMPW imm8 m512 zmm k +// VPCMPW imm8 zmm zmm k k +// VPCMPW imm8 zmm zmm k +// Construct and append a VPCMPW instruction to the active function. +// Operates on the global context. +func VPCMPW(ops ...operand.Op) { ctx.VPCMPW(ops...) } + +// VPCOMPRESSD: Store Sparse Packed Doubleword Integer Values into Dense Memory/Register. +// +// Forms: +// +// VPCOMPRESSD xmm k m128 +// VPCOMPRESSD xmm k xmm +// VPCOMPRESSD xmm m128 +// VPCOMPRESSD xmm xmm +// VPCOMPRESSD ymm k m256 +// VPCOMPRESSD ymm k ymm +// VPCOMPRESSD ymm m256 +// VPCOMPRESSD ymm ymm +// VPCOMPRESSD zmm k m512 +// VPCOMPRESSD zmm k zmm +// VPCOMPRESSD zmm m512 +// VPCOMPRESSD zmm zmm +// Construct and append a VPCOMPRESSD instruction to the active function. +func (c *Context) VPCOMPRESSD(ops ...operand.Op) { + c.addinstruction(x86.VPCOMPRESSD(ops...)) +} + +// VPCOMPRESSD: Store Sparse Packed Doubleword Integer Values into Dense Memory/Register. +// +// Forms: +// +// VPCOMPRESSD xmm k m128 +// VPCOMPRESSD xmm k xmm +// VPCOMPRESSD xmm m128 +// VPCOMPRESSD xmm xmm +// VPCOMPRESSD ymm k m256 +// VPCOMPRESSD ymm k ymm +// VPCOMPRESSD ymm m256 +// VPCOMPRESSD ymm ymm +// VPCOMPRESSD zmm k m512 +// VPCOMPRESSD zmm k zmm +// VPCOMPRESSD zmm m512 +// VPCOMPRESSD zmm zmm +// Construct and append a VPCOMPRESSD instruction to the active function. +// Operates on the global context. +func VPCOMPRESSD(ops ...operand.Op) { ctx.VPCOMPRESSD(ops...) } + +// VPCOMPRESSD_Z: Store Sparse Packed Doubleword Integer Values into Dense Memory/Register (Zeroing Masking). +// +// Forms: +// +// VPCOMPRESSD.Z xmm k m128 +// VPCOMPRESSD.Z xmm k xmm +// VPCOMPRESSD.Z ymm k m256 +// VPCOMPRESSD.Z ymm k ymm +// VPCOMPRESSD.Z zmm k m512 +// VPCOMPRESSD.Z zmm k zmm +// Construct and append a VPCOMPRESSD.Z instruction to the active function. +func (c *Context) VPCOMPRESSD_Z(xyz, k, mxyz operand.Op) { + c.addinstruction(x86.VPCOMPRESSD_Z(xyz, k, mxyz)) +} + +// VPCOMPRESSD_Z: Store Sparse Packed Doubleword Integer Values into Dense Memory/Register (Zeroing Masking). +// +// Forms: +// +// VPCOMPRESSD.Z xmm k m128 +// VPCOMPRESSD.Z xmm k xmm +// VPCOMPRESSD.Z ymm k m256 +// VPCOMPRESSD.Z ymm k ymm +// VPCOMPRESSD.Z zmm k m512 +// VPCOMPRESSD.Z zmm k zmm +// Construct and append a VPCOMPRESSD.Z instruction to the active function. +// Operates on the global context. +func VPCOMPRESSD_Z(xyz, k, mxyz operand.Op) { ctx.VPCOMPRESSD_Z(xyz, k, mxyz) } + +// VPCOMPRESSQ: Store Sparse Packed Quadword Integer Values into Dense Memory/Register. +// +// Forms: +// +// VPCOMPRESSQ xmm k m128 +// VPCOMPRESSQ xmm k xmm +// VPCOMPRESSQ xmm m128 +// VPCOMPRESSQ xmm xmm +// VPCOMPRESSQ ymm k m256 +// VPCOMPRESSQ ymm k ymm +// VPCOMPRESSQ ymm m256 +// VPCOMPRESSQ ymm ymm +// VPCOMPRESSQ zmm k m512 +// VPCOMPRESSQ zmm k zmm +// VPCOMPRESSQ zmm m512 +// VPCOMPRESSQ zmm zmm +// Construct and append a VPCOMPRESSQ instruction to the active function. +func (c *Context) VPCOMPRESSQ(ops ...operand.Op) { + c.addinstruction(x86.VPCOMPRESSQ(ops...)) +} + +// VPCOMPRESSQ: Store Sparse Packed Quadword Integer Values into Dense Memory/Register. +// +// Forms: +// +// VPCOMPRESSQ xmm k m128 +// VPCOMPRESSQ xmm k xmm +// VPCOMPRESSQ xmm m128 +// VPCOMPRESSQ xmm xmm +// VPCOMPRESSQ ymm k m256 +// VPCOMPRESSQ ymm k ymm +// VPCOMPRESSQ ymm m256 +// VPCOMPRESSQ ymm ymm +// VPCOMPRESSQ zmm k m512 +// VPCOMPRESSQ zmm k zmm +// VPCOMPRESSQ zmm m512 +// VPCOMPRESSQ zmm zmm +// Construct and append a VPCOMPRESSQ instruction to the active function. +// Operates on the global context. +func VPCOMPRESSQ(ops ...operand.Op) { ctx.VPCOMPRESSQ(ops...) } + +// VPCOMPRESSQ_Z: Store Sparse Packed Quadword Integer Values into Dense Memory/Register (Zeroing Masking). +// +// Forms: +// +// VPCOMPRESSQ.Z xmm k m128 +// VPCOMPRESSQ.Z xmm k xmm +// VPCOMPRESSQ.Z ymm k m256 +// VPCOMPRESSQ.Z ymm k ymm +// VPCOMPRESSQ.Z zmm k m512 +// VPCOMPRESSQ.Z zmm k zmm +// Construct and append a VPCOMPRESSQ.Z instruction to the active function. +func (c *Context) VPCOMPRESSQ_Z(xyz, k, mxyz operand.Op) { + c.addinstruction(x86.VPCOMPRESSQ_Z(xyz, k, mxyz)) +} + +// VPCOMPRESSQ_Z: Store Sparse Packed Quadword Integer Values into Dense Memory/Register (Zeroing Masking). +// +// Forms: +// +// VPCOMPRESSQ.Z xmm k m128 +// VPCOMPRESSQ.Z xmm k xmm +// VPCOMPRESSQ.Z ymm k m256 +// VPCOMPRESSQ.Z ymm k ymm +// VPCOMPRESSQ.Z zmm k m512 +// VPCOMPRESSQ.Z zmm k zmm +// Construct and append a VPCOMPRESSQ.Z instruction to the active function. +// Operates on the global context. +func VPCOMPRESSQ_Z(xyz, k, mxyz operand.Op) { ctx.VPCOMPRESSQ_Z(xyz, k, mxyz) } + +// VPCONFLICTD: Detect Conflicts Within a Vector of Packed Doubleword Values into Dense Memory/Register. +// +// Forms: +// +// VPCONFLICTD m128 k xmm +// VPCONFLICTD m128 xmm +// VPCONFLICTD m256 k ymm +// VPCONFLICTD m256 ymm +// VPCONFLICTD xmm k xmm +// VPCONFLICTD xmm xmm +// VPCONFLICTD ymm k ymm +// VPCONFLICTD ymm ymm +// VPCONFLICTD m512 k zmm +// VPCONFLICTD m512 zmm +// VPCONFLICTD zmm k zmm +// VPCONFLICTD zmm zmm +// Construct and append a VPCONFLICTD instruction to the active function. +func (c *Context) VPCONFLICTD(ops ...operand.Op) { + c.addinstruction(x86.VPCONFLICTD(ops...)) +} + +// VPCONFLICTD: Detect Conflicts Within a Vector of Packed Doubleword Values into Dense Memory/Register. +// +// Forms: +// +// VPCONFLICTD m128 k xmm +// VPCONFLICTD m128 xmm +// VPCONFLICTD m256 k ymm +// VPCONFLICTD m256 ymm +// VPCONFLICTD xmm k xmm +// VPCONFLICTD xmm xmm +// VPCONFLICTD ymm k ymm +// VPCONFLICTD ymm ymm +// VPCONFLICTD m512 k zmm +// VPCONFLICTD m512 zmm +// VPCONFLICTD zmm k zmm +// VPCONFLICTD zmm zmm +// Construct and append a VPCONFLICTD instruction to the active function. +// Operates on the global context. +func VPCONFLICTD(ops ...operand.Op) { ctx.VPCONFLICTD(ops...) } + +// VPCONFLICTD_BCST: Detect Conflicts Within a Vector of Packed Doubleword Values into Dense Memory/Register (Broadcast). +// +// Forms: +// +// VPCONFLICTD.BCST m32 k xmm +// VPCONFLICTD.BCST m32 k ymm +// VPCONFLICTD.BCST m32 xmm +// VPCONFLICTD.BCST m32 ymm +// VPCONFLICTD.BCST m32 k zmm +// VPCONFLICTD.BCST m32 zmm +// Construct and append a VPCONFLICTD.BCST instruction to the active function. +func (c *Context) VPCONFLICTD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPCONFLICTD_BCST(ops...)) +} + +// VPCONFLICTD_BCST: Detect Conflicts Within a Vector of Packed Doubleword Values into Dense Memory/Register (Broadcast). +// +// Forms: +// +// VPCONFLICTD.BCST m32 k xmm +// VPCONFLICTD.BCST m32 k ymm +// VPCONFLICTD.BCST m32 xmm +// VPCONFLICTD.BCST m32 ymm +// VPCONFLICTD.BCST m32 k zmm +// VPCONFLICTD.BCST m32 zmm +// Construct and append a VPCONFLICTD.BCST instruction to the active function. +// Operates on the global context. +func VPCONFLICTD_BCST(ops ...operand.Op) { ctx.VPCONFLICTD_BCST(ops...) } + +// VPCONFLICTD_BCST_Z: Detect Conflicts Within a Vector of Packed Doubleword Values into Dense Memory/Register (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPCONFLICTD.BCST.Z m32 k xmm +// VPCONFLICTD.BCST.Z m32 k ymm +// VPCONFLICTD.BCST.Z m32 k zmm +// Construct and append a VPCONFLICTD.BCST.Z instruction to the active function. +func (c *Context) VPCONFLICTD_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VPCONFLICTD_BCST_Z(m, k, xyz)) +} + +// VPCONFLICTD_BCST_Z: Detect Conflicts Within a Vector of Packed Doubleword Values into Dense Memory/Register (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPCONFLICTD.BCST.Z m32 k xmm +// VPCONFLICTD.BCST.Z m32 k ymm +// VPCONFLICTD.BCST.Z m32 k zmm +// Construct and append a VPCONFLICTD.BCST.Z instruction to the active function. +// Operates on the global context. +func VPCONFLICTD_BCST_Z(m, k, xyz operand.Op) { ctx.VPCONFLICTD_BCST_Z(m, k, xyz) } + +// VPCONFLICTD_Z: Detect Conflicts Within a Vector of Packed Doubleword Values into Dense Memory/Register (Zeroing Masking). +// +// Forms: +// +// VPCONFLICTD.Z m128 k xmm +// VPCONFLICTD.Z m256 k ymm +// VPCONFLICTD.Z xmm k xmm +// VPCONFLICTD.Z ymm k ymm +// VPCONFLICTD.Z m512 k zmm +// VPCONFLICTD.Z zmm k zmm +// Construct and append a VPCONFLICTD.Z instruction to the active function. +func (c *Context) VPCONFLICTD_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPCONFLICTD_Z(mxyz, k, xyz)) +} + +// VPCONFLICTD_Z: Detect Conflicts Within a Vector of Packed Doubleword Values into Dense Memory/Register (Zeroing Masking). +// +// Forms: +// +// VPCONFLICTD.Z m128 k xmm +// VPCONFLICTD.Z m256 k ymm +// VPCONFLICTD.Z xmm k xmm +// VPCONFLICTD.Z ymm k ymm +// VPCONFLICTD.Z m512 k zmm +// VPCONFLICTD.Z zmm k zmm +// Construct and append a VPCONFLICTD.Z instruction to the active function. +// Operates on the global context. +func VPCONFLICTD_Z(mxyz, k, xyz operand.Op) { ctx.VPCONFLICTD_Z(mxyz, k, xyz) } + +// VPCONFLICTQ: Detect Conflicts Within a Vector of Packed Quadword Values into Dense Memory/Register. +// +// Forms: +// +// VPCONFLICTQ m128 k xmm +// VPCONFLICTQ m128 xmm +// VPCONFLICTQ m256 k ymm +// VPCONFLICTQ m256 ymm +// VPCONFLICTQ xmm k xmm +// VPCONFLICTQ xmm xmm +// VPCONFLICTQ ymm k ymm +// VPCONFLICTQ ymm ymm +// VPCONFLICTQ m512 k zmm +// VPCONFLICTQ m512 zmm +// VPCONFLICTQ zmm k zmm +// VPCONFLICTQ zmm zmm +// Construct and append a VPCONFLICTQ instruction to the active function. +func (c *Context) VPCONFLICTQ(ops ...operand.Op) { + c.addinstruction(x86.VPCONFLICTQ(ops...)) +} + +// VPCONFLICTQ: Detect Conflicts Within a Vector of Packed Quadword Values into Dense Memory/Register. +// +// Forms: +// +// VPCONFLICTQ m128 k xmm +// VPCONFLICTQ m128 xmm +// VPCONFLICTQ m256 k ymm +// VPCONFLICTQ m256 ymm +// VPCONFLICTQ xmm k xmm +// VPCONFLICTQ xmm xmm +// VPCONFLICTQ ymm k ymm +// VPCONFLICTQ ymm ymm +// VPCONFLICTQ m512 k zmm +// VPCONFLICTQ m512 zmm +// VPCONFLICTQ zmm k zmm +// VPCONFLICTQ zmm zmm +// Construct and append a VPCONFLICTQ instruction to the active function. +// Operates on the global context. +func VPCONFLICTQ(ops ...operand.Op) { ctx.VPCONFLICTQ(ops...) } + +// VPCONFLICTQ_BCST: Detect Conflicts Within a Vector of Packed Quadword Values into Dense Memory/Register (Broadcast). +// +// Forms: +// +// VPCONFLICTQ.BCST m64 k xmm +// VPCONFLICTQ.BCST m64 k ymm +// VPCONFLICTQ.BCST m64 xmm +// VPCONFLICTQ.BCST m64 ymm +// VPCONFLICTQ.BCST m64 k zmm +// VPCONFLICTQ.BCST m64 zmm +// Construct and append a VPCONFLICTQ.BCST instruction to the active function. +func (c *Context) VPCONFLICTQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPCONFLICTQ_BCST(ops...)) +} + +// VPCONFLICTQ_BCST: Detect Conflicts Within a Vector of Packed Quadword Values into Dense Memory/Register (Broadcast). +// +// Forms: +// +// VPCONFLICTQ.BCST m64 k xmm +// VPCONFLICTQ.BCST m64 k ymm +// VPCONFLICTQ.BCST m64 xmm +// VPCONFLICTQ.BCST m64 ymm +// VPCONFLICTQ.BCST m64 k zmm +// VPCONFLICTQ.BCST m64 zmm +// Construct and append a VPCONFLICTQ.BCST instruction to the active function. +// Operates on the global context. +func VPCONFLICTQ_BCST(ops ...operand.Op) { ctx.VPCONFLICTQ_BCST(ops...) } + +// VPCONFLICTQ_BCST_Z: Detect Conflicts Within a Vector of Packed Quadword Values into Dense Memory/Register (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPCONFLICTQ.BCST.Z m64 k xmm +// VPCONFLICTQ.BCST.Z m64 k ymm +// VPCONFLICTQ.BCST.Z m64 k zmm +// Construct and append a VPCONFLICTQ.BCST.Z instruction to the active function. +func (c *Context) VPCONFLICTQ_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VPCONFLICTQ_BCST_Z(m, k, xyz)) +} + +// VPCONFLICTQ_BCST_Z: Detect Conflicts Within a Vector of Packed Quadword Values into Dense Memory/Register (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPCONFLICTQ.BCST.Z m64 k xmm +// VPCONFLICTQ.BCST.Z m64 k ymm +// VPCONFLICTQ.BCST.Z m64 k zmm +// Construct and append a VPCONFLICTQ.BCST.Z instruction to the active function. +// Operates on the global context. +func VPCONFLICTQ_BCST_Z(m, k, xyz operand.Op) { ctx.VPCONFLICTQ_BCST_Z(m, k, xyz) } + +// VPCONFLICTQ_Z: Detect Conflicts Within a Vector of Packed Quadword Values into Dense Memory/Register (Zeroing Masking). +// +// Forms: +// +// VPCONFLICTQ.Z m128 k xmm +// VPCONFLICTQ.Z m256 k ymm +// VPCONFLICTQ.Z xmm k xmm +// VPCONFLICTQ.Z ymm k ymm +// VPCONFLICTQ.Z m512 k zmm +// VPCONFLICTQ.Z zmm k zmm +// Construct and append a VPCONFLICTQ.Z instruction to the active function. +func (c *Context) VPCONFLICTQ_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPCONFLICTQ_Z(mxyz, k, xyz)) +} + +// VPCONFLICTQ_Z: Detect Conflicts Within a Vector of Packed Quadword Values into Dense Memory/Register (Zeroing Masking). +// +// Forms: +// +// VPCONFLICTQ.Z m128 k xmm +// VPCONFLICTQ.Z m256 k ymm +// VPCONFLICTQ.Z xmm k xmm +// VPCONFLICTQ.Z ymm k ymm +// VPCONFLICTQ.Z m512 k zmm +// VPCONFLICTQ.Z zmm k zmm +// Construct and append a VPCONFLICTQ.Z instruction to the active function. +// Operates on the global context. +func VPCONFLICTQ_Z(mxyz, k, xyz operand.Op) { ctx.VPCONFLICTQ_Z(mxyz, k, xyz) } + +// VPERM2F128: Permute Floating-Point Values. +// +// Forms: +// +// VPERM2F128 imm8 m256 ymm ymm +// VPERM2F128 imm8 ymm ymm ymm +// Construct and append a VPERM2F128 instruction to the active function. +func (c *Context) VPERM2F128(i, my, y, y1 operand.Op) { + c.addinstruction(x86.VPERM2F128(i, my, y, y1)) +} + +// VPERM2F128: Permute Floating-Point Values. +// +// Forms: +// +// VPERM2F128 imm8 m256 ymm ymm +// VPERM2F128 imm8 ymm ymm ymm +// Construct and append a VPERM2F128 instruction to the active function. +// Operates on the global context. +func VPERM2F128(i, my, y, y1 operand.Op) { ctx.VPERM2F128(i, my, y, y1) } + +// VPERM2I128: Permute 128-Bit Integer Values. +// +// Forms: +// +// VPERM2I128 imm8 m256 ymm ymm +// VPERM2I128 imm8 ymm ymm ymm +// Construct and append a VPERM2I128 instruction to the active function. +func (c *Context) VPERM2I128(i, my, y, y1 operand.Op) { + c.addinstruction(x86.VPERM2I128(i, my, y, y1)) +} + +// VPERM2I128: Permute 128-Bit Integer Values. +// +// Forms: +// +// VPERM2I128 imm8 m256 ymm ymm +// VPERM2I128 imm8 ymm ymm ymm +// Construct and append a VPERM2I128 instruction to the active function. +// Operates on the global context. +func VPERM2I128(i, my, y, y1 operand.Op) { ctx.VPERM2I128(i, my, y, y1) } + +// VPERMB: Permute Byte Integers. +// +// Forms: +// +// VPERMB m128 xmm k xmm +// VPERMB m128 xmm xmm +// VPERMB m256 ymm k ymm +// VPERMB m256 ymm ymm +// VPERMB xmm xmm k xmm +// VPERMB xmm xmm xmm +// VPERMB ymm ymm k ymm +// VPERMB ymm ymm ymm +// VPERMB m512 zmm k zmm +// VPERMB m512 zmm zmm +// VPERMB zmm zmm k zmm +// VPERMB zmm zmm zmm +// Construct and append a VPERMB instruction to the active function. +func (c *Context) VPERMB(ops ...operand.Op) { + c.addinstruction(x86.VPERMB(ops...)) +} + +// VPERMB: Permute Byte Integers. +// +// Forms: +// +// VPERMB m128 xmm k xmm +// VPERMB m128 xmm xmm +// VPERMB m256 ymm k ymm +// VPERMB m256 ymm ymm +// VPERMB xmm xmm k xmm +// VPERMB xmm xmm xmm +// VPERMB ymm ymm k ymm +// VPERMB ymm ymm ymm +// VPERMB m512 zmm k zmm +// VPERMB m512 zmm zmm +// VPERMB zmm zmm k zmm +// VPERMB zmm zmm zmm +// Construct and append a VPERMB instruction to the active function. +// Operates on the global context. +func VPERMB(ops ...operand.Op) { ctx.VPERMB(ops...) } + +// VPERMB_Z: Permute Byte Integers (Zeroing Masking). +// +// Forms: +// +// VPERMB.Z m128 xmm k xmm +// VPERMB.Z m256 ymm k ymm +// VPERMB.Z xmm xmm k xmm +// VPERMB.Z ymm ymm k ymm +// VPERMB.Z m512 zmm k zmm +// VPERMB.Z zmm zmm k zmm +// Construct and append a VPERMB.Z instruction to the active function. +func (c *Context) VPERMB_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPERMB_Z(mxyz, xyz, k, xyz1)) +} + +// VPERMB_Z: Permute Byte Integers (Zeroing Masking). +// +// Forms: +// +// VPERMB.Z m128 xmm k xmm +// VPERMB.Z m256 ymm k ymm +// VPERMB.Z xmm xmm k xmm +// VPERMB.Z ymm ymm k ymm +// VPERMB.Z m512 zmm k zmm +// VPERMB.Z zmm zmm k zmm +// Construct and append a VPERMB.Z instruction to the active function. +// Operates on the global context. +func VPERMB_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPERMB_Z(mxyz, xyz, k, xyz1) } + +// VPERMD: Permute Doubleword Integers. +// +// Forms: +// +// VPERMD m256 ymm ymm +// VPERMD ymm ymm ymm +// VPERMD m256 ymm k ymm +// VPERMD ymm ymm k ymm +// VPERMD m512 zmm k zmm +// VPERMD m512 zmm zmm +// VPERMD zmm zmm k zmm +// VPERMD zmm zmm zmm +// Construct and append a VPERMD instruction to the active function. +func (c *Context) VPERMD(ops ...operand.Op) { + c.addinstruction(x86.VPERMD(ops...)) +} + +// VPERMD: Permute Doubleword Integers. +// +// Forms: +// +// VPERMD m256 ymm ymm +// VPERMD ymm ymm ymm +// VPERMD m256 ymm k ymm +// VPERMD ymm ymm k ymm +// VPERMD m512 zmm k zmm +// VPERMD m512 zmm zmm +// VPERMD zmm zmm k zmm +// VPERMD zmm zmm zmm +// Construct and append a VPERMD instruction to the active function. +// Operates on the global context. +func VPERMD(ops ...operand.Op) { ctx.VPERMD(ops...) } + +// VPERMD_BCST: Permute Doubleword Integers (Broadcast). +// +// Forms: +// +// VPERMD.BCST m32 ymm k ymm +// VPERMD.BCST m32 ymm ymm +// VPERMD.BCST m32 zmm k zmm +// VPERMD.BCST m32 zmm zmm +// Construct and append a VPERMD.BCST instruction to the active function. +func (c *Context) VPERMD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPERMD_BCST(ops...)) +} + +// VPERMD_BCST: Permute Doubleword Integers (Broadcast). +// +// Forms: +// +// VPERMD.BCST m32 ymm k ymm +// VPERMD.BCST m32 ymm ymm +// VPERMD.BCST m32 zmm k zmm +// VPERMD.BCST m32 zmm zmm +// Construct and append a VPERMD.BCST instruction to the active function. +// Operates on the global context. +func VPERMD_BCST(ops ...operand.Op) { ctx.VPERMD_BCST(ops...) } + +// VPERMD_BCST_Z: Permute Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMD.BCST.Z m32 ymm k ymm +// VPERMD.BCST.Z m32 zmm k zmm +// Construct and append a VPERMD.BCST.Z instruction to the active function. +func (c *Context) VPERMD_BCST_Z(m, yz, k, yz1 operand.Op) { + c.addinstruction(x86.VPERMD_BCST_Z(m, yz, k, yz1)) +} + +// VPERMD_BCST_Z: Permute Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMD.BCST.Z m32 ymm k ymm +// VPERMD.BCST.Z m32 zmm k zmm +// Construct and append a VPERMD.BCST.Z instruction to the active function. +// Operates on the global context. +func VPERMD_BCST_Z(m, yz, k, yz1 operand.Op) { ctx.VPERMD_BCST_Z(m, yz, k, yz1) } + +// VPERMD_Z: Permute Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VPERMD.Z m256 ymm k ymm +// VPERMD.Z ymm ymm k ymm +// VPERMD.Z m512 zmm k zmm +// VPERMD.Z zmm zmm k zmm +// Construct and append a VPERMD.Z instruction to the active function. +func (c *Context) VPERMD_Z(myz, yz, k, yz1 operand.Op) { + c.addinstruction(x86.VPERMD_Z(myz, yz, k, yz1)) +} + +// VPERMD_Z: Permute Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VPERMD.Z m256 ymm k ymm +// VPERMD.Z ymm ymm k ymm +// VPERMD.Z m512 zmm k zmm +// VPERMD.Z zmm zmm k zmm +// Construct and append a VPERMD.Z instruction to the active function. +// Operates on the global context. +func VPERMD_Z(myz, yz, k, yz1 operand.Op) { ctx.VPERMD_Z(myz, yz, k, yz1) } + +// VPERMI2B: Full Permute of Bytes From Two Tables Overwriting the Index. +// +// Forms: +// +// VPERMI2B m128 xmm k xmm +// VPERMI2B m128 xmm xmm +// VPERMI2B m256 ymm k ymm +// VPERMI2B m256 ymm ymm +// VPERMI2B xmm xmm k xmm +// VPERMI2B xmm xmm xmm +// VPERMI2B ymm ymm k ymm +// VPERMI2B ymm ymm ymm +// VPERMI2B m512 zmm k zmm +// VPERMI2B m512 zmm zmm +// VPERMI2B zmm zmm k zmm +// VPERMI2B zmm zmm zmm +// Construct and append a VPERMI2B instruction to the active function. +func (c *Context) VPERMI2B(ops ...operand.Op) { + c.addinstruction(x86.VPERMI2B(ops...)) +} + +// VPERMI2B: Full Permute of Bytes From Two Tables Overwriting the Index. +// +// Forms: +// +// VPERMI2B m128 xmm k xmm +// VPERMI2B m128 xmm xmm +// VPERMI2B m256 ymm k ymm +// VPERMI2B m256 ymm ymm +// VPERMI2B xmm xmm k xmm +// VPERMI2B xmm xmm xmm +// VPERMI2B ymm ymm k ymm +// VPERMI2B ymm ymm ymm +// VPERMI2B m512 zmm k zmm +// VPERMI2B m512 zmm zmm +// VPERMI2B zmm zmm k zmm +// VPERMI2B zmm zmm zmm +// Construct and append a VPERMI2B instruction to the active function. +// Operates on the global context. +func VPERMI2B(ops ...operand.Op) { ctx.VPERMI2B(ops...) } + +// VPERMI2B_Z: Full Permute of Bytes From Two Tables Overwriting the Index (Zeroing Masking). +// +// Forms: +// +// VPERMI2B.Z m128 xmm k xmm +// VPERMI2B.Z m256 ymm k ymm +// VPERMI2B.Z xmm xmm k xmm +// VPERMI2B.Z ymm ymm k ymm +// VPERMI2B.Z m512 zmm k zmm +// VPERMI2B.Z zmm zmm k zmm +// Construct and append a VPERMI2B.Z instruction to the active function. +func (c *Context) VPERMI2B_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPERMI2B_Z(mxyz, xyz, k, xyz1)) +} + +// VPERMI2B_Z: Full Permute of Bytes From Two Tables Overwriting the Index (Zeroing Masking). +// +// Forms: +// +// VPERMI2B.Z m128 xmm k xmm +// VPERMI2B.Z m256 ymm k ymm +// VPERMI2B.Z xmm xmm k xmm +// VPERMI2B.Z ymm ymm k ymm +// VPERMI2B.Z m512 zmm k zmm +// VPERMI2B.Z zmm zmm k zmm +// Construct and append a VPERMI2B.Z instruction to the active function. +// Operates on the global context. +func VPERMI2B_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPERMI2B_Z(mxyz, xyz, k, xyz1) } + +// VPERMI2D: Full Permute of Doublewords From Two Tables Overwriting the Index. +// +// Forms: +// +// VPERMI2D m128 xmm k xmm +// VPERMI2D m128 xmm xmm +// VPERMI2D m256 ymm k ymm +// VPERMI2D m256 ymm ymm +// VPERMI2D xmm xmm k xmm +// VPERMI2D xmm xmm xmm +// VPERMI2D ymm ymm k ymm +// VPERMI2D ymm ymm ymm +// VPERMI2D m512 zmm k zmm +// VPERMI2D m512 zmm zmm +// VPERMI2D zmm zmm k zmm +// VPERMI2D zmm zmm zmm +// Construct and append a VPERMI2D instruction to the active function. +func (c *Context) VPERMI2D(ops ...operand.Op) { + c.addinstruction(x86.VPERMI2D(ops...)) +} + +// VPERMI2D: Full Permute of Doublewords From Two Tables Overwriting the Index. +// +// Forms: +// +// VPERMI2D m128 xmm k xmm +// VPERMI2D m128 xmm xmm +// VPERMI2D m256 ymm k ymm +// VPERMI2D m256 ymm ymm +// VPERMI2D xmm xmm k xmm +// VPERMI2D xmm xmm xmm +// VPERMI2D ymm ymm k ymm +// VPERMI2D ymm ymm ymm +// VPERMI2D m512 zmm k zmm +// VPERMI2D m512 zmm zmm +// VPERMI2D zmm zmm k zmm +// VPERMI2D zmm zmm zmm +// Construct and append a VPERMI2D instruction to the active function. +// Operates on the global context. +func VPERMI2D(ops ...operand.Op) { ctx.VPERMI2D(ops...) } + +// VPERMI2D_BCST: Full Permute of Doublewords From Two Tables Overwriting the Index (Broadcast). +// +// Forms: +// +// VPERMI2D.BCST m32 xmm k xmm +// VPERMI2D.BCST m32 xmm xmm +// VPERMI2D.BCST m32 ymm k ymm +// VPERMI2D.BCST m32 ymm ymm +// VPERMI2D.BCST m32 zmm k zmm +// VPERMI2D.BCST m32 zmm zmm +// Construct and append a VPERMI2D.BCST instruction to the active function. +func (c *Context) VPERMI2D_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPERMI2D_BCST(ops...)) +} + +// VPERMI2D_BCST: Full Permute of Doublewords From Two Tables Overwriting the Index (Broadcast). +// +// Forms: +// +// VPERMI2D.BCST m32 xmm k xmm +// VPERMI2D.BCST m32 xmm xmm +// VPERMI2D.BCST m32 ymm k ymm +// VPERMI2D.BCST m32 ymm ymm +// VPERMI2D.BCST m32 zmm k zmm +// VPERMI2D.BCST m32 zmm zmm +// Construct and append a VPERMI2D.BCST instruction to the active function. +// Operates on the global context. +func VPERMI2D_BCST(ops ...operand.Op) { ctx.VPERMI2D_BCST(ops...) } + +// VPERMI2D_BCST_Z: Full Permute of Doublewords From Two Tables Overwriting the Index (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMI2D.BCST.Z m32 xmm k xmm +// VPERMI2D.BCST.Z m32 ymm k ymm +// VPERMI2D.BCST.Z m32 zmm k zmm +// Construct and append a VPERMI2D.BCST.Z instruction to the active function. +func (c *Context) VPERMI2D_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPERMI2D_BCST_Z(m, xyz, k, xyz1)) +} + +// VPERMI2D_BCST_Z: Full Permute of Doublewords From Two Tables Overwriting the Index (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMI2D.BCST.Z m32 xmm k xmm +// VPERMI2D.BCST.Z m32 ymm k ymm +// VPERMI2D.BCST.Z m32 zmm k zmm +// Construct and append a VPERMI2D.BCST.Z instruction to the active function. +// Operates on the global context. +func VPERMI2D_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPERMI2D_BCST_Z(m, xyz, k, xyz1) } + +// VPERMI2D_Z: Full Permute of Doublewords From Two Tables Overwriting the Index (Zeroing Masking). +// +// Forms: +// +// VPERMI2D.Z m128 xmm k xmm +// VPERMI2D.Z m256 ymm k ymm +// VPERMI2D.Z xmm xmm k xmm +// VPERMI2D.Z ymm ymm k ymm +// VPERMI2D.Z m512 zmm k zmm +// VPERMI2D.Z zmm zmm k zmm +// Construct and append a VPERMI2D.Z instruction to the active function. +func (c *Context) VPERMI2D_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPERMI2D_Z(mxyz, xyz, k, xyz1)) +} + +// VPERMI2D_Z: Full Permute of Doublewords From Two Tables Overwriting the Index (Zeroing Masking). +// +// Forms: +// +// VPERMI2D.Z m128 xmm k xmm +// VPERMI2D.Z m256 ymm k ymm +// VPERMI2D.Z xmm xmm k xmm +// VPERMI2D.Z ymm ymm k ymm +// VPERMI2D.Z m512 zmm k zmm +// VPERMI2D.Z zmm zmm k zmm +// Construct and append a VPERMI2D.Z instruction to the active function. +// Operates on the global context. +func VPERMI2D_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPERMI2D_Z(mxyz, xyz, k, xyz1) } + +// VPERMI2PD: Full Permute of Double-Precision Floating-Point Values From Two Tables Overwriting the Index. +// +// Forms: +// +// VPERMI2PD m128 xmm k xmm +// VPERMI2PD m128 xmm xmm +// VPERMI2PD m256 ymm k ymm +// VPERMI2PD m256 ymm ymm +// VPERMI2PD xmm xmm k xmm +// VPERMI2PD xmm xmm xmm +// VPERMI2PD ymm ymm k ymm +// VPERMI2PD ymm ymm ymm +// VPERMI2PD m512 zmm k zmm +// VPERMI2PD m512 zmm zmm +// VPERMI2PD zmm zmm k zmm +// VPERMI2PD zmm zmm zmm +// Construct and append a VPERMI2PD instruction to the active function. +func (c *Context) VPERMI2PD(ops ...operand.Op) { + c.addinstruction(x86.VPERMI2PD(ops...)) +} + +// VPERMI2PD: Full Permute of Double-Precision Floating-Point Values From Two Tables Overwriting the Index. +// +// Forms: +// +// VPERMI2PD m128 xmm k xmm +// VPERMI2PD m128 xmm xmm +// VPERMI2PD m256 ymm k ymm +// VPERMI2PD m256 ymm ymm +// VPERMI2PD xmm xmm k xmm +// VPERMI2PD xmm xmm xmm +// VPERMI2PD ymm ymm k ymm +// VPERMI2PD ymm ymm ymm +// VPERMI2PD m512 zmm k zmm +// VPERMI2PD m512 zmm zmm +// VPERMI2PD zmm zmm k zmm +// VPERMI2PD zmm zmm zmm +// Construct and append a VPERMI2PD instruction to the active function. +// Operates on the global context. +func VPERMI2PD(ops ...operand.Op) { ctx.VPERMI2PD(ops...) } + +// VPERMI2PD_BCST: Full Permute of Double-Precision Floating-Point Values From Two Tables Overwriting the Index (Broadcast). +// +// Forms: +// +// VPERMI2PD.BCST m64 xmm k xmm +// VPERMI2PD.BCST m64 xmm xmm +// VPERMI2PD.BCST m64 ymm k ymm +// VPERMI2PD.BCST m64 ymm ymm +// VPERMI2PD.BCST m64 zmm k zmm +// VPERMI2PD.BCST m64 zmm zmm +// Construct and append a VPERMI2PD.BCST instruction to the active function. +func (c *Context) VPERMI2PD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPERMI2PD_BCST(ops...)) +} + +// VPERMI2PD_BCST: Full Permute of Double-Precision Floating-Point Values From Two Tables Overwriting the Index (Broadcast). +// +// Forms: +// +// VPERMI2PD.BCST m64 xmm k xmm +// VPERMI2PD.BCST m64 xmm xmm +// VPERMI2PD.BCST m64 ymm k ymm +// VPERMI2PD.BCST m64 ymm ymm +// VPERMI2PD.BCST m64 zmm k zmm +// VPERMI2PD.BCST m64 zmm zmm +// Construct and append a VPERMI2PD.BCST instruction to the active function. +// Operates on the global context. +func VPERMI2PD_BCST(ops ...operand.Op) { ctx.VPERMI2PD_BCST(ops...) } + +// VPERMI2PD_BCST_Z: Full Permute of Double-Precision Floating-Point Values From Two Tables Overwriting the Index (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMI2PD.BCST.Z m64 xmm k xmm +// VPERMI2PD.BCST.Z m64 ymm k ymm +// VPERMI2PD.BCST.Z m64 zmm k zmm +// Construct and append a VPERMI2PD.BCST.Z instruction to the active function. +func (c *Context) VPERMI2PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPERMI2PD_BCST_Z(m, xyz, k, xyz1)) +} + +// VPERMI2PD_BCST_Z: Full Permute of Double-Precision Floating-Point Values From Two Tables Overwriting the Index (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMI2PD.BCST.Z m64 xmm k xmm +// VPERMI2PD.BCST.Z m64 ymm k ymm +// VPERMI2PD.BCST.Z m64 zmm k zmm +// Construct and append a VPERMI2PD.BCST.Z instruction to the active function. +// Operates on the global context. +func VPERMI2PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPERMI2PD_BCST_Z(m, xyz, k, xyz1) } + +// VPERMI2PD_Z: Full Permute of Double-Precision Floating-Point Values From Two Tables Overwriting the Index (Zeroing Masking). +// +// Forms: +// +// VPERMI2PD.Z m128 xmm k xmm +// VPERMI2PD.Z m256 ymm k ymm +// VPERMI2PD.Z xmm xmm k xmm +// VPERMI2PD.Z ymm ymm k ymm +// VPERMI2PD.Z m512 zmm k zmm +// VPERMI2PD.Z zmm zmm k zmm +// Construct and append a VPERMI2PD.Z instruction to the active function. +func (c *Context) VPERMI2PD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPERMI2PD_Z(mxyz, xyz, k, xyz1)) +} + +// VPERMI2PD_Z: Full Permute of Double-Precision Floating-Point Values From Two Tables Overwriting the Index (Zeroing Masking). +// +// Forms: +// +// VPERMI2PD.Z m128 xmm k xmm +// VPERMI2PD.Z m256 ymm k ymm +// VPERMI2PD.Z xmm xmm k xmm +// VPERMI2PD.Z ymm ymm k ymm +// VPERMI2PD.Z m512 zmm k zmm +// VPERMI2PD.Z zmm zmm k zmm +// Construct and append a VPERMI2PD.Z instruction to the active function. +// Operates on the global context. +func VPERMI2PD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPERMI2PD_Z(mxyz, xyz, k, xyz1) } + +// VPERMI2PS: Full Permute of Single-Precision Floating-Point Values From Two Tables Overwriting the Index. +// +// Forms: +// +// VPERMI2PS m128 xmm k xmm +// VPERMI2PS m128 xmm xmm +// VPERMI2PS m256 ymm k ymm +// VPERMI2PS m256 ymm ymm +// VPERMI2PS xmm xmm k xmm +// VPERMI2PS xmm xmm xmm +// VPERMI2PS ymm ymm k ymm +// VPERMI2PS ymm ymm ymm +// VPERMI2PS m512 zmm k zmm +// VPERMI2PS m512 zmm zmm +// VPERMI2PS zmm zmm k zmm +// VPERMI2PS zmm zmm zmm +// Construct and append a VPERMI2PS instruction to the active function. +func (c *Context) VPERMI2PS(ops ...operand.Op) { + c.addinstruction(x86.VPERMI2PS(ops...)) +} + +// VPERMI2PS: Full Permute of Single-Precision Floating-Point Values From Two Tables Overwriting the Index. +// +// Forms: +// +// VPERMI2PS m128 xmm k xmm +// VPERMI2PS m128 xmm xmm +// VPERMI2PS m256 ymm k ymm +// VPERMI2PS m256 ymm ymm +// VPERMI2PS xmm xmm k xmm +// VPERMI2PS xmm xmm xmm +// VPERMI2PS ymm ymm k ymm +// VPERMI2PS ymm ymm ymm +// VPERMI2PS m512 zmm k zmm +// VPERMI2PS m512 zmm zmm +// VPERMI2PS zmm zmm k zmm +// VPERMI2PS zmm zmm zmm +// Construct and append a VPERMI2PS instruction to the active function. +// Operates on the global context. +func VPERMI2PS(ops ...operand.Op) { ctx.VPERMI2PS(ops...) } + +// VPERMI2PS_BCST: Full Permute of Single-Precision Floating-Point Values From Two Tables Overwriting the Index (Broadcast). +// +// Forms: +// +// VPERMI2PS.BCST m32 xmm k xmm +// VPERMI2PS.BCST m32 xmm xmm +// VPERMI2PS.BCST m32 ymm k ymm +// VPERMI2PS.BCST m32 ymm ymm +// VPERMI2PS.BCST m32 zmm k zmm +// VPERMI2PS.BCST m32 zmm zmm +// Construct and append a VPERMI2PS.BCST instruction to the active function. +func (c *Context) VPERMI2PS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPERMI2PS_BCST(ops...)) +} + +// VPERMI2PS_BCST: Full Permute of Single-Precision Floating-Point Values From Two Tables Overwriting the Index (Broadcast). +// +// Forms: +// +// VPERMI2PS.BCST m32 xmm k xmm +// VPERMI2PS.BCST m32 xmm xmm +// VPERMI2PS.BCST m32 ymm k ymm +// VPERMI2PS.BCST m32 ymm ymm +// VPERMI2PS.BCST m32 zmm k zmm +// VPERMI2PS.BCST m32 zmm zmm +// Construct and append a VPERMI2PS.BCST instruction to the active function. +// Operates on the global context. +func VPERMI2PS_BCST(ops ...operand.Op) { ctx.VPERMI2PS_BCST(ops...) } + +// VPERMI2PS_BCST_Z: Full Permute of Single-Precision Floating-Point Values From Two Tables Overwriting the Index (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMI2PS.BCST.Z m32 xmm k xmm +// VPERMI2PS.BCST.Z m32 ymm k ymm +// VPERMI2PS.BCST.Z m32 zmm k zmm +// Construct and append a VPERMI2PS.BCST.Z instruction to the active function. +func (c *Context) VPERMI2PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPERMI2PS_BCST_Z(m, xyz, k, xyz1)) +} + +// VPERMI2PS_BCST_Z: Full Permute of Single-Precision Floating-Point Values From Two Tables Overwriting the Index (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMI2PS.BCST.Z m32 xmm k xmm +// VPERMI2PS.BCST.Z m32 ymm k ymm +// VPERMI2PS.BCST.Z m32 zmm k zmm +// Construct and append a VPERMI2PS.BCST.Z instruction to the active function. +// Operates on the global context. +func VPERMI2PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPERMI2PS_BCST_Z(m, xyz, k, xyz1) } + +// VPERMI2PS_Z: Full Permute of Single-Precision Floating-Point Values From Two Tables Overwriting the Index (Zeroing Masking). +// +// Forms: +// +// VPERMI2PS.Z m128 xmm k xmm +// VPERMI2PS.Z m256 ymm k ymm +// VPERMI2PS.Z xmm xmm k xmm +// VPERMI2PS.Z ymm ymm k ymm +// VPERMI2PS.Z m512 zmm k zmm +// VPERMI2PS.Z zmm zmm k zmm +// Construct and append a VPERMI2PS.Z instruction to the active function. +func (c *Context) VPERMI2PS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPERMI2PS_Z(mxyz, xyz, k, xyz1)) +} + +// VPERMI2PS_Z: Full Permute of Single-Precision Floating-Point Values From Two Tables Overwriting the Index (Zeroing Masking). +// +// Forms: +// +// VPERMI2PS.Z m128 xmm k xmm +// VPERMI2PS.Z m256 ymm k ymm +// VPERMI2PS.Z xmm xmm k xmm +// VPERMI2PS.Z ymm ymm k ymm +// VPERMI2PS.Z m512 zmm k zmm +// VPERMI2PS.Z zmm zmm k zmm +// Construct and append a VPERMI2PS.Z instruction to the active function. +// Operates on the global context. +func VPERMI2PS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPERMI2PS_Z(mxyz, xyz, k, xyz1) } + +// VPERMI2Q: Full Permute of Quadwords From Two Tables Overwriting the Index. +// +// Forms: +// +// VPERMI2Q m128 xmm k xmm +// VPERMI2Q m128 xmm xmm +// VPERMI2Q m256 ymm k ymm +// VPERMI2Q m256 ymm ymm +// VPERMI2Q xmm xmm k xmm +// VPERMI2Q xmm xmm xmm +// VPERMI2Q ymm ymm k ymm +// VPERMI2Q ymm ymm ymm +// VPERMI2Q m512 zmm k zmm +// VPERMI2Q m512 zmm zmm +// VPERMI2Q zmm zmm k zmm +// VPERMI2Q zmm zmm zmm +// Construct and append a VPERMI2Q instruction to the active function. +func (c *Context) VPERMI2Q(ops ...operand.Op) { + c.addinstruction(x86.VPERMI2Q(ops...)) +} + +// VPERMI2Q: Full Permute of Quadwords From Two Tables Overwriting the Index. +// +// Forms: +// +// VPERMI2Q m128 xmm k xmm +// VPERMI2Q m128 xmm xmm +// VPERMI2Q m256 ymm k ymm +// VPERMI2Q m256 ymm ymm +// VPERMI2Q xmm xmm k xmm +// VPERMI2Q xmm xmm xmm +// VPERMI2Q ymm ymm k ymm +// VPERMI2Q ymm ymm ymm +// VPERMI2Q m512 zmm k zmm +// VPERMI2Q m512 zmm zmm +// VPERMI2Q zmm zmm k zmm +// VPERMI2Q zmm zmm zmm +// Construct and append a VPERMI2Q instruction to the active function. +// Operates on the global context. +func VPERMI2Q(ops ...operand.Op) { ctx.VPERMI2Q(ops...) } + +// VPERMI2Q_BCST: Full Permute of Quadwords From Two Tables Overwriting the Index (Broadcast). +// +// Forms: +// +// VPERMI2Q.BCST m64 xmm k xmm +// VPERMI2Q.BCST m64 xmm xmm +// VPERMI2Q.BCST m64 ymm k ymm +// VPERMI2Q.BCST m64 ymm ymm +// VPERMI2Q.BCST m64 zmm k zmm +// VPERMI2Q.BCST m64 zmm zmm +// Construct and append a VPERMI2Q.BCST instruction to the active function. +func (c *Context) VPERMI2Q_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPERMI2Q_BCST(ops...)) +} + +// VPERMI2Q_BCST: Full Permute of Quadwords From Two Tables Overwriting the Index (Broadcast). +// +// Forms: +// +// VPERMI2Q.BCST m64 xmm k xmm +// VPERMI2Q.BCST m64 xmm xmm +// VPERMI2Q.BCST m64 ymm k ymm +// VPERMI2Q.BCST m64 ymm ymm +// VPERMI2Q.BCST m64 zmm k zmm +// VPERMI2Q.BCST m64 zmm zmm +// Construct and append a VPERMI2Q.BCST instruction to the active function. +// Operates on the global context. +func VPERMI2Q_BCST(ops ...operand.Op) { ctx.VPERMI2Q_BCST(ops...) } + +// VPERMI2Q_BCST_Z: Full Permute of Quadwords From Two Tables Overwriting the Index (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMI2Q.BCST.Z m64 xmm k xmm +// VPERMI2Q.BCST.Z m64 ymm k ymm +// VPERMI2Q.BCST.Z m64 zmm k zmm +// Construct and append a VPERMI2Q.BCST.Z instruction to the active function. +func (c *Context) VPERMI2Q_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPERMI2Q_BCST_Z(m, xyz, k, xyz1)) +} + +// VPERMI2Q_BCST_Z: Full Permute of Quadwords From Two Tables Overwriting the Index (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMI2Q.BCST.Z m64 xmm k xmm +// VPERMI2Q.BCST.Z m64 ymm k ymm +// VPERMI2Q.BCST.Z m64 zmm k zmm +// Construct and append a VPERMI2Q.BCST.Z instruction to the active function. +// Operates on the global context. +func VPERMI2Q_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPERMI2Q_BCST_Z(m, xyz, k, xyz1) } + +// VPERMI2Q_Z: Full Permute of Quadwords From Two Tables Overwriting the Index (Zeroing Masking). +// +// Forms: +// +// VPERMI2Q.Z m128 xmm k xmm +// VPERMI2Q.Z m256 ymm k ymm +// VPERMI2Q.Z xmm xmm k xmm +// VPERMI2Q.Z ymm ymm k ymm +// VPERMI2Q.Z m512 zmm k zmm +// VPERMI2Q.Z zmm zmm k zmm +// Construct and append a VPERMI2Q.Z instruction to the active function. +func (c *Context) VPERMI2Q_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPERMI2Q_Z(mxyz, xyz, k, xyz1)) +} + +// VPERMI2Q_Z: Full Permute of Quadwords From Two Tables Overwriting the Index (Zeroing Masking). +// +// Forms: +// +// VPERMI2Q.Z m128 xmm k xmm +// VPERMI2Q.Z m256 ymm k ymm +// VPERMI2Q.Z xmm xmm k xmm +// VPERMI2Q.Z ymm ymm k ymm +// VPERMI2Q.Z m512 zmm k zmm +// VPERMI2Q.Z zmm zmm k zmm +// Construct and append a VPERMI2Q.Z instruction to the active function. +// Operates on the global context. +func VPERMI2Q_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPERMI2Q_Z(mxyz, xyz, k, xyz1) } + +// VPERMI2W: Full Permute of Words From Two Tables Overwriting the Index. +// +// Forms: +// +// VPERMI2W m128 xmm k xmm +// VPERMI2W m128 xmm xmm +// VPERMI2W m256 ymm k ymm +// VPERMI2W m256 ymm ymm +// VPERMI2W xmm xmm k xmm +// VPERMI2W xmm xmm xmm +// VPERMI2W ymm ymm k ymm +// VPERMI2W ymm ymm ymm +// VPERMI2W m512 zmm k zmm +// VPERMI2W m512 zmm zmm +// VPERMI2W zmm zmm k zmm +// VPERMI2W zmm zmm zmm +// Construct and append a VPERMI2W instruction to the active function. +func (c *Context) VPERMI2W(ops ...operand.Op) { + c.addinstruction(x86.VPERMI2W(ops...)) +} + +// VPERMI2W: Full Permute of Words From Two Tables Overwriting the Index. +// +// Forms: +// +// VPERMI2W m128 xmm k xmm +// VPERMI2W m128 xmm xmm +// VPERMI2W m256 ymm k ymm +// VPERMI2W m256 ymm ymm +// VPERMI2W xmm xmm k xmm +// VPERMI2W xmm xmm xmm +// VPERMI2W ymm ymm k ymm +// VPERMI2W ymm ymm ymm +// VPERMI2W m512 zmm k zmm +// VPERMI2W m512 zmm zmm +// VPERMI2W zmm zmm k zmm +// VPERMI2W zmm zmm zmm +// Construct and append a VPERMI2W instruction to the active function. +// Operates on the global context. +func VPERMI2W(ops ...operand.Op) { ctx.VPERMI2W(ops...) } + +// VPERMI2W_Z: Full Permute of Words From Two Tables Overwriting the Index (Zeroing Masking). +// +// Forms: +// +// VPERMI2W.Z m128 xmm k xmm +// VPERMI2W.Z m256 ymm k ymm +// VPERMI2W.Z xmm xmm k xmm +// VPERMI2W.Z ymm ymm k ymm +// VPERMI2W.Z m512 zmm k zmm +// VPERMI2W.Z zmm zmm k zmm +// Construct and append a VPERMI2W.Z instruction to the active function. +func (c *Context) VPERMI2W_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPERMI2W_Z(mxyz, xyz, k, xyz1)) +} + +// VPERMI2W_Z: Full Permute of Words From Two Tables Overwriting the Index (Zeroing Masking). +// +// Forms: +// +// VPERMI2W.Z m128 xmm k xmm +// VPERMI2W.Z m256 ymm k ymm +// VPERMI2W.Z xmm xmm k xmm +// VPERMI2W.Z ymm ymm k ymm +// VPERMI2W.Z m512 zmm k zmm +// VPERMI2W.Z zmm zmm k zmm +// Construct and append a VPERMI2W.Z instruction to the active function. +// Operates on the global context. +func VPERMI2W_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPERMI2W_Z(mxyz, xyz, k, xyz1) } + +// VPERMILPD: Permute Double-Precision Floating-Point Values. +// +// Forms: +// +// VPERMILPD imm8 m128 xmm +// VPERMILPD imm8 m256 ymm +// VPERMILPD imm8 xmm xmm +// VPERMILPD imm8 ymm ymm +// VPERMILPD m128 xmm xmm +// VPERMILPD m256 ymm ymm +// VPERMILPD xmm xmm xmm +// VPERMILPD ymm ymm ymm +// VPERMILPD imm8 m128 k xmm +// VPERMILPD imm8 m256 k ymm +// VPERMILPD imm8 xmm k xmm +// VPERMILPD imm8 ymm k ymm +// VPERMILPD m128 xmm k xmm +// VPERMILPD m256 ymm k ymm +// VPERMILPD xmm xmm k xmm +// VPERMILPD ymm ymm k ymm +// VPERMILPD imm8 m512 k zmm +// VPERMILPD imm8 m512 zmm +// VPERMILPD imm8 zmm k zmm +// VPERMILPD imm8 zmm zmm +// VPERMILPD m512 zmm k zmm +// VPERMILPD m512 zmm zmm +// VPERMILPD zmm zmm k zmm +// VPERMILPD zmm zmm zmm +// Construct and append a VPERMILPD instruction to the active function. +func (c *Context) VPERMILPD(ops ...operand.Op) { + c.addinstruction(x86.VPERMILPD(ops...)) +} + +// VPERMILPD: Permute Double-Precision Floating-Point Values. +// +// Forms: +// +// VPERMILPD imm8 m128 xmm +// VPERMILPD imm8 m256 ymm +// VPERMILPD imm8 xmm xmm +// VPERMILPD imm8 ymm ymm +// VPERMILPD m128 xmm xmm +// VPERMILPD m256 ymm ymm +// VPERMILPD xmm xmm xmm +// VPERMILPD ymm ymm ymm +// VPERMILPD imm8 m128 k xmm +// VPERMILPD imm8 m256 k ymm +// VPERMILPD imm8 xmm k xmm +// VPERMILPD imm8 ymm k ymm +// VPERMILPD m128 xmm k xmm +// VPERMILPD m256 ymm k ymm +// VPERMILPD xmm xmm k xmm +// VPERMILPD ymm ymm k ymm +// VPERMILPD imm8 m512 k zmm +// VPERMILPD imm8 m512 zmm +// VPERMILPD imm8 zmm k zmm +// VPERMILPD imm8 zmm zmm +// VPERMILPD m512 zmm k zmm +// VPERMILPD m512 zmm zmm +// VPERMILPD zmm zmm k zmm +// VPERMILPD zmm zmm zmm +// Construct and append a VPERMILPD instruction to the active function. +// Operates on the global context. +func VPERMILPD(ops ...operand.Op) { ctx.VPERMILPD(ops...) } + +// VPERMILPD_BCST: Permute Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VPERMILPD.BCST imm8 m64 k xmm +// VPERMILPD.BCST imm8 m64 k ymm +// VPERMILPD.BCST imm8 m64 xmm +// VPERMILPD.BCST imm8 m64 ymm +// VPERMILPD.BCST m64 xmm k xmm +// VPERMILPD.BCST m64 xmm xmm +// VPERMILPD.BCST m64 ymm k ymm +// VPERMILPD.BCST m64 ymm ymm +// VPERMILPD.BCST imm8 m64 k zmm +// VPERMILPD.BCST imm8 m64 zmm +// VPERMILPD.BCST m64 zmm k zmm +// VPERMILPD.BCST m64 zmm zmm +// Construct and append a VPERMILPD.BCST instruction to the active function. +func (c *Context) VPERMILPD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPERMILPD_BCST(ops...)) +} + +// VPERMILPD_BCST: Permute Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VPERMILPD.BCST imm8 m64 k xmm +// VPERMILPD.BCST imm8 m64 k ymm +// VPERMILPD.BCST imm8 m64 xmm +// VPERMILPD.BCST imm8 m64 ymm +// VPERMILPD.BCST m64 xmm k xmm +// VPERMILPD.BCST m64 xmm xmm +// VPERMILPD.BCST m64 ymm k ymm +// VPERMILPD.BCST m64 ymm ymm +// VPERMILPD.BCST imm8 m64 k zmm +// VPERMILPD.BCST imm8 m64 zmm +// VPERMILPD.BCST m64 zmm k zmm +// VPERMILPD.BCST m64 zmm zmm +// Construct and append a VPERMILPD.BCST instruction to the active function. +// Operates on the global context. +func VPERMILPD_BCST(ops ...operand.Op) { ctx.VPERMILPD_BCST(ops...) } + +// VPERMILPD_BCST_Z: Permute Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMILPD.BCST.Z imm8 m64 k xmm +// VPERMILPD.BCST.Z imm8 m64 k ymm +// VPERMILPD.BCST.Z m64 xmm k xmm +// VPERMILPD.BCST.Z m64 ymm k ymm +// VPERMILPD.BCST.Z imm8 m64 k zmm +// VPERMILPD.BCST.Z m64 zmm k zmm +// Construct and append a VPERMILPD.BCST.Z instruction to the active function. +func (c *Context) VPERMILPD_BCST_Z(im, mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPERMILPD_BCST_Z(im, mxyz, k, xyz)) +} + +// VPERMILPD_BCST_Z: Permute Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMILPD.BCST.Z imm8 m64 k xmm +// VPERMILPD.BCST.Z imm8 m64 k ymm +// VPERMILPD.BCST.Z m64 xmm k xmm +// VPERMILPD.BCST.Z m64 ymm k ymm +// VPERMILPD.BCST.Z imm8 m64 k zmm +// VPERMILPD.BCST.Z m64 zmm k zmm +// Construct and append a VPERMILPD.BCST.Z instruction to the active function. +// Operates on the global context. +func VPERMILPD_BCST_Z(im, mxyz, k, xyz operand.Op) { ctx.VPERMILPD_BCST_Z(im, mxyz, k, xyz) } + +// VPERMILPD_Z: Permute Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VPERMILPD.Z imm8 m128 k xmm +// VPERMILPD.Z imm8 m256 k ymm +// VPERMILPD.Z imm8 xmm k xmm +// VPERMILPD.Z imm8 ymm k ymm +// VPERMILPD.Z m128 xmm k xmm +// VPERMILPD.Z m256 ymm k ymm +// VPERMILPD.Z xmm xmm k xmm +// VPERMILPD.Z ymm ymm k ymm +// VPERMILPD.Z imm8 m512 k zmm +// VPERMILPD.Z imm8 zmm k zmm +// VPERMILPD.Z m512 zmm k zmm +// VPERMILPD.Z zmm zmm k zmm +// Construct and append a VPERMILPD.Z instruction to the active function. +func (c *Context) VPERMILPD_Z(imxyz, mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPERMILPD_Z(imxyz, mxyz, k, xyz)) +} + +// VPERMILPD_Z: Permute Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VPERMILPD.Z imm8 m128 k xmm +// VPERMILPD.Z imm8 m256 k ymm +// VPERMILPD.Z imm8 xmm k xmm +// VPERMILPD.Z imm8 ymm k ymm +// VPERMILPD.Z m128 xmm k xmm +// VPERMILPD.Z m256 ymm k ymm +// VPERMILPD.Z xmm xmm k xmm +// VPERMILPD.Z ymm ymm k ymm +// VPERMILPD.Z imm8 m512 k zmm +// VPERMILPD.Z imm8 zmm k zmm +// VPERMILPD.Z m512 zmm k zmm +// VPERMILPD.Z zmm zmm k zmm +// Construct and append a VPERMILPD.Z instruction to the active function. +// Operates on the global context. +func VPERMILPD_Z(imxyz, mxyz, k, xyz operand.Op) { ctx.VPERMILPD_Z(imxyz, mxyz, k, xyz) } + +// VPERMILPS: Permute Single-Precision Floating-Point Values. +// +// Forms: +// +// VPERMILPS imm8 m128 xmm +// VPERMILPS imm8 m256 ymm +// VPERMILPS imm8 xmm xmm +// VPERMILPS imm8 ymm ymm +// VPERMILPS m128 xmm xmm +// VPERMILPS m256 ymm ymm +// VPERMILPS xmm xmm xmm +// VPERMILPS ymm ymm ymm +// VPERMILPS imm8 m128 k xmm +// VPERMILPS imm8 m256 k ymm +// VPERMILPS imm8 xmm k xmm +// VPERMILPS imm8 ymm k ymm +// VPERMILPS m128 xmm k xmm +// VPERMILPS m256 ymm k ymm +// VPERMILPS xmm xmm k xmm +// VPERMILPS ymm ymm k ymm +// VPERMILPS imm8 m512 k zmm +// VPERMILPS imm8 m512 zmm +// VPERMILPS imm8 zmm k zmm +// VPERMILPS imm8 zmm zmm +// VPERMILPS m512 zmm k zmm +// VPERMILPS m512 zmm zmm +// VPERMILPS zmm zmm k zmm +// VPERMILPS zmm zmm zmm +// Construct and append a VPERMILPS instruction to the active function. +func (c *Context) VPERMILPS(ops ...operand.Op) { + c.addinstruction(x86.VPERMILPS(ops...)) +} + +// VPERMILPS: Permute Single-Precision Floating-Point Values. +// +// Forms: +// +// VPERMILPS imm8 m128 xmm +// VPERMILPS imm8 m256 ymm +// VPERMILPS imm8 xmm xmm +// VPERMILPS imm8 ymm ymm +// VPERMILPS m128 xmm xmm +// VPERMILPS m256 ymm ymm +// VPERMILPS xmm xmm xmm +// VPERMILPS ymm ymm ymm +// VPERMILPS imm8 m128 k xmm +// VPERMILPS imm8 m256 k ymm +// VPERMILPS imm8 xmm k xmm +// VPERMILPS imm8 ymm k ymm +// VPERMILPS m128 xmm k xmm +// VPERMILPS m256 ymm k ymm +// VPERMILPS xmm xmm k xmm +// VPERMILPS ymm ymm k ymm +// VPERMILPS imm8 m512 k zmm +// VPERMILPS imm8 m512 zmm +// VPERMILPS imm8 zmm k zmm +// VPERMILPS imm8 zmm zmm +// VPERMILPS m512 zmm k zmm +// VPERMILPS m512 zmm zmm +// VPERMILPS zmm zmm k zmm +// VPERMILPS zmm zmm zmm +// Construct and append a VPERMILPS instruction to the active function. +// Operates on the global context. +func VPERMILPS(ops ...operand.Op) { ctx.VPERMILPS(ops...) } + +// VPERMILPS_BCST: Permute Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VPERMILPS.BCST imm8 m32 k xmm +// VPERMILPS.BCST imm8 m32 k ymm +// VPERMILPS.BCST imm8 m32 xmm +// VPERMILPS.BCST imm8 m32 ymm +// VPERMILPS.BCST m32 xmm k xmm +// VPERMILPS.BCST m32 xmm xmm +// VPERMILPS.BCST m32 ymm k ymm +// VPERMILPS.BCST m32 ymm ymm +// VPERMILPS.BCST imm8 m32 k zmm +// VPERMILPS.BCST imm8 m32 zmm +// VPERMILPS.BCST m32 zmm k zmm +// VPERMILPS.BCST m32 zmm zmm +// Construct and append a VPERMILPS.BCST instruction to the active function. +func (c *Context) VPERMILPS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPERMILPS_BCST(ops...)) +} + +// VPERMILPS_BCST: Permute Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VPERMILPS.BCST imm8 m32 k xmm +// VPERMILPS.BCST imm8 m32 k ymm +// VPERMILPS.BCST imm8 m32 xmm +// VPERMILPS.BCST imm8 m32 ymm +// VPERMILPS.BCST m32 xmm k xmm +// VPERMILPS.BCST m32 xmm xmm +// VPERMILPS.BCST m32 ymm k ymm +// VPERMILPS.BCST m32 ymm ymm +// VPERMILPS.BCST imm8 m32 k zmm +// VPERMILPS.BCST imm8 m32 zmm +// VPERMILPS.BCST m32 zmm k zmm +// VPERMILPS.BCST m32 zmm zmm +// Construct and append a VPERMILPS.BCST instruction to the active function. +// Operates on the global context. +func VPERMILPS_BCST(ops ...operand.Op) { ctx.VPERMILPS_BCST(ops...) } + +// VPERMILPS_BCST_Z: Permute Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMILPS.BCST.Z imm8 m32 k xmm +// VPERMILPS.BCST.Z imm8 m32 k ymm +// VPERMILPS.BCST.Z m32 xmm k xmm +// VPERMILPS.BCST.Z m32 ymm k ymm +// VPERMILPS.BCST.Z imm8 m32 k zmm +// VPERMILPS.BCST.Z m32 zmm k zmm +// Construct and append a VPERMILPS.BCST.Z instruction to the active function. +func (c *Context) VPERMILPS_BCST_Z(im, mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPERMILPS_BCST_Z(im, mxyz, k, xyz)) +} + +// VPERMILPS_BCST_Z: Permute Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMILPS.BCST.Z imm8 m32 k xmm +// VPERMILPS.BCST.Z imm8 m32 k ymm +// VPERMILPS.BCST.Z m32 xmm k xmm +// VPERMILPS.BCST.Z m32 ymm k ymm +// VPERMILPS.BCST.Z imm8 m32 k zmm +// VPERMILPS.BCST.Z m32 zmm k zmm +// Construct and append a VPERMILPS.BCST.Z instruction to the active function. +// Operates on the global context. +func VPERMILPS_BCST_Z(im, mxyz, k, xyz operand.Op) { ctx.VPERMILPS_BCST_Z(im, mxyz, k, xyz) } + +// VPERMILPS_Z: Permute Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VPERMILPS.Z imm8 m128 k xmm +// VPERMILPS.Z imm8 m256 k ymm +// VPERMILPS.Z imm8 xmm k xmm +// VPERMILPS.Z imm8 ymm k ymm +// VPERMILPS.Z m128 xmm k xmm +// VPERMILPS.Z m256 ymm k ymm +// VPERMILPS.Z xmm xmm k xmm +// VPERMILPS.Z ymm ymm k ymm +// VPERMILPS.Z imm8 m512 k zmm +// VPERMILPS.Z imm8 zmm k zmm +// VPERMILPS.Z m512 zmm k zmm +// VPERMILPS.Z zmm zmm k zmm +// Construct and append a VPERMILPS.Z instruction to the active function. +func (c *Context) VPERMILPS_Z(imxyz, mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPERMILPS_Z(imxyz, mxyz, k, xyz)) +} + +// VPERMILPS_Z: Permute Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VPERMILPS.Z imm8 m128 k xmm +// VPERMILPS.Z imm8 m256 k ymm +// VPERMILPS.Z imm8 xmm k xmm +// VPERMILPS.Z imm8 ymm k ymm +// VPERMILPS.Z m128 xmm k xmm +// VPERMILPS.Z m256 ymm k ymm +// VPERMILPS.Z xmm xmm k xmm +// VPERMILPS.Z ymm ymm k ymm +// VPERMILPS.Z imm8 m512 k zmm +// VPERMILPS.Z imm8 zmm k zmm +// VPERMILPS.Z m512 zmm k zmm +// VPERMILPS.Z zmm zmm k zmm +// Construct and append a VPERMILPS.Z instruction to the active function. +// Operates on the global context. +func VPERMILPS_Z(imxyz, mxyz, k, xyz operand.Op) { ctx.VPERMILPS_Z(imxyz, mxyz, k, xyz) } + +// VPERMPD: Permute Double-Precision Floating-Point Elements. +// +// Forms: +// +// VPERMPD imm8 m256 ymm +// VPERMPD imm8 ymm ymm +// VPERMPD imm8 m256 k ymm +// VPERMPD imm8 ymm k ymm +// VPERMPD m256 ymm k ymm +// VPERMPD m256 ymm ymm +// VPERMPD ymm ymm k ymm +// VPERMPD ymm ymm ymm +// VPERMPD imm8 m512 k zmm +// VPERMPD imm8 m512 zmm +// VPERMPD imm8 zmm k zmm +// VPERMPD imm8 zmm zmm +// VPERMPD m512 zmm k zmm +// VPERMPD m512 zmm zmm +// VPERMPD zmm zmm k zmm +// VPERMPD zmm zmm zmm +// Construct and append a VPERMPD instruction to the active function. +func (c *Context) VPERMPD(ops ...operand.Op) { + c.addinstruction(x86.VPERMPD(ops...)) +} + +// VPERMPD: Permute Double-Precision Floating-Point Elements. +// +// Forms: +// +// VPERMPD imm8 m256 ymm +// VPERMPD imm8 ymm ymm +// VPERMPD imm8 m256 k ymm +// VPERMPD imm8 ymm k ymm +// VPERMPD m256 ymm k ymm +// VPERMPD m256 ymm ymm +// VPERMPD ymm ymm k ymm +// VPERMPD ymm ymm ymm +// VPERMPD imm8 m512 k zmm +// VPERMPD imm8 m512 zmm +// VPERMPD imm8 zmm k zmm +// VPERMPD imm8 zmm zmm +// VPERMPD m512 zmm k zmm +// VPERMPD m512 zmm zmm +// VPERMPD zmm zmm k zmm +// VPERMPD zmm zmm zmm +// Construct and append a VPERMPD instruction to the active function. +// Operates on the global context. +func VPERMPD(ops ...operand.Op) { ctx.VPERMPD(ops...) } + +// VPERMPD_BCST: Permute Double-Precision Floating-Point Elements (Broadcast). +// +// Forms: +// +// VPERMPD.BCST imm8 m64 k ymm +// VPERMPD.BCST imm8 m64 ymm +// VPERMPD.BCST m64 ymm k ymm +// VPERMPD.BCST m64 ymm ymm +// VPERMPD.BCST imm8 m64 k zmm +// VPERMPD.BCST imm8 m64 zmm +// VPERMPD.BCST m64 zmm k zmm +// VPERMPD.BCST m64 zmm zmm +// Construct and append a VPERMPD.BCST instruction to the active function. +func (c *Context) VPERMPD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPERMPD_BCST(ops...)) +} + +// VPERMPD_BCST: Permute Double-Precision Floating-Point Elements (Broadcast). +// +// Forms: +// +// VPERMPD.BCST imm8 m64 k ymm +// VPERMPD.BCST imm8 m64 ymm +// VPERMPD.BCST m64 ymm k ymm +// VPERMPD.BCST m64 ymm ymm +// VPERMPD.BCST imm8 m64 k zmm +// VPERMPD.BCST imm8 m64 zmm +// VPERMPD.BCST m64 zmm k zmm +// VPERMPD.BCST m64 zmm zmm +// Construct and append a VPERMPD.BCST instruction to the active function. +// Operates on the global context. +func VPERMPD_BCST(ops ...operand.Op) { ctx.VPERMPD_BCST(ops...) } + +// VPERMPD_BCST_Z: Permute Double-Precision Floating-Point Elements (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMPD.BCST.Z imm8 m64 k ymm +// VPERMPD.BCST.Z m64 ymm k ymm +// VPERMPD.BCST.Z imm8 m64 k zmm +// VPERMPD.BCST.Z m64 zmm k zmm +// Construct and append a VPERMPD.BCST.Z instruction to the active function. +func (c *Context) VPERMPD_BCST_Z(im, myz, k, yz operand.Op) { + c.addinstruction(x86.VPERMPD_BCST_Z(im, myz, k, yz)) +} + +// VPERMPD_BCST_Z: Permute Double-Precision Floating-Point Elements (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMPD.BCST.Z imm8 m64 k ymm +// VPERMPD.BCST.Z m64 ymm k ymm +// VPERMPD.BCST.Z imm8 m64 k zmm +// VPERMPD.BCST.Z m64 zmm k zmm +// Construct and append a VPERMPD.BCST.Z instruction to the active function. +// Operates on the global context. +func VPERMPD_BCST_Z(im, myz, k, yz operand.Op) { ctx.VPERMPD_BCST_Z(im, myz, k, yz) } + +// VPERMPD_Z: Permute Double-Precision Floating-Point Elements (Zeroing Masking). +// +// Forms: +// +// VPERMPD.Z imm8 m256 k ymm +// VPERMPD.Z imm8 ymm k ymm +// VPERMPD.Z m256 ymm k ymm +// VPERMPD.Z ymm ymm k ymm +// VPERMPD.Z imm8 m512 k zmm +// VPERMPD.Z imm8 zmm k zmm +// VPERMPD.Z m512 zmm k zmm +// VPERMPD.Z zmm zmm k zmm +// Construct and append a VPERMPD.Z instruction to the active function. +func (c *Context) VPERMPD_Z(imyz, myz, k, yz operand.Op) { + c.addinstruction(x86.VPERMPD_Z(imyz, myz, k, yz)) +} + +// VPERMPD_Z: Permute Double-Precision Floating-Point Elements (Zeroing Masking). +// +// Forms: +// +// VPERMPD.Z imm8 m256 k ymm +// VPERMPD.Z imm8 ymm k ymm +// VPERMPD.Z m256 ymm k ymm +// VPERMPD.Z ymm ymm k ymm +// VPERMPD.Z imm8 m512 k zmm +// VPERMPD.Z imm8 zmm k zmm +// VPERMPD.Z m512 zmm k zmm +// VPERMPD.Z zmm zmm k zmm +// Construct and append a VPERMPD.Z instruction to the active function. +// Operates on the global context. +func VPERMPD_Z(imyz, myz, k, yz operand.Op) { ctx.VPERMPD_Z(imyz, myz, k, yz) } + +// VPERMPS: Permute Single-Precision Floating-Point Elements. +// +// Forms: +// +// VPERMPS m256 ymm ymm +// VPERMPS ymm ymm ymm +// VPERMPS m256 ymm k ymm +// VPERMPS ymm ymm k ymm +// VPERMPS m512 zmm k zmm +// VPERMPS m512 zmm zmm +// VPERMPS zmm zmm k zmm +// VPERMPS zmm zmm zmm +// Construct and append a VPERMPS instruction to the active function. +func (c *Context) VPERMPS(ops ...operand.Op) { + c.addinstruction(x86.VPERMPS(ops...)) +} + +// VPERMPS: Permute Single-Precision Floating-Point Elements. +// +// Forms: +// +// VPERMPS m256 ymm ymm +// VPERMPS ymm ymm ymm +// VPERMPS m256 ymm k ymm +// VPERMPS ymm ymm k ymm +// VPERMPS m512 zmm k zmm +// VPERMPS m512 zmm zmm +// VPERMPS zmm zmm k zmm +// VPERMPS zmm zmm zmm +// Construct and append a VPERMPS instruction to the active function. +// Operates on the global context. +func VPERMPS(ops ...operand.Op) { ctx.VPERMPS(ops...) } + +// VPERMPS_BCST: Permute Single-Precision Floating-Point Elements (Broadcast). +// +// Forms: +// +// VPERMPS.BCST m32 ymm k ymm +// VPERMPS.BCST m32 ymm ymm +// VPERMPS.BCST m32 zmm k zmm +// VPERMPS.BCST m32 zmm zmm +// Construct and append a VPERMPS.BCST instruction to the active function. +func (c *Context) VPERMPS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPERMPS_BCST(ops...)) +} + +// VPERMPS_BCST: Permute Single-Precision Floating-Point Elements (Broadcast). +// +// Forms: +// +// VPERMPS.BCST m32 ymm k ymm +// VPERMPS.BCST m32 ymm ymm +// VPERMPS.BCST m32 zmm k zmm +// VPERMPS.BCST m32 zmm zmm +// Construct and append a VPERMPS.BCST instruction to the active function. +// Operates on the global context. +func VPERMPS_BCST(ops ...operand.Op) { ctx.VPERMPS_BCST(ops...) } + +// VPERMPS_BCST_Z: Permute Single-Precision Floating-Point Elements (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMPS.BCST.Z m32 ymm k ymm +// VPERMPS.BCST.Z m32 zmm k zmm +// Construct and append a VPERMPS.BCST.Z instruction to the active function. +func (c *Context) VPERMPS_BCST_Z(m, yz, k, yz1 operand.Op) { + c.addinstruction(x86.VPERMPS_BCST_Z(m, yz, k, yz1)) +} + +// VPERMPS_BCST_Z: Permute Single-Precision Floating-Point Elements (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMPS.BCST.Z m32 ymm k ymm +// VPERMPS.BCST.Z m32 zmm k zmm +// Construct and append a VPERMPS.BCST.Z instruction to the active function. +// Operates on the global context. +func VPERMPS_BCST_Z(m, yz, k, yz1 operand.Op) { ctx.VPERMPS_BCST_Z(m, yz, k, yz1) } + +// VPERMPS_Z: Permute Single-Precision Floating-Point Elements (Zeroing Masking). +// +// Forms: +// +// VPERMPS.Z m256 ymm k ymm +// VPERMPS.Z ymm ymm k ymm +// VPERMPS.Z m512 zmm k zmm +// VPERMPS.Z zmm zmm k zmm +// Construct and append a VPERMPS.Z instruction to the active function. +func (c *Context) VPERMPS_Z(myz, yz, k, yz1 operand.Op) { + c.addinstruction(x86.VPERMPS_Z(myz, yz, k, yz1)) +} + +// VPERMPS_Z: Permute Single-Precision Floating-Point Elements (Zeroing Masking). +// +// Forms: +// +// VPERMPS.Z m256 ymm k ymm +// VPERMPS.Z ymm ymm k ymm +// VPERMPS.Z m512 zmm k zmm +// VPERMPS.Z zmm zmm k zmm +// Construct and append a VPERMPS.Z instruction to the active function. +// Operates on the global context. +func VPERMPS_Z(myz, yz, k, yz1 operand.Op) { ctx.VPERMPS_Z(myz, yz, k, yz1) } + +// VPERMQ: Permute Quadword Integers. +// +// Forms: +// +// VPERMQ imm8 m256 ymm +// VPERMQ imm8 ymm ymm +// VPERMQ imm8 m256 k ymm +// VPERMQ imm8 ymm k ymm +// VPERMQ m256 ymm k ymm +// VPERMQ m256 ymm ymm +// VPERMQ ymm ymm k ymm +// VPERMQ ymm ymm ymm +// VPERMQ imm8 m512 k zmm +// VPERMQ imm8 m512 zmm +// VPERMQ imm8 zmm k zmm +// VPERMQ imm8 zmm zmm +// VPERMQ m512 zmm k zmm +// VPERMQ m512 zmm zmm +// VPERMQ zmm zmm k zmm +// VPERMQ zmm zmm zmm +// Construct and append a VPERMQ instruction to the active function. +func (c *Context) VPERMQ(ops ...operand.Op) { + c.addinstruction(x86.VPERMQ(ops...)) +} + +// VPERMQ: Permute Quadword Integers. +// +// Forms: +// +// VPERMQ imm8 m256 ymm +// VPERMQ imm8 ymm ymm +// VPERMQ imm8 m256 k ymm +// VPERMQ imm8 ymm k ymm +// VPERMQ m256 ymm k ymm +// VPERMQ m256 ymm ymm +// VPERMQ ymm ymm k ymm +// VPERMQ ymm ymm ymm +// VPERMQ imm8 m512 k zmm +// VPERMQ imm8 m512 zmm +// VPERMQ imm8 zmm k zmm +// VPERMQ imm8 zmm zmm +// VPERMQ m512 zmm k zmm +// VPERMQ m512 zmm zmm +// VPERMQ zmm zmm k zmm +// VPERMQ zmm zmm zmm +// Construct and append a VPERMQ instruction to the active function. +// Operates on the global context. +func VPERMQ(ops ...operand.Op) { ctx.VPERMQ(ops...) } + +// VPERMQ_BCST: Permute Quadword Integers (Broadcast). +// +// Forms: +// +// VPERMQ.BCST imm8 m64 k ymm +// VPERMQ.BCST imm8 m64 ymm +// VPERMQ.BCST m64 ymm k ymm +// VPERMQ.BCST m64 ymm ymm +// VPERMQ.BCST imm8 m64 k zmm +// VPERMQ.BCST imm8 m64 zmm +// VPERMQ.BCST m64 zmm k zmm +// VPERMQ.BCST m64 zmm zmm +// Construct and append a VPERMQ.BCST instruction to the active function. +func (c *Context) VPERMQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPERMQ_BCST(ops...)) +} + +// VPERMQ_BCST: Permute Quadword Integers (Broadcast). +// +// Forms: +// +// VPERMQ.BCST imm8 m64 k ymm +// VPERMQ.BCST imm8 m64 ymm +// VPERMQ.BCST m64 ymm k ymm +// VPERMQ.BCST m64 ymm ymm +// VPERMQ.BCST imm8 m64 k zmm +// VPERMQ.BCST imm8 m64 zmm +// VPERMQ.BCST m64 zmm k zmm +// VPERMQ.BCST m64 zmm zmm +// Construct and append a VPERMQ.BCST instruction to the active function. +// Operates on the global context. +func VPERMQ_BCST(ops ...operand.Op) { ctx.VPERMQ_BCST(ops...) } + +// VPERMQ_BCST_Z: Permute Quadword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMQ.BCST.Z imm8 m64 k ymm +// VPERMQ.BCST.Z m64 ymm k ymm +// VPERMQ.BCST.Z imm8 m64 k zmm +// VPERMQ.BCST.Z m64 zmm k zmm +// Construct and append a VPERMQ.BCST.Z instruction to the active function. +func (c *Context) VPERMQ_BCST_Z(im, myz, k, yz operand.Op) { + c.addinstruction(x86.VPERMQ_BCST_Z(im, myz, k, yz)) +} + +// VPERMQ_BCST_Z: Permute Quadword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMQ.BCST.Z imm8 m64 k ymm +// VPERMQ.BCST.Z m64 ymm k ymm +// VPERMQ.BCST.Z imm8 m64 k zmm +// VPERMQ.BCST.Z m64 zmm k zmm +// Construct and append a VPERMQ.BCST.Z instruction to the active function. +// Operates on the global context. +func VPERMQ_BCST_Z(im, myz, k, yz operand.Op) { ctx.VPERMQ_BCST_Z(im, myz, k, yz) } + +// VPERMQ_Z: Permute Quadword Integers (Zeroing Masking). +// +// Forms: +// +// VPERMQ.Z imm8 m256 k ymm +// VPERMQ.Z imm8 ymm k ymm +// VPERMQ.Z m256 ymm k ymm +// VPERMQ.Z ymm ymm k ymm +// VPERMQ.Z imm8 m512 k zmm +// VPERMQ.Z imm8 zmm k zmm +// VPERMQ.Z m512 zmm k zmm +// VPERMQ.Z zmm zmm k zmm +// Construct and append a VPERMQ.Z instruction to the active function. +func (c *Context) VPERMQ_Z(imyz, myz, k, yz operand.Op) { + c.addinstruction(x86.VPERMQ_Z(imyz, myz, k, yz)) +} + +// VPERMQ_Z: Permute Quadword Integers (Zeroing Masking). +// +// Forms: +// +// VPERMQ.Z imm8 m256 k ymm +// VPERMQ.Z imm8 ymm k ymm +// VPERMQ.Z m256 ymm k ymm +// VPERMQ.Z ymm ymm k ymm +// VPERMQ.Z imm8 m512 k zmm +// VPERMQ.Z imm8 zmm k zmm +// VPERMQ.Z m512 zmm k zmm +// VPERMQ.Z zmm zmm k zmm +// Construct and append a VPERMQ.Z instruction to the active function. +// Operates on the global context. +func VPERMQ_Z(imyz, myz, k, yz operand.Op) { ctx.VPERMQ_Z(imyz, myz, k, yz) } + +// VPERMT2B: Full Permute of Bytes From Two Tables Overwriting a Table. +// +// Forms: +// +// VPERMT2B m128 xmm k xmm +// VPERMT2B m128 xmm xmm +// VPERMT2B m256 ymm k ymm +// VPERMT2B m256 ymm ymm +// VPERMT2B xmm xmm k xmm +// VPERMT2B xmm xmm xmm +// VPERMT2B ymm ymm k ymm +// VPERMT2B ymm ymm ymm +// VPERMT2B m512 zmm k zmm +// VPERMT2B m512 zmm zmm +// VPERMT2B zmm zmm k zmm +// VPERMT2B zmm zmm zmm +// Construct and append a VPERMT2B instruction to the active function. +func (c *Context) VPERMT2B(ops ...operand.Op) { + c.addinstruction(x86.VPERMT2B(ops...)) +} + +// VPERMT2B: Full Permute of Bytes From Two Tables Overwriting a Table. +// +// Forms: +// +// VPERMT2B m128 xmm k xmm +// VPERMT2B m128 xmm xmm +// VPERMT2B m256 ymm k ymm +// VPERMT2B m256 ymm ymm +// VPERMT2B xmm xmm k xmm +// VPERMT2B xmm xmm xmm +// VPERMT2B ymm ymm k ymm +// VPERMT2B ymm ymm ymm +// VPERMT2B m512 zmm k zmm +// VPERMT2B m512 zmm zmm +// VPERMT2B zmm zmm k zmm +// VPERMT2B zmm zmm zmm +// Construct and append a VPERMT2B instruction to the active function. +// Operates on the global context. +func VPERMT2B(ops ...operand.Op) { ctx.VPERMT2B(ops...) } + +// VPERMT2B_Z: Full Permute of Bytes From Two Tables Overwriting a Table (Zeroing Masking). +// +// Forms: +// +// VPERMT2B.Z m128 xmm k xmm +// VPERMT2B.Z m256 ymm k ymm +// VPERMT2B.Z xmm xmm k xmm +// VPERMT2B.Z ymm ymm k ymm +// VPERMT2B.Z m512 zmm k zmm +// VPERMT2B.Z zmm zmm k zmm +// Construct and append a VPERMT2B.Z instruction to the active function. +func (c *Context) VPERMT2B_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPERMT2B_Z(mxyz, xyz, k, xyz1)) +} + +// VPERMT2B_Z: Full Permute of Bytes From Two Tables Overwriting a Table (Zeroing Masking). +// +// Forms: +// +// VPERMT2B.Z m128 xmm k xmm +// VPERMT2B.Z m256 ymm k ymm +// VPERMT2B.Z xmm xmm k xmm +// VPERMT2B.Z ymm ymm k ymm +// VPERMT2B.Z m512 zmm k zmm +// VPERMT2B.Z zmm zmm k zmm +// Construct and append a VPERMT2B.Z instruction to the active function. +// Operates on the global context. +func VPERMT2B_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPERMT2B_Z(mxyz, xyz, k, xyz1) } + +// VPERMT2D: Full Permute of Doublewords From Two Tables Overwriting a Table. +// +// Forms: +// +// VPERMT2D m128 xmm k xmm +// VPERMT2D m128 xmm xmm +// VPERMT2D m256 ymm k ymm +// VPERMT2D m256 ymm ymm +// VPERMT2D xmm xmm k xmm +// VPERMT2D xmm xmm xmm +// VPERMT2D ymm ymm k ymm +// VPERMT2D ymm ymm ymm +// VPERMT2D m512 zmm k zmm +// VPERMT2D m512 zmm zmm +// VPERMT2D zmm zmm k zmm +// VPERMT2D zmm zmm zmm +// Construct and append a VPERMT2D instruction to the active function. +func (c *Context) VPERMT2D(ops ...operand.Op) { + c.addinstruction(x86.VPERMT2D(ops...)) +} + +// VPERMT2D: Full Permute of Doublewords From Two Tables Overwriting a Table. +// +// Forms: +// +// VPERMT2D m128 xmm k xmm +// VPERMT2D m128 xmm xmm +// VPERMT2D m256 ymm k ymm +// VPERMT2D m256 ymm ymm +// VPERMT2D xmm xmm k xmm +// VPERMT2D xmm xmm xmm +// VPERMT2D ymm ymm k ymm +// VPERMT2D ymm ymm ymm +// VPERMT2D m512 zmm k zmm +// VPERMT2D m512 zmm zmm +// VPERMT2D zmm zmm k zmm +// VPERMT2D zmm zmm zmm +// Construct and append a VPERMT2D instruction to the active function. +// Operates on the global context. +func VPERMT2D(ops ...operand.Op) { ctx.VPERMT2D(ops...) } + +// VPERMT2D_BCST: Full Permute of Doublewords From Two Tables Overwriting a Table (Broadcast). +// +// Forms: +// +// VPERMT2D.BCST m32 xmm k xmm +// VPERMT2D.BCST m32 xmm xmm +// VPERMT2D.BCST m32 ymm k ymm +// VPERMT2D.BCST m32 ymm ymm +// VPERMT2D.BCST m32 zmm k zmm +// VPERMT2D.BCST m32 zmm zmm +// Construct and append a VPERMT2D.BCST instruction to the active function. +func (c *Context) VPERMT2D_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPERMT2D_BCST(ops...)) +} + +// VPERMT2D_BCST: Full Permute of Doublewords From Two Tables Overwriting a Table (Broadcast). +// +// Forms: +// +// VPERMT2D.BCST m32 xmm k xmm +// VPERMT2D.BCST m32 xmm xmm +// VPERMT2D.BCST m32 ymm k ymm +// VPERMT2D.BCST m32 ymm ymm +// VPERMT2D.BCST m32 zmm k zmm +// VPERMT2D.BCST m32 zmm zmm +// Construct and append a VPERMT2D.BCST instruction to the active function. +// Operates on the global context. +func VPERMT2D_BCST(ops ...operand.Op) { ctx.VPERMT2D_BCST(ops...) } + +// VPERMT2D_BCST_Z: Full Permute of Doublewords From Two Tables Overwriting a Table (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMT2D.BCST.Z m32 xmm k xmm +// VPERMT2D.BCST.Z m32 ymm k ymm +// VPERMT2D.BCST.Z m32 zmm k zmm +// Construct and append a VPERMT2D.BCST.Z instruction to the active function. +func (c *Context) VPERMT2D_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPERMT2D_BCST_Z(m, xyz, k, xyz1)) +} + +// VPERMT2D_BCST_Z: Full Permute of Doublewords From Two Tables Overwriting a Table (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMT2D.BCST.Z m32 xmm k xmm +// VPERMT2D.BCST.Z m32 ymm k ymm +// VPERMT2D.BCST.Z m32 zmm k zmm +// Construct and append a VPERMT2D.BCST.Z instruction to the active function. +// Operates on the global context. +func VPERMT2D_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPERMT2D_BCST_Z(m, xyz, k, xyz1) } + +// VPERMT2D_Z: Full Permute of Doublewords From Two Tables Overwriting a Table (Zeroing Masking). +// +// Forms: +// +// VPERMT2D.Z m128 xmm k xmm +// VPERMT2D.Z m256 ymm k ymm +// VPERMT2D.Z xmm xmm k xmm +// VPERMT2D.Z ymm ymm k ymm +// VPERMT2D.Z m512 zmm k zmm +// VPERMT2D.Z zmm zmm k zmm +// Construct and append a VPERMT2D.Z instruction to the active function. +func (c *Context) VPERMT2D_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPERMT2D_Z(mxyz, xyz, k, xyz1)) +} + +// VPERMT2D_Z: Full Permute of Doublewords From Two Tables Overwriting a Table (Zeroing Masking). +// +// Forms: +// +// VPERMT2D.Z m128 xmm k xmm +// VPERMT2D.Z m256 ymm k ymm +// VPERMT2D.Z xmm xmm k xmm +// VPERMT2D.Z ymm ymm k ymm +// VPERMT2D.Z m512 zmm k zmm +// VPERMT2D.Z zmm zmm k zmm +// Construct and append a VPERMT2D.Z instruction to the active function. +// Operates on the global context. +func VPERMT2D_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPERMT2D_Z(mxyz, xyz, k, xyz1) } + +// VPERMT2PD: Full Permute of Double-Precision Floating-Point Values From Two Tables Overwriting a Table. +// +// Forms: +// +// VPERMT2PD m128 xmm k xmm +// VPERMT2PD m128 xmm xmm +// VPERMT2PD m256 ymm k ymm +// VPERMT2PD m256 ymm ymm +// VPERMT2PD xmm xmm k xmm +// VPERMT2PD xmm xmm xmm +// VPERMT2PD ymm ymm k ymm +// VPERMT2PD ymm ymm ymm +// VPERMT2PD m512 zmm k zmm +// VPERMT2PD m512 zmm zmm +// VPERMT2PD zmm zmm k zmm +// VPERMT2PD zmm zmm zmm +// Construct and append a VPERMT2PD instruction to the active function. +func (c *Context) VPERMT2PD(ops ...operand.Op) { + c.addinstruction(x86.VPERMT2PD(ops...)) +} + +// VPERMT2PD: Full Permute of Double-Precision Floating-Point Values From Two Tables Overwriting a Table. +// +// Forms: +// +// VPERMT2PD m128 xmm k xmm +// VPERMT2PD m128 xmm xmm +// VPERMT2PD m256 ymm k ymm +// VPERMT2PD m256 ymm ymm +// VPERMT2PD xmm xmm k xmm +// VPERMT2PD xmm xmm xmm +// VPERMT2PD ymm ymm k ymm +// VPERMT2PD ymm ymm ymm +// VPERMT2PD m512 zmm k zmm +// VPERMT2PD m512 zmm zmm +// VPERMT2PD zmm zmm k zmm +// VPERMT2PD zmm zmm zmm +// Construct and append a VPERMT2PD instruction to the active function. +// Operates on the global context. +func VPERMT2PD(ops ...operand.Op) { ctx.VPERMT2PD(ops...) } + +// VPERMT2PD_BCST: Full Permute of Double-Precision Floating-Point Values From Two Tables Overwriting a Table (Broadcast). +// +// Forms: +// +// VPERMT2PD.BCST m64 xmm k xmm +// VPERMT2PD.BCST m64 xmm xmm +// VPERMT2PD.BCST m64 ymm k ymm +// VPERMT2PD.BCST m64 ymm ymm +// VPERMT2PD.BCST m64 zmm k zmm +// VPERMT2PD.BCST m64 zmm zmm +// Construct and append a VPERMT2PD.BCST instruction to the active function. +func (c *Context) VPERMT2PD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPERMT2PD_BCST(ops...)) +} + +// VPERMT2PD_BCST: Full Permute of Double-Precision Floating-Point Values From Two Tables Overwriting a Table (Broadcast). +// +// Forms: +// +// VPERMT2PD.BCST m64 xmm k xmm +// VPERMT2PD.BCST m64 xmm xmm +// VPERMT2PD.BCST m64 ymm k ymm +// VPERMT2PD.BCST m64 ymm ymm +// VPERMT2PD.BCST m64 zmm k zmm +// VPERMT2PD.BCST m64 zmm zmm +// Construct and append a VPERMT2PD.BCST instruction to the active function. +// Operates on the global context. +func VPERMT2PD_BCST(ops ...operand.Op) { ctx.VPERMT2PD_BCST(ops...) } + +// VPERMT2PD_BCST_Z: Full Permute of Double-Precision Floating-Point Values From Two Tables Overwriting a Table (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMT2PD.BCST.Z m64 xmm k xmm +// VPERMT2PD.BCST.Z m64 ymm k ymm +// VPERMT2PD.BCST.Z m64 zmm k zmm +// Construct and append a VPERMT2PD.BCST.Z instruction to the active function. +func (c *Context) VPERMT2PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPERMT2PD_BCST_Z(m, xyz, k, xyz1)) +} + +// VPERMT2PD_BCST_Z: Full Permute of Double-Precision Floating-Point Values From Two Tables Overwriting a Table (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMT2PD.BCST.Z m64 xmm k xmm +// VPERMT2PD.BCST.Z m64 ymm k ymm +// VPERMT2PD.BCST.Z m64 zmm k zmm +// Construct and append a VPERMT2PD.BCST.Z instruction to the active function. +// Operates on the global context. +func VPERMT2PD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPERMT2PD_BCST_Z(m, xyz, k, xyz1) } + +// VPERMT2PD_Z: Full Permute of Double-Precision Floating-Point Values From Two Tables Overwriting a Table (Zeroing Masking). +// +// Forms: +// +// VPERMT2PD.Z m128 xmm k xmm +// VPERMT2PD.Z m256 ymm k ymm +// VPERMT2PD.Z xmm xmm k xmm +// VPERMT2PD.Z ymm ymm k ymm +// VPERMT2PD.Z m512 zmm k zmm +// VPERMT2PD.Z zmm zmm k zmm +// Construct and append a VPERMT2PD.Z instruction to the active function. +func (c *Context) VPERMT2PD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPERMT2PD_Z(mxyz, xyz, k, xyz1)) +} + +// VPERMT2PD_Z: Full Permute of Double-Precision Floating-Point Values From Two Tables Overwriting a Table (Zeroing Masking). +// +// Forms: +// +// VPERMT2PD.Z m128 xmm k xmm +// VPERMT2PD.Z m256 ymm k ymm +// VPERMT2PD.Z xmm xmm k xmm +// VPERMT2PD.Z ymm ymm k ymm +// VPERMT2PD.Z m512 zmm k zmm +// VPERMT2PD.Z zmm zmm k zmm +// Construct and append a VPERMT2PD.Z instruction to the active function. +// Operates on the global context. +func VPERMT2PD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPERMT2PD_Z(mxyz, xyz, k, xyz1) } + +// VPERMT2PS: Full Permute of Single-Precision Floating-Point Values From Two Tables Overwriting a Table. +// +// Forms: +// +// VPERMT2PS m128 xmm k xmm +// VPERMT2PS m128 xmm xmm +// VPERMT2PS m256 ymm k ymm +// VPERMT2PS m256 ymm ymm +// VPERMT2PS xmm xmm k xmm +// VPERMT2PS xmm xmm xmm +// VPERMT2PS ymm ymm k ymm +// VPERMT2PS ymm ymm ymm +// VPERMT2PS m512 zmm k zmm +// VPERMT2PS m512 zmm zmm +// VPERMT2PS zmm zmm k zmm +// VPERMT2PS zmm zmm zmm +// Construct and append a VPERMT2PS instruction to the active function. +func (c *Context) VPERMT2PS(ops ...operand.Op) { + c.addinstruction(x86.VPERMT2PS(ops...)) +} + +// VPERMT2PS: Full Permute of Single-Precision Floating-Point Values From Two Tables Overwriting a Table. +// +// Forms: +// +// VPERMT2PS m128 xmm k xmm +// VPERMT2PS m128 xmm xmm +// VPERMT2PS m256 ymm k ymm +// VPERMT2PS m256 ymm ymm +// VPERMT2PS xmm xmm k xmm +// VPERMT2PS xmm xmm xmm +// VPERMT2PS ymm ymm k ymm +// VPERMT2PS ymm ymm ymm +// VPERMT2PS m512 zmm k zmm +// VPERMT2PS m512 zmm zmm +// VPERMT2PS zmm zmm k zmm +// VPERMT2PS zmm zmm zmm +// Construct and append a VPERMT2PS instruction to the active function. +// Operates on the global context. +func VPERMT2PS(ops ...operand.Op) { ctx.VPERMT2PS(ops...) } + +// VPERMT2PS_BCST: Full Permute of Single-Precision Floating-Point Values From Two Tables Overwriting a Table (Broadcast). +// +// Forms: +// +// VPERMT2PS.BCST m32 xmm k xmm +// VPERMT2PS.BCST m32 xmm xmm +// VPERMT2PS.BCST m32 ymm k ymm +// VPERMT2PS.BCST m32 ymm ymm +// VPERMT2PS.BCST m32 zmm k zmm +// VPERMT2PS.BCST m32 zmm zmm +// Construct and append a VPERMT2PS.BCST instruction to the active function. +func (c *Context) VPERMT2PS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPERMT2PS_BCST(ops...)) +} + +// VPERMT2PS_BCST: Full Permute of Single-Precision Floating-Point Values From Two Tables Overwriting a Table (Broadcast). +// +// Forms: +// +// VPERMT2PS.BCST m32 xmm k xmm +// VPERMT2PS.BCST m32 xmm xmm +// VPERMT2PS.BCST m32 ymm k ymm +// VPERMT2PS.BCST m32 ymm ymm +// VPERMT2PS.BCST m32 zmm k zmm +// VPERMT2PS.BCST m32 zmm zmm +// Construct and append a VPERMT2PS.BCST instruction to the active function. +// Operates on the global context. +func VPERMT2PS_BCST(ops ...operand.Op) { ctx.VPERMT2PS_BCST(ops...) } + +// VPERMT2PS_BCST_Z: Full Permute of Single-Precision Floating-Point Values From Two Tables Overwriting a Table (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMT2PS.BCST.Z m32 xmm k xmm +// VPERMT2PS.BCST.Z m32 ymm k ymm +// VPERMT2PS.BCST.Z m32 zmm k zmm +// Construct and append a VPERMT2PS.BCST.Z instruction to the active function. +func (c *Context) VPERMT2PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPERMT2PS_BCST_Z(m, xyz, k, xyz1)) +} + +// VPERMT2PS_BCST_Z: Full Permute of Single-Precision Floating-Point Values From Two Tables Overwriting a Table (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMT2PS.BCST.Z m32 xmm k xmm +// VPERMT2PS.BCST.Z m32 ymm k ymm +// VPERMT2PS.BCST.Z m32 zmm k zmm +// Construct and append a VPERMT2PS.BCST.Z instruction to the active function. +// Operates on the global context. +func VPERMT2PS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPERMT2PS_BCST_Z(m, xyz, k, xyz1) } + +// VPERMT2PS_Z: Full Permute of Single-Precision Floating-Point Values From Two Tables Overwriting a Table (Zeroing Masking). +// +// Forms: +// +// VPERMT2PS.Z m128 xmm k xmm +// VPERMT2PS.Z m256 ymm k ymm +// VPERMT2PS.Z xmm xmm k xmm +// VPERMT2PS.Z ymm ymm k ymm +// VPERMT2PS.Z m512 zmm k zmm +// VPERMT2PS.Z zmm zmm k zmm +// Construct and append a VPERMT2PS.Z instruction to the active function. +func (c *Context) VPERMT2PS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPERMT2PS_Z(mxyz, xyz, k, xyz1)) +} + +// VPERMT2PS_Z: Full Permute of Single-Precision Floating-Point Values From Two Tables Overwriting a Table (Zeroing Masking). +// +// Forms: +// +// VPERMT2PS.Z m128 xmm k xmm +// VPERMT2PS.Z m256 ymm k ymm +// VPERMT2PS.Z xmm xmm k xmm +// VPERMT2PS.Z ymm ymm k ymm +// VPERMT2PS.Z m512 zmm k zmm +// VPERMT2PS.Z zmm zmm k zmm +// Construct and append a VPERMT2PS.Z instruction to the active function. +// Operates on the global context. +func VPERMT2PS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPERMT2PS_Z(mxyz, xyz, k, xyz1) } + +// VPERMT2Q: Full Permute of Quadwords From Two Tables Overwriting a Table. +// +// Forms: +// +// VPERMT2Q m128 xmm k xmm +// VPERMT2Q m128 xmm xmm +// VPERMT2Q m256 ymm k ymm +// VPERMT2Q m256 ymm ymm +// VPERMT2Q xmm xmm k xmm +// VPERMT2Q xmm xmm xmm +// VPERMT2Q ymm ymm k ymm +// VPERMT2Q ymm ymm ymm +// VPERMT2Q m512 zmm k zmm +// VPERMT2Q m512 zmm zmm +// VPERMT2Q zmm zmm k zmm +// VPERMT2Q zmm zmm zmm +// Construct and append a VPERMT2Q instruction to the active function. +func (c *Context) VPERMT2Q(ops ...operand.Op) { + c.addinstruction(x86.VPERMT2Q(ops...)) +} + +// VPERMT2Q: Full Permute of Quadwords From Two Tables Overwriting a Table. +// +// Forms: +// +// VPERMT2Q m128 xmm k xmm +// VPERMT2Q m128 xmm xmm +// VPERMT2Q m256 ymm k ymm +// VPERMT2Q m256 ymm ymm +// VPERMT2Q xmm xmm k xmm +// VPERMT2Q xmm xmm xmm +// VPERMT2Q ymm ymm k ymm +// VPERMT2Q ymm ymm ymm +// VPERMT2Q m512 zmm k zmm +// VPERMT2Q m512 zmm zmm +// VPERMT2Q zmm zmm k zmm +// VPERMT2Q zmm zmm zmm +// Construct and append a VPERMT2Q instruction to the active function. +// Operates on the global context. +func VPERMT2Q(ops ...operand.Op) { ctx.VPERMT2Q(ops...) } + +// VPERMT2Q_BCST: Full Permute of Quadwords From Two Tables Overwriting a Table (Broadcast). +// +// Forms: +// +// VPERMT2Q.BCST m64 xmm k xmm +// VPERMT2Q.BCST m64 xmm xmm +// VPERMT2Q.BCST m64 ymm k ymm +// VPERMT2Q.BCST m64 ymm ymm +// VPERMT2Q.BCST m64 zmm k zmm +// VPERMT2Q.BCST m64 zmm zmm +// Construct and append a VPERMT2Q.BCST instruction to the active function. +func (c *Context) VPERMT2Q_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPERMT2Q_BCST(ops...)) +} + +// VPERMT2Q_BCST: Full Permute of Quadwords From Two Tables Overwriting a Table (Broadcast). +// +// Forms: +// +// VPERMT2Q.BCST m64 xmm k xmm +// VPERMT2Q.BCST m64 xmm xmm +// VPERMT2Q.BCST m64 ymm k ymm +// VPERMT2Q.BCST m64 ymm ymm +// VPERMT2Q.BCST m64 zmm k zmm +// VPERMT2Q.BCST m64 zmm zmm +// Construct and append a VPERMT2Q.BCST instruction to the active function. +// Operates on the global context. +func VPERMT2Q_BCST(ops ...operand.Op) { ctx.VPERMT2Q_BCST(ops...) } + +// VPERMT2Q_BCST_Z: Full Permute of Quadwords From Two Tables Overwriting a Table (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMT2Q.BCST.Z m64 xmm k xmm +// VPERMT2Q.BCST.Z m64 ymm k ymm +// VPERMT2Q.BCST.Z m64 zmm k zmm +// Construct and append a VPERMT2Q.BCST.Z instruction to the active function. +func (c *Context) VPERMT2Q_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPERMT2Q_BCST_Z(m, xyz, k, xyz1)) +} + +// VPERMT2Q_BCST_Z: Full Permute of Quadwords From Two Tables Overwriting a Table (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMT2Q.BCST.Z m64 xmm k xmm +// VPERMT2Q.BCST.Z m64 ymm k ymm +// VPERMT2Q.BCST.Z m64 zmm k zmm +// Construct and append a VPERMT2Q.BCST.Z instruction to the active function. +// Operates on the global context. +func VPERMT2Q_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPERMT2Q_BCST_Z(m, xyz, k, xyz1) } + +// VPERMT2Q_Z: Full Permute of Quadwords From Two Tables Overwriting a Table (Zeroing Masking). +// +// Forms: +// +// VPERMT2Q.Z m128 xmm k xmm +// VPERMT2Q.Z m256 ymm k ymm +// VPERMT2Q.Z xmm xmm k xmm +// VPERMT2Q.Z ymm ymm k ymm +// VPERMT2Q.Z m512 zmm k zmm +// VPERMT2Q.Z zmm zmm k zmm +// Construct and append a VPERMT2Q.Z instruction to the active function. +func (c *Context) VPERMT2Q_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPERMT2Q_Z(mxyz, xyz, k, xyz1)) +} + +// VPERMT2Q_Z: Full Permute of Quadwords From Two Tables Overwriting a Table (Zeroing Masking). +// +// Forms: +// +// VPERMT2Q.Z m128 xmm k xmm +// VPERMT2Q.Z m256 ymm k ymm +// VPERMT2Q.Z xmm xmm k xmm +// VPERMT2Q.Z ymm ymm k ymm +// VPERMT2Q.Z m512 zmm k zmm +// VPERMT2Q.Z zmm zmm k zmm +// Construct and append a VPERMT2Q.Z instruction to the active function. +// Operates on the global context. +func VPERMT2Q_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPERMT2Q_Z(mxyz, xyz, k, xyz1) } + +// VPERMT2W: Full Permute of Words From Two Tables Overwriting a Table. +// +// Forms: +// +// VPERMT2W m128 xmm k xmm +// VPERMT2W m128 xmm xmm +// VPERMT2W m256 ymm k ymm +// VPERMT2W m256 ymm ymm +// VPERMT2W xmm xmm k xmm +// VPERMT2W xmm xmm xmm +// VPERMT2W ymm ymm k ymm +// VPERMT2W ymm ymm ymm +// VPERMT2W m512 zmm k zmm +// VPERMT2W m512 zmm zmm +// VPERMT2W zmm zmm k zmm +// VPERMT2W zmm zmm zmm +// Construct and append a VPERMT2W instruction to the active function. +func (c *Context) VPERMT2W(ops ...operand.Op) { + c.addinstruction(x86.VPERMT2W(ops...)) +} + +// VPERMT2W: Full Permute of Words From Two Tables Overwriting a Table. +// +// Forms: +// +// VPERMT2W m128 xmm k xmm +// VPERMT2W m128 xmm xmm +// VPERMT2W m256 ymm k ymm +// VPERMT2W m256 ymm ymm +// VPERMT2W xmm xmm k xmm +// VPERMT2W xmm xmm xmm +// VPERMT2W ymm ymm k ymm +// VPERMT2W ymm ymm ymm +// VPERMT2W m512 zmm k zmm +// VPERMT2W m512 zmm zmm +// VPERMT2W zmm zmm k zmm +// VPERMT2W zmm zmm zmm +// Construct and append a VPERMT2W instruction to the active function. +// Operates on the global context. +func VPERMT2W(ops ...operand.Op) { ctx.VPERMT2W(ops...) } + +// VPERMT2W_Z: Full Permute of Words From Two Tables Overwriting a Table (Zeroing Masking). +// +// Forms: +// +// VPERMT2W.Z m128 xmm k xmm +// VPERMT2W.Z m256 ymm k ymm +// VPERMT2W.Z xmm xmm k xmm +// VPERMT2W.Z ymm ymm k ymm +// VPERMT2W.Z m512 zmm k zmm +// VPERMT2W.Z zmm zmm k zmm +// Construct and append a VPERMT2W.Z instruction to the active function. +func (c *Context) VPERMT2W_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPERMT2W_Z(mxyz, xyz, k, xyz1)) +} + +// VPERMT2W_Z: Full Permute of Words From Two Tables Overwriting a Table (Zeroing Masking). +// +// Forms: +// +// VPERMT2W.Z m128 xmm k xmm +// VPERMT2W.Z m256 ymm k ymm +// VPERMT2W.Z xmm xmm k xmm +// VPERMT2W.Z ymm ymm k ymm +// VPERMT2W.Z m512 zmm k zmm +// VPERMT2W.Z zmm zmm k zmm +// Construct and append a VPERMT2W.Z instruction to the active function. +// Operates on the global context. +func VPERMT2W_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPERMT2W_Z(mxyz, xyz, k, xyz1) } + +// VPERMW: Permute Word Integers. +// +// Forms: +// +// VPERMW m128 xmm k xmm +// VPERMW m128 xmm xmm +// VPERMW m256 ymm k ymm +// VPERMW m256 ymm ymm +// VPERMW xmm xmm k xmm +// VPERMW xmm xmm xmm +// VPERMW ymm ymm k ymm +// VPERMW ymm ymm ymm +// VPERMW m512 zmm k zmm +// VPERMW m512 zmm zmm +// VPERMW zmm zmm k zmm +// VPERMW zmm zmm zmm +// Construct and append a VPERMW instruction to the active function. +func (c *Context) VPERMW(ops ...operand.Op) { + c.addinstruction(x86.VPERMW(ops...)) +} + +// VPERMW: Permute Word Integers. +// +// Forms: +// +// VPERMW m128 xmm k xmm +// VPERMW m128 xmm xmm +// VPERMW m256 ymm k ymm +// VPERMW m256 ymm ymm +// VPERMW xmm xmm k xmm +// VPERMW xmm xmm xmm +// VPERMW ymm ymm k ymm +// VPERMW ymm ymm ymm +// VPERMW m512 zmm k zmm +// VPERMW m512 zmm zmm +// VPERMW zmm zmm k zmm +// VPERMW zmm zmm zmm +// Construct and append a VPERMW instruction to the active function. +// Operates on the global context. +func VPERMW(ops ...operand.Op) { ctx.VPERMW(ops...) } + +// VPERMW_Z: Permute Word Integers (Zeroing Masking). +// +// Forms: +// +// VPERMW.Z m128 xmm k xmm +// VPERMW.Z m256 ymm k ymm +// VPERMW.Z xmm xmm k xmm +// VPERMW.Z ymm ymm k ymm +// VPERMW.Z m512 zmm k zmm +// VPERMW.Z zmm zmm k zmm +// Construct and append a VPERMW.Z instruction to the active function. +func (c *Context) VPERMW_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPERMW_Z(mxyz, xyz, k, xyz1)) +} + +// VPERMW_Z: Permute Word Integers (Zeroing Masking). +// +// Forms: +// +// VPERMW.Z m128 xmm k xmm +// VPERMW.Z m256 ymm k ymm +// VPERMW.Z xmm xmm k xmm +// VPERMW.Z ymm ymm k ymm +// VPERMW.Z m512 zmm k zmm +// VPERMW.Z zmm zmm k zmm +// Construct and append a VPERMW.Z instruction to the active function. +// Operates on the global context. +func VPERMW_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPERMW_Z(mxyz, xyz, k, xyz1) } + +// VPEXPANDD: Load Sparse Packed Doubleword Integer Values from Dense Memory/Register. +// +// Forms: +// +// VPEXPANDD m128 k xmm +// VPEXPANDD m128 xmm +// VPEXPANDD m256 k ymm +// VPEXPANDD m256 ymm +// VPEXPANDD xmm k xmm +// VPEXPANDD xmm xmm +// VPEXPANDD ymm k ymm +// VPEXPANDD ymm ymm +// VPEXPANDD m512 k zmm +// VPEXPANDD m512 zmm +// VPEXPANDD zmm k zmm +// VPEXPANDD zmm zmm +// Construct and append a VPEXPANDD instruction to the active function. +func (c *Context) VPEXPANDD(ops ...operand.Op) { + c.addinstruction(x86.VPEXPANDD(ops...)) +} + +// VPEXPANDD: Load Sparse Packed Doubleword Integer Values from Dense Memory/Register. +// +// Forms: +// +// VPEXPANDD m128 k xmm +// VPEXPANDD m128 xmm +// VPEXPANDD m256 k ymm +// VPEXPANDD m256 ymm +// VPEXPANDD xmm k xmm +// VPEXPANDD xmm xmm +// VPEXPANDD ymm k ymm +// VPEXPANDD ymm ymm +// VPEXPANDD m512 k zmm +// VPEXPANDD m512 zmm +// VPEXPANDD zmm k zmm +// VPEXPANDD zmm zmm +// Construct and append a VPEXPANDD instruction to the active function. +// Operates on the global context. +func VPEXPANDD(ops ...operand.Op) { ctx.VPEXPANDD(ops...) } + +// VPEXPANDD_Z: Load Sparse Packed Doubleword Integer Values from Dense Memory/Register (Zeroing Masking). +// +// Forms: +// +// VPEXPANDD.Z m128 k xmm +// VPEXPANDD.Z m256 k ymm +// VPEXPANDD.Z xmm k xmm +// VPEXPANDD.Z ymm k ymm +// VPEXPANDD.Z m512 k zmm +// VPEXPANDD.Z zmm k zmm +// Construct and append a VPEXPANDD.Z instruction to the active function. +func (c *Context) VPEXPANDD_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPEXPANDD_Z(mxyz, k, xyz)) +} + +// VPEXPANDD_Z: Load Sparse Packed Doubleword Integer Values from Dense Memory/Register (Zeroing Masking). +// +// Forms: +// +// VPEXPANDD.Z m128 k xmm +// VPEXPANDD.Z m256 k ymm +// VPEXPANDD.Z xmm k xmm +// VPEXPANDD.Z ymm k ymm +// VPEXPANDD.Z m512 k zmm +// VPEXPANDD.Z zmm k zmm +// Construct and append a VPEXPANDD.Z instruction to the active function. +// Operates on the global context. +func VPEXPANDD_Z(mxyz, k, xyz operand.Op) { ctx.VPEXPANDD_Z(mxyz, k, xyz) } + +// VPEXPANDQ: Load Sparse Packed Quadword Integer Values from Dense Memory/Register. +// +// Forms: +// +// VPEXPANDQ m128 k xmm +// VPEXPANDQ m128 xmm +// VPEXPANDQ m256 k ymm +// VPEXPANDQ m256 ymm +// VPEXPANDQ xmm k xmm +// VPEXPANDQ xmm xmm +// VPEXPANDQ ymm k ymm +// VPEXPANDQ ymm ymm +// VPEXPANDQ m512 k zmm +// VPEXPANDQ m512 zmm +// VPEXPANDQ zmm k zmm +// VPEXPANDQ zmm zmm +// Construct and append a VPEXPANDQ instruction to the active function. +func (c *Context) VPEXPANDQ(ops ...operand.Op) { + c.addinstruction(x86.VPEXPANDQ(ops...)) +} + +// VPEXPANDQ: Load Sparse Packed Quadword Integer Values from Dense Memory/Register. +// +// Forms: +// +// VPEXPANDQ m128 k xmm +// VPEXPANDQ m128 xmm +// VPEXPANDQ m256 k ymm +// VPEXPANDQ m256 ymm +// VPEXPANDQ xmm k xmm +// VPEXPANDQ xmm xmm +// VPEXPANDQ ymm k ymm +// VPEXPANDQ ymm ymm +// VPEXPANDQ m512 k zmm +// VPEXPANDQ m512 zmm +// VPEXPANDQ zmm k zmm +// VPEXPANDQ zmm zmm +// Construct and append a VPEXPANDQ instruction to the active function. +// Operates on the global context. +func VPEXPANDQ(ops ...operand.Op) { ctx.VPEXPANDQ(ops...) } + +// VPEXPANDQ_Z: Load Sparse Packed Quadword Integer Values from Dense Memory/Register (Zeroing Masking). +// +// Forms: +// +// VPEXPANDQ.Z m128 k xmm +// VPEXPANDQ.Z m256 k ymm +// VPEXPANDQ.Z xmm k xmm +// VPEXPANDQ.Z ymm k ymm +// VPEXPANDQ.Z m512 k zmm +// VPEXPANDQ.Z zmm k zmm +// Construct and append a VPEXPANDQ.Z instruction to the active function. +func (c *Context) VPEXPANDQ_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPEXPANDQ_Z(mxyz, k, xyz)) +} + +// VPEXPANDQ_Z: Load Sparse Packed Quadword Integer Values from Dense Memory/Register (Zeroing Masking). +// +// Forms: +// +// VPEXPANDQ.Z m128 k xmm +// VPEXPANDQ.Z m256 k ymm +// VPEXPANDQ.Z xmm k xmm +// VPEXPANDQ.Z ymm k ymm +// VPEXPANDQ.Z m512 k zmm +// VPEXPANDQ.Z zmm k zmm +// Construct and append a VPEXPANDQ.Z instruction to the active function. +// Operates on the global context. +func VPEXPANDQ_Z(mxyz, k, xyz operand.Op) { ctx.VPEXPANDQ_Z(mxyz, k, xyz) } + +// VPEXTRB: Extract Byte. +// +// Forms: +// +// VPEXTRB imm8 xmm m8 +// VPEXTRB imm8 xmm r32 +// Construct and append a VPEXTRB instruction to the active function. +func (c *Context) VPEXTRB(i, x, mr operand.Op) { + c.addinstruction(x86.VPEXTRB(i, x, mr)) +} + +// VPEXTRB: Extract Byte. +// +// Forms: +// +// VPEXTRB imm8 xmm m8 +// VPEXTRB imm8 xmm r32 +// Construct and append a VPEXTRB instruction to the active function. +// Operates on the global context. +func VPEXTRB(i, x, mr operand.Op) { ctx.VPEXTRB(i, x, mr) } + +// VPEXTRD: Extract Doubleword. +// +// Forms: +// +// VPEXTRD imm8 xmm m32 +// VPEXTRD imm8 xmm r32 +// Construct and append a VPEXTRD instruction to the active function. +func (c *Context) VPEXTRD(i, x, mr operand.Op) { + c.addinstruction(x86.VPEXTRD(i, x, mr)) +} + +// VPEXTRD: Extract Doubleword. +// +// Forms: +// +// VPEXTRD imm8 xmm m32 +// VPEXTRD imm8 xmm r32 +// Construct and append a VPEXTRD instruction to the active function. +// Operates on the global context. +func VPEXTRD(i, x, mr operand.Op) { ctx.VPEXTRD(i, x, mr) } + +// VPEXTRQ: Extract Quadword. +// +// Forms: +// +// VPEXTRQ imm8 xmm m64 +// VPEXTRQ imm8 xmm r64 +// Construct and append a VPEXTRQ instruction to the active function. +func (c *Context) VPEXTRQ(i, x, mr operand.Op) { + c.addinstruction(x86.VPEXTRQ(i, x, mr)) +} + +// VPEXTRQ: Extract Quadword. +// +// Forms: +// +// VPEXTRQ imm8 xmm m64 +// VPEXTRQ imm8 xmm r64 +// Construct and append a VPEXTRQ instruction to the active function. +// Operates on the global context. +func VPEXTRQ(i, x, mr operand.Op) { ctx.VPEXTRQ(i, x, mr) } + +// VPEXTRW: Extract Word. +// +// Forms: +// +// VPEXTRW imm8 xmm m16 +// VPEXTRW imm8 xmm r32 +// Construct and append a VPEXTRW instruction to the active function. +func (c *Context) VPEXTRW(i, x, mr operand.Op) { + c.addinstruction(x86.VPEXTRW(i, x, mr)) +} + +// VPEXTRW: Extract Word. +// +// Forms: +// +// VPEXTRW imm8 xmm m16 +// VPEXTRW imm8 xmm r32 +// Construct and append a VPEXTRW instruction to the active function. +// Operates on the global context. +func VPEXTRW(i, x, mr operand.Op) { ctx.VPEXTRW(i, x, mr) } + +// VPGATHERDD: Gather Packed Doubleword Values Using Signed Doubleword Indices. +// +// Forms: +// +// VPGATHERDD xmm vm32x xmm +// VPGATHERDD ymm vm32y ymm +// VPGATHERDD vm32x k xmm +// VPGATHERDD vm32y k ymm +// VPGATHERDD vm32z k zmm +// Construct and append a VPGATHERDD instruction to the active function. +func (c *Context) VPGATHERDD(vxy, kv, xyz operand.Op) { + c.addinstruction(x86.VPGATHERDD(vxy, kv, xyz)) +} + +// VPGATHERDD: Gather Packed Doubleword Values Using Signed Doubleword Indices. +// +// Forms: +// +// VPGATHERDD xmm vm32x xmm +// VPGATHERDD ymm vm32y ymm +// VPGATHERDD vm32x k xmm +// VPGATHERDD vm32y k ymm +// VPGATHERDD vm32z k zmm +// Construct and append a VPGATHERDD instruction to the active function. +// Operates on the global context. +func VPGATHERDD(vxy, kv, xyz operand.Op) { ctx.VPGATHERDD(vxy, kv, xyz) } + +// VPGATHERDQ: Gather Packed Quadword Values Using Signed Doubleword Indices. +// +// Forms: +// +// VPGATHERDQ xmm vm32x xmm +// VPGATHERDQ ymm vm32x ymm +// VPGATHERDQ vm32x k xmm +// VPGATHERDQ vm32x k ymm +// VPGATHERDQ vm32y k zmm +// Construct and append a VPGATHERDQ instruction to the active function. +func (c *Context) VPGATHERDQ(vxy, kv, xyz operand.Op) { + c.addinstruction(x86.VPGATHERDQ(vxy, kv, xyz)) +} + +// VPGATHERDQ: Gather Packed Quadword Values Using Signed Doubleword Indices. +// +// Forms: +// +// VPGATHERDQ xmm vm32x xmm +// VPGATHERDQ ymm vm32x ymm +// VPGATHERDQ vm32x k xmm +// VPGATHERDQ vm32x k ymm +// VPGATHERDQ vm32y k zmm +// Construct and append a VPGATHERDQ instruction to the active function. +// Operates on the global context. +func VPGATHERDQ(vxy, kv, xyz operand.Op) { ctx.VPGATHERDQ(vxy, kv, xyz) } + +// VPGATHERQD: Gather Packed Doubleword Values Using Signed Quadword Indices. +// +// Forms: +// +// VPGATHERQD xmm vm64x xmm +// VPGATHERQD xmm vm64y xmm +// VPGATHERQD vm64x k xmm +// VPGATHERQD vm64y k xmm +// VPGATHERQD vm64z k ymm +// Construct and append a VPGATHERQD instruction to the active function. +func (c *Context) VPGATHERQD(vx, kv, xy operand.Op) { + c.addinstruction(x86.VPGATHERQD(vx, kv, xy)) +} + +// VPGATHERQD: Gather Packed Doubleword Values Using Signed Quadword Indices. +// +// Forms: +// +// VPGATHERQD xmm vm64x xmm +// VPGATHERQD xmm vm64y xmm +// VPGATHERQD vm64x k xmm +// VPGATHERQD vm64y k xmm +// VPGATHERQD vm64z k ymm +// Construct and append a VPGATHERQD instruction to the active function. +// Operates on the global context. +func VPGATHERQD(vx, kv, xy operand.Op) { ctx.VPGATHERQD(vx, kv, xy) } + +// VPGATHERQQ: Gather Packed Quadword Values Using Signed Quadword Indices. +// +// Forms: +// +// VPGATHERQQ xmm vm64x xmm +// VPGATHERQQ ymm vm64y ymm +// VPGATHERQQ vm64x k xmm +// VPGATHERQQ vm64y k ymm +// VPGATHERQQ vm64z k zmm +// Construct and append a VPGATHERQQ instruction to the active function. +func (c *Context) VPGATHERQQ(vxy, kv, xyz operand.Op) { + c.addinstruction(x86.VPGATHERQQ(vxy, kv, xyz)) +} + +// VPGATHERQQ: Gather Packed Quadword Values Using Signed Quadword Indices. +// +// Forms: +// +// VPGATHERQQ xmm vm64x xmm +// VPGATHERQQ ymm vm64y ymm +// VPGATHERQQ vm64x k xmm +// VPGATHERQQ vm64y k ymm +// VPGATHERQQ vm64z k zmm +// Construct and append a VPGATHERQQ instruction to the active function. +// Operates on the global context. +func VPGATHERQQ(vxy, kv, xyz operand.Op) { ctx.VPGATHERQQ(vxy, kv, xyz) } + +// VPHADDD: Packed Horizontal Add Doubleword Integer. +// +// Forms: +// +// VPHADDD m256 ymm ymm +// VPHADDD ymm ymm ymm +// VPHADDD m128 xmm xmm +// VPHADDD xmm xmm xmm +// Construct and append a VPHADDD instruction to the active function. +func (c *Context) VPHADDD(mxy, xy, xy1 operand.Op) { + c.addinstruction(x86.VPHADDD(mxy, xy, xy1)) +} + +// VPHADDD: Packed Horizontal Add Doubleword Integer. +// +// Forms: +// +// VPHADDD m256 ymm ymm +// VPHADDD ymm ymm ymm +// VPHADDD m128 xmm xmm +// VPHADDD xmm xmm xmm +// Construct and append a VPHADDD instruction to the active function. +// Operates on the global context. +func VPHADDD(mxy, xy, xy1 operand.Op) { ctx.VPHADDD(mxy, xy, xy1) } + +// VPHADDSW: Packed Horizontal Add Signed Word Integers with Signed Saturation. +// +// Forms: +// +// VPHADDSW m256 ymm ymm +// VPHADDSW ymm ymm ymm +// VPHADDSW m128 xmm xmm +// VPHADDSW xmm xmm xmm +// Construct and append a VPHADDSW instruction to the active function. +func (c *Context) VPHADDSW(mxy, xy, xy1 operand.Op) { + c.addinstruction(x86.VPHADDSW(mxy, xy, xy1)) +} + +// VPHADDSW: Packed Horizontal Add Signed Word Integers with Signed Saturation. +// +// Forms: +// +// VPHADDSW m256 ymm ymm +// VPHADDSW ymm ymm ymm +// VPHADDSW m128 xmm xmm +// VPHADDSW xmm xmm xmm +// Construct and append a VPHADDSW instruction to the active function. +// Operates on the global context. +func VPHADDSW(mxy, xy, xy1 operand.Op) { ctx.VPHADDSW(mxy, xy, xy1) } + +// VPHADDW: Packed Horizontal Add Word Integers. +// +// Forms: +// +// VPHADDW m256 ymm ymm +// VPHADDW ymm ymm ymm +// VPHADDW m128 xmm xmm +// VPHADDW xmm xmm xmm +// Construct and append a VPHADDW instruction to the active function. +func (c *Context) VPHADDW(mxy, xy, xy1 operand.Op) { + c.addinstruction(x86.VPHADDW(mxy, xy, xy1)) +} + +// VPHADDW: Packed Horizontal Add Word Integers. +// +// Forms: +// +// VPHADDW m256 ymm ymm +// VPHADDW ymm ymm ymm +// VPHADDW m128 xmm xmm +// VPHADDW xmm xmm xmm +// Construct and append a VPHADDW instruction to the active function. +// Operates on the global context. +func VPHADDW(mxy, xy, xy1 operand.Op) { ctx.VPHADDW(mxy, xy, xy1) } + +// VPHMINPOSUW: Packed Horizontal Minimum of Unsigned Word Integers. +// +// Forms: +// +// VPHMINPOSUW m128 xmm +// VPHMINPOSUW xmm xmm +// Construct and append a VPHMINPOSUW instruction to the active function. +func (c *Context) VPHMINPOSUW(mx, x operand.Op) { + c.addinstruction(x86.VPHMINPOSUW(mx, x)) +} + +// VPHMINPOSUW: Packed Horizontal Minimum of Unsigned Word Integers. +// +// Forms: +// +// VPHMINPOSUW m128 xmm +// VPHMINPOSUW xmm xmm +// Construct and append a VPHMINPOSUW instruction to the active function. +// Operates on the global context. +func VPHMINPOSUW(mx, x operand.Op) { ctx.VPHMINPOSUW(mx, x) } + +// VPHSUBD: Packed Horizontal Subtract Doubleword Integers. +// +// Forms: +// +// VPHSUBD m256 ymm ymm +// VPHSUBD ymm ymm ymm +// VPHSUBD m128 xmm xmm +// VPHSUBD xmm xmm xmm +// Construct and append a VPHSUBD instruction to the active function. +func (c *Context) VPHSUBD(mxy, xy, xy1 operand.Op) { + c.addinstruction(x86.VPHSUBD(mxy, xy, xy1)) +} + +// VPHSUBD: Packed Horizontal Subtract Doubleword Integers. +// +// Forms: +// +// VPHSUBD m256 ymm ymm +// VPHSUBD ymm ymm ymm +// VPHSUBD m128 xmm xmm +// VPHSUBD xmm xmm xmm +// Construct and append a VPHSUBD instruction to the active function. +// Operates on the global context. +func VPHSUBD(mxy, xy, xy1 operand.Op) { ctx.VPHSUBD(mxy, xy, xy1) } + +// VPHSUBSW: Packed Horizontal Subtract Signed Word Integers with Signed Saturation. +// +// Forms: +// +// VPHSUBSW m256 ymm ymm +// VPHSUBSW ymm ymm ymm +// VPHSUBSW m128 xmm xmm +// VPHSUBSW xmm xmm xmm +// Construct and append a VPHSUBSW instruction to the active function. +func (c *Context) VPHSUBSW(mxy, xy, xy1 operand.Op) { + c.addinstruction(x86.VPHSUBSW(mxy, xy, xy1)) +} + +// VPHSUBSW: Packed Horizontal Subtract Signed Word Integers with Signed Saturation. +// +// Forms: +// +// VPHSUBSW m256 ymm ymm +// VPHSUBSW ymm ymm ymm +// VPHSUBSW m128 xmm xmm +// VPHSUBSW xmm xmm xmm +// Construct and append a VPHSUBSW instruction to the active function. +// Operates on the global context. +func VPHSUBSW(mxy, xy, xy1 operand.Op) { ctx.VPHSUBSW(mxy, xy, xy1) } + +// VPHSUBW: Packed Horizontal Subtract Word Integers. +// +// Forms: +// +// VPHSUBW m256 ymm ymm +// VPHSUBW ymm ymm ymm +// VPHSUBW m128 xmm xmm +// VPHSUBW xmm xmm xmm +// Construct and append a VPHSUBW instruction to the active function. +func (c *Context) VPHSUBW(mxy, xy, xy1 operand.Op) { + c.addinstruction(x86.VPHSUBW(mxy, xy, xy1)) } -// MOVWQZX: Move with Zero-Extend. +// VPHSUBW: Packed Horizontal Subtract Word Integers. // // Forms: // -// MOVWQZX r16 r64 -// MOVWQZX m16 r64 -// Construct and append a MOVWQZX instruction to the active function. +// VPHSUBW m256 ymm ymm +// VPHSUBW ymm ymm ymm +// VPHSUBW m128 xmm xmm +// VPHSUBW xmm xmm xmm +// Construct and append a VPHSUBW instruction to the active function. // Operates on the global context. -func MOVWQZX(mr, r operand.Op) { ctx.MOVWQZX(mr, r) } +func VPHSUBW(mxy, xy, xy1 operand.Op) { ctx.VPHSUBW(mxy, xy, xy1) } -// MPSADBW: Compute Multiple Packed Sums of Absolute Difference. +// VPINSRB: Insert Byte. // // Forms: // -// MPSADBW imm8 xmm xmm -// MPSADBW imm8 m128 xmm -// Construct and append a MPSADBW instruction to the active function. -func (c *Context) MPSADBW(i, mx, x operand.Op) { - if inst, err := x86.MPSADBW(i, mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPINSRB imm8 m8 xmm xmm +// VPINSRB imm8 r32 xmm xmm +// Construct and append a VPINSRB instruction to the active function. +func (c *Context) VPINSRB(i, mr, x, x1 operand.Op) { + c.addinstruction(x86.VPINSRB(i, mr, x, x1)) } -// MPSADBW: Compute Multiple Packed Sums of Absolute Difference. +// VPINSRB: Insert Byte. // // Forms: // -// MPSADBW imm8 xmm xmm -// MPSADBW imm8 m128 xmm -// Construct and append a MPSADBW instruction to the active function. +// VPINSRB imm8 m8 xmm xmm +// VPINSRB imm8 r32 xmm xmm +// Construct and append a VPINSRB instruction to the active function. // Operates on the global context. -func MPSADBW(i, mx, x operand.Op) { ctx.MPSADBW(i, mx, x) } +func VPINSRB(i, mr, x, x1 operand.Op) { ctx.VPINSRB(i, mr, x, x1) } -// MULB: Unsigned Multiply. +// VPINSRD: Insert Doubleword. // // Forms: // -// MULB r8 -// MULB m8 -// Construct and append a MULB instruction to the active function. -func (c *Context) MULB(mr operand.Op) { - if inst, err := x86.MULB(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPINSRD imm8 m32 xmm xmm +// VPINSRD imm8 r32 xmm xmm +// Construct and append a VPINSRD instruction to the active function. +func (c *Context) VPINSRD(i, mr, x, x1 operand.Op) { + c.addinstruction(x86.VPINSRD(i, mr, x, x1)) } -// MULB: Unsigned Multiply. +// VPINSRD: Insert Doubleword. // // Forms: // -// MULB r8 -// MULB m8 -// Construct and append a MULB instruction to the active function. +// VPINSRD imm8 m32 xmm xmm +// VPINSRD imm8 r32 xmm xmm +// Construct and append a VPINSRD instruction to the active function. // Operates on the global context. -func MULB(mr operand.Op) { ctx.MULB(mr) } +func VPINSRD(i, mr, x, x1 operand.Op) { ctx.VPINSRD(i, mr, x, x1) } -// MULL: Unsigned Multiply. +// VPINSRQ: Insert Quadword. // // Forms: // -// MULL r32 -// MULL m32 -// Construct and append a MULL instruction to the active function. -func (c *Context) MULL(mr operand.Op) { - if inst, err := x86.MULL(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPINSRQ imm8 m64 xmm xmm +// VPINSRQ imm8 r64 xmm xmm +// Construct and append a VPINSRQ instruction to the active function. +func (c *Context) VPINSRQ(i, mr, x, x1 operand.Op) { + c.addinstruction(x86.VPINSRQ(i, mr, x, x1)) } -// MULL: Unsigned Multiply. +// VPINSRQ: Insert Quadword. // // Forms: // -// MULL r32 -// MULL m32 -// Construct and append a MULL instruction to the active function. +// VPINSRQ imm8 m64 xmm xmm +// VPINSRQ imm8 r64 xmm xmm +// Construct and append a VPINSRQ instruction to the active function. // Operates on the global context. -func MULL(mr operand.Op) { ctx.MULL(mr) } +func VPINSRQ(i, mr, x, x1 operand.Op) { ctx.VPINSRQ(i, mr, x, x1) } -// MULPD: Multiply Packed Double-Precision Floating-Point Values. +// VPINSRW: Insert Word. // // Forms: // -// MULPD xmm xmm -// MULPD m128 xmm -// Construct and append a MULPD instruction to the active function. -func (c *Context) MULPD(mx, x operand.Op) { - if inst, err := x86.MULPD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPINSRW imm8 m16 xmm xmm +// VPINSRW imm8 r32 xmm xmm +// Construct and append a VPINSRW instruction to the active function. +func (c *Context) VPINSRW(i, mr, x, x1 operand.Op) { + c.addinstruction(x86.VPINSRW(i, mr, x, x1)) } -// MULPD: Multiply Packed Double-Precision Floating-Point Values. +// VPINSRW: Insert Word. // // Forms: // -// MULPD xmm xmm -// MULPD m128 xmm -// Construct and append a MULPD instruction to the active function. +// VPINSRW imm8 m16 xmm xmm +// VPINSRW imm8 r32 xmm xmm +// Construct and append a VPINSRW instruction to the active function. // Operates on the global context. -func MULPD(mx, x operand.Op) { ctx.MULPD(mx, x) } +func VPINSRW(i, mr, x, x1 operand.Op) { ctx.VPINSRW(i, mr, x, x1) } -// MULPS: Multiply Packed Single-Precision Floating-Point Values. +// VPLZCNTD: Count the Number of Leading Zero Bits for Packed Doubleword Values. // // Forms: // -// MULPS xmm xmm -// MULPS m128 xmm -// Construct and append a MULPS instruction to the active function. -func (c *Context) MULPS(mx, x operand.Op) { - if inst, err := x86.MULPS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPLZCNTD m128 k xmm +// VPLZCNTD m128 xmm +// VPLZCNTD m256 k ymm +// VPLZCNTD m256 ymm +// VPLZCNTD xmm k xmm +// VPLZCNTD xmm xmm +// VPLZCNTD ymm k ymm +// VPLZCNTD ymm ymm +// VPLZCNTD m512 k zmm +// VPLZCNTD m512 zmm +// VPLZCNTD zmm k zmm +// VPLZCNTD zmm zmm +// Construct and append a VPLZCNTD instruction to the active function. +func (c *Context) VPLZCNTD(ops ...operand.Op) { + c.addinstruction(x86.VPLZCNTD(ops...)) } -// MULPS: Multiply Packed Single-Precision Floating-Point Values. +// VPLZCNTD: Count the Number of Leading Zero Bits for Packed Doubleword Values. // // Forms: // -// MULPS xmm xmm -// MULPS m128 xmm -// Construct and append a MULPS instruction to the active function. +// VPLZCNTD m128 k xmm +// VPLZCNTD m128 xmm +// VPLZCNTD m256 k ymm +// VPLZCNTD m256 ymm +// VPLZCNTD xmm k xmm +// VPLZCNTD xmm xmm +// VPLZCNTD ymm k ymm +// VPLZCNTD ymm ymm +// VPLZCNTD m512 k zmm +// VPLZCNTD m512 zmm +// VPLZCNTD zmm k zmm +// VPLZCNTD zmm zmm +// Construct and append a VPLZCNTD instruction to the active function. // Operates on the global context. -func MULPS(mx, x operand.Op) { ctx.MULPS(mx, x) } +func VPLZCNTD(ops ...operand.Op) { ctx.VPLZCNTD(ops...) } -// MULQ: Unsigned Multiply. +// VPLZCNTD_BCST: Count the Number of Leading Zero Bits for Packed Doubleword Values (Broadcast). // // Forms: // -// MULQ r64 -// MULQ m64 -// Construct and append a MULQ instruction to the active function. -func (c *Context) MULQ(mr operand.Op) { - if inst, err := x86.MULQ(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPLZCNTD.BCST m32 k xmm +// VPLZCNTD.BCST m32 k ymm +// VPLZCNTD.BCST m32 xmm +// VPLZCNTD.BCST m32 ymm +// VPLZCNTD.BCST m32 k zmm +// VPLZCNTD.BCST m32 zmm +// Construct and append a VPLZCNTD.BCST instruction to the active function. +func (c *Context) VPLZCNTD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPLZCNTD_BCST(ops...)) } -// MULQ: Unsigned Multiply. +// VPLZCNTD_BCST: Count the Number of Leading Zero Bits for Packed Doubleword Values (Broadcast). // // Forms: // -// MULQ r64 -// MULQ m64 -// Construct and append a MULQ instruction to the active function. +// VPLZCNTD.BCST m32 k xmm +// VPLZCNTD.BCST m32 k ymm +// VPLZCNTD.BCST m32 xmm +// VPLZCNTD.BCST m32 ymm +// VPLZCNTD.BCST m32 k zmm +// VPLZCNTD.BCST m32 zmm +// Construct and append a VPLZCNTD.BCST instruction to the active function. // Operates on the global context. -func MULQ(mr operand.Op) { ctx.MULQ(mr) } +func VPLZCNTD_BCST(ops ...operand.Op) { ctx.VPLZCNTD_BCST(ops...) } -// MULSD: Multiply Scalar Double-Precision Floating-Point Values. +// VPLZCNTD_BCST_Z: Count the Number of Leading Zero Bits for Packed Doubleword Values (Broadcast, Zeroing Masking). // // Forms: // -// MULSD xmm xmm -// MULSD m64 xmm -// Construct and append a MULSD instruction to the active function. -func (c *Context) MULSD(mx, x operand.Op) { - if inst, err := x86.MULSD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPLZCNTD.BCST.Z m32 k xmm +// VPLZCNTD.BCST.Z m32 k ymm +// VPLZCNTD.BCST.Z m32 k zmm +// Construct and append a VPLZCNTD.BCST.Z instruction to the active function. +func (c *Context) VPLZCNTD_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VPLZCNTD_BCST_Z(m, k, xyz)) } -// MULSD: Multiply Scalar Double-Precision Floating-Point Values. +// VPLZCNTD_BCST_Z: Count the Number of Leading Zero Bits for Packed Doubleword Values (Broadcast, Zeroing Masking). // // Forms: // -// MULSD xmm xmm -// MULSD m64 xmm -// Construct and append a MULSD instruction to the active function. +// VPLZCNTD.BCST.Z m32 k xmm +// VPLZCNTD.BCST.Z m32 k ymm +// VPLZCNTD.BCST.Z m32 k zmm +// Construct and append a VPLZCNTD.BCST.Z instruction to the active function. // Operates on the global context. -func MULSD(mx, x operand.Op) { ctx.MULSD(mx, x) } +func VPLZCNTD_BCST_Z(m, k, xyz operand.Op) { ctx.VPLZCNTD_BCST_Z(m, k, xyz) } -// MULSS: Multiply Scalar Single-Precision Floating-Point Values. +// VPLZCNTD_Z: Count the Number of Leading Zero Bits for Packed Doubleword Values (Zeroing Masking). // // Forms: // -// MULSS xmm xmm -// MULSS m32 xmm -// Construct and append a MULSS instruction to the active function. -func (c *Context) MULSS(mx, x operand.Op) { - if inst, err := x86.MULSS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPLZCNTD.Z m128 k xmm +// VPLZCNTD.Z m256 k ymm +// VPLZCNTD.Z xmm k xmm +// VPLZCNTD.Z ymm k ymm +// VPLZCNTD.Z m512 k zmm +// VPLZCNTD.Z zmm k zmm +// Construct and append a VPLZCNTD.Z instruction to the active function. +func (c *Context) VPLZCNTD_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPLZCNTD_Z(mxyz, k, xyz)) } -// MULSS: Multiply Scalar Single-Precision Floating-Point Values. +// VPLZCNTD_Z: Count the Number of Leading Zero Bits for Packed Doubleword Values (Zeroing Masking). // // Forms: // -// MULSS xmm xmm -// MULSS m32 xmm -// Construct and append a MULSS instruction to the active function. +// VPLZCNTD.Z m128 k xmm +// VPLZCNTD.Z m256 k ymm +// VPLZCNTD.Z xmm k xmm +// VPLZCNTD.Z ymm k ymm +// VPLZCNTD.Z m512 k zmm +// VPLZCNTD.Z zmm k zmm +// Construct and append a VPLZCNTD.Z instruction to the active function. // Operates on the global context. -func MULSS(mx, x operand.Op) { ctx.MULSS(mx, x) } +func VPLZCNTD_Z(mxyz, k, xyz operand.Op) { ctx.VPLZCNTD_Z(mxyz, k, xyz) } -// MULW: Unsigned Multiply. +// VPLZCNTQ: Count the Number of Leading Zero Bits for Packed Quadword Values. // // Forms: // -// MULW r16 -// MULW m16 -// Construct and append a MULW instruction to the active function. -func (c *Context) MULW(mr operand.Op) { - if inst, err := x86.MULW(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPLZCNTQ m128 k xmm +// VPLZCNTQ m128 xmm +// VPLZCNTQ m256 k ymm +// VPLZCNTQ m256 ymm +// VPLZCNTQ xmm k xmm +// VPLZCNTQ xmm xmm +// VPLZCNTQ ymm k ymm +// VPLZCNTQ ymm ymm +// VPLZCNTQ m512 k zmm +// VPLZCNTQ m512 zmm +// VPLZCNTQ zmm k zmm +// VPLZCNTQ zmm zmm +// Construct and append a VPLZCNTQ instruction to the active function. +func (c *Context) VPLZCNTQ(ops ...operand.Op) { + c.addinstruction(x86.VPLZCNTQ(ops...)) } -// MULW: Unsigned Multiply. +// VPLZCNTQ: Count the Number of Leading Zero Bits for Packed Quadword Values. // // Forms: // -// MULW r16 -// MULW m16 -// Construct and append a MULW instruction to the active function. +// VPLZCNTQ m128 k xmm +// VPLZCNTQ m128 xmm +// VPLZCNTQ m256 k ymm +// VPLZCNTQ m256 ymm +// VPLZCNTQ xmm k xmm +// VPLZCNTQ xmm xmm +// VPLZCNTQ ymm k ymm +// VPLZCNTQ ymm ymm +// VPLZCNTQ m512 k zmm +// VPLZCNTQ m512 zmm +// VPLZCNTQ zmm k zmm +// VPLZCNTQ zmm zmm +// Construct and append a VPLZCNTQ instruction to the active function. // Operates on the global context. -func MULW(mr operand.Op) { ctx.MULW(mr) } +func VPLZCNTQ(ops ...operand.Op) { ctx.VPLZCNTQ(ops...) } -// MULXL: Unsigned Multiply Without Affecting Flags. +// VPLZCNTQ_BCST: Count the Number of Leading Zero Bits for Packed Quadword Values (Broadcast). // // Forms: // -// MULXL r32 r32 r32 -// MULXL m32 r32 r32 -// Construct and append a MULXL instruction to the active function. -func (c *Context) MULXL(mr, r, r1 operand.Op) { - if inst, err := x86.MULXL(mr, r, r1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPLZCNTQ.BCST m64 k xmm +// VPLZCNTQ.BCST m64 k ymm +// VPLZCNTQ.BCST m64 xmm +// VPLZCNTQ.BCST m64 ymm +// VPLZCNTQ.BCST m64 k zmm +// VPLZCNTQ.BCST m64 zmm +// Construct and append a VPLZCNTQ.BCST instruction to the active function. +func (c *Context) VPLZCNTQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPLZCNTQ_BCST(ops...)) } -// MULXL: Unsigned Multiply Without Affecting Flags. +// VPLZCNTQ_BCST: Count the Number of Leading Zero Bits for Packed Quadword Values (Broadcast). // // Forms: // -// MULXL r32 r32 r32 -// MULXL m32 r32 r32 -// Construct and append a MULXL instruction to the active function. +// VPLZCNTQ.BCST m64 k xmm +// VPLZCNTQ.BCST m64 k ymm +// VPLZCNTQ.BCST m64 xmm +// VPLZCNTQ.BCST m64 ymm +// VPLZCNTQ.BCST m64 k zmm +// VPLZCNTQ.BCST m64 zmm +// Construct and append a VPLZCNTQ.BCST instruction to the active function. // Operates on the global context. -func MULXL(mr, r, r1 operand.Op) { ctx.MULXL(mr, r, r1) } +func VPLZCNTQ_BCST(ops ...operand.Op) { ctx.VPLZCNTQ_BCST(ops...) } -// MULXQ: Unsigned Multiply Without Affecting Flags. +// VPLZCNTQ_BCST_Z: Count the Number of Leading Zero Bits for Packed Quadword Values (Broadcast, Zeroing Masking). // // Forms: // -// MULXQ r64 r64 r64 -// MULXQ m64 r64 r64 -// Construct and append a MULXQ instruction to the active function. -func (c *Context) MULXQ(mr, r, r1 operand.Op) { - if inst, err := x86.MULXQ(mr, r, r1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPLZCNTQ.BCST.Z m64 k xmm +// VPLZCNTQ.BCST.Z m64 k ymm +// VPLZCNTQ.BCST.Z m64 k zmm +// Construct and append a VPLZCNTQ.BCST.Z instruction to the active function. +func (c *Context) VPLZCNTQ_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VPLZCNTQ_BCST_Z(m, k, xyz)) } -// MULXQ: Unsigned Multiply Without Affecting Flags. +// VPLZCNTQ_BCST_Z: Count the Number of Leading Zero Bits for Packed Quadword Values (Broadcast, Zeroing Masking). // // Forms: // -// MULXQ r64 r64 r64 -// MULXQ m64 r64 r64 -// Construct and append a MULXQ instruction to the active function. +// VPLZCNTQ.BCST.Z m64 k xmm +// VPLZCNTQ.BCST.Z m64 k ymm +// VPLZCNTQ.BCST.Z m64 k zmm +// Construct and append a VPLZCNTQ.BCST.Z instruction to the active function. +// Operates on the global context. +func VPLZCNTQ_BCST_Z(m, k, xyz operand.Op) { ctx.VPLZCNTQ_BCST_Z(m, k, xyz) } + +// VPLZCNTQ_Z: Count the Number of Leading Zero Bits for Packed Quadword Values (Zeroing Masking). +// +// Forms: +// +// VPLZCNTQ.Z m128 k xmm +// VPLZCNTQ.Z m256 k ymm +// VPLZCNTQ.Z xmm k xmm +// VPLZCNTQ.Z ymm k ymm +// VPLZCNTQ.Z m512 k zmm +// VPLZCNTQ.Z zmm k zmm +// Construct and append a VPLZCNTQ.Z instruction to the active function. +func (c *Context) VPLZCNTQ_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPLZCNTQ_Z(mxyz, k, xyz)) +} + +// VPLZCNTQ_Z: Count the Number of Leading Zero Bits for Packed Quadword Values (Zeroing Masking). +// +// Forms: +// +// VPLZCNTQ.Z m128 k xmm +// VPLZCNTQ.Z m256 k ymm +// VPLZCNTQ.Z xmm k xmm +// VPLZCNTQ.Z ymm k ymm +// VPLZCNTQ.Z m512 k zmm +// VPLZCNTQ.Z zmm k zmm +// Construct and append a VPLZCNTQ.Z instruction to the active function. +// Operates on the global context. +func VPLZCNTQ_Z(mxyz, k, xyz operand.Op) { ctx.VPLZCNTQ_Z(mxyz, k, xyz) } + +// VPMADD52HUQ: Packed Multiply of Unsigned 52-bit Unsigned Integers and Add High 52-bit Products to Quadword Accumulators. +// +// Forms: +// +// VPMADD52HUQ m128 xmm k xmm +// VPMADD52HUQ m128 xmm xmm +// VPMADD52HUQ m256 ymm k ymm +// VPMADD52HUQ m256 ymm ymm +// VPMADD52HUQ xmm xmm k xmm +// VPMADD52HUQ xmm xmm xmm +// VPMADD52HUQ ymm ymm k ymm +// VPMADD52HUQ ymm ymm ymm +// VPMADD52HUQ m512 zmm k zmm +// VPMADD52HUQ m512 zmm zmm +// VPMADD52HUQ zmm zmm k zmm +// VPMADD52HUQ zmm zmm zmm +// Construct and append a VPMADD52HUQ instruction to the active function. +func (c *Context) VPMADD52HUQ(ops ...operand.Op) { + c.addinstruction(x86.VPMADD52HUQ(ops...)) +} + +// VPMADD52HUQ: Packed Multiply of Unsigned 52-bit Unsigned Integers and Add High 52-bit Products to Quadword Accumulators. +// +// Forms: +// +// VPMADD52HUQ m128 xmm k xmm +// VPMADD52HUQ m128 xmm xmm +// VPMADD52HUQ m256 ymm k ymm +// VPMADD52HUQ m256 ymm ymm +// VPMADD52HUQ xmm xmm k xmm +// VPMADD52HUQ xmm xmm xmm +// VPMADD52HUQ ymm ymm k ymm +// VPMADD52HUQ ymm ymm ymm +// VPMADD52HUQ m512 zmm k zmm +// VPMADD52HUQ m512 zmm zmm +// VPMADD52HUQ zmm zmm k zmm +// VPMADD52HUQ zmm zmm zmm +// Construct and append a VPMADD52HUQ instruction to the active function. +// Operates on the global context. +func VPMADD52HUQ(ops ...operand.Op) { ctx.VPMADD52HUQ(ops...) } + +// VPMADD52HUQ_BCST: Packed Multiply of Unsigned 52-bit Unsigned Integers and Add High 52-bit Products to Quadword Accumulators (Broadcast). +// +// Forms: +// +// VPMADD52HUQ.BCST m64 xmm k xmm +// VPMADD52HUQ.BCST m64 xmm xmm +// VPMADD52HUQ.BCST m64 ymm k ymm +// VPMADD52HUQ.BCST m64 ymm ymm +// VPMADD52HUQ.BCST m64 zmm k zmm +// VPMADD52HUQ.BCST m64 zmm zmm +// Construct and append a VPMADD52HUQ.BCST instruction to the active function. +func (c *Context) VPMADD52HUQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPMADD52HUQ_BCST(ops...)) +} + +// VPMADD52HUQ_BCST: Packed Multiply of Unsigned 52-bit Unsigned Integers and Add High 52-bit Products to Quadword Accumulators (Broadcast). +// +// Forms: +// +// VPMADD52HUQ.BCST m64 xmm k xmm +// VPMADD52HUQ.BCST m64 xmm xmm +// VPMADD52HUQ.BCST m64 ymm k ymm +// VPMADD52HUQ.BCST m64 ymm ymm +// VPMADD52HUQ.BCST m64 zmm k zmm +// VPMADD52HUQ.BCST m64 zmm zmm +// Construct and append a VPMADD52HUQ.BCST instruction to the active function. +// Operates on the global context. +func VPMADD52HUQ_BCST(ops ...operand.Op) { ctx.VPMADD52HUQ_BCST(ops...) } + +// VPMADD52HUQ_BCST_Z: Packed Multiply of Unsigned 52-bit Unsigned Integers and Add High 52-bit Products to Quadword Accumulators (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPMADD52HUQ.BCST.Z m64 xmm k xmm +// VPMADD52HUQ.BCST.Z m64 ymm k ymm +// VPMADD52HUQ.BCST.Z m64 zmm k zmm +// Construct and append a VPMADD52HUQ.BCST.Z instruction to the active function. +func (c *Context) VPMADD52HUQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMADD52HUQ_BCST_Z(m, xyz, k, xyz1)) +} + +// VPMADD52HUQ_BCST_Z: Packed Multiply of Unsigned 52-bit Unsigned Integers and Add High 52-bit Products to Quadword Accumulators (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPMADD52HUQ.BCST.Z m64 xmm k xmm +// VPMADD52HUQ.BCST.Z m64 ymm k ymm +// VPMADD52HUQ.BCST.Z m64 zmm k zmm +// Construct and append a VPMADD52HUQ.BCST.Z instruction to the active function. +// Operates on the global context. +func VPMADD52HUQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPMADD52HUQ_BCST_Z(m, xyz, k, xyz1) } + +// VPMADD52HUQ_Z: Packed Multiply of Unsigned 52-bit Unsigned Integers and Add High 52-bit Products to Quadword Accumulators (Zeroing Masking). +// +// Forms: +// +// VPMADD52HUQ.Z m128 xmm k xmm +// VPMADD52HUQ.Z m256 ymm k ymm +// VPMADD52HUQ.Z xmm xmm k xmm +// VPMADD52HUQ.Z ymm ymm k ymm +// VPMADD52HUQ.Z m512 zmm k zmm +// VPMADD52HUQ.Z zmm zmm k zmm +// Construct and append a VPMADD52HUQ.Z instruction to the active function. +func (c *Context) VPMADD52HUQ_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMADD52HUQ_Z(mxyz, xyz, k, xyz1)) +} + +// VPMADD52HUQ_Z: Packed Multiply of Unsigned 52-bit Unsigned Integers and Add High 52-bit Products to Quadword Accumulators (Zeroing Masking). +// +// Forms: +// +// VPMADD52HUQ.Z m128 xmm k xmm +// VPMADD52HUQ.Z m256 ymm k ymm +// VPMADD52HUQ.Z xmm xmm k xmm +// VPMADD52HUQ.Z ymm ymm k ymm +// VPMADD52HUQ.Z m512 zmm k zmm +// VPMADD52HUQ.Z zmm zmm k zmm +// Construct and append a VPMADD52HUQ.Z instruction to the active function. +// Operates on the global context. +func VPMADD52HUQ_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPMADD52HUQ_Z(mxyz, xyz, k, xyz1) } + +// VPMADD52LUQ: Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit Products to Quadword Accumulators. +// +// Forms: +// +// VPMADD52LUQ m128 xmm k xmm +// VPMADD52LUQ m128 xmm xmm +// VPMADD52LUQ m256 ymm k ymm +// VPMADD52LUQ m256 ymm ymm +// VPMADD52LUQ xmm xmm k xmm +// VPMADD52LUQ xmm xmm xmm +// VPMADD52LUQ ymm ymm k ymm +// VPMADD52LUQ ymm ymm ymm +// VPMADD52LUQ m512 zmm k zmm +// VPMADD52LUQ m512 zmm zmm +// VPMADD52LUQ zmm zmm k zmm +// VPMADD52LUQ zmm zmm zmm +// Construct and append a VPMADD52LUQ instruction to the active function. +func (c *Context) VPMADD52LUQ(ops ...operand.Op) { + c.addinstruction(x86.VPMADD52LUQ(ops...)) +} + +// VPMADD52LUQ: Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit Products to Quadword Accumulators. +// +// Forms: +// +// VPMADD52LUQ m128 xmm k xmm +// VPMADD52LUQ m128 xmm xmm +// VPMADD52LUQ m256 ymm k ymm +// VPMADD52LUQ m256 ymm ymm +// VPMADD52LUQ xmm xmm k xmm +// VPMADD52LUQ xmm xmm xmm +// VPMADD52LUQ ymm ymm k ymm +// VPMADD52LUQ ymm ymm ymm +// VPMADD52LUQ m512 zmm k zmm +// VPMADD52LUQ m512 zmm zmm +// VPMADD52LUQ zmm zmm k zmm +// VPMADD52LUQ zmm zmm zmm +// Construct and append a VPMADD52LUQ instruction to the active function. +// Operates on the global context. +func VPMADD52LUQ(ops ...operand.Op) { ctx.VPMADD52LUQ(ops...) } + +// VPMADD52LUQ_BCST: Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit Products to Quadword Accumulators (Broadcast). +// +// Forms: +// +// VPMADD52LUQ.BCST m64 xmm k xmm +// VPMADD52LUQ.BCST m64 xmm xmm +// VPMADD52LUQ.BCST m64 ymm k ymm +// VPMADD52LUQ.BCST m64 ymm ymm +// VPMADD52LUQ.BCST m64 zmm k zmm +// VPMADD52LUQ.BCST m64 zmm zmm +// Construct and append a VPMADD52LUQ.BCST instruction to the active function. +func (c *Context) VPMADD52LUQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPMADD52LUQ_BCST(ops...)) +} + +// VPMADD52LUQ_BCST: Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit Products to Quadword Accumulators (Broadcast). +// +// Forms: +// +// VPMADD52LUQ.BCST m64 xmm k xmm +// VPMADD52LUQ.BCST m64 xmm xmm +// VPMADD52LUQ.BCST m64 ymm k ymm +// VPMADD52LUQ.BCST m64 ymm ymm +// VPMADD52LUQ.BCST m64 zmm k zmm +// VPMADD52LUQ.BCST m64 zmm zmm +// Construct and append a VPMADD52LUQ.BCST instruction to the active function. +// Operates on the global context. +func VPMADD52LUQ_BCST(ops ...operand.Op) { ctx.VPMADD52LUQ_BCST(ops...) } + +// VPMADD52LUQ_BCST_Z: Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit Products to Quadword Accumulators (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPMADD52LUQ.BCST.Z m64 xmm k xmm +// VPMADD52LUQ.BCST.Z m64 ymm k ymm +// VPMADD52LUQ.BCST.Z m64 zmm k zmm +// Construct and append a VPMADD52LUQ.BCST.Z instruction to the active function. +func (c *Context) VPMADD52LUQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMADD52LUQ_BCST_Z(m, xyz, k, xyz1)) +} + +// VPMADD52LUQ_BCST_Z: Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit Products to Quadword Accumulators (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPMADD52LUQ.BCST.Z m64 xmm k xmm +// VPMADD52LUQ.BCST.Z m64 ymm k ymm +// VPMADD52LUQ.BCST.Z m64 zmm k zmm +// Construct and append a VPMADD52LUQ.BCST.Z instruction to the active function. +// Operates on the global context. +func VPMADD52LUQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPMADD52LUQ_BCST_Z(m, xyz, k, xyz1) } + +// VPMADD52LUQ_Z: Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit Products to Quadword Accumulators (Zeroing Masking). +// +// Forms: +// +// VPMADD52LUQ.Z m128 xmm k xmm +// VPMADD52LUQ.Z m256 ymm k ymm +// VPMADD52LUQ.Z xmm xmm k xmm +// VPMADD52LUQ.Z ymm ymm k ymm +// VPMADD52LUQ.Z m512 zmm k zmm +// VPMADD52LUQ.Z zmm zmm k zmm +// Construct and append a VPMADD52LUQ.Z instruction to the active function. +func (c *Context) VPMADD52LUQ_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMADD52LUQ_Z(mxyz, xyz, k, xyz1)) +} + +// VPMADD52LUQ_Z: Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit Products to Quadword Accumulators (Zeroing Masking). +// +// Forms: +// +// VPMADD52LUQ.Z m128 xmm k xmm +// VPMADD52LUQ.Z m256 ymm k ymm +// VPMADD52LUQ.Z xmm xmm k xmm +// VPMADD52LUQ.Z ymm ymm k ymm +// VPMADD52LUQ.Z m512 zmm k zmm +// VPMADD52LUQ.Z zmm zmm k zmm +// Construct and append a VPMADD52LUQ.Z instruction to the active function. +// Operates on the global context. +func VPMADD52LUQ_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPMADD52LUQ_Z(mxyz, xyz, k, xyz1) } + +// VPMADDUBSW: Multiply and Add Packed Signed and Unsigned Byte Integers. +// +// Forms: +// +// VPMADDUBSW m256 ymm ymm +// VPMADDUBSW ymm ymm ymm +// VPMADDUBSW m128 xmm xmm +// VPMADDUBSW xmm xmm xmm +// VPMADDUBSW m128 xmm k xmm +// VPMADDUBSW m256 ymm k ymm +// VPMADDUBSW xmm xmm k xmm +// VPMADDUBSW ymm ymm k ymm +// VPMADDUBSW m512 zmm k zmm +// VPMADDUBSW m512 zmm zmm +// VPMADDUBSW zmm zmm k zmm +// VPMADDUBSW zmm zmm zmm +// Construct and append a VPMADDUBSW instruction to the active function. +func (c *Context) VPMADDUBSW(ops ...operand.Op) { + c.addinstruction(x86.VPMADDUBSW(ops...)) +} + +// VPMADDUBSW: Multiply and Add Packed Signed and Unsigned Byte Integers. +// +// Forms: +// +// VPMADDUBSW m256 ymm ymm +// VPMADDUBSW ymm ymm ymm +// VPMADDUBSW m128 xmm xmm +// VPMADDUBSW xmm xmm xmm +// VPMADDUBSW m128 xmm k xmm +// VPMADDUBSW m256 ymm k ymm +// VPMADDUBSW xmm xmm k xmm +// VPMADDUBSW ymm ymm k ymm +// VPMADDUBSW m512 zmm k zmm +// VPMADDUBSW m512 zmm zmm +// VPMADDUBSW zmm zmm k zmm +// VPMADDUBSW zmm zmm zmm +// Construct and append a VPMADDUBSW instruction to the active function. +// Operates on the global context. +func VPMADDUBSW(ops ...operand.Op) { ctx.VPMADDUBSW(ops...) } + +// VPMADDUBSW_Z: Multiply and Add Packed Signed and Unsigned Byte Integers (Zeroing Masking). +// +// Forms: +// +// VPMADDUBSW.Z m128 xmm k xmm +// VPMADDUBSW.Z m256 ymm k ymm +// VPMADDUBSW.Z xmm xmm k xmm +// VPMADDUBSW.Z ymm ymm k ymm +// VPMADDUBSW.Z m512 zmm k zmm +// VPMADDUBSW.Z zmm zmm k zmm +// Construct and append a VPMADDUBSW.Z instruction to the active function. +func (c *Context) VPMADDUBSW_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMADDUBSW_Z(mxyz, xyz, k, xyz1)) +} + +// VPMADDUBSW_Z: Multiply and Add Packed Signed and Unsigned Byte Integers (Zeroing Masking). +// +// Forms: +// +// VPMADDUBSW.Z m128 xmm k xmm +// VPMADDUBSW.Z m256 ymm k ymm +// VPMADDUBSW.Z xmm xmm k xmm +// VPMADDUBSW.Z ymm ymm k ymm +// VPMADDUBSW.Z m512 zmm k zmm +// VPMADDUBSW.Z zmm zmm k zmm +// Construct and append a VPMADDUBSW.Z instruction to the active function. +// Operates on the global context. +func VPMADDUBSW_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPMADDUBSW_Z(mxyz, xyz, k, xyz1) } + +// VPMADDWD: Multiply and Add Packed Signed Word Integers. +// +// Forms: +// +// VPMADDWD m256 ymm ymm +// VPMADDWD ymm ymm ymm +// VPMADDWD m128 xmm xmm +// VPMADDWD xmm xmm xmm +// VPMADDWD m128 xmm k xmm +// VPMADDWD m256 ymm k ymm +// VPMADDWD xmm xmm k xmm +// VPMADDWD ymm ymm k ymm +// VPMADDWD m512 zmm k zmm +// VPMADDWD m512 zmm zmm +// VPMADDWD zmm zmm k zmm +// VPMADDWD zmm zmm zmm +// Construct and append a VPMADDWD instruction to the active function. +func (c *Context) VPMADDWD(ops ...operand.Op) { + c.addinstruction(x86.VPMADDWD(ops...)) +} + +// VPMADDWD: Multiply and Add Packed Signed Word Integers. +// +// Forms: +// +// VPMADDWD m256 ymm ymm +// VPMADDWD ymm ymm ymm +// VPMADDWD m128 xmm xmm +// VPMADDWD xmm xmm xmm +// VPMADDWD m128 xmm k xmm +// VPMADDWD m256 ymm k ymm +// VPMADDWD xmm xmm k xmm +// VPMADDWD ymm ymm k ymm +// VPMADDWD m512 zmm k zmm +// VPMADDWD m512 zmm zmm +// VPMADDWD zmm zmm k zmm +// VPMADDWD zmm zmm zmm +// Construct and append a VPMADDWD instruction to the active function. +// Operates on the global context. +func VPMADDWD(ops ...operand.Op) { ctx.VPMADDWD(ops...) } + +// VPMADDWD_Z: Multiply and Add Packed Signed Word Integers (Zeroing Masking). +// +// Forms: +// +// VPMADDWD.Z m128 xmm k xmm +// VPMADDWD.Z m256 ymm k ymm +// VPMADDWD.Z xmm xmm k xmm +// VPMADDWD.Z ymm ymm k ymm +// VPMADDWD.Z m512 zmm k zmm +// VPMADDWD.Z zmm zmm k zmm +// Construct and append a VPMADDWD.Z instruction to the active function. +func (c *Context) VPMADDWD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMADDWD_Z(mxyz, xyz, k, xyz1)) +} + +// VPMADDWD_Z: Multiply and Add Packed Signed Word Integers (Zeroing Masking). +// +// Forms: +// +// VPMADDWD.Z m128 xmm k xmm +// VPMADDWD.Z m256 ymm k ymm +// VPMADDWD.Z xmm xmm k xmm +// VPMADDWD.Z ymm ymm k ymm +// VPMADDWD.Z m512 zmm k zmm +// VPMADDWD.Z zmm zmm k zmm +// Construct and append a VPMADDWD.Z instruction to the active function. +// Operates on the global context. +func VPMADDWD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPMADDWD_Z(mxyz, xyz, k, xyz1) } + +// VPMASKMOVD: Conditional Move Packed Doubleword Integers. +// +// Forms: +// +// VPMASKMOVD m128 xmm xmm +// VPMASKMOVD m256 ymm ymm +// VPMASKMOVD xmm xmm m128 +// VPMASKMOVD ymm ymm m256 +// Construct and append a VPMASKMOVD instruction to the active function. +func (c *Context) VPMASKMOVD(mxy, xy, mxy1 operand.Op) { + c.addinstruction(x86.VPMASKMOVD(mxy, xy, mxy1)) +} + +// VPMASKMOVD: Conditional Move Packed Doubleword Integers. +// +// Forms: +// +// VPMASKMOVD m128 xmm xmm +// VPMASKMOVD m256 ymm ymm +// VPMASKMOVD xmm xmm m128 +// VPMASKMOVD ymm ymm m256 +// Construct and append a VPMASKMOVD instruction to the active function. +// Operates on the global context. +func VPMASKMOVD(mxy, xy, mxy1 operand.Op) { ctx.VPMASKMOVD(mxy, xy, mxy1) } + +// VPMASKMOVQ: Conditional Move Packed Quadword Integers. +// +// Forms: +// +// VPMASKMOVQ m128 xmm xmm +// VPMASKMOVQ m256 ymm ymm +// VPMASKMOVQ xmm xmm m128 +// VPMASKMOVQ ymm ymm m256 +// Construct and append a VPMASKMOVQ instruction to the active function. +func (c *Context) VPMASKMOVQ(mxy, xy, mxy1 operand.Op) { + c.addinstruction(x86.VPMASKMOVQ(mxy, xy, mxy1)) +} + +// VPMASKMOVQ: Conditional Move Packed Quadword Integers. +// +// Forms: +// +// VPMASKMOVQ m128 xmm xmm +// VPMASKMOVQ m256 ymm ymm +// VPMASKMOVQ xmm xmm m128 +// VPMASKMOVQ ymm ymm m256 +// Construct and append a VPMASKMOVQ instruction to the active function. +// Operates on the global context. +func VPMASKMOVQ(mxy, xy, mxy1 operand.Op) { ctx.VPMASKMOVQ(mxy, xy, mxy1) } + +// VPMAXSB: Maximum of Packed Signed Byte Integers. +// +// Forms: +// +// VPMAXSB m256 ymm ymm +// VPMAXSB ymm ymm ymm +// VPMAXSB m128 xmm xmm +// VPMAXSB xmm xmm xmm +// VPMAXSB m128 xmm k xmm +// VPMAXSB m256 ymm k ymm +// VPMAXSB xmm xmm k xmm +// VPMAXSB ymm ymm k ymm +// VPMAXSB m512 zmm k zmm +// VPMAXSB m512 zmm zmm +// VPMAXSB zmm zmm k zmm +// VPMAXSB zmm zmm zmm +// Construct and append a VPMAXSB instruction to the active function. +func (c *Context) VPMAXSB(ops ...operand.Op) { + c.addinstruction(x86.VPMAXSB(ops...)) +} + +// VPMAXSB: Maximum of Packed Signed Byte Integers. +// +// Forms: +// +// VPMAXSB m256 ymm ymm +// VPMAXSB ymm ymm ymm +// VPMAXSB m128 xmm xmm +// VPMAXSB xmm xmm xmm +// VPMAXSB m128 xmm k xmm +// VPMAXSB m256 ymm k ymm +// VPMAXSB xmm xmm k xmm +// VPMAXSB ymm ymm k ymm +// VPMAXSB m512 zmm k zmm +// VPMAXSB m512 zmm zmm +// VPMAXSB zmm zmm k zmm +// VPMAXSB zmm zmm zmm +// Construct and append a VPMAXSB instruction to the active function. +// Operates on the global context. +func VPMAXSB(ops ...operand.Op) { ctx.VPMAXSB(ops...) } + +// VPMAXSB_Z: Maximum of Packed Signed Byte Integers (Zeroing Masking). +// +// Forms: +// +// VPMAXSB.Z m128 xmm k xmm +// VPMAXSB.Z m256 ymm k ymm +// VPMAXSB.Z xmm xmm k xmm +// VPMAXSB.Z ymm ymm k ymm +// VPMAXSB.Z m512 zmm k zmm +// VPMAXSB.Z zmm zmm k zmm +// Construct and append a VPMAXSB.Z instruction to the active function. +func (c *Context) VPMAXSB_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMAXSB_Z(mxyz, xyz, k, xyz1)) +} + +// VPMAXSB_Z: Maximum of Packed Signed Byte Integers (Zeroing Masking). +// +// Forms: +// +// VPMAXSB.Z m128 xmm k xmm +// VPMAXSB.Z m256 ymm k ymm +// VPMAXSB.Z xmm xmm k xmm +// VPMAXSB.Z ymm ymm k ymm +// VPMAXSB.Z m512 zmm k zmm +// VPMAXSB.Z zmm zmm k zmm +// Construct and append a VPMAXSB.Z instruction to the active function. +// Operates on the global context. +func VPMAXSB_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPMAXSB_Z(mxyz, xyz, k, xyz1) } + +// VPMAXSD: Maximum of Packed Signed Doubleword Integers. +// +// Forms: +// +// VPMAXSD m256 ymm ymm +// VPMAXSD ymm ymm ymm +// VPMAXSD m128 xmm xmm +// VPMAXSD xmm xmm xmm +// VPMAXSD m128 xmm k xmm +// VPMAXSD m256 ymm k ymm +// VPMAXSD xmm xmm k xmm +// VPMAXSD ymm ymm k ymm +// VPMAXSD m512 zmm k zmm +// VPMAXSD m512 zmm zmm +// VPMAXSD zmm zmm k zmm +// VPMAXSD zmm zmm zmm +// Construct and append a VPMAXSD instruction to the active function. +func (c *Context) VPMAXSD(ops ...operand.Op) { + c.addinstruction(x86.VPMAXSD(ops...)) +} + +// VPMAXSD: Maximum of Packed Signed Doubleword Integers. +// +// Forms: +// +// VPMAXSD m256 ymm ymm +// VPMAXSD ymm ymm ymm +// VPMAXSD m128 xmm xmm +// VPMAXSD xmm xmm xmm +// VPMAXSD m128 xmm k xmm +// VPMAXSD m256 ymm k ymm +// VPMAXSD xmm xmm k xmm +// VPMAXSD ymm ymm k ymm +// VPMAXSD m512 zmm k zmm +// VPMAXSD m512 zmm zmm +// VPMAXSD zmm zmm k zmm +// VPMAXSD zmm zmm zmm +// Construct and append a VPMAXSD instruction to the active function. +// Operates on the global context. +func VPMAXSD(ops ...operand.Op) { ctx.VPMAXSD(ops...) } + +// VPMAXSD_BCST: Maximum of Packed Signed Doubleword Integers (Broadcast). +// +// Forms: +// +// VPMAXSD.BCST m32 xmm k xmm +// VPMAXSD.BCST m32 xmm xmm +// VPMAXSD.BCST m32 ymm k ymm +// VPMAXSD.BCST m32 ymm ymm +// VPMAXSD.BCST m32 zmm k zmm +// VPMAXSD.BCST m32 zmm zmm +// Construct and append a VPMAXSD.BCST instruction to the active function. +func (c *Context) VPMAXSD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPMAXSD_BCST(ops...)) +} + +// VPMAXSD_BCST: Maximum of Packed Signed Doubleword Integers (Broadcast). +// +// Forms: +// +// VPMAXSD.BCST m32 xmm k xmm +// VPMAXSD.BCST m32 xmm xmm +// VPMAXSD.BCST m32 ymm k ymm +// VPMAXSD.BCST m32 ymm ymm +// VPMAXSD.BCST m32 zmm k zmm +// VPMAXSD.BCST m32 zmm zmm +// Construct and append a VPMAXSD.BCST instruction to the active function. +// Operates on the global context. +func VPMAXSD_BCST(ops ...operand.Op) { ctx.VPMAXSD_BCST(ops...) } + +// VPMAXSD_BCST_Z: Maximum of Packed Signed Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPMAXSD.BCST.Z m32 xmm k xmm +// VPMAXSD.BCST.Z m32 ymm k ymm +// VPMAXSD.BCST.Z m32 zmm k zmm +// Construct and append a VPMAXSD.BCST.Z instruction to the active function. +func (c *Context) VPMAXSD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMAXSD_BCST_Z(m, xyz, k, xyz1)) +} + +// VPMAXSD_BCST_Z: Maximum of Packed Signed Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPMAXSD.BCST.Z m32 xmm k xmm +// VPMAXSD.BCST.Z m32 ymm k ymm +// VPMAXSD.BCST.Z m32 zmm k zmm +// Construct and append a VPMAXSD.BCST.Z instruction to the active function. +// Operates on the global context. +func VPMAXSD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPMAXSD_BCST_Z(m, xyz, k, xyz1) } + +// VPMAXSD_Z: Maximum of Packed Signed Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VPMAXSD.Z m128 xmm k xmm +// VPMAXSD.Z m256 ymm k ymm +// VPMAXSD.Z xmm xmm k xmm +// VPMAXSD.Z ymm ymm k ymm +// VPMAXSD.Z m512 zmm k zmm +// VPMAXSD.Z zmm zmm k zmm +// Construct and append a VPMAXSD.Z instruction to the active function. +func (c *Context) VPMAXSD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMAXSD_Z(mxyz, xyz, k, xyz1)) +} + +// VPMAXSD_Z: Maximum of Packed Signed Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VPMAXSD.Z m128 xmm k xmm +// VPMAXSD.Z m256 ymm k ymm +// VPMAXSD.Z xmm xmm k xmm +// VPMAXSD.Z ymm ymm k ymm +// VPMAXSD.Z m512 zmm k zmm +// VPMAXSD.Z zmm zmm k zmm +// Construct and append a VPMAXSD.Z instruction to the active function. +// Operates on the global context. +func VPMAXSD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPMAXSD_Z(mxyz, xyz, k, xyz1) } + +// VPMAXSQ: Maximum of Packed Signed Quadword Integers. +// +// Forms: +// +// VPMAXSQ m128 xmm k xmm +// VPMAXSQ m128 xmm xmm +// VPMAXSQ m256 ymm k ymm +// VPMAXSQ m256 ymm ymm +// VPMAXSQ xmm xmm k xmm +// VPMAXSQ xmm xmm xmm +// VPMAXSQ ymm ymm k ymm +// VPMAXSQ ymm ymm ymm +// VPMAXSQ m512 zmm k zmm +// VPMAXSQ m512 zmm zmm +// VPMAXSQ zmm zmm k zmm +// VPMAXSQ zmm zmm zmm +// Construct and append a VPMAXSQ instruction to the active function. +func (c *Context) VPMAXSQ(ops ...operand.Op) { + c.addinstruction(x86.VPMAXSQ(ops...)) +} + +// VPMAXSQ: Maximum of Packed Signed Quadword Integers. +// +// Forms: +// +// VPMAXSQ m128 xmm k xmm +// VPMAXSQ m128 xmm xmm +// VPMAXSQ m256 ymm k ymm +// VPMAXSQ m256 ymm ymm +// VPMAXSQ xmm xmm k xmm +// VPMAXSQ xmm xmm xmm +// VPMAXSQ ymm ymm k ymm +// VPMAXSQ ymm ymm ymm +// VPMAXSQ m512 zmm k zmm +// VPMAXSQ m512 zmm zmm +// VPMAXSQ zmm zmm k zmm +// VPMAXSQ zmm zmm zmm +// Construct and append a VPMAXSQ instruction to the active function. +// Operates on the global context. +func VPMAXSQ(ops ...operand.Op) { ctx.VPMAXSQ(ops...) } + +// VPMAXSQ_BCST: Maximum of Packed Signed Quadword Integers (Broadcast). +// +// Forms: +// +// VPMAXSQ.BCST m64 xmm k xmm +// VPMAXSQ.BCST m64 xmm xmm +// VPMAXSQ.BCST m64 ymm k ymm +// VPMAXSQ.BCST m64 ymm ymm +// VPMAXSQ.BCST m64 zmm k zmm +// VPMAXSQ.BCST m64 zmm zmm +// Construct and append a VPMAXSQ.BCST instruction to the active function. +func (c *Context) VPMAXSQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPMAXSQ_BCST(ops...)) +} + +// VPMAXSQ_BCST: Maximum of Packed Signed Quadword Integers (Broadcast). +// +// Forms: +// +// VPMAXSQ.BCST m64 xmm k xmm +// VPMAXSQ.BCST m64 xmm xmm +// VPMAXSQ.BCST m64 ymm k ymm +// VPMAXSQ.BCST m64 ymm ymm +// VPMAXSQ.BCST m64 zmm k zmm +// VPMAXSQ.BCST m64 zmm zmm +// Construct and append a VPMAXSQ.BCST instruction to the active function. // Operates on the global context. -func MULXQ(mr, r, r1 operand.Op) { ctx.MULXQ(mr, r, r1) } +func VPMAXSQ_BCST(ops ...operand.Op) { ctx.VPMAXSQ_BCST(ops...) } -// MWAIT: Monitor Wait. +// VPMAXSQ_BCST_Z: Maximum of Packed Signed Quadword Integers (Broadcast, Zeroing Masking). // // Forms: // -// MWAIT -// Construct and append a MWAIT instruction to the active function. -func (c *Context) MWAIT() { - if inst, err := x86.MWAIT(); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMAXSQ.BCST.Z m64 xmm k xmm +// VPMAXSQ.BCST.Z m64 ymm k ymm +// VPMAXSQ.BCST.Z m64 zmm k zmm +// Construct and append a VPMAXSQ.BCST.Z instruction to the active function. +func (c *Context) VPMAXSQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMAXSQ_BCST_Z(m, xyz, k, xyz1)) } -// MWAIT: Monitor Wait. +// VPMAXSQ_BCST_Z: Maximum of Packed Signed Quadword Integers (Broadcast, Zeroing Masking). // // Forms: // -// MWAIT -// Construct and append a MWAIT instruction to the active function. +// VPMAXSQ.BCST.Z m64 xmm k xmm +// VPMAXSQ.BCST.Z m64 ymm k ymm +// VPMAXSQ.BCST.Z m64 zmm k zmm +// Construct and append a VPMAXSQ.BCST.Z instruction to the active function. // Operates on the global context. -func MWAIT() { ctx.MWAIT() } +func VPMAXSQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPMAXSQ_BCST_Z(m, xyz, k, xyz1) } -// NEGB: Two's Complement Negation. +// VPMAXSQ_Z: Maximum of Packed Signed Quadword Integers (Zeroing Masking). // // Forms: // -// NEGB r8 -// NEGB m8 -// Construct and append a NEGB instruction to the active function. -func (c *Context) NEGB(mr operand.Op) { - if inst, err := x86.NEGB(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMAXSQ.Z m128 xmm k xmm +// VPMAXSQ.Z m256 ymm k ymm +// VPMAXSQ.Z xmm xmm k xmm +// VPMAXSQ.Z ymm ymm k ymm +// VPMAXSQ.Z m512 zmm k zmm +// VPMAXSQ.Z zmm zmm k zmm +// Construct and append a VPMAXSQ.Z instruction to the active function. +func (c *Context) VPMAXSQ_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMAXSQ_Z(mxyz, xyz, k, xyz1)) } -// NEGB: Two's Complement Negation. +// VPMAXSQ_Z: Maximum of Packed Signed Quadword Integers (Zeroing Masking). // // Forms: // -// NEGB r8 -// NEGB m8 -// Construct and append a NEGB instruction to the active function. +// VPMAXSQ.Z m128 xmm k xmm +// VPMAXSQ.Z m256 ymm k ymm +// VPMAXSQ.Z xmm xmm k xmm +// VPMAXSQ.Z ymm ymm k ymm +// VPMAXSQ.Z m512 zmm k zmm +// VPMAXSQ.Z zmm zmm k zmm +// Construct and append a VPMAXSQ.Z instruction to the active function. // Operates on the global context. -func NEGB(mr operand.Op) { ctx.NEGB(mr) } +func VPMAXSQ_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPMAXSQ_Z(mxyz, xyz, k, xyz1) } -// NEGL: Two's Complement Negation. +// VPMAXSW: Maximum of Packed Signed Word Integers. // // Forms: // -// NEGL r32 -// NEGL m32 -// Construct and append a NEGL instruction to the active function. -func (c *Context) NEGL(mr operand.Op) { - if inst, err := x86.NEGL(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMAXSW m256 ymm ymm +// VPMAXSW ymm ymm ymm +// VPMAXSW m128 xmm xmm +// VPMAXSW xmm xmm xmm +// VPMAXSW m128 xmm k xmm +// VPMAXSW m256 ymm k ymm +// VPMAXSW xmm xmm k xmm +// VPMAXSW ymm ymm k ymm +// VPMAXSW m512 zmm k zmm +// VPMAXSW m512 zmm zmm +// VPMAXSW zmm zmm k zmm +// VPMAXSW zmm zmm zmm +// Construct and append a VPMAXSW instruction to the active function. +func (c *Context) VPMAXSW(ops ...operand.Op) { + c.addinstruction(x86.VPMAXSW(ops...)) } -// NEGL: Two's Complement Negation. +// VPMAXSW: Maximum of Packed Signed Word Integers. // // Forms: // -// NEGL r32 -// NEGL m32 -// Construct and append a NEGL instruction to the active function. +// VPMAXSW m256 ymm ymm +// VPMAXSW ymm ymm ymm +// VPMAXSW m128 xmm xmm +// VPMAXSW xmm xmm xmm +// VPMAXSW m128 xmm k xmm +// VPMAXSW m256 ymm k ymm +// VPMAXSW xmm xmm k xmm +// VPMAXSW ymm ymm k ymm +// VPMAXSW m512 zmm k zmm +// VPMAXSW m512 zmm zmm +// VPMAXSW zmm zmm k zmm +// VPMAXSW zmm zmm zmm +// Construct and append a VPMAXSW instruction to the active function. // Operates on the global context. -func NEGL(mr operand.Op) { ctx.NEGL(mr) } +func VPMAXSW(ops ...operand.Op) { ctx.VPMAXSW(ops...) } -// NEGQ: Two's Complement Negation. +// VPMAXSW_Z: Maximum of Packed Signed Word Integers (Zeroing Masking). // // Forms: // -// NEGQ r64 -// NEGQ m64 -// Construct and append a NEGQ instruction to the active function. -func (c *Context) NEGQ(mr operand.Op) { - if inst, err := x86.NEGQ(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMAXSW.Z m128 xmm k xmm +// VPMAXSW.Z m256 ymm k ymm +// VPMAXSW.Z xmm xmm k xmm +// VPMAXSW.Z ymm ymm k ymm +// VPMAXSW.Z m512 zmm k zmm +// VPMAXSW.Z zmm zmm k zmm +// Construct and append a VPMAXSW.Z instruction to the active function. +func (c *Context) VPMAXSW_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMAXSW_Z(mxyz, xyz, k, xyz1)) } -// NEGQ: Two's Complement Negation. +// VPMAXSW_Z: Maximum of Packed Signed Word Integers (Zeroing Masking). // // Forms: // -// NEGQ r64 -// NEGQ m64 -// Construct and append a NEGQ instruction to the active function. +// VPMAXSW.Z m128 xmm k xmm +// VPMAXSW.Z m256 ymm k ymm +// VPMAXSW.Z xmm xmm k xmm +// VPMAXSW.Z ymm ymm k ymm +// VPMAXSW.Z m512 zmm k zmm +// VPMAXSW.Z zmm zmm k zmm +// Construct and append a VPMAXSW.Z instruction to the active function. // Operates on the global context. -func NEGQ(mr operand.Op) { ctx.NEGQ(mr) } +func VPMAXSW_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPMAXSW_Z(mxyz, xyz, k, xyz1) } -// NEGW: Two's Complement Negation. +// VPMAXUB: Maximum of Packed Unsigned Byte Integers. // // Forms: // -// NEGW r16 -// NEGW m16 -// Construct and append a NEGW instruction to the active function. -func (c *Context) NEGW(mr operand.Op) { - if inst, err := x86.NEGW(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMAXUB m256 ymm ymm +// VPMAXUB ymm ymm ymm +// VPMAXUB m128 xmm xmm +// VPMAXUB xmm xmm xmm +// VPMAXUB m128 xmm k xmm +// VPMAXUB m256 ymm k ymm +// VPMAXUB xmm xmm k xmm +// VPMAXUB ymm ymm k ymm +// VPMAXUB m512 zmm k zmm +// VPMAXUB m512 zmm zmm +// VPMAXUB zmm zmm k zmm +// VPMAXUB zmm zmm zmm +// Construct and append a VPMAXUB instruction to the active function. +func (c *Context) VPMAXUB(ops ...operand.Op) { + c.addinstruction(x86.VPMAXUB(ops...)) } -// NEGW: Two's Complement Negation. +// VPMAXUB: Maximum of Packed Unsigned Byte Integers. // // Forms: // -// NEGW r16 -// NEGW m16 -// Construct and append a NEGW instruction to the active function. +// VPMAXUB m256 ymm ymm +// VPMAXUB ymm ymm ymm +// VPMAXUB m128 xmm xmm +// VPMAXUB xmm xmm xmm +// VPMAXUB m128 xmm k xmm +// VPMAXUB m256 ymm k ymm +// VPMAXUB xmm xmm k xmm +// VPMAXUB ymm ymm k ymm +// VPMAXUB m512 zmm k zmm +// VPMAXUB m512 zmm zmm +// VPMAXUB zmm zmm k zmm +// VPMAXUB zmm zmm zmm +// Construct and append a VPMAXUB instruction to the active function. // Operates on the global context. -func NEGW(mr operand.Op) { ctx.NEGW(mr) } +func VPMAXUB(ops ...operand.Op) { ctx.VPMAXUB(ops...) } -// NOP: No Operation. +// VPMAXUB_Z: Maximum of Packed Unsigned Byte Integers (Zeroing Masking). // // Forms: // -// NOP -// Construct and append a NOP instruction to the active function. -func (c *Context) NOP() { - if inst, err := x86.NOP(); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMAXUB.Z m128 xmm k xmm +// VPMAXUB.Z m256 ymm k ymm +// VPMAXUB.Z xmm xmm k xmm +// VPMAXUB.Z ymm ymm k ymm +// VPMAXUB.Z m512 zmm k zmm +// VPMAXUB.Z zmm zmm k zmm +// Construct and append a VPMAXUB.Z instruction to the active function. +func (c *Context) VPMAXUB_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMAXUB_Z(mxyz, xyz, k, xyz1)) } -// NOP: No Operation. +// VPMAXUB_Z: Maximum of Packed Unsigned Byte Integers (Zeroing Masking). // // Forms: // -// NOP -// Construct and append a NOP instruction to the active function. +// VPMAXUB.Z m128 xmm k xmm +// VPMAXUB.Z m256 ymm k ymm +// VPMAXUB.Z xmm xmm k xmm +// VPMAXUB.Z ymm ymm k ymm +// VPMAXUB.Z m512 zmm k zmm +// VPMAXUB.Z zmm zmm k zmm +// Construct and append a VPMAXUB.Z instruction to the active function. // Operates on the global context. -func NOP() { ctx.NOP() } +func VPMAXUB_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPMAXUB_Z(mxyz, xyz, k, xyz1) } -// NOTB: One's Complement Negation. +// VPMAXUD: Maximum of Packed Unsigned Doubleword Integers. // // Forms: // -// NOTB r8 -// NOTB m8 -// Construct and append a NOTB instruction to the active function. -func (c *Context) NOTB(mr operand.Op) { - if inst, err := x86.NOTB(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMAXUD m256 ymm ymm +// VPMAXUD ymm ymm ymm +// VPMAXUD m128 xmm xmm +// VPMAXUD xmm xmm xmm +// VPMAXUD m128 xmm k xmm +// VPMAXUD m256 ymm k ymm +// VPMAXUD xmm xmm k xmm +// VPMAXUD ymm ymm k ymm +// VPMAXUD m512 zmm k zmm +// VPMAXUD m512 zmm zmm +// VPMAXUD zmm zmm k zmm +// VPMAXUD zmm zmm zmm +// Construct and append a VPMAXUD instruction to the active function. +func (c *Context) VPMAXUD(ops ...operand.Op) { + c.addinstruction(x86.VPMAXUD(ops...)) } -// NOTB: One's Complement Negation. +// VPMAXUD: Maximum of Packed Unsigned Doubleword Integers. // // Forms: // -// NOTB r8 -// NOTB m8 -// Construct and append a NOTB instruction to the active function. +// VPMAXUD m256 ymm ymm +// VPMAXUD ymm ymm ymm +// VPMAXUD m128 xmm xmm +// VPMAXUD xmm xmm xmm +// VPMAXUD m128 xmm k xmm +// VPMAXUD m256 ymm k ymm +// VPMAXUD xmm xmm k xmm +// VPMAXUD ymm ymm k ymm +// VPMAXUD m512 zmm k zmm +// VPMAXUD m512 zmm zmm +// VPMAXUD zmm zmm k zmm +// VPMAXUD zmm zmm zmm +// Construct and append a VPMAXUD instruction to the active function. // Operates on the global context. -func NOTB(mr operand.Op) { ctx.NOTB(mr) } +func VPMAXUD(ops ...operand.Op) { ctx.VPMAXUD(ops...) } -// NOTL: One's Complement Negation. +// VPMAXUD_BCST: Maximum of Packed Unsigned Doubleword Integers (Broadcast). // // Forms: // -// NOTL r32 -// NOTL m32 -// Construct and append a NOTL instruction to the active function. -func (c *Context) NOTL(mr operand.Op) { - if inst, err := x86.NOTL(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMAXUD.BCST m32 xmm k xmm +// VPMAXUD.BCST m32 xmm xmm +// VPMAXUD.BCST m32 ymm k ymm +// VPMAXUD.BCST m32 ymm ymm +// VPMAXUD.BCST m32 zmm k zmm +// VPMAXUD.BCST m32 zmm zmm +// Construct and append a VPMAXUD.BCST instruction to the active function. +func (c *Context) VPMAXUD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPMAXUD_BCST(ops...)) } -// NOTL: One's Complement Negation. +// VPMAXUD_BCST: Maximum of Packed Unsigned Doubleword Integers (Broadcast). // // Forms: // -// NOTL r32 -// NOTL m32 -// Construct and append a NOTL instruction to the active function. +// VPMAXUD.BCST m32 xmm k xmm +// VPMAXUD.BCST m32 xmm xmm +// VPMAXUD.BCST m32 ymm k ymm +// VPMAXUD.BCST m32 ymm ymm +// VPMAXUD.BCST m32 zmm k zmm +// VPMAXUD.BCST m32 zmm zmm +// Construct and append a VPMAXUD.BCST instruction to the active function. // Operates on the global context. -func NOTL(mr operand.Op) { ctx.NOTL(mr) } +func VPMAXUD_BCST(ops ...operand.Op) { ctx.VPMAXUD_BCST(ops...) } -// NOTQ: One's Complement Negation. +// VPMAXUD_BCST_Z: Maximum of Packed Unsigned Doubleword Integers (Broadcast, Zeroing Masking). // // Forms: // -// NOTQ r64 -// NOTQ m64 -// Construct and append a NOTQ instruction to the active function. -func (c *Context) NOTQ(mr operand.Op) { - if inst, err := x86.NOTQ(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMAXUD.BCST.Z m32 xmm k xmm +// VPMAXUD.BCST.Z m32 ymm k ymm +// VPMAXUD.BCST.Z m32 zmm k zmm +// Construct and append a VPMAXUD.BCST.Z instruction to the active function. +func (c *Context) VPMAXUD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMAXUD_BCST_Z(m, xyz, k, xyz1)) } -// NOTQ: One's Complement Negation. +// VPMAXUD_BCST_Z: Maximum of Packed Unsigned Doubleword Integers (Broadcast, Zeroing Masking). // // Forms: // -// NOTQ r64 -// NOTQ m64 -// Construct and append a NOTQ instruction to the active function. +// VPMAXUD.BCST.Z m32 xmm k xmm +// VPMAXUD.BCST.Z m32 ymm k ymm +// VPMAXUD.BCST.Z m32 zmm k zmm +// Construct and append a VPMAXUD.BCST.Z instruction to the active function. // Operates on the global context. -func NOTQ(mr operand.Op) { ctx.NOTQ(mr) } +func VPMAXUD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPMAXUD_BCST_Z(m, xyz, k, xyz1) } -// NOTW: One's Complement Negation. +// VPMAXUD_Z: Maximum of Packed Unsigned Doubleword Integers (Zeroing Masking). // // Forms: // -// NOTW r16 -// NOTW m16 -// Construct and append a NOTW instruction to the active function. -func (c *Context) NOTW(mr operand.Op) { - if inst, err := x86.NOTW(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMAXUD.Z m128 xmm k xmm +// VPMAXUD.Z m256 ymm k ymm +// VPMAXUD.Z xmm xmm k xmm +// VPMAXUD.Z ymm ymm k ymm +// VPMAXUD.Z m512 zmm k zmm +// VPMAXUD.Z zmm zmm k zmm +// Construct and append a VPMAXUD.Z instruction to the active function. +func (c *Context) VPMAXUD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMAXUD_Z(mxyz, xyz, k, xyz1)) } -// NOTW: One's Complement Negation. +// VPMAXUD_Z: Maximum of Packed Unsigned Doubleword Integers (Zeroing Masking). // // Forms: // -// NOTW r16 -// NOTW m16 -// Construct and append a NOTW instruction to the active function. +// VPMAXUD.Z m128 xmm k xmm +// VPMAXUD.Z m256 ymm k ymm +// VPMAXUD.Z xmm xmm k xmm +// VPMAXUD.Z ymm ymm k ymm +// VPMAXUD.Z m512 zmm k zmm +// VPMAXUD.Z zmm zmm k zmm +// Construct and append a VPMAXUD.Z instruction to the active function. // Operates on the global context. -func NOTW(mr operand.Op) { ctx.NOTW(mr) } +func VPMAXUD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPMAXUD_Z(mxyz, xyz, k, xyz1) } -// ORB: Logical Inclusive OR. +// VPMAXUQ: Maximum of Packed Unsigned Quadword Integers. // // Forms: // -// ORB imm8 al -// ORB imm8 r8 -// ORB r8 r8 -// ORB m8 r8 -// ORB imm8 m8 -// ORB r8 m8 -// Construct and append a ORB instruction to the active function. -func (c *Context) ORB(imr, amr operand.Op) { - if inst, err := x86.ORB(imr, amr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMAXUQ m128 xmm k xmm +// VPMAXUQ m128 xmm xmm +// VPMAXUQ m256 ymm k ymm +// VPMAXUQ m256 ymm ymm +// VPMAXUQ xmm xmm k xmm +// VPMAXUQ xmm xmm xmm +// VPMAXUQ ymm ymm k ymm +// VPMAXUQ ymm ymm ymm +// VPMAXUQ m512 zmm k zmm +// VPMAXUQ m512 zmm zmm +// VPMAXUQ zmm zmm k zmm +// VPMAXUQ zmm zmm zmm +// Construct and append a VPMAXUQ instruction to the active function. +func (c *Context) VPMAXUQ(ops ...operand.Op) { + c.addinstruction(x86.VPMAXUQ(ops...)) } -// ORB: Logical Inclusive OR. +// VPMAXUQ: Maximum of Packed Unsigned Quadword Integers. // // Forms: // -// ORB imm8 al -// ORB imm8 r8 -// ORB r8 r8 -// ORB m8 r8 -// ORB imm8 m8 -// ORB r8 m8 -// Construct and append a ORB instruction to the active function. +// VPMAXUQ m128 xmm k xmm +// VPMAXUQ m128 xmm xmm +// VPMAXUQ m256 ymm k ymm +// VPMAXUQ m256 ymm ymm +// VPMAXUQ xmm xmm k xmm +// VPMAXUQ xmm xmm xmm +// VPMAXUQ ymm ymm k ymm +// VPMAXUQ ymm ymm ymm +// VPMAXUQ m512 zmm k zmm +// VPMAXUQ m512 zmm zmm +// VPMAXUQ zmm zmm k zmm +// VPMAXUQ zmm zmm zmm +// Construct and append a VPMAXUQ instruction to the active function. // Operates on the global context. -func ORB(imr, amr operand.Op) { ctx.ORB(imr, amr) } +func VPMAXUQ(ops ...operand.Op) { ctx.VPMAXUQ(ops...) } -// ORL: Logical Inclusive OR. +// VPMAXUQ_BCST: Maximum of Packed Unsigned Quadword Integers (Broadcast). // // Forms: // -// ORL imm32 eax -// ORL imm8 r32 -// ORL imm32 r32 -// ORL r32 r32 -// ORL m32 r32 -// ORL imm8 m32 -// ORL imm32 m32 -// ORL r32 m32 -// Construct and append a ORL instruction to the active function. -func (c *Context) ORL(imr, emr operand.Op) { - if inst, err := x86.ORL(imr, emr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMAXUQ.BCST m64 xmm k xmm +// VPMAXUQ.BCST m64 xmm xmm +// VPMAXUQ.BCST m64 ymm k ymm +// VPMAXUQ.BCST m64 ymm ymm +// VPMAXUQ.BCST m64 zmm k zmm +// VPMAXUQ.BCST m64 zmm zmm +// Construct and append a VPMAXUQ.BCST instruction to the active function. +func (c *Context) VPMAXUQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPMAXUQ_BCST(ops...)) } -// ORL: Logical Inclusive OR. +// VPMAXUQ_BCST: Maximum of Packed Unsigned Quadword Integers (Broadcast). // // Forms: // -// ORL imm32 eax -// ORL imm8 r32 -// ORL imm32 r32 -// ORL r32 r32 -// ORL m32 r32 -// ORL imm8 m32 -// ORL imm32 m32 -// ORL r32 m32 -// Construct and append a ORL instruction to the active function. +// VPMAXUQ.BCST m64 xmm k xmm +// VPMAXUQ.BCST m64 xmm xmm +// VPMAXUQ.BCST m64 ymm k ymm +// VPMAXUQ.BCST m64 ymm ymm +// VPMAXUQ.BCST m64 zmm k zmm +// VPMAXUQ.BCST m64 zmm zmm +// Construct and append a VPMAXUQ.BCST instruction to the active function. // Operates on the global context. -func ORL(imr, emr operand.Op) { ctx.ORL(imr, emr) } +func VPMAXUQ_BCST(ops ...operand.Op) { ctx.VPMAXUQ_BCST(ops...) } -// ORPD: Bitwise Logical OR of Double-Precision Floating-Point Values. +// VPMAXUQ_BCST_Z: Maximum of Packed Unsigned Quadword Integers (Broadcast, Zeroing Masking). // // Forms: // -// ORPD xmm xmm -// ORPD m128 xmm -// Construct and append a ORPD instruction to the active function. -func (c *Context) ORPD(mx, x operand.Op) { - if inst, err := x86.ORPD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMAXUQ.BCST.Z m64 xmm k xmm +// VPMAXUQ.BCST.Z m64 ymm k ymm +// VPMAXUQ.BCST.Z m64 zmm k zmm +// Construct and append a VPMAXUQ.BCST.Z instruction to the active function. +func (c *Context) VPMAXUQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMAXUQ_BCST_Z(m, xyz, k, xyz1)) } -// ORPD: Bitwise Logical OR of Double-Precision Floating-Point Values. +// VPMAXUQ_BCST_Z: Maximum of Packed Unsigned Quadword Integers (Broadcast, Zeroing Masking). // // Forms: // -// ORPD xmm xmm -// ORPD m128 xmm -// Construct and append a ORPD instruction to the active function. +// VPMAXUQ.BCST.Z m64 xmm k xmm +// VPMAXUQ.BCST.Z m64 ymm k ymm +// VPMAXUQ.BCST.Z m64 zmm k zmm +// Construct and append a VPMAXUQ.BCST.Z instruction to the active function. // Operates on the global context. -func ORPD(mx, x operand.Op) { ctx.ORPD(mx, x) } +func VPMAXUQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPMAXUQ_BCST_Z(m, xyz, k, xyz1) } -// ORPS: Bitwise Logical OR of Single-Precision Floating-Point Values. +// VPMAXUQ_Z: Maximum of Packed Unsigned Quadword Integers (Zeroing Masking). // // Forms: // -// ORPS xmm xmm -// ORPS m128 xmm -// Construct and append a ORPS instruction to the active function. -func (c *Context) ORPS(mx, x operand.Op) { - if inst, err := x86.ORPS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMAXUQ.Z m128 xmm k xmm +// VPMAXUQ.Z m256 ymm k ymm +// VPMAXUQ.Z xmm xmm k xmm +// VPMAXUQ.Z ymm ymm k ymm +// VPMAXUQ.Z m512 zmm k zmm +// VPMAXUQ.Z zmm zmm k zmm +// Construct and append a VPMAXUQ.Z instruction to the active function. +func (c *Context) VPMAXUQ_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMAXUQ_Z(mxyz, xyz, k, xyz1)) } -// ORPS: Bitwise Logical OR of Single-Precision Floating-Point Values. +// VPMAXUQ_Z: Maximum of Packed Unsigned Quadword Integers (Zeroing Masking). // // Forms: // -// ORPS xmm xmm -// ORPS m128 xmm -// Construct and append a ORPS instruction to the active function. +// VPMAXUQ.Z m128 xmm k xmm +// VPMAXUQ.Z m256 ymm k ymm +// VPMAXUQ.Z xmm xmm k xmm +// VPMAXUQ.Z ymm ymm k ymm +// VPMAXUQ.Z m512 zmm k zmm +// VPMAXUQ.Z zmm zmm k zmm +// Construct and append a VPMAXUQ.Z instruction to the active function. // Operates on the global context. -func ORPS(mx, x operand.Op) { ctx.ORPS(mx, x) } +func VPMAXUQ_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPMAXUQ_Z(mxyz, xyz, k, xyz1) } -// ORQ: Logical Inclusive OR. +// VPMAXUW: Maximum of Packed Unsigned Word Integers. // // Forms: // -// ORQ imm32 rax -// ORQ imm8 r64 -// ORQ imm32 r64 -// ORQ r64 r64 -// ORQ m64 r64 -// ORQ imm8 m64 -// ORQ imm32 m64 -// ORQ r64 m64 -// Construct and append a ORQ instruction to the active function. -func (c *Context) ORQ(imr, mr operand.Op) { - if inst, err := x86.ORQ(imr, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMAXUW m256 ymm ymm +// VPMAXUW ymm ymm ymm +// VPMAXUW m128 xmm xmm +// VPMAXUW xmm xmm xmm +// VPMAXUW m128 xmm k xmm +// VPMAXUW m256 ymm k ymm +// VPMAXUW xmm xmm k xmm +// VPMAXUW ymm ymm k ymm +// VPMAXUW m512 zmm k zmm +// VPMAXUW m512 zmm zmm +// VPMAXUW zmm zmm k zmm +// VPMAXUW zmm zmm zmm +// Construct and append a VPMAXUW instruction to the active function. +func (c *Context) VPMAXUW(ops ...operand.Op) { + c.addinstruction(x86.VPMAXUW(ops...)) } -// ORQ: Logical Inclusive OR. +// VPMAXUW: Maximum of Packed Unsigned Word Integers. // // Forms: // -// ORQ imm32 rax -// ORQ imm8 r64 -// ORQ imm32 r64 -// ORQ r64 r64 -// ORQ m64 r64 -// ORQ imm8 m64 -// ORQ imm32 m64 -// ORQ r64 m64 -// Construct and append a ORQ instruction to the active function. +// VPMAXUW m256 ymm ymm +// VPMAXUW ymm ymm ymm +// VPMAXUW m128 xmm xmm +// VPMAXUW xmm xmm xmm +// VPMAXUW m128 xmm k xmm +// VPMAXUW m256 ymm k ymm +// VPMAXUW xmm xmm k xmm +// VPMAXUW ymm ymm k ymm +// VPMAXUW m512 zmm k zmm +// VPMAXUW m512 zmm zmm +// VPMAXUW zmm zmm k zmm +// VPMAXUW zmm zmm zmm +// Construct and append a VPMAXUW instruction to the active function. // Operates on the global context. -func ORQ(imr, mr operand.Op) { ctx.ORQ(imr, mr) } +func VPMAXUW(ops ...operand.Op) { ctx.VPMAXUW(ops...) } -// ORW: Logical Inclusive OR. +// VPMAXUW_Z: Maximum of Packed Unsigned Word Integers (Zeroing Masking). // // Forms: // -// ORW imm16 ax -// ORW imm8 r16 -// ORW imm16 r16 -// ORW r16 r16 -// ORW m16 r16 -// ORW imm8 m16 -// ORW imm16 m16 -// ORW r16 m16 -// Construct and append a ORW instruction to the active function. -func (c *Context) ORW(imr, amr operand.Op) { - if inst, err := x86.ORW(imr, amr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMAXUW.Z m128 xmm k xmm +// VPMAXUW.Z m256 ymm k ymm +// VPMAXUW.Z xmm xmm k xmm +// VPMAXUW.Z ymm ymm k ymm +// VPMAXUW.Z m512 zmm k zmm +// VPMAXUW.Z zmm zmm k zmm +// Construct and append a VPMAXUW.Z instruction to the active function. +func (c *Context) VPMAXUW_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMAXUW_Z(mxyz, xyz, k, xyz1)) } -// ORW: Logical Inclusive OR. +// VPMAXUW_Z: Maximum of Packed Unsigned Word Integers (Zeroing Masking). // // Forms: // -// ORW imm16 ax -// ORW imm8 r16 -// ORW imm16 r16 -// ORW r16 r16 -// ORW m16 r16 -// ORW imm8 m16 -// ORW imm16 m16 -// ORW r16 m16 -// Construct and append a ORW instruction to the active function. +// VPMAXUW.Z m128 xmm k xmm +// VPMAXUW.Z m256 ymm k ymm +// VPMAXUW.Z xmm xmm k xmm +// VPMAXUW.Z ymm ymm k ymm +// VPMAXUW.Z m512 zmm k zmm +// VPMAXUW.Z zmm zmm k zmm +// Construct and append a VPMAXUW.Z instruction to the active function. // Operates on the global context. -func ORW(imr, amr operand.Op) { ctx.ORW(imr, amr) } +func VPMAXUW_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPMAXUW_Z(mxyz, xyz, k, xyz1) } -// PABSB: Packed Absolute Value of Byte Integers. +// VPMINSB: Minimum of Packed Signed Byte Integers. // // Forms: // -// PABSB xmm xmm -// PABSB m128 xmm -// Construct and append a PABSB instruction to the active function. -func (c *Context) PABSB(mx, x operand.Op) { - if inst, err := x86.PABSB(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMINSB m256 ymm ymm +// VPMINSB ymm ymm ymm +// VPMINSB m128 xmm xmm +// VPMINSB xmm xmm xmm +// VPMINSB m128 xmm k xmm +// VPMINSB m256 ymm k ymm +// VPMINSB xmm xmm k xmm +// VPMINSB ymm ymm k ymm +// VPMINSB m512 zmm k zmm +// VPMINSB m512 zmm zmm +// VPMINSB zmm zmm k zmm +// VPMINSB zmm zmm zmm +// Construct and append a VPMINSB instruction to the active function. +func (c *Context) VPMINSB(ops ...operand.Op) { + c.addinstruction(x86.VPMINSB(ops...)) } -// PABSB: Packed Absolute Value of Byte Integers. +// VPMINSB: Minimum of Packed Signed Byte Integers. // // Forms: // -// PABSB xmm xmm -// PABSB m128 xmm -// Construct and append a PABSB instruction to the active function. +// VPMINSB m256 ymm ymm +// VPMINSB ymm ymm ymm +// VPMINSB m128 xmm xmm +// VPMINSB xmm xmm xmm +// VPMINSB m128 xmm k xmm +// VPMINSB m256 ymm k ymm +// VPMINSB xmm xmm k xmm +// VPMINSB ymm ymm k ymm +// VPMINSB m512 zmm k zmm +// VPMINSB m512 zmm zmm +// VPMINSB zmm zmm k zmm +// VPMINSB zmm zmm zmm +// Construct and append a VPMINSB instruction to the active function. // Operates on the global context. -func PABSB(mx, x operand.Op) { ctx.PABSB(mx, x) } +func VPMINSB(ops ...operand.Op) { ctx.VPMINSB(ops...) } -// PABSD: Packed Absolute Value of Doubleword Integers. +// VPMINSB_Z: Minimum of Packed Signed Byte Integers (Zeroing Masking). // // Forms: // -// PABSD xmm xmm -// PABSD m128 xmm -// Construct and append a PABSD instruction to the active function. -func (c *Context) PABSD(mx, x operand.Op) { - if inst, err := x86.PABSD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMINSB.Z m128 xmm k xmm +// VPMINSB.Z m256 ymm k ymm +// VPMINSB.Z xmm xmm k xmm +// VPMINSB.Z ymm ymm k ymm +// VPMINSB.Z m512 zmm k zmm +// VPMINSB.Z zmm zmm k zmm +// Construct and append a VPMINSB.Z instruction to the active function. +func (c *Context) VPMINSB_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMINSB_Z(mxyz, xyz, k, xyz1)) } -// PABSD: Packed Absolute Value of Doubleword Integers. +// VPMINSB_Z: Minimum of Packed Signed Byte Integers (Zeroing Masking). // // Forms: // -// PABSD xmm xmm -// PABSD m128 xmm -// Construct and append a PABSD instruction to the active function. +// VPMINSB.Z m128 xmm k xmm +// VPMINSB.Z m256 ymm k ymm +// VPMINSB.Z xmm xmm k xmm +// VPMINSB.Z ymm ymm k ymm +// VPMINSB.Z m512 zmm k zmm +// VPMINSB.Z zmm zmm k zmm +// Construct and append a VPMINSB.Z instruction to the active function. // Operates on the global context. -func PABSD(mx, x operand.Op) { ctx.PABSD(mx, x) } +func VPMINSB_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPMINSB_Z(mxyz, xyz, k, xyz1) } -// PABSW: Packed Absolute Value of Word Integers. +// VPMINSD: Minimum of Packed Signed Doubleword Integers. // // Forms: // -// PABSW xmm xmm -// PABSW m128 xmm -// Construct and append a PABSW instruction to the active function. -func (c *Context) PABSW(mx, x operand.Op) { - if inst, err := x86.PABSW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMINSD m256 ymm ymm +// VPMINSD ymm ymm ymm +// VPMINSD m128 xmm xmm +// VPMINSD xmm xmm xmm +// VPMINSD m128 xmm k xmm +// VPMINSD m256 ymm k ymm +// VPMINSD xmm xmm k xmm +// VPMINSD ymm ymm k ymm +// VPMINSD m512 zmm k zmm +// VPMINSD m512 zmm zmm +// VPMINSD zmm zmm k zmm +// VPMINSD zmm zmm zmm +// Construct and append a VPMINSD instruction to the active function. +func (c *Context) VPMINSD(ops ...operand.Op) { + c.addinstruction(x86.VPMINSD(ops...)) } -// PABSW: Packed Absolute Value of Word Integers. +// VPMINSD: Minimum of Packed Signed Doubleword Integers. // // Forms: // -// PABSW xmm xmm -// PABSW m128 xmm -// Construct and append a PABSW instruction to the active function. +// VPMINSD m256 ymm ymm +// VPMINSD ymm ymm ymm +// VPMINSD m128 xmm xmm +// VPMINSD xmm xmm xmm +// VPMINSD m128 xmm k xmm +// VPMINSD m256 ymm k ymm +// VPMINSD xmm xmm k xmm +// VPMINSD ymm ymm k ymm +// VPMINSD m512 zmm k zmm +// VPMINSD m512 zmm zmm +// VPMINSD zmm zmm k zmm +// VPMINSD zmm zmm zmm +// Construct and append a VPMINSD instruction to the active function. // Operates on the global context. -func PABSW(mx, x operand.Op) { ctx.PABSW(mx, x) } +func VPMINSD(ops ...operand.Op) { ctx.VPMINSD(ops...) } -// PACKSSLW: Pack Doublewords into Words with Signed Saturation. +// VPMINSD_BCST: Minimum of Packed Signed Doubleword Integers (Broadcast). // // Forms: // -// PACKSSLW xmm xmm -// PACKSSLW m128 xmm -// Construct and append a PACKSSLW instruction to the active function. -func (c *Context) PACKSSLW(mx, x operand.Op) { - if inst, err := x86.PACKSSLW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMINSD.BCST m32 xmm k xmm +// VPMINSD.BCST m32 xmm xmm +// VPMINSD.BCST m32 ymm k ymm +// VPMINSD.BCST m32 ymm ymm +// VPMINSD.BCST m32 zmm k zmm +// VPMINSD.BCST m32 zmm zmm +// Construct and append a VPMINSD.BCST instruction to the active function. +func (c *Context) VPMINSD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPMINSD_BCST(ops...)) } -// PACKSSLW: Pack Doublewords into Words with Signed Saturation. +// VPMINSD_BCST: Minimum of Packed Signed Doubleword Integers (Broadcast). // // Forms: // -// PACKSSLW xmm xmm -// PACKSSLW m128 xmm -// Construct and append a PACKSSLW instruction to the active function. +// VPMINSD.BCST m32 xmm k xmm +// VPMINSD.BCST m32 xmm xmm +// VPMINSD.BCST m32 ymm k ymm +// VPMINSD.BCST m32 ymm ymm +// VPMINSD.BCST m32 zmm k zmm +// VPMINSD.BCST m32 zmm zmm +// Construct and append a VPMINSD.BCST instruction to the active function. // Operates on the global context. -func PACKSSLW(mx, x operand.Op) { ctx.PACKSSLW(mx, x) } +func VPMINSD_BCST(ops ...operand.Op) { ctx.VPMINSD_BCST(ops...) } -// PACKSSWB: Pack Words into Bytes with Signed Saturation. +// VPMINSD_BCST_Z: Minimum of Packed Signed Doubleword Integers (Broadcast, Zeroing Masking). // // Forms: // -// PACKSSWB xmm xmm -// PACKSSWB m128 xmm -// Construct and append a PACKSSWB instruction to the active function. -func (c *Context) PACKSSWB(mx, x operand.Op) { - if inst, err := x86.PACKSSWB(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMINSD.BCST.Z m32 xmm k xmm +// VPMINSD.BCST.Z m32 ymm k ymm +// VPMINSD.BCST.Z m32 zmm k zmm +// Construct and append a VPMINSD.BCST.Z instruction to the active function. +func (c *Context) VPMINSD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMINSD_BCST_Z(m, xyz, k, xyz1)) } -// PACKSSWB: Pack Words into Bytes with Signed Saturation. +// VPMINSD_BCST_Z: Minimum of Packed Signed Doubleword Integers (Broadcast, Zeroing Masking). // // Forms: // -// PACKSSWB xmm xmm -// PACKSSWB m128 xmm -// Construct and append a PACKSSWB instruction to the active function. +// VPMINSD.BCST.Z m32 xmm k xmm +// VPMINSD.BCST.Z m32 ymm k ymm +// VPMINSD.BCST.Z m32 zmm k zmm +// Construct and append a VPMINSD.BCST.Z instruction to the active function. // Operates on the global context. -func PACKSSWB(mx, x operand.Op) { ctx.PACKSSWB(mx, x) } +func VPMINSD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPMINSD_BCST_Z(m, xyz, k, xyz1) } -// PACKUSDW: Pack Doublewords into Words with Unsigned Saturation. +// VPMINSD_Z: Minimum of Packed Signed Doubleword Integers (Zeroing Masking). // // Forms: // -// PACKUSDW xmm xmm -// PACKUSDW m128 xmm -// Construct and append a PACKUSDW instruction to the active function. -func (c *Context) PACKUSDW(mx, x operand.Op) { - if inst, err := x86.PACKUSDW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMINSD.Z m128 xmm k xmm +// VPMINSD.Z m256 ymm k ymm +// VPMINSD.Z xmm xmm k xmm +// VPMINSD.Z ymm ymm k ymm +// VPMINSD.Z m512 zmm k zmm +// VPMINSD.Z zmm zmm k zmm +// Construct and append a VPMINSD.Z instruction to the active function. +func (c *Context) VPMINSD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMINSD_Z(mxyz, xyz, k, xyz1)) } -// PACKUSDW: Pack Doublewords into Words with Unsigned Saturation. +// VPMINSD_Z: Minimum of Packed Signed Doubleword Integers (Zeroing Masking). // // Forms: // -// PACKUSDW xmm xmm -// PACKUSDW m128 xmm -// Construct and append a PACKUSDW instruction to the active function. +// VPMINSD.Z m128 xmm k xmm +// VPMINSD.Z m256 ymm k ymm +// VPMINSD.Z xmm xmm k xmm +// VPMINSD.Z ymm ymm k ymm +// VPMINSD.Z m512 zmm k zmm +// VPMINSD.Z zmm zmm k zmm +// Construct and append a VPMINSD.Z instruction to the active function. // Operates on the global context. -func PACKUSDW(mx, x operand.Op) { ctx.PACKUSDW(mx, x) } +func VPMINSD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPMINSD_Z(mxyz, xyz, k, xyz1) } -// PACKUSWB: Pack Words into Bytes with Unsigned Saturation. +// VPMINSQ: Minimum of Packed Signed Quadword Integers. // // Forms: // -// PACKUSWB xmm xmm -// PACKUSWB m128 xmm -// Construct and append a PACKUSWB instruction to the active function. -func (c *Context) PACKUSWB(mx, x operand.Op) { - if inst, err := x86.PACKUSWB(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMINSQ m128 xmm k xmm +// VPMINSQ m128 xmm xmm +// VPMINSQ m256 ymm k ymm +// VPMINSQ m256 ymm ymm +// VPMINSQ xmm xmm k xmm +// VPMINSQ xmm xmm xmm +// VPMINSQ ymm ymm k ymm +// VPMINSQ ymm ymm ymm +// VPMINSQ m512 zmm k zmm +// VPMINSQ m512 zmm zmm +// VPMINSQ zmm zmm k zmm +// VPMINSQ zmm zmm zmm +// Construct and append a VPMINSQ instruction to the active function. +func (c *Context) VPMINSQ(ops ...operand.Op) { + c.addinstruction(x86.VPMINSQ(ops...)) } -// PACKUSWB: Pack Words into Bytes with Unsigned Saturation. +// VPMINSQ: Minimum of Packed Signed Quadword Integers. // // Forms: // -// PACKUSWB xmm xmm -// PACKUSWB m128 xmm -// Construct and append a PACKUSWB instruction to the active function. +// VPMINSQ m128 xmm k xmm +// VPMINSQ m128 xmm xmm +// VPMINSQ m256 ymm k ymm +// VPMINSQ m256 ymm ymm +// VPMINSQ xmm xmm k xmm +// VPMINSQ xmm xmm xmm +// VPMINSQ ymm ymm k ymm +// VPMINSQ ymm ymm ymm +// VPMINSQ m512 zmm k zmm +// VPMINSQ m512 zmm zmm +// VPMINSQ zmm zmm k zmm +// VPMINSQ zmm zmm zmm +// Construct and append a VPMINSQ instruction to the active function. // Operates on the global context. -func PACKUSWB(mx, x operand.Op) { ctx.PACKUSWB(mx, x) } +func VPMINSQ(ops ...operand.Op) { ctx.VPMINSQ(ops...) } -// PADDB: Add Packed Byte Integers. +// VPMINSQ_BCST: Minimum of Packed Signed Quadword Integers (Broadcast). // // Forms: // -// PADDB xmm xmm -// PADDB m128 xmm -// Construct and append a PADDB instruction to the active function. -func (c *Context) PADDB(mx, x operand.Op) { - if inst, err := x86.PADDB(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMINSQ.BCST m64 xmm k xmm +// VPMINSQ.BCST m64 xmm xmm +// VPMINSQ.BCST m64 ymm k ymm +// VPMINSQ.BCST m64 ymm ymm +// VPMINSQ.BCST m64 zmm k zmm +// VPMINSQ.BCST m64 zmm zmm +// Construct and append a VPMINSQ.BCST instruction to the active function. +func (c *Context) VPMINSQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPMINSQ_BCST(ops...)) } -// PADDB: Add Packed Byte Integers. +// VPMINSQ_BCST: Minimum of Packed Signed Quadword Integers (Broadcast). // // Forms: // -// PADDB xmm xmm -// PADDB m128 xmm -// Construct and append a PADDB instruction to the active function. +// VPMINSQ.BCST m64 xmm k xmm +// VPMINSQ.BCST m64 xmm xmm +// VPMINSQ.BCST m64 ymm k ymm +// VPMINSQ.BCST m64 ymm ymm +// VPMINSQ.BCST m64 zmm k zmm +// VPMINSQ.BCST m64 zmm zmm +// Construct and append a VPMINSQ.BCST instruction to the active function. // Operates on the global context. -func PADDB(mx, x operand.Op) { ctx.PADDB(mx, x) } +func VPMINSQ_BCST(ops ...operand.Op) { ctx.VPMINSQ_BCST(ops...) } -// PADDD: Add Packed Doubleword Integers. +// VPMINSQ_BCST_Z: Minimum of Packed Signed Quadword Integers (Broadcast, Zeroing Masking). // // Forms: // -// PADDD xmm xmm -// PADDD m128 xmm -// Construct and append a PADDD instruction to the active function. -func (c *Context) PADDD(mx, x operand.Op) { - if inst, err := x86.PADDD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMINSQ.BCST.Z m64 xmm k xmm +// VPMINSQ.BCST.Z m64 ymm k ymm +// VPMINSQ.BCST.Z m64 zmm k zmm +// Construct and append a VPMINSQ.BCST.Z instruction to the active function. +func (c *Context) VPMINSQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMINSQ_BCST_Z(m, xyz, k, xyz1)) } -// PADDD: Add Packed Doubleword Integers. +// VPMINSQ_BCST_Z: Minimum of Packed Signed Quadword Integers (Broadcast, Zeroing Masking). // // Forms: // -// PADDD xmm xmm -// PADDD m128 xmm -// Construct and append a PADDD instruction to the active function. +// VPMINSQ.BCST.Z m64 xmm k xmm +// VPMINSQ.BCST.Z m64 ymm k ymm +// VPMINSQ.BCST.Z m64 zmm k zmm +// Construct and append a VPMINSQ.BCST.Z instruction to the active function. // Operates on the global context. -func PADDD(mx, x operand.Op) { ctx.PADDD(mx, x) } +func VPMINSQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPMINSQ_BCST_Z(m, xyz, k, xyz1) } -// PADDL: Add Packed Doubleword Integers. +// VPMINSQ_Z: Minimum of Packed Signed Quadword Integers (Zeroing Masking). // // Forms: // -// PADDL xmm xmm -// PADDL m128 xmm -// Construct and append a PADDL instruction to the active function. -func (c *Context) PADDL(mx, x operand.Op) { - if inst, err := x86.PADDL(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMINSQ.Z m128 xmm k xmm +// VPMINSQ.Z m256 ymm k ymm +// VPMINSQ.Z xmm xmm k xmm +// VPMINSQ.Z ymm ymm k ymm +// VPMINSQ.Z m512 zmm k zmm +// VPMINSQ.Z zmm zmm k zmm +// Construct and append a VPMINSQ.Z instruction to the active function. +func (c *Context) VPMINSQ_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMINSQ_Z(mxyz, xyz, k, xyz1)) } -// PADDL: Add Packed Doubleword Integers. +// VPMINSQ_Z: Minimum of Packed Signed Quadword Integers (Zeroing Masking). // // Forms: // -// PADDL xmm xmm -// PADDL m128 xmm -// Construct and append a PADDL instruction to the active function. +// VPMINSQ.Z m128 xmm k xmm +// VPMINSQ.Z m256 ymm k ymm +// VPMINSQ.Z xmm xmm k xmm +// VPMINSQ.Z ymm ymm k ymm +// VPMINSQ.Z m512 zmm k zmm +// VPMINSQ.Z zmm zmm k zmm +// Construct and append a VPMINSQ.Z instruction to the active function. // Operates on the global context. -func PADDL(mx, x operand.Op) { ctx.PADDL(mx, x) } +func VPMINSQ_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPMINSQ_Z(mxyz, xyz, k, xyz1) } -// PADDQ: Add Packed Quadword Integers. +// VPMINSW: Minimum of Packed Signed Word Integers. // // Forms: // -// PADDQ xmm xmm -// PADDQ m128 xmm -// Construct and append a PADDQ instruction to the active function. -func (c *Context) PADDQ(mx, x operand.Op) { - if inst, err := x86.PADDQ(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMINSW m256 ymm ymm +// VPMINSW ymm ymm ymm +// VPMINSW m128 xmm xmm +// VPMINSW xmm xmm xmm +// VPMINSW m128 xmm k xmm +// VPMINSW m256 ymm k ymm +// VPMINSW xmm xmm k xmm +// VPMINSW ymm ymm k ymm +// VPMINSW m512 zmm k zmm +// VPMINSW m512 zmm zmm +// VPMINSW zmm zmm k zmm +// VPMINSW zmm zmm zmm +// Construct and append a VPMINSW instruction to the active function. +func (c *Context) VPMINSW(ops ...operand.Op) { + c.addinstruction(x86.VPMINSW(ops...)) } -// PADDQ: Add Packed Quadword Integers. +// VPMINSW: Minimum of Packed Signed Word Integers. // // Forms: // -// PADDQ xmm xmm -// PADDQ m128 xmm -// Construct and append a PADDQ instruction to the active function. +// VPMINSW m256 ymm ymm +// VPMINSW ymm ymm ymm +// VPMINSW m128 xmm xmm +// VPMINSW xmm xmm xmm +// VPMINSW m128 xmm k xmm +// VPMINSW m256 ymm k ymm +// VPMINSW xmm xmm k xmm +// VPMINSW ymm ymm k ymm +// VPMINSW m512 zmm k zmm +// VPMINSW m512 zmm zmm +// VPMINSW zmm zmm k zmm +// VPMINSW zmm zmm zmm +// Construct and append a VPMINSW instruction to the active function. // Operates on the global context. -func PADDQ(mx, x operand.Op) { ctx.PADDQ(mx, x) } +func VPMINSW(ops ...operand.Op) { ctx.VPMINSW(ops...) } -// PADDSB: Add Packed Signed Byte Integers with Signed Saturation. +// VPMINSW_Z: Minimum of Packed Signed Word Integers (Zeroing Masking). // // Forms: // -// PADDSB xmm xmm -// PADDSB m128 xmm -// Construct and append a PADDSB instruction to the active function. -func (c *Context) PADDSB(mx, x operand.Op) { - if inst, err := x86.PADDSB(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMINSW.Z m128 xmm k xmm +// VPMINSW.Z m256 ymm k ymm +// VPMINSW.Z xmm xmm k xmm +// VPMINSW.Z ymm ymm k ymm +// VPMINSW.Z m512 zmm k zmm +// VPMINSW.Z zmm zmm k zmm +// Construct and append a VPMINSW.Z instruction to the active function. +func (c *Context) VPMINSW_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMINSW_Z(mxyz, xyz, k, xyz1)) } -// PADDSB: Add Packed Signed Byte Integers with Signed Saturation. +// VPMINSW_Z: Minimum of Packed Signed Word Integers (Zeroing Masking). // // Forms: // -// PADDSB xmm xmm -// PADDSB m128 xmm -// Construct and append a PADDSB instruction to the active function. +// VPMINSW.Z m128 xmm k xmm +// VPMINSW.Z m256 ymm k ymm +// VPMINSW.Z xmm xmm k xmm +// VPMINSW.Z ymm ymm k ymm +// VPMINSW.Z m512 zmm k zmm +// VPMINSW.Z zmm zmm k zmm +// Construct and append a VPMINSW.Z instruction to the active function. // Operates on the global context. -func PADDSB(mx, x operand.Op) { ctx.PADDSB(mx, x) } +func VPMINSW_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPMINSW_Z(mxyz, xyz, k, xyz1) } -// PADDSW: Add Packed Signed Word Integers with Signed Saturation. +// VPMINUB: Minimum of Packed Unsigned Byte Integers. // // Forms: // -// PADDSW xmm xmm -// PADDSW m128 xmm -// Construct and append a PADDSW instruction to the active function. -func (c *Context) PADDSW(mx, x operand.Op) { - if inst, err := x86.PADDSW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMINUB m256 ymm ymm +// VPMINUB ymm ymm ymm +// VPMINUB m128 xmm xmm +// VPMINUB xmm xmm xmm +// VPMINUB m128 xmm k xmm +// VPMINUB m256 ymm k ymm +// VPMINUB xmm xmm k xmm +// VPMINUB ymm ymm k ymm +// VPMINUB m512 zmm k zmm +// VPMINUB m512 zmm zmm +// VPMINUB zmm zmm k zmm +// VPMINUB zmm zmm zmm +// Construct and append a VPMINUB instruction to the active function. +func (c *Context) VPMINUB(ops ...operand.Op) { + c.addinstruction(x86.VPMINUB(ops...)) } -// PADDSW: Add Packed Signed Word Integers with Signed Saturation. +// VPMINUB: Minimum of Packed Unsigned Byte Integers. // // Forms: // -// PADDSW xmm xmm -// PADDSW m128 xmm -// Construct and append a PADDSW instruction to the active function. +// VPMINUB m256 ymm ymm +// VPMINUB ymm ymm ymm +// VPMINUB m128 xmm xmm +// VPMINUB xmm xmm xmm +// VPMINUB m128 xmm k xmm +// VPMINUB m256 ymm k ymm +// VPMINUB xmm xmm k xmm +// VPMINUB ymm ymm k ymm +// VPMINUB m512 zmm k zmm +// VPMINUB m512 zmm zmm +// VPMINUB zmm zmm k zmm +// VPMINUB zmm zmm zmm +// Construct and append a VPMINUB instruction to the active function. // Operates on the global context. -func PADDSW(mx, x operand.Op) { ctx.PADDSW(mx, x) } +func VPMINUB(ops ...operand.Op) { ctx.VPMINUB(ops...) } -// PADDUSB: Add Packed Unsigned Byte Integers with Unsigned Saturation. +// VPMINUB_Z: Minimum of Packed Unsigned Byte Integers (Zeroing Masking). // // Forms: // -// PADDUSB xmm xmm -// PADDUSB m128 xmm -// Construct and append a PADDUSB instruction to the active function. -func (c *Context) PADDUSB(mx, x operand.Op) { - if inst, err := x86.PADDUSB(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMINUB.Z m128 xmm k xmm +// VPMINUB.Z m256 ymm k ymm +// VPMINUB.Z xmm xmm k xmm +// VPMINUB.Z ymm ymm k ymm +// VPMINUB.Z m512 zmm k zmm +// VPMINUB.Z zmm zmm k zmm +// Construct and append a VPMINUB.Z instruction to the active function. +func (c *Context) VPMINUB_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMINUB_Z(mxyz, xyz, k, xyz1)) } -// PADDUSB: Add Packed Unsigned Byte Integers with Unsigned Saturation. +// VPMINUB_Z: Minimum of Packed Unsigned Byte Integers (Zeroing Masking). // // Forms: // -// PADDUSB xmm xmm -// PADDUSB m128 xmm -// Construct and append a PADDUSB instruction to the active function. +// VPMINUB.Z m128 xmm k xmm +// VPMINUB.Z m256 ymm k ymm +// VPMINUB.Z xmm xmm k xmm +// VPMINUB.Z ymm ymm k ymm +// VPMINUB.Z m512 zmm k zmm +// VPMINUB.Z zmm zmm k zmm +// Construct and append a VPMINUB.Z instruction to the active function. // Operates on the global context. -func PADDUSB(mx, x operand.Op) { ctx.PADDUSB(mx, x) } +func VPMINUB_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPMINUB_Z(mxyz, xyz, k, xyz1) } -// PADDUSW: Add Packed Unsigned Word Integers with Unsigned Saturation. +// VPMINUD: Minimum of Packed Unsigned Doubleword Integers. // // Forms: // -// PADDUSW xmm xmm -// PADDUSW m128 xmm -// Construct and append a PADDUSW instruction to the active function. -func (c *Context) PADDUSW(mx, x operand.Op) { - if inst, err := x86.PADDUSW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMINUD m256 ymm ymm +// VPMINUD ymm ymm ymm +// VPMINUD m128 xmm xmm +// VPMINUD xmm xmm xmm +// VPMINUD m128 xmm k xmm +// VPMINUD m256 ymm k ymm +// VPMINUD xmm xmm k xmm +// VPMINUD ymm ymm k ymm +// VPMINUD m512 zmm k zmm +// VPMINUD m512 zmm zmm +// VPMINUD zmm zmm k zmm +// VPMINUD zmm zmm zmm +// Construct and append a VPMINUD instruction to the active function. +func (c *Context) VPMINUD(ops ...operand.Op) { + c.addinstruction(x86.VPMINUD(ops...)) } -// PADDUSW: Add Packed Unsigned Word Integers with Unsigned Saturation. +// VPMINUD: Minimum of Packed Unsigned Doubleword Integers. // // Forms: // -// PADDUSW xmm xmm -// PADDUSW m128 xmm -// Construct and append a PADDUSW instruction to the active function. +// VPMINUD m256 ymm ymm +// VPMINUD ymm ymm ymm +// VPMINUD m128 xmm xmm +// VPMINUD xmm xmm xmm +// VPMINUD m128 xmm k xmm +// VPMINUD m256 ymm k ymm +// VPMINUD xmm xmm k xmm +// VPMINUD ymm ymm k ymm +// VPMINUD m512 zmm k zmm +// VPMINUD m512 zmm zmm +// VPMINUD zmm zmm k zmm +// VPMINUD zmm zmm zmm +// Construct and append a VPMINUD instruction to the active function. // Operates on the global context. -func PADDUSW(mx, x operand.Op) { ctx.PADDUSW(mx, x) } +func VPMINUD(ops ...operand.Op) { ctx.VPMINUD(ops...) } -// PADDW: Add Packed Word Integers. +// VPMINUD_BCST: Minimum of Packed Unsigned Doubleword Integers (Broadcast). // // Forms: // -// PADDW xmm xmm -// PADDW m128 xmm -// Construct and append a PADDW instruction to the active function. -func (c *Context) PADDW(mx, x operand.Op) { - if inst, err := x86.PADDW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMINUD.BCST m32 xmm k xmm +// VPMINUD.BCST m32 xmm xmm +// VPMINUD.BCST m32 ymm k ymm +// VPMINUD.BCST m32 ymm ymm +// VPMINUD.BCST m32 zmm k zmm +// VPMINUD.BCST m32 zmm zmm +// Construct and append a VPMINUD.BCST instruction to the active function. +func (c *Context) VPMINUD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPMINUD_BCST(ops...)) } -// PADDW: Add Packed Word Integers. +// VPMINUD_BCST: Minimum of Packed Unsigned Doubleword Integers (Broadcast). // // Forms: // -// PADDW xmm xmm -// PADDW m128 xmm -// Construct and append a PADDW instruction to the active function. +// VPMINUD.BCST m32 xmm k xmm +// VPMINUD.BCST m32 xmm xmm +// VPMINUD.BCST m32 ymm k ymm +// VPMINUD.BCST m32 ymm ymm +// VPMINUD.BCST m32 zmm k zmm +// VPMINUD.BCST m32 zmm zmm +// Construct and append a VPMINUD.BCST instruction to the active function. // Operates on the global context. -func PADDW(mx, x operand.Op) { ctx.PADDW(mx, x) } +func VPMINUD_BCST(ops ...operand.Op) { ctx.VPMINUD_BCST(ops...) } -// PALIGNR: Packed Align Right. +// VPMINUD_BCST_Z: Minimum of Packed Unsigned Doubleword Integers (Broadcast, Zeroing Masking). // // Forms: // -// PALIGNR imm8 xmm xmm -// PALIGNR imm8 m128 xmm -// Construct and append a PALIGNR instruction to the active function. -func (c *Context) PALIGNR(i, mx, x operand.Op) { - if inst, err := x86.PALIGNR(i, mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMINUD.BCST.Z m32 xmm k xmm +// VPMINUD.BCST.Z m32 ymm k ymm +// VPMINUD.BCST.Z m32 zmm k zmm +// Construct and append a VPMINUD.BCST.Z instruction to the active function. +func (c *Context) VPMINUD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMINUD_BCST_Z(m, xyz, k, xyz1)) } -// PALIGNR: Packed Align Right. +// VPMINUD_BCST_Z: Minimum of Packed Unsigned Doubleword Integers (Broadcast, Zeroing Masking). // // Forms: // -// PALIGNR imm8 xmm xmm -// PALIGNR imm8 m128 xmm -// Construct and append a PALIGNR instruction to the active function. +// VPMINUD.BCST.Z m32 xmm k xmm +// VPMINUD.BCST.Z m32 ymm k ymm +// VPMINUD.BCST.Z m32 zmm k zmm +// Construct and append a VPMINUD.BCST.Z instruction to the active function. // Operates on the global context. -func PALIGNR(i, mx, x operand.Op) { ctx.PALIGNR(i, mx, x) } +func VPMINUD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPMINUD_BCST_Z(m, xyz, k, xyz1) } -// PAND: Packed Bitwise Logical AND. +// VPMINUD_Z: Minimum of Packed Unsigned Doubleword Integers (Zeroing Masking). // // Forms: // -// PAND xmm xmm -// PAND m128 xmm -// Construct and append a PAND instruction to the active function. -func (c *Context) PAND(mx, x operand.Op) { - if inst, err := x86.PAND(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMINUD.Z m128 xmm k xmm +// VPMINUD.Z m256 ymm k ymm +// VPMINUD.Z xmm xmm k xmm +// VPMINUD.Z ymm ymm k ymm +// VPMINUD.Z m512 zmm k zmm +// VPMINUD.Z zmm zmm k zmm +// Construct and append a VPMINUD.Z instruction to the active function. +func (c *Context) VPMINUD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMINUD_Z(mxyz, xyz, k, xyz1)) } -// PAND: Packed Bitwise Logical AND. +// VPMINUD_Z: Minimum of Packed Unsigned Doubleword Integers (Zeroing Masking). // // Forms: // -// PAND xmm xmm -// PAND m128 xmm -// Construct and append a PAND instruction to the active function. +// VPMINUD.Z m128 xmm k xmm +// VPMINUD.Z m256 ymm k ymm +// VPMINUD.Z xmm xmm k xmm +// VPMINUD.Z ymm ymm k ymm +// VPMINUD.Z m512 zmm k zmm +// VPMINUD.Z zmm zmm k zmm +// Construct and append a VPMINUD.Z instruction to the active function. // Operates on the global context. -func PAND(mx, x operand.Op) { ctx.PAND(mx, x) } +func VPMINUD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPMINUD_Z(mxyz, xyz, k, xyz1) } -// PANDN: Packed Bitwise Logical AND NOT. +// VPMINUQ: Minimum of Packed Unsigned Quadword Integers. // // Forms: // -// PANDN xmm xmm -// PANDN m128 xmm -// Construct and append a PANDN instruction to the active function. -func (c *Context) PANDN(mx, x operand.Op) { - if inst, err := x86.PANDN(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMINUQ m128 xmm k xmm +// VPMINUQ m128 xmm xmm +// VPMINUQ m256 ymm k ymm +// VPMINUQ m256 ymm ymm +// VPMINUQ xmm xmm k xmm +// VPMINUQ xmm xmm xmm +// VPMINUQ ymm ymm k ymm +// VPMINUQ ymm ymm ymm +// VPMINUQ m512 zmm k zmm +// VPMINUQ m512 zmm zmm +// VPMINUQ zmm zmm k zmm +// VPMINUQ zmm zmm zmm +// Construct and append a VPMINUQ instruction to the active function. +func (c *Context) VPMINUQ(ops ...operand.Op) { + c.addinstruction(x86.VPMINUQ(ops...)) } -// PANDN: Packed Bitwise Logical AND NOT. +// VPMINUQ: Minimum of Packed Unsigned Quadword Integers. // // Forms: // -// PANDN xmm xmm -// PANDN m128 xmm -// Construct and append a PANDN instruction to the active function. +// VPMINUQ m128 xmm k xmm +// VPMINUQ m128 xmm xmm +// VPMINUQ m256 ymm k ymm +// VPMINUQ m256 ymm ymm +// VPMINUQ xmm xmm k xmm +// VPMINUQ xmm xmm xmm +// VPMINUQ ymm ymm k ymm +// VPMINUQ ymm ymm ymm +// VPMINUQ m512 zmm k zmm +// VPMINUQ m512 zmm zmm +// VPMINUQ zmm zmm k zmm +// VPMINUQ zmm zmm zmm +// Construct and append a VPMINUQ instruction to the active function. // Operates on the global context. -func PANDN(mx, x operand.Op) { ctx.PANDN(mx, x) } +func VPMINUQ(ops ...operand.Op) { ctx.VPMINUQ(ops...) } -// PAUSE: Spin Loop Hint. +// VPMINUQ_BCST: Minimum of Packed Unsigned Quadword Integers (Broadcast). // // Forms: // -// PAUSE -// Construct and append a PAUSE instruction to the active function. -func (c *Context) PAUSE() { - if inst, err := x86.PAUSE(); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMINUQ.BCST m64 xmm k xmm +// VPMINUQ.BCST m64 xmm xmm +// VPMINUQ.BCST m64 ymm k ymm +// VPMINUQ.BCST m64 ymm ymm +// VPMINUQ.BCST m64 zmm k zmm +// VPMINUQ.BCST m64 zmm zmm +// Construct and append a VPMINUQ.BCST instruction to the active function. +func (c *Context) VPMINUQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPMINUQ_BCST(ops...)) } -// PAUSE: Spin Loop Hint. +// VPMINUQ_BCST: Minimum of Packed Unsigned Quadword Integers (Broadcast). // // Forms: // -// PAUSE -// Construct and append a PAUSE instruction to the active function. +// VPMINUQ.BCST m64 xmm k xmm +// VPMINUQ.BCST m64 xmm xmm +// VPMINUQ.BCST m64 ymm k ymm +// VPMINUQ.BCST m64 ymm ymm +// VPMINUQ.BCST m64 zmm k zmm +// VPMINUQ.BCST m64 zmm zmm +// Construct and append a VPMINUQ.BCST instruction to the active function. // Operates on the global context. -func PAUSE() { ctx.PAUSE() } +func VPMINUQ_BCST(ops ...operand.Op) { ctx.VPMINUQ_BCST(ops...) } -// PAVGB: Average Packed Byte Integers. +// VPMINUQ_BCST_Z: Minimum of Packed Unsigned Quadword Integers (Broadcast, Zeroing Masking). // // Forms: // -// PAVGB xmm xmm -// PAVGB m128 xmm -// Construct and append a PAVGB instruction to the active function. -func (c *Context) PAVGB(mx, x operand.Op) { - if inst, err := x86.PAVGB(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMINUQ.BCST.Z m64 xmm k xmm +// VPMINUQ.BCST.Z m64 ymm k ymm +// VPMINUQ.BCST.Z m64 zmm k zmm +// Construct and append a VPMINUQ.BCST.Z instruction to the active function. +func (c *Context) VPMINUQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMINUQ_BCST_Z(m, xyz, k, xyz1)) } -// PAVGB: Average Packed Byte Integers. +// VPMINUQ_BCST_Z: Minimum of Packed Unsigned Quadword Integers (Broadcast, Zeroing Masking). // // Forms: // -// PAVGB xmm xmm -// PAVGB m128 xmm -// Construct and append a PAVGB instruction to the active function. +// VPMINUQ.BCST.Z m64 xmm k xmm +// VPMINUQ.BCST.Z m64 ymm k ymm +// VPMINUQ.BCST.Z m64 zmm k zmm +// Construct and append a VPMINUQ.BCST.Z instruction to the active function. // Operates on the global context. -func PAVGB(mx, x operand.Op) { ctx.PAVGB(mx, x) } +func VPMINUQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPMINUQ_BCST_Z(m, xyz, k, xyz1) } -// PAVGW: Average Packed Word Integers. +// VPMINUQ_Z: Minimum of Packed Unsigned Quadword Integers (Zeroing Masking). // // Forms: // -// PAVGW xmm xmm -// PAVGW m128 xmm -// Construct and append a PAVGW instruction to the active function. -func (c *Context) PAVGW(mx, x operand.Op) { - if inst, err := x86.PAVGW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMINUQ.Z m128 xmm k xmm +// VPMINUQ.Z m256 ymm k ymm +// VPMINUQ.Z xmm xmm k xmm +// VPMINUQ.Z ymm ymm k ymm +// VPMINUQ.Z m512 zmm k zmm +// VPMINUQ.Z zmm zmm k zmm +// Construct and append a VPMINUQ.Z instruction to the active function. +func (c *Context) VPMINUQ_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMINUQ_Z(mxyz, xyz, k, xyz1)) } -// PAVGW: Average Packed Word Integers. +// VPMINUQ_Z: Minimum of Packed Unsigned Quadword Integers (Zeroing Masking). // // Forms: // -// PAVGW xmm xmm -// PAVGW m128 xmm -// Construct and append a PAVGW instruction to the active function. +// VPMINUQ.Z m128 xmm k xmm +// VPMINUQ.Z m256 ymm k ymm +// VPMINUQ.Z xmm xmm k xmm +// VPMINUQ.Z ymm ymm k ymm +// VPMINUQ.Z m512 zmm k zmm +// VPMINUQ.Z zmm zmm k zmm +// Construct and append a VPMINUQ.Z instruction to the active function. // Operates on the global context. -func PAVGW(mx, x operand.Op) { ctx.PAVGW(mx, x) } +func VPMINUQ_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPMINUQ_Z(mxyz, xyz, k, xyz1) } -// PBLENDVB: Variable Blend Packed Bytes. +// VPMINUW: Minimum of Packed Unsigned Word Integers. // // Forms: // -// PBLENDVB xmm0 xmm xmm -// PBLENDVB xmm0 m128 xmm -// Construct and append a PBLENDVB instruction to the active function. -func (c *Context) PBLENDVB(x, mx, x1 operand.Op) { - if inst, err := x86.PBLENDVB(x, mx, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMINUW m256 ymm ymm +// VPMINUW ymm ymm ymm +// VPMINUW m128 xmm xmm +// VPMINUW xmm xmm xmm +// VPMINUW m128 xmm k xmm +// VPMINUW m256 ymm k ymm +// VPMINUW xmm xmm k xmm +// VPMINUW ymm ymm k ymm +// VPMINUW m512 zmm k zmm +// VPMINUW m512 zmm zmm +// VPMINUW zmm zmm k zmm +// VPMINUW zmm zmm zmm +// Construct and append a VPMINUW instruction to the active function. +func (c *Context) VPMINUW(ops ...operand.Op) { + c.addinstruction(x86.VPMINUW(ops...)) } -// PBLENDVB: Variable Blend Packed Bytes. +// VPMINUW: Minimum of Packed Unsigned Word Integers. // // Forms: // -// PBLENDVB xmm0 xmm xmm -// PBLENDVB xmm0 m128 xmm -// Construct and append a PBLENDVB instruction to the active function. +// VPMINUW m256 ymm ymm +// VPMINUW ymm ymm ymm +// VPMINUW m128 xmm xmm +// VPMINUW xmm xmm xmm +// VPMINUW m128 xmm k xmm +// VPMINUW m256 ymm k ymm +// VPMINUW xmm xmm k xmm +// VPMINUW ymm ymm k ymm +// VPMINUW m512 zmm k zmm +// VPMINUW m512 zmm zmm +// VPMINUW zmm zmm k zmm +// VPMINUW zmm zmm zmm +// Construct and append a VPMINUW instruction to the active function. // Operates on the global context. -func PBLENDVB(x, mx, x1 operand.Op) { ctx.PBLENDVB(x, mx, x1) } +func VPMINUW(ops ...operand.Op) { ctx.VPMINUW(ops...) } -// PBLENDW: Blend Packed Words. +// VPMINUW_Z: Minimum of Packed Unsigned Word Integers (Zeroing Masking). // // Forms: // -// PBLENDW imm8 xmm xmm -// PBLENDW imm8 m128 xmm -// Construct and append a PBLENDW instruction to the active function. -func (c *Context) PBLENDW(i, mx, x operand.Op) { - if inst, err := x86.PBLENDW(i, mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMINUW.Z m128 xmm k xmm +// VPMINUW.Z m256 ymm k ymm +// VPMINUW.Z xmm xmm k xmm +// VPMINUW.Z ymm ymm k ymm +// VPMINUW.Z m512 zmm k zmm +// VPMINUW.Z zmm zmm k zmm +// Construct and append a VPMINUW.Z instruction to the active function. +func (c *Context) VPMINUW_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMINUW_Z(mxyz, xyz, k, xyz1)) } -// PBLENDW: Blend Packed Words. +// VPMINUW_Z: Minimum of Packed Unsigned Word Integers (Zeroing Masking). // // Forms: // -// PBLENDW imm8 xmm xmm -// PBLENDW imm8 m128 xmm -// Construct and append a PBLENDW instruction to the active function. +// VPMINUW.Z m128 xmm k xmm +// VPMINUW.Z m256 ymm k ymm +// VPMINUW.Z xmm xmm k xmm +// VPMINUW.Z ymm ymm k ymm +// VPMINUW.Z m512 zmm k zmm +// VPMINUW.Z zmm zmm k zmm +// Construct and append a VPMINUW.Z instruction to the active function. // Operates on the global context. -func PBLENDW(i, mx, x operand.Op) { ctx.PBLENDW(i, mx, x) } +func VPMINUW_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPMINUW_Z(mxyz, xyz, k, xyz1) } -// PCLMULQDQ: Carry-Less Quadword Multiplication. +// VPMOVB2M: Move Signs of Packed Byte Integers to Mask Register. // // Forms: // -// PCLMULQDQ imm8 xmm xmm -// PCLMULQDQ imm8 m128 xmm -// Construct and append a PCLMULQDQ instruction to the active function. -func (c *Context) PCLMULQDQ(i, mx, x operand.Op) { - if inst, err := x86.PCLMULQDQ(i, mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVB2M xmm k +// VPMOVB2M ymm k +// VPMOVB2M zmm k +// Construct and append a VPMOVB2M instruction to the active function. +func (c *Context) VPMOVB2M(xyz, k operand.Op) { + c.addinstruction(x86.VPMOVB2M(xyz, k)) } -// PCLMULQDQ: Carry-Less Quadword Multiplication. +// VPMOVB2M: Move Signs of Packed Byte Integers to Mask Register. // // Forms: // -// PCLMULQDQ imm8 xmm xmm -// PCLMULQDQ imm8 m128 xmm -// Construct and append a PCLMULQDQ instruction to the active function. +// VPMOVB2M xmm k +// VPMOVB2M ymm k +// VPMOVB2M zmm k +// Construct and append a VPMOVB2M instruction to the active function. // Operates on the global context. -func PCLMULQDQ(i, mx, x operand.Op) { ctx.PCLMULQDQ(i, mx, x) } +func VPMOVB2M(xyz, k operand.Op) { ctx.VPMOVB2M(xyz, k) } -// PCMPEQB: Compare Packed Byte Data for Equality. +// VPMOVD2M: Move Signs of Packed Doubleword Integers to Mask Register. // // Forms: // -// PCMPEQB xmm xmm -// PCMPEQB m128 xmm -// Construct and append a PCMPEQB instruction to the active function. -func (c *Context) PCMPEQB(mx, x operand.Op) { - if inst, err := x86.PCMPEQB(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVD2M xmm k +// VPMOVD2M ymm k +// VPMOVD2M zmm k +// Construct and append a VPMOVD2M instruction to the active function. +func (c *Context) VPMOVD2M(xyz, k operand.Op) { + c.addinstruction(x86.VPMOVD2M(xyz, k)) } -// PCMPEQB: Compare Packed Byte Data for Equality. +// VPMOVD2M: Move Signs of Packed Doubleword Integers to Mask Register. // // Forms: // -// PCMPEQB xmm xmm -// PCMPEQB m128 xmm -// Construct and append a PCMPEQB instruction to the active function. +// VPMOVD2M xmm k +// VPMOVD2M ymm k +// VPMOVD2M zmm k +// Construct and append a VPMOVD2M instruction to the active function. // Operates on the global context. -func PCMPEQB(mx, x operand.Op) { ctx.PCMPEQB(mx, x) } +func VPMOVD2M(xyz, k operand.Op) { ctx.VPMOVD2M(xyz, k) } -// PCMPEQL: Compare Packed Doubleword Data for Equality. +// VPMOVDB: Down Convert Packed Doubleword Values to Byte Values with Truncation. // // Forms: // -// PCMPEQL xmm xmm -// PCMPEQL m128 xmm -// Construct and append a PCMPEQL instruction to the active function. -func (c *Context) PCMPEQL(mx, x operand.Op) { - if inst, err := x86.PCMPEQL(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVDB xmm k m32 +// VPMOVDB xmm k xmm +// VPMOVDB xmm m32 +// VPMOVDB xmm xmm +// VPMOVDB ymm k m64 +// VPMOVDB ymm k xmm +// VPMOVDB ymm m64 +// VPMOVDB ymm xmm +// VPMOVDB zmm k m128 +// VPMOVDB zmm k xmm +// VPMOVDB zmm m128 +// VPMOVDB zmm xmm +// Construct and append a VPMOVDB instruction to the active function. +func (c *Context) VPMOVDB(ops ...operand.Op) { + c.addinstruction(x86.VPMOVDB(ops...)) } -// PCMPEQL: Compare Packed Doubleword Data for Equality. +// VPMOVDB: Down Convert Packed Doubleword Values to Byte Values with Truncation. // // Forms: // -// PCMPEQL xmm xmm -// PCMPEQL m128 xmm -// Construct and append a PCMPEQL instruction to the active function. +// VPMOVDB xmm k m32 +// VPMOVDB xmm k xmm +// VPMOVDB xmm m32 +// VPMOVDB xmm xmm +// VPMOVDB ymm k m64 +// VPMOVDB ymm k xmm +// VPMOVDB ymm m64 +// VPMOVDB ymm xmm +// VPMOVDB zmm k m128 +// VPMOVDB zmm k xmm +// VPMOVDB zmm m128 +// VPMOVDB zmm xmm +// Construct and append a VPMOVDB instruction to the active function. // Operates on the global context. -func PCMPEQL(mx, x operand.Op) { ctx.PCMPEQL(mx, x) } +func VPMOVDB(ops ...operand.Op) { ctx.VPMOVDB(ops...) } -// PCMPEQQ: Compare Packed Quadword Data for Equality. +// VPMOVDB_Z: Down Convert Packed Doubleword Values to Byte Values with Truncation (Zeroing Masking). // // Forms: // -// PCMPEQQ xmm xmm -// PCMPEQQ m128 xmm -// Construct and append a PCMPEQQ instruction to the active function. -func (c *Context) PCMPEQQ(mx, x operand.Op) { - if inst, err := x86.PCMPEQQ(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVDB.Z xmm k m32 +// VPMOVDB.Z xmm k xmm +// VPMOVDB.Z ymm k m64 +// VPMOVDB.Z ymm k xmm +// VPMOVDB.Z zmm k m128 +// VPMOVDB.Z zmm k xmm +// Construct and append a VPMOVDB.Z instruction to the active function. +func (c *Context) VPMOVDB_Z(xyz, k, mx operand.Op) { + c.addinstruction(x86.VPMOVDB_Z(xyz, k, mx)) } -// PCMPEQQ: Compare Packed Quadword Data for Equality. +// VPMOVDB_Z: Down Convert Packed Doubleword Values to Byte Values with Truncation (Zeroing Masking). // // Forms: // -// PCMPEQQ xmm xmm -// PCMPEQQ m128 xmm -// Construct and append a PCMPEQQ instruction to the active function. +// VPMOVDB.Z xmm k m32 +// VPMOVDB.Z xmm k xmm +// VPMOVDB.Z ymm k m64 +// VPMOVDB.Z ymm k xmm +// VPMOVDB.Z zmm k m128 +// VPMOVDB.Z zmm k xmm +// Construct and append a VPMOVDB.Z instruction to the active function. // Operates on the global context. -func PCMPEQQ(mx, x operand.Op) { ctx.PCMPEQQ(mx, x) } +func VPMOVDB_Z(xyz, k, mx operand.Op) { ctx.VPMOVDB_Z(xyz, k, mx) } -// PCMPEQW: Compare Packed Word Data for Equality. +// VPMOVDW: Down Convert Packed Doubleword Values to Word Values with Truncation. // // Forms: // -// PCMPEQW xmm xmm -// PCMPEQW m128 xmm -// Construct and append a PCMPEQW instruction to the active function. -func (c *Context) PCMPEQW(mx, x operand.Op) { - if inst, err := x86.PCMPEQW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVDW xmm k m64 +// VPMOVDW xmm k xmm +// VPMOVDW xmm m64 +// VPMOVDW xmm xmm +// VPMOVDW ymm k m128 +// VPMOVDW ymm k xmm +// VPMOVDW ymm m128 +// VPMOVDW ymm xmm +// VPMOVDW zmm k m256 +// VPMOVDW zmm k ymm +// VPMOVDW zmm m256 +// VPMOVDW zmm ymm +// Construct and append a VPMOVDW instruction to the active function. +func (c *Context) VPMOVDW(ops ...operand.Op) { + c.addinstruction(x86.VPMOVDW(ops...)) } -// PCMPEQW: Compare Packed Word Data for Equality. +// VPMOVDW: Down Convert Packed Doubleword Values to Word Values with Truncation. // // Forms: // -// PCMPEQW xmm xmm -// PCMPEQW m128 xmm -// Construct and append a PCMPEQW instruction to the active function. +// VPMOVDW xmm k m64 +// VPMOVDW xmm k xmm +// VPMOVDW xmm m64 +// VPMOVDW xmm xmm +// VPMOVDW ymm k m128 +// VPMOVDW ymm k xmm +// VPMOVDW ymm m128 +// VPMOVDW ymm xmm +// VPMOVDW zmm k m256 +// VPMOVDW zmm k ymm +// VPMOVDW zmm m256 +// VPMOVDW zmm ymm +// Construct and append a VPMOVDW instruction to the active function. // Operates on the global context. -func PCMPEQW(mx, x operand.Op) { ctx.PCMPEQW(mx, x) } +func VPMOVDW(ops ...operand.Op) { ctx.VPMOVDW(ops...) } -// PCMPESTRI: Packed Compare Explicit Length Strings, Return Index. +// VPMOVDW_Z: Down Convert Packed Doubleword Values to Word Values with Truncation (Zeroing Masking). // // Forms: // -// PCMPESTRI imm8 xmm xmm -// PCMPESTRI imm8 m128 xmm -// Construct and append a PCMPESTRI instruction to the active function. -func (c *Context) PCMPESTRI(i, mx, x operand.Op) { - if inst, err := x86.PCMPESTRI(i, mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVDW.Z xmm k m64 +// VPMOVDW.Z xmm k xmm +// VPMOVDW.Z ymm k m128 +// VPMOVDW.Z ymm k xmm +// VPMOVDW.Z zmm k m256 +// VPMOVDW.Z zmm k ymm +// Construct and append a VPMOVDW.Z instruction to the active function. +func (c *Context) VPMOVDW_Z(xyz, k, mxy operand.Op) { + c.addinstruction(x86.VPMOVDW_Z(xyz, k, mxy)) } -// PCMPESTRI: Packed Compare Explicit Length Strings, Return Index. +// VPMOVDW_Z: Down Convert Packed Doubleword Values to Word Values with Truncation (Zeroing Masking). // // Forms: // -// PCMPESTRI imm8 xmm xmm -// PCMPESTRI imm8 m128 xmm -// Construct and append a PCMPESTRI instruction to the active function. +// VPMOVDW.Z xmm k m64 +// VPMOVDW.Z xmm k xmm +// VPMOVDW.Z ymm k m128 +// VPMOVDW.Z ymm k xmm +// VPMOVDW.Z zmm k m256 +// VPMOVDW.Z zmm k ymm +// Construct and append a VPMOVDW.Z instruction to the active function. // Operates on the global context. -func PCMPESTRI(i, mx, x operand.Op) { ctx.PCMPESTRI(i, mx, x) } +func VPMOVDW_Z(xyz, k, mxy operand.Op) { ctx.VPMOVDW_Z(xyz, k, mxy) } -// PCMPESTRM: Packed Compare Explicit Length Strings, Return Mask. +// VPMOVM2B: Expand Bits of Mask Register to Packed Byte Integers. // // Forms: // -// PCMPESTRM imm8 xmm xmm -// PCMPESTRM imm8 m128 xmm -// Construct and append a PCMPESTRM instruction to the active function. -func (c *Context) PCMPESTRM(i, mx, x operand.Op) { - if inst, err := x86.PCMPESTRM(i, mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVM2B k xmm +// VPMOVM2B k ymm +// VPMOVM2B k zmm +// Construct and append a VPMOVM2B instruction to the active function. +func (c *Context) VPMOVM2B(k, xyz operand.Op) { + c.addinstruction(x86.VPMOVM2B(k, xyz)) } -// PCMPESTRM: Packed Compare Explicit Length Strings, Return Mask. +// VPMOVM2B: Expand Bits of Mask Register to Packed Byte Integers. // // Forms: // -// PCMPESTRM imm8 xmm xmm -// PCMPESTRM imm8 m128 xmm -// Construct and append a PCMPESTRM instruction to the active function. +// VPMOVM2B k xmm +// VPMOVM2B k ymm +// VPMOVM2B k zmm +// Construct and append a VPMOVM2B instruction to the active function. // Operates on the global context. -func PCMPESTRM(i, mx, x operand.Op) { ctx.PCMPESTRM(i, mx, x) } +func VPMOVM2B(k, xyz operand.Op) { ctx.VPMOVM2B(k, xyz) } -// PCMPGTB: Compare Packed Signed Byte Integers for Greater Than. +// VPMOVM2D: Expand Bits of Mask Register to Packed Doubleword Integers. // // Forms: // -// PCMPGTB xmm xmm -// PCMPGTB m128 xmm -// Construct and append a PCMPGTB instruction to the active function. -func (c *Context) PCMPGTB(mx, x operand.Op) { - if inst, err := x86.PCMPGTB(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVM2D k xmm +// VPMOVM2D k ymm +// VPMOVM2D k zmm +// Construct and append a VPMOVM2D instruction to the active function. +func (c *Context) VPMOVM2D(k, xyz operand.Op) { + c.addinstruction(x86.VPMOVM2D(k, xyz)) } -// PCMPGTB: Compare Packed Signed Byte Integers for Greater Than. +// VPMOVM2D: Expand Bits of Mask Register to Packed Doubleword Integers. // // Forms: // -// PCMPGTB xmm xmm -// PCMPGTB m128 xmm -// Construct and append a PCMPGTB instruction to the active function. +// VPMOVM2D k xmm +// VPMOVM2D k ymm +// VPMOVM2D k zmm +// Construct and append a VPMOVM2D instruction to the active function. // Operates on the global context. -func PCMPGTB(mx, x operand.Op) { ctx.PCMPGTB(mx, x) } +func VPMOVM2D(k, xyz operand.Op) { ctx.VPMOVM2D(k, xyz) } -// PCMPGTL: Compare Packed Signed Doubleword Integers for Greater Than. +// VPMOVM2Q: Expand Bits of Mask Register to Packed Quadword Integers. // // Forms: // -// PCMPGTL xmm xmm -// PCMPGTL m128 xmm -// Construct and append a PCMPGTL instruction to the active function. -func (c *Context) PCMPGTL(mx, x operand.Op) { - if inst, err := x86.PCMPGTL(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVM2Q k xmm +// VPMOVM2Q k ymm +// VPMOVM2Q k zmm +// Construct and append a VPMOVM2Q instruction to the active function. +func (c *Context) VPMOVM2Q(k, xyz operand.Op) { + c.addinstruction(x86.VPMOVM2Q(k, xyz)) } -// PCMPGTL: Compare Packed Signed Doubleword Integers for Greater Than. +// VPMOVM2Q: Expand Bits of Mask Register to Packed Quadword Integers. // // Forms: // -// PCMPGTL xmm xmm -// PCMPGTL m128 xmm -// Construct and append a PCMPGTL instruction to the active function. +// VPMOVM2Q k xmm +// VPMOVM2Q k ymm +// VPMOVM2Q k zmm +// Construct and append a VPMOVM2Q instruction to the active function. // Operates on the global context. -func PCMPGTL(mx, x operand.Op) { ctx.PCMPGTL(mx, x) } +func VPMOVM2Q(k, xyz operand.Op) { ctx.VPMOVM2Q(k, xyz) } -// PCMPGTQ: Compare Packed Data for Greater Than. +// VPMOVM2W: Expand Bits of Mask Register to Packed Word Integers. // // Forms: // -// PCMPGTQ xmm xmm -// PCMPGTQ m128 xmm -// Construct and append a PCMPGTQ instruction to the active function. -func (c *Context) PCMPGTQ(mx, x operand.Op) { - if inst, err := x86.PCMPGTQ(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVM2W k xmm +// VPMOVM2W k ymm +// VPMOVM2W k zmm +// Construct and append a VPMOVM2W instruction to the active function. +func (c *Context) VPMOVM2W(k, xyz operand.Op) { + c.addinstruction(x86.VPMOVM2W(k, xyz)) } -// PCMPGTQ: Compare Packed Data for Greater Than. +// VPMOVM2W: Expand Bits of Mask Register to Packed Word Integers. // // Forms: // -// PCMPGTQ xmm xmm -// PCMPGTQ m128 xmm -// Construct and append a PCMPGTQ instruction to the active function. +// VPMOVM2W k xmm +// VPMOVM2W k ymm +// VPMOVM2W k zmm +// Construct and append a VPMOVM2W instruction to the active function. // Operates on the global context. -func PCMPGTQ(mx, x operand.Op) { ctx.PCMPGTQ(mx, x) } +func VPMOVM2W(k, xyz operand.Op) { ctx.VPMOVM2W(k, xyz) } -// PCMPGTW: Compare Packed Signed Word Integers for Greater Than. +// VPMOVMSKB: Move Byte Mask. // // Forms: // -// PCMPGTW xmm xmm -// PCMPGTW m128 xmm -// Construct and append a PCMPGTW instruction to the active function. -func (c *Context) PCMPGTW(mx, x operand.Op) { - if inst, err := x86.PCMPGTW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVMSKB ymm r32 +// VPMOVMSKB xmm r32 +// Construct and append a VPMOVMSKB instruction to the active function. +func (c *Context) VPMOVMSKB(xy, r operand.Op) { + c.addinstruction(x86.VPMOVMSKB(xy, r)) } -// PCMPGTW: Compare Packed Signed Word Integers for Greater Than. +// VPMOVMSKB: Move Byte Mask. // // Forms: // -// PCMPGTW xmm xmm -// PCMPGTW m128 xmm -// Construct and append a PCMPGTW instruction to the active function. +// VPMOVMSKB ymm r32 +// VPMOVMSKB xmm r32 +// Construct and append a VPMOVMSKB instruction to the active function. // Operates on the global context. -func PCMPGTW(mx, x operand.Op) { ctx.PCMPGTW(mx, x) } +func VPMOVMSKB(xy, r operand.Op) { ctx.VPMOVMSKB(xy, r) } -// PCMPISTRI: Packed Compare Implicit Length Strings, Return Index. +// VPMOVQ2M: Move Signs of Packed Quadword Integers to Mask Register. // // Forms: // -// PCMPISTRI imm8 xmm xmm -// PCMPISTRI imm8 m128 xmm -// Construct and append a PCMPISTRI instruction to the active function. -func (c *Context) PCMPISTRI(i, mx, x operand.Op) { - if inst, err := x86.PCMPISTRI(i, mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVQ2M xmm k +// VPMOVQ2M ymm k +// VPMOVQ2M zmm k +// Construct and append a VPMOVQ2M instruction to the active function. +func (c *Context) VPMOVQ2M(xyz, k operand.Op) { + c.addinstruction(x86.VPMOVQ2M(xyz, k)) } -// PCMPISTRI: Packed Compare Implicit Length Strings, Return Index. +// VPMOVQ2M: Move Signs of Packed Quadword Integers to Mask Register. // // Forms: // -// PCMPISTRI imm8 xmm xmm -// PCMPISTRI imm8 m128 xmm -// Construct and append a PCMPISTRI instruction to the active function. +// VPMOVQ2M xmm k +// VPMOVQ2M ymm k +// VPMOVQ2M zmm k +// Construct and append a VPMOVQ2M instruction to the active function. // Operates on the global context. -func PCMPISTRI(i, mx, x operand.Op) { ctx.PCMPISTRI(i, mx, x) } +func VPMOVQ2M(xyz, k operand.Op) { ctx.VPMOVQ2M(xyz, k) } -// PCMPISTRM: Packed Compare Implicit Length Strings, Return Mask. +// VPMOVQB: Down Convert Packed Quadword Values to Byte Values with Truncation. // // Forms: // -// PCMPISTRM imm8 xmm xmm -// PCMPISTRM imm8 m128 xmm -// Construct and append a PCMPISTRM instruction to the active function. -func (c *Context) PCMPISTRM(i, mx, x operand.Op) { - if inst, err := x86.PCMPISTRM(i, mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVQB xmm k m16 +// VPMOVQB xmm k xmm +// VPMOVQB xmm m16 +// VPMOVQB xmm xmm +// VPMOVQB ymm k m32 +// VPMOVQB ymm k xmm +// VPMOVQB ymm m32 +// VPMOVQB ymm xmm +// VPMOVQB zmm k m64 +// VPMOVQB zmm k xmm +// VPMOVQB zmm m64 +// VPMOVQB zmm xmm +// Construct and append a VPMOVQB instruction to the active function. +func (c *Context) VPMOVQB(ops ...operand.Op) { + c.addinstruction(x86.VPMOVQB(ops...)) } -// PCMPISTRM: Packed Compare Implicit Length Strings, Return Mask. +// VPMOVQB: Down Convert Packed Quadword Values to Byte Values with Truncation. // // Forms: // -// PCMPISTRM imm8 xmm xmm -// PCMPISTRM imm8 m128 xmm -// Construct and append a PCMPISTRM instruction to the active function. +// VPMOVQB xmm k m16 +// VPMOVQB xmm k xmm +// VPMOVQB xmm m16 +// VPMOVQB xmm xmm +// VPMOVQB ymm k m32 +// VPMOVQB ymm k xmm +// VPMOVQB ymm m32 +// VPMOVQB ymm xmm +// VPMOVQB zmm k m64 +// VPMOVQB zmm k xmm +// VPMOVQB zmm m64 +// VPMOVQB zmm xmm +// Construct and append a VPMOVQB instruction to the active function. // Operates on the global context. -func PCMPISTRM(i, mx, x operand.Op) { ctx.PCMPISTRM(i, mx, x) } +func VPMOVQB(ops ...operand.Op) { ctx.VPMOVQB(ops...) } -// PDEPL: Parallel Bits Deposit. +// VPMOVQB_Z: Down Convert Packed Quadword Values to Byte Values with Truncation (Zeroing Masking). // // Forms: // -// PDEPL r32 r32 r32 -// PDEPL m32 r32 r32 -// Construct and append a PDEPL instruction to the active function. -func (c *Context) PDEPL(mr, r, r1 operand.Op) { - if inst, err := x86.PDEPL(mr, r, r1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVQB.Z xmm k m16 +// VPMOVQB.Z xmm k xmm +// VPMOVQB.Z ymm k m32 +// VPMOVQB.Z ymm k xmm +// VPMOVQB.Z zmm k m64 +// VPMOVQB.Z zmm k xmm +// Construct and append a VPMOVQB.Z instruction to the active function. +func (c *Context) VPMOVQB_Z(xyz, k, mx operand.Op) { + c.addinstruction(x86.VPMOVQB_Z(xyz, k, mx)) } -// PDEPL: Parallel Bits Deposit. +// VPMOVQB_Z: Down Convert Packed Quadword Values to Byte Values with Truncation (Zeroing Masking). // // Forms: // -// PDEPL r32 r32 r32 -// PDEPL m32 r32 r32 -// Construct and append a PDEPL instruction to the active function. +// VPMOVQB.Z xmm k m16 +// VPMOVQB.Z xmm k xmm +// VPMOVQB.Z ymm k m32 +// VPMOVQB.Z ymm k xmm +// VPMOVQB.Z zmm k m64 +// VPMOVQB.Z zmm k xmm +// Construct and append a VPMOVQB.Z instruction to the active function. // Operates on the global context. -func PDEPL(mr, r, r1 operand.Op) { ctx.PDEPL(mr, r, r1) } +func VPMOVQB_Z(xyz, k, mx operand.Op) { ctx.VPMOVQB_Z(xyz, k, mx) } -// PDEPQ: Parallel Bits Deposit. +// VPMOVQD: Down Convert Packed Quadword Values to Doubleword Values with Truncation. // // Forms: // -// PDEPQ r64 r64 r64 -// PDEPQ m64 r64 r64 -// Construct and append a PDEPQ instruction to the active function. -func (c *Context) PDEPQ(mr, r, r1 operand.Op) { - if inst, err := x86.PDEPQ(mr, r, r1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVQD xmm k m64 +// VPMOVQD xmm k xmm +// VPMOVQD xmm m64 +// VPMOVQD xmm xmm +// VPMOVQD ymm k m128 +// VPMOVQD ymm k xmm +// VPMOVQD ymm m128 +// VPMOVQD ymm xmm +// VPMOVQD zmm k m256 +// VPMOVQD zmm k ymm +// VPMOVQD zmm m256 +// VPMOVQD zmm ymm +// Construct and append a VPMOVQD instruction to the active function. +func (c *Context) VPMOVQD(ops ...operand.Op) { + c.addinstruction(x86.VPMOVQD(ops...)) } -// PDEPQ: Parallel Bits Deposit. +// VPMOVQD: Down Convert Packed Quadword Values to Doubleword Values with Truncation. // // Forms: // -// PDEPQ r64 r64 r64 -// PDEPQ m64 r64 r64 -// Construct and append a PDEPQ instruction to the active function. +// VPMOVQD xmm k m64 +// VPMOVQD xmm k xmm +// VPMOVQD xmm m64 +// VPMOVQD xmm xmm +// VPMOVQD ymm k m128 +// VPMOVQD ymm k xmm +// VPMOVQD ymm m128 +// VPMOVQD ymm xmm +// VPMOVQD zmm k m256 +// VPMOVQD zmm k ymm +// VPMOVQD zmm m256 +// VPMOVQD zmm ymm +// Construct and append a VPMOVQD instruction to the active function. // Operates on the global context. -func PDEPQ(mr, r, r1 operand.Op) { ctx.PDEPQ(mr, r, r1) } +func VPMOVQD(ops ...operand.Op) { ctx.VPMOVQD(ops...) } -// PEXTL: Parallel Bits Extract. +// VPMOVQD_Z: Down Convert Packed Quadword Values to Doubleword Values with Truncation (Zeroing Masking). // // Forms: // -// PEXTL r32 r32 r32 -// PEXTL m32 r32 r32 -// Construct and append a PEXTL instruction to the active function. -func (c *Context) PEXTL(mr, r, r1 operand.Op) { - if inst, err := x86.PEXTL(mr, r, r1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVQD.Z xmm k m64 +// VPMOVQD.Z xmm k xmm +// VPMOVQD.Z ymm k m128 +// VPMOVQD.Z ymm k xmm +// VPMOVQD.Z zmm k m256 +// VPMOVQD.Z zmm k ymm +// Construct and append a VPMOVQD.Z instruction to the active function. +func (c *Context) VPMOVQD_Z(xyz, k, mxy operand.Op) { + c.addinstruction(x86.VPMOVQD_Z(xyz, k, mxy)) } -// PEXTL: Parallel Bits Extract. +// VPMOVQD_Z: Down Convert Packed Quadword Values to Doubleword Values with Truncation (Zeroing Masking). // // Forms: // -// PEXTL r32 r32 r32 -// PEXTL m32 r32 r32 -// Construct and append a PEXTL instruction to the active function. +// VPMOVQD.Z xmm k m64 +// VPMOVQD.Z xmm k xmm +// VPMOVQD.Z ymm k m128 +// VPMOVQD.Z ymm k xmm +// VPMOVQD.Z zmm k m256 +// VPMOVQD.Z zmm k ymm +// Construct and append a VPMOVQD.Z instruction to the active function. // Operates on the global context. -func PEXTL(mr, r, r1 operand.Op) { ctx.PEXTL(mr, r, r1) } +func VPMOVQD_Z(xyz, k, mxy operand.Op) { ctx.VPMOVQD_Z(xyz, k, mxy) } -// PEXTQ: Parallel Bits Extract. +// VPMOVQW: Down Convert Packed Quadword Values to Word Values with Truncation. // // Forms: // -// PEXTQ r64 r64 r64 -// PEXTQ m64 r64 r64 -// Construct and append a PEXTQ instruction to the active function. -func (c *Context) PEXTQ(mr, r, r1 operand.Op) { - if inst, err := x86.PEXTQ(mr, r, r1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVQW xmm k m32 +// VPMOVQW xmm k xmm +// VPMOVQW xmm m32 +// VPMOVQW xmm xmm +// VPMOVQW ymm k m64 +// VPMOVQW ymm k xmm +// VPMOVQW ymm m64 +// VPMOVQW ymm xmm +// VPMOVQW zmm k m128 +// VPMOVQW zmm k xmm +// VPMOVQW zmm m128 +// VPMOVQW zmm xmm +// Construct and append a VPMOVQW instruction to the active function. +func (c *Context) VPMOVQW(ops ...operand.Op) { + c.addinstruction(x86.VPMOVQW(ops...)) } -// PEXTQ: Parallel Bits Extract. +// VPMOVQW: Down Convert Packed Quadword Values to Word Values with Truncation. // // Forms: // -// PEXTQ r64 r64 r64 -// PEXTQ m64 r64 r64 -// Construct and append a PEXTQ instruction to the active function. +// VPMOVQW xmm k m32 +// VPMOVQW xmm k xmm +// VPMOVQW xmm m32 +// VPMOVQW xmm xmm +// VPMOVQW ymm k m64 +// VPMOVQW ymm k xmm +// VPMOVQW ymm m64 +// VPMOVQW ymm xmm +// VPMOVQW zmm k m128 +// VPMOVQW zmm k xmm +// VPMOVQW zmm m128 +// VPMOVQW zmm xmm +// Construct and append a VPMOVQW instruction to the active function. // Operates on the global context. -func PEXTQ(mr, r, r1 operand.Op) { ctx.PEXTQ(mr, r, r1) } +func VPMOVQW(ops ...operand.Op) { ctx.VPMOVQW(ops...) } -// PEXTRB: Extract Byte. +// VPMOVQW_Z: Down Convert Packed Quadword Values to Word Values with Truncation (Zeroing Masking). // // Forms: // -// PEXTRB imm8 xmm r32 -// PEXTRB imm8 xmm m8 -// Construct and append a PEXTRB instruction to the active function. -func (c *Context) PEXTRB(i, x, mr operand.Op) { - if inst, err := x86.PEXTRB(i, x, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVQW.Z xmm k m32 +// VPMOVQW.Z xmm k xmm +// VPMOVQW.Z ymm k m64 +// VPMOVQW.Z ymm k xmm +// VPMOVQW.Z zmm k m128 +// VPMOVQW.Z zmm k xmm +// Construct and append a VPMOVQW.Z instruction to the active function. +func (c *Context) VPMOVQW_Z(xyz, k, mx operand.Op) { + c.addinstruction(x86.VPMOVQW_Z(xyz, k, mx)) } -// PEXTRB: Extract Byte. +// VPMOVQW_Z: Down Convert Packed Quadword Values to Word Values with Truncation (Zeroing Masking). // // Forms: // -// PEXTRB imm8 xmm r32 -// PEXTRB imm8 xmm m8 -// Construct and append a PEXTRB instruction to the active function. +// VPMOVQW.Z xmm k m32 +// VPMOVQW.Z xmm k xmm +// VPMOVQW.Z ymm k m64 +// VPMOVQW.Z ymm k xmm +// VPMOVQW.Z zmm k m128 +// VPMOVQW.Z zmm k xmm +// Construct and append a VPMOVQW.Z instruction to the active function. // Operates on the global context. -func PEXTRB(i, x, mr operand.Op) { ctx.PEXTRB(i, x, mr) } +func VPMOVQW_Z(xyz, k, mx operand.Op) { ctx.VPMOVQW_Z(xyz, k, mx) } -// PEXTRD: Extract Doubleword. +// VPMOVSDB: Down Convert Packed Doubleword Values to Byte Values with Signed Saturation. // // Forms: // -// PEXTRD imm8 xmm r32 -// PEXTRD imm8 xmm m32 -// Construct and append a PEXTRD instruction to the active function. -func (c *Context) PEXTRD(i, x, mr operand.Op) { - if inst, err := x86.PEXTRD(i, x, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVSDB xmm k m32 +// VPMOVSDB xmm k xmm +// VPMOVSDB xmm m32 +// VPMOVSDB xmm xmm +// VPMOVSDB ymm k m64 +// VPMOVSDB ymm k xmm +// VPMOVSDB ymm m64 +// VPMOVSDB ymm xmm +// VPMOVSDB zmm k m128 +// VPMOVSDB zmm k xmm +// VPMOVSDB zmm m128 +// VPMOVSDB zmm xmm +// Construct and append a VPMOVSDB instruction to the active function. +func (c *Context) VPMOVSDB(ops ...operand.Op) { + c.addinstruction(x86.VPMOVSDB(ops...)) } -// PEXTRD: Extract Doubleword. +// VPMOVSDB: Down Convert Packed Doubleword Values to Byte Values with Signed Saturation. // // Forms: // -// PEXTRD imm8 xmm r32 -// PEXTRD imm8 xmm m32 -// Construct and append a PEXTRD instruction to the active function. +// VPMOVSDB xmm k m32 +// VPMOVSDB xmm k xmm +// VPMOVSDB xmm m32 +// VPMOVSDB xmm xmm +// VPMOVSDB ymm k m64 +// VPMOVSDB ymm k xmm +// VPMOVSDB ymm m64 +// VPMOVSDB ymm xmm +// VPMOVSDB zmm k m128 +// VPMOVSDB zmm k xmm +// VPMOVSDB zmm m128 +// VPMOVSDB zmm xmm +// Construct and append a VPMOVSDB instruction to the active function. // Operates on the global context. -func PEXTRD(i, x, mr operand.Op) { ctx.PEXTRD(i, x, mr) } +func VPMOVSDB(ops ...operand.Op) { ctx.VPMOVSDB(ops...) } -// PEXTRQ: Extract Quadword. +// VPMOVSDB_Z: Down Convert Packed Doubleword Values to Byte Values with Signed Saturation (Zeroing Masking). // // Forms: // -// PEXTRQ imm8 xmm r64 -// PEXTRQ imm8 xmm m64 -// Construct and append a PEXTRQ instruction to the active function. -func (c *Context) PEXTRQ(i, x, mr operand.Op) { - if inst, err := x86.PEXTRQ(i, x, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVSDB.Z xmm k m32 +// VPMOVSDB.Z xmm k xmm +// VPMOVSDB.Z ymm k m64 +// VPMOVSDB.Z ymm k xmm +// VPMOVSDB.Z zmm k m128 +// VPMOVSDB.Z zmm k xmm +// Construct and append a VPMOVSDB.Z instruction to the active function. +func (c *Context) VPMOVSDB_Z(xyz, k, mx operand.Op) { + c.addinstruction(x86.VPMOVSDB_Z(xyz, k, mx)) } -// PEXTRQ: Extract Quadword. +// VPMOVSDB_Z: Down Convert Packed Doubleword Values to Byte Values with Signed Saturation (Zeroing Masking). // // Forms: // -// PEXTRQ imm8 xmm r64 -// PEXTRQ imm8 xmm m64 -// Construct and append a PEXTRQ instruction to the active function. +// VPMOVSDB.Z xmm k m32 +// VPMOVSDB.Z xmm k xmm +// VPMOVSDB.Z ymm k m64 +// VPMOVSDB.Z ymm k xmm +// VPMOVSDB.Z zmm k m128 +// VPMOVSDB.Z zmm k xmm +// Construct and append a VPMOVSDB.Z instruction to the active function. // Operates on the global context. -func PEXTRQ(i, x, mr operand.Op) { ctx.PEXTRQ(i, x, mr) } +func VPMOVSDB_Z(xyz, k, mx operand.Op) { ctx.VPMOVSDB_Z(xyz, k, mx) } -// PEXTRW: Extract Word. +// VPMOVSDW: Down Convert Packed Doubleword Values to Word Values with Signed Saturation. // // Forms: // -// PEXTRW imm8 xmm r32 -// PEXTRW imm8 xmm m16 -// Construct and append a PEXTRW instruction to the active function. -func (c *Context) PEXTRW(i, x, mr operand.Op) { - if inst, err := x86.PEXTRW(i, x, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVSDW xmm k m64 +// VPMOVSDW xmm k xmm +// VPMOVSDW xmm m64 +// VPMOVSDW xmm xmm +// VPMOVSDW ymm k m128 +// VPMOVSDW ymm k xmm +// VPMOVSDW ymm m128 +// VPMOVSDW ymm xmm +// VPMOVSDW zmm k m256 +// VPMOVSDW zmm k ymm +// VPMOVSDW zmm m256 +// VPMOVSDW zmm ymm +// Construct and append a VPMOVSDW instruction to the active function. +func (c *Context) VPMOVSDW(ops ...operand.Op) { + c.addinstruction(x86.VPMOVSDW(ops...)) } -// PEXTRW: Extract Word. +// VPMOVSDW: Down Convert Packed Doubleword Values to Word Values with Signed Saturation. // // Forms: // -// PEXTRW imm8 xmm r32 -// PEXTRW imm8 xmm m16 -// Construct and append a PEXTRW instruction to the active function. +// VPMOVSDW xmm k m64 +// VPMOVSDW xmm k xmm +// VPMOVSDW xmm m64 +// VPMOVSDW xmm xmm +// VPMOVSDW ymm k m128 +// VPMOVSDW ymm k xmm +// VPMOVSDW ymm m128 +// VPMOVSDW ymm xmm +// VPMOVSDW zmm k m256 +// VPMOVSDW zmm k ymm +// VPMOVSDW zmm m256 +// VPMOVSDW zmm ymm +// Construct and append a VPMOVSDW instruction to the active function. // Operates on the global context. -func PEXTRW(i, x, mr operand.Op) { ctx.PEXTRW(i, x, mr) } +func VPMOVSDW(ops ...operand.Op) { ctx.VPMOVSDW(ops...) } -// PHADDD: Packed Horizontal Add Doubleword Integer. +// VPMOVSDW_Z: Down Convert Packed Doubleword Values to Word Values with Signed Saturation (Zeroing Masking). // // Forms: // -// PHADDD xmm xmm -// PHADDD m128 xmm -// Construct and append a PHADDD instruction to the active function. -func (c *Context) PHADDD(mx, x operand.Op) { - if inst, err := x86.PHADDD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVSDW.Z xmm k m64 +// VPMOVSDW.Z xmm k xmm +// VPMOVSDW.Z ymm k m128 +// VPMOVSDW.Z ymm k xmm +// VPMOVSDW.Z zmm k m256 +// VPMOVSDW.Z zmm k ymm +// Construct and append a VPMOVSDW.Z instruction to the active function. +func (c *Context) VPMOVSDW_Z(xyz, k, mxy operand.Op) { + c.addinstruction(x86.VPMOVSDW_Z(xyz, k, mxy)) } -// PHADDD: Packed Horizontal Add Doubleword Integer. +// VPMOVSDW_Z: Down Convert Packed Doubleword Values to Word Values with Signed Saturation (Zeroing Masking). // // Forms: // -// PHADDD xmm xmm -// PHADDD m128 xmm -// Construct and append a PHADDD instruction to the active function. +// VPMOVSDW.Z xmm k m64 +// VPMOVSDW.Z xmm k xmm +// VPMOVSDW.Z ymm k m128 +// VPMOVSDW.Z ymm k xmm +// VPMOVSDW.Z zmm k m256 +// VPMOVSDW.Z zmm k ymm +// Construct and append a VPMOVSDW.Z instruction to the active function. // Operates on the global context. -func PHADDD(mx, x operand.Op) { ctx.PHADDD(mx, x) } +func VPMOVSDW_Z(xyz, k, mxy operand.Op) { ctx.VPMOVSDW_Z(xyz, k, mxy) } -// PHADDSW: Packed Horizontal Add Signed Word Integers with Signed Saturation. +// VPMOVSQB: Down Convert Packed Quadword Values to Byte Values with Signed Saturation. // // Forms: // -// PHADDSW xmm xmm -// PHADDSW m128 xmm -// Construct and append a PHADDSW instruction to the active function. -func (c *Context) PHADDSW(mx, x operand.Op) { - if inst, err := x86.PHADDSW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVSQB xmm k m16 +// VPMOVSQB xmm k xmm +// VPMOVSQB xmm m16 +// VPMOVSQB xmm xmm +// VPMOVSQB ymm k m32 +// VPMOVSQB ymm k xmm +// VPMOVSQB ymm m32 +// VPMOVSQB ymm xmm +// VPMOVSQB zmm k m64 +// VPMOVSQB zmm k xmm +// VPMOVSQB zmm m64 +// VPMOVSQB zmm xmm +// Construct and append a VPMOVSQB instruction to the active function. +func (c *Context) VPMOVSQB(ops ...operand.Op) { + c.addinstruction(x86.VPMOVSQB(ops...)) } -// PHADDSW: Packed Horizontal Add Signed Word Integers with Signed Saturation. +// VPMOVSQB: Down Convert Packed Quadword Values to Byte Values with Signed Saturation. // // Forms: // -// PHADDSW xmm xmm -// PHADDSW m128 xmm -// Construct and append a PHADDSW instruction to the active function. +// VPMOVSQB xmm k m16 +// VPMOVSQB xmm k xmm +// VPMOVSQB xmm m16 +// VPMOVSQB xmm xmm +// VPMOVSQB ymm k m32 +// VPMOVSQB ymm k xmm +// VPMOVSQB ymm m32 +// VPMOVSQB ymm xmm +// VPMOVSQB zmm k m64 +// VPMOVSQB zmm k xmm +// VPMOVSQB zmm m64 +// VPMOVSQB zmm xmm +// Construct and append a VPMOVSQB instruction to the active function. // Operates on the global context. -func PHADDSW(mx, x operand.Op) { ctx.PHADDSW(mx, x) } +func VPMOVSQB(ops ...operand.Op) { ctx.VPMOVSQB(ops...) } -// PHADDW: Packed Horizontal Add Word Integers. +// VPMOVSQB_Z: Down Convert Packed Quadword Values to Byte Values with Signed Saturation (Zeroing Masking). // // Forms: // -// PHADDW xmm xmm -// PHADDW m128 xmm -// Construct and append a PHADDW instruction to the active function. -func (c *Context) PHADDW(mx, x operand.Op) { - if inst, err := x86.PHADDW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVSQB.Z xmm k m16 +// VPMOVSQB.Z xmm k xmm +// VPMOVSQB.Z ymm k m32 +// VPMOVSQB.Z ymm k xmm +// VPMOVSQB.Z zmm k m64 +// VPMOVSQB.Z zmm k xmm +// Construct and append a VPMOVSQB.Z instruction to the active function. +func (c *Context) VPMOVSQB_Z(xyz, k, mx operand.Op) { + c.addinstruction(x86.VPMOVSQB_Z(xyz, k, mx)) } -// PHADDW: Packed Horizontal Add Word Integers. +// VPMOVSQB_Z: Down Convert Packed Quadword Values to Byte Values with Signed Saturation (Zeroing Masking). // // Forms: // -// PHADDW xmm xmm -// PHADDW m128 xmm -// Construct and append a PHADDW instruction to the active function. +// VPMOVSQB.Z xmm k m16 +// VPMOVSQB.Z xmm k xmm +// VPMOVSQB.Z ymm k m32 +// VPMOVSQB.Z ymm k xmm +// VPMOVSQB.Z zmm k m64 +// VPMOVSQB.Z zmm k xmm +// Construct and append a VPMOVSQB.Z instruction to the active function. // Operates on the global context. -func PHADDW(mx, x operand.Op) { ctx.PHADDW(mx, x) } +func VPMOVSQB_Z(xyz, k, mx operand.Op) { ctx.VPMOVSQB_Z(xyz, k, mx) } -// PHMINPOSUW: Packed Horizontal Minimum of Unsigned Word Integers. +// VPMOVSQD: Down Convert Packed Quadword Values to Doubleword Values with Signed Saturation. // // Forms: // -// PHMINPOSUW xmm xmm -// PHMINPOSUW m128 xmm -// Construct and append a PHMINPOSUW instruction to the active function. -func (c *Context) PHMINPOSUW(mx, x operand.Op) { - if inst, err := x86.PHMINPOSUW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVSQD xmm k m64 +// VPMOVSQD xmm k xmm +// VPMOVSQD xmm m64 +// VPMOVSQD xmm xmm +// VPMOVSQD ymm k m128 +// VPMOVSQD ymm k xmm +// VPMOVSQD ymm m128 +// VPMOVSQD ymm xmm +// VPMOVSQD zmm k m256 +// VPMOVSQD zmm k ymm +// VPMOVSQD zmm m256 +// VPMOVSQD zmm ymm +// Construct and append a VPMOVSQD instruction to the active function. +func (c *Context) VPMOVSQD(ops ...operand.Op) { + c.addinstruction(x86.VPMOVSQD(ops...)) } -// PHMINPOSUW: Packed Horizontal Minimum of Unsigned Word Integers. +// VPMOVSQD: Down Convert Packed Quadword Values to Doubleword Values with Signed Saturation. // // Forms: // -// PHMINPOSUW xmm xmm -// PHMINPOSUW m128 xmm -// Construct and append a PHMINPOSUW instruction to the active function. +// VPMOVSQD xmm k m64 +// VPMOVSQD xmm k xmm +// VPMOVSQD xmm m64 +// VPMOVSQD xmm xmm +// VPMOVSQD ymm k m128 +// VPMOVSQD ymm k xmm +// VPMOVSQD ymm m128 +// VPMOVSQD ymm xmm +// VPMOVSQD zmm k m256 +// VPMOVSQD zmm k ymm +// VPMOVSQD zmm m256 +// VPMOVSQD zmm ymm +// Construct and append a VPMOVSQD instruction to the active function. // Operates on the global context. -func PHMINPOSUW(mx, x operand.Op) { ctx.PHMINPOSUW(mx, x) } +func VPMOVSQD(ops ...operand.Op) { ctx.VPMOVSQD(ops...) } -// PHSUBD: Packed Horizontal Subtract Doubleword Integers. +// VPMOVSQD_Z: Down Convert Packed Quadword Values to Doubleword Values with Signed Saturation (Zeroing Masking). // // Forms: -// -// PHSUBD xmm xmm -// PHSUBD m128 xmm -// Construct and append a PHSUBD instruction to the active function. -func (c *Context) PHSUBD(mx, x operand.Op) { - if inst, err := x86.PHSUBD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// +// VPMOVSQD.Z xmm k m64 +// VPMOVSQD.Z xmm k xmm +// VPMOVSQD.Z ymm k m128 +// VPMOVSQD.Z ymm k xmm +// VPMOVSQD.Z zmm k m256 +// VPMOVSQD.Z zmm k ymm +// Construct and append a VPMOVSQD.Z instruction to the active function. +func (c *Context) VPMOVSQD_Z(xyz, k, mxy operand.Op) { + c.addinstruction(x86.VPMOVSQD_Z(xyz, k, mxy)) } -// PHSUBD: Packed Horizontal Subtract Doubleword Integers. +// VPMOVSQD_Z: Down Convert Packed Quadword Values to Doubleword Values with Signed Saturation (Zeroing Masking). // // Forms: // -// PHSUBD xmm xmm -// PHSUBD m128 xmm -// Construct and append a PHSUBD instruction to the active function. +// VPMOVSQD.Z xmm k m64 +// VPMOVSQD.Z xmm k xmm +// VPMOVSQD.Z ymm k m128 +// VPMOVSQD.Z ymm k xmm +// VPMOVSQD.Z zmm k m256 +// VPMOVSQD.Z zmm k ymm +// Construct and append a VPMOVSQD.Z instruction to the active function. // Operates on the global context. -func PHSUBD(mx, x operand.Op) { ctx.PHSUBD(mx, x) } +func VPMOVSQD_Z(xyz, k, mxy operand.Op) { ctx.VPMOVSQD_Z(xyz, k, mxy) } -// PHSUBSW: Packed Horizontal Subtract Signed Word Integers with Signed Saturation. +// VPMOVSQW: Down Convert Packed Quadword Values to Word Values with Signed Saturation. // // Forms: // -// PHSUBSW xmm xmm -// PHSUBSW m128 xmm -// Construct and append a PHSUBSW instruction to the active function. -func (c *Context) PHSUBSW(mx, x operand.Op) { - if inst, err := x86.PHSUBSW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVSQW xmm k m32 +// VPMOVSQW xmm k xmm +// VPMOVSQW xmm m32 +// VPMOVSQW xmm xmm +// VPMOVSQW ymm k m64 +// VPMOVSQW ymm k xmm +// VPMOVSQW ymm m64 +// VPMOVSQW ymm xmm +// VPMOVSQW zmm k m128 +// VPMOVSQW zmm k xmm +// VPMOVSQW zmm m128 +// VPMOVSQW zmm xmm +// Construct and append a VPMOVSQW instruction to the active function. +func (c *Context) VPMOVSQW(ops ...operand.Op) { + c.addinstruction(x86.VPMOVSQW(ops...)) } -// PHSUBSW: Packed Horizontal Subtract Signed Word Integers with Signed Saturation. +// VPMOVSQW: Down Convert Packed Quadword Values to Word Values with Signed Saturation. // // Forms: // -// PHSUBSW xmm xmm -// PHSUBSW m128 xmm -// Construct and append a PHSUBSW instruction to the active function. +// VPMOVSQW xmm k m32 +// VPMOVSQW xmm k xmm +// VPMOVSQW xmm m32 +// VPMOVSQW xmm xmm +// VPMOVSQW ymm k m64 +// VPMOVSQW ymm k xmm +// VPMOVSQW ymm m64 +// VPMOVSQW ymm xmm +// VPMOVSQW zmm k m128 +// VPMOVSQW zmm k xmm +// VPMOVSQW zmm m128 +// VPMOVSQW zmm xmm +// Construct and append a VPMOVSQW instruction to the active function. // Operates on the global context. -func PHSUBSW(mx, x operand.Op) { ctx.PHSUBSW(mx, x) } +func VPMOVSQW(ops ...operand.Op) { ctx.VPMOVSQW(ops...) } -// PHSUBW: Packed Horizontal Subtract Word Integers. +// VPMOVSQW_Z: Down Convert Packed Quadword Values to Word Values with Signed Saturation (Zeroing Masking). // // Forms: // -// PHSUBW xmm xmm -// PHSUBW m128 xmm -// Construct and append a PHSUBW instruction to the active function. -func (c *Context) PHSUBW(mx, x operand.Op) { - if inst, err := x86.PHSUBW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVSQW.Z xmm k m32 +// VPMOVSQW.Z xmm k xmm +// VPMOVSQW.Z ymm k m64 +// VPMOVSQW.Z ymm k xmm +// VPMOVSQW.Z zmm k m128 +// VPMOVSQW.Z zmm k xmm +// Construct and append a VPMOVSQW.Z instruction to the active function. +func (c *Context) VPMOVSQW_Z(xyz, k, mx operand.Op) { + c.addinstruction(x86.VPMOVSQW_Z(xyz, k, mx)) } -// PHSUBW: Packed Horizontal Subtract Word Integers. +// VPMOVSQW_Z: Down Convert Packed Quadword Values to Word Values with Signed Saturation (Zeroing Masking). // // Forms: // -// PHSUBW xmm xmm -// PHSUBW m128 xmm -// Construct and append a PHSUBW instruction to the active function. +// VPMOVSQW.Z xmm k m32 +// VPMOVSQW.Z xmm k xmm +// VPMOVSQW.Z ymm k m64 +// VPMOVSQW.Z ymm k xmm +// VPMOVSQW.Z zmm k m128 +// VPMOVSQW.Z zmm k xmm +// Construct and append a VPMOVSQW.Z instruction to the active function. // Operates on the global context. -func PHSUBW(mx, x operand.Op) { ctx.PHSUBW(mx, x) } +func VPMOVSQW_Z(xyz, k, mx operand.Op) { ctx.VPMOVSQW_Z(xyz, k, mx) } -// PINSRB: Insert Byte. +// VPMOVSWB: Down Convert Packed Word Values to Byte Values with Signed Saturation. // // Forms: // -// PINSRB imm8 r32 xmm -// PINSRB imm8 m8 xmm -// Construct and append a PINSRB instruction to the active function. -func (c *Context) PINSRB(i, mr, x operand.Op) { - if inst, err := x86.PINSRB(i, mr, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVSWB xmm k m64 +// VPMOVSWB xmm k xmm +// VPMOVSWB xmm m64 +// VPMOVSWB xmm xmm +// VPMOVSWB ymm k m128 +// VPMOVSWB ymm k xmm +// VPMOVSWB ymm m128 +// VPMOVSWB ymm xmm +// VPMOVSWB zmm k m256 +// VPMOVSWB zmm k ymm +// VPMOVSWB zmm m256 +// VPMOVSWB zmm ymm +// Construct and append a VPMOVSWB instruction to the active function. +func (c *Context) VPMOVSWB(ops ...operand.Op) { + c.addinstruction(x86.VPMOVSWB(ops...)) } -// PINSRB: Insert Byte. +// VPMOVSWB: Down Convert Packed Word Values to Byte Values with Signed Saturation. // // Forms: // -// PINSRB imm8 r32 xmm -// PINSRB imm8 m8 xmm -// Construct and append a PINSRB instruction to the active function. +// VPMOVSWB xmm k m64 +// VPMOVSWB xmm k xmm +// VPMOVSWB xmm m64 +// VPMOVSWB xmm xmm +// VPMOVSWB ymm k m128 +// VPMOVSWB ymm k xmm +// VPMOVSWB ymm m128 +// VPMOVSWB ymm xmm +// VPMOVSWB zmm k m256 +// VPMOVSWB zmm k ymm +// VPMOVSWB zmm m256 +// VPMOVSWB zmm ymm +// Construct and append a VPMOVSWB instruction to the active function. // Operates on the global context. -func PINSRB(i, mr, x operand.Op) { ctx.PINSRB(i, mr, x) } +func VPMOVSWB(ops ...operand.Op) { ctx.VPMOVSWB(ops...) } -// PINSRD: Insert Doubleword. +// VPMOVSWB_Z: Down Convert Packed Word Values to Byte Values with Signed Saturation (Zeroing Masking). // // Forms: // -// PINSRD imm8 r32 xmm -// PINSRD imm8 m32 xmm -// Construct and append a PINSRD instruction to the active function. -func (c *Context) PINSRD(i, mr, x operand.Op) { - if inst, err := x86.PINSRD(i, mr, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVSWB.Z xmm k m64 +// VPMOVSWB.Z xmm k xmm +// VPMOVSWB.Z ymm k m128 +// VPMOVSWB.Z ymm k xmm +// VPMOVSWB.Z zmm k m256 +// VPMOVSWB.Z zmm k ymm +// Construct and append a VPMOVSWB.Z instruction to the active function. +func (c *Context) VPMOVSWB_Z(xyz, k, mxy operand.Op) { + c.addinstruction(x86.VPMOVSWB_Z(xyz, k, mxy)) } -// PINSRD: Insert Doubleword. +// VPMOVSWB_Z: Down Convert Packed Word Values to Byte Values with Signed Saturation (Zeroing Masking). // // Forms: // -// PINSRD imm8 r32 xmm -// PINSRD imm8 m32 xmm -// Construct and append a PINSRD instruction to the active function. +// VPMOVSWB.Z xmm k m64 +// VPMOVSWB.Z xmm k xmm +// VPMOVSWB.Z ymm k m128 +// VPMOVSWB.Z ymm k xmm +// VPMOVSWB.Z zmm k m256 +// VPMOVSWB.Z zmm k ymm +// Construct and append a VPMOVSWB.Z instruction to the active function. // Operates on the global context. -func PINSRD(i, mr, x operand.Op) { ctx.PINSRD(i, mr, x) } +func VPMOVSWB_Z(xyz, k, mxy operand.Op) { ctx.VPMOVSWB_Z(xyz, k, mxy) } -// PINSRQ: Insert Quadword. +// VPMOVSXBD: Move Packed Byte Integers to Doubleword Integers with Sign Extension. // // Forms: // -// PINSRQ imm8 r64 xmm -// PINSRQ imm8 m64 xmm -// Construct and append a PINSRQ instruction to the active function. -func (c *Context) PINSRQ(i, mr, x operand.Op) { - if inst, err := x86.PINSRQ(i, mr, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVSXBD m64 ymm +// VPMOVSXBD xmm ymm +// VPMOVSXBD m32 xmm +// VPMOVSXBD xmm xmm +// VPMOVSXBD m32 k xmm +// VPMOVSXBD m64 k ymm +// VPMOVSXBD xmm k xmm +// VPMOVSXBD xmm k ymm +// VPMOVSXBD m128 k zmm +// VPMOVSXBD m128 zmm +// VPMOVSXBD xmm k zmm +// VPMOVSXBD xmm zmm +// Construct and append a VPMOVSXBD instruction to the active function. +func (c *Context) VPMOVSXBD(ops ...operand.Op) { + c.addinstruction(x86.VPMOVSXBD(ops...)) } -// PINSRQ: Insert Quadword. +// VPMOVSXBD: Move Packed Byte Integers to Doubleword Integers with Sign Extension. // // Forms: // -// PINSRQ imm8 r64 xmm -// PINSRQ imm8 m64 xmm -// Construct and append a PINSRQ instruction to the active function. +// VPMOVSXBD m64 ymm +// VPMOVSXBD xmm ymm +// VPMOVSXBD m32 xmm +// VPMOVSXBD xmm xmm +// VPMOVSXBD m32 k xmm +// VPMOVSXBD m64 k ymm +// VPMOVSXBD xmm k xmm +// VPMOVSXBD xmm k ymm +// VPMOVSXBD m128 k zmm +// VPMOVSXBD m128 zmm +// VPMOVSXBD xmm k zmm +// VPMOVSXBD xmm zmm +// Construct and append a VPMOVSXBD instruction to the active function. // Operates on the global context. -func PINSRQ(i, mr, x operand.Op) { ctx.PINSRQ(i, mr, x) } +func VPMOVSXBD(ops ...operand.Op) { ctx.VPMOVSXBD(ops...) } -// PINSRW: Insert Word. +// VPMOVSXBD_Z: Move Packed Byte Integers to Doubleword Integers with Sign Extension (Zeroing Masking). // // Forms: // -// PINSRW imm8 r32 xmm -// PINSRW imm8 m16 xmm -// Construct and append a PINSRW instruction to the active function. -func (c *Context) PINSRW(i, mr, x operand.Op) { - if inst, err := x86.PINSRW(i, mr, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVSXBD.Z m32 k xmm +// VPMOVSXBD.Z m64 k ymm +// VPMOVSXBD.Z xmm k xmm +// VPMOVSXBD.Z xmm k ymm +// VPMOVSXBD.Z m128 k zmm +// VPMOVSXBD.Z xmm k zmm +// Construct and append a VPMOVSXBD.Z instruction to the active function. +func (c *Context) VPMOVSXBD_Z(mx, k, xyz operand.Op) { + c.addinstruction(x86.VPMOVSXBD_Z(mx, k, xyz)) } -// PINSRW: Insert Word. +// VPMOVSXBD_Z: Move Packed Byte Integers to Doubleword Integers with Sign Extension (Zeroing Masking). // // Forms: // -// PINSRW imm8 r32 xmm -// PINSRW imm8 m16 xmm -// Construct and append a PINSRW instruction to the active function. +// VPMOVSXBD.Z m32 k xmm +// VPMOVSXBD.Z m64 k ymm +// VPMOVSXBD.Z xmm k xmm +// VPMOVSXBD.Z xmm k ymm +// VPMOVSXBD.Z m128 k zmm +// VPMOVSXBD.Z xmm k zmm +// Construct and append a VPMOVSXBD.Z instruction to the active function. // Operates on the global context. -func PINSRW(i, mr, x operand.Op) { ctx.PINSRW(i, mr, x) } +func VPMOVSXBD_Z(mx, k, xyz operand.Op) { ctx.VPMOVSXBD_Z(mx, k, xyz) } -// PMADDUBSW: Multiply and Add Packed Signed and Unsigned Byte Integers. +// VPMOVSXBQ: Move Packed Byte Integers to Quadword Integers with Sign Extension. // // Forms: // -// PMADDUBSW xmm xmm -// PMADDUBSW m128 xmm -// Construct and append a PMADDUBSW instruction to the active function. -func (c *Context) PMADDUBSW(mx, x operand.Op) { - if inst, err := x86.PMADDUBSW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVSXBQ m32 ymm +// VPMOVSXBQ xmm ymm +// VPMOVSXBQ m16 xmm +// VPMOVSXBQ xmm xmm +// VPMOVSXBQ m16 k xmm +// VPMOVSXBQ m32 k ymm +// VPMOVSXBQ xmm k xmm +// VPMOVSXBQ xmm k ymm +// VPMOVSXBQ m64 k zmm +// VPMOVSXBQ m64 zmm +// VPMOVSXBQ xmm k zmm +// VPMOVSXBQ xmm zmm +// Construct and append a VPMOVSXBQ instruction to the active function. +func (c *Context) VPMOVSXBQ(ops ...operand.Op) { + c.addinstruction(x86.VPMOVSXBQ(ops...)) } -// PMADDUBSW: Multiply and Add Packed Signed and Unsigned Byte Integers. +// VPMOVSXBQ: Move Packed Byte Integers to Quadword Integers with Sign Extension. // // Forms: // -// PMADDUBSW xmm xmm -// PMADDUBSW m128 xmm -// Construct and append a PMADDUBSW instruction to the active function. +// VPMOVSXBQ m32 ymm +// VPMOVSXBQ xmm ymm +// VPMOVSXBQ m16 xmm +// VPMOVSXBQ xmm xmm +// VPMOVSXBQ m16 k xmm +// VPMOVSXBQ m32 k ymm +// VPMOVSXBQ xmm k xmm +// VPMOVSXBQ xmm k ymm +// VPMOVSXBQ m64 k zmm +// VPMOVSXBQ m64 zmm +// VPMOVSXBQ xmm k zmm +// VPMOVSXBQ xmm zmm +// Construct and append a VPMOVSXBQ instruction to the active function. // Operates on the global context. -func PMADDUBSW(mx, x operand.Op) { ctx.PMADDUBSW(mx, x) } +func VPMOVSXBQ(ops ...operand.Op) { ctx.VPMOVSXBQ(ops...) } -// PMADDWL: Multiply and Add Packed Signed Word Integers. +// VPMOVSXBQ_Z: Move Packed Byte Integers to Quadword Integers with Sign Extension (Zeroing Masking). // // Forms: // -// PMADDWL xmm xmm -// PMADDWL m128 xmm -// Construct and append a PMADDWL instruction to the active function. -func (c *Context) PMADDWL(mx, x operand.Op) { - if inst, err := x86.PMADDWL(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVSXBQ.Z m16 k xmm +// VPMOVSXBQ.Z m32 k ymm +// VPMOVSXBQ.Z xmm k xmm +// VPMOVSXBQ.Z xmm k ymm +// VPMOVSXBQ.Z m64 k zmm +// VPMOVSXBQ.Z xmm k zmm +// Construct and append a VPMOVSXBQ.Z instruction to the active function. +func (c *Context) VPMOVSXBQ_Z(mx, k, xyz operand.Op) { + c.addinstruction(x86.VPMOVSXBQ_Z(mx, k, xyz)) } -// PMADDWL: Multiply and Add Packed Signed Word Integers. +// VPMOVSXBQ_Z: Move Packed Byte Integers to Quadword Integers with Sign Extension (Zeroing Masking). // // Forms: // -// PMADDWL xmm xmm -// PMADDWL m128 xmm -// Construct and append a PMADDWL instruction to the active function. +// VPMOVSXBQ.Z m16 k xmm +// VPMOVSXBQ.Z m32 k ymm +// VPMOVSXBQ.Z xmm k xmm +// VPMOVSXBQ.Z xmm k ymm +// VPMOVSXBQ.Z m64 k zmm +// VPMOVSXBQ.Z xmm k zmm +// Construct and append a VPMOVSXBQ.Z instruction to the active function. // Operates on the global context. -func PMADDWL(mx, x operand.Op) { ctx.PMADDWL(mx, x) } +func VPMOVSXBQ_Z(mx, k, xyz operand.Op) { ctx.VPMOVSXBQ_Z(mx, k, xyz) } -// PMAXSB: Maximum of Packed Signed Byte Integers. +// VPMOVSXBW: Move Packed Byte Integers to Word Integers with Sign Extension. // // Forms: // -// PMAXSB xmm xmm -// PMAXSB m128 xmm -// Construct and append a PMAXSB instruction to the active function. -func (c *Context) PMAXSB(mx, x operand.Op) { - if inst, err := x86.PMAXSB(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVSXBW m128 ymm +// VPMOVSXBW xmm ymm +// VPMOVSXBW m64 xmm +// VPMOVSXBW xmm xmm +// VPMOVSXBW m128 k ymm +// VPMOVSXBW m64 k xmm +// VPMOVSXBW xmm k xmm +// VPMOVSXBW xmm k ymm +// VPMOVSXBW m256 k zmm +// VPMOVSXBW m256 zmm +// VPMOVSXBW ymm k zmm +// VPMOVSXBW ymm zmm +// Construct and append a VPMOVSXBW instruction to the active function. +func (c *Context) VPMOVSXBW(ops ...operand.Op) { + c.addinstruction(x86.VPMOVSXBW(ops...)) } -// PMAXSB: Maximum of Packed Signed Byte Integers. +// VPMOVSXBW: Move Packed Byte Integers to Word Integers with Sign Extension. // // Forms: // -// PMAXSB xmm xmm -// PMAXSB m128 xmm -// Construct and append a PMAXSB instruction to the active function. +// VPMOVSXBW m128 ymm +// VPMOVSXBW xmm ymm +// VPMOVSXBW m64 xmm +// VPMOVSXBW xmm xmm +// VPMOVSXBW m128 k ymm +// VPMOVSXBW m64 k xmm +// VPMOVSXBW xmm k xmm +// VPMOVSXBW xmm k ymm +// VPMOVSXBW m256 k zmm +// VPMOVSXBW m256 zmm +// VPMOVSXBW ymm k zmm +// VPMOVSXBW ymm zmm +// Construct and append a VPMOVSXBW instruction to the active function. // Operates on the global context. -func PMAXSB(mx, x operand.Op) { ctx.PMAXSB(mx, x) } +func VPMOVSXBW(ops ...operand.Op) { ctx.VPMOVSXBW(ops...) } -// PMAXSD: Maximum of Packed Signed Doubleword Integers. +// VPMOVSXBW_Z: Move Packed Byte Integers to Word Integers with Sign Extension (Zeroing Masking). // // Forms: // -// PMAXSD xmm xmm -// PMAXSD m128 xmm -// Construct and append a PMAXSD instruction to the active function. -func (c *Context) PMAXSD(mx, x operand.Op) { - if inst, err := x86.PMAXSD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVSXBW.Z m128 k ymm +// VPMOVSXBW.Z m64 k xmm +// VPMOVSXBW.Z xmm k xmm +// VPMOVSXBW.Z xmm k ymm +// VPMOVSXBW.Z m256 k zmm +// VPMOVSXBW.Z ymm k zmm +// Construct and append a VPMOVSXBW.Z instruction to the active function. +func (c *Context) VPMOVSXBW_Z(mxy, k, xyz operand.Op) { + c.addinstruction(x86.VPMOVSXBW_Z(mxy, k, xyz)) } -// PMAXSD: Maximum of Packed Signed Doubleword Integers. +// VPMOVSXBW_Z: Move Packed Byte Integers to Word Integers with Sign Extension (Zeroing Masking). // // Forms: // -// PMAXSD xmm xmm -// PMAXSD m128 xmm -// Construct and append a PMAXSD instruction to the active function. +// VPMOVSXBW.Z m128 k ymm +// VPMOVSXBW.Z m64 k xmm +// VPMOVSXBW.Z xmm k xmm +// VPMOVSXBW.Z xmm k ymm +// VPMOVSXBW.Z m256 k zmm +// VPMOVSXBW.Z ymm k zmm +// Construct and append a VPMOVSXBW.Z instruction to the active function. // Operates on the global context. -func PMAXSD(mx, x operand.Op) { ctx.PMAXSD(mx, x) } +func VPMOVSXBW_Z(mxy, k, xyz operand.Op) { ctx.VPMOVSXBW_Z(mxy, k, xyz) } -// PMAXSW: Maximum of Packed Signed Word Integers. +// VPMOVSXDQ: Move Packed Doubleword Integers to Quadword Integers with Sign Extension. // // Forms: // -// PMAXSW xmm xmm -// PMAXSW m128 xmm -// Construct and append a PMAXSW instruction to the active function. -func (c *Context) PMAXSW(mx, x operand.Op) { - if inst, err := x86.PMAXSW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVSXDQ m128 ymm +// VPMOVSXDQ xmm ymm +// VPMOVSXDQ m64 xmm +// VPMOVSXDQ xmm xmm +// VPMOVSXDQ m128 k ymm +// VPMOVSXDQ m64 k xmm +// VPMOVSXDQ xmm k xmm +// VPMOVSXDQ xmm k ymm +// VPMOVSXDQ m256 k zmm +// VPMOVSXDQ m256 zmm +// VPMOVSXDQ ymm k zmm +// VPMOVSXDQ ymm zmm +// Construct and append a VPMOVSXDQ instruction to the active function. +func (c *Context) VPMOVSXDQ(ops ...operand.Op) { + c.addinstruction(x86.VPMOVSXDQ(ops...)) } -// PMAXSW: Maximum of Packed Signed Word Integers. +// VPMOVSXDQ: Move Packed Doubleword Integers to Quadword Integers with Sign Extension. // // Forms: // -// PMAXSW xmm xmm -// PMAXSW m128 xmm -// Construct and append a PMAXSW instruction to the active function. +// VPMOVSXDQ m128 ymm +// VPMOVSXDQ xmm ymm +// VPMOVSXDQ m64 xmm +// VPMOVSXDQ xmm xmm +// VPMOVSXDQ m128 k ymm +// VPMOVSXDQ m64 k xmm +// VPMOVSXDQ xmm k xmm +// VPMOVSXDQ xmm k ymm +// VPMOVSXDQ m256 k zmm +// VPMOVSXDQ m256 zmm +// VPMOVSXDQ ymm k zmm +// VPMOVSXDQ ymm zmm +// Construct and append a VPMOVSXDQ instruction to the active function. // Operates on the global context. -func PMAXSW(mx, x operand.Op) { ctx.PMAXSW(mx, x) } +func VPMOVSXDQ(ops ...operand.Op) { ctx.VPMOVSXDQ(ops...) } -// PMAXUB: Maximum of Packed Unsigned Byte Integers. +// VPMOVSXDQ_Z: Move Packed Doubleword Integers to Quadword Integers with Sign Extension (Zeroing Masking). // // Forms: // -// PMAXUB xmm xmm -// PMAXUB m128 xmm -// Construct and append a PMAXUB instruction to the active function. -func (c *Context) PMAXUB(mx, x operand.Op) { - if inst, err := x86.PMAXUB(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVSXDQ.Z m128 k ymm +// VPMOVSXDQ.Z m64 k xmm +// VPMOVSXDQ.Z xmm k xmm +// VPMOVSXDQ.Z xmm k ymm +// VPMOVSXDQ.Z m256 k zmm +// VPMOVSXDQ.Z ymm k zmm +// Construct and append a VPMOVSXDQ.Z instruction to the active function. +func (c *Context) VPMOVSXDQ_Z(mxy, k, xyz operand.Op) { + c.addinstruction(x86.VPMOVSXDQ_Z(mxy, k, xyz)) } -// PMAXUB: Maximum of Packed Unsigned Byte Integers. +// VPMOVSXDQ_Z: Move Packed Doubleword Integers to Quadword Integers with Sign Extension (Zeroing Masking). // // Forms: // -// PMAXUB xmm xmm -// PMAXUB m128 xmm -// Construct and append a PMAXUB instruction to the active function. +// VPMOVSXDQ.Z m128 k ymm +// VPMOVSXDQ.Z m64 k xmm +// VPMOVSXDQ.Z xmm k xmm +// VPMOVSXDQ.Z xmm k ymm +// VPMOVSXDQ.Z m256 k zmm +// VPMOVSXDQ.Z ymm k zmm +// Construct and append a VPMOVSXDQ.Z instruction to the active function. // Operates on the global context. -func PMAXUB(mx, x operand.Op) { ctx.PMAXUB(mx, x) } +func VPMOVSXDQ_Z(mxy, k, xyz operand.Op) { ctx.VPMOVSXDQ_Z(mxy, k, xyz) } -// PMAXUD: Maximum of Packed Unsigned Doubleword Integers. +// VPMOVSXWD: Move Packed Word Integers to Doubleword Integers with Sign Extension. // // Forms: // -// PMAXUD xmm xmm -// PMAXUD m128 xmm -// Construct and append a PMAXUD instruction to the active function. -func (c *Context) PMAXUD(mx, x operand.Op) { - if inst, err := x86.PMAXUD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVSXWD m128 ymm +// VPMOVSXWD xmm ymm +// VPMOVSXWD m64 xmm +// VPMOVSXWD xmm xmm +// VPMOVSXWD m128 k ymm +// VPMOVSXWD m64 k xmm +// VPMOVSXWD xmm k xmm +// VPMOVSXWD xmm k ymm +// VPMOVSXWD m256 k zmm +// VPMOVSXWD m256 zmm +// VPMOVSXWD ymm k zmm +// VPMOVSXWD ymm zmm +// Construct and append a VPMOVSXWD instruction to the active function. +func (c *Context) VPMOVSXWD(ops ...operand.Op) { + c.addinstruction(x86.VPMOVSXWD(ops...)) } -// PMAXUD: Maximum of Packed Unsigned Doubleword Integers. +// VPMOVSXWD: Move Packed Word Integers to Doubleword Integers with Sign Extension. // // Forms: // -// PMAXUD xmm xmm -// PMAXUD m128 xmm -// Construct and append a PMAXUD instruction to the active function. +// VPMOVSXWD m128 ymm +// VPMOVSXWD xmm ymm +// VPMOVSXWD m64 xmm +// VPMOVSXWD xmm xmm +// VPMOVSXWD m128 k ymm +// VPMOVSXWD m64 k xmm +// VPMOVSXWD xmm k xmm +// VPMOVSXWD xmm k ymm +// VPMOVSXWD m256 k zmm +// VPMOVSXWD m256 zmm +// VPMOVSXWD ymm k zmm +// VPMOVSXWD ymm zmm +// Construct and append a VPMOVSXWD instruction to the active function. // Operates on the global context. -func PMAXUD(mx, x operand.Op) { ctx.PMAXUD(mx, x) } +func VPMOVSXWD(ops ...operand.Op) { ctx.VPMOVSXWD(ops...) } -// PMAXUW: Maximum of Packed Unsigned Word Integers. +// VPMOVSXWD_Z: Move Packed Word Integers to Doubleword Integers with Sign Extension (Zeroing Masking). // // Forms: // -// PMAXUW xmm xmm -// PMAXUW m128 xmm -// Construct and append a PMAXUW instruction to the active function. -func (c *Context) PMAXUW(mx, x operand.Op) { - if inst, err := x86.PMAXUW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVSXWD.Z m128 k ymm +// VPMOVSXWD.Z m64 k xmm +// VPMOVSXWD.Z xmm k xmm +// VPMOVSXWD.Z xmm k ymm +// VPMOVSXWD.Z m256 k zmm +// VPMOVSXWD.Z ymm k zmm +// Construct and append a VPMOVSXWD.Z instruction to the active function. +func (c *Context) VPMOVSXWD_Z(mxy, k, xyz operand.Op) { + c.addinstruction(x86.VPMOVSXWD_Z(mxy, k, xyz)) } -// PMAXUW: Maximum of Packed Unsigned Word Integers. +// VPMOVSXWD_Z: Move Packed Word Integers to Doubleword Integers with Sign Extension (Zeroing Masking). // // Forms: // -// PMAXUW xmm xmm -// PMAXUW m128 xmm -// Construct and append a PMAXUW instruction to the active function. +// VPMOVSXWD.Z m128 k ymm +// VPMOVSXWD.Z m64 k xmm +// VPMOVSXWD.Z xmm k xmm +// VPMOVSXWD.Z xmm k ymm +// VPMOVSXWD.Z m256 k zmm +// VPMOVSXWD.Z ymm k zmm +// Construct and append a VPMOVSXWD.Z instruction to the active function. // Operates on the global context. -func PMAXUW(mx, x operand.Op) { ctx.PMAXUW(mx, x) } +func VPMOVSXWD_Z(mxy, k, xyz operand.Op) { ctx.VPMOVSXWD_Z(mxy, k, xyz) } -// PMINSB: Minimum of Packed Signed Byte Integers. +// VPMOVSXWQ: Move Packed Word Integers to Quadword Integers with Sign Extension. // // Forms: // -// PMINSB xmm xmm -// PMINSB m128 xmm -// Construct and append a PMINSB instruction to the active function. -func (c *Context) PMINSB(mx, x operand.Op) { - if inst, err := x86.PMINSB(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVSXWQ m64 ymm +// VPMOVSXWQ xmm ymm +// VPMOVSXWQ m32 xmm +// VPMOVSXWQ xmm xmm +// VPMOVSXWQ m32 k xmm +// VPMOVSXWQ m64 k ymm +// VPMOVSXWQ xmm k xmm +// VPMOVSXWQ xmm k ymm +// VPMOVSXWQ m128 k zmm +// VPMOVSXWQ m128 zmm +// VPMOVSXWQ xmm k zmm +// VPMOVSXWQ xmm zmm +// Construct and append a VPMOVSXWQ instruction to the active function. +func (c *Context) VPMOVSXWQ(ops ...operand.Op) { + c.addinstruction(x86.VPMOVSXWQ(ops...)) } -// PMINSB: Minimum of Packed Signed Byte Integers. +// VPMOVSXWQ: Move Packed Word Integers to Quadword Integers with Sign Extension. // // Forms: // -// PMINSB xmm xmm -// PMINSB m128 xmm -// Construct and append a PMINSB instruction to the active function. +// VPMOVSXWQ m64 ymm +// VPMOVSXWQ xmm ymm +// VPMOVSXWQ m32 xmm +// VPMOVSXWQ xmm xmm +// VPMOVSXWQ m32 k xmm +// VPMOVSXWQ m64 k ymm +// VPMOVSXWQ xmm k xmm +// VPMOVSXWQ xmm k ymm +// VPMOVSXWQ m128 k zmm +// VPMOVSXWQ m128 zmm +// VPMOVSXWQ xmm k zmm +// VPMOVSXWQ xmm zmm +// Construct and append a VPMOVSXWQ instruction to the active function. // Operates on the global context. -func PMINSB(mx, x operand.Op) { ctx.PMINSB(mx, x) } +func VPMOVSXWQ(ops ...operand.Op) { ctx.VPMOVSXWQ(ops...) } -// PMINSD: Minimum of Packed Signed Doubleword Integers. +// VPMOVSXWQ_Z: Move Packed Word Integers to Quadword Integers with Sign Extension (Zeroing Masking). // // Forms: // -// PMINSD xmm xmm -// PMINSD m128 xmm -// Construct and append a PMINSD instruction to the active function. -func (c *Context) PMINSD(mx, x operand.Op) { - if inst, err := x86.PMINSD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVSXWQ.Z m32 k xmm +// VPMOVSXWQ.Z m64 k ymm +// VPMOVSXWQ.Z xmm k xmm +// VPMOVSXWQ.Z xmm k ymm +// VPMOVSXWQ.Z m128 k zmm +// VPMOVSXWQ.Z xmm k zmm +// Construct and append a VPMOVSXWQ.Z instruction to the active function. +func (c *Context) VPMOVSXWQ_Z(mx, k, xyz operand.Op) { + c.addinstruction(x86.VPMOVSXWQ_Z(mx, k, xyz)) } -// PMINSD: Minimum of Packed Signed Doubleword Integers. +// VPMOVSXWQ_Z: Move Packed Word Integers to Quadword Integers with Sign Extension (Zeroing Masking). // // Forms: // -// PMINSD xmm xmm -// PMINSD m128 xmm -// Construct and append a PMINSD instruction to the active function. +// VPMOVSXWQ.Z m32 k xmm +// VPMOVSXWQ.Z m64 k ymm +// VPMOVSXWQ.Z xmm k xmm +// VPMOVSXWQ.Z xmm k ymm +// VPMOVSXWQ.Z m128 k zmm +// VPMOVSXWQ.Z xmm k zmm +// Construct and append a VPMOVSXWQ.Z instruction to the active function. // Operates on the global context. -func PMINSD(mx, x operand.Op) { ctx.PMINSD(mx, x) } +func VPMOVSXWQ_Z(mx, k, xyz operand.Op) { ctx.VPMOVSXWQ_Z(mx, k, xyz) } -// PMINSW: Minimum of Packed Signed Word Integers. +// VPMOVUSDB: Down Convert Packed Doubleword Values to Byte Values with Unsigned Saturation. // // Forms: // -// PMINSW xmm xmm -// PMINSW m128 xmm -// Construct and append a PMINSW instruction to the active function. -func (c *Context) PMINSW(mx, x operand.Op) { - if inst, err := x86.PMINSW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVUSDB xmm k m32 +// VPMOVUSDB xmm k xmm +// VPMOVUSDB xmm m32 +// VPMOVUSDB xmm xmm +// VPMOVUSDB ymm k m64 +// VPMOVUSDB ymm k xmm +// VPMOVUSDB ymm m64 +// VPMOVUSDB ymm xmm +// VPMOVUSDB zmm k m128 +// VPMOVUSDB zmm k xmm +// VPMOVUSDB zmm m128 +// VPMOVUSDB zmm xmm +// Construct and append a VPMOVUSDB instruction to the active function. +func (c *Context) VPMOVUSDB(ops ...operand.Op) { + c.addinstruction(x86.VPMOVUSDB(ops...)) } -// PMINSW: Minimum of Packed Signed Word Integers. +// VPMOVUSDB: Down Convert Packed Doubleword Values to Byte Values with Unsigned Saturation. // // Forms: // -// PMINSW xmm xmm -// PMINSW m128 xmm -// Construct and append a PMINSW instruction to the active function. +// VPMOVUSDB xmm k m32 +// VPMOVUSDB xmm k xmm +// VPMOVUSDB xmm m32 +// VPMOVUSDB xmm xmm +// VPMOVUSDB ymm k m64 +// VPMOVUSDB ymm k xmm +// VPMOVUSDB ymm m64 +// VPMOVUSDB ymm xmm +// VPMOVUSDB zmm k m128 +// VPMOVUSDB zmm k xmm +// VPMOVUSDB zmm m128 +// VPMOVUSDB zmm xmm +// Construct and append a VPMOVUSDB instruction to the active function. // Operates on the global context. -func PMINSW(mx, x operand.Op) { ctx.PMINSW(mx, x) } +func VPMOVUSDB(ops ...operand.Op) { ctx.VPMOVUSDB(ops...) } -// PMINUB: Minimum of Packed Unsigned Byte Integers. +// VPMOVUSDB_Z: Down Convert Packed Doubleword Values to Byte Values with Unsigned Saturation (Zeroing Masking). // // Forms: // -// PMINUB xmm xmm -// PMINUB m128 xmm -// Construct and append a PMINUB instruction to the active function. -func (c *Context) PMINUB(mx, x operand.Op) { - if inst, err := x86.PMINUB(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVUSDB.Z xmm k m32 +// VPMOVUSDB.Z xmm k xmm +// VPMOVUSDB.Z ymm k m64 +// VPMOVUSDB.Z ymm k xmm +// VPMOVUSDB.Z zmm k m128 +// VPMOVUSDB.Z zmm k xmm +// Construct and append a VPMOVUSDB.Z instruction to the active function. +func (c *Context) VPMOVUSDB_Z(xyz, k, mx operand.Op) { + c.addinstruction(x86.VPMOVUSDB_Z(xyz, k, mx)) } -// PMINUB: Minimum of Packed Unsigned Byte Integers. +// VPMOVUSDB_Z: Down Convert Packed Doubleword Values to Byte Values with Unsigned Saturation (Zeroing Masking). // // Forms: // -// PMINUB xmm xmm -// PMINUB m128 xmm -// Construct and append a PMINUB instruction to the active function. +// VPMOVUSDB.Z xmm k m32 +// VPMOVUSDB.Z xmm k xmm +// VPMOVUSDB.Z ymm k m64 +// VPMOVUSDB.Z ymm k xmm +// VPMOVUSDB.Z zmm k m128 +// VPMOVUSDB.Z zmm k xmm +// Construct and append a VPMOVUSDB.Z instruction to the active function. // Operates on the global context. -func PMINUB(mx, x operand.Op) { ctx.PMINUB(mx, x) } +func VPMOVUSDB_Z(xyz, k, mx operand.Op) { ctx.VPMOVUSDB_Z(xyz, k, mx) } -// PMINUD: Minimum of Packed Unsigned Doubleword Integers. +// VPMOVUSDW: Down Convert Packed Doubleword Values to Word Values with Unsigned Saturation. // // Forms: // -// PMINUD xmm xmm -// PMINUD m128 xmm -// Construct and append a PMINUD instruction to the active function. -func (c *Context) PMINUD(mx, x operand.Op) { - if inst, err := x86.PMINUD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVUSDW xmm k m64 +// VPMOVUSDW xmm k xmm +// VPMOVUSDW xmm m64 +// VPMOVUSDW xmm xmm +// VPMOVUSDW ymm k m128 +// VPMOVUSDW ymm k xmm +// VPMOVUSDW ymm m128 +// VPMOVUSDW ymm xmm +// VPMOVUSDW zmm k m256 +// VPMOVUSDW zmm k ymm +// VPMOVUSDW zmm m256 +// VPMOVUSDW zmm ymm +// Construct and append a VPMOVUSDW instruction to the active function. +func (c *Context) VPMOVUSDW(ops ...operand.Op) { + c.addinstruction(x86.VPMOVUSDW(ops...)) } -// PMINUD: Minimum of Packed Unsigned Doubleword Integers. +// VPMOVUSDW: Down Convert Packed Doubleword Values to Word Values with Unsigned Saturation. // // Forms: // -// PMINUD xmm xmm -// PMINUD m128 xmm -// Construct and append a PMINUD instruction to the active function. +// VPMOVUSDW xmm k m64 +// VPMOVUSDW xmm k xmm +// VPMOVUSDW xmm m64 +// VPMOVUSDW xmm xmm +// VPMOVUSDW ymm k m128 +// VPMOVUSDW ymm k xmm +// VPMOVUSDW ymm m128 +// VPMOVUSDW ymm xmm +// VPMOVUSDW zmm k m256 +// VPMOVUSDW zmm k ymm +// VPMOVUSDW zmm m256 +// VPMOVUSDW zmm ymm +// Construct and append a VPMOVUSDW instruction to the active function. // Operates on the global context. -func PMINUD(mx, x operand.Op) { ctx.PMINUD(mx, x) } +func VPMOVUSDW(ops ...operand.Op) { ctx.VPMOVUSDW(ops...) } -// PMINUW: Minimum of Packed Unsigned Word Integers. +// VPMOVUSDW_Z: Down Convert Packed Doubleword Values to Word Values with Unsigned Saturation (Zeroing Masking). // // Forms: // -// PMINUW xmm xmm -// PMINUW m128 xmm -// Construct and append a PMINUW instruction to the active function. -func (c *Context) PMINUW(mx, x operand.Op) { - if inst, err := x86.PMINUW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVUSDW.Z xmm k m64 +// VPMOVUSDW.Z xmm k xmm +// VPMOVUSDW.Z ymm k m128 +// VPMOVUSDW.Z ymm k xmm +// VPMOVUSDW.Z zmm k m256 +// VPMOVUSDW.Z zmm k ymm +// Construct and append a VPMOVUSDW.Z instruction to the active function. +func (c *Context) VPMOVUSDW_Z(xyz, k, mxy operand.Op) { + c.addinstruction(x86.VPMOVUSDW_Z(xyz, k, mxy)) } -// PMINUW: Minimum of Packed Unsigned Word Integers. +// VPMOVUSDW_Z: Down Convert Packed Doubleword Values to Word Values with Unsigned Saturation (Zeroing Masking). // // Forms: // -// PMINUW xmm xmm -// PMINUW m128 xmm -// Construct and append a PMINUW instruction to the active function. +// VPMOVUSDW.Z xmm k m64 +// VPMOVUSDW.Z xmm k xmm +// VPMOVUSDW.Z ymm k m128 +// VPMOVUSDW.Z ymm k xmm +// VPMOVUSDW.Z zmm k m256 +// VPMOVUSDW.Z zmm k ymm +// Construct and append a VPMOVUSDW.Z instruction to the active function. // Operates on the global context. -func PMINUW(mx, x operand.Op) { ctx.PMINUW(mx, x) } +func VPMOVUSDW_Z(xyz, k, mxy operand.Op) { ctx.VPMOVUSDW_Z(xyz, k, mxy) } -// PMOVMSKB: Move Byte Mask. +// VPMOVUSQB: Down Convert Packed Quadword Values to Byte Values with Unsigned Saturation. // // Forms: // -// PMOVMSKB xmm r32 -// Construct and append a PMOVMSKB instruction to the active function. -func (c *Context) PMOVMSKB(x, r operand.Op) { - if inst, err := x86.PMOVMSKB(x, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVUSQB xmm k m16 +// VPMOVUSQB xmm k xmm +// VPMOVUSQB xmm m16 +// VPMOVUSQB xmm xmm +// VPMOVUSQB ymm k m32 +// VPMOVUSQB ymm k xmm +// VPMOVUSQB ymm m32 +// VPMOVUSQB ymm xmm +// VPMOVUSQB zmm k m64 +// VPMOVUSQB zmm k xmm +// VPMOVUSQB zmm m64 +// VPMOVUSQB zmm xmm +// Construct and append a VPMOVUSQB instruction to the active function. +func (c *Context) VPMOVUSQB(ops ...operand.Op) { + c.addinstruction(x86.VPMOVUSQB(ops...)) } -// PMOVMSKB: Move Byte Mask. +// VPMOVUSQB: Down Convert Packed Quadword Values to Byte Values with Unsigned Saturation. // // Forms: // -// PMOVMSKB xmm r32 -// Construct and append a PMOVMSKB instruction to the active function. +// VPMOVUSQB xmm k m16 +// VPMOVUSQB xmm k xmm +// VPMOVUSQB xmm m16 +// VPMOVUSQB xmm xmm +// VPMOVUSQB ymm k m32 +// VPMOVUSQB ymm k xmm +// VPMOVUSQB ymm m32 +// VPMOVUSQB ymm xmm +// VPMOVUSQB zmm k m64 +// VPMOVUSQB zmm k xmm +// VPMOVUSQB zmm m64 +// VPMOVUSQB zmm xmm +// Construct and append a VPMOVUSQB instruction to the active function. // Operates on the global context. -func PMOVMSKB(x, r operand.Op) { ctx.PMOVMSKB(x, r) } +func VPMOVUSQB(ops ...operand.Op) { ctx.VPMOVUSQB(ops...) } -// PMOVSXBD: Move Packed Byte Integers to Doubleword Integers with Sign Extension. +// VPMOVUSQB_Z: Down Convert Packed Quadword Values to Byte Values with Unsigned Saturation (Zeroing Masking). // // Forms: // -// PMOVSXBD xmm xmm -// PMOVSXBD m32 xmm -// Construct and append a PMOVSXBD instruction to the active function. -func (c *Context) PMOVSXBD(mx, x operand.Op) { - if inst, err := x86.PMOVSXBD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVUSQB.Z xmm k m16 +// VPMOVUSQB.Z xmm k xmm +// VPMOVUSQB.Z ymm k m32 +// VPMOVUSQB.Z ymm k xmm +// VPMOVUSQB.Z zmm k m64 +// VPMOVUSQB.Z zmm k xmm +// Construct and append a VPMOVUSQB.Z instruction to the active function. +func (c *Context) VPMOVUSQB_Z(xyz, k, mx operand.Op) { + c.addinstruction(x86.VPMOVUSQB_Z(xyz, k, mx)) } -// PMOVSXBD: Move Packed Byte Integers to Doubleword Integers with Sign Extension. +// VPMOVUSQB_Z: Down Convert Packed Quadword Values to Byte Values with Unsigned Saturation (Zeroing Masking). // // Forms: // -// PMOVSXBD xmm xmm -// PMOVSXBD m32 xmm -// Construct and append a PMOVSXBD instruction to the active function. +// VPMOVUSQB.Z xmm k m16 +// VPMOVUSQB.Z xmm k xmm +// VPMOVUSQB.Z ymm k m32 +// VPMOVUSQB.Z ymm k xmm +// VPMOVUSQB.Z zmm k m64 +// VPMOVUSQB.Z zmm k xmm +// Construct and append a VPMOVUSQB.Z instruction to the active function. // Operates on the global context. -func PMOVSXBD(mx, x operand.Op) { ctx.PMOVSXBD(mx, x) } +func VPMOVUSQB_Z(xyz, k, mx operand.Op) { ctx.VPMOVUSQB_Z(xyz, k, mx) } -// PMOVSXBQ: Move Packed Byte Integers to Quadword Integers with Sign Extension. +// VPMOVUSQD: Down Convert Packed Quadword Values to Doubleword Values with Unsigned Saturation. // // Forms: // -// PMOVSXBQ xmm xmm -// PMOVSXBQ m16 xmm -// Construct and append a PMOVSXBQ instruction to the active function. -func (c *Context) PMOVSXBQ(mx, x operand.Op) { - if inst, err := x86.PMOVSXBQ(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVUSQD xmm k m64 +// VPMOVUSQD xmm k xmm +// VPMOVUSQD xmm m64 +// VPMOVUSQD xmm xmm +// VPMOVUSQD ymm k m128 +// VPMOVUSQD ymm k xmm +// VPMOVUSQD ymm m128 +// VPMOVUSQD ymm xmm +// VPMOVUSQD zmm k m256 +// VPMOVUSQD zmm k ymm +// VPMOVUSQD zmm m256 +// VPMOVUSQD zmm ymm +// Construct and append a VPMOVUSQD instruction to the active function. +func (c *Context) VPMOVUSQD(ops ...operand.Op) { + c.addinstruction(x86.VPMOVUSQD(ops...)) } -// PMOVSXBQ: Move Packed Byte Integers to Quadword Integers with Sign Extension. +// VPMOVUSQD: Down Convert Packed Quadword Values to Doubleword Values with Unsigned Saturation. // // Forms: // -// PMOVSXBQ xmm xmm -// PMOVSXBQ m16 xmm -// Construct and append a PMOVSXBQ instruction to the active function. +// VPMOVUSQD xmm k m64 +// VPMOVUSQD xmm k xmm +// VPMOVUSQD xmm m64 +// VPMOVUSQD xmm xmm +// VPMOVUSQD ymm k m128 +// VPMOVUSQD ymm k xmm +// VPMOVUSQD ymm m128 +// VPMOVUSQD ymm xmm +// VPMOVUSQD zmm k m256 +// VPMOVUSQD zmm k ymm +// VPMOVUSQD zmm m256 +// VPMOVUSQD zmm ymm +// Construct and append a VPMOVUSQD instruction to the active function. // Operates on the global context. -func PMOVSXBQ(mx, x operand.Op) { ctx.PMOVSXBQ(mx, x) } +func VPMOVUSQD(ops ...operand.Op) { ctx.VPMOVUSQD(ops...) } -// PMOVSXBW: Move Packed Byte Integers to Word Integers with Sign Extension. +// VPMOVUSQD_Z: Down Convert Packed Quadword Values to Doubleword Values with Unsigned Saturation (Zeroing Masking). // // Forms: // -// PMOVSXBW xmm xmm -// PMOVSXBW m64 xmm -// Construct and append a PMOVSXBW instruction to the active function. -func (c *Context) PMOVSXBW(mx, x operand.Op) { - if inst, err := x86.PMOVSXBW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVUSQD.Z xmm k m64 +// VPMOVUSQD.Z xmm k xmm +// VPMOVUSQD.Z ymm k m128 +// VPMOVUSQD.Z ymm k xmm +// VPMOVUSQD.Z zmm k m256 +// VPMOVUSQD.Z zmm k ymm +// Construct and append a VPMOVUSQD.Z instruction to the active function. +func (c *Context) VPMOVUSQD_Z(xyz, k, mxy operand.Op) { + c.addinstruction(x86.VPMOVUSQD_Z(xyz, k, mxy)) } -// PMOVSXBW: Move Packed Byte Integers to Word Integers with Sign Extension. +// VPMOVUSQD_Z: Down Convert Packed Quadword Values to Doubleword Values with Unsigned Saturation (Zeroing Masking). // // Forms: // -// PMOVSXBW xmm xmm -// PMOVSXBW m64 xmm -// Construct and append a PMOVSXBW instruction to the active function. +// VPMOVUSQD.Z xmm k m64 +// VPMOVUSQD.Z xmm k xmm +// VPMOVUSQD.Z ymm k m128 +// VPMOVUSQD.Z ymm k xmm +// VPMOVUSQD.Z zmm k m256 +// VPMOVUSQD.Z zmm k ymm +// Construct and append a VPMOVUSQD.Z instruction to the active function. // Operates on the global context. -func PMOVSXBW(mx, x operand.Op) { ctx.PMOVSXBW(mx, x) } +func VPMOVUSQD_Z(xyz, k, mxy operand.Op) { ctx.VPMOVUSQD_Z(xyz, k, mxy) } -// PMOVSXDQ: Move Packed Doubleword Integers to Quadword Integers with Sign Extension. +// VPMOVUSQW: Down Convert Packed Quadword Values to Word Values with Unsigned Saturation. // // Forms: // -// PMOVSXDQ xmm xmm -// PMOVSXDQ m64 xmm -// Construct and append a PMOVSXDQ instruction to the active function. -func (c *Context) PMOVSXDQ(mx, x operand.Op) { - if inst, err := x86.PMOVSXDQ(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVUSQW xmm k m32 +// VPMOVUSQW xmm k xmm +// VPMOVUSQW xmm m32 +// VPMOVUSQW xmm xmm +// VPMOVUSQW ymm k m64 +// VPMOVUSQW ymm k xmm +// VPMOVUSQW ymm m64 +// VPMOVUSQW ymm xmm +// VPMOVUSQW zmm k m128 +// VPMOVUSQW zmm k xmm +// VPMOVUSQW zmm m128 +// VPMOVUSQW zmm xmm +// Construct and append a VPMOVUSQW instruction to the active function. +func (c *Context) VPMOVUSQW(ops ...operand.Op) { + c.addinstruction(x86.VPMOVUSQW(ops...)) } -// PMOVSXDQ: Move Packed Doubleword Integers to Quadword Integers with Sign Extension. +// VPMOVUSQW: Down Convert Packed Quadword Values to Word Values with Unsigned Saturation. // // Forms: // -// PMOVSXDQ xmm xmm -// PMOVSXDQ m64 xmm -// Construct and append a PMOVSXDQ instruction to the active function. +// VPMOVUSQW xmm k m32 +// VPMOVUSQW xmm k xmm +// VPMOVUSQW xmm m32 +// VPMOVUSQW xmm xmm +// VPMOVUSQW ymm k m64 +// VPMOVUSQW ymm k xmm +// VPMOVUSQW ymm m64 +// VPMOVUSQW ymm xmm +// VPMOVUSQW zmm k m128 +// VPMOVUSQW zmm k xmm +// VPMOVUSQW zmm m128 +// VPMOVUSQW zmm xmm +// Construct and append a VPMOVUSQW instruction to the active function. // Operates on the global context. -func PMOVSXDQ(mx, x operand.Op) { ctx.PMOVSXDQ(mx, x) } +func VPMOVUSQW(ops ...operand.Op) { ctx.VPMOVUSQW(ops...) } -// PMOVSXWD: Move Packed Word Integers to Doubleword Integers with Sign Extension. +// VPMOVUSQW_Z: Down Convert Packed Quadword Values to Word Values with Unsigned Saturation (Zeroing Masking). // // Forms: // -// PMOVSXWD xmm xmm -// PMOVSXWD m64 xmm -// Construct and append a PMOVSXWD instruction to the active function. -func (c *Context) PMOVSXWD(mx, x operand.Op) { - if inst, err := x86.PMOVSXWD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVUSQW.Z xmm k m32 +// VPMOVUSQW.Z xmm k xmm +// VPMOVUSQW.Z ymm k m64 +// VPMOVUSQW.Z ymm k xmm +// VPMOVUSQW.Z zmm k m128 +// VPMOVUSQW.Z zmm k xmm +// Construct and append a VPMOVUSQW.Z instruction to the active function. +func (c *Context) VPMOVUSQW_Z(xyz, k, mx operand.Op) { + c.addinstruction(x86.VPMOVUSQW_Z(xyz, k, mx)) } -// PMOVSXWD: Move Packed Word Integers to Doubleword Integers with Sign Extension. +// VPMOVUSQW_Z: Down Convert Packed Quadword Values to Word Values with Unsigned Saturation (Zeroing Masking). // // Forms: // -// PMOVSXWD xmm xmm -// PMOVSXWD m64 xmm -// Construct and append a PMOVSXWD instruction to the active function. +// VPMOVUSQW.Z xmm k m32 +// VPMOVUSQW.Z xmm k xmm +// VPMOVUSQW.Z ymm k m64 +// VPMOVUSQW.Z ymm k xmm +// VPMOVUSQW.Z zmm k m128 +// VPMOVUSQW.Z zmm k xmm +// Construct and append a VPMOVUSQW.Z instruction to the active function. // Operates on the global context. -func PMOVSXWD(mx, x operand.Op) { ctx.PMOVSXWD(mx, x) } +func VPMOVUSQW_Z(xyz, k, mx operand.Op) { ctx.VPMOVUSQW_Z(xyz, k, mx) } -// PMOVSXWQ: Move Packed Word Integers to Quadword Integers with Sign Extension. +// VPMOVUSWB: Down Convert Packed Word Values to Byte Values with Unsigned Saturation. // // Forms: // -// PMOVSXWQ xmm xmm -// PMOVSXWQ m32 xmm -// Construct and append a PMOVSXWQ instruction to the active function. -func (c *Context) PMOVSXWQ(mx, x operand.Op) { - if inst, err := x86.PMOVSXWQ(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVUSWB xmm k m64 +// VPMOVUSWB xmm k xmm +// VPMOVUSWB xmm m64 +// VPMOVUSWB xmm xmm +// VPMOVUSWB ymm k m128 +// VPMOVUSWB ymm k xmm +// VPMOVUSWB ymm m128 +// VPMOVUSWB ymm xmm +// VPMOVUSWB zmm k m256 +// VPMOVUSWB zmm k ymm +// VPMOVUSWB zmm m256 +// VPMOVUSWB zmm ymm +// Construct and append a VPMOVUSWB instruction to the active function. +func (c *Context) VPMOVUSWB(ops ...operand.Op) { + c.addinstruction(x86.VPMOVUSWB(ops...)) } -// PMOVSXWQ: Move Packed Word Integers to Quadword Integers with Sign Extension. +// VPMOVUSWB: Down Convert Packed Word Values to Byte Values with Unsigned Saturation. // // Forms: // -// PMOVSXWQ xmm xmm -// PMOVSXWQ m32 xmm -// Construct and append a PMOVSXWQ instruction to the active function. +// VPMOVUSWB xmm k m64 +// VPMOVUSWB xmm k xmm +// VPMOVUSWB xmm m64 +// VPMOVUSWB xmm xmm +// VPMOVUSWB ymm k m128 +// VPMOVUSWB ymm k xmm +// VPMOVUSWB ymm m128 +// VPMOVUSWB ymm xmm +// VPMOVUSWB zmm k m256 +// VPMOVUSWB zmm k ymm +// VPMOVUSWB zmm m256 +// VPMOVUSWB zmm ymm +// Construct and append a VPMOVUSWB instruction to the active function. // Operates on the global context. -func PMOVSXWQ(mx, x operand.Op) { ctx.PMOVSXWQ(mx, x) } +func VPMOVUSWB(ops ...operand.Op) { ctx.VPMOVUSWB(ops...) } -// PMOVZXBD: Move Packed Byte Integers to Doubleword Integers with Zero Extension. +// VPMOVUSWB_Z: Down Convert Packed Word Values to Byte Values with Unsigned Saturation (Zeroing Masking). // // Forms: // -// PMOVZXBD xmm xmm -// PMOVZXBD m32 xmm -// Construct and append a PMOVZXBD instruction to the active function. -func (c *Context) PMOVZXBD(mx, x operand.Op) { - if inst, err := x86.PMOVZXBD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVUSWB.Z xmm k m64 +// VPMOVUSWB.Z xmm k xmm +// VPMOVUSWB.Z ymm k m128 +// VPMOVUSWB.Z ymm k xmm +// VPMOVUSWB.Z zmm k m256 +// VPMOVUSWB.Z zmm k ymm +// Construct and append a VPMOVUSWB.Z instruction to the active function. +func (c *Context) VPMOVUSWB_Z(xyz, k, mxy operand.Op) { + c.addinstruction(x86.VPMOVUSWB_Z(xyz, k, mxy)) } -// PMOVZXBD: Move Packed Byte Integers to Doubleword Integers with Zero Extension. +// VPMOVUSWB_Z: Down Convert Packed Word Values to Byte Values with Unsigned Saturation (Zeroing Masking). // // Forms: // -// PMOVZXBD xmm xmm -// PMOVZXBD m32 xmm -// Construct and append a PMOVZXBD instruction to the active function. +// VPMOVUSWB.Z xmm k m64 +// VPMOVUSWB.Z xmm k xmm +// VPMOVUSWB.Z ymm k m128 +// VPMOVUSWB.Z ymm k xmm +// VPMOVUSWB.Z zmm k m256 +// VPMOVUSWB.Z zmm k ymm +// Construct and append a VPMOVUSWB.Z instruction to the active function. // Operates on the global context. -func PMOVZXBD(mx, x operand.Op) { ctx.PMOVZXBD(mx, x) } +func VPMOVUSWB_Z(xyz, k, mxy operand.Op) { ctx.VPMOVUSWB_Z(xyz, k, mxy) } -// PMOVZXBQ: Move Packed Byte Integers to Quadword Integers with Zero Extension. +// VPMOVW2M: Move Signs of Packed Word Integers to Mask Register. // // Forms: // -// PMOVZXBQ xmm xmm -// PMOVZXBQ m16 xmm -// Construct and append a PMOVZXBQ instruction to the active function. -func (c *Context) PMOVZXBQ(mx, x operand.Op) { - if inst, err := x86.PMOVZXBQ(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVW2M xmm k +// VPMOVW2M ymm k +// VPMOVW2M zmm k +// Construct and append a VPMOVW2M instruction to the active function. +func (c *Context) VPMOVW2M(xyz, k operand.Op) { + c.addinstruction(x86.VPMOVW2M(xyz, k)) } -// PMOVZXBQ: Move Packed Byte Integers to Quadword Integers with Zero Extension. +// VPMOVW2M: Move Signs of Packed Word Integers to Mask Register. // // Forms: // -// PMOVZXBQ xmm xmm -// PMOVZXBQ m16 xmm -// Construct and append a PMOVZXBQ instruction to the active function. +// VPMOVW2M xmm k +// VPMOVW2M ymm k +// VPMOVW2M zmm k +// Construct and append a VPMOVW2M instruction to the active function. // Operates on the global context. -func PMOVZXBQ(mx, x operand.Op) { ctx.PMOVZXBQ(mx, x) } +func VPMOVW2M(xyz, k operand.Op) { ctx.VPMOVW2M(xyz, k) } -// PMOVZXBW: Move Packed Byte Integers to Word Integers with Zero Extension. +// VPMOVWB: Down Convert Packed Word Values to Byte Values with Truncation. // // Forms: // -// PMOVZXBW xmm xmm -// PMOVZXBW m64 xmm -// Construct and append a PMOVZXBW instruction to the active function. -func (c *Context) PMOVZXBW(mx, x operand.Op) { - if inst, err := x86.PMOVZXBW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVWB xmm k m64 +// VPMOVWB xmm k xmm +// VPMOVWB xmm m64 +// VPMOVWB xmm xmm +// VPMOVWB ymm k m128 +// VPMOVWB ymm k xmm +// VPMOVWB ymm m128 +// VPMOVWB ymm xmm +// VPMOVWB zmm k m256 +// VPMOVWB zmm k ymm +// VPMOVWB zmm m256 +// VPMOVWB zmm ymm +// Construct and append a VPMOVWB instruction to the active function. +func (c *Context) VPMOVWB(ops ...operand.Op) { + c.addinstruction(x86.VPMOVWB(ops...)) } -// PMOVZXBW: Move Packed Byte Integers to Word Integers with Zero Extension. +// VPMOVWB: Down Convert Packed Word Values to Byte Values with Truncation. // // Forms: // -// PMOVZXBW xmm xmm -// PMOVZXBW m64 xmm -// Construct and append a PMOVZXBW instruction to the active function. +// VPMOVWB xmm k m64 +// VPMOVWB xmm k xmm +// VPMOVWB xmm m64 +// VPMOVWB xmm xmm +// VPMOVWB ymm k m128 +// VPMOVWB ymm k xmm +// VPMOVWB ymm m128 +// VPMOVWB ymm xmm +// VPMOVWB zmm k m256 +// VPMOVWB zmm k ymm +// VPMOVWB zmm m256 +// VPMOVWB zmm ymm +// Construct and append a VPMOVWB instruction to the active function. // Operates on the global context. -func PMOVZXBW(mx, x operand.Op) { ctx.PMOVZXBW(mx, x) } +func VPMOVWB(ops ...operand.Op) { ctx.VPMOVWB(ops...) } -// PMOVZXDQ: Move Packed Doubleword Integers to Quadword Integers with Zero Extension. +// VPMOVWB_Z: Down Convert Packed Word Values to Byte Values with Truncation (Zeroing Masking). // // Forms: // -// PMOVZXDQ xmm xmm -// PMOVZXDQ m64 xmm -// Construct and append a PMOVZXDQ instruction to the active function. -func (c *Context) PMOVZXDQ(mx, x operand.Op) { - if inst, err := x86.PMOVZXDQ(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVWB.Z xmm k m64 +// VPMOVWB.Z xmm k xmm +// VPMOVWB.Z ymm k m128 +// VPMOVWB.Z ymm k xmm +// VPMOVWB.Z zmm k m256 +// VPMOVWB.Z zmm k ymm +// Construct and append a VPMOVWB.Z instruction to the active function. +func (c *Context) VPMOVWB_Z(xyz, k, mxy operand.Op) { + c.addinstruction(x86.VPMOVWB_Z(xyz, k, mxy)) } -// PMOVZXDQ: Move Packed Doubleword Integers to Quadword Integers with Zero Extension. +// VPMOVWB_Z: Down Convert Packed Word Values to Byte Values with Truncation (Zeroing Masking). // // Forms: // -// PMOVZXDQ xmm xmm -// PMOVZXDQ m64 xmm -// Construct and append a PMOVZXDQ instruction to the active function. +// VPMOVWB.Z xmm k m64 +// VPMOVWB.Z xmm k xmm +// VPMOVWB.Z ymm k m128 +// VPMOVWB.Z ymm k xmm +// VPMOVWB.Z zmm k m256 +// VPMOVWB.Z zmm k ymm +// Construct and append a VPMOVWB.Z instruction to the active function. // Operates on the global context. -func PMOVZXDQ(mx, x operand.Op) { ctx.PMOVZXDQ(mx, x) } +func VPMOVWB_Z(xyz, k, mxy operand.Op) { ctx.VPMOVWB_Z(xyz, k, mxy) } -// PMOVZXWD: Move Packed Word Integers to Doubleword Integers with Zero Extension. +// VPMOVZXBD: Move Packed Byte Integers to Doubleword Integers with Zero Extension. // // Forms: // -// PMOVZXWD xmm xmm -// PMOVZXWD m64 xmm -// Construct and append a PMOVZXWD instruction to the active function. -func (c *Context) PMOVZXWD(mx, x operand.Op) { - if inst, err := x86.PMOVZXWD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVZXBD m64 ymm +// VPMOVZXBD xmm ymm +// VPMOVZXBD m32 xmm +// VPMOVZXBD xmm xmm +// VPMOVZXBD m32 k xmm +// VPMOVZXBD m64 k ymm +// VPMOVZXBD xmm k xmm +// VPMOVZXBD xmm k ymm +// VPMOVZXBD m128 k zmm +// VPMOVZXBD m128 zmm +// VPMOVZXBD xmm k zmm +// VPMOVZXBD xmm zmm +// Construct and append a VPMOVZXBD instruction to the active function. +func (c *Context) VPMOVZXBD(ops ...operand.Op) { + c.addinstruction(x86.VPMOVZXBD(ops...)) } -// PMOVZXWD: Move Packed Word Integers to Doubleword Integers with Zero Extension. +// VPMOVZXBD: Move Packed Byte Integers to Doubleword Integers with Zero Extension. // // Forms: // -// PMOVZXWD xmm xmm -// PMOVZXWD m64 xmm -// Construct and append a PMOVZXWD instruction to the active function. +// VPMOVZXBD m64 ymm +// VPMOVZXBD xmm ymm +// VPMOVZXBD m32 xmm +// VPMOVZXBD xmm xmm +// VPMOVZXBD m32 k xmm +// VPMOVZXBD m64 k ymm +// VPMOVZXBD xmm k xmm +// VPMOVZXBD xmm k ymm +// VPMOVZXBD m128 k zmm +// VPMOVZXBD m128 zmm +// VPMOVZXBD xmm k zmm +// VPMOVZXBD xmm zmm +// Construct and append a VPMOVZXBD instruction to the active function. // Operates on the global context. -func PMOVZXWD(mx, x operand.Op) { ctx.PMOVZXWD(mx, x) } +func VPMOVZXBD(ops ...operand.Op) { ctx.VPMOVZXBD(ops...) } -// PMOVZXWQ: Move Packed Word Integers to Quadword Integers with Zero Extension. +// VPMOVZXBD_Z: Move Packed Byte Integers to Doubleword Integers with Zero Extension (Zeroing Masking). // // Forms: // -// PMOVZXWQ xmm xmm -// PMOVZXWQ m32 xmm -// Construct and append a PMOVZXWQ instruction to the active function. -func (c *Context) PMOVZXWQ(mx, x operand.Op) { - if inst, err := x86.PMOVZXWQ(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVZXBD.Z m32 k xmm +// VPMOVZXBD.Z m64 k ymm +// VPMOVZXBD.Z xmm k xmm +// VPMOVZXBD.Z xmm k ymm +// VPMOVZXBD.Z m128 k zmm +// VPMOVZXBD.Z xmm k zmm +// Construct and append a VPMOVZXBD.Z instruction to the active function. +func (c *Context) VPMOVZXBD_Z(mx, k, xyz operand.Op) { + c.addinstruction(x86.VPMOVZXBD_Z(mx, k, xyz)) } -// PMOVZXWQ: Move Packed Word Integers to Quadword Integers with Zero Extension. +// VPMOVZXBD_Z: Move Packed Byte Integers to Doubleword Integers with Zero Extension (Zeroing Masking). // // Forms: // -// PMOVZXWQ xmm xmm -// PMOVZXWQ m32 xmm -// Construct and append a PMOVZXWQ instruction to the active function. +// VPMOVZXBD.Z m32 k xmm +// VPMOVZXBD.Z m64 k ymm +// VPMOVZXBD.Z xmm k xmm +// VPMOVZXBD.Z xmm k ymm +// VPMOVZXBD.Z m128 k zmm +// VPMOVZXBD.Z xmm k zmm +// Construct and append a VPMOVZXBD.Z instruction to the active function. // Operates on the global context. -func PMOVZXWQ(mx, x operand.Op) { ctx.PMOVZXWQ(mx, x) } +func VPMOVZXBD_Z(mx, k, xyz operand.Op) { ctx.VPMOVZXBD_Z(mx, k, xyz) } -// PMULDQ: Multiply Packed Signed Doubleword Integers and Store Quadword Result. +// VPMOVZXBQ: Move Packed Byte Integers to Quadword Integers with Zero Extension. // // Forms: // -// PMULDQ xmm xmm -// PMULDQ m128 xmm -// Construct and append a PMULDQ instruction to the active function. -func (c *Context) PMULDQ(mx, x operand.Op) { - if inst, err := x86.PMULDQ(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVZXBQ m32 ymm +// VPMOVZXBQ xmm ymm +// VPMOVZXBQ m16 xmm +// VPMOVZXBQ xmm xmm +// VPMOVZXBQ m16 k xmm +// VPMOVZXBQ m32 k ymm +// VPMOVZXBQ xmm k xmm +// VPMOVZXBQ xmm k ymm +// VPMOVZXBQ m64 k zmm +// VPMOVZXBQ m64 zmm +// VPMOVZXBQ xmm k zmm +// VPMOVZXBQ xmm zmm +// Construct and append a VPMOVZXBQ instruction to the active function. +func (c *Context) VPMOVZXBQ(ops ...operand.Op) { + c.addinstruction(x86.VPMOVZXBQ(ops...)) } -// PMULDQ: Multiply Packed Signed Doubleword Integers and Store Quadword Result. +// VPMOVZXBQ: Move Packed Byte Integers to Quadword Integers with Zero Extension. // // Forms: // -// PMULDQ xmm xmm -// PMULDQ m128 xmm -// Construct and append a PMULDQ instruction to the active function. +// VPMOVZXBQ m32 ymm +// VPMOVZXBQ xmm ymm +// VPMOVZXBQ m16 xmm +// VPMOVZXBQ xmm xmm +// VPMOVZXBQ m16 k xmm +// VPMOVZXBQ m32 k ymm +// VPMOVZXBQ xmm k xmm +// VPMOVZXBQ xmm k ymm +// VPMOVZXBQ m64 k zmm +// VPMOVZXBQ m64 zmm +// VPMOVZXBQ xmm k zmm +// VPMOVZXBQ xmm zmm +// Construct and append a VPMOVZXBQ instruction to the active function. // Operates on the global context. -func PMULDQ(mx, x operand.Op) { ctx.PMULDQ(mx, x) } +func VPMOVZXBQ(ops ...operand.Op) { ctx.VPMOVZXBQ(ops...) } -// PMULHRSW: Packed Multiply Signed Word Integers and Store High Result with Round and Scale. +// VPMOVZXBQ_Z: Move Packed Byte Integers to Quadword Integers with Zero Extension (Zeroing Masking). // // Forms: // -// PMULHRSW xmm xmm -// PMULHRSW m128 xmm -// Construct and append a PMULHRSW instruction to the active function. -func (c *Context) PMULHRSW(mx, x operand.Op) { - if inst, err := x86.PMULHRSW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVZXBQ.Z m16 k xmm +// VPMOVZXBQ.Z m32 k ymm +// VPMOVZXBQ.Z xmm k xmm +// VPMOVZXBQ.Z xmm k ymm +// VPMOVZXBQ.Z m64 k zmm +// VPMOVZXBQ.Z xmm k zmm +// Construct and append a VPMOVZXBQ.Z instruction to the active function. +func (c *Context) VPMOVZXBQ_Z(mx, k, xyz operand.Op) { + c.addinstruction(x86.VPMOVZXBQ_Z(mx, k, xyz)) } -// PMULHRSW: Packed Multiply Signed Word Integers and Store High Result with Round and Scale. +// VPMOVZXBQ_Z: Move Packed Byte Integers to Quadword Integers with Zero Extension (Zeroing Masking). // // Forms: // -// PMULHRSW xmm xmm -// PMULHRSW m128 xmm -// Construct and append a PMULHRSW instruction to the active function. +// VPMOVZXBQ.Z m16 k xmm +// VPMOVZXBQ.Z m32 k ymm +// VPMOVZXBQ.Z xmm k xmm +// VPMOVZXBQ.Z xmm k ymm +// VPMOVZXBQ.Z m64 k zmm +// VPMOVZXBQ.Z xmm k zmm +// Construct and append a VPMOVZXBQ.Z instruction to the active function. // Operates on the global context. -func PMULHRSW(mx, x operand.Op) { ctx.PMULHRSW(mx, x) } +func VPMOVZXBQ_Z(mx, k, xyz operand.Op) { ctx.VPMOVZXBQ_Z(mx, k, xyz) } -// PMULHUW: Multiply Packed Unsigned Word Integers and Store High Result. +// VPMOVZXBW: Move Packed Byte Integers to Word Integers with Zero Extension. // // Forms: // -// PMULHUW xmm xmm -// PMULHUW m128 xmm -// Construct and append a PMULHUW instruction to the active function. -func (c *Context) PMULHUW(mx, x operand.Op) { - if inst, err := x86.PMULHUW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVZXBW m128 ymm +// VPMOVZXBW xmm ymm +// VPMOVZXBW m64 xmm +// VPMOVZXBW xmm xmm +// VPMOVZXBW m128 k ymm +// VPMOVZXBW m64 k xmm +// VPMOVZXBW xmm k xmm +// VPMOVZXBW xmm k ymm +// VPMOVZXBW m256 k zmm +// VPMOVZXBW m256 zmm +// VPMOVZXBW ymm k zmm +// VPMOVZXBW ymm zmm +// Construct and append a VPMOVZXBW instruction to the active function. +func (c *Context) VPMOVZXBW(ops ...operand.Op) { + c.addinstruction(x86.VPMOVZXBW(ops...)) } -// PMULHUW: Multiply Packed Unsigned Word Integers and Store High Result. +// VPMOVZXBW: Move Packed Byte Integers to Word Integers with Zero Extension. // // Forms: // -// PMULHUW xmm xmm -// PMULHUW m128 xmm -// Construct and append a PMULHUW instruction to the active function. +// VPMOVZXBW m128 ymm +// VPMOVZXBW xmm ymm +// VPMOVZXBW m64 xmm +// VPMOVZXBW xmm xmm +// VPMOVZXBW m128 k ymm +// VPMOVZXBW m64 k xmm +// VPMOVZXBW xmm k xmm +// VPMOVZXBW xmm k ymm +// VPMOVZXBW m256 k zmm +// VPMOVZXBW m256 zmm +// VPMOVZXBW ymm k zmm +// VPMOVZXBW ymm zmm +// Construct and append a VPMOVZXBW instruction to the active function. // Operates on the global context. -func PMULHUW(mx, x operand.Op) { ctx.PMULHUW(mx, x) } +func VPMOVZXBW(ops ...operand.Op) { ctx.VPMOVZXBW(ops...) } -// PMULHW: Multiply Packed Signed Word Integers and Store High Result. +// VPMOVZXBW_Z: Move Packed Byte Integers to Word Integers with Zero Extension (Zeroing Masking). // // Forms: // -// PMULHW xmm xmm -// PMULHW m128 xmm -// Construct and append a PMULHW instruction to the active function. -func (c *Context) PMULHW(mx, x operand.Op) { - if inst, err := x86.PMULHW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVZXBW.Z m128 k ymm +// VPMOVZXBW.Z m64 k xmm +// VPMOVZXBW.Z xmm k xmm +// VPMOVZXBW.Z xmm k ymm +// VPMOVZXBW.Z m256 k zmm +// VPMOVZXBW.Z ymm k zmm +// Construct and append a VPMOVZXBW.Z instruction to the active function. +func (c *Context) VPMOVZXBW_Z(mxy, k, xyz operand.Op) { + c.addinstruction(x86.VPMOVZXBW_Z(mxy, k, xyz)) } -// PMULHW: Multiply Packed Signed Word Integers and Store High Result. +// VPMOVZXBW_Z: Move Packed Byte Integers to Word Integers with Zero Extension (Zeroing Masking). // // Forms: // -// PMULHW xmm xmm -// PMULHW m128 xmm -// Construct and append a PMULHW instruction to the active function. +// VPMOVZXBW.Z m128 k ymm +// VPMOVZXBW.Z m64 k xmm +// VPMOVZXBW.Z xmm k xmm +// VPMOVZXBW.Z xmm k ymm +// VPMOVZXBW.Z m256 k zmm +// VPMOVZXBW.Z ymm k zmm +// Construct and append a VPMOVZXBW.Z instruction to the active function. // Operates on the global context. -func PMULHW(mx, x operand.Op) { ctx.PMULHW(mx, x) } +func VPMOVZXBW_Z(mxy, k, xyz operand.Op) { ctx.VPMOVZXBW_Z(mxy, k, xyz) } -// PMULLD: Multiply Packed Signed Doubleword Integers and Store Low Result. +// VPMOVZXDQ: Move Packed Doubleword Integers to Quadword Integers with Zero Extension. // // Forms: // -// PMULLD xmm xmm -// PMULLD m128 xmm -// Construct and append a PMULLD instruction to the active function. -func (c *Context) PMULLD(mx, x operand.Op) { - if inst, err := x86.PMULLD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVZXDQ m128 ymm +// VPMOVZXDQ xmm ymm +// VPMOVZXDQ m64 xmm +// VPMOVZXDQ xmm xmm +// VPMOVZXDQ m128 k ymm +// VPMOVZXDQ m64 k xmm +// VPMOVZXDQ xmm k xmm +// VPMOVZXDQ xmm k ymm +// VPMOVZXDQ m256 k zmm +// VPMOVZXDQ m256 zmm +// VPMOVZXDQ ymm k zmm +// VPMOVZXDQ ymm zmm +// Construct and append a VPMOVZXDQ instruction to the active function. +func (c *Context) VPMOVZXDQ(ops ...operand.Op) { + c.addinstruction(x86.VPMOVZXDQ(ops...)) } -// PMULLD: Multiply Packed Signed Doubleword Integers and Store Low Result. +// VPMOVZXDQ: Move Packed Doubleword Integers to Quadword Integers with Zero Extension. // // Forms: // -// PMULLD xmm xmm -// PMULLD m128 xmm -// Construct and append a PMULLD instruction to the active function. +// VPMOVZXDQ m128 ymm +// VPMOVZXDQ xmm ymm +// VPMOVZXDQ m64 xmm +// VPMOVZXDQ xmm xmm +// VPMOVZXDQ m128 k ymm +// VPMOVZXDQ m64 k xmm +// VPMOVZXDQ xmm k xmm +// VPMOVZXDQ xmm k ymm +// VPMOVZXDQ m256 k zmm +// VPMOVZXDQ m256 zmm +// VPMOVZXDQ ymm k zmm +// VPMOVZXDQ ymm zmm +// Construct and append a VPMOVZXDQ instruction to the active function. // Operates on the global context. -func PMULLD(mx, x operand.Op) { ctx.PMULLD(mx, x) } +func VPMOVZXDQ(ops ...operand.Op) { ctx.VPMOVZXDQ(ops...) } -// PMULLW: Multiply Packed Signed Word Integers and Store Low Result. +// VPMOVZXDQ_Z: Move Packed Doubleword Integers to Quadword Integers with Zero Extension (Zeroing Masking). // // Forms: // -// PMULLW xmm xmm -// PMULLW m128 xmm -// Construct and append a PMULLW instruction to the active function. -func (c *Context) PMULLW(mx, x operand.Op) { - if inst, err := x86.PMULLW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVZXDQ.Z m128 k ymm +// VPMOVZXDQ.Z m64 k xmm +// VPMOVZXDQ.Z xmm k xmm +// VPMOVZXDQ.Z xmm k ymm +// VPMOVZXDQ.Z m256 k zmm +// VPMOVZXDQ.Z ymm k zmm +// Construct and append a VPMOVZXDQ.Z instruction to the active function. +func (c *Context) VPMOVZXDQ_Z(mxy, k, xyz operand.Op) { + c.addinstruction(x86.VPMOVZXDQ_Z(mxy, k, xyz)) } -// PMULLW: Multiply Packed Signed Word Integers and Store Low Result. +// VPMOVZXDQ_Z: Move Packed Doubleword Integers to Quadword Integers with Zero Extension (Zeroing Masking). // // Forms: // -// PMULLW xmm xmm -// PMULLW m128 xmm -// Construct and append a PMULLW instruction to the active function. +// VPMOVZXDQ.Z m128 k ymm +// VPMOVZXDQ.Z m64 k xmm +// VPMOVZXDQ.Z xmm k xmm +// VPMOVZXDQ.Z xmm k ymm +// VPMOVZXDQ.Z m256 k zmm +// VPMOVZXDQ.Z ymm k zmm +// Construct and append a VPMOVZXDQ.Z instruction to the active function. // Operates on the global context. -func PMULLW(mx, x operand.Op) { ctx.PMULLW(mx, x) } +func VPMOVZXDQ_Z(mxy, k, xyz operand.Op) { ctx.VPMOVZXDQ_Z(mxy, k, xyz) } -// PMULULQ: Multiply Packed Unsigned Doubleword Integers. +// VPMOVZXWD: Move Packed Word Integers to Doubleword Integers with Zero Extension. // // Forms: // -// PMULULQ xmm xmm -// PMULULQ m128 xmm -// Construct and append a PMULULQ instruction to the active function. -func (c *Context) PMULULQ(mx, x operand.Op) { - if inst, err := x86.PMULULQ(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVZXWD m128 ymm +// VPMOVZXWD xmm ymm +// VPMOVZXWD m64 xmm +// VPMOVZXWD xmm xmm +// VPMOVZXWD m128 k ymm +// VPMOVZXWD m64 k xmm +// VPMOVZXWD xmm k xmm +// VPMOVZXWD xmm k ymm +// VPMOVZXWD m256 k zmm +// VPMOVZXWD m256 zmm +// VPMOVZXWD ymm k zmm +// VPMOVZXWD ymm zmm +// Construct and append a VPMOVZXWD instruction to the active function. +func (c *Context) VPMOVZXWD(ops ...operand.Op) { + c.addinstruction(x86.VPMOVZXWD(ops...)) } -// PMULULQ: Multiply Packed Unsigned Doubleword Integers. +// VPMOVZXWD: Move Packed Word Integers to Doubleword Integers with Zero Extension. // // Forms: // -// PMULULQ xmm xmm -// PMULULQ m128 xmm -// Construct and append a PMULULQ instruction to the active function. +// VPMOVZXWD m128 ymm +// VPMOVZXWD xmm ymm +// VPMOVZXWD m64 xmm +// VPMOVZXWD xmm xmm +// VPMOVZXWD m128 k ymm +// VPMOVZXWD m64 k xmm +// VPMOVZXWD xmm k xmm +// VPMOVZXWD xmm k ymm +// VPMOVZXWD m256 k zmm +// VPMOVZXWD m256 zmm +// VPMOVZXWD ymm k zmm +// VPMOVZXWD ymm zmm +// Construct and append a VPMOVZXWD instruction to the active function. // Operates on the global context. -func PMULULQ(mx, x operand.Op) { ctx.PMULULQ(mx, x) } +func VPMOVZXWD(ops ...operand.Op) { ctx.VPMOVZXWD(ops...) } -// POPCNTL: Count of Number of Bits Set to 1. +// VPMOVZXWD_Z: Move Packed Word Integers to Doubleword Integers with Zero Extension (Zeroing Masking). // // Forms: // -// POPCNTL r32 r32 -// POPCNTL m32 r32 -// Construct and append a POPCNTL instruction to the active function. -func (c *Context) POPCNTL(mr, r operand.Op) { - if inst, err := x86.POPCNTL(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVZXWD.Z m128 k ymm +// VPMOVZXWD.Z m64 k xmm +// VPMOVZXWD.Z xmm k xmm +// VPMOVZXWD.Z xmm k ymm +// VPMOVZXWD.Z m256 k zmm +// VPMOVZXWD.Z ymm k zmm +// Construct and append a VPMOVZXWD.Z instruction to the active function. +func (c *Context) VPMOVZXWD_Z(mxy, k, xyz operand.Op) { + c.addinstruction(x86.VPMOVZXWD_Z(mxy, k, xyz)) } -// POPCNTL: Count of Number of Bits Set to 1. +// VPMOVZXWD_Z: Move Packed Word Integers to Doubleword Integers with Zero Extension (Zeroing Masking). // // Forms: // -// POPCNTL r32 r32 -// POPCNTL m32 r32 -// Construct and append a POPCNTL instruction to the active function. +// VPMOVZXWD.Z m128 k ymm +// VPMOVZXWD.Z m64 k xmm +// VPMOVZXWD.Z xmm k xmm +// VPMOVZXWD.Z xmm k ymm +// VPMOVZXWD.Z m256 k zmm +// VPMOVZXWD.Z ymm k zmm +// Construct and append a VPMOVZXWD.Z instruction to the active function. // Operates on the global context. -func POPCNTL(mr, r operand.Op) { ctx.POPCNTL(mr, r) } +func VPMOVZXWD_Z(mxy, k, xyz operand.Op) { ctx.VPMOVZXWD_Z(mxy, k, xyz) } -// POPCNTQ: Count of Number of Bits Set to 1. +// VPMOVZXWQ: Move Packed Word Integers to Quadword Integers with Zero Extension. // // Forms: // -// POPCNTQ r64 r64 -// POPCNTQ m64 r64 -// Construct and append a POPCNTQ instruction to the active function. -func (c *Context) POPCNTQ(mr, r operand.Op) { - if inst, err := x86.POPCNTQ(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVZXWQ m64 ymm +// VPMOVZXWQ xmm ymm +// VPMOVZXWQ m32 xmm +// VPMOVZXWQ xmm xmm +// VPMOVZXWQ m32 k xmm +// VPMOVZXWQ m64 k ymm +// VPMOVZXWQ xmm k xmm +// VPMOVZXWQ xmm k ymm +// VPMOVZXWQ m128 k zmm +// VPMOVZXWQ m128 zmm +// VPMOVZXWQ xmm k zmm +// VPMOVZXWQ xmm zmm +// Construct and append a VPMOVZXWQ instruction to the active function. +func (c *Context) VPMOVZXWQ(ops ...operand.Op) { + c.addinstruction(x86.VPMOVZXWQ(ops...)) } -// POPCNTQ: Count of Number of Bits Set to 1. +// VPMOVZXWQ: Move Packed Word Integers to Quadword Integers with Zero Extension. // // Forms: // -// POPCNTQ r64 r64 -// POPCNTQ m64 r64 -// Construct and append a POPCNTQ instruction to the active function. +// VPMOVZXWQ m64 ymm +// VPMOVZXWQ xmm ymm +// VPMOVZXWQ m32 xmm +// VPMOVZXWQ xmm xmm +// VPMOVZXWQ m32 k xmm +// VPMOVZXWQ m64 k ymm +// VPMOVZXWQ xmm k xmm +// VPMOVZXWQ xmm k ymm +// VPMOVZXWQ m128 k zmm +// VPMOVZXWQ m128 zmm +// VPMOVZXWQ xmm k zmm +// VPMOVZXWQ xmm zmm +// Construct and append a VPMOVZXWQ instruction to the active function. // Operates on the global context. -func POPCNTQ(mr, r operand.Op) { ctx.POPCNTQ(mr, r) } +func VPMOVZXWQ(ops ...operand.Op) { ctx.VPMOVZXWQ(ops...) } -// POPCNTW: Count of Number of Bits Set to 1. +// VPMOVZXWQ_Z: Move Packed Word Integers to Quadword Integers with Zero Extension (Zeroing Masking). // // Forms: // -// POPCNTW r16 r16 -// POPCNTW m16 r16 -// Construct and append a POPCNTW instruction to the active function. -func (c *Context) POPCNTW(mr, r operand.Op) { - if inst, err := x86.POPCNTW(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMOVZXWQ.Z m32 k xmm +// VPMOVZXWQ.Z m64 k ymm +// VPMOVZXWQ.Z xmm k xmm +// VPMOVZXWQ.Z xmm k ymm +// VPMOVZXWQ.Z m128 k zmm +// VPMOVZXWQ.Z xmm k zmm +// Construct and append a VPMOVZXWQ.Z instruction to the active function. +func (c *Context) VPMOVZXWQ_Z(mx, k, xyz operand.Op) { + c.addinstruction(x86.VPMOVZXWQ_Z(mx, k, xyz)) } -// POPCNTW: Count of Number of Bits Set to 1. +// VPMOVZXWQ_Z: Move Packed Word Integers to Quadword Integers with Zero Extension (Zeroing Masking). // // Forms: // -// POPCNTW r16 r16 -// POPCNTW m16 r16 -// Construct and append a POPCNTW instruction to the active function. +// VPMOVZXWQ.Z m32 k xmm +// VPMOVZXWQ.Z m64 k ymm +// VPMOVZXWQ.Z xmm k xmm +// VPMOVZXWQ.Z xmm k ymm +// VPMOVZXWQ.Z m128 k zmm +// VPMOVZXWQ.Z xmm k zmm +// Construct and append a VPMOVZXWQ.Z instruction to the active function. // Operates on the global context. -func POPCNTW(mr, r operand.Op) { ctx.POPCNTW(mr, r) } +func VPMOVZXWQ_Z(mx, k, xyz operand.Op) { ctx.VPMOVZXWQ_Z(mx, k, xyz) } -// POPQ: Pop a Value from the Stack. +// VPMULDQ: Multiply Packed Signed Doubleword Integers and Store Quadword Result. // // Forms: // -// POPQ r64 -// POPQ m64 -// Construct and append a POPQ instruction to the active function. -func (c *Context) POPQ(mr operand.Op) { - if inst, err := x86.POPQ(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMULDQ m256 ymm ymm +// VPMULDQ ymm ymm ymm +// VPMULDQ m128 xmm xmm +// VPMULDQ xmm xmm xmm +// VPMULDQ m128 xmm k xmm +// VPMULDQ m256 ymm k ymm +// VPMULDQ xmm xmm k xmm +// VPMULDQ ymm ymm k ymm +// VPMULDQ m512 zmm k zmm +// VPMULDQ m512 zmm zmm +// VPMULDQ zmm zmm k zmm +// VPMULDQ zmm zmm zmm +// Construct and append a VPMULDQ instruction to the active function. +func (c *Context) VPMULDQ(ops ...operand.Op) { + c.addinstruction(x86.VPMULDQ(ops...)) } -// POPQ: Pop a Value from the Stack. +// VPMULDQ: Multiply Packed Signed Doubleword Integers and Store Quadword Result. // // Forms: // -// POPQ r64 -// POPQ m64 -// Construct and append a POPQ instruction to the active function. +// VPMULDQ m256 ymm ymm +// VPMULDQ ymm ymm ymm +// VPMULDQ m128 xmm xmm +// VPMULDQ xmm xmm xmm +// VPMULDQ m128 xmm k xmm +// VPMULDQ m256 ymm k ymm +// VPMULDQ xmm xmm k xmm +// VPMULDQ ymm ymm k ymm +// VPMULDQ m512 zmm k zmm +// VPMULDQ m512 zmm zmm +// VPMULDQ zmm zmm k zmm +// VPMULDQ zmm zmm zmm +// Construct and append a VPMULDQ instruction to the active function. // Operates on the global context. -func POPQ(mr operand.Op) { ctx.POPQ(mr) } +func VPMULDQ(ops ...operand.Op) { ctx.VPMULDQ(ops...) } -// POPW: Pop a Value from the Stack. +// VPMULDQ_BCST: Multiply Packed Signed Doubleword Integers and Store Quadword Result (Broadcast). // // Forms: // -// POPW r16 -// POPW m16 -// Construct and append a POPW instruction to the active function. -func (c *Context) POPW(mr operand.Op) { - if inst, err := x86.POPW(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMULDQ.BCST m64 xmm k xmm +// VPMULDQ.BCST m64 xmm xmm +// VPMULDQ.BCST m64 ymm k ymm +// VPMULDQ.BCST m64 ymm ymm +// VPMULDQ.BCST m64 zmm k zmm +// VPMULDQ.BCST m64 zmm zmm +// Construct and append a VPMULDQ.BCST instruction to the active function. +func (c *Context) VPMULDQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPMULDQ_BCST(ops...)) } -// POPW: Pop a Value from the Stack. +// VPMULDQ_BCST: Multiply Packed Signed Doubleword Integers and Store Quadword Result (Broadcast). // // Forms: // -// POPW r16 -// POPW m16 -// Construct and append a POPW instruction to the active function. +// VPMULDQ.BCST m64 xmm k xmm +// VPMULDQ.BCST m64 xmm xmm +// VPMULDQ.BCST m64 ymm k ymm +// VPMULDQ.BCST m64 ymm ymm +// VPMULDQ.BCST m64 zmm k zmm +// VPMULDQ.BCST m64 zmm zmm +// Construct and append a VPMULDQ.BCST instruction to the active function. // Operates on the global context. -func POPW(mr operand.Op) { ctx.POPW(mr) } +func VPMULDQ_BCST(ops ...operand.Op) { ctx.VPMULDQ_BCST(ops...) } -// POR: Packed Bitwise Logical OR. +// VPMULDQ_BCST_Z: Multiply Packed Signed Doubleword Integers and Store Quadword Result (Broadcast, Zeroing Masking). // // Forms: // -// POR xmm xmm -// POR m128 xmm -// Construct and append a POR instruction to the active function. -func (c *Context) POR(mx, x operand.Op) { - if inst, err := x86.POR(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMULDQ.BCST.Z m64 xmm k xmm +// VPMULDQ.BCST.Z m64 ymm k ymm +// VPMULDQ.BCST.Z m64 zmm k zmm +// Construct and append a VPMULDQ.BCST.Z instruction to the active function. +func (c *Context) VPMULDQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMULDQ_BCST_Z(m, xyz, k, xyz1)) } -// POR: Packed Bitwise Logical OR. +// VPMULDQ_BCST_Z: Multiply Packed Signed Doubleword Integers and Store Quadword Result (Broadcast, Zeroing Masking). // // Forms: // -// POR xmm xmm -// POR m128 xmm -// Construct and append a POR instruction to the active function. +// VPMULDQ.BCST.Z m64 xmm k xmm +// VPMULDQ.BCST.Z m64 ymm k ymm +// VPMULDQ.BCST.Z m64 zmm k zmm +// Construct and append a VPMULDQ.BCST.Z instruction to the active function. // Operates on the global context. -func POR(mx, x operand.Op) { ctx.POR(mx, x) } +func VPMULDQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPMULDQ_BCST_Z(m, xyz, k, xyz1) } -// PREFETCHNTA: Prefetch Data Into Caches using NTA Hint. +// VPMULDQ_Z: Multiply Packed Signed Doubleword Integers and Store Quadword Result (Zeroing Masking). // // Forms: // -// PREFETCHNTA m8 -// Construct and append a PREFETCHNTA instruction to the active function. -func (c *Context) PREFETCHNTA(m operand.Op) { - if inst, err := x86.PREFETCHNTA(m); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMULDQ.Z m128 xmm k xmm +// VPMULDQ.Z m256 ymm k ymm +// VPMULDQ.Z xmm xmm k xmm +// VPMULDQ.Z ymm ymm k ymm +// VPMULDQ.Z m512 zmm k zmm +// VPMULDQ.Z zmm zmm k zmm +// Construct and append a VPMULDQ.Z instruction to the active function. +func (c *Context) VPMULDQ_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMULDQ_Z(mxyz, xyz, k, xyz1)) } -// PREFETCHNTA: Prefetch Data Into Caches using NTA Hint. +// VPMULDQ_Z: Multiply Packed Signed Doubleword Integers and Store Quadword Result (Zeroing Masking). // // Forms: // -// PREFETCHNTA m8 -// Construct and append a PREFETCHNTA instruction to the active function. +// VPMULDQ.Z m128 xmm k xmm +// VPMULDQ.Z m256 ymm k ymm +// VPMULDQ.Z xmm xmm k xmm +// VPMULDQ.Z ymm ymm k ymm +// VPMULDQ.Z m512 zmm k zmm +// VPMULDQ.Z zmm zmm k zmm +// Construct and append a VPMULDQ.Z instruction to the active function. // Operates on the global context. -func PREFETCHNTA(m operand.Op) { ctx.PREFETCHNTA(m) } +func VPMULDQ_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPMULDQ_Z(mxyz, xyz, k, xyz1) } -// PREFETCHT0: Prefetch Data Into Caches using T0 Hint. +// VPMULHRSW: Packed Multiply Signed Word Integers and Store High Result with Round and Scale. // // Forms: // -// PREFETCHT0 m8 -// Construct and append a PREFETCHT0 instruction to the active function. -func (c *Context) PREFETCHT0(m operand.Op) { - if inst, err := x86.PREFETCHT0(m); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMULHRSW m256 ymm ymm +// VPMULHRSW ymm ymm ymm +// VPMULHRSW m128 xmm xmm +// VPMULHRSW xmm xmm xmm +// VPMULHRSW m128 xmm k xmm +// VPMULHRSW m256 ymm k ymm +// VPMULHRSW xmm xmm k xmm +// VPMULHRSW ymm ymm k ymm +// VPMULHRSW m512 zmm k zmm +// VPMULHRSW m512 zmm zmm +// VPMULHRSW zmm zmm k zmm +// VPMULHRSW zmm zmm zmm +// Construct and append a VPMULHRSW instruction to the active function. +func (c *Context) VPMULHRSW(ops ...operand.Op) { + c.addinstruction(x86.VPMULHRSW(ops...)) } -// PREFETCHT0: Prefetch Data Into Caches using T0 Hint. +// VPMULHRSW: Packed Multiply Signed Word Integers and Store High Result with Round and Scale. // // Forms: // -// PREFETCHT0 m8 -// Construct and append a PREFETCHT0 instruction to the active function. +// VPMULHRSW m256 ymm ymm +// VPMULHRSW ymm ymm ymm +// VPMULHRSW m128 xmm xmm +// VPMULHRSW xmm xmm xmm +// VPMULHRSW m128 xmm k xmm +// VPMULHRSW m256 ymm k ymm +// VPMULHRSW xmm xmm k xmm +// VPMULHRSW ymm ymm k ymm +// VPMULHRSW m512 zmm k zmm +// VPMULHRSW m512 zmm zmm +// VPMULHRSW zmm zmm k zmm +// VPMULHRSW zmm zmm zmm +// Construct and append a VPMULHRSW instruction to the active function. // Operates on the global context. -func PREFETCHT0(m operand.Op) { ctx.PREFETCHT0(m) } +func VPMULHRSW(ops ...operand.Op) { ctx.VPMULHRSW(ops...) } -// PREFETCHT1: Prefetch Data Into Caches using T1 Hint. +// VPMULHRSW_Z: Packed Multiply Signed Word Integers and Store High Result with Round and Scale (Zeroing Masking). // // Forms: // -// PREFETCHT1 m8 -// Construct and append a PREFETCHT1 instruction to the active function. -func (c *Context) PREFETCHT1(m operand.Op) { - if inst, err := x86.PREFETCHT1(m); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMULHRSW.Z m128 xmm k xmm +// VPMULHRSW.Z m256 ymm k ymm +// VPMULHRSW.Z xmm xmm k xmm +// VPMULHRSW.Z ymm ymm k ymm +// VPMULHRSW.Z m512 zmm k zmm +// VPMULHRSW.Z zmm zmm k zmm +// Construct and append a VPMULHRSW.Z instruction to the active function. +func (c *Context) VPMULHRSW_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMULHRSW_Z(mxyz, xyz, k, xyz1)) } -// PREFETCHT1: Prefetch Data Into Caches using T1 Hint. +// VPMULHRSW_Z: Packed Multiply Signed Word Integers and Store High Result with Round and Scale (Zeroing Masking). // // Forms: // -// PREFETCHT1 m8 -// Construct and append a PREFETCHT1 instruction to the active function. +// VPMULHRSW.Z m128 xmm k xmm +// VPMULHRSW.Z m256 ymm k ymm +// VPMULHRSW.Z xmm xmm k xmm +// VPMULHRSW.Z ymm ymm k ymm +// VPMULHRSW.Z m512 zmm k zmm +// VPMULHRSW.Z zmm zmm k zmm +// Construct and append a VPMULHRSW.Z instruction to the active function. // Operates on the global context. -func PREFETCHT1(m operand.Op) { ctx.PREFETCHT1(m) } +func VPMULHRSW_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPMULHRSW_Z(mxyz, xyz, k, xyz1) } -// PREFETCHT2: Prefetch Data Into Caches using T2 Hint. +// VPMULHUW: Multiply Packed Unsigned Word Integers and Store High Result. // // Forms: // -// PREFETCHT2 m8 -// Construct and append a PREFETCHT2 instruction to the active function. -func (c *Context) PREFETCHT2(m operand.Op) { - if inst, err := x86.PREFETCHT2(m); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMULHUW m256 ymm ymm +// VPMULHUW ymm ymm ymm +// VPMULHUW m128 xmm xmm +// VPMULHUW xmm xmm xmm +// VPMULHUW m128 xmm k xmm +// VPMULHUW m256 ymm k ymm +// VPMULHUW xmm xmm k xmm +// VPMULHUW ymm ymm k ymm +// VPMULHUW m512 zmm k zmm +// VPMULHUW m512 zmm zmm +// VPMULHUW zmm zmm k zmm +// VPMULHUW zmm zmm zmm +// Construct and append a VPMULHUW instruction to the active function. +func (c *Context) VPMULHUW(ops ...operand.Op) { + c.addinstruction(x86.VPMULHUW(ops...)) } -// PREFETCHT2: Prefetch Data Into Caches using T2 Hint. +// VPMULHUW: Multiply Packed Unsigned Word Integers and Store High Result. // // Forms: // -// PREFETCHT2 m8 -// Construct and append a PREFETCHT2 instruction to the active function. +// VPMULHUW m256 ymm ymm +// VPMULHUW ymm ymm ymm +// VPMULHUW m128 xmm xmm +// VPMULHUW xmm xmm xmm +// VPMULHUW m128 xmm k xmm +// VPMULHUW m256 ymm k ymm +// VPMULHUW xmm xmm k xmm +// VPMULHUW ymm ymm k ymm +// VPMULHUW m512 zmm k zmm +// VPMULHUW m512 zmm zmm +// VPMULHUW zmm zmm k zmm +// VPMULHUW zmm zmm zmm +// Construct and append a VPMULHUW instruction to the active function. // Operates on the global context. -func PREFETCHT2(m operand.Op) { ctx.PREFETCHT2(m) } +func VPMULHUW(ops ...operand.Op) { ctx.VPMULHUW(ops...) } -// PSADBW: Compute Sum of Absolute Differences. +// VPMULHUW_Z: Multiply Packed Unsigned Word Integers and Store High Result (Zeroing Masking). // // Forms: // -// PSADBW xmm xmm -// PSADBW m128 xmm -// Construct and append a PSADBW instruction to the active function. -func (c *Context) PSADBW(mx, x operand.Op) { - if inst, err := x86.PSADBW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMULHUW.Z m128 xmm k xmm +// VPMULHUW.Z m256 ymm k ymm +// VPMULHUW.Z xmm xmm k xmm +// VPMULHUW.Z ymm ymm k ymm +// VPMULHUW.Z m512 zmm k zmm +// VPMULHUW.Z zmm zmm k zmm +// Construct and append a VPMULHUW.Z instruction to the active function. +func (c *Context) VPMULHUW_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMULHUW_Z(mxyz, xyz, k, xyz1)) } -// PSADBW: Compute Sum of Absolute Differences. +// VPMULHUW_Z: Multiply Packed Unsigned Word Integers and Store High Result (Zeroing Masking). // // Forms: // -// PSADBW xmm xmm -// PSADBW m128 xmm -// Construct and append a PSADBW instruction to the active function. +// VPMULHUW.Z m128 xmm k xmm +// VPMULHUW.Z m256 ymm k ymm +// VPMULHUW.Z xmm xmm k xmm +// VPMULHUW.Z ymm ymm k ymm +// VPMULHUW.Z m512 zmm k zmm +// VPMULHUW.Z zmm zmm k zmm +// Construct and append a VPMULHUW.Z instruction to the active function. // Operates on the global context. -func PSADBW(mx, x operand.Op) { ctx.PSADBW(mx, x) } +func VPMULHUW_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPMULHUW_Z(mxyz, xyz, k, xyz1) } -// PSHUFB: Packed Shuffle Bytes. +// VPMULHW: Multiply Packed Signed Word Integers and Store High Result. // // Forms: // -// PSHUFB xmm xmm -// PSHUFB m128 xmm -// Construct and append a PSHUFB instruction to the active function. -func (c *Context) PSHUFB(mx, x operand.Op) { - if inst, err := x86.PSHUFB(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMULHW m256 ymm ymm +// VPMULHW ymm ymm ymm +// VPMULHW m128 xmm xmm +// VPMULHW xmm xmm xmm +// VPMULHW m128 xmm k xmm +// VPMULHW m256 ymm k ymm +// VPMULHW xmm xmm k xmm +// VPMULHW ymm ymm k ymm +// VPMULHW m512 zmm k zmm +// VPMULHW m512 zmm zmm +// VPMULHW zmm zmm k zmm +// VPMULHW zmm zmm zmm +// Construct and append a VPMULHW instruction to the active function. +func (c *Context) VPMULHW(ops ...operand.Op) { + c.addinstruction(x86.VPMULHW(ops...)) } -// PSHUFB: Packed Shuffle Bytes. +// VPMULHW: Multiply Packed Signed Word Integers and Store High Result. // // Forms: // -// PSHUFB xmm xmm -// PSHUFB m128 xmm -// Construct and append a PSHUFB instruction to the active function. +// VPMULHW m256 ymm ymm +// VPMULHW ymm ymm ymm +// VPMULHW m128 xmm xmm +// VPMULHW xmm xmm xmm +// VPMULHW m128 xmm k xmm +// VPMULHW m256 ymm k ymm +// VPMULHW xmm xmm k xmm +// VPMULHW ymm ymm k ymm +// VPMULHW m512 zmm k zmm +// VPMULHW m512 zmm zmm +// VPMULHW zmm zmm k zmm +// VPMULHW zmm zmm zmm +// Construct and append a VPMULHW instruction to the active function. // Operates on the global context. -func PSHUFB(mx, x operand.Op) { ctx.PSHUFB(mx, x) } +func VPMULHW(ops ...operand.Op) { ctx.VPMULHW(ops...) } -// PSHUFD: Shuffle Packed Doublewords. +// VPMULHW_Z: Multiply Packed Signed Word Integers and Store High Result (Zeroing Masking). // // Forms: // -// PSHUFD imm8 xmm xmm -// PSHUFD imm8 m128 xmm -// Construct and append a PSHUFD instruction to the active function. -func (c *Context) PSHUFD(i, mx, x operand.Op) { - if inst, err := x86.PSHUFD(i, mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMULHW.Z m128 xmm k xmm +// VPMULHW.Z m256 ymm k ymm +// VPMULHW.Z xmm xmm k xmm +// VPMULHW.Z ymm ymm k ymm +// VPMULHW.Z m512 zmm k zmm +// VPMULHW.Z zmm zmm k zmm +// Construct and append a VPMULHW.Z instruction to the active function. +func (c *Context) VPMULHW_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMULHW_Z(mxyz, xyz, k, xyz1)) } -// PSHUFD: Shuffle Packed Doublewords. +// VPMULHW_Z: Multiply Packed Signed Word Integers and Store High Result (Zeroing Masking). // // Forms: // -// PSHUFD imm8 xmm xmm -// PSHUFD imm8 m128 xmm -// Construct and append a PSHUFD instruction to the active function. +// VPMULHW.Z m128 xmm k xmm +// VPMULHW.Z m256 ymm k ymm +// VPMULHW.Z xmm xmm k xmm +// VPMULHW.Z ymm ymm k ymm +// VPMULHW.Z m512 zmm k zmm +// VPMULHW.Z zmm zmm k zmm +// Construct and append a VPMULHW.Z instruction to the active function. // Operates on the global context. -func PSHUFD(i, mx, x operand.Op) { ctx.PSHUFD(i, mx, x) } +func VPMULHW_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPMULHW_Z(mxyz, xyz, k, xyz1) } -// PSHUFHW: Shuffle Packed High Words. +// VPMULLD: Multiply Packed Signed Doubleword Integers and Store Low Result. // // Forms: // -// PSHUFHW imm8 xmm xmm -// PSHUFHW imm8 m128 xmm -// Construct and append a PSHUFHW instruction to the active function. -func (c *Context) PSHUFHW(i, mx, x operand.Op) { - if inst, err := x86.PSHUFHW(i, mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMULLD m256 ymm ymm +// VPMULLD ymm ymm ymm +// VPMULLD m128 xmm xmm +// VPMULLD xmm xmm xmm +// VPMULLD m128 xmm k xmm +// VPMULLD m256 ymm k ymm +// VPMULLD xmm xmm k xmm +// VPMULLD ymm ymm k ymm +// VPMULLD m512 zmm k zmm +// VPMULLD m512 zmm zmm +// VPMULLD zmm zmm k zmm +// VPMULLD zmm zmm zmm +// Construct and append a VPMULLD instruction to the active function. +func (c *Context) VPMULLD(ops ...operand.Op) { + c.addinstruction(x86.VPMULLD(ops...)) } -// PSHUFHW: Shuffle Packed High Words. +// VPMULLD: Multiply Packed Signed Doubleword Integers and Store Low Result. // // Forms: // -// PSHUFHW imm8 xmm xmm -// PSHUFHW imm8 m128 xmm -// Construct and append a PSHUFHW instruction to the active function. +// VPMULLD m256 ymm ymm +// VPMULLD ymm ymm ymm +// VPMULLD m128 xmm xmm +// VPMULLD xmm xmm xmm +// VPMULLD m128 xmm k xmm +// VPMULLD m256 ymm k ymm +// VPMULLD xmm xmm k xmm +// VPMULLD ymm ymm k ymm +// VPMULLD m512 zmm k zmm +// VPMULLD m512 zmm zmm +// VPMULLD zmm zmm k zmm +// VPMULLD zmm zmm zmm +// Construct and append a VPMULLD instruction to the active function. // Operates on the global context. -func PSHUFHW(i, mx, x operand.Op) { ctx.PSHUFHW(i, mx, x) } +func VPMULLD(ops ...operand.Op) { ctx.VPMULLD(ops...) } -// PSHUFL: Shuffle Packed Doublewords. +// VPMULLD_BCST: Multiply Packed Signed Doubleword Integers and Store Low Result (Broadcast). // // Forms: // -// PSHUFL imm8 xmm xmm -// PSHUFL imm8 m128 xmm -// Construct and append a PSHUFL instruction to the active function. -func (c *Context) PSHUFL(i, mx, x operand.Op) { - if inst, err := x86.PSHUFL(i, mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMULLD.BCST m32 xmm k xmm +// VPMULLD.BCST m32 xmm xmm +// VPMULLD.BCST m32 ymm k ymm +// VPMULLD.BCST m32 ymm ymm +// VPMULLD.BCST m32 zmm k zmm +// VPMULLD.BCST m32 zmm zmm +// Construct and append a VPMULLD.BCST instruction to the active function. +func (c *Context) VPMULLD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPMULLD_BCST(ops...)) } -// PSHUFL: Shuffle Packed Doublewords. +// VPMULLD_BCST: Multiply Packed Signed Doubleword Integers and Store Low Result (Broadcast). // // Forms: // -// PSHUFL imm8 xmm xmm -// PSHUFL imm8 m128 xmm -// Construct and append a PSHUFL instruction to the active function. +// VPMULLD.BCST m32 xmm k xmm +// VPMULLD.BCST m32 xmm xmm +// VPMULLD.BCST m32 ymm k ymm +// VPMULLD.BCST m32 ymm ymm +// VPMULLD.BCST m32 zmm k zmm +// VPMULLD.BCST m32 zmm zmm +// Construct and append a VPMULLD.BCST instruction to the active function. // Operates on the global context. -func PSHUFL(i, mx, x operand.Op) { ctx.PSHUFL(i, mx, x) } +func VPMULLD_BCST(ops ...operand.Op) { ctx.VPMULLD_BCST(ops...) } -// PSHUFLW: Shuffle Packed Low Words. +// VPMULLD_BCST_Z: Multiply Packed Signed Doubleword Integers and Store Low Result (Broadcast, Zeroing Masking). // // Forms: // -// PSHUFLW imm8 xmm xmm -// PSHUFLW imm8 m128 xmm -// Construct and append a PSHUFLW instruction to the active function. -func (c *Context) PSHUFLW(i, mx, x operand.Op) { - if inst, err := x86.PSHUFLW(i, mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMULLD.BCST.Z m32 xmm k xmm +// VPMULLD.BCST.Z m32 ymm k ymm +// VPMULLD.BCST.Z m32 zmm k zmm +// Construct and append a VPMULLD.BCST.Z instruction to the active function. +func (c *Context) VPMULLD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMULLD_BCST_Z(m, xyz, k, xyz1)) } -// PSHUFLW: Shuffle Packed Low Words. +// VPMULLD_BCST_Z: Multiply Packed Signed Doubleword Integers and Store Low Result (Broadcast, Zeroing Masking). // // Forms: // -// PSHUFLW imm8 xmm xmm -// PSHUFLW imm8 m128 xmm -// Construct and append a PSHUFLW instruction to the active function. +// VPMULLD.BCST.Z m32 xmm k xmm +// VPMULLD.BCST.Z m32 ymm k ymm +// VPMULLD.BCST.Z m32 zmm k zmm +// Construct and append a VPMULLD.BCST.Z instruction to the active function. // Operates on the global context. -func PSHUFLW(i, mx, x operand.Op) { ctx.PSHUFLW(i, mx, x) } +func VPMULLD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPMULLD_BCST_Z(m, xyz, k, xyz1) } -// PSIGNB: Packed Sign of Byte Integers. +// VPMULLD_Z: Multiply Packed Signed Doubleword Integers and Store Low Result (Zeroing Masking). // // Forms: // -// PSIGNB xmm xmm -// PSIGNB m128 xmm -// Construct and append a PSIGNB instruction to the active function. -func (c *Context) PSIGNB(mx, x operand.Op) { - if inst, err := x86.PSIGNB(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMULLD.Z m128 xmm k xmm +// VPMULLD.Z m256 ymm k ymm +// VPMULLD.Z xmm xmm k xmm +// VPMULLD.Z ymm ymm k ymm +// VPMULLD.Z m512 zmm k zmm +// VPMULLD.Z zmm zmm k zmm +// Construct and append a VPMULLD.Z instruction to the active function. +func (c *Context) VPMULLD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMULLD_Z(mxyz, xyz, k, xyz1)) } -// PSIGNB: Packed Sign of Byte Integers. +// VPMULLD_Z: Multiply Packed Signed Doubleword Integers and Store Low Result (Zeroing Masking). // // Forms: // -// PSIGNB xmm xmm -// PSIGNB m128 xmm -// Construct and append a PSIGNB instruction to the active function. +// VPMULLD.Z m128 xmm k xmm +// VPMULLD.Z m256 ymm k ymm +// VPMULLD.Z xmm xmm k xmm +// VPMULLD.Z ymm ymm k ymm +// VPMULLD.Z m512 zmm k zmm +// VPMULLD.Z zmm zmm k zmm +// Construct and append a VPMULLD.Z instruction to the active function. // Operates on the global context. -func PSIGNB(mx, x operand.Op) { ctx.PSIGNB(mx, x) } +func VPMULLD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPMULLD_Z(mxyz, xyz, k, xyz1) } -// PSIGND: Packed Sign of Doubleword Integers. +// VPMULLQ: Multiply Packed Signed Quadword Integers and Store Low Result. // // Forms: // -// PSIGND xmm xmm -// PSIGND m128 xmm -// Construct and append a PSIGND instruction to the active function. -func (c *Context) PSIGND(mx, x operand.Op) { - if inst, err := x86.PSIGND(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMULLQ m128 xmm k xmm +// VPMULLQ m128 xmm xmm +// VPMULLQ m256 ymm k ymm +// VPMULLQ m256 ymm ymm +// VPMULLQ xmm xmm k xmm +// VPMULLQ xmm xmm xmm +// VPMULLQ ymm ymm k ymm +// VPMULLQ ymm ymm ymm +// VPMULLQ m512 zmm k zmm +// VPMULLQ m512 zmm zmm +// VPMULLQ zmm zmm k zmm +// VPMULLQ zmm zmm zmm +// Construct and append a VPMULLQ instruction to the active function. +func (c *Context) VPMULLQ(ops ...operand.Op) { + c.addinstruction(x86.VPMULLQ(ops...)) } -// PSIGND: Packed Sign of Doubleword Integers. +// VPMULLQ: Multiply Packed Signed Quadword Integers and Store Low Result. // // Forms: // -// PSIGND xmm xmm -// PSIGND m128 xmm -// Construct and append a PSIGND instruction to the active function. +// VPMULLQ m128 xmm k xmm +// VPMULLQ m128 xmm xmm +// VPMULLQ m256 ymm k ymm +// VPMULLQ m256 ymm ymm +// VPMULLQ xmm xmm k xmm +// VPMULLQ xmm xmm xmm +// VPMULLQ ymm ymm k ymm +// VPMULLQ ymm ymm ymm +// VPMULLQ m512 zmm k zmm +// VPMULLQ m512 zmm zmm +// VPMULLQ zmm zmm k zmm +// VPMULLQ zmm zmm zmm +// Construct and append a VPMULLQ instruction to the active function. // Operates on the global context. -func PSIGND(mx, x operand.Op) { ctx.PSIGND(mx, x) } +func VPMULLQ(ops ...operand.Op) { ctx.VPMULLQ(ops...) } -// PSIGNW: Packed Sign of Word Integers. +// VPMULLQ_BCST: Multiply Packed Signed Quadword Integers and Store Low Result (Broadcast). // // Forms: // -// PSIGNW xmm xmm -// PSIGNW m128 xmm -// Construct and append a PSIGNW instruction to the active function. -func (c *Context) PSIGNW(mx, x operand.Op) { - if inst, err := x86.PSIGNW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMULLQ.BCST m64 xmm k xmm +// VPMULLQ.BCST m64 xmm xmm +// VPMULLQ.BCST m64 ymm k ymm +// VPMULLQ.BCST m64 ymm ymm +// VPMULLQ.BCST m64 zmm k zmm +// VPMULLQ.BCST m64 zmm zmm +// Construct and append a VPMULLQ.BCST instruction to the active function. +func (c *Context) VPMULLQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPMULLQ_BCST(ops...)) } -// PSIGNW: Packed Sign of Word Integers. +// VPMULLQ_BCST: Multiply Packed Signed Quadword Integers and Store Low Result (Broadcast). // // Forms: // -// PSIGNW xmm xmm -// PSIGNW m128 xmm -// Construct and append a PSIGNW instruction to the active function. +// VPMULLQ.BCST m64 xmm k xmm +// VPMULLQ.BCST m64 xmm xmm +// VPMULLQ.BCST m64 ymm k ymm +// VPMULLQ.BCST m64 ymm ymm +// VPMULLQ.BCST m64 zmm k zmm +// VPMULLQ.BCST m64 zmm zmm +// Construct and append a VPMULLQ.BCST instruction to the active function. // Operates on the global context. -func PSIGNW(mx, x operand.Op) { ctx.PSIGNW(mx, x) } +func VPMULLQ_BCST(ops ...operand.Op) { ctx.VPMULLQ_BCST(ops...) } -// PSLLDQ: Shift Packed Double Quadword Left Logical. +// VPMULLQ_BCST_Z: Multiply Packed Signed Quadword Integers and Store Low Result (Broadcast, Zeroing Masking). // // Forms: // -// PSLLDQ imm8 xmm -// Construct and append a PSLLDQ instruction to the active function. -func (c *Context) PSLLDQ(i, x operand.Op) { - if inst, err := x86.PSLLDQ(i, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMULLQ.BCST.Z m64 xmm k xmm +// VPMULLQ.BCST.Z m64 ymm k ymm +// VPMULLQ.BCST.Z m64 zmm k zmm +// Construct and append a VPMULLQ.BCST.Z instruction to the active function. +func (c *Context) VPMULLQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMULLQ_BCST_Z(m, xyz, k, xyz1)) } -// PSLLDQ: Shift Packed Double Quadword Left Logical. +// VPMULLQ_BCST_Z: Multiply Packed Signed Quadword Integers and Store Low Result (Broadcast, Zeroing Masking). // // Forms: // -// PSLLDQ imm8 xmm -// Construct and append a PSLLDQ instruction to the active function. +// VPMULLQ.BCST.Z m64 xmm k xmm +// VPMULLQ.BCST.Z m64 ymm k ymm +// VPMULLQ.BCST.Z m64 zmm k zmm +// Construct and append a VPMULLQ.BCST.Z instruction to the active function. // Operates on the global context. -func PSLLDQ(i, x operand.Op) { ctx.PSLLDQ(i, x) } +func VPMULLQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPMULLQ_BCST_Z(m, xyz, k, xyz1) } -// PSLLL: Shift Packed Doubleword Data Left Logical. +// VPMULLQ_Z: Multiply Packed Signed Quadword Integers and Store Low Result (Zeroing Masking). // // Forms: // -// PSLLL imm8 xmm -// PSLLL xmm xmm -// PSLLL m128 xmm -// Construct and append a PSLLL instruction to the active function. -func (c *Context) PSLLL(imx, x operand.Op) { - if inst, err := x86.PSLLL(imx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMULLQ.Z m128 xmm k xmm +// VPMULLQ.Z m256 ymm k ymm +// VPMULLQ.Z xmm xmm k xmm +// VPMULLQ.Z ymm ymm k ymm +// VPMULLQ.Z m512 zmm k zmm +// VPMULLQ.Z zmm zmm k zmm +// Construct and append a VPMULLQ.Z instruction to the active function. +func (c *Context) VPMULLQ_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMULLQ_Z(mxyz, xyz, k, xyz1)) } -// PSLLL: Shift Packed Doubleword Data Left Logical. +// VPMULLQ_Z: Multiply Packed Signed Quadword Integers and Store Low Result (Zeroing Masking). // // Forms: // -// PSLLL imm8 xmm -// PSLLL xmm xmm -// PSLLL m128 xmm -// Construct and append a PSLLL instruction to the active function. +// VPMULLQ.Z m128 xmm k xmm +// VPMULLQ.Z m256 ymm k ymm +// VPMULLQ.Z xmm xmm k xmm +// VPMULLQ.Z ymm ymm k ymm +// VPMULLQ.Z m512 zmm k zmm +// VPMULLQ.Z zmm zmm k zmm +// Construct and append a VPMULLQ.Z instruction to the active function. // Operates on the global context. -func PSLLL(imx, x operand.Op) { ctx.PSLLL(imx, x) } +func VPMULLQ_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPMULLQ_Z(mxyz, xyz, k, xyz1) } -// PSLLO: Shift Packed Double Quadword Left Logical. +// VPMULLW: Multiply Packed Signed Word Integers and Store Low Result. // // Forms: // -// PSLLO imm8 xmm -// Construct and append a PSLLO instruction to the active function. -func (c *Context) PSLLO(i, x operand.Op) { - if inst, err := x86.PSLLO(i, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMULLW m256 ymm ymm +// VPMULLW ymm ymm ymm +// VPMULLW m128 xmm xmm +// VPMULLW xmm xmm xmm +// VPMULLW m128 xmm k xmm +// VPMULLW m256 ymm k ymm +// VPMULLW xmm xmm k xmm +// VPMULLW ymm ymm k ymm +// VPMULLW m512 zmm k zmm +// VPMULLW m512 zmm zmm +// VPMULLW zmm zmm k zmm +// VPMULLW zmm zmm zmm +// Construct and append a VPMULLW instruction to the active function. +func (c *Context) VPMULLW(ops ...operand.Op) { + c.addinstruction(x86.VPMULLW(ops...)) } -// PSLLO: Shift Packed Double Quadword Left Logical. +// VPMULLW: Multiply Packed Signed Word Integers and Store Low Result. // // Forms: // -// PSLLO imm8 xmm -// Construct and append a PSLLO instruction to the active function. +// VPMULLW m256 ymm ymm +// VPMULLW ymm ymm ymm +// VPMULLW m128 xmm xmm +// VPMULLW xmm xmm xmm +// VPMULLW m128 xmm k xmm +// VPMULLW m256 ymm k ymm +// VPMULLW xmm xmm k xmm +// VPMULLW ymm ymm k ymm +// VPMULLW m512 zmm k zmm +// VPMULLW m512 zmm zmm +// VPMULLW zmm zmm k zmm +// VPMULLW zmm zmm zmm +// Construct and append a VPMULLW instruction to the active function. // Operates on the global context. -func PSLLO(i, x operand.Op) { ctx.PSLLO(i, x) } +func VPMULLW(ops ...operand.Op) { ctx.VPMULLW(ops...) } -// PSLLQ: Shift Packed Quadword Data Left Logical. +// VPMULLW_Z: Multiply Packed Signed Word Integers and Store Low Result (Zeroing Masking). // // Forms: // -// PSLLQ imm8 xmm -// PSLLQ xmm xmm -// PSLLQ m128 xmm -// Construct and append a PSLLQ instruction to the active function. -func (c *Context) PSLLQ(imx, x operand.Op) { - if inst, err := x86.PSLLQ(imx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMULLW.Z m128 xmm k xmm +// VPMULLW.Z m256 ymm k ymm +// VPMULLW.Z xmm xmm k xmm +// VPMULLW.Z ymm ymm k ymm +// VPMULLW.Z m512 zmm k zmm +// VPMULLW.Z zmm zmm k zmm +// Construct and append a VPMULLW.Z instruction to the active function. +func (c *Context) VPMULLW_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMULLW_Z(mxyz, xyz, k, xyz1)) } -// PSLLQ: Shift Packed Quadword Data Left Logical. +// VPMULLW_Z: Multiply Packed Signed Word Integers and Store Low Result (Zeroing Masking). // // Forms: // -// PSLLQ imm8 xmm -// PSLLQ xmm xmm -// PSLLQ m128 xmm -// Construct and append a PSLLQ instruction to the active function. +// VPMULLW.Z m128 xmm k xmm +// VPMULLW.Z m256 ymm k ymm +// VPMULLW.Z xmm xmm k xmm +// VPMULLW.Z ymm ymm k ymm +// VPMULLW.Z m512 zmm k zmm +// VPMULLW.Z zmm zmm k zmm +// Construct and append a VPMULLW.Z instruction to the active function. // Operates on the global context. -func PSLLQ(imx, x operand.Op) { ctx.PSLLQ(imx, x) } +func VPMULLW_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPMULLW_Z(mxyz, xyz, k, xyz1) } -// PSLLW: Shift Packed Word Data Left Logical. +// VPMULTISHIFTQB: Select Packed Unaligned Bytes from Quadword Sources. // // Forms: // -// PSLLW imm8 xmm -// PSLLW xmm xmm -// PSLLW m128 xmm -// Construct and append a PSLLW instruction to the active function. -func (c *Context) PSLLW(imx, x operand.Op) { - if inst, err := x86.PSLLW(imx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMULTISHIFTQB m128 xmm k xmm +// VPMULTISHIFTQB m128 xmm xmm +// VPMULTISHIFTQB m256 ymm k ymm +// VPMULTISHIFTQB m256 ymm ymm +// VPMULTISHIFTQB xmm xmm k xmm +// VPMULTISHIFTQB xmm xmm xmm +// VPMULTISHIFTQB ymm ymm k ymm +// VPMULTISHIFTQB ymm ymm ymm +// VPMULTISHIFTQB m512 zmm k zmm +// VPMULTISHIFTQB m512 zmm zmm +// VPMULTISHIFTQB zmm zmm k zmm +// VPMULTISHIFTQB zmm zmm zmm +// Construct and append a VPMULTISHIFTQB instruction to the active function. +func (c *Context) VPMULTISHIFTQB(ops ...operand.Op) { + c.addinstruction(x86.VPMULTISHIFTQB(ops...)) } -// PSLLW: Shift Packed Word Data Left Logical. +// VPMULTISHIFTQB: Select Packed Unaligned Bytes from Quadword Sources. // // Forms: // -// PSLLW imm8 xmm -// PSLLW xmm xmm -// PSLLW m128 xmm -// Construct and append a PSLLW instruction to the active function. +// VPMULTISHIFTQB m128 xmm k xmm +// VPMULTISHIFTQB m128 xmm xmm +// VPMULTISHIFTQB m256 ymm k ymm +// VPMULTISHIFTQB m256 ymm ymm +// VPMULTISHIFTQB xmm xmm k xmm +// VPMULTISHIFTQB xmm xmm xmm +// VPMULTISHIFTQB ymm ymm k ymm +// VPMULTISHIFTQB ymm ymm ymm +// VPMULTISHIFTQB m512 zmm k zmm +// VPMULTISHIFTQB m512 zmm zmm +// VPMULTISHIFTQB zmm zmm k zmm +// VPMULTISHIFTQB zmm zmm zmm +// Construct and append a VPMULTISHIFTQB instruction to the active function. // Operates on the global context. -func PSLLW(imx, x operand.Op) { ctx.PSLLW(imx, x) } +func VPMULTISHIFTQB(ops ...operand.Op) { ctx.VPMULTISHIFTQB(ops...) } -// PSRAL: Shift Packed Doubleword Data Right Arithmetic. +// VPMULTISHIFTQB_BCST: Select Packed Unaligned Bytes from Quadword Sources (Broadcast). // // Forms: // -// PSRAL imm8 xmm -// PSRAL xmm xmm -// PSRAL m128 xmm -// Construct and append a PSRAL instruction to the active function. -func (c *Context) PSRAL(imx, x operand.Op) { - if inst, err := x86.PSRAL(imx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMULTISHIFTQB.BCST m64 xmm k xmm +// VPMULTISHIFTQB.BCST m64 xmm xmm +// VPMULTISHIFTQB.BCST m64 ymm k ymm +// VPMULTISHIFTQB.BCST m64 ymm ymm +// VPMULTISHIFTQB.BCST m64 zmm k zmm +// VPMULTISHIFTQB.BCST m64 zmm zmm +// Construct and append a VPMULTISHIFTQB.BCST instruction to the active function. +func (c *Context) VPMULTISHIFTQB_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPMULTISHIFTQB_BCST(ops...)) } -// PSRAL: Shift Packed Doubleword Data Right Arithmetic. +// VPMULTISHIFTQB_BCST: Select Packed Unaligned Bytes from Quadword Sources (Broadcast). // // Forms: // -// PSRAL imm8 xmm -// PSRAL xmm xmm -// PSRAL m128 xmm -// Construct and append a PSRAL instruction to the active function. +// VPMULTISHIFTQB.BCST m64 xmm k xmm +// VPMULTISHIFTQB.BCST m64 xmm xmm +// VPMULTISHIFTQB.BCST m64 ymm k ymm +// VPMULTISHIFTQB.BCST m64 ymm ymm +// VPMULTISHIFTQB.BCST m64 zmm k zmm +// VPMULTISHIFTQB.BCST m64 zmm zmm +// Construct and append a VPMULTISHIFTQB.BCST instruction to the active function. // Operates on the global context. -func PSRAL(imx, x operand.Op) { ctx.PSRAL(imx, x) } +func VPMULTISHIFTQB_BCST(ops ...operand.Op) { ctx.VPMULTISHIFTQB_BCST(ops...) } -// PSRAW: Shift Packed Word Data Right Arithmetic. +// VPMULTISHIFTQB_BCST_Z: Select Packed Unaligned Bytes from Quadword Sources (Broadcast, Zeroing Masking). // // Forms: // -// PSRAW imm8 xmm -// PSRAW xmm xmm -// PSRAW m128 xmm -// Construct and append a PSRAW instruction to the active function. -func (c *Context) PSRAW(imx, x operand.Op) { - if inst, err := x86.PSRAW(imx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMULTISHIFTQB.BCST.Z m64 xmm k xmm +// VPMULTISHIFTQB.BCST.Z m64 ymm k ymm +// VPMULTISHIFTQB.BCST.Z m64 zmm k zmm +// Construct and append a VPMULTISHIFTQB.BCST.Z instruction to the active function. +func (c *Context) VPMULTISHIFTQB_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMULTISHIFTQB_BCST_Z(m, xyz, k, xyz1)) } -// PSRAW: Shift Packed Word Data Right Arithmetic. +// VPMULTISHIFTQB_BCST_Z: Select Packed Unaligned Bytes from Quadword Sources (Broadcast, Zeroing Masking). // // Forms: // -// PSRAW imm8 xmm -// PSRAW xmm xmm -// PSRAW m128 xmm -// Construct and append a PSRAW instruction to the active function. +// VPMULTISHIFTQB.BCST.Z m64 xmm k xmm +// VPMULTISHIFTQB.BCST.Z m64 ymm k ymm +// VPMULTISHIFTQB.BCST.Z m64 zmm k zmm +// Construct and append a VPMULTISHIFTQB.BCST.Z instruction to the active function. // Operates on the global context. -func PSRAW(imx, x operand.Op) { ctx.PSRAW(imx, x) } +func VPMULTISHIFTQB_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPMULTISHIFTQB_BCST_Z(m, xyz, k, xyz1) } -// PSRLDQ: Shift Packed Double Quadword Right Logical. +// VPMULTISHIFTQB_Z: Select Packed Unaligned Bytes from Quadword Sources (Zeroing Masking). // // Forms: // -// PSRLDQ imm8 xmm -// Construct and append a PSRLDQ instruction to the active function. -func (c *Context) PSRLDQ(i, x operand.Op) { - if inst, err := x86.PSRLDQ(i, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMULTISHIFTQB.Z m128 xmm k xmm +// VPMULTISHIFTQB.Z m256 ymm k ymm +// VPMULTISHIFTQB.Z xmm xmm k xmm +// VPMULTISHIFTQB.Z ymm ymm k ymm +// VPMULTISHIFTQB.Z m512 zmm k zmm +// VPMULTISHIFTQB.Z zmm zmm k zmm +// Construct and append a VPMULTISHIFTQB.Z instruction to the active function. +func (c *Context) VPMULTISHIFTQB_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMULTISHIFTQB_Z(mxyz, xyz, k, xyz1)) } -// PSRLDQ: Shift Packed Double Quadword Right Logical. +// VPMULTISHIFTQB_Z: Select Packed Unaligned Bytes from Quadword Sources (Zeroing Masking). // // Forms: // -// PSRLDQ imm8 xmm -// Construct and append a PSRLDQ instruction to the active function. +// VPMULTISHIFTQB.Z m128 xmm k xmm +// VPMULTISHIFTQB.Z m256 ymm k ymm +// VPMULTISHIFTQB.Z xmm xmm k xmm +// VPMULTISHIFTQB.Z ymm ymm k ymm +// VPMULTISHIFTQB.Z m512 zmm k zmm +// VPMULTISHIFTQB.Z zmm zmm k zmm +// Construct and append a VPMULTISHIFTQB.Z instruction to the active function. // Operates on the global context. -func PSRLDQ(i, x operand.Op) { ctx.PSRLDQ(i, x) } +func VPMULTISHIFTQB_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPMULTISHIFTQB_Z(mxyz, xyz, k, xyz1) } -// PSRLL: Shift Packed Doubleword Data Right Logical. +// VPMULUDQ: Multiply Packed Unsigned Doubleword Integers. // // Forms: // -// PSRLL imm8 xmm -// PSRLL xmm xmm -// PSRLL m128 xmm -// Construct and append a PSRLL instruction to the active function. -func (c *Context) PSRLL(imx, x operand.Op) { - if inst, err := x86.PSRLL(imx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMULUDQ m256 ymm ymm +// VPMULUDQ ymm ymm ymm +// VPMULUDQ m128 xmm xmm +// VPMULUDQ xmm xmm xmm +// VPMULUDQ m128 xmm k xmm +// VPMULUDQ m256 ymm k ymm +// VPMULUDQ xmm xmm k xmm +// VPMULUDQ ymm ymm k ymm +// VPMULUDQ m512 zmm k zmm +// VPMULUDQ m512 zmm zmm +// VPMULUDQ zmm zmm k zmm +// VPMULUDQ zmm zmm zmm +// Construct and append a VPMULUDQ instruction to the active function. +func (c *Context) VPMULUDQ(ops ...operand.Op) { + c.addinstruction(x86.VPMULUDQ(ops...)) } -// PSRLL: Shift Packed Doubleword Data Right Logical. +// VPMULUDQ: Multiply Packed Unsigned Doubleword Integers. // // Forms: // -// PSRLL imm8 xmm -// PSRLL xmm xmm -// PSRLL m128 xmm -// Construct and append a PSRLL instruction to the active function. +// VPMULUDQ m256 ymm ymm +// VPMULUDQ ymm ymm ymm +// VPMULUDQ m128 xmm xmm +// VPMULUDQ xmm xmm xmm +// VPMULUDQ m128 xmm k xmm +// VPMULUDQ m256 ymm k ymm +// VPMULUDQ xmm xmm k xmm +// VPMULUDQ ymm ymm k ymm +// VPMULUDQ m512 zmm k zmm +// VPMULUDQ m512 zmm zmm +// VPMULUDQ zmm zmm k zmm +// VPMULUDQ zmm zmm zmm +// Construct and append a VPMULUDQ instruction to the active function. // Operates on the global context. -func PSRLL(imx, x operand.Op) { ctx.PSRLL(imx, x) } +func VPMULUDQ(ops ...operand.Op) { ctx.VPMULUDQ(ops...) } -// PSRLO: Shift Packed Double Quadword Right Logical. +// VPMULUDQ_BCST: Multiply Packed Unsigned Doubleword Integers (Broadcast). // // Forms: // -// PSRLO imm8 xmm -// Construct and append a PSRLO instruction to the active function. -func (c *Context) PSRLO(i, x operand.Op) { - if inst, err := x86.PSRLO(i, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMULUDQ.BCST m64 xmm k xmm +// VPMULUDQ.BCST m64 xmm xmm +// VPMULUDQ.BCST m64 ymm k ymm +// VPMULUDQ.BCST m64 ymm ymm +// VPMULUDQ.BCST m64 zmm k zmm +// VPMULUDQ.BCST m64 zmm zmm +// Construct and append a VPMULUDQ.BCST instruction to the active function. +func (c *Context) VPMULUDQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPMULUDQ_BCST(ops...)) } -// PSRLO: Shift Packed Double Quadword Right Logical. +// VPMULUDQ_BCST: Multiply Packed Unsigned Doubleword Integers (Broadcast). // // Forms: // -// PSRLO imm8 xmm -// Construct and append a PSRLO instruction to the active function. +// VPMULUDQ.BCST m64 xmm k xmm +// VPMULUDQ.BCST m64 xmm xmm +// VPMULUDQ.BCST m64 ymm k ymm +// VPMULUDQ.BCST m64 ymm ymm +// VPMULUDQ.BCST m64 zmm k zmm +// VPMULUDQ.BCST m64 zmm zmm +// Construct and append a VPMULUDQ.BCST instruction to the active function. // Operates on the global context. -func PSRLO(i, x operand.Op) { ctx.PSRLO(i, x) } +func VPMULUDQ_BCST(ops ...operand.Op) { ctx.VPMULUDQ_BCST(ops...) } -// PSRLQ: Shift Packed Quadword Data Right Logical. +// VPMULUDQ_BCST_Z: Multiply Packed Unsigned Doubleword Integers (Broadcast, Zeroing Masking). // // Forms: // -// PSRLQ imm8 xmm -// PSRLQ xmm xmm -// PSRLQ m128 xmm -// Construct and append a PSRLQ instruction to the active function. -func (c *Context) PSRLQ(imx, x operand.Op) { - if inst, err := x86.PSRLQ(imx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMULUDQ.BCST.Z m64 xmm k xmm +// VPMULUDQ.BCST.Z m64 ymm k ymm +// VPMULUDQ.BCST.Z m64 zmm k zmm +// Construct and append a VPMULUDQ.BCST.Z instruction to the active function. +func (c *Context) VPMULUDQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMULUDQ_BCST_Z(m, xyz, k, xyz1)) } -// PSRLQ: Shift Packed Quadword Data Right Logical. +// VPMULUDQ_BCST_Z: Multiply Packed Unsigned Doubleword Integers (Broadcast, Zeroing Masking). // // Forms: // -// PSRLQ imm8 xmm -// PSRLQ xmm xmm -// PSRLQ m128 xmm -// Construct and append a PSRLQ instruction to the active function. +// VPMULUDQ.BCST.Z m64 xmm k xmm +// VPMULUDQ.BCST.Z m64 ymm k ymm +// VPMULUDQ.BCST.Z m64 zmm k zmm +// Construct and append a VPMULUDQ.BCST.Z instruction to the active function. // Operates on the global context. -func PSRLQ(imx, x operand.Op) { ctx.PSRLQ(imx, x) } +func VPMULUDQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPMULUDQ_BCST_Z(m, xyz, k, xyz1) } -// PSRLW: Shift Packed Word Data Right Logical. +// VPMULUDQ_Z: Multiply Packed Unsigned Doubleword Integers (Zeroing Masking). // // Forms: // -// PSRLW imm8 xmm -// PSRLW xmm xmm -// PSRLW m128 xmm -// Construct and append a PSRLW instruction to the active function. -func (c *Context) PSRLW(imx, x operand.Op) { - if inst, err := x86.PSRLW(imx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPMULUDQ.Z m128 xmm k xmm +// VPMULUDQ.Z m256 ymm k ymm +// VPMULUDQ.Z xmm xmm k xmm +// VPMULUDQ.Z ymm ymm k ymm +// VPMULUDQ.Z m512 zmm k zmm +// VPMULUDQ.Z zmm zmm k zmm +// Construct and append a VPMULUDQ.Z instruction to the active function. +func (c *Context) VPMULUDQ_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPMULUDQ_Z(mxyz, xyz, k, xyz1)) } -// PSRLW: Shift Packed Word Data Right Logical. +// VPMULUDQ_Z: Multiply Packed Unsigned Doubleword Integers (Zeroing Masking). // // Forms: // -// PSRLW imm8 xmm -// PSRLW xmm xmm -// PSRLW m128 xmm -// Construct and append a PSRLW instruction to the active function. +// VPMULUDQ.Z m128 xmm k xmm +// VPMULUDQ.Z m256 ymm k ymm +// VPMULUDQ.Z xmm xmm k xmm +// VPMULUDQ.Z ymm ymm k ymm +// VPMULUDQ.Z m512 zmm k zmm +// VPMULUDQ.Z zmm zmm k zmm +// Construct and append a VPMULUDQ.Z instruction to the active function. // Operates on the global context. -func PSRLW(imx, x operand.Op) { ctx.PSRLW(imx, x) } +func VPMULUDQ_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPMULUDQ_Z(mxyz, xyz, k, xyz1) } -// PSUBB: Subtract Packed Byte Integers. +// VPOPCNTD: Packed Population Count for Doubleword Integers. // // Forms: // -// PSUBB xmm xmm -// PSUBB m128 xmm -// Construct and append a PSUBB instruction to the active function. -func (c *Context) PSUBB(mx, x operand.Op) { - if inst, err := x86.PSUBB(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPOPCNTD m512 k zmm +// VPOPCNTD m512 zmm +// VPOPCNTD zmm k zmm +// VPOPCNTD zmm zmm +// Construct and append a VPOPCNTD instruction to the active function. +func (c *Context) VPOPCNTD(ops ...operand.Op) { + c.addinstruction(x86.VPOPCNTD(ops...)) } -// PSUBB: Subtract Packed Byte Integers. +// VPOPCNTD: Packed Population Count for Doubleword Integers. // // Forms: // -// PSUBB xmm xmm -// PSUBB m128 xmm -// Construct and append a PSUBB instruction to the active function. +// VPOPCNTD m512 k zmm +// VPOPCNTD m512 zmm +// VPOPCNTD zmm k zmm +// VPOPCNTD zmm zmm +// Construct and append a VPOPCNTD instruction to the active function. // Operates on the global context. -func PSUBB(mx, x operand.Op) { ctx.PSUBB(mx, x) } +func VPOPCNTD(ops ...operand.Op) { ctx.VPOPCNTD(ops...) } -// PSUBL: Subtract Packed Doubleword Integers. +// VPOPCNTD_BCST: Packed Population Count for Doubleword Integers (Broadcast). // // Forms: // -// PSUBL xmm xmm -// PSUBL m128 xmm -// Construct and append a PSUBL instruction to the active function. -func (c *Context) PSUBL(mx, x operand.Op) { - if inst, err := x86.PSUBL(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPOPCNTD.BCST m32 k zmm +// VPOPCNTD.BCST m32 zmm +// Construct and append a VPOPCNTD.BCST instruction to the active function. +func (c *Context) VPOPCNTD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPOPCNTD_BCST(ops...)) } -// PSUBL: Subtract Packed Doubleword Integers. +// VPOPCNTD_BCST: Packed Population Count for Doubleword Integers (Broadcast). // // Forms: // -// PSUBL xmm xmm -// PSUBL m128 xmm -// Construct and append a PSUBL instruction to the active function. +// VPOPCNTD.BCST m32 k zmm +// VPOPCNTD.BCST m32 zmm +// Construct and append a VPOPCNTD.BCST instruction to the active function. // Operates on the global context. -func PSUBL(mx, x operand.Op) { ctx.PSUBL(mx, x) } +func VPOPCNTD_BCST(ops ...operand.Op) { ctx.VPOPCNTD_BCST(ops...) } -// PSUBQ: Subtract Packed Quadword Integers. +// VPOPCNTD_BCST_Z: Packed Population Count for Doubleword Integers (Broadcast, Zeroing Masking). // // Forms: // -// PSUBQ xmm xmm -// PSUBQ m128 xmm -// Construct and append a PSUBQ instruction to the active function. -func (c *Context) PSUBQ(mx, x operand.Op) { - if inst, err := x86.PSUBQ(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPOPCNTD.BCST.Z m32 k zmm +// Construct and append a VPOPCNTD.BCST.Z instruction to the active function. +func (c *Context) VPOPCNTD_BCST_Z(m, k, z operand.Op) { + c.addinstruction(x86.VPOPCNTD_BCST_Z(m, k, z)) } -// PSUBQ: Subtract Packed Quadword Integers. +// VPOPCNTD_BCST_Z: Packed Population Count for Doubleword Integers (Broadcast, Zeroing Masking). // // Forms: // -// PSUBQ xmm xmm -// PSUBQ m128 xmm -// Construct and append a PSUBQ instruction to the active function. +// VPOPCNTD.BCST.Z m32 k zmm +// Construct and append a VPOPCNTD.BCST.Z instruction to the active function. // Operates on the global context. -func PSUBQ(mx, x operand.Op) { ctx.PSUBQ(mx, x) } +func VPOPCNTD_BCST_Z(m, k, z operand.Op) { ctx.VPOPCNTD_BCST_Z(m, k, z) } -// PSUBSB: Subtract Packed Signed Byte Integers with Signed Saturation. +// VPOPCNTD_Z: Packed Population Count for Doubleword Integers (Zeroing Masking). // // Forms: // -// PSUBSB xmm xmm -// PSUBSB m128 xmm -// Construct and append a PSUBSB instruction to the active function. -func (c *Context) PSUBSB(mx, x operand.Op) { - if inst, err := x86.PSUBSB(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPOPCNTD.Z m512 k zmm +// VPOPCNTD.Z zmm k zmm +// Construct and append a VPOPCNTD.Z instruction to the active function. +func (c *Context) VPOPCNTD_Z(mz, k, z operand.Op) { + c.addinstruction(x86.VPOPCNTD_Z(mz, k, z)) } -// PSUBSB: Subtract Packed Signed Byte Integers with Signed Saturation. +// VPOPCNTD_Z: Packed Population Count for Doubleword Integers (Zeroing Masking). // // Forms: // -// PSUBSB xmm xmm -// PSUBSB m128 xmm -// Construct and append a PSUBSB instruction to the active function. +// VPOPCNTD.Z m512 k zmm +// VPOPCNTD.Z zmm k zmm +// Construct and append a VPOPCNTD.Z instruction to the active function. // Operates on the global context. -func PSUBSB(mx, x operand.Op) { ctx.PSUBSB(mx, x) } +func VPOPCNTD_Z(mz, k, z operand.Op) { ctx.VPOPCNTD_Z(mz, k, z) } -// PSUBSW: Subtract Packed Signed Word Integers with Signed Saturation. +// VPOPCNTQ: Packed Population Count for Quadword Integers. // // Forms: // -// PSUBSW xmm xmm -// PSUBSW m128 xmm -// Construct and append a PSUBSW instruction to the active function. -func (c *Context) PSUBSW(mx, x operand.Op) { - if inst, err := x86.PSUBSW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPOPCNTQ m512 k zmm +// VPOPCNTQ m512 zmm +// VPOPCNTQ zmm k zmm +// VPOPCNTQ zmm zmm +// Construct and append a VPOPCNTQ instruction to the active function. +func (c *Context) VPOPCNTQ(ops ...operand.Op) { + c.addinstruction(x86.VPOPCNTQ(ops...)) } -// PSUBSW: Subtract Packed Signed Word Integers with Signed Saturation. +// VPOPCNTQ: Packed Population Count for Quadword Integers. // // Forms: // -// PSUBSW xmm xmm -// PSUBSW m128 xmm -// Construct and append a PSUBSW instruction to the active function. +// VPOPCNTQ m512 k zmm +// VPOPCNTQ m512 zmm +// VPOPCNTQ zmm k zmm +// VPOPCNTQ zmm zmm +// Construct and append a VPOPCNTQ instruction to the active function. // Operates on the global context. -func PSUBSW(mx, x operand.Op) { ctx.PSUBSW(mx, x) } +func VPOPCNTQ(ops ...operand.Op) { ctx.VPOPCNTQ(ops...) } -// PSUBUSB: Subtract Packed Unsigned Byte Integers with Unsigned Saturation. +// VPOPCNTQ_BCST: Packed Population Count for Quadword Integers (Broadcast). // // Forms: // -// PSUBUSB xmm xmm -// PSUBUSB m128 xmm -// Construct and append a PSUBUSB instruction to the active function. -func (c *Context) PSUBUSB(mx, x operand.Op) { - if inst, err := x86.PSUBUSB(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPOPCNTQ.BCST m64 k zmm +// VPOPCNTQ.BCST m64 zmm +// Construct and append a VPOPCNTQ.BCST instruction to the active function. +func (c *Context) VPOPCNTQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPOPCNTQ_BCST(ops...)) } -// PSUBUSB: Subtract Packed Unsigned Byte Integers with Unsigned Saturation. +// VPOPCNTQ_BCST: Packed Population Count for Quadword Integers (Broadcast). // // Forms: // -// PSUBUSB xmm xmm -// PSUBUSB m128 xmm -// Construct and append a PSUBUSB instruction to the active function. +// VPOPCNTQ.BCST m64 k zmm +// VPOPCNTQ.BCST m64 zmm +// Construct and append a VPOPCNTQ.BCST instruction to the active function. // Operates on the global context. -func PSUBUSB(mx, x operand.Op) { ctx.PSUBUSB(mx, x) } +func VPOPCNTQ_BCST(ops ...operand.Op) { ctx.VPOPCNTQ_BCST(ops...) } -// PSUBUSW: Subtract Packed Unsigned Word Integers with Unsigned Saturation. +// VPOPCNTQ_BCST_Z: Packed Population Count for Quadword Integers (Broadcast, Zeroing Masking). // // Forms: // -// PSUBUSW xmm xmm -// PSUBUSW m128 xmm -// Construct and append a PSUBUSW instruction to the active function. -func (c *Context) PSUBUSW(mx, x operand.Op) { - if inst, err := x86.PSUBUSW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPOPCNTQ.BCST.Z m64 k zmm +// Construct and append a VPOPCNTQ.BCST.Z instruction to the active function. +func (c *Context) VPOPCNTQ_BCST_Z(m, k, z operand.Op) { + c.addinstruction(x86.VPOPCNTQ_BCST_Z(m, k, z)) } -// PSUBUSW: Subtract Packed Unsigned Word Integers with Unsigned Saturation. +// VPOPCNTQ_BCST_Z: Packed Population Count for Quadword Integers (Broadcast, Zeroing Masking). // // Forms: // -// PSUBUSW xmm xmm -// PSUBUSW m128 xmm -// Construct and append a PSUBUSW instruction to the active function. +// VPOPCNTQ.BCST.Z m64 k zmm +// Construct and append a VPOPCNTQ.BCST.Z instruction to the active function. // Operates on the global context. -func PSUBUSW(mx, x operand.Op) { ctx.PSUBUSW(mx, x) } +func VPOPCNTQ_BCST_Z(m, k, z operand.Op) { ctx.VPOPCNTQ_BCST_Z(m, k, z) } -// PSUBW: Subtract Packed Word Integers. +// VPOPCNTQ_Z: Packed Population Count for Quadword Integers (Zeroing Masking). // // Forms: // -// PSUBW xmm xmm -// PSUBW m128 xmm -// Construct and append a PSUBW instruction to the active function. -func (c *Context) PSUBW(mx, x operand.Op) { - if inst, err := x86.PSUBW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPOPCNTQ.Z m512 k zmm +// VPOPCNTQ.Z zmm k zmm +// Construct and append a VPOPCNTQ.Z instruction to the active function. +func (c *Context) VPOPCNTQ_Z(mz, k, z operand.Op) { + c.addinstruction(x86.VPOPCNTQ_Z(mz, k, z)) } -// PSUBW: Subtract Packed Word Integers. +// VPOPCNTQ_Z: Packed Population Count for Quadword Integers (Zeroing Masking). // // Forms: // -// PSUBW xmm xmm -// PSUBW m128 xmm -// Construct and append a PSUBW instruction to the active function. +// VPOPCNTQ.Z m512 k zmm +// VPOPCNTQ.Z zmm k zmm +// Construct and append a VPOPCNTQ.Z instruction to the active function. // Operates on the global context. -func PSUBW(mx, x operand.Op) { ctx.PSUBW(mx, x) } +func VPOPCNTQ_Z(mz, k, z operand.Op) { ctx.VPOPCNTQ_Z(mz, k, z) } -// PTEST: Packed Logical Compare. +// VPOR: Packed Bitwise Logical OR. // // Forms: // -// PTEST xmm xmm -// PTEST m128 xmm -// Construct and append a PTEST instruction to the active function. -func (c *Context) PTEST(mx, x operand.Op) { - if inst, err := x86.PTEST(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPOR m256 ymm ymm +// VPOR ymm ymm ymm +// VPOR m128 xmm xmm +// VPOR xmm xmm xmm +// Construct and append a VPOR instruction to the active function. +func (c *Context) VPOR(mxy, xy, xy1 operand.Op) { + c.addinstruction(x86.VPOR(mxy, xy, xy1)) } -// PTEST: Packed Logical Compare. +// VPOR: Packed Bitwise Logical OR. // // Forms: // -// PTEST xmm xmm -// PTEST m128 xmm -// Construct and append a PTEST instruction to the active function. +// VPOR m256 ymm ymm +// VPOR ymm ymm ymm +// VPOR m128 xmm xmm +// VPOR xmm xmm xmm +// Construct and append a VPOR instruction to the active function. // Operates on the global context. -func PTEST(mx, x operand.Op) { ctx.PTEST(mx, x) } +func VPOR(mxy, xy, xy1 operand.Op) { ctx.VPOR(mxy, xy, xy1) } -// PUNPCKHBW: Unpack and Interleave High-Order Bytes into Words. +// VPORD: Bitwise Logical OR of Packed Doubleword Integers. // // Forms: // -// PUNPCKHBW xmm xmm -// PUNPCKHBW m128 xmm -// Construct and append a PUNPCKHBW instruction to the active function. -func (c *Context) PUNPCKHBW(mx, x operand.Op) { - if inst, err := x86.PUNPCKHBW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPORD m128 xmm k xmm +// VPORD m128 xmm xmm +// VPORD m256 ymm k ymm +// VPORD m256 ymm ymm +// VPORD xmm xmm k xmm +// VPORD xmm xmm xmm +// VPORD ymm ymm k ymm +// VPORD ymm ymm ymm +// VPORD m512 zmm k zmm +// VPORD m512 zmm zmm +// VPORD zmm zmm k zmm +// VPORD zmm zmm zmm +// Construct and append a VPORD instruction to the active function. +func (c *Context) VPORD(ops ...operand.Op) { + c.addinstruction(x86.VPORD(ops...)) } -// PUNPCKHBW: Unpack and Interleave High-Order Bytes into Words. +// VPORD: Bitwise Logical OR of Packed Doubleword Integers. // // Forms: // -// PUNPCKHBW xmm xmm -// PUNPCKHBW m128 xmm -// Construct and append a PUNPCKHBW instruction to the active function. +// VPORD m128 xmm k xmm +// VPORD m128 xmm xmm +// VPORD m256 ymm k ymm +// VPORD m256 ymm ymm +// VPORD xmm xmm k xmm +// VPORD xmm xmm xmm +// VPORD ymm ymm k ymm +// VPORD ymm ymm ymm +// VPORD m512 zmm k zmm +// VPORD m512 zmm zmm +// VPORD zmm zmm k zmm +// VPORD zmm zmm zmm +// Construct and append a VPORD instruction to the active function. // Operates on the global context. -func PUNPCKHBW(mx, x operand.Op) { ctx.PUNPCKHBW(mx, x) } +func VPORD(ops ...operand.Op) { ctx.VPORD(ops...) } -// PUNPCKHLQ: Unpack and Interleave High-Order Doublewords into Quadwords. +// VPORD_BCST: Bitwise Logical OR of Packed Doubleword Integers (Broadcast). // // Forms: // -// PUNPCKHLQ xmm xmm -// PUNPCKHLQ m128 xmm -// Construct and append a PUNPCKHLQ instruction to the active function. -func (c *Context) PUNPCKHLQ(mx, x operand.Op) { - if inst, err := x86.PUNPCKHLQ(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPORD.BCST m32 xmm k xmm +// VPORD.BCST m32 xmm xmm +// VPORD.BCST m32 ymm k ymm +// VPORD.BCST m32 ymm ymm +// VPORD.BCST m32 zmm k zmm +// VPORD.BCST m32 zmm zmm +// Construct and append a VPORD.BCST instruction to the active function. +func (c *Context) VPORD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPORD_BCST(ops...)) } -// PUNPCKHLQ: Unpack and Interleave High-Order Doublewords into Quadwords. +// VPORD_BCST: Bitwise Logical OR of Packed Doubleword Integers (Broadcast). // // Forms: // -// PUNPCKHLQ xmm xmm -// PUNPCKHLQ m128 xmm -// Construct and append a PUNPCKHLQ instruction to the active function. +// VPORD.BCST m32 xmm k xmm +// VPORD.BCST m32 xmm xmm +// VPORD.BCST m32 ymm k ymm +// VPORD.BCST m32 ymm ymm +// VPORD.BCST m32 zmm k zmm +// VPORD.BCST m32 zmm zmm +// Construct and append a VPORD.BCST instruction to the active function. // Operates on the global context. -func PUNPCKHLQ(mx, x operand.Op) { ctx.PUNPCKHLQ(mx, x) } +func VPORD_BCST(ops ...operand.Op) { ctx.VPORD_BCST(ops...) } -// PUNPCKHQDQ: Unpack and Interleave High-Order Quadwords into Double Quadwords. +// VPORD_BCST_Z: Bitwise Logical OR of Packed Doubleword Integers (Broadcast, Zeroing Masking). // // Forms: // -// PUNPCKHQDQ xmm xmm -// PUNPCKHQDQ m128 xmm -// Construct and append a PUNPCKHQDQ instruction to the active function. -func (c *Context) PUNPCKHQDQ(mx, x operand.Op) { - if inst, err := x86.PUNPCKHQDQ(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPORD.BCST.Z m32 xmm k xmm +// VPORD.BCST.Z m32 ymm k ymm +// VPORD.BCST.Z m32 zmm k zmm +// Construct and append a VPORD.BCST.Z instruction to the active function. +func (c *Context) VPORD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPORD_BCST_Z(m, xyz, k, xyz1)) } -// PUNPCKHQDQ: Unpack and Interleave High-Order Quadwords into Double Quadwords. +// VPORD_BCST_Z: Bitwise Logical OR of Packed Doubleword Integers (Broadcast, Zeroing Masking). // // Forms: // -// PUNPCKHQDQ xmm xmm -// PUNPCKHQDQ m128 xmm -// Construct and append a PUNPCKHQDQ instruction to the active function. +// VPORD.BCST.Z m32 xmm k xmm +// VPORD.BCST.Z m32 ymm k ymm +// VPORD.BCST.Z m32 zmm k zmm +// Construct and append a VPORD.BCST.Z instruction to the active function. // Operates on the global context. -func PUNPCKHQDQ(mx, x operand.Op) { ctx.PUNPCKHQDQ(mx, x) } +func VPORD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPORD_BCST_Z(m, xyz, k, xyz1) } -// PUNPCKHWL: Unpack and Interleave High-Order Words into Doublewords. +// VPORD_Z: Bitwise Logical OR of Packed Doubleword Integers (Zeroing Masking). // // Forms: // -// PUNPCKHWL xmm xmm -// PUNPCKHWL m128 xmm -// Construct and append a PUNPCKHWL instruction to the active function. -func (c *Context) PUNPCKHWL(mx, x operand.Op) { - if inst, err := x86.PUNPCKHWL(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPORD.Z m128 xmm k xmm +// VPORD.Z m256 ymm k ymm +// VPORD.Z xmm xmm k xmm +// VPORD.Z ymm ymm k ymm +// VPORD.Z m512 zmm k zmm +// VPORD.Z zmm zmm k zmm +// Construct and append a VPORD.Z instruction to the active function. +func (c *Context) VPORD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPORD_Z(mxyz, xyz, k, xyz1)) } -// PUNPCKHWL: Unpack and Interleave High-Order Words into Doublewords. +// VPORD_Z: Bitwise Logical OR of Packed Doubleword Integers (Zeroing Masking). // // Forms: // -// PUNPCKHWL xmm xmm -// PUNPCKHWL m128 xmm -// Construct and append a PUNPCKHWL instruction to the active function. +// VPORD.Z m128 xmm k xmm +// VPORD.Z m256 ymm k ymm +// VPORD.Z xmm xmm k xmm +// VPORD.Z ymm ymm k ymm +// VPORD.Z m512 zmm k zmm +// VPORD.Z zmm zmm k zmm +// Construct and append a VPORD.Z instruction to the active function. // Operates on the global context. -func PUNPCKHWL(mx, x operand.Op) { ctx.PUNPCKHWL(mx, x) } +func VPORD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPORD_Z(mxyz, xyz, k, xyz1) } -// PUNPCKLBW: Unpack and Interleave Low-Order Bytes into Words. +// VPORQ: Bitwise Logical OR of Packed Quadword Integers. // // Forms: // -// PUNPCKLBW xmm xmm -// PUNPCKLBW m128 xmm -// Construct and append a PUNPCKLBW instruction to the active function. -func (c *Context) PUNPCKLBW(mx, x operand.Op) { - if inst, err := x86.PUNPCKLBW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPORQ m128 xmm k xmm +// VPORQ m128 xmm xmm +// VPORQ m256 ymm k ymm +// VPORQ m256 ymm ymm +// VPORQ xmm xmm k xmm +// VPORQ xmm xmm xmm +// VPORQ ymm ymm k ymm +// VPORQ ymm ymm ymm +// VPORQ m512 zmm k zmm +// VPORQ m512 zmm zmm +// VPORQ zmm zmm k zmm +// VPORQ zmm zmm zmm +// Construct and append a VPORQ instruction to the active function. +func (c *Context) VPORQ(ops ...operand.Op) { + c.addinstruction(x86.VPORQ(ops...)) } -// PUNPCKLBW: Unpack and Interleave Low-Order Bytes into Words. +// VPORQ: Bitwise Logical OR of Packed Quadword Integers. // // Forms: // -// PUNPCKLBW xmm xmm -// PUNPCKLBW m128 xmm -// Construct and append a PUNPCKLBW instruction to the active function. +// VPORQ m128 xmm k xmm +// VPORQ m128 xmm xmm +// VPORQ m256 ymm k ymm +// VPORQ m256 ymm ymm +// VPORQ xmm xmm k xmm +// VPORQ xmm xmm xmm +// VPORQ ymm ymm k ymm +// VPORQ ymm ymm ymm +// VPORQ m512 zmm k zmm +// VPORQ m512 zmm zmm +// VPORQ zmm zmm k zmm +// VPORQ zmm zmm zmm +// Construct and append a VPORQ instruction to the active function. // Operates on the global context. -func PUNPCKLBW(mx, x operand.Op) { ctx.PUNPCKLBW(mx, x) } +func VPORQ(ops ...operand.Op) { ctx.VPORQ(ops...) } -// PUNPCKLLQ: Unpack and Interleave Low-Order Doublewords into Quadwords. +// VPORQ_BCST: Bitwise Logical OR of Packed Quadword Integers (Broadcast). // // Forms: // -// PUNPCKLLQ xmm xmm -// PUNPCKLLQ m128 xmm -// Construct and append a PUNPCKLLQ instruction to the active function. -func (c *Context) PUNPCKLLQ(mx, x operand.Op) { - if inst, err := x86.PUNPCKLLQ(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPORQ.BCST m64 xmm k xmm +// VPORQ.BCST m64 xmm xmm +// VPORQ.BCST m64 ymm k ymm +// VPORQ.BCST m64 ymm ymm +// VPORQ.BCST m64 zmm k zmm +// VPORQ.BCST m64 zmm zmm +// Construct and append a VPORQ.BCST instruction to the active function. +func (c *Context) VPORQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPORQ_BCST(ops...)) } -// PUNPCKLLQ: Unpack and Interleave Low-Order Doublewords into Quadwords. +// VPORQ_BCST: Bitwise Logical OR of Packed Quadword Integers (Broadcast). // // Forms: // -// PUNPCKLLQ xmm xmm -// PUNPCKLLQ m128 xmm -// Construct and append a PUNPCKLLQ instruction to the active function. +// VPORQ.BCST m64 xmm k xmm +// VPORQ.BCST m64 xmm xmm +// VPORQ.BCST m64 ymm k ymm +// VPORQ.BCST m64 ymm ymm +// VPORQ.BCST m64 zmm k zmm +// VPORQ.BCST m64 zmm zmm +// Construct and append a VPORQ.BCST instruction to the active function. // Operates on the global context. -func PUNPCKLLQ(mx, x operand.Op) { ctx.PUNPCKLLQ(mx, x) } +func VPORQ_BCST(ops ...operand.Op) { ctx.VPORQ_BCST(ops...) } -// PUNPCKLQDQ: Unpack and Interleave Low-Order Quadwords into Double Quadwords. +// VPORQ_BCST_Z: Bitwise Logical OR of Packed Quadword Integers (Broadcast, Zeroing Masking). // // Forms: // -// PUNPCKLQDQ xmm xmm -// PUNPCKLQDQ m128 xmm -// Construct and append a PUNPCKLQDQ instruction to the active function. -func (c *Context) PUNPCKLQDQ(mx, x operand.Op) { - if inst, err := x86.PUNPCKLQDQ(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPORQ.BCST.Z m64 xmm k xmm +// VPORQ.BCST.Z m64 ymm k ymm +// VPORQ.BCST.Z m64 zmm k zmm +// Construct and append a VPORQ.BCST.Z instruction to the active function. +func (c *Context) VPORQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPORQ_BCST_Z(m, xyz, k, xyz1)) } -// PUNPCKLQDQ: Unpack and Interleave Low-Order Quadwords into Double Quadwords. +// VPORQ_BCST_Z: Bitwise Logical OR of Packed Quadword Integers (Broadcast, Zeroing Masking). // // Forms: // -// PUNPCKLQDQ xmm xmm -// PUNPCKLQDQ m128 xmm -// Construct and append a PUNPCKLQDQ instruction to the active function. +// VPORQ.BCST.Z m64 xmm k xmm +// VPORQ.BCST.Z m64 ymm k ymm +// VPORQ.BCST.Z m64 zmm k zmm +// Construct and append a VPORQ.BCST.Z instruction to the active function. // Operates on the global context. -func PUNPCKLQDQ(mx, x operand.Op) { ctx.PUNPCKLQDQ(mx, x) } +func VPORQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPORQ_BCST_Z(m, xyz, k, xyz1) } -// PUNPCKLWL: Unpack and Interleave Low-Order Words into Doublewords. +// VPORQ_Z: Bitwise Logical OR of Packed Quadword Integers (Zeroing Masking). // // Forms: // -// PUNPCKLWL xmm xmm -// PUNPCKLWL m128 xmm -// Construct and append a PUNPCKLWL instruction to the active function. -func (c *Context) PUNPCKLWL(mx, x operand.Op) { - if inst, err := x86.PUNPCKLWL(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPORQ.Z m128 xmm k xmm +// VPORQ.Z m256 ymm k ymm +// VPORQ.Z xmm xmm k xmm +// VPORQ.Z ymm ymm k ymm +// VPORQ.Z m512 zmm k zmm +// VPORQ.Z zmm zmm k zmm +// Construct and append a VPORQ.Z instruction to the active function. +func (c *Context) VPORQ_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPORQ_Z(mxyz, xyz, k, xyz1)) } -// PUNPCKLWL: Unpack and Interleave Low-Order Words into Doublewords. +// VPORQ_Z: Bitwise Logical OR of Packed Quadword Integers (Zeroing Masking). // // Forms: // -// PUNPCKLWL xmm xmm -// PUNPCKLWL m128 xmm -// Construct and append a PUNPCKLWL instruction to the active function. +// VPORQ.Z m128 xmm k xmm +// VPORQ.Z m256 ymm k ymm +// VPORQ.Z xmm xmm k xmm +// VPORQ.Z ymm ymm k ymm +// VPORQ.Z m512 zmm k zmm +// VPORQ.Z zmm zmm k zmm +// Construct and append a VPORQ.Z instruction to the active function. // Operates on the global context. -func PUNPCKLWL(mx, x operand.Op) { ctx.PUNPCKLWL(mx, x) } +func VPORQ_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPORQ_Z(mxyz, xyz, k, xyz1) } -// PUSHQ: Push Value Onto the Stack. +// VPROLD: Rotate Packed Doubleword Left. // // Forms: // -// PUSHQ imm8 -// PUSHQ imm32 -// PUSHQ r64 -// PUSHQ m64 -// Construct and append a PUSHQ instruction to the active function. -func (c *Context) PUSHQ(imr operand.Op) { - if inst, err := x86.PUSHQ(imr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPROLD imm8 m128 k xmm +// VPROLD imm8 m128 xmm +// VPROLD imm8 m256 k ymm +// VPROLD imm8 m256 ymm +// VPROLD imm8 xmm k xmm +// VPROLD imm8 xmm xmm +// VPROLD imm8 ymm k ymm +// VPROLD imm8 ymm ymm +// VPROLD imm8 m512 k zmm +// VPROLD imm8 m512 zmm +// VPROLD imm8 zmm k zmm +// VPROLD imm8 zmm zmm +// Construct and append a VPROLD instruction to the active function. +func (c *Context) VPROLD(ops ...operand.Op) { + c.addinstruction(x86.VPROLD(ops...)) } -// PUSHQ: Push Value Onto the Stack. +// VPROLD: Rotate Packed Doubleword Left. // // Forms: // -// PUSHQ imm8 -// PUSHQ imm32 -// PUSHQ r64 -// PUSHQ m64 -// Construct and append a PUSHQ instruction to the active function. +// VPROLD imm8 m128 k xmm +// VPROLD imm8 m128 xmm +// VPROLD imm8 m256 k ymm +// VPROLD imm8 m256 ymm +// VPROLD imm8 xmm k xmm +// VPROLD imm8 xmm xmm +// VPROLD imm8 ymm k ymm +// VPROLD imm8 ymm ymm +// VPROLD imm8 m512 k zmm +// VPROLD imm8 m512 zmm +// VPROLD imm8 zmm k zmm +// VPROLD imm8 zmm zmm +// Construct and append a VPROLD instruction to the active function. // Operates on the global context. -func PUSHQ(imr operand.Op) { ctx.PUSHQ(imr) } +func VPROLD(ops ...operand.Op) { ctx.VPROLD(ops...) } -// PUSHW: Push Value Onto the Stack. +// VPROLD_BCST: Rotate Packed Doubleword Left (Broadcast). // // Forms: // -// PUSHW r16 -// PUSHW m16 -// Construct and append a PUSHW instruction to the active function. -func (c *Context) PUSHW(mr operand.Op) { - if inst, err := x86.PUSHW(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPROLD.BCST imm8 m32 k xmm +// VPROLD.BCST imm8 m32 k ymm +// VPROLD.BCST imm8 m32 xmm +// VPROLD.BCST imm8 m32 ymm +// VPROLD.BCST imm8 m32 k zmm +// VPROLD.BCST imm8 m32 zmm +// Construct and append a VPROLD.BCST instruction to the active function. +func (c *Context) VPROLD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPROLD_BCST(ops...)) } -// PUSHW: Push Value Onto the Stack. +// VPROLD_BCST: Rotate Packed Doubleword Left (Broadcast). // // Forms: // -// PUSHW r16 -// PUSHW m16 -// Construct and append a PUSHW instruction to the active function. +// VPROLD.BCST imm8 m32 k xmm +// VPROLD.BCST imm8 m32 k ymm +// VPROLD.BCST imm8 m32 xmm +// VPROLD.BCST imm8 m32 ymm +// VPROLD.BCST imm8 m32 k zmm +// VPROLD.BCST imm8 m32 zmm +// Construct and append a VPROLD.BCST instruction to the active function. // Operates on the global context. -func PUSHW(mr operand.Op) { ctx.PUSHW(mr) } +func VPROLD_BCST(ops ...operand.Op) { ctx.VPROLD_BCST(ops...) } -// PXOR: Packed Bitwise Logical Exclusive OR. +// VPROLD_BCST_Z: Rotate Packed Doubleword Left (Broadcast, Zeroing Masking). // // Forms: // -// PXOR xmm xmm -// PXOR m128 xmm -// Construct and append a PXOR instruction to the active function. -func (c *Context) PXOR(mx, x operand.Op) { - if inst, err := x86.PXOR(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPROLD.BCST.Z imm8 m32 k xmm +// VPROLD.BCST.Z imm8 m32 k ymm +// VPROLD.BCST.Z imm8 m32 k zmm +// Construct and append a VPROLD.BCST.Z instruction to the active function. +func (c *Context) VPROLD_BCST_Z(i, m, k, xyz operand.Op) { + c.addinstruction(x86.VPROLD_BCST_Z(i, m, k, xyz)) } -// PXOR: Packed Bitwise Logical Exclusive OR. +// VPROLD_BCST_Z: Rotate Packed Doubleword Left (Broadcast, Zeroing Masking). // // Forms: // -// PXOR xmm xmm -// PXOR m128 xmm -// Construct and append a PXOR instruction to the active function. +// VPROLD.BCST.Z imm8 m32 k xmm +// VPROLD.BCST.Z imm8 m32 k ymm +// VPROLD.BCST.Z imm8 m32 k zmm +// Construct and append a VPROLD.BCST.Z instruction to the active function. // Operates on the global context. -func PXOR(mx, x operand.Op) { ctx.PXOR(mx, x) } +func VPROLD_BCST_Z(i, m, k, xyz operand.Op) { ctx.VPROLD_BCST_Z(i, m, k, xyz) } -// RCLB: Rotate Left through Carry Flag. +// VPROLD_Z: Rotate Packed Doubleword Left (Zeroing Masking). // // Forms: // -// RCLB 1 r8 -// RCLB imm8 r8 -// RCLB cl r8 -// RCLB 1 m8 -// RCLB imm8 m8 -// RCLB cl m8 -// Construct and append a RCLB instruction to the active function. -func (c *Context) RCLB(ci, mr operand.Op) { - if inst, err := x86.RCLB(ci, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPROLD.Z imm8 m128 k xmm +// VPROLD.Z imm8 m256 k ymm +// VPROLD.Z imm8 xmm k xmm +// VPROLD.Z imm8 ymm k ymm +// VPROLD.Z imm8 m512 k zmm +// VPROLD.Z imm8 zmm k zmm +// Construct and append a VPROLD.Z instruction to the active function. +func (c *Context) VPROLD_Z(i, mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPROLD_Z(i, mxyz, k, xyz)) } -// RCLB: Rotate Left through Carry Flag. +// VPROLD_Z: Rotate Packed Doubleword Left (Zeroing Masking). // // Forms: // -// RCLB 1 r8 -// RCLB imm8 r8 -// RCLB cl r8 -// RCLB 1 m8 -// RCLB imm8 m8 -// RCLB cl m8 -// Construct and append a RCLB instruction to the active function. +// VPROLD.Z imm8 m128 k xmm +// VPROLD.Z imm8 m256 k ymm +// VPROLD.Z imm8 xmm k xmm +// VPROLD.Z imm8 ymm k ymm +// VPROLD.Z imm8 m512 k zmm +// VPROLD.Z imm8 zmm k zmm +// Construct and append a VPROLD.Z instruction to the active function. // Operates on the global context. -func RCLB(ci, mr operand.Op) { ctx.RCLB(ci, mr) } +func VPROLD_Z(i, mxyz, k, xyz operand.Op) { ctx.VPROLD_Z(i, mxyz, k, xyz) } -// RCLL: Rotate Left through Carry Flag. +// VPROLQ: Rotate Packed Quadword Left. // // Forms: // -// RCLL 1 r32 -// RCLL imm8 r32 -// RCLL cl r32 -// RCLL 1 m32 -// RCLL imm8 m32 -// RCLL cl m32 -// Construct and append a RCLL instruction to the active function. -func (c *Context) RCLL(ci, mr operand.Op) { - if inst, err := x86.RCLL(ci, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPROLQ imm8 m128 k xmm +// VPROLQ imm8 m128 xmm +// VPROLQ imm8 m256 k ymm +// VPROLQ imm8 m256 ymm +// VPROLQ imm8 xmm k xmm +// VPROLQ imm8 xmm xmm +// VPROLQ imm8 ymm k ymm +// VPROLQ imm8 ymm ymm +// VPROLQ imm8 m512 k zmm +// VPROLQ imm8 m512 zmm +// VPROLQ imm8 zmm k zmm +// VPROLQ imm8 zmm zmm +// Construct and append a VPROLQ instruction to the active function. +func (c *Context) VPROLQ(ops ...operand.Op) { + c.addinstruction(x86.VPROLQ(ops...)) } -// RCLL: Rotate Left through Carry Flag. +// VPROLQ: Rotate Packed Quadword Left. // // Forms: // -// RCLL 1 r32 -// RCLL imm8 r32 -// RCLL cl r32 -// RCLL 1 m32 -// RCLL imm8 m32 -// RCLL cl m32 -// Construct and append a RCLL instruction to the active function. +// VPROLQ imm8 m128 k xmm +// VPROLQ imm8 m128 xmm +// VPROLQ imm8 m256 k ymm +// VPROLQ imm8 m256 ymm +// VPROLQ imm8 xmm k xmm +// VPROLQ imm8 xmm xmm +// VPROLQ imm8 ymm k ymm +// VPROLQ imm8 ymm ymm +// VPROLQ imm8 m512 k zmm +// VPROLQ imm8 m512 zmm +// VPROLQ imm8 zmm k zmm +// VPROLQ imm8 zmm zmm +// Construct and append a VPROLQ instruction to the active function. // Operates on the global context. -func RCLL(ci, mr operand.Op) { ctx.RCLL(ci, mr) } +func VPROLQ(ops ...operand.Op) { ctx.VPROLQ(ops...) } -// RCLQ: Rotate Left through Carry Flag. +// VPROLQ_BCST: Rotate Packed Quadword Left (Broadcast). // // Forms: // -// RCLQ 1 r64 -// RCLQ imm8 r64 -// RCLQ cl r64 -// RCLQ 1 m64 -// RCLQ imm8 m64 -// RCLQ cl m64 -// Construct and append a RCLQ instruction to the active function. -func (c *Context) RCLQ(ci, mr operand.Op) { - if inst, err := x86.RCLQ(ci, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPROLQ.BCST imm8 m64 k xmm +// VPROLQ.BCST imm8 m64 k ymm +// VPROLQ.BCST imm8 m64 xmm +// VPROLQ.BCST imm8 m64 ymm +// VPROLQ.BCST imm8 m64 k zmm +// VPROLQ.BCST imm8 m64 zmm +// Construct and append a VPROLQ.BCST instruction to the active function. +func (c *Context) VPROLQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPROLQ_BCST(ops...)) } -// RCLQ: Rotate Left through Carry Flag. +// VPROLQ_BCST: Rotate Packed Quadword Left (Broadcast). // // Forms: // -// RCLQ 1 r64 -// RCLQ imm8 r64 -// RCLQ cl r64 -// RCLQ 1 m64 -// RCLQ imm8 m64 -// RCLQ cl m64 -// Construct and append a RCLQ instruction to the active function. +// VPROLQ.BCST imm8 m64 k xmm +// VPROLQ.BCST imm8 m64 k ymm +// VPROLQ.BCST imm8 m64 xmm +// VPROLQ.BCST imm8 m64 ymm +// VPROLQ.BCST imm8 m64 k zmm +// VPROLQ.BCST imm8 m64 zmm +// Construct and append a VPROLQ.BCST instruction to the active function. // Operates on the global context. -func RCLQ(ci, mr operand.Op) { ctx.RCLQ(ci, mr) } +func VPROLQ_BCST(ops ...operand.Op) { ctx.VPROLQ_BCST(ops...) } -// RCLW: Rotate Left through Carry Flag. +// VPROLQ_BCST_Z: Rotate Packed Quadword Left (Broadcast, Zeroing Masking). // // Forms: // -// RCLW 1 r16 -// RCLW imm8 r16 -// RCLW cl r16 -// RCLW 1 m16 -// RCLW imm8 m16 -// RCLW cl m16 -// Construct and append a RCLW instruction to the active function. -func (c *Context) RCLW(ci, mr operand.Op) { - if inst, err := x86.RCLW(ci, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPROLQ.BCST.Z imm8 m64 k xmm +// VPROLQ.BCST.Z imm8 m64 k ymm +// VPROLQ.BCST.Z imm8 m64 k zmm +// Construct and append a VPROLQ.BCST.Z instruction to the active function. +func (c *Context) VPROLQ_BCST_Z(i, m, k, xyz operand.Op) { + c.addinstruction(x86.VPROLQ_BCST_Z(i, m, k, xyz)) } -// RCLW: Rotate Left through Carry Flag. +// VPROLQ_BCST_Z: Rotate Packed Quadword Left (Broadcast, Zeroing Masking). // // Forms: // -// RCLW 1 r16 -// RCLW imm8 r16 -// RCLW cl r16 -// RCLW 1 m16 -// RCLW imm8 m16 -// RCLW cl m16 -// Construct and append a RCLW instruction to the active function. +// VPROLQ.BCST.Z imm8 m64 k xmm +// VPROLQ.BCST.Z imm8 m64 k ymm +// VPROLQ.BCST.Z imm8 m64 k zmm +// Construct and append a VPROLQ.BCST.Z instruction to the active function. // Operates on the global context. -func RCLW(ci, mr operand.Op) { ctx.RCLW(ci, mr) } +func VPROLQ_BCST_Z(i, m, k, xyz operand.Op) { ctx.VPROLQ_BCST_Z(i, m, k, xyz) } -// RCPPS: Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values. +// VPROLQ_Z: Rotate Packed Quadword Left (Zeroing Masking). // // Forms: // -// RCPPS xmm xmm -// RCPPS m128 xmm -// Construct and append a RCPPS instruction to the active function. -func (c *Context) RCPPS(mx, x operand.Op) { - if inst, err := x86.RCPPS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPROLQ.Z imm8 m128 k xmm +// VPROLQ.Z imm8 m256 k ymm +// VPROLQ.Z imm8 xmm k xmm +// VPROLQ.Z imm8 ymm k ymm +// VPROLQ.Z imm8 m512 k zmm +// VPROLQ.Z imm8 zmm k zmm +// Construct and append a VPROLQ.Z instruction to the active function. +func (c *Context) VPROLQ_Z(i, mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPROLQ_Z(i, mxyz, k, xyz)) } -// RCPPS: Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values. +// VPROLQ_Z: Rotate Packed Quadword Left (Zeroing Masking). // // Forms: // -// RCPPS xmm xmm -// RCPPS m128 xmm -// Construct and append a RCPPS instruction to the active function. +// VPROLQ.Z imm8 m128 k xmm +// VPROLQ.Z imm8 m256 k ymm +// VPROLQ.Z imm8 xmm k xmm +// VPROLQ.Z imm8 ymm k ymm +// VPROLQ.Z imm8 m512 k zmm +// VPROLQ.Z imm8 zmm k zmm +// Construct and append a VPROLQ.Z instruction to the active function. // Operates on the global context. -func RCPPS(mx, x operand.Op) { ctx.RCPPS(mx, x) } +func VPROLQ_Z(i, mxyz, k, xyz operand.Op) { ctx.VPROLQ_Z(i, mxyz, k, xyz) } -// RCPSS: Compute Approximate Reciprocal of Scalar Single-Precision Floating-Point Values. +// VPROLVD: Variable Rotate Packed Doubleword Left. // // Forms: // -// RCPSS xmm xmm -// RCPSS m32 xmm -// Construct and append a RCPSS instruction to the active function. -func (c *Context) RCPSS(mx, x operand.Op) { - if inst, err := x86.RCPSS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPROLVD m128 xmm k xmm +// VPROLVD m128 xmm xmm +// VPROLVD m256 ymm k ymm +// VPROLVD m256 ymm ymm +// VPROLVD xmm xmm k xmm +// VPROLVD xmm xmm xmm +// VPROLVD ymm ymm k ymm +// VPROLVD ymm ymm ymm +// VPROLVD m512 zmm k zmm +// VPROLVD m512 zmm zmm +// VPROLVD zmm zmm k zmm +// VPROLVD zmm zmm zmm +// Construct and append a VPROLVD instruction to the active function. +func (c *Context) VPROLVD(ops ...operand.Op) { + c.addinstruction(x86.VPROLVD(ops...)) } -// RCPSS: Compute Approximate Reciprocal of Scalar Single-Precision Floating-Point Values. +// VPROLVD: Variable Rotate Packed Doubleword Left. // // Forms: // -// RCPSS xmm xmm -// RCPSS m32 xmm -// Construct and append a RCPSS instruction to the active function. +// VPROLVD m128 xmm k xmm +// VPROLVD m128 xmm xmm +// VPROLVD m256 ymm k ymm +// VPROLVD m256 ymm ymm +// VPROLVD xmm xmm k xmm +// VPROLVD xmm xmm xmm +// VPROLVD ymm ymm k ymm +// VPROLVD ymm ymm ymm +// VPROLVD m512 zmm k zmm +// VPROLVD m512 zmm zmm +// VPROLVD zmm zmm k zmm +// VPROLVD zmm zmm zmm +// Construct and append a VPROLVD instruction to the active function. // Operates on the global context. -func RCPSS(mx, x operand.Op) { ctx.RCPSS(mx, x) } +func VPROLVD(ops ...operand.Op) { ctx.VPROLVD(ops...) } -// RCRB: Rotate Right through Carry Flag. +// VPROLVD_BCST: Variable Rotate Packed Doubleword Left (Broadcast). // // Forms: // -// RCRB 1 r8 -// RCRB imm8 r8 -// RCRB cl r8 -// RCRB 1 m8 -// RCRB imm8 m8 -// RCRB cl m8 -// Construct and append a RCRB instruction to the active function. -func (c *Context) RCRB(ci, mr operand.Op) { - if inst, err := x86.RCRB(ci, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPROLVD.BCST m32 xmm k xmm +// VPROLVD.BCST m32 xmm xmm +// VPROLVD.BCST m32 ymm k ymm +// VPROLVD.BCST m32 ymm ymm +// VPROLVD.BCST m32 zmm k zmm +// VPROLVD.BCST m32 zmm zmm +// Construct and append a VPROLVD.BCST instruction to the active function. +func (c *Context) VPROLVD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPROLVD_BCST(ops...)) } -// RCRB: Rotate Right through Carry Flag. +// VPROLVD_BCST: Variable Rotate Packed Doubleword Left (Broadcast). // // Forms: // -// RCRB 1 r8 -// RCRB imm8 r8 -// RCRB cl r8 -// RCRB 1 m8 -// RCRB imm8 m8 -// RCRB cl m8 -// Construct and append a RCRB instruction to the active function. +// VPROLVD.BCST m32 xmm k xmm +// VPROLVD.BCST m32 xmm xmm +// VPROLVD.BCST m32 ymm k ymm +// VPROLVD.BCST m32 ymm ymm +// VPROLVD.BCST m32 zmm k zmm +// VPROLVD.BCST m32 zmm zmm +// Construct and append a VPROLVD.BCST instruction to the active function. +// Operates on the global context. +func VPROLVD_BCST(ops ...operand.Op) { ctx.VPROLVD_BCST(ops...) } + +// VPROLVD_BCST_Z: Variable Rotate Packed Doubleword Left (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPROLVD.BCST.Z m32 xmm k xmm +// VPROLVD.BCST.Z m32 ymm k ymm +// VPROLVD.BCST.Z m32 zmm k zmm +// Construct and append a VPROLVD.BCST.Z instruction to the active function. +func (c *Context) VPROLVD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPROLVD_BCST_Z(m, xyz, k, xyz1)) +} + +// VPROLVD_BCST_Z: Variable Rotate Packed Doubleword Left (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPROLVD.BCST.Z m32 xmm k xmm +// VPROLVD.BCST.Z m32 ymm k ymm +// VPROLVD.BCST.Z m32 zmm k zmm +// Construct and append a VPROLVD.BCST.Z instruction to the active function. // Operates on the global context. -func RCRB(ci, mr operand.Op) { ctx.RCRB(ci, mr) } +func VPROLVD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPROLVD_BCST_Z(m, xyz, k, xyz1) } -// RCRL: Rotate Right through Carry Flag. +// VPROLVD_Z: Variable Rotate Packed Doubleword Left (Zeroing Masking). // // Forms: // -// RCRL 1 r32 -// RCRL imm8 r32 -// RCRL cl r32 -// RCRL 1 m32 -// RCRL imm8 m32 -// RCRL cl m32 -// Construct and append a RCRL instruction to the active function. -func (c *Context) RCRL(ci, mr operand.Op) { - if inst, err := x86.RCRL(ci, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPROLVD.Z m128 xmm k xmm +// VPROLVD.Z m256 ymm k ymm +// VPROLVD.Z xmm xmm k xmm +// VPROLVD.Z ymm ymm k ymm +// VPROLVD.Z m512 zmm k zmm +// VPROLVD.Z zmm zmm k zmm +// Construct and append a VPROLVD.Z instruction to the active function. +func (c *Context) VPROLVD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPROLVD_Z(mxyz, xyz, k, xyz1)) } -// RCRL: Rotate Right through Carry Flag. +// VPROLVD_Z: Variable Rotate Packed Doubleword Left (Zeroing Masking). // // Forms: // -// RCRL 1 r32 -// RCRL imm8 r32 -// RCRL cl r32 -// RCRL 1 m32 -// RCRL imm8 m32 -// RCRL cl m32 -// Construct and append a RCRL instruction to the active function. +// VPROLVD.Z m128 xmm k xmm +// VPROLVD.Z m256 ymm k ymm +// VPROLVD.Z xmm xmm k xmm +// VPROLVD.Z ymm ymm k ymm +// VPROLVD.Z m512 zmm k zmm +// VPROLVD.Z zmm zmm k zmm +// Construct and append a VPROLVD.Z instruction to the active function. // Operates on the global context. -func RCRL(ci, mr operand.Op) { ctx.RCRL(ci, mr) } +func VPROLVD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPROLVD_Z(mxyz, xyz, k, xyz1) } -// RCRQ: Rotate Right through Carry Flag. +// VPROLVQ: Variable Rotate Packed Quadword Left. // // Forms: // -// RCRQ 1 r64 -// RCRQ imm8 r64 -// RCRQ cl r64 -// RCRQ 1 m64 -// RCRQ imm8 m64 -// RCRQ cl m64 -// Construct and append a RCRQ instruction to the active function. -func (c *Context) RCRQ(ci, mr operand.Op) { - if inst, err := x86.RCRQ(ci, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPROLVQ m128 xmm k xmm +// VPROLVQ m128 xmm xmm +// VPROLVQ m256 ymm k ymm +// VPROLVQ m256 ymm ymm +// VPROLVQ xmm xmm k xmm +// VPROLVQ xmm xmm xmm +// VPROLVQ ymm ymm k ymm +// VPROLVQ ymm ymm ymm +// VPROLVQ m512 zmm k zmm +// VPROLVQ m512 zmm zmm +// VPROLVQ zmm zmm k zmm +// VPROLVQ zmm zmm zmm +// Construct and append a VPROLVQ instruction to the active function. +func (c *Context) VPROLVQ(ops ...operand.Op) { + c.addinstruction(x86.VPROLVQ(ops...)) } -// RCRQ: Rotate Right through Carry Flag. +// VPROLVQ: Variable Rotate Packed Quadword Left. // // Forms: // -// RCRQ 1 r64 -// RCRQ imm8 r64 -// RCRQ cl r64 -// RCRQ 1 m64 -// RCRQ imm8 m64 -// RCRQ cl m64 -// Construct and append a RCRQ instruction to the active function. +// VPROLVQ m128 xmm k xmm +// VPROLVQ m128 xmm xmm +// VPROLVQ m256 ymm k ymm +// VPROLVQ m256 ymm ymm +// VPROLVQ xmm xmm k xmm +// VPROLVQ xmm xmm xmm +// VPROLVQ ymm ymm k ymm +// VPROLVQ ymm ymm ymm +// VPROLVQ m512 zmm k zmm +// VPROLVQ m512 zmm zmm +// VPROLVQ zmm zmm k zmm +// VPROLVQ zmm zmm zmm +// Construct and append a VPROLVQ instruction to the active function. // Operates on the global context. -func RCRQ(ci, mr operand.Op) { ctx.RCRQ(ci, mr) } +func VPROLVQ(ops ...operand.Op) { ctx.VPROLVQ(ops...) } -// RCRW: Rotate Right through Carry Flag. +// VPROLVQ_BCST: Variable Rotate Packed Quadword Left (Broadcast). // // Forms: // -// RCRW 1 r16 -// RCRW imm8 r16 -// RCRW cl r16 -// RCRW 1 m16 -// RCRW imm8 m16 -// RCRW cl m16 -// Construct and append a RCRW instruction to the active function. -func (c *Context) RCRW(ci, mr operand.Op) { - if inst, err := x86.RCRW(ci, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPROLVQ.BCST m64 xmm k xmm +// VPROLVQ.BCST m64 xmm xmm +// VPROLVQ.BCST m64 ymm k ymm +// VPROLVQ.BCST m64 ymm ymm +// VPROLVQ.BCST m64 zmm k zmm +// VPROLVQ.BCST m64 zmm zmm +// Construct and append a VPROLVQ.BCST instruction to the active function. +func (c *Context) VPROLVQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPROLVQ_BCST(ops...)) } -// RCRW: Rotate Right through Carry Flag. +// VPROLVQ_BCST: Variable Rotate Packed Quadword Left (Broadcast). // // Forms: // -// RCRW 1 r16 -// RCRW imm8 r16 -// RCRW cl r16 -// RCRW 1 m16 -// RCRW imm8 m16 -// RCRW cl m16 -// Construct and append a RCRW instruction to the active function. +// VPROLVQ.BCST m64 xmm k xmm +// VPROLVQ.BCST m64 xmm xmm +// VPROLVQ.BCST m64 ymm k ymm +// VPROLVQ.BCST m64 ymm ymm +// VPROLVQ.BCST m64 zmm k zmm +// VPROLVQ.BCST m64 zmm zmm +// Construct and append a VPROLVQ.BCST instruction to the active function. // Operates on the global context. -func RCRW(ci, mr operand.Op) { ctx.RCRW(ci, mr) } +func VPROLVQ_BCST(ops ...operand.Op) { ctx.VPROLVQ_BCST(ops...) } -// RDRANDL: Read Random Number. +// VPROLVQ_BCST_Z: Variable Rotate Packed Quadword Left (Broadcast, Zeroing Masking). // // Forms: // -// RDRANDL r32 -// Construct and append a RDRANDL instruction to the active function. -func (c *Context) RDRANDL(r operand.Op) { - if inst, err := x86.RDRANDL(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPROLVQ.BCST.Z m64 xmm k xmm +// VPROLVQ.BCST.Z m64 ymm k ymm +// VPROLVQ.BCST.Z m64 zmm k zmm +// Construct and append a VPROLVQ.BCST.Z instruction to the active function. +func (c *Context) VPROLVQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPROLVQ_BCST_Z(m, xyz, k, xyz1)) } -// RDRANDL: Read Random Number. +// VPROLVQ_BCST_Z: Variable Rotate Packed Quadword Left (Broadcast, Zeroing Masking). // // Forms: // -// RDRANDL r32 -// Construct and append a RDRANDL instruction to the active function. +// VPROLVQ.BCST.Z m64 xmm k xmm +// VPROLVQ.BCST.Z m64 ymm k ymm +// VPROLVQ.BCST.Z m64 zmm k zmm +// Construct and append a VPROLVQ.BCST.Z instruction to the active function. // Operates on the global context. -func RDRANDL(r operand.Op) { ctx.RDRANDL(r) } +func VPROLVQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPROLVQ_BCST_Z(m, xyz, k, xyz1) } -// RDRANDQ: Read Random Number. +// VPROLVQ_Z: Variable Rotate Packed Quadword Left (Zeroing Masking). // // Forms: // -// RDRANDQ r64 -// Construct and append a RDRANDQ instruction to the active function. -func (c *Context) RDRANDQ(r operand.Op) { - if inst, err := x86.RDRANDQ(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPROLVQ.Z m128 xmm k xmm +// VPROLVQ.Z m256 ymm k ymm +// VPROLVQ.Z xmm xmm k xmm +// VPROLVQ.Z ymm ymm k ymm +// VPROLVQ.Z m512 zmm k zmm +// VPROLVQ.Z zmm zmm k zmm +// Construct and append a VPROLVQ.Z instruction to the active function. +func (c *Context) VPROLVQ_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPROLVQ_Z(mxyz, xyz, k, xyz1)) } -// RDRANDQ: Read Random Number. +// VPROLVQ_Z: Variable Rotate Packed Quadword Left (Zeroing Masking). // // Forms: // -// RDRANDQ r64 -// Construct and append a RDRANDQ instruction to the active function. +// VPROLVQ.Z m128 xmm k xmm +// VPROLVQ.Z m256 ymm k ymm +// VPROLVQ.Z xmm xmm k xmm +// VPROLVQ.Z ymm ymm k ymm +// VPROLVQ.Z m512 zmm k zmm +// VPROLVQ.Z zmm zmm k zmm +// Construct and append a VPROLVQ.Z instruction to the active function. // Operates on the global context. -func RDRANDQ(r operand.Op) { ctx.RDRANDQ(r) } +func VPROLVQ_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPROLVQ_Z(mxyz, xyz, k, xyz1) } -// RDRANDW: Read Random Number. +// VPRORD: Rotate Packed Doubleword Right. // // Forms: // -// RDRANDW r16 -// Construct and append a RDRANDW instruction to the active function. -func (c *Context) RDRANDW(r operand.Op) { - if inst, err := x86.RDRANDW(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPRORD imm8 m128 k xmm +// VPRORD imm8 m128 xmm +// VPRORD imm8 m256 k ymm +// VPRORD imm8 m256 ymm +// VPRORD imm8 xmm k xmm +// VPRORD imm8 xmm xmm +// VPRORD imm8 ymm k ymm +// VPRORD imm8 ymm ymm +// VPRORD imm8 m512 k zmm +// VPRORD imm8 m512 zmm +// VPRORD imm8 zmm k zmm +// VPRORD imm8 zmm zmm +// Construct and append a VPRORD instruction to the active function. +func (c *Context) VPRORD(ops ...operand.Op) { + c.addinstruction(x86.VPRORD(ops...)) } -// RDRANDW: Read Random Number. +// VPRORD: Rotate Packed Doubleword Right. // // Forms: // -// RDRANDW r16 -// Construct and append a RDRANDW instruction to the active function. +// VPRORD imm8 m128 k xmm +// VPRORD imm8 m128 xmm +// VPRORD imm8 m256 k ymm +// VPRORD imm8 m256 ymm +// VPRORD imm8 xmm k xmm +// VPRORD imm8 xmm xmm +// VPRORD imm8 ymm k ymm +// VPRORD imm8 ymm ymm +// VPRORD imm8 m512 k zmm +// VPRORD imm8 m512 zmm +// VPRORD imm8 zmm k zmm +// VPRORD imm8 zmm zmm +// Construct and append a VPRORD instruction to the active function. // Operates on the global context. -func RDRANDW(r operand.Op) { ctx.RDRANDW(r) } +func VPRORD(ops ...operand.Op) { ctx.VPRORD(ops...) } -// RDSEEDL: Read Random SEED. +// VPRORD_BCST: Rotate Packed Doubleword Right (Broadcast). // // Forms: // -// RDSEEDL r32 -// Construct and append a RDSEEDL instruction to the active function. -func (c *Context) RDSEEDL(r operand.Op) { - if inst, err := x86.RDSEEDL(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPRORD.BCST imm8 m32 k xmm +// VPRORD.BCST imm8 m32 k ymm +// VPRORD.BCST imm8 m32 xmm +// VPRORD.BCST imm8 m32 ymm +// VPRORD.BCST imm8 m32 k zmm +// VPRORD.BCST imm8 m32 zmm +// Construct and append a VPRORD.BCST instruction to the active function. +func (c *Context) VPRORD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPRORD_BCST(ops...)) } -// RDSEEDL: Read Random SEED. +// VPRORD_BCST: Rotate Packed Doubleword Right (Broadcast). // // Forms: // -// RDSEEDL r32 -// Construct and append a RDSEEDL instruction to the active function. +// VPRORD.BCST imm8 m32 k xmm +// VPRORD.BCST imm8 m32 k ymm +// VPRORD.BCST imm8 m32 xmm +// VPRORD.BCST imm8 m32 ymm +// VPRORD.BCST imm8 m32 k zmm +// VPRORD.BCST imm8 m32 zmm +// Construct and append a VPRORD.BCST instruction to the active function. // Operates on the global context. -func RDSEEDL(r operand.Op) { ctx.RDSEEDL(r) } +func VPRORD_BCST(ops ...operand.Op) { ctx.VPRORD_BCST(ops...) } -// RDSEEDQ: Read Random SEED. +// VPRORD_BCST_Z: Rotate Packed Doubleword Right (Broadcast, Zeroing Masking). // // Forms: // -// RDSEEDQ r64 -// Construct and append a RDSEEDQ instruction to the active function. -func (c *Context) RDSEEDQ(r operand.Op) { - if inst, err := x86.RDSEEDQ(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPRORD.BCST.Z imm8 m32 k xmm +// VPRORD.BCST.Z imm8 m32 k ymm +// VPRORD.BCST.Z imm8 m32 k zmm +// Construct and append a VPRORD.BCST.Z instruction to the active function. +func (c *Context) VPRORD_BCST_Z(i, m, k, xyz operand.Op) { + c.addinstruction(x86.VPRORD_BCST_Z(i, m, k, xyz)) } -// RDSEEDQ: Read Random SEED. +// VPRORD_BCST_Z: Rotate Packed Doubleword Right (Broadcast, Zeroing Masking). // // Forms: // -// RDSEEDQ r64 -// Construct and append a RDSEEDQ instruction to the active function. +// VPRORD.BCST.Z imm8 m32 k xmm +// VPRORD.BCST.Z imm8 m32 k ymm +// VPRORD.BCST.Z imm8 m32 k zmm +// Construct and append a VPRORD.BCST.Z instruction to the active function. // Operates on the global context. -func RDSEEDQ(r operand.Op) { ctx.RDSEEDQ(r) } +func VPRORD_BCST_Z(i, m, k, xyz operand.Op) { ctx.VPRORD_BCST_Z(i, m, k, xyz) } -// RDSEEDW: Read Random SEED. +// VPRORD_Z: Rotate Packed Doubleword Right (Zeroing Masking). // // Forms: // -// RDSEEDW r16 -// Construct and append a RDSEEDW instruction to the active function. -func (c *Context) RDSEEDW(r operand.Op) { - if inst, err := x86.RDSEEDW(r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPRORD.Z imm8 m128 k xmm +// VPRORD.Z imm8 m256 k ymm +// VPRORD.Z imm8 xmm k xmm +// VPRORD.Z imm8 ymm k ymm +// VPRORD.Z imm8 m512 k zmm +// VPRORD.Z imm8 zmm k zmm +// Construct and append a VPRORD.Z instruction to the active function. +func (c *Context) VPRORD_Z(i, mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPRORD_Z(i, mxyz, k, xyz)) } -// RDSEEDW: Read Random SEED. +// VPRORD_Z: Rotate Packed Doubleword Right (Zeroing Masking). // // Forms: // -// RDSEEDW r16 -// Construct and append a RDSEEDW instruction to the active function. +// VPRORD.Z imm8 m128 k xmm +// VPRORD.Z imm8 m256 k ymm +// VPRORD.Z imm8 xmm k xmm +// VPRORD.Z imm8 ymm k ymm +// VPRORD.Z imm8 m512 k zmm +// VPRORD.Z imm8 zmm k zmm +// Construct and append a VPRORD.Z instruction to the active function. // Operates on the global context. -func RDSEEDW(r operand.Op) { ctx.RDSEEDW(r) } +func VPRORD_Z(i, mxyz, k, xyz operand.Op) { ctx.VPRORD_Z(i, mxyz, k, xyz) } -// RDTSC: Read Time-Stamp Counter. +// VPRORQ: Rotate Packed Quadword Right. // // Forms: // -// RDTSC -// Construct and append a RDTSC instruction to the active function. -func (c *Context) RDTSC() { - if inst, err := x86.RDTSC(); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPRORQ imm8 m128 k xmm +// VPRORQ imm8 m128 xmm +// VPRORQ imm8 m256 k ymm +// VPRORQ imm8 m256 ymm +// VPRORQ imm8 xmm k xmm +// VPRORQ imm8 xmm xmm +// VPRORQ imm8 ymm k ymm +// VPRORQ imm8 ymm ymm +// VPRORQ imm8 m512 k zmm +// VPRORQ imm8 m512 zmm +// VPRORQ imm8 zmm k zmm +// VPRORQ imm8 zmm zmm +// Construct and append a VPRORQ instruction to the active function. +func (c *Context) VPRORQ(ops ...operand.Op) { + c.addinstruction(x86.VPRORQ(ops...)) } -// RDTSC: Read Time-Stamp Counter. +// VPRORQ: Rotate Packed Quadword Right. // // Forms: // -// RDTSC -// Construct and append a RDTSC instruction to the active function. +// VPRORQ imm8 m128 k xmm +// VPRORQ imm8 m128 xmm +// VPRORQ imm8 m256 k ymm +// VPRORQ imm8 m256 ymm +// VPRORQ imm8 xmm k xmm +// VPRORQ imm8 xmm xmm +// VPRORQ imm8 ymm k ymm +// VPRORQ imm8 ymm ymm +// VPRORQ imm8 m512 k zmm +// VPRORQ imm8 m512 zmm +// VPRORQ imm8 zmm k zmm +// VPRORQ imm8 zmm zmm +// Construct and append a VPRORQ instruction to the active function. // Operates on the global context. -func RDTSC() { ctx.RDTSC() } +func VPRORQ(ops ...operand.Op) { ctx.VPRORQ(ops...) } -// RDTSCP: Read Time-Stamp Counter and Processor ID. +// VPRORQ_BCST: Rotate Packed Quadword Right (Broadcast). // // Forms: // -// RDTSCP -// Construct and append a RDTSCP instruction to the active function. -func (c *Context) RDTSCP() { - if inst, err := x86.RDTSCP(); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPRORQ.BCST imm8 m64 k xmm +// VPRORQ.BCST imm8 m64 k ymm +// VPRORQ.BCST imm8 m64 xmm +// VPRORQ.BCST imm8 m64 ymm +// VPRORQ.BCST imm8 m64 k zmm +// VPRORQ.BCST imm8 m64 zmm +// Construct and append a VPRORQ.BCST instruction to the active function. +func (c *Context) VPRORQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPRORQ_BCST(ops...)) } -// RDTSCP: Read Time-Stamp Counter and Processor ID. +// VPRORQ_BCST: Rotate Packed Quadword Right (Broadcast). // // Forms: // -// RDTSCP -// Construct and append a RDTSCP instruction to the active function. +// VPRORQ.BCST imm8 m64 k xmm +// VPRORQ.BCST imm8 m64 k ymm +// VPRORQ.BCST imm8 m64 xmm +// VPRORQ.BCST imm8 m64 ymm +// VPRORQ.BCST imm8 m64 k zmm +// VPRORQ.BCST imm8 m64 zmm +// Construct and append a VPRORQ.BCST instruction to the active function. // Operates on the global context. -func RDTSCP() { ctx.RDTSCP() } +func VPRORQ_BCST(ops ...operand.Op) { ctx.VPRORQ_BCST(ops...) } -// RET: Return from Procedure. +// VPRORQ_BCST_Z: Rotate Packed Quadword Right (Broadcast, Zeroing Masking). // // Forms: // -// RET -// Construct and append a RET instruction to the active function. -func (c *Context) RET() { - if inst, err := x86.RET(); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPRORQ.BCST.Z imm8 m64 k xmm +// VPRORQ.BCST.Z imm8 m64 k ymm +// VPRORQ.BCST.Z imm8 m64 k zmm +// Construct and append a VPRORQ.BCST.Z instruction to the active function. +func (c *Context) VPRORQ_BCST_Z(i, m, k, xyz operand.Op) { + c.addinstruction(x86.VPRORQ_BCST_Z(i, m, k, xyz)) } -// RET: Return from Procedure. +// VPRORQ_BCST_Z: Rotate Packed Quadword Right (Broadcast, Zeroing Masking). // // Forms: // -// RET -// Construct and append a RET instruction to the active function. +// VPRORQ.BCST.Z imm8 m64 k xmm +// VPRORQ.BCST.Z imm8 m64 k ymm +// VPRORQ.BCST.Z imm8 m64 k zmm +// Construct and append a VPRORQ.BCST.Z instruction to the active function. // Operates on the global context. -func RET() { ctx.RET() } +func VPRORQ_BCST_Z(i, m, k, xyz operand.Op) { ctx.VPRORQ_BCST_Z(i, m, k, xyz) } -// RETFL: Return from Procedure. +// VPRORQ_Z: Rotate Packed Quadword Right (Zeroing Masking). // // Forms: // -// RETFL imm16 -// Construct and append a RETFL instruction to the active function. -func (c *Context) RETFL(i operand.Op) { - if inst, err := x86.RETFL(i); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPRORQ.Z imm8 m128 k xmm +// VPRORQ.Z imm8 m256 k ymm +// VPRORQ.Z imm8 xmm k xmm +// VPRORQ.Z imm8 ymm k ymm +// VPRORQ.Z imm8 m512 k zmm +// VPRORQ.Z imm8 zmm k zmm +// Construct and append a VPRORQ.Z instruction to the active function. +func (c *Context) VPRORQ_Z(i, mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPRORQ_Z(i, mxyz, k, xyz)) } -// RETFL: Return from Procedure. +// VPRORQ_Z: Rotate Packed Quadword Right (Zeroing Masking). // // Forms: // -// RETFL imm16 -// Construct and append a RETFL instruction to the active function. +// VPRORQ.Z imm8 m128 k xmm +// VPRORQ.Z imm8 m256 k ymm +// VPRORQ.Z imm8 xmm k xmm +// VPRORQ.Z imm8 ymm k ymm +// VPRORQ.Z imm8 m512 k zmm +// VPRORQ.Z imm8 zmm k zmm +// Construct and append a VPRORQ.Z instruction to the active function. // Operates on the global context. -func RETFL(i operand.Op) { ctx.RETFL(i) } +func VPRORQ_Z(i, mxyz, k, xyz operand.Op) { ctx.VPRORQ_Z(i, mxyz, k, xyz) } -// RETFQ: Return from Procedure. +// VPRORVD: Variable Rotate Packed Doubleword Right. // // Forms: // -// RETFQ imm16 -// Construct and append a RETFQ instruction to the active function. -func (c *Context) RETFQ(i operand.Op) { - if inst, err := x86.RETFQ(i); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPRORVD m128 xmm k xmm +// VPRORVD m128 xmm xmm +// VPRORVD m256 ymm k ymm +// VPRORVD m256 ymm ymm +// VPRORVD xmm xmm k xmm +// VPRORVD xmm xmm xmm +// VPRORVD ymm ymm k ymm +// VPRORVD ymm ymm ymm +// VPRORVD m512 zmm k zmm +// VPRORVD m512 zmm zmm +// VPRORVD zmm zmm k zmm +// VPRORVD zmm zmm zmm +// Construct and append a VPRORVD instruction to the active function. +func (c *Context) VPRORVD(ops ...operand.Op) { + c.addinstruction(x86.VPRORVD(ops...)) } -// RETFQ: Return from Procedure. +// VPRORVD: Variable Rotate Packed Doubleword Right. // // Forms: // -// RETFQ imm16 -// Construct and append a RETFQ instruction to the active function. +// VPRORVD m128 xmm k xmm +// VPRORVD m128 xmm xmm +// VPRORVD m256 ymm k ymm +// VPRORVD m256 ymm ymm +// VPRORVD xmm xmm k xmm +// VPRORVD xmm xmm xmm +// VPRORVD ymm ymm k ymm +// VPRORVD ymm ymm ymm +// VPRORVD m512 zmm k zmm +// VPRORVD m512 zmm zmm +// VPRORVD zmm zmm k zmm +// VPRORVD zmm zmm zmm +// Construct and append a VPRORVD instruction to the active function. // Operates on the global context. -func RETFQ(i operand.Op) { ctx.RETFQ(i) } +func VPRORVD(ops ...operand.Op) { ctx.VPRORVD(ops...) } -// RETFW: Return from Procedure. +// VPRORVD_BCST: Variable Rotate Packed Doubleword Right (Broadcast). // // Forms: // -// RETFW imm16 -// Construct and append a RETFW instruction to the active function. -func (c *Context) RETFW(i operand.Op) { - if inst, err := x86.RETFW(i); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPRORVD.BCST m32 xmm k xmm +// VPRORVD.BCST m32 xmm xmm +// VPRORVD.BCST m32 ymm k ymm +// VPRORVD.BCST m32 ymm ymm +// VPRORVD.BCST m32 zmm k zmm +// VPRORVD.BCST m32 zmm zmm +// Construct and append a VPRORVD.BCST instruction to the active function. +func (c *Context) VPRORVD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPRORVD_BCST(ops...)) } -// RETFW: Return from Procedure. +// VPRORVD_BCST: Variable Rotate Packed Doubleword Right (Broadcast). // // Forms: // -// RETFW imm16 -// Construct and append a RETFW instruction to the active function. +// VPRORVD.BCST m32 xmm k xmm +// VPRORVD.BCST m32 xmm xmm +// VPRORVD.BCST m32 ymm k ymm +// VPRORVD.BCST m32 ymm ymm +// VPRORVD.BCST m32 zmm k zmm +// VPRORVD.BCST m32 zmm zmm +// Construct and append a VPRORVD.BCST instruction to the active function. // Operates on the global context. -func RETFW(i operand.Op) { ctx.RETFW(i) } +func VPRORVD_BCST(ops ...operand.Op) { ctx.VPRORVD_BCST(ops...) } -// ROLB: Rotate Left. +// VPRORVD_BCST_Z: Variable Rotate Packed Doubleword Right (Broadcast, Zeroing Masking). // // Forms: // -// ROLB 1 r8 -// ROLB imm8 r8 -// ROLB cl r8 -// ROLB 1 m8 -// ROLB imm8 m8 -// ROLB cl m8 -// Construct and append a ROLB instruction to the active function. -func (c *Context) ROLB(ci, mr operand.Op) { - if inst, err := x86.ROLB(ci, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPRORVD.BCST.Z m32 xmm k xmm +// VPRORVD.BCST.Z m32 ymm k ymm +// VPRORVD.BCST.Z m32 zmm k zmm +// Construct and append a VPRORVD.BCST.Z instruction to the active function. +func (c *Context) VPRORVD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPRORVD_BCST_Z(m, xyz, k, xyz1)) } -// ROLB: Rotate Left. +// VPRORVD_BCST_Z: Variable Rotate Packed Doubleword Right (Broadcast, Zeroing Masking). // // Forms: // -// ROLB 1 r8 -// ROLB imm8 r8 -// ROLB cl r8 -// ROLB 1 m8 -// ROLB imm8 m8 -// ROLB cl m8 -// Construct and append a ROLB instruction to the active function. +// VPRORVD.BCST.Z m32 xmm k xmm +// VPRORVD.BCST.Z m32 ymm k ymm +// VPRORVD.BCST.Z m32 zmm k zmm +// Construct and append a VPRORVD.BCST.Z instruction to the active function. // Operates on the global context. -func ROLB(ci, mr operand.Op) { ctx.ROLB(ci, mr) } +func VPRORVD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPRORVD_BCST_Z(m, xyz, k, xyz1) } -// ROLL: Rotate Left. +// VPRORVD_Z: Variable Rotate Packed Doubleword Right (Zeroing Masking). // // Forms: // -// ROLL 1 r32 -// ROLL imm8 r32 -// ROLL cl r32 -// ROLL 1 m32 -// ROLL imm8 m32 -// ROLL cl m32 -// Construct and append a ROLL instruction to the active function. -func (c *Context) ROLL(ci, mr operand.Op) { - if inst, err := x86.ROLL(ci, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPRORVD.Z m128 xmm k xmm +// VPRORVD.Z m256 ymm k ymm +// VPRORVD.Z xmm xmm k xmm +// VPRORVD.Z ymm ymm k ymm +// VPRORVD.Z m512 zmm k zmm +// VPRORVD.Z zmm zmm k zmm +// Construct and append a VPRORVD.Z instruction to the active function. +func (c *Context) VPRORVD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPRORVD_Z(mxyz, xyz, k, xyz1)) } -// ROLL: Rotate Left. +// VPRORVD_Z: Variable Rotate Packed Doubleword Right (Zeroing Masking). // // Forms: // -// ROLL 1 r32 -// ROLL imm8 r32 -// ROLL cl r32 -// ROLL 1 m32 -// ROLL imm8 m32 -// ROLL cl m32 -// Construct and append a ROLL instruction to the active function. +// VPRORVD.Z m128 xmm k xmm +// VPRORVD.Z m256 ymm k ymm +// VPRORVD.Z xmm xmm k xmm +// VPRORVD.Z ymm ymm k ymm +// VPRORVD.Z m512 zmm k zmm +// VPRORVD.Z zmm zmm k zmm +// Construct and append a VPRORVD.Z instruction to the active function. // Operates on the global context. -func ROLL(ci, mr operand.Op) { ctx.ROLL(ci, mr) } +func VPRORVD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPRORVD_Z(mxyz, xyz, k, xyz1) } -// ROLQ: Rotate Left. +// VPRORVQ: Variable Rotate Packed Quadword Right. // // Forms: // -// ROLQ 1 r64 -// ROLQ imm8 r64 -// ROLQ cl r64 -// ROLQ 1 m64 -// ROLQ imm8 m64 -// ROLQ cl m64 -// Construct and append a ROLQ instruction to the active function. -func (c *Context) ROLQ(ci, mr operand.Op) { - if inst, err := x86.ROLQ(ci, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPRORVQ m128 xmm k xmm +// VPRORVQ m128 xmm xmm +// VPRORVQ m256 ymm k ymm +// VPRORVQ m256 ymm ymm +// VPRORVQ xmm xmm k xmm +// VPRORVQ xmm xmm xmm +// VPRORVQ ymm ymm k ymm +// VPRORVQ ymm ymm ymm +// VPRORVQ m512 zmm k zmm +// VPRORVQ m512 zmm zmm +// VPRORVQ zmm zmm k zmm +// VPRORVQ zmm zmm zmm +// Construct and append a VPRORVQ instruction to the active function. +func (c *Context) VPRORVQ(ops ...operand.Op) { + c.addinstruction(x86.VPRORVQ(ops...)) } -// ROLQ: Rotate Left. +// VPRORVQ: Variable Rotate Packed Quadword Right. // // Forms: // -// ROLQ 1 r64 -// ROLQ imm8 r64 -// ROLQ cl r64 -// ROLQ 1 m64 -// ROLQ imm8 m64 -// ROLQ cl m64 -// Construct and append a ROLQ instruction to the active function. +// VPRORVQ m128 xmm k xmm +// VPRORVQ m128 xmm xmm +// VPRORVQ m256 ymm k ymm +// VPRORVQ m256 ymm ymm +// VPRORVQ xmm xmm k xmm +// VPRORVQ xmm xmm xmm +// VPRORVQ ymm ymm k ymm +// VPRORVQ ymm ymm ymm +// VPRORVQ m512 zmm k zmm +// VPRORVQ m512 zmm zmm +// VPRORVQ zmm zmm k zmm +// VPRORVQ zmm zmm zmm +// Construct and append a VPRORVQ instruction to the active function. // Operates on the global context. -func ROLQ(ci, mr operand.Op) { ctx.ROLQ(ci, mr) } +func VPRORVQ(ops ...operand.Op) { ctx.VPRORVQ(ops...) } -// ROLW: Rotate Left. +// VPRORVQ_BCST: Variable Rotate Packed Quadword Right (Broadcast). // // Forms: // -// ROLW 1 r16 -// ROLW imm8 r16 -// ROLW cl r16 -// ROLW 1 m16 -// ROLW imm8 m16 -// ROLW cl m16 -// Construct and append a ROLW instruction to the active function. -func (c *Context) ROLW(ci, mr operand.Op) { - if inst, err := x86.ROLW(ci, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPRORVQ.BCST m64 xmm k xmm +// VPRORVQ.BCST m64 xmm xmm +// VPRORVQ.BCST m64 ymm k ymm +// VPRORVQ.BCST m64 ymm ymm +// VPRORVQ.BCST m64 zmm k zmm +// VPRORVQ.BCST m64 zmm zmm +// Construct and append a VPRORVQ.BCST instruction to the active function. +func (c *Context) VPRORVQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPRORVQ_BCST(ops...)) } -// ROLW: Rotate Left. +// VPRORVQ_BCST: Variable Rotate Packed Quadword Right (Broadcast). // // Forms: // -// ROLW 1 r16 -// ROLW imm8 r16 -// ROLW cl r16 -// ROLW 1 m16 -// ROLW imm8 m16 -// ROLW cl m16 -// Construct and append a ROLW instruction to the active function. +// VPRORVQ.BCST m64 xmm k xmm +// VPRORVQ.BCST m64 xmm xmm +// VPRORVQ.BCST m64 ymm k ymm +// VPRORVQ.BCST m64 ymm ymm +// VPRORVQ.BCST m64 zmm k zmm +// VPRORVQ.BCST m64 zmm zmm +// Construct and append a VPRORVQ.BCST instruction to the active function. // Operates on the global context. -func ROLW(ci, mr operand.Op) { ctx.ROLW(ci, mr) } +func VPRORVQ_BCST(ops ...operand.Op) { ctx.VPRORVQ_BCST(ops...) } -// RORB: Rotate Right. +// VPRORVQ_BCST_Z: Variable Rotate Packed Quadword Right (Broadcast, Zeroing Masking). // // Forms: // -// RORB 1 r8 -// RORB imm8 r8 -// RORB cl r8 -// RORB 1 m8 -// RORB imm8 m8 -// RORB cl m8 -// Construct and append a RORB instruction to the active function. -func (c *Context) RORB(ci, mr operand.Op) { - if inst, err := x86.RORB(ci, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPRORVQ.BCST.Z m64 xmm k xmm +// VPRORVQ.BCST.Z m64 ymm k ymm +// VPRORVQ.BCST.Z m64 zmm k zmm +// Construct and append a VPRORVQ.BCST.Z instruction to the active function. +func (c *Context) VPRORVQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPRORVQ_BCST_Z(m, xyz, k, xyz1)) } -// RORB: Rotate Right. +// VPRORVQ_BCST_Z: Variable Rotate Packed Quadword Right (Broadcast, Zeroing Masking). // // Forms: // -// RORB 1 r8 -// RORB imm8 r8 -// RORB cl r8 -// RORB 1 m8 -// RORB imm8 m8 -// RORB cl m8 -// Construct and append a RORB instruction to the active function. +// VPRORVQ.BCST.Z m64 xmm k xmm +// VPRORVQ.BCST.Z m64 ymm k ymm +// VPRORVQ.BCST.Z m64 zmm k zmm +// Construct and append a VPRORVQ.BCST.Z instruction to the active function. // Operates on the global context. -func RORB(ci, mr operand.Op) { ctx.RORB(ci, mr) } +func VPRORVQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPRORVQ_BCST_Z(m, xyz, k, xyz1) } -// RORL: Rotate Right. +// VPRORVQ_Z: Variable Rotate Packed Quadword Right (Zeroing Masking). // // Forms: // -// RORL 1 r32 -// RORL imm8 r32 -// RORL cl r32 -// RORL 1 m32 -// RORL imm8 m32 -// RORL cl m32 -// Construct and append a RORL instruction to the active function. -func (c *Context) RORL(ci, mr operand.Op) { - if inst, err := x86.RORL(ci, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPRORVQ.Z m128 xmm k xmm +// VPRORVQ.Z m256 ymm k ymm +// VPRORVQ.Z xmm xmm k xmm +// VPRORVQ.Z ymm ymm k ymm +// VPRORVQ.Z m512 zmm k zmm +// VPRORVQ.Z zmm zmm k zmm +// Construct and append a VPRORVQ.Z instruction to the active function. +func (c *Context) VPRORVQ_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPRORVQ_Z(mxyz, xyz, k, xyz1)) } -// RORL: Rotate Right. +// VPRORVQ_Z: Variable Rotate Packed Quadword Right (Zeroing Masking). // // Forms: // -// RORL 1 r32 -// RORL imm8 r32 -// RORL cl r32 -// RORL 1 m32 -// RORL imm8 m32 -// RORL cl m32 -// Construct and append a RORL instruction to the active function. +// VPRORVQ.Z m128 xmm k xmm +// VPRORVQ.Z m256 ymm k ymm +// VPRORVQ.Z xmm xmm k xmm +// VPRORVQ.Z ymm ymm k ymm +// VPRORVQ.Z m512 zmm k zmm +// VPRORVQ.Z zmm zmm k zmm +// Construct and append a VPRORVQ.Z instruction to the active function. // Operates on the global context. -func RORL(ci, mr operand.Op) { ctx.RORL(ci, mr) } +func VPRORVQ_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPRORVQ_Z(mxyz, xyz, k, xyz1) } -// RORQ: Rotate Right. +// VPSADBW: Compute Sum of Absolute Differences. // // Forms: // -// RORQ 1 r64 -// RORQ imm8 r64 -// RORQ cl r64 -// RORQ 1 m64 -// RORQ imm8 m64 -// RORQ cl m64 -// Construct and append a RORQ instruction to the active function. -func (c *Context) RORQ(ci, mr operand.Op) { - if inst, err := x86.RORQ(ci, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSADBW m256 ymm ymm +// VPSADBW ymm ymm ymm +// VPSADBW m128 xmm xmm +// VPSADBW xmm xmm xmm +// VPSADBW m512 zmm zmm +// VPSADBW zmm zmm zmm +// Construct and append a VPSADBW instruction to the active function. +func (c *Context) VPSADBW(mxyz, xyz, xyz1 operand.Op) { + c.addinstruction(x86.VPSADBW(mxyz, xyz, xyz1)) } -// RORQ: Rotate Right. +// VPSADBW: Compute Sum of Absolute Differences. // // Forms: // -// RORQ 1 r64 -// RORQ imm8 r64 -// RORQ cl r64 -// RORQ 1 m64 -// RORQ imm8 m64 -// RORQ cl m64 -// Construct and append a RORQ instruction to the active function. +// VPSADBW m256 ymm ymm +// VPSADBW ymm ymm ymm +// VPSADBW m128 xmm xmm +// VPSADBW xmm xmm xmm +// VPSADBW m512 zmm zmm +// VPSADBW zmm zmm zmm +// Construct and append a VPSADBW instruction to the active function. // Operates on the global context. -func RORQ(ci, mr operand.Op) { ctx.RORQ(ci, mr) } +func VPSADBW(mxyz, xyz, xyz1 operand.Op) { ctx.VPSADBW(mxyz, xyz, xyz1) } -// RORW: Rotate Right. +// VPSCATTERDD: Scatter Packed Doubleword Values with Signed Doubleword Indices. // // Forms: // -// RORW 1 r16 -// RORW imm8 r16 -// RORW cl r16 -// RORW 1 m16 -// RORW imm8 m16 -// RORW cl m16 -// Construct and append a RORW instruction to the active function. -func (c *Context) RORW(ci, mr operand.Op) { - if inst, err := x86.RORW(ci, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSCATTERDD xmm k vm32x +// VPSCATTERDD ymm k vm32y +// VPSCATTERDD zmm k vm32z +// Construct and append a VPSCATTERDD instruction to the active function. +func (c *Context) VPSCATTERDD(xyz, k, v operand.Op) { + c.addinstruction(x86.VPSCATTERDD(xyz, k, v)) } -// RORW: Rotate Right. +// VPSCATTERDD: Scatter Packed Doubleword Values with Signed Doubleword Indices. // // Forms: // -// RORW 1 r16 -// RORW imm8 r16 -// RORW cl r16 -// RORW 1 m16 -// RORW imm8 m16 -// RORW cl m16 -// Construct and append a RORW instruction to the active function. +// VPSCATTERDD xmm k vm32x +// VPSCATTERDD ymm k vm32y +// VPSCATTERDD zmm k vm32z +// Construct and append a VPSCATTERDD instruction to the active function. // Operates on the global context. -func RORW(ci, mr operand.Op) { ctx.RORW(ci, mr) } +func VPSCATTERDD(xyz, k, v operand.Op) { ctx.VPSCATTERDD(xyz, k, v) } -// RORXL: Rotate Right Logical Without Affecting Flags. +// VPSCATTERDQ: Scatter Packed Quadword Values with Signed Doubleword Indices. // // Forms: // -// RORXL imm8 r32 r32 -// RORXL imm8 m32 r32 -// Construct and append a RORXL instruction to the active function. -func (c *Context) RORXL(i, mr, r operand.Op) { - if inst, err := x86.RORXL(i, mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSCATTERDQ xmm k vm32x +// VPSCATTERDQ ymm k vm32x +// VPSCATTERDQ zmm k vm32y +// Construct and append a VPSCATTERDQ instruction to the active function. +func (c *Context) VPSCATTERDQ(xyz, k, v operand.Op) { + c.addinstruction(x86.VPSCATTERDQ(xyz, k, v)) } -// RORXL: Rotate Right Logical Without Affecting Flags. +// VPSCATTERDQ: Scatter Packed Quadword Values with Signed Doubleword Indices. // // Forms: // -// RORXL imm8 r32 r32 -// RORXL imm8 m32 r32 -// Construct and append a RORXL instruction to the active function. +// VPSCATTERDQ xmm k vm32x +// VPSCATTERDQ ymm k vm32x +// VPSCATTERDQ zmm k vm32y +// Construct and append a VPSCATTERDQ instruction to the active function. // Operates on the global context. -func RORXL(i, mr, r operand.Op) { ctx.RORXL(i, mr, r) } +func VPSCATTERDQ(xyz, k, v operand.Op) { ctx.VPSCATTERDQ(xyz, k, v) } -// RORXQ: Rotate Right Logical Without Affecting Flags. +// VPSCATTERQD: Scatter Packed Doubleword Values with Signed Quadword Indices. // // Forms: // -// RORXQ imm8 r64 r64 -// RORXQ imm8 m64 r64 -// Construct and append a RORXQ instruction to the active function. -func (c *Context) RORXQ(i, mr, r operand.Op) { - if inst, err := x86.RORXQ(i, mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSCATTERQD xmm k vm64x +// VPSCATTERQD xmm k vm64y +// VPSCATTERQD ymm k vm64z +// Construct and append a VPSCATTERQD instruction to the active function. +func (c *Context) VPSCATTERQD(xy, k, v operand.Op) { + c.addinstruction(x86.VPSCATTERQD(xy, k, v)) } -// RORXQ: Rotate Right Logical Without Affecting Flags. +// VPSCATTERQD: Scatter Packed Doubleword Values with Signed Quadword Indices. // // Forms: // -// RORXQ imm8 r64 r64 -// RORXQ imm8 m64 r64 -// Construct and append a RORXQ instruction to the active function. +// VPSCATTERQD xmm k vm64x +// VPSCATTERQD xmm k vm64y +// VPSCATTERQD ymm k vm64z +// Construct and append a VPSCATTERQD instruction to the active function. // Operates on the global context. -func RORXQ(i, mr, r operand.Op) { ctx.RORXQ(i, mr, r) } +func VPSCATTERQD(xy, k, v operand.Op) { ctx.VPSCATTERQD(xy, k, v) } -// ROUNDPD: Round Packed Double Precision Floating-Point Values. +// VPSCATTERQQ: Scatter Packed Quadword Values with Signed Quadword Indices. // // Forms: // -// ROUNDPD imm8 xmm xmm -// ROUNDPD imm8 m128 xmm -// Construct and append a ROUNDPD instruction to the active function. -func (c *Context) ROUNDPD(i, mx, x operand.Op) { - if inst, err := x86.ROUNDPD(i, mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSCATTERQQ xmm k vm64x +// VPSCATTERQQ ymm k vm64y +// VPSCATTERQQ zmm k vm64z +// Construct and append a VPSCATTERQQ instruction to the active function. +func (c *Context) VPSCATTERQQ(xyz, k, v operand.Op) { + c.addinstruction(x86.VPSCATTERQQ(xyz, k, v)) } -// ROUNDPD: Round Packed Double Precision Floating-Point Values. +// VPSCATTERQQ: Scatter Packed Quadword Values with Signed Quadword Indices. // // Forms: // -// ROUNDPD imm8 xmm xmm -// ROUNDPD imm8 m128 xmm -// Construct and append a ROUNDPD instruction to the active function. +// VPSCATTERQQ xmm k vm64x +// VPSCATTERQQ ymm k vm64y +// VPSCATTERQQ zmm k vm64z +// Construct and append a VPSCATTERQQ instruction to the active function. // Operates on the global context. -func ROUNDPD(i, mx, x operand.Op) { ctx.ROUNDPD(i, mx, x) } +func VPSCATTERQQ(xyz, k, v operand.Op) { ctx.VPSCATTERQQ(xyz, k, v) } -// ROUNDPS: Round Packed Single Precision Floating-Point Values. +// VPSHUFB: Packed Shuffle Bytes. // // Forms: // -// ROUNDPS imm8 xmm xmm -// ROUNDPS imm8 m128 xmm -// Construct and append a ROUNDPS instruction to the active function. -func (c *Context) ROUNDPS(i, mx, x operand.Op) { - if inst, err := x86.ROUNDPS(i, mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSHUFB m256 ymm ymm +// VPSHUFB ymm ymm ymm +// VPSHUFB m128 xmm xmm +// VPSHUFB xmm xmm xmm +// VPSHUFB m128 xmm k xmm +// VPSHUFB m256 ymm k ymm +// VPSHUFB xmm xmm k xmm +// VPSHUFB ymm ymm k ymm +// VPSHUFB m512 zmm k zmm +// VPSHUFB m512 zmm zmm +// VPSHUFB zmm zmm k zmm +// VPSHUFB zmm zmm zmm +// Construct and append a VPSHUFB instruction to the active function. +func (c *Context) VPSHUFB(ops ...operand.Op) { + c.addinstruction(x86.VPSHUFB(ops...)) } -// ROUNDPS: Round Packed Single Precision Floating-Point Values. +// VPSHUFB: Packed Shuffle Bytes. // // Forms: // -// ROUNDPS imm8 xmm xmm -// ROUNDPS imm8 m128 xmm -// Construct and append a ROUNDPS instruction to the active function. +// VPSHUFB m256 ymm ymm +// VPSHUFB ymm ymm ymm +// VPSHUFB m128 xmm xmm +// VPSHUFB xmm xmm xmm +// VPSHUFB m128 xmm k xmm +// VPSHUFB m256 ymm k ymm +// VPSHUFB xmm xmm k xmm +// VPSHUFB ymm ymm k ymm +// VPSHUFB m512 zmm k zmm +// VPSHUFB m512 zmm zmm +// VPSHUFB zmm zmm k zmm +// VPSHUFB zmm zmm zmm +// Construct and append a VPSHUFB instruction to the active function. // Operates on the global context. -func ROUNDPS(i, mx, x operand.Op) { ctx.ROUNDPS(i, mx, x) } +func VPSHUFB(ops ...operand.Op) { ctx.VPSHUFB(ops...) } -// ROUNDSD: Round Scalar Double Precision Floating-Point Values. +// VPSHUFB_Z: Packed Shuffle Bytes (Zeroing Masking). // // Forms: // -// ROUNDSD imm8 xmm xmm -// ROUNDSD imm8 m64 xmm -// Construct and append a ROUNDSD instruction to the active function. -func (c *Context) ROUNDSD(i, mx, x operand.Op) { - if inst, err := x86.ROUNDSD(i, mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSHUFB.Z m128 xmm k xmm +// VPSHUFB.Z m256 ymm k ymm +// VPSHUFB.Z xmm xmm k xmm +// VPSHUFB.Z ymm ymm k ymm +// VPSHUFB.Z m512 zmm k zmm +// VPSHUFB.Z zmm zmm k zmm +// Construct and append a VPSHUFB.Z instruction to the active function. +func (c *Context) VPSHUFB_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPSHUFB_Z(mxyz, xyz, k, xyz1)) } -// ROUNDSD: Round Scalar Double Precision Floating-Point Values. +// VPSHUFB_Z: Packed Shuffle Bytes (Zeroing Masking). // // Forms: // -// ROUNDSD imm8 xmm xmm -// ROUNDSD imm8 m64 xmm -// Construct and append a ROUNDSD instruction to the active function. +// VPSHUFB.Z m128 xmm k xmm +// VPSHUFB.Z m256 ymm k ymm +// VPSHUFB.Z xmm xmm k xmm +// VPSHUFB.Z ymm ymm k ymm +// VPSHUFB.Z m512 zmm k zmm +// VPSHUFB.Z zmm zmm k zmm +// Construct and append a VPSHUFB.Z instruction to the active function. // Operates on the global context. -func ROUNDSD(i, mx, x operand.Op) { ctx.ROUNDSD(i, mx, x) } +func VPSHUFB_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPSHUFB_Z(mxyz, xyz, k, xyz1) } -// ROUNDSS: Round Scalar Single Precision Floating-Point Values. +// VPSHUFD: Shuffle Packed Doublewords. // // Forms: // -// ROUNDSS imm8 xmm xmm -// ROUNDSS imm8 m32 xmm -// Construct and append a ROUNDSS instruction to the active function. -func (c *Context) ROUNDSS(i, mx, x operand.Op) { - if inst, err := x86.ROUNDSS(i, mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSHUFD imm8 m256 ymm +// VPSHUFD imm8 ymm ymm +// VPSHUFD imm8 m128 xmm +// VPSHUFD imm8 xmm xmm +// VPSHUFD imm8 m128 k xmm +// VPSHUFD imm8 m256 k ymm +// VPSHUFD imm8 xmm k xmm +// VPSHUFD imm8 ymm k ymm +// VPSHUFD imm8 m512 k zmm +// VPSHUFD imm8 m512 zmm +// VPSHUFD imm8 zmm k zmm +// VPSHUFD imm8 zmm zmm +// Construct and append a VPSHUFD instruction to the active function. +func (c *Context) VPSHUFD(ops ...operand.Op) { + c.addinstruction(x86.VPSHUFD(ops...)) } -// ROUNDSS: Round Scalar Single Precision Floating-Point Values. +// VPSHUFD: Shuffle Packed Doublewords. // // Forms: // -// ROUNDSS imm8 xmm xmm -// ROUNDSS imm8 m32 xmm -// Construct and append a ROUNDSS instruction to the active function. +// VPSHUFD imm8 m256 ymm +// VPSHUFD imm8 ymm ymm +// VPSHUFD imm8 m128 xmm +// VPSHUFD imm8 xmm xmm +// VPSHUFD imm8 m128 k xmm +// VPSHUFD imm8 m256 k ymm +// VPSHUFD imm8 xmm k xmm +// VPSHUFD imm8 ymm k ymm +// VPSHUFD imm8 m512 k zmm +// VPSHUFD imm8 m512 zmm +// VPSHUFD imm8 zmm k zmm +// VPSHUFD imm8 zmm zmm +// Construct and append a VPSHUFD instruction to the active function. // Operates on the global context. -func ROUNDSS(i, mx, x operand.Op) { ctx.ROUNDSS(i, mx, x) } +func VPSHUFD(ops ...operand.Op) { ctx.VPSHUFD(ops...) } -// RSQRTPS: Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values. +// VPSHUFD_BCST: Shuffle Packed Doublewords (Broadcast). // // Forms: // -// RSQRTPS xmm xmm -// RSQRTPS m128 xmm -// Construct and append a RSQRTPS instruction to the active function. -func (c *Context) RSQRTPS(mx, x operand.Op) { - if inst, err := x86.RSQRTPS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSHUFD.BCST imm8 m32 k xmm +// VPSHUFD.BCST imm8 m32 k ymm +// VPSHUFD.BCST imm8 m32 xmm +// VPSHUFD.BCST imm8 m32 ymm +// VPSHUFD.BCST imm8 m32 k zmm +// VPSHUFD.BCST imm8 m32 zmm +// Construct and append a VPSHUFD.BCST instruction to the active function. +func (c *Context) VPSHUFD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPSHUFD_BCST(ops...)) } -// RSQRTPS: Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values. +// VPSHUFD_BCST: Shuffle Packed Doublewords (Broadcast). // // Forms: // -// RSQRTPS xmm xmm -// RSQRTPS m128 xmm -// Construct and append a RSQRTPS instruction to the active function. +// VPSHUFD.BCST imm8 m32 k xmm +// VPSHUFD.BCST imm8 m32 k ymm +// VPSHUFD.BCST imm8 m32 xmm +// VPSHUFD.BCST imm8 m32 ymm +// VPSHUFD.BCST imm8 m32 k zmm +// VPSHUFD.BCST imm8 m32 zmm +// Construct and append a VPSHUFD.BCST instruction to the active function. // Operates on the global context. -func RSQRTPS(mx, x operand.Op) { ctx.RSQRTPS(mx, x) } +func VPSHUFD_BCST(ops ...operand.Op) { ctx.VPSHUFD_BCST(ops...) } -// RSQRTSS: Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value. +// VPSHUFD_BCST_Z: Shuffle Packed Doublewords (Broadcast, Zeroing Masking). // // Forms: // -// RSQRTSS xmm xmm -// RSQRTSS m32 xmm -// Construct and append a RSQRTSS instruction to the active function. -func (c *Context) RSQRTSS(mx, x operand.Op) { - if inst, err := x86.RSQRTSS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSHUFD.BCST.Z imm8 m32 k xmm +// VPSHUFD.BCST.Z imm8 m32 k ymm +// VPSHUFD.BCST.Z imm8 m32 k zmm +// Construct and append a VPSHUFD.BCST.Z instruction to the active function. +func (c *Context) VPSHUFD_BCST_Z(i, m, k, xyz operand.Op) { + c.addinstruction(x86.VPSHUFD_BCST_Z(i, m, k, xyz)) } -// RSQRTSS: Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value. +// VPSHUFD_BCST_Z: Shuffle Packed Doublewords (Broadcast, Zeroing Masking). // // Forms: // -// RSQRTSS xmm xmm -// RSQRTSS m32 xmm -// Construct and append a RSQRTSS instruction to the active function. +// VPSHUFD.BCST.Z imm8 m32 k xmm +// VPSHUFD.BCST.Z imm8 m32 k ymm +// VPSHUFD.BCST.Z imm8 m32 k zmm +// Construct and append a VPSHUFD.BCST.Z instruction to the active function. // Operates on the global context. -func RSQRTSS(mx, x operand.Op) { ctx.RSQRTSS(mx, x) } +func VPSHUFD_BCST_Z(i, m, k, xyz operand.Op) { ctx.VPSHUFD_BCST_Z(i, m, k, xyz) } -// SALB: Arithmetic Shift Left. +// VPSHUFD_Z: Shuffle Packed Doublewords (Zeroing Masking). // // Forms: // -// SALB 1 r8 -// SALB imm8 r8 -// SALB cl r8 -// SALB 1 m8 -// SALB imm8 m8 -// SALB cl m8 -// Construct and append a SALB instruction to the active function. -func (c *Context) SALB(ci, mr operand.Op) { - if inst, err := x86.SALB(ci, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSHUFD.Z imm8 m128 k xmm +// VPSHUFD.Z imm8 m256 k ymm +// VPSHUFD.Z imm8 xmm k xmm +// VPSHUFD.Z imm8 ymm k ymm +// VPSHUFD.Z imm8 m512 k zmm +// VPSHUFD.Z imm8 zmm k zmm +// Construct and append a VPSHUFD.Z instruction to the active function. +func (c *Context) VPSHUFD_Z(i, mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPSHUFD_Z(i, mxyz, k, xyz)) } -// SALB: Arithmetic Shift Left. +// VPSHUFD_Z: Shuffle Packed Doublewords (Zeroing Masking). // // Forms: // -// SALB 1 r8 -// SALB imm8 r8 -// SALB cl r8 -// SALB 1 m8 -// SALB imm8 m8 -// SALB cl m8 -// Construct and append a SALB instruction to the active function. +// VPSHUFD.Z imm8 m128 k xmm +// VPSHUFD.Z imm8 m256 k ymm +// VPSHUFD.Z imm8 xmm k xmm +// VPSHUFD.Z imm8 ymm k ymm +// VPSHUFD.Z imm8 m512 k zmm +// VPSHUFD.Z imm8 zmm k zmm +// Construct and append a VPSHUFD.Z instruction to the active function. // Operates on the global context. -func SALB(ci, mr operand.Op) { ctx.SALB(ci, mr) } +func VPSHUFD_Z(i, mxyz, k, xyz operand.Op) { ctx.VPSHUFD_Z(i, mxyz, k, xyz) } -// SALL: Arithmetic Shift Left. +// VPSHUFHW: Shuffle Packed High Words. // // Forms: // -// SALL 1 r32 -// SALL imm8 r32 -// SALL cl r32 -// SALL 1 m32 -// SALL imm8 m32 -// SALL cl m32 -// Construct and append a SALL instruction to the active function. -func (c *Context) SALL(ci, mr operand.Op) { - if inst, err := x86.SALL(ci, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSHUFHW imm8 m256 ymm +// VPSHUFHW imm8 ymm ymm +// VPSHUFHW imm8 m128 xmm +// VPSHUFHW imm8 xmm xmm +// VPSHUFHW imm8 m128 k xmm +// VPSHUFHW imm8 m256 k ymm +// VPSHUFHW imm8 xmm k xmm +// VPSHUFHW imm8 ymm k ymm +// VPSHUFHW imm8 m512 k zmm +// VPSHUFHW imm8 m512 zmm +// VPSHUFHW imm8 zmm k zmm +// VPSHUFHW imm8 zmm zmm +// Construct and append a VPSHUFHW instruction to the active function. +func (c *Context) VPSHUFHW(ops ...operand.Op) { + c.addinstruction(x86.VPSHUFHW(ops...)) } -// SALL: Arithmetic Shift Left. +// VPSHUFHW: Shuffle Packed High Words. // // Forms: // -// SALL 1 r32 -// SALL imm8 r32 -// SALL cl r32 -// SALL 1 m32 -// SALL imm8 m32 -// SALL cl m32 -// Construct and append a SALL instruction to the active function. +// VPSHUFHW imm8 m256 ymm +// VPSHUFHW imm8 ymm ymm +// VPSHUFHW imm8 m128 xmm +// VPSHUFHW imm8 xmm xmm +// VPSHUFHW imm8 m128 k xmm +// VPSHUFHW imm8 m256 k ymm +// VPSHUFHW imm8 xmm k xmm +// VPSHUFHW imm8 ymm k ymm +// VPSHUFHW imm8 m512 k zmm +// VPSHUFHW imm8 m512 zmm +// VPSHUFHW imm8 zmm k zmm +// VPSHUFHW imm8 zmm zmm +// Construct and append a VPSHUFHW instruction to the active function. // Operates on the global context. -func SALL(ci, mr operand.Op) { ctx.SALL(ci, mr) } +func VPSHUFHW(ops ...operand.Op) { ctx.VPSHUFHW(ops...) } -// SALQ: Arithmetic Shift Left. +// VPSHUFHW_Z: Shuffle Packed High Words (Zeroing Masking). // // Forms: // -// SALQ 1 r64 -// SALQ imm8 r64 -// SALQ cl r64 -// SALQ 1 m64 -// SALQ imm8 m64 -// SALQ cl m64 -// Construct and append a SALQ instruction to the active function. -func (c *Context) SALQ(ci, mr operand.Op) { - if inst, err := x86.SALQ(ci, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSHUFHW.Z imm8 m128 k xmm +// VPSHUFHW.Z imm8 m256 k ymm +// VPSHUFHW.Z imm8 xmm k xmm +// VPSHUFHW.Z imm8 ymm k ymm +// VPSHUFHW.Z imm8 m512 k zmm +// VPSHUFHW.Z imm8 zmm k zmm +// Construct and append a VPSHUFHW.Z instruction to the active function. +func (c *Context) VPSHUFHW_Z(i, mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPSHUFHW_Z(i, mxyz, k, xyz)) } -// SALQ: Arithmetic Shift Left. +// VPSHUFHW_Z: Shuffle Packed High Words (Zeroing Masking). // // Forms: // -// SALQ 1 r64 -// SALQ imm8 r64 -// SALQ cl r64 -// SALQ 1 m64 -// SALQ imm8 m64 -// SALQ cl m64 -// Construct and append a SALQ instruction to the active function. +// VPSHUFHW.Z imm8 m128 k xmm +// VPSHUFHW.Z imm8 m256 k ymm +// VPSHUFHW.Z imm8 xmm k xmm +// VPSHUFHW.Z imm8 ymm k ymm +// VPSHUFHW.Z imm8 m512 k zmm +// VPSHUFHW.Z imm8 zmm k zmm +// Construct and append a VPSHUFHW.Z instruction to the active function. // Operates on the global context. -func SALQ(ci, mr operand.Op) { ctx.SALQ(ci, mr) } +func VPSHUFHW_Z(i, mxyz, k, xyz operand.Op) { ctx.VPSHUFHW_Z(i, mxyz, k, xyz) } -// SALW: Arithmetic Shift Left. +// VPSHUFLW: Shuffle Packed Low Words. // // Forms: // -// SALW 1 r16 -// SALW imm8 r16 -// SALW cl r16 -// SALW 1 m16 -// SALW imm8 m16 -// SALW cl m16 -// Construct and append a SALW instruction to the active function. -func (c *Context) SALW(ci, mr operand.Op) { - if inst, err := x86.SALW(ci, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSHUFLW imm8 m256 ymm +// VPSHUFLW imm8 ymm ymm +// VPSHUFLW imm8 m128 xmm +// VPSHUFLW imm8 xmm xmm +// VPSHUFLW imm8 m128 k xmm +// VPSHUFLW imm8 m256 k ymm +// VPSHUFLW imm8 xmm k xmm +// VPSHUFLW imm8 ymm k ymm +// VPSHUFLW imm8 m512 k zmm +// VPSHUFLW imm8 m512 zmm +// VPSHUFLW imm8 zmm k zmm +// VPSHUFLW imm8 zmm zmm +// Construct and append a VPSHUFLW instruction to the active function. +func (c *Context) VPSHUFLW(ops ...operand.Op) { + c.addinstruction(x86.VPSHUFLW(ops...)) } -// SALW: Arithmetic Shift Left. +// VPSHUFLW: Shuffle Packed Low Words. // // Forms: // -// SALW 1 r16 -// SALW imm8 r16 -// SALW cl r16 -// SALW 1 m16 -// SALW imm8 m16 -// SALW cl m16 -// Construct and append a SALW instruction to the active function. +// VPSHUFLW imm8 m256 ymm +// VPSHUFLW imm8 ymm ymm +// VPSHUFLW imm8 m128 xmm +// VPSHUFLW imm8 xmm xmm +// VPSHUFLW imm8 m128 k xmm +// VPSHUFLW imm8 m256 k ymm +// VPSHUFLW imm8 xmm k xmm +// VPSHUFLW imm8 ymm k ymm +// VPSHUFLW imm8 m512 k zmm +// VPSHUFLW imm8 m512 zmm +// VPSHUFLW imm8 zmm k zmm +// VPSHUFLW imm8 zmm zmm +// Construct and append a VPSHUFLW instruction to the active function. // Operates on the global context. -func SALW(ci, mr operand.Op) { ctx.SALW(ci, mr) } +func VPSHUFLW(ops ...operand.Op) { ctx.VPSHUFLW(ops...) } -// SARB: Arithmetic Shift Right. +// VPSHUFLW_Z: Shuffle Packed Low Words (Zeroing Masking). // // Forms: // -// SARB 1 r8 -// SARB imm8 r8 -// SARB cl r8 -// SARB 1 m8 -// SARB imm8 m8 -// SARB cl m8 -// Construct and append a SARB instruction to the active function. -func (c *Context) SARB(ci, mr operand.Op) { - if inst, err := x86.SARB(ci, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSHUFLW.Z imm8 m128 k xmm +// VPSHUFLW.Z imm8 m256 k ymm +// VPSHUFLW.Z imm8 xmm k xmm +// VPSHUFLW.Z imm8 ymm k ymm +// VPSHUFLW.Z imm8 m512 k zmm +// VPSHUFLW.Z imm8 zmm k zmm +// Construct and append a VPSHUFLW.Z instruction to the active function. +func (c *Context) VPSHUFLW_Z(i, mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPSHUFLW_Z(i, mxyz, k, xyz)) } -// SARB: Arithmetic Shift Right. +// VPSHUFLW_Z: Shuffle Packed Low Words (Zeroing Masking). // // Forms: // -// SARB 1 r8 -// SARB imm8 r8 -// SARB cl r8 -// SARB 1 m8 -// SARB imm8 m8 -// SARB cl m8 -// Construct and append a SARB instruction to the active function. +// VPSHUFLW.Z imm8 m128 k xmm +// VPSHUFLW.Z imm8 m256 k ymm +// VPSHUFLW.Z imm8 xmm k xmm +// VPSHUFLW.Z imm8 ymm k ymm +// VPSHUFLW.Z imm8 m512 k zmm +// VPSHUFLW.Z imm8 zmm k zmm +// Construct and append a VPSHUFLW.Z instruction to the active function. // Operates on the global context. -func SARB(ci, mr operand.Op) { ctx.SARB(ci, mr) } +func VPSHUFLW_Z(i, mxyz, k, xyz operand.Op) { ctx.VPSHUFLW_Z(i, mxyz, k, xyz) } -// SARL: Arithmetic Shift Right. +// VPSIGNB: Packed Sign of Byte Integers. // // Forms: // -// SARL 1 r32 -// SARL imm8 r32 -// SARL cl r32 -// SARL 1 m32 -// SARL imm8 m32 -// SARL cl m32 -// Construct and append a SARL instruction to the active function. -func (c *Context) SARL(ci, mr operand.Op) { - if inst, err := x86.SARL(ci, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSIGNB m256 ymm ymm +// VPSIGNB ymm ymm ymm +// VPSIGNB m128 xmm xmm +// VPSIGNB xmm xmm xmm +// Construct and append a VPSIGNB instruction to the active function. +func (c *Context) VPSIGNB(mxy, xy, xy1 operand.Op) { + c.addinstruction(x86.VPSIGNB(mxy, xy, xy1)) } -// SARL: Arithmetic Shift Right. +// VPSIGNB: Packed Sign of Byte Integers. // // Forms: // -// SARL 1 r32 -// SARL imm8 r32 -// SARL cl r32 -// SARL 1 m32 -// SARL imm8 m32 -// SARL cl m32 -// Construct and append a SARL instruction to the active function. +// VPSIGNB m256 ymm ymm +// VPSIGNB ymm ymm ymm +// VPSIGNB m128 xmm xmm +// VPSIGNB xmm xmm xmm +// Construct and append a VPSIGNB instruction to the active function. // Operates on the global context. -func SARL(ci, mr operand.Op) { ctx.SARL(ci, mr) } +func VPSIGNB(mxy, xy, xy1 operand.Op) { ctx.VPSIGNB(mxy, xy, xy1) } -// SARQ: Arithmetic Shift Right. +// VPSIGND: Packed Sign of Doubleword Integers. // // Forms: // -// SARQ 1 r64 -// SARQ imm8 r64 -// SARQ cl r64 -// SARQ 1 m64 -// SARQ imm8 m64 -// SARQ cl m64 -// Construct and append a SARQ instruction to the active function. -func (c *Context) SARQ(ci, mr operand.Op) { - if inst, err := x86.SARQ(ci, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSIGND m256 ymm ymm +// VPSIGND ymm ymm ymm +// VPSIGND m128 xmm xmm +// VPSIGND xmm xmm xmm +// Construct and append a VPSIGND instruction to the active function. +func (c *Context) VPSIGND(mxy, xy, xy1 operand.Op) { + c.addinstruction(x86.VPSIGND(mxy, xy, xy1)) } -// SARQ: Arithmetic Shift Right. +// VPSIGND: Packed Sign of Doubleword Integers. // // Forms: // -// SARQ 1 r64 -// SARQ imm8 r64 -// SARQ cl r64 -// SARQ 1 m64 -// SARQ imm8 m64 -// SARQ cl m64 -// Construct and append a SARQ instruction to the active function. +// VPSIGND m256 ymm ymm +// VPSIGND ymm ymm ymm +// VPSIGND m128 xmm xmm +// VPSIGND xmm xmm xmm +// Construct and append a VPSIGND instruction to the active function. // Operates on the global context. -func SARQ(ci, mr operand.Op) { ctx.SARQ(ci, mr) } +func VPSIGND(mxy, xy, xy1 operand.Op) { ctx.VPSIGND(mxy, xy, xy1) } -// SARW: Arithmetic Shift Right. +// VPSIGNW: Packed Sign of Word Integers. // // Forms: // -// SARW 1 r16 -// SARW imm8 r16 -// SARW cl r16 -// SARW 1 m16 -// SARW imm8 m16 -// SARW cl m16 -// Construct and append a SARW instruction to the active function. -func (c *Context) SARW(ci, mr operand.Op) { - if inst, err := x86.SARW(ci, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSIGNW m256 ymm ymm +// VPSIGNW ymm ymm ymm +// VPSIGNW m128 xmm xmm +// VPSIGNW xmm xmm xmm +// Construct and append a VPSIGNW instruction to the active function. +func (c *Context) VPSIGNW(mxy, xy, xy1 operand.Op) { + c.addinstruction(x86.VPSIGNW(mxy, xy, xy1)) } -// SARW: Arithmetic Shift Right. +// VPSIGNW: Packed Sign of Word Integers. // // Forms: // -// SARW 1 r16 -// SARW imm8 r16 -// SARW cl r16 -// SARW 1 m16 -// SARW imm8 m16 -// SARW cl m16 -// Construct and append a SARW instruction to the active function. +// VPSIGNW m256 ymm ymm +// VPSIGNW ymm ymm ymm +// VPSIGNW m128 xmm xmm +// VPSIGNW xmm xmm xmm +// Construct and append a VPSIGNW instruction to the active function. // Operates on the global context. -func SARW(ci, mr operand.Op) { ctx.SARW(ci, mr) } +func VPSIGNW(mxy, xy, xy1 operand.Op) { ctx.VPSIGNW(mxy, xy, xy1) } -// SARXL: Arithmetic Shift Right Without Affecting Flags. +// VPSLLD: Shift Packed Doubleword Data Left Logical. // // Forms: // -// SARXL r32 r32 r32 -// SARXL r32 m32 r32 -// Construct and append a SARXL instruction to the active function. -func (c *Context) SARXL(r, mr, r1 operand.Op) { - if inst, err := x86.SARXL(r, mr, r1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSLLD imm8 ymm ymm +// VPSLLD m128 ymm ymm +// VPSLLD xmm ymm ymm +// VPSLLD imm8 xmm xmm +// VPSLLD m128 xmm xmm +// VPSLLD xmm xmm xmm +// VPSLLD imm8 m128 k xmm +// VPSLLD imm8 m128 xmm +// VPSLLD imm8 m256 k ymm +// VPSLLD imm8 m256 ymm +// VPSLLD imm8 xmm k xmm +// VPSLLD imm8 ymm k ymm +// VPSLLD m128 xmm k xmm +// VPSLLD m128 ymm k ymm +// VPSLLD xmm xmm k xmm +// VPSLLD xmm ymm k ymm +// VPSLLD imm8 m512 k zmm +// VPSLLD imm8 m512 zmm +// VPSLLD imm8 zmm k zmm +// VPSLLD imm8 zmm zmm +// VPSLLD m128 zmm k zmm +// VPSLLD m128 zmm zmm +// VPSLLD xmm zmm k zmm +// VPSLLD xmm zmm zmm +// Construct and append a VPSLLD instruction to the active function. +func (c *Context) VPSLLD(ops ...operand.Op) { + c.addinstruction(x86.VPSLLD(ops...)) } -// SARXL: Arithmetic Shift Right Without Affecting Flags. +// VPSLLD: Shift Packed Doubleword Data Left Logical. // // Forms: // -// SARXL r32 r32 r32 -// SARXL r32 m32 r32 -// Construct and append a SARXL instruction to the active function. +// VPSLLD imm8 ymm ymm +// VPSLLD m128 ymm ymm +// VPSLLD xmm ymm ymm +// VPSLLD imm8 xmm xmm +// VPSLLD m128 xmm xmm +// VPSLLD xmm xmm xmm +// VPSLLD imm8 m128 k xmm +// VPSLLD imm8 m128 xmm +// VPSLLD imm8 m256 k ymm +// VPSLLD imm8 m256 ymm +// VPSLLD imm8 xmm k xmm +// VPSLLD imm8 ymm k ymm +// VPSLLD m128 xmm k xmm +// VPSLLD m128 ymm k ymm +// VPSLLD xmm xmm k xmm +// VPSLLD xmm ymm k ymm +// VPSLLD imm8 m512 k zmm +// VPSLLD imm8 m512 zmm +// VPSLLD imm8 zmm k zmm +// VPSLLD imm8 zmm zmm +// VPSLLD m128 zmm k zmm +// VPSLLD m128 zmm zmm +// VPSLLD xmm zmm k zmm +// VPSLLD xmm zmm zmm +// Construct and append a VPSLLD instruction to the active function. // Operates on the global context. -func SARXL(r, mr, r1 operand.Op) { ctx.SARXL(r, mr, r1) } +func VPSLLD(ops ...operand.Op) { ctx.VPSLLD(ops...) } -// SARXQ: Arithmetic Shift Right Without Affecting Flags. +// VPSLLDQ: Shift Packed Double Quadword Left Logical. // // Forms: // -// SARXQ r64 r64 r64 -// SARXQ r64 m64 r64 -// Construct and append a SARXQ instruction to the active function. -func (c *Context) SARXQ(r, mr, r1 operand.Op) { - if inst, err := x86.SARXQ(r, mr, r1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSLLDQ imm8 ymm ymm +// VPSLLDQ imm8 xmm xmm +// VPSLLDQ imm8 m128 xmm +// VPSLLDQ imm8 m256 ymm +// VPSLLDQ imm8 m512 zmm +// VPSLLDQ imm8 zmm zmm +// Construct and append a VPSLLDQ instruction to the active function. +func (c *Context) VPSLLDQ(i, mxyz, xyz operand.Op) { + c.addinstruction(x86.VPSLLDQ(i, mxyz, xyz)) } -// SARXQ: Arithmetic Shift Right Without Affecting Flags. +// VPSLLDQ: Shift Packed Double Quadword Left Logical. // // Forms: // -// SARXQ r64 r64 r64 -// SARXQ r64 m64 r64 -// Construct and append a SARXQ instruction to the active function. +// VPSLLDQ imm8 ymm ymm +// VPSLLDQ imm8 xmm xmm +// VPSLLDQ imm8 m128 xmm +// VPSLLDQ imm8 m256 ymm +// VPSLLDQ imm8 m512 zmm +// VPSLLDQ imm8 zmm zmm +// Construct and append a VPSLLDQ instruction to the active function. // Operates on the global context. -func SARXQ(r, mr, r1 operand.Op) { ctx.SARXQ(r, mr, r1) } +func VPSLLDQ(i, mxyz, xyz operand.Op) { ctx.VPSLLDQ(i, mxyz, xyz) } -// SBBB: Subtract with Borrow. +// VPSLLD_BCST: Shift Packed Doubleword Data Left Logical (Broadcast). // // Forms: // -// SBBB imm8 al -// SBBB imm8 r8 -// SBBB r8 r8 -// SBBB m8 r8 -// SBBB imm8 m8 -// SBBB r8 m8 -// Construct and append a SBBB instruction to the active function. -func (c *Context) SBBB(imr, amr operand.Op) { - if inst, err := x86.SBBB(imr, amr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSLLD.BCST imm8 m32 k xmm +// VPSLLD.BCST imm8 m32 k ymm +// VPSLLD.BCST imm8 m32 xmm +// VPSLLD.BCST imm8 m32 ymm +// VPSLLD.BCST imm8 m32 k zmm +// VPSLLD.BCST imm8 m32 zmm +// Construct and append a VPSLLD.BCST instruction to the active function. +func (c *Context) VPSLLD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPSLLD_BCST(ops...)) } -// SBBB: Subtract with Borrow. +// VPSLLD_BCST: Shift Packed Doubleword Data Left Logical (Broadcast). // // Forms: // -// SBBB imm8 al -// SBBB imm8 r8 -// SBBB r8 r8 -// SBBB m8 r8 -// SBBB imm8 m8 -// SBBB r8 m8 -// Construct and append a SBBB instruction to the active function. +// VPSLLD.BCST imm8 m32 k xmm +// VPSLLD.BCST imm8 m32 k ymm +// VPSLLD.BCST imm8 m32 xmm +// VPSLLD.BCST imm8 m32 ymm +// VPSLLD.BCST imm8 m32 k zmm +// VPSLLD.BCST imm8 m32 zmm +// Construct and append a VPSLLD.BCST instruction to the active function. // Operates on the global context. -func SBBB(imr, amr operand.Op) { ctx.SBBB(imr, amr) } +func VPSLLD_BCST(ops ...operand.Op) { ctx.VPSLLD_BCST(ops...) } -// SBBL: Subtract with Borrow. +// VPSLLD_BCST_Z: Shift Packed Doubleword Data Left Logical (Broadcast, Zeroing Masking). // // Forms: // -// SBBL imm32 eax -// SBBL imm8 r32 -// SBBL imm32 r32 -// SBBL r32 r32 -// SBBL m32 r32 -// SBBL imm8 m32 -// SBBL imm32 m32 -// SBBL r32 m32 -// Construct and append a SBBL instruction to the active function. -func (c *Context) SBBL(imr, emr operand.Op) { - if inst, err := x86.SBBL(imr, emr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSLLD.BCST.Z imm8 m32 k xmm +// VPSLLD.BCST.Z imm8 m32 k ymm +// VPSLLD.BCST.Z imm8 m32 k zmm +// Construct and append a VPSLLD.BCST.Z instruction to the active function. +func (c *Context) VPSLLD_BCST_Z(i, m, k, xyz operand.Op) { + c.addinstruction(x86.VPSLLD_BCST_Z(i, m, k, xyz)) } -// SBBL: Subtract with Borrow. +// VPSLLD_BCST_Z: Shift Packed Doubleword Data Left Logical (Broadcast, Zeroing Masking). // // Forms: // -// SBBL imm32 eax -// SBBL imm8 r32 -// SBBL imm32 r32 -// SBBL r32 r32 -// SBBL m32 r32 -// SBBL imm8 m32 -// SBBL imm32 m32 -// SBBL r32 m32 -// Construct and append a SBBL instruction to the active function. +// VPSLLD.BCST.Z imm8 m32 k xmm +// VPSLLD.BCST.Z imm8 m32 k ymm +// VPSLLD.BCST.Z imm8 m32 k zmm +// Construct and append a VPSLLD.BCST.Z instruction to the active function. // Operates on the global context. -func SBBL(imr, emr operand.Op) { ctx.SBBL(imr, emr) } +func VPSLLD_BCST_Z(i, m, k, xyz operand.Op) { ctx.VPSLLD_BCST_Z(i, m, k, xyz) } -// SBBQ: Subtract with Borrow. +// VPSLLD_Z: Shift Packed Doubleword Data Left Logical (Zeroing Masking). // // Forms: // -// SBBQ imm32 rax -// SBBQ imm8 r64 -// SBBQ imm32 r64 -// SBBQ r64 r64 -// SBBQ m64 r64 -// SBBQ imm8 m64 -// SBBQ imm32 m64 -// SBBQ r64 m64 -// Construct and append a SBBQ instruction to the active function. -func (c *Context) SBBQ(imr, mr operand.Op) { - if inst, err := x86.SBBQ(imr, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSLLD.Z imm8 m128 k xmm +// VPSLLD.Z imm8 m256 k ymm +// VPSLLD.Z imm8 xmm k xmm +// VPSLLD.Z imm8 ymm k ymm +// VPSLLD.Z m128 xmm k xmm +// VPSLLD.Z m128 ymm k ymm +// VPSLLD.Z xmm xmm k xmm +// VPSLLD.Z xmm ymm k ymm +// VPSLLD.Z imm8 m512 k zmm +// VPSLLD.Z imm8 zmm k zmm +// VPSLLD.Z m128 zmm k zmm +// VPSLLD.Z xmm zmm k zmm +// Construct and append a VPSLLD.Z instruction to the active function. +func (c *Context) VPSLLD_Z(imx, mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPSLLD_Z(imx, mxyz, k, xyz)) } -// SBBQ: Subtract with Borrow. +// VPSLLD_Z: Shift Packed Doubleword Data Left Logical (Zeroing Masking). // // Forms: // -// SBBQ imm32 rax -// SBBQ imm8 r64 -// SBBQ imm32 r64 -// SBBQ r64 r64 -// SBBQ m64 r64 -// SBBQ imm8 m64 -// SBBQ imm32 m64 -// SBBQ r64 m64 -// Construct and append a SBBQ instruction to the active function. +// VPSLLD.Z imm8 m128 k xmm +// VPSLLD.Z imm8 m256 k ymm +// VPSLLD.Z imm8 xmm k xmm +// VPSLLD.Z imm8 ymm k ymm +// VPSLLD.Z m128 xmm k xmm +// VPSLLD.Z m128 ymm k ymm +// VPSLLD.Z xmm xmm k xmm +// VPSLLD.Z xmm ymm k ymm +// VPSLLD.Z imm8 m512 k zmm +// VPSLLD.Z imm8 zmm k zmm +// VPSLLD.Z m128 zmm k zmm +// VPSLLD.Z xmm zmm k zmm +// Construct and append a VPSLLD.Z instruction to the active function. // Operates on the global context. -func SBBQ(imr, mr operand.Op) { ctx.SBBQ(imr, mr) } +func VPSLLD_Z(imx, mxyz, k, xyz operand.Op) { ctx.VPSLLD_Z(imx, mxyz, k, xyz) } -// SBBW: Subtract with Borrow. +// VPSLLQ: Shift Packed Quadword Data Left Logical. // // Forms: // -// SBBW imm16 ax -// SBBW imm8 r16 -// SBBW imm16 r16 -// SBBW r16 r16 -// SBBW m16 r16 -// SBBW imm8 m16 -// SBBW imm16 m16 -// SBBW r16 m16 -// Construct and append a SBBW instruction to the active function. -func (c *Context) SBBW(imr, amr operand.Op) { - if inst, err := x86.SBBW(imr, amr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSLLQ imm8 ymm ymm +// VPSLLQ m128 ymm ymm +// VPSLLQ xmm ymm ymm +// VPSLLQ imm8 xmm xmm +// VPSLLQ m128 xmm xmm +// VPSLLQ xmm xmm xmm +// VPSLLQ imm8 m128 k xmm +// VPSLLQ imm8 m128 xmm +// VPSLLQ imm8 m256 k ymm +// VPSLLQ imm8 m256 ymm +// VPSLLQ imm8 xmm k xmm +// VPSLLQ imm8 ymm k ymm +// VPSLLQ m128 xmm k xmm +// VPSLLQ m128 ymm k ymm +// VPSLLQ xmm xmm k xmm +// VPSLLQ xmm ymm k ymm +// VPSLLQ imm8 m512 k zmm +// VPSLLQ imm8 m512 zmm +// VPSLLQ imm8 zmm k zmm +// VPSLLQ imm8 zmm zmm +// VPSLLQ m128 zmm k zmm +// VPSLLQ m128 zmm zmm +// VPSLLQ xmm zmm k zmm +// VPSLLQ xmm zmm zmm +// Construct and append a VPSLLQ instruction to the active function. +func (c *Context) VPSLLQ(ops ...operand.Op) { + c.addinstruction(x86.VPSLLQ(ops...)) } -// SBBW: Subtract with Borrow. +// VPSLLQ: Shift Packed Quadword Data Left Logical. // // Forms: // -// SBBW imm16 ax -// SBBW imm8 r16 -// SBBW imm16 r16 -// SBBW r16 r16 -// SBBW m16 r16 -// SBBW imm8 m16 -// SBBW imm16 m16 -// SBBW r16 m16 -// Construct and append a SBBW instruction to the active function. +// VPSLLQ imm8 ymm ymm +// VPSLLQ m128 ymm ymm +// VPSLLQ xmm ymm ymm +// VPSLLQ imm8 xmm xmm +// VPSLLQ m128 xmm xmm +// VPSLLQ xmm xmm xmm +// VPSLLQ imm8 m128 k xmm +// VPSLLQ imm8 m128 xmm +// VPSLLQ imm8 m256 k ymm +// VPSLLQ imm8 m256 ymm +// VPSLLQ imm8 xmm k xmm +// VPSLLQ imm8 ymm k ymm +// VPSLLQ m128 xmm k xmm +// VPSLLQ m128 ymm k ymm +// VPSLLQ xmm xmm k xmm +// VPSLLQ xmm ymm k ymm +// VPSLLQ imm8 m512 k zmm +// VPSLLQ imm8 m512 zmm +// VPSLLQ imm8 zmm k zmm +// VPSLLQ imm8 zmm zmm +// VPSLLQ m128 zmm k zmm +// VPSLLQ m128 zmm zmm +// VPSLLQ xmm zmm k zmm +// VPSLLQ xmm zmm zmm +// Construct and append a VPSLLQ instruction to the active function. // Operates on the global context. -func SBBW(imr, amr operand.Op) { ctx.SBBW(imr, amr) } +func VPSLLQ(ops ...operand.Op) { ctx.VPSLLQ(ops...) } -// SETCC: Set byte if above or equal (CF == 0). +// VPSLLQ_BCST: Shift Packed Quadword Data Left Logical (Broadcast). // // Forms: // -// SETCC r8 -// SETCC m8 -// Construct and append a SETCC instruction to the active function. -func (c *Context) SETCC(mr operand.Op) { - if inst, err := x86.SETCC(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSLLQ.BCST imm8 m64 k xmm +// VPSLLQ.BCST imm8 m64 k ymm +// VPSLLQ.BCST imm8 m64 xmm +// VPSLLQ.BCST imm8 m64 ymm +// VPSLLQ.BCST imm8 m64 k zmm +// VPSLLQ.BCST imm8 m64 zmm +// Construct and append a VPSLLQ.BCST instruction to the active function. +func (c *Context) VPSLLQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPSLLQ_BCST(ops...)) } -// SETCC: Set byte if above or equal (CF == 0). +// VPSLLQ_BCST: Shift Packed Quadword Data Left Logical (Broadcast). // // Forms: // -// SETCC r8 -// SETCC m8 -// Construct and append a SETCC instruction to the active function. +// VPSLLQ.BCST imm8 m64 k xmm +// VPSLLQ.BCST imm8 m64 k ymm +// VPSLLQ.BCST imm8 m64 xmm +// VPSLLQ.BCST imm8 m64 ymm +// VPSLLQ.BCST imm8 m64 k zmm +// VPSLLQ.BCST imm8 m64 zmm +// Construct and append a VPSLLQ.BCST instruction to the active function. // Operates on the global context. -func SETCC(mr operand.Op) { ctx.SETCC(mr) } +func VPSLLQ_BCST(ops ...operand.Op) { ctx.VPSLLQ_BCST(ops...) } -// SETCS: Set byte if below (CF == 1). +// VPSLLQ_BCST_Z: Shift Packed Quadword Data Left Logical (Broadcast, Zeroing Masking). // // Forms: // -// SETCS r8 -// SETCS m8 -// Construct and append a SETCS instruction to the active function. -func (c *Context) SETCS(mr operand.Op) { - if inst, err := x86.SETCS(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSLLQ.BCST.Z imm8 m64 k xmm +// VPSLLQ.BCST.Z imm8 m64 k ymm +// VPSLLQ.BCST.Z imm8 m64 k zmm +// Construct and append a VPSLLQ.BCST.Z instruction to the active function. +func (c *Context) VPSLLQ_BCST_Z(i, m, k, xyz operand.Op) { + c.addinstruction(x86.VPSLLQ_BCST_Z(i, m, k, xyz)) } -// SETCS: Set byte if below (CF == 1). +// VPSLLQ_BCST_Z: Shift Packed Quadword Data Left Logical (Broadcast, Zeroing Masking). // // Forms: // -// SETCS r8 -// SETCS m8 -// Construct and append a SETCS instruction to the active function. +// VPSLLQ.BCST.Z imm8 m64 k xmm +// VPSLLQ.BCST.Z imm8 m64 k ymm +// VPSLLQ.BCST.Z imm8 m64 k zmm +// Construct and append a VPSLLQ.BCST.Z instruction to the active function. // Operates on the global context. -func SETCS(mr operand.Op) { ctx.SETCS(mr) } +func VPSLLQ_BCST_Z(i, m, k, xyz operand.Op) { ctx.VPSLLQ_BCST_Z(i, m, k, xyz) } -// SETEQ: Set byte if equal (ZF == 1). +// VPSLLQ_Z: Shift Packed Quadword Data Left Logical (Zeroing Masking). // // Forms: // -// SETEQ r8 -// SETEQ m8 -// Construct and append a SETEQ instruction to the active function. -func (c *Context) SETEQ(mr operand.Op) { - if inst, err := x86.SETEQ(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSLLQ.Z imm8 m128 k xmm +// VPSLLQ.Z imm8 m256 k ymm +// VPSLLQ.Z imm8 xmm k xmm +// VPSLLQ.Z imm8 ymm k ymm +// VPSLLQ.Z m128 xmm k xmm +// VPSLLQ.Z m128 ymm k ymm +// VPSLLQ.Z xmm xmm k xmm +// VPSLLQ.Z xmm ymm k ymm +// VPSLLQ.Z imm8 m512 k zmm +// VPSLLQ.Z imm8 zmm k zmm +// VPSLLQ.Z m128 zmm k zmm +// VPSLLQ.Z xmm zmm k zmm +// Construct and append a VPSLLQ.Z instruction to the active function. +func (c *Context) VPSLLQ_Z(imx, mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPSLLQ_Z(imx, mxyz, k, xyz)) } -// SETEQ: Set byte if equal (ZF == 1). +// VPSLLQ_Z: Shift Packed Quadword Data Left Logical (Zeroing Masking). // // Forms: // -// SETEQ r8 -// SETEQ m8 -// Construct and append a SETEQ instruction to the active function. +// VPSLLQ.Z imm8 m128 k xmm +// VPSLLQ.Z imm8 m256 k ymm +// VPSLLQ.Z imm8 xmm k xmm +// VPSLLQ.Z imm8 ymm k ymm +// VPSLLQ.Z m128 xmm k xmm +// VPSLLQ.Z m128 ymm k ymm +// VPSLLQ.Z xmm xmm k xmm +// VPSLLQ.Z xmm ymm k ymm +// VPSLLQ.Z imm8 m512 k zmm +// VPSLLQ.Z imm8 zmm k zmm +// VPSLLQ.Z m128 zmm k zmm +// VPSLLQ.Z xmm zmm k zmm +// Construct and append a VPSLLQ.Z instruction to the active function. // Operates on the global context. -func SETEQ(mr operand.Op) { ctx.SETEQ(mr) } +func VPSLLQ_Z(imx, mxyz, k, xyz operand.Op) { ctx.VPSLLQ_Z(imx, mxyz, k, xyz) } -// SETGE: Set byte if greater or equal (SF == OF). +// VPSLLVD: Variable Shift Packed Doubleword Data Left Logical. // // Forms: // -// SETGE r8 -// SETGE m8 -// Construct and append a SETGE instruction to the active function. -func (c *Context) SETGE(mr operand.Op) { - if inst, err := x86.SETGE(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSLLVD m128 xmm xmm +// VPSLLVD m256 ymm ymm +// VPSLLVD xmm xmm xmm +// VPSLLVD ymm ymm ymm +// VPSLLVD m128 xmm k xmm +// VPSLLVD m256 ymm k ymm +// VPSLLVD xmm xmm k xmm +// VPSLLVD ymm ymm k ymm +// VPSLLVD m512 zmm k zmm +// VPSLLVD m512 zmm zmm +// VPSLLVD zmm zmm k zmm +// VPSLLVD zmm zmm zmm +// Construct and append a VPSLLVD instruction to the active function. +func (c *Context) VPSLLVD(ops ...operand.Op) { + c.addinstruction(x86.VPSLLVD(ops...)) } -// SETGE: Set byte if greater or equal (SF == OF). +// VPSLLVD: Variable Shift Packed Doubleword Data Left Logical. // // Forms: // -// SETGE r8 -// SETGE m8 -// Construct and append a SETGE instruction to the active function. +// VPSLLVD m128 xmm xmm +// VPSLLVD m256 ymm ymm +// VPSLLVD xmm xmm xmm +// VPSLLVD ymm ymm ymm +// VPSLLVD m128 xmm k xmm +// VPSLLVD m256 ymm k ymm +// VPSLLVD xmm xmm k xmm +// VPSLLVD ymm ymm k ymm +// VPSLLVD m512 zmm k zmm +// VPSLLVD m512 zmm zmm +// VPSLLVD zmm zmm k zmm +// VPSLLVD zmm zmm zmm +// Construct and append a VPSLLVD instruction to the active function. // Operates on the global context. -func SETGE(mr operand.Op) { ctx.SETGE(mr) } +func VPSLLVD(ops ...operand.Op) { ctx.VPSLLVD(ops...) } -// SETGT: Set byte if greater (ZF == 0 and SF == OF). +// VPSLLVD_BCST: Variable Shift Packed Doubleword Data Left Logical (Broadcast). // // Forms: // -// SETGT r8 -// SETGT m8 -// Construct and append a SETGT instruction to the active function. -func (c *Context) SETGT(mr operand.Op) { - if inst, err := x86.SETGT(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSLLVD.BCST m32 xmm k xmm +// VPSLLVD.BCST m32 xmm xmm +// VPSLLVD.BCST m32 ymm k ymm +// VPSLLVD.BCST m32 ymm ymm +// VPSLLVD.BCST m32 zmm k zmm +// VPSLLVD.BCST m32 zmm zmm +// Construct and append a VPSLLVD.BCST instruction to the active function. +func (c *Context) VPSLLVD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPSLLVD_BCST(ops...)) } -// SETGT: Set byte if greater (ZF == 0 and SF == OF). +// VPSLLVD_BCST: Variable Shift Packed Doubleword Data Left Logical (Broadcast). // // Forms: // -// SETGT r8 -// SETGT m8 -// Construct and append a SETGT instruction to the active function. +// VPSLLVD.BCST m32 xmm k xmm +// VPSLLVD.BCST m32 xmm xmm +// VPSLLVD.BCST m32 ymm k ymm +// VPSLLVD.BCST m32 ymm ymm +// VPSLLVD.BCST m32 zmm k zmm +// VPSLLVD.BCST m32 zmm zmm +// Construct and append a VPSLLVD.BCST instruction to the active function. // Operates on the global context. -func SETGT(mr operand.Op) { ctx.SETGT(mr) } +func VPSLLVD_BCST(ops ...operand.Op) { ctx.VPSLLVD_BCST(ops...) } -// SETHI: Set byte if above (CF == 0 and ZF == 0). +// VPSLLVD_BCST_Z: Variable Shift Packed Doubleword Data Left Logical (Broadcast, Zeroing Masking). // // Forms: // -// SETHI r8 -// SETHI m8 -// Construct and append a SETHI instruction to the active function. -func (c *Context) SETHI(mr operand.Op) { - if inst, err := x86.SETHI(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSLLVD.BCST.Z m32 xmm k xmm +// VPSLLVD.BCST.Z m32 ymm k ymm +// VPSLLVD.BCST.Z m32 zmm k zmm +// Construct and append a VPSLLVD.BCST.Z instruction to the active function. +func (c *Context) VPSLLVD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPSLLVD_BCST_Z(m, xyz, k, xyz1)) } -// SETHI: Set byte if above (CF == 0 and ZF == 0). +// VPSLLVD_BCST_Z: Variable Shift Packed Doubleword Data Left Logical (Broadcast, Zeroing Masking). // // Forms: // -// SETHI r8 -// SETHI m8 -// Construct and append a SETHI instruction to the active function. +// VPSLLVD.BCST.Z m32 xmm k xmm +// VPSLLVD.BCST.Z m32 ymm k ymm +// VPSLLVD.BCST.Z m32 zmm k zmm +// Construct and append a VPSLLVD.BCST.Z instruction to the active function. // Operates on the global context. -func SETHI(mr operand.Op) { ctx.SETHI(mr) } +func VPSLLVD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPSLLVD_BCST_Z(m, xyz, k, xyz1) } -// SETLE: Set byte if less or equal (ZF == 1 or SF != OF). +// VPSLLVD_Z: Variable Shift Packed Doubleword Data Left Logical (Zeroing Masking). // // Forms: // -// SETLE r8 -// SETLE m8 -// Construct and append a SETLE instruction to the active function. -func (c *Context) SETLE(mr operand.Op) { - if inst, err := x86.SETLE(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSLLVD.Z m128 xmm k xmm +// VPSLLVD.Z m256 ymm k ymm +// VPSLLVD.Z xmm xmm k xmm +// VPSLLVD.Z ymm ymm k ymm +// VPSLLVD.Z m512 zmm k zmm +// VPSLLVD.Z zmm zmm k zmm +// Construct and append a VPSLLVD.Z instruction to the active function. +func (c *Context) VPSLLVD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPSLLVD_Z(mxyz, xyz, k, xyz1)) } -// SETLE: Set byte if less or equal (ZF == 1 or SF != OF). +// VPSLLVD_Z: Variable Shift Packed Doubleword Data Left Logical (Zeroing Masking). // // Forms: // -// SETLE r8 -// SETLE m8 -// Construct and append a SETLE instruction to the active function. +// VPSLLVD.Z m128 xmm k xmm +// VPSLLVD.Z m256 ymm k ymm +// VPSLLVD.Z xmm xmm k xmm +// VPSLLVD.Z ymm ymm k ymm +// VPSLLVD.Z m512 zmm k zmm +// VPSLLVD.Z zmm zmm k zmm +// Construct and append a VPSLLVD.Z instruction to the active function. // Operates on the global context. -func SETLE(mr operand.Op) { ctx.SETLE(mr) } +func VPSLLVD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPSLLVD_Z(mxyz, xyz, k, xyz1) } -// SETLS: Set byte if below or equal (CF == 1 or ZF == 1). +// VPSLLVQ: Variable Shift Packed Quadword Data Left Logical. // // Forms: // -// SETLS r8 -// SETLS m8 -// Construct and append a SETLS instruction to the active function. -func (c *Context) SETLS(mr operand.Op) { - if inst, err := x86.SETLS(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSLLVQ m128 xmm xmm +// VPSLLVQ m256 ymm ymm +// VPSLLVQ xmm xmm xmm +// VPSLLVQ ymm ymm ymm +// VPSLLVQ m128 xmm k xmm +// VPSLLVQ m256 ymm k ymm +// VPSLLVQ xmm xmm k xmm +// VPSLLVQ ymm ymm k ymm +// VPSLLVQ m512 zmm k zmm +// VPSLLVQ m512 zmm zmm +// VPSLLVQ zmm zmm k zmm +// VPSLLVQ zmm zmm zmm +// Construct and append a VPSLLVQ instruction to the active function. +func (c *Context) VPSLLVQ(ops ...operand.Op) { + c.addinstruction(x86.VPSLLVQ(ops...)) } -// SETLS: Set byte if below or equal (CF == 1 or ZF == 1). +// VPSLLVQ: Variable Shift Packed Quadword Data Left Logical. // // Forms: // -// SETLS r8 -// SETLS m8 -// Construct and append a SETLS instruction to the active function. +// VPSLLVQ m128 xmm xmm +// VPSLLVQ m256 ymm ymm +// VPSLLVQ xmm xmm xmm +// VPSLLVQ ymm ymm ymm +// VPSLLVQ m128 xmm k xmm +// VPSLLVQ m256 ymm k ymm +// VPSLLVQ xmm xmm k xmm +// VPSLLVQ ymm ymm k ymm +// VPSLLVQ m512 zmm k zmm +// VPSLLVQ m512 zmm zmm +// VPSLLVQ zmm zmm k zmm +// VPSLLVQ zmm zmm zmm +// Construct and append a VPSLLVQ instruction to the active function. // Operates on the global context. -func SETLS(mr operand.Op) { ctx.SETLS(mr) } +func VPSLLVQ(ops ...operand.Op) { ctx.VPSLLVQ(ops...) } -// SETLT: Set byte if less (SF != OF). +// VPSLLVQ_BCST: Variable Shift Packed Quadword Data Left Logical (Broadcast). // // Forms: // -// SETLT r8 -// SETLT m8 -// Construct and append a SETLT instruction to the active function. -func (c *Context) SETLT(mr operand.Op) { - if inst, err := x86.SETLT(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSLLVQ.BCST m64 xmm k xmm +// VPSLLVQ.BCST m64 xmm xmm +// VPSLLVQ.BCST m64 ymm k ymm +// VPSLLVQ.BCST m64 ymm ymm +// VPSLLVQ.BCST m64 zmm k zmm +// VPSLLVQ.BCST m64 zmm zmm +// Construct and append a VPSLLVQ.BCST instruction to the active function. +func (c *Context) VPSLLVQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPSLLVQ_BCST(ops...)) } -// SETLT: Set byte if less (SF != OF). +// VPSLLVQ_BCST: Variable Shift Packed Quadword Data Left Logical (Broadcast). // // Forms: // -// SETLT r8 -// SETLT m8 -// Construct and append a SETLT instruction to the active function. +// VPSLLVQ.BCST m64 xmm k xmm +// VPSLLVQ.BCST m64 xmm xmm +// VPSLLVQ.BCST m64 ymm k ymm +// VPSLLVQ.BCST m64 ymm ymm +// VPSLLVQ.BCST m64 zmm k zmm +// VPSLLVQ.BCST m64 zmm zmm +// Construct and append a VPSLLVQ.BCST instruction to the active function. // Operates on the global context. -func SETLT(mr operand.Op) { ctx.SETLT(mr) } +func VPSLLVQ_BCST(ops ...operand.Op) { ctx.VPSLLVQ_BCST(ops...) } -// SETMI: Set byte if sign (SF == 1). +// VPSLLVQ_BCST_Z: Variable Shift Packed Quadword Data Left Logical (Broadcast, Zeroing Masking). // // Forms: // -// SETMI r8 -// SETMI m8 -// Construct and append a SETMI instruction to the active function. -func (c *Context) SETMI(mr operand.Op) { - if inst, err := x86.SETMI(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSLLVQ.BCST.Z m64 xmm k xmm +// VPSLLVQ.BCST.Z m64 ymm k ymm +// VPSLLVQ.BCST.Z m64 zmm k zmm +// Construct and append a VPSLLVQ.BCST.Z instruction to the active function. +func (c *Context) VPSLLVQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPSLLVQ_BCST_Z(m, xyz, k, xyz1)) } -// SETMI: Set byte if sign (SF == 1). +// VPSLLVQ_BCST_Z: Variable Shift Packed Quadword Data Left Logical (Broadcast, Zeroing Masking). // // Forms: // -// SETMI r8 -// SETMI m8 -// Construct and append a SETMI instruction to the active function. +// VPSLLVQ.BCST.Z m64 xmm k xmm +// VPSLLVQ.BCST.Z m64 ymm k ymm +// VPSLLVQ.BCST.Z m64 zmm k zmm +// Construct and append a VPSLLVQ.BCST.Z instruction to the active function. // Operates on the global context. -func SETMI(mr operand.Op) { ctx.SETMI(mr) } +func VPSLLVQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPSLLVQ_BCST_Z(m, xyz, k, xyz1) } -// SETNE: Set byte if not equal (ZF == 0). +// VPSLLVQ_Z: Variable Shift Packed Quadword Data Left Logical (Zeroing Masking). // // Forms: // -// SETNE r8 -// SETNE m8 -// Construct and append a SETNE instruction to the active function. -func (c *Context) SETNE(mr operand.Op) { - if inst, err := x86.SETNE(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSLLVQ.Z m128 xmm k xmm +// VPSLLVQ.Z m256 ymm k ymm +// VPSLLVQ.Z xmm xmm k xmm +// VPSLLVQ.Z ymm ymm k ymm +// VPSLLVQ.Z m512 zmm k zmm +// VPSLLVQ.Z zmm zmm k zmm +// Construct and append a VPSLLVQ.Z instruction to the active function. +func (c *Context) VPSLLVQ_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPSLLVQ_Z(mxyz, xyz, k, xyz1)) } -// SETNE: Set byte if not equal (ZF == 0). +// VPSLLVQ_Z: Variable Shift Packed Quadword Data Left Logical (Zeroing Masking). // // Forms: // -// SETNE r8 -// SETNE m8 -// Construct and append a SETNE instruction to the active function. +// VPSLLVQ.Z m128 xmm k xmm +// VPSLLVQ.Z m256 ymm k ymm +// VPSLLVQ.Z xmm xmm k xmm +// VPSLLVQ.Z ymm ymm k ymm +// VPSLLVQ.Z m512 zmm k zmm +// VPSLLVQ.Z zmm zmm k zmm +// Construct and append a VPSLLVQ.Z instruction to the active function. // Operates on the global context. -func SETNE(mr operand.Op) { ctx.SETNE(mr) } +func VPSLLVQ_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPSLLVQ_Z(mxyz, xyz, k, xyz1) } -// SETOC: Set byte if not overflow (OF == 0). +// VPSLLVW: Variable Shift Packed Word Data Left Logical. // // Forms: // -// SETOC r8 -// SETOC m8 -// Construct and append a SETOC instruction to the active function. -func (c *Context) SETOC(mr operand.Op) { - if inst, err := x86.SETOC(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSLLVW m128 xmm k xmm +// VPSLLVW m128 xmm xmm +// VPSLLVW m256 ymm k ymm +// VPSLLVW m256 ymm ymm +// VPSLLVW xmm xmm k xmm +// VPSLLVW xmm xmm xmm +// VPSLLVW ymm ymm k ymm +// VPSLLVW ymm ymm ymm +// VPSLLVW m512 zmm k zmm +// VPSLLVW m512 zmm zmm +// VPSLLVW zmm zmm k zmm +// VPSLLVW zmm zmm zmm +// Construct and append a VPSLLVW instruction to the active function. +func (c *Context) VPSLLVW(ops ...operand.Op) { + c.addinstruction(x86.VPSLLVW(ops...)) } -// SETOC: Set byte if not overflow (OF == 0). +// VPSLLVW: Variable Shift Packed Word Data Left Logical. // // Forms: // -// SETOC r8 -// SETOC m8 -// Construct and append a SETOC instruction to the active function. +// VPSLLVW m128 xmm k xmm +// VPSLLVW m128 xmm xmm +// VPSLLVW m256 ymm k ymm +// VPSLLVW m256 ymm ymm +// VPSLLVW xmm xmm k xmm +// VPSLLVW xmm xmm xmm +// VPSLLVW ymm ymm k ymm +// VPSLLVW ymm ymm ymm +// VPSLLVW m512 zmm k zmm +// VPSLLVW m512 zmm zmm +// VPSLLVW zmm zmm k zmm +// VPSLLVW zmm zmm zmm +// Construct and append a VPSLLVW instruction to the active function. // Operates on the global context. -func SETOC(mr operand.Op) { ctx.SETOC(mr) } +func VPSLLVW(ops ...operand.Op) { ctx.VPSLLVW(ops...) } -// SETOS: Set byte if overflow (OF == 1). +// VPSLLVW_Z: Variable Shift Packed Word Data Left Logical (Zeroing Masking). // // Forms: // -// SETOS r8 -// SETOS m8 -// Construct and append a SETOS instruction to the active function. -func (c *Context) SETOS(mr operand.Op) { - if inst, err := x86.SETOS(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSLLVW.Z m128 xmm k xmm +// VPSLLVW.Z m256 ymm k ymm +// VPSLLVW.Z xmm xmm k xmm +// VPSLLVW.Z ymm ymm k ymm +// VPSLLVW.Z m512 zmm k zmm +// VPSLLVW.Z zmm zmm k zmm +// Construct and append a VPSLLVW.Z instruction to the active function. +func (c *Context) VPSLLVW_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPSLLVW_Z(mxyz, xyz, k, xyz1)) } -// SETOS: Set byte if overflow (OF == 1). +// VPSLLVW_Z: Variable Shift Packed Word Data Left Logical (Zeroing Masking). // // Forms: // -// SETOS r8 -// SETOS m8 -// Construct and append a SETOS instruction to the active function. +// VPSLLVW.Z m128 xmm k xmm +// VPSLLVW.Z m256 ymm k ymm +// VPSLLVW.Z xmm xmm k xmm +// VPSLLVW.Z ymm ymm k ymm +// VPSLLVW.Z m512 zmm k zmm +// VPSLLVW.Z zmm zmm k zmm +// Construct and append a VPSLLVW.Z instruction to the active function. // Operates on the global context. -func SETOS(mr operand.Op) { ctx.SETOS(mr) } +func VPSLLVW_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPSLLVW_Z(mxyz, xyz, k, xyz1) } -// SETPC: Set byte if not parity (PF == 0). +// VPSLLW: Shift Packed Word Data Left Logical. // // Forms: // -// SETPC r8 -// SETPC m8 -// Construct and append a SETPC instruction to the active function. -func (c *Context) SETPC(mr operand.Op) { - if inst, err := x86.SETPC(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSLLW imm8 ymm ymm +// VPSLLW m128 ymm ymm +// VPSLLW xmm ymm ymm +// VPSLLW imm8 xmm xmm +// VPSLLW m128 xmm xmm +// VPSLLW xmm xmm xmm +// VPSLLW imm8 m128 k xmm +// VPSLLW imm8 m128 xmm +// VPSLLW imm8 m256 k ymm +// VPSLLW imm8 m256 ymm +// VPSLLW imm8 xmm k xmm +// VPSLLW imm8 ymm k ymm +// VPSLLW m128 xmm k xmm +// VPSLLW m128 ymm k ymm +// VPSLLW xmm xmm k xmm +// VPSLLW xmm ymm k ymm +// VPSLLW imm8 m512 k zmm +// VPSLLW imm8 m512 zmm +// VPSLLW imm8 zmm k zmm +// VPSLLW imm8 zmm zmm +// VPSLLW m128 zmm k zmm +// VPSLLW m128 zmm zmm +// VPSLLW xmm zmm k zmm +// VPSLLW xmm zmm zmm +// Construct and append a VPSLLW instruction to the active function. +func (c *Context) VPSLLW(ops ...operand.Op) { + c.addinstruction(x86.VPSLLW(ops...)) } -// SETPC: Set byte if not parity (PF == 0). +// VPSLLW: Shift Packed Word Data Left Logical. // // Forms: // -// SETPC r8 -// SETPC m8 -// Construct and append a SETPC instruction to the active function. +// VPSLLW imm8 ymm ymm +// VPSLLW m128 ymm ymm +// VPSLLW xmm ymm ymm +// VPSLLW imm8 xmm xmm +// VPSLLW m128 xmm xmm +// VPSLLW xmm xmm xmm +// VPSLLW imm8 m128 k xmm +// VPSLLW imm8 m128 xmm +// VPSLLW imm8 m256 k ymm +// VPSLLW imm8 m256 ymm +// VPSLLW imm8 xmm k xmm +// VPSLLW imm8 ymm k ymm +// VPSLLW m128 xmm k xmm +// VPSLLW m128 ymm k ymm +// VPSLLW xmm xmm k xmm +// VPSLLW xmm ymm k ymm +// VPSLLW imm8 m512 k zmm +// VPSLLW imm8 m512 zmm +// VPSLLW imm8 zmm k zmm +// VPSLLW imm8 zmm zmm +// VPSLLW m128 zmm k zmm +// VPSLLW m128 zmm zmm +// VPSLLW xmm zmm k zmm +// VPSLLW xmm zmm zmm +// Construct and append a VPSLLW instruction to the active function. // Operates on the global context. -func SETPC(mr operand.Op) { ctx.SETPC(mr) } +func VPSLLW(ops ...operand.Op) { ctx.VPSLLW(ops...) } -// SETPL: Set byte if not sign (SF == 0). +// VPSLLW_Z: Shift Packed Word Data Left Logical (Zeroing Masking). // // Forms: // -// SETPL r8 -// SETPL m8 -// Construct and append a SETPL instruction to the active function. -func (c *Context) SETPL(mr operand.Op) { - if inst, err := x86.SETPL(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSLLW.Z imm8 m128 k xmm +// VPSLLW.Z imm8 m256 k ymm +// VPSLLW.Z imm8 xmm k xmm +// VPSLLW.Z imm8 ymm k ymm +// VPSLLW.Z m128 xmm k xmm +// VPSLLW.Z m128 ymm k ymm +// VPSLLW.Z xmm xmm k xmm +// VPSLLW.Z xmm ymm k ymm +// VPSLLW.Z imm8 m512 k zmm +// VPSLLW.Z imm8 zmm k zmm +// VPSLLW.Z m128 zmm k zmm +// VPSLLW.Z xmm zmm k zmm +// Construct and append a VPSLLW.Z instruction to the active function. +func (c *Context) VPSLLW_Z(imx, mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPSLLW_Z(imx, mxyz, k, xyz)) } -// SETPL: Set byte if not sign (SF == 0). +// VPSLLW_Z: Shift Packed Word Data Left Logical (Zeroing Masking). // // Forms: // -// SETPL r8 -// SETPL m8 -// Construct and append a SETPL instruction to the active function. +// VPSLLW.Z imm8 m128 k xmm +// VPSLLW.Z imm8 m256 k ymm +// VPSLLW.Z imm8 xmm k xmm +// VPSLLW.Z imm8 ymm k ymm +// VPSLLW.Z m128 xmm k xmm +// VPSLLW.Z m128 ymm k ymm +// VPSLLW.Z xmm xmm k xmm +// VPSLLW.Z xmm ymm k ymm +// VPSLLW.Z imm8 m512 k zmm +// VPSLLW.Z imm8 zmm k zmm +// VPSLLW.Z m128 zmm k zmm +// VPSLLW.Z xmm zmm k zmm +// Construct and append a VPSLLW.Z instruction to the active function. // Operates on the global context. -func SETPL(mr operand.Op) { ctx.SETPL(mr) } +func VPSLLW_Z(imx, mxyz, k, xyz operand.Op) { ctx.VPSLLW_Z(imx, mxyz, k, xyz) } -// SETPS: Set byte if parity (PF == 1). +// VPSRAD: Shift Packed Doubleword Data Right Arithmetic. // // Forms: // -// SETPS r8 -// SETPS m8 -// Construct and append a SETPS instruction to the active function. -func (c *Context) SETPS(mr operand.Op) { - if inst, err := x86.SETPS(mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRAD imm8 ymm ymm +// VPSRAD m128 ymm ymm +// VPSRAD xmm ymm ymm +// VPSRAD imm8 xmm xmm +// VPSRAD m128 xmm xmm +// VPSRAD xmm xmm xmm +// VPSRAD imm8 m128 k xmm +// VPSRAD imm8 m128 xmm +// VPSRAD imm8 m256 k ymm +// VPSRAD imm8 m256 ymm +// VPSRAD imm8 xmm k xmm +// VPSRAD imm8 ymm k ymm +// VPSRAD m128 xmm k xmm +// VPSRAD m128 ymm k ymm +// VPSRAD xmm xmm k xmm +// VPSRAD xmm ymm k ymm +// VPSRAD imm8 m512 k zmm +// VPSRAD imm8 m512 zmm +// VPSRAD imm8 zmm k zmm +// VPSRAD imm8 zmm zmm +// VPSRAD m128 zmm k zmm +// VPSRAD m128 zmm zmm +// VPSRAD xmm zmm k zmm +// VPSRAD xmm zmm zmm +// Construct and append a VPSRAD instruction to the active function. +func (c *Context) VPSRAD(ops ...operand.Op) { + c.addinstruction(x86.VPSRAD(ops...)) } -// SETPS: Set byte if parity (PF == 1). +// VPSRAD: Shift Packed Doubleword Data Right Arithmetic. // // Forms: // -// SETPS r8 -// SETPS m8 -// Construct and append a SETPS instruction to the active function. +// VPSRAD imm8 ymm ymm +// VPSRAD m128 ymm ymm +// VPSRAD xmm ymm ymm +// VPSRAD imm8 xmm xmm +// VPSRAD m128 xmm xmm +// VPSRAD xmm xmm xmm +// VPSRAD imm8 m128 k xmm +// VPSRAD imm8 m128 xmm +// VPSRAD imm8 m256 k ymm +// VPSRAD imm8 m256 ymm +// VPSRAD imm8 xmm k xmm +// VPSRAD imm8 ymm k ymm +// VPSRAD m128 xmm k xmm +// VPSRAD m128 ymm k ymm +// VPSRAD xmm xmm k xmm +// VPSRAD xmm ymm k ymm +// VPSRAD imm8 m512 k zmm +// VPSRAD imm8 m512 zmm +// VPSRAD imm8 zmm k zmm +// VPSRAD imm8 zmm zmm +// VPSRAD m128 zmm k zmm +// VPSRAD m128 zmm zmm +// VPSRAD xmm zmm k zmm +// VPSRAD xmm zmm zmm +// Construct and append a VPSRAD instruction to the active function. // Operates on the global context. -func SETPS(mr operand.Op) { ctx.SETPS(mr) } +func VPSRAD(ops ...operand.Op) { ctx.VPSRAD(ops...) } -// SFENCE: Store Fence. +// VPSRAD_BCST: Shift Packed Doubleword Data Right Arithmetic (Broadcast). // // Forms: // -// SFENCE -// Construct and append a SFENCE instruction to the active function. -func (c *Context) SFENCE() { - if inst, err := x86.SFENCE(); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRAD.BCST imm8 m32 k xmm +// VPSRAD.BCST imm8 m32 k ymm +// VPSRAD.BCST imm8 m32 xmm +// VPSRAD.BCST imm8 m32 ymm +// VPSRAD.BCST imm8 m32 k zmm +// VPSRAD.BCST imm8 m32 zmm +// Construct and append a VPSRAD.BCST instruction to the active function. +func (c *Context) VPSRAD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPSRAD_BCST(ops...)) } -// SFENCE: Store Fence. +// VPSRAD_BCST: Shift Packed Doubleword Data Right Arithmetic (Broadcast). // // Forms: // -// SFENCE -// Construct and append a SFENCE instruction to the active function. +// VPSRAD.BCST imm8 m32 k xmm +// VPSRAD.BCST imm8 m32 k ymm +// VPSRAD.BCST imm8 m32 xmm +// VPSRAD.BCST imm8 m32 ymm +// VPSRAD.BCST imm8 m32 k zmm +// VPSRAD.BCST imm8 m32 zmm +// Construct and append a VPSRAD.BCST instruction to the active function. // Operates on the global context. -func SFENCE() { ctx.SFENCE() } +func VPSRAD_BCST(ops ...operand.Op) { ctx.VPSRAD_BCST(ops...) } -// SHA1MSG1: Perform an Intermediate Calculation for the Next Four SHA1 Message Doublewords. +// VPSRAD_BCST_Z: Shift Packed Doubleword Data Right Arithmetic (Broadcast, Zeroing Masking). // // Forms: // -// SHA1MSG1 xmm xmm -// SHA1MSG1 m128 xmm -// Construct and append a SHA1MSG1 instruction to the active function. -func (c *Context) SHA1MSG1(mx, x operand.Op) { - if inst, err := x86.SHA1MSG1(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRAD.BCST.Z imm8 m32 k xmm +// VPSRAD.BCST.Z imm8 m32 k ymm +// VPSRAD.BCST.Z imm8 m32 k zmm +// Construct and append a VPSRAD.BCST.Z instruction to the active function. +func (c *Context) VPSRAD_BCST_Z(i, m, k, xyz operand.Op) { + c.addinstruction(x86.VPSRAD_BCST_Z(i, m, k, xyz)) } -// SHA1MSG1: Perform an Intermediate Calculation for the Next Four SHA1 Message Doublewords. +// VPSRAD_BCST_Z: Shift Packed Doubleword Data Right Arithmetic (Broadcast, Zeroing Masking). // // Forms: // -// SHA1MSG1 xmm xmm -// SHA1MSG1 m128 xmm -// Construct and append a SHA1MSG1 instruction to the active function. +// VPSRAD.BCST.Z imm8 m32 k xmm +// VPSRAD.BCST.Z imm8 m32 k ymm +// VPSRAD.BCST.Z imm8 m32 k zmm +// Construct and append a VPSRAD.BCST.Z instruction to the active function. // Operates on the global context. -func SHA1MSG1(mx, x operand.Op) { ctx.SHA1MSG1(mx, x) } +func VPSRAD_BCST_Z(i, m, k, xyz operand.Op) { ctx.VPSRAD_BCST_Z(i, m, k, xyz) } -// SHA1MSG2: Perform a Final Calculation for the Next Four SHA1 Message Doublewords. +// VPSRAD_Z: Shift Packed Doubleword Data Right Arithmetic (Zeroing Masking). // // Forms: // -// SHA1MSG2 xmm xmm -// SHA1MSG2 m128 xmm -// Construct and append a SHA1MSG2 instruction to the active function. -func (c *Context) SHA1MSG2(mx, x operand.Op) { - if inst, err := x86.SHA1MSG2(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRAD.Z imm8 m128 k xmm +// VPSRAD.Z imm8 m256 k ymm +// VPSRAD.Z imm8 xmm k xmm +// VPSRAD.Z imm8 ymm k ymm +// VPSRAD.Z m128 xmm k xmm +// VPSRAD.Z m128 ymm k ymm +// VPSRAD.Z xmm xmm k xmm +// VPSRAD.Z xmm ymm k ymm +// VPSRAD.Z imm8 m512 k zmm +// VPSRAD.Z imm8 zmm k zmm +// VPSRAD.Z m128 zmm k zmm +// VPSRAD.Z xmm zmm k zmm +// Construct and append a VPSRAD.Z instruction to the active function. +func (c *Context) VPSRAD_Z(imx, mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPSRAD_Z(imx, mxyz, k, xyz)) } -// SHA1MSG2: Perform a Final Calculation for the Next Four SHA1 Message Doublewords. +// VPSRAD_Z: Shift Packed Doubleword Data Right Arithmetic (Zeroing Masking). // // Forms: // -// SHA1MSG2 xmm xmm -// SHA1MSG2 m128 xmm -// Construct and append a SHA1MSG2 instruction to the active function. +// VPSRAD.Z imm8 m128 k xmm +// VPSRAD.Z imm8 m256 k ymm +// VPSRAD.Z imm8 xmm k xmm +// VPSRAD.Z imm8 ymm k ymm +// VPSRAD.Z m128 xmm k xmm +// VPSRAD.Z m128 ymm k ymm +// VPSRAD.Z xmm xmm k xmm +// VPSRAD.Z xmm ymm k ymm +// VPSRAD.Z imm8 m512 k zmm +// VPSRAD.Z imm8 zmm k zmm +// VPSRAD.Z m128 zmm k zmm +// VPSRAD.Z xmm zmm k zmm +// Construct and append a VPSRAD.Z instruction to the active function. // Operates on the global context. -func SHA1MSG2(mx, x operand.Op) { ctx.SHA1MSG2(mx, x) } +func VPSRAD_Z(imx, mxyz, k, xyz operand.Op) { ctx.VPSRAD_Z(imx, mxyz, k, xyz) } -// SHA1NEXTE: Calculate SHA1 State Variable E after Four Rounds. +// VPSRAQ: Shift Packed Quadword Data Right Arithmetic. // // Forms: // -// SHA1NEXTE xmm xmm -// SHA1NEXTE m128 xmm -// Construct and append a SHA1NEXTE instruction to the active function. -func (c *Context) SHA1NEXTE(mx, x operand.Op) { - if inst, err := x86.SHA1NEXTE(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRAQ imm8 m128 k xmm +// VPSRAQ imm8 m128 xmm +// VPSRAQ imm8 m256 k ymm +// VPSRAQ imm8 m256 ymm +// VPSRAQ imm8 xmm k xmm +// VPSRAQ imm8 xmm xmm +// VPSRAQ imm8 ymm k ymm +// VPSRAQ imm8 ymm ymm +// VPSRAQ m128 xmm k xmm +// VPSRAQ m128 xmm xmm +// VPSRAQ m128 ymm k ymm +// VPSRAQ m128 ymm ymm +// VPSRAQ xmm xmm k xmm +// VPSRAQ xmm xmm xmm +// VPSRAQ xmm ymm k ymm +// VPSRAQ xmm ymm ymm +// VPSRAQ imm8 m512 k zmm +// VPSRAQ imm8 m512 zmm +// VPSRAQ imm8 zmm k zmm +// VPSRAQ imm8 zmm zmm +// VPSRAQ m128 zmm k zmm +// VPSRAQ m128 zmm zmm +// VPSRAQ xmm zmm k zmm +// VPSRAQ xmm zmm zmm +// Construct and append a VPSRAQ instruction to the active function. +func (c *Context) VPSRAQ(ops ...operand.Op) { + c.addinstruction(x86.VPSRAQ(ops...)) } -// SHA1NEXTE: Calculate SHA1 State Variable E after Four Rounds. +// VPSRAQ: Shift Packed Quadword Data Right Arithmetic. // // Forms: // -// SHA1NEXTE xmm xmm -// SHA1NEXTE m128 xmm -// Construct and append a SHA1NEXTE instruction to the active function. -// Operates on the global context. -func SHA1NEXTE(mx, x operand.Op) { ctx.SHA1NEXTE(mx, x) } - -// SHA1RNDS4: Perform Four Rounds of SHA1 Operation. -// +// VPSRAQ imm8 m128 k xmm +// VPSRAQ imm8 m128 xmm +// VPSRAQ imm8 m256 k ymm +// VPSRAQ imm8 m256 ymm +// VPSRAQ imm8 xmm k xmm +// VPSRAQ imm8 xmm xmm +// VPSRAQ imm8 ymm k ymm +// VPSRAQ imm8 ymm ymm +// VPSRAQ m128 xmm k xmm +// VPSRAQ m128 xmm xmm +// VPSRAQ m128 ymm k ymm +// VPSRAQ m128 ymm ymm +// VPSRAQ xmm xmm k xmm +// VPSRAQ xmm xmm xmm +// VPSRAQ xmm ymm k ymm +// VPSRAQ xmm ymm ymm +// VPSRAQ imm8 m512 k zmm +// VPSRAQ imm8 m512 zmm +// VPSRAQ imm8 zmm k zmm +// VPSRAQ imm8 zmm zmm +// VPSRAQ m128 zmm k zmm +// VPSRAQ m128 zmm zmm +// VPSRAQ xmm zmm k zmm +// VPSRAQ xmm zmm zmm +// Construct and append a VPSRAQ instruction to the active function. +// Operates on the global context. +func VPSRAQ(ops ...operand.Op) { ctx.VPSRAQ(ops...) } + +// VPSRAQ_BCST: Shift Packed Quadword Data Right Arithmetic (Broadcast). +// // Forms: // -// SHA1RNDS4 imm2u xmm xmm -// SHA1RNDS4 imm2u m128 xmm -// Construct and append a SHA1RNDS4 instruction to the active function. -func (c *Context) SHA1RNDS4(i, mx, x operand.Op) { - if inst, err := x86.SHA1RNDS4(i, mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRAQ.BCST imm8 m64 k xmm +// VPSRAQ.BCST imm8 m64 k ymm +// VPSRAQ.BCST imm8 m64 xmm +// VPSRAQ.BCST imm8 m64 ymm +// VPSRAQ.BCST imm8 m64 k zmm +// VPSRAQ.BCST imm8 m64 zmm +// Construct and append a VPSRAQ.BCST instruction to the active function. +func (c *Context) VPSRAQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPSRAQ_BCST(ops...)) } -// SHA1RNDS4: Perform Four Rounds of SHA1 Operation. +// VPSRAQ_BCST: Shift Packed Quadword Data Right Arithmetic (Broadcast). // // Forms: // -// SHA1RNDS4 imm2u xmm xmm -// SHA1RNDS4 imm2u m128 xmm -// Construct and append a SHA1RNDS4 instruction to the active function. +// VPSRAQ.BCST imm8 m64 k xmm +// VPSRAQ.BCST imm8 m64 k ymm +// VPSRAQ.BCST imm8 m64 xmm +// VPSRAQ.BCST imm8 m64 ymm +// VPSRAQ.BCST imm8 m64 k zmm +// VPSRAQ.BCST imm8 m64 zmm +// Construct and append a VPSRAQ.BCST instruction to the active function. // Operates on the global context. -func SHA1RNDS4(i, mx, x operand.Op) { ctx.SHA1RNDS4(i, mx, x) } +func VPSRAQ_BCST(ops ...operand.Op) { ctx.VPSRAQ_BCST(ops...) } -// SHA256MSG1: Perform an Intermediate Calculation for the Next Four SHA256 Message Doublewords. +// VPSRAQ_BCST_Z: Shift Packed Quadword Data Right Arithmetic (Broadcast, Zeroing Masking). // // Forms: // -// SHA256MSG1 xmm xmm -// SHA256MSG1 m128 xmm -// Construct and append a SHA256MSG1 instruction to the active function. -func (c *Context) SHA256MSG1(mx, x operand.Op) { - if inst, err := x86.SHA256MSG1(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } -} - -// SHA256MSG1: Perform an Intermediate Calculation for the Next Four SHA256 Message Doublewords. +// VPSRAQ.BCST.Z imm8 m64 k xmm +// VPSRAQ.BCST.Z imm8 m64 k ymm +// VPSRAQ.BCST.Z imm8 m64 k zmm +// Construct and append a VPSRAQ.BCST.Z instruction to the active function. +func (c *Context) VPSRAQ_BCST_Z(i, m, k, xyz operand.Op) { + c.addinstruction(x86.VPSRAQ_BCST_Z(i, m, k, xyz)) +} + +// VPSRAQ_BCST_Z: Shift Packed Quadword Data Right Arithmetic (Broadcast, Zeroing Masking). // // Forms: // -// SHA256MSG1 xmm xmm -// SHA256MSG1 m128 xmm -// Construct and append a SHA256MSG1 instruction to the active function. +// VPSRAQ.BCST.Z imm8 m64 k xmm +// VPSRAQ.BCST.Z imm8 m64 k ymm +// VPSRAQ.BCST.Z imm8 m64 k zmm +// Construct and append a VPSRAQ.BCST.Z instruction to the active function. // Operates on the global context. -func SHA256MSG1(mx, x operand.Op) { ctx.SHA256MSG1(mx, x) } +func VPSRAQ_BCST_Z(i, m, k, xyz operand.Op) { ctx.VPSRAQ_BCST_Z(i, m, k, xyz) } -// SHA256MSG2: Perform a Final Calculation for the Next Four SHA256 Message Doublewords. +// VPSRAQ_Z: Shift Packed Quadword Data Right Arithmetic (Zeroing Masking). // // Forms: // -// SHA256MSG2 xmm xmm -// SHA256MSG2 m128 xmm -// Construct and append a SHA256MSG2 instruction to the active function. -func (c *Context) SHA256MSG2(mx, x operand.Op) { - if inst, err := x86.SHA256MSG2(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRAQ.Z imm8 m128 k xmm +// VPSRAQ.Z imm8 m256 k ymm +// VPSRAQ.Z imm8 xmm k xmm +// VPSRAQ.Z imm8 ymm k ymm +// VPSRAQ.Z m128 xmm k xmm +// VPSRAQ.Z m128 ymm k ymm +// VPSRAQ.Z xmm xmm k xmm +// VPSRAQ.Z xmm ymm k ymm +// VPSRAQ.Z imm8 m512 k zmm +// VPSRAQ.Z imm8 zmm k zmm +// VPSRAQ.Z m128 zmm k zmm +// VPSRAQ.Z xmm zmm k zmm +// Construct and append a VPSRAQ.Z instruction to the active function. +func (c *Context) VPSRAQ_Z(imx, mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPSRAQ_Z(imx, mxyz, k, xyz)) } -// SHA256MSG2: Perform a Final Calculation for the Next Four SHA256 Message Doublewords. +// VPSRAQ_Z: Shift Packed Quadword Data Right Arithmetic (Zeroing Masking). // // Forms: // -// SHA256MSG2 xmm xmm -// SHA256MSG2 m128 xmm -// Construct and append a SHA256MSG2 instruction to the active function. +// VPSRAQ.Z imm8 m128 k xmm +// VPSRAQ.Z imm8 m256 k ymm +// VPSRAQ.Z imm8 xmm k xmm +// VPSRAQ.Z imm8 ymm k ymm +// VPSRAQ.Z m128 xmm k xmm +// VPSRAQ.Z m128 ymm k ymm +// VPSRAQ.Z xmm xmm k xmm +// VPSRAQ.Z xmm ymm k ymm +// VPSRAQ.Z imm8 m512 k zmm +// VPSRAQ.Z imm8 zmm k zmm +// VPSRAQ.Z m128 zmm k zmm +// VPSRAQ.Z xmm zmm k zmm +// Construct and append a VPSRAQ.Z instruction to the active function. // Operates on the global context. -func SHA256MSG2(mx, x operand.Op) { ctx.SHA256MSG2(mx, x) } +func VPSRAQ_Z(imx, mxyz, k, xyz operand.Op) { ctx.VPSRAQ_Z(imx, mxyz, k, xyz) } -// SHA256RNDS2: Perform Two Rounds of SHA256 Operation. +// VPSRAVD: Variable Shift Packed Doubleword Data Right Arithmetic. // // Forms: // -// SHA256RNDS2 xmm0 xmm xmm -// SHA256RNDS2 xmm0 m128 xmm -// Construct and append a SHA256RNDS2 instruction to the active function. -func (c *Context) SHA256RNDS2(x, mx, x1 operand.Op) { - if inst, err := x86.SHA256RNDS2(x, mx, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRAVD m128 xmm xmm +// VPSRAVD m256 ymm ymm +// VPSRAVD xmm xmm xmm +// VPSRAVD ymm ymm ymm +// VPSRAVD m128 xmm k xmm +// VPSRAVD m256 ymm k ymm +// VPSRAVD xmm xmm k xmm +// VPSRAVD ymm ymm k ymm +// VPSRAVD m512 zmm k zmm +// VPSRAVD m512 zmm zmm +// VPSRAVD zmm zmm k zmm +// VPSRAVD zmm zmm zmm +// Construct and append a VPSRAVD instruction to the active function. +func (c *Context) VPSRAVD(ops ...operand.Op) { + c.addinstruction(x86.VPSRAVD(ops...)) } -// SHA256RNDS2: Perform Two Rounds of SHA256 Operation. +// VPSRAVD: Variable Shift Packed Doubleword Data Right Arithmetic. // // Forms: // -// SHA256RNDS2 xmm0 xmm xmm -// SHA256RNDS2 xmm0 m128 xmm -// Construct and append a SHA256RNDS2 instruction to the active function. +// VPSRAVD m128 xmm xmm +// VPSRAVD m256 ymm ymm +// VPSRAVD xmm xmm xmm +// VPSRAVD ymm ymm ymm +// VPSRAVD m128 xmm k xmm +// VPSRAVD m256 ymm k ymm +// VPSRAVD xmm xmm k xmm +// VPSRAVD ymm ymm k ymm +// VPSRAVD m512 zmm k zmm +// VPSRAVD m512 zmm zmm +// VPSRAVD zmm zmm k zmm +// VPSRAVD zmm zmm zmm +// Construct and append a VPSRAVD instruction to the active function. // Operates on the global context. -func SHA256RNDS2(x, mx, x1 operand.Op) { ctx.SHA256RNDS2(x, mx, x1) } +func VPSRAVD(ops ...operand.Op) { ctx.VPSRAVD(ops...) } -// SHLB: Logical Shift Left. +// VPSRAVD_BCST: Variable Shift Packed Doubleword Data Right Arithmetic (Broadcast). // // Forms: // -// SHLB 1 r8 -// SHLB imm8 r8 -// SHLB cl r8 -// SHLB 1 m8 -// SHLB imm8 m8 -// SHLB cl m8 -// Construct and append a SHLB instruction to the active function. -func (c *Context) SHLB(ci, mr operand.Op) { - if inst, err := x86.SHLB(ci, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRAVD.BCST m32 xmm k xmm +// VPSRAVD.BCST m32 xmm xmm +// VPSRAVD.BCST m32 ymm k ymm +// VPSRAVD.BCST m32 ymm ymm +// VPSRAVD.BCST m32 zmm k zmm +// VPSRAVD.BCST m32 zmm zmm +// Construct and append a VPSRAVD.BCST instruction to the active function. +func (c *Context) VPSRAVD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPSRAVD_BCST(ops...)) } -// SHLB: Logical Shift Left. +// VPSRAVD_BCST: Variable Shift Packed Doubleword Data Right Arithmetic (Broadcast). // // Forms: // -// SHLB 1 r8 -// SHLB imm8 r8 -// SHLB cl r8 -// SHLB 1 m8 -// SHLB imm8 m8 -// SHLB cl m8 -// Construct and append a SHLB instruction to the active function. +// VPSRAVD.BCST m32 xmm k xmm +// VPSRAVD.BCST m32 xmm xmm +// VPSRAVD.BCST m32 ymm k ymm +// VPSRAVD.BCST m32 ymm ymm +// VPSRAVD.BCST m32 zmm k zmm +// VPSRAVD.BCST m32 zmm zmm +// Construct and append a VPSRAVD.BCST instruction to the active function. // Operates on the global context. -func SHLB(ci, mr operand.Op) { ctx.SHLB(ci, mr) } +func VPSRAVD_BCST(ops ...operand.Op) { ctx.VPSRAVD_BCST(ops...) } -// SHLL: Logical Shift Left. +// VPSRAVD_BCST_Z: Variable Shift Packed Doubleword Data Right Arithmetic (Broadcast, Zeroing Masking). // // Forms: // -// SHLL 1 r32 -// SHLL imm8 r32 -// SHLL cl r32 -// SHLL 1 m32 -// SHLL imm8 m32 -// SHLL cl m32 -// SHLL imm8 r32 r32 -// SHLL cl r32 r32 -// SHLL imm8 r32 m32 -// SHLL cl r32 m32 -// Construct and append a SHLL instruction to the active function. -func (c *Context) SHLL(ops ...operand.Op) { - if inst, err := x86.SHLL(ops...); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRAVD.BCST.Z m32 xmm k xmm +// VPSRAVD.BCST.Z m32 ymm k ymm +// VPSRAVD.BCST.Z m32 zmm k zmm +// Construct and append a VPSRAVD.BCST.Z instruction to the active function. +func (c *Context) VPSRAVD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPSRAVD_BCST_Z(m, xyz, k, xyz1)) } -// SHLL: Logical Shift Left. +// VPSRAVD_BCST_Z: Variable Shift Packed Doubleword Data Right Arithmetic (Broadcast, Zeroing Masking). // // Forms: // -// SHLL 1 r32 -// SHLL imm8 r32 -// SHLL cl r32 -// SHLL 1 m32 -// SHLL imm8 m32 -// SHLL cl m32 -// SHLL imm8 r32 r32 -// SHLL cl r32 r32 -// SHLL imm8 r32 m32 -// SHLL cl r32 m32 -// Construct and append a SHLL instruction to the active function. +// VPSRAVD.BCST.Z m32 xmm k xmm +// VPSRAVD.BCST.Z m32 ymm k ymm +// VPSRAVD.BCST.Z m32 zmm k zmm +// Construct and append a VPSRAVD.BCST.Z instruction to the active function. // Operates on the global context. -func SHLL(ops ...operand.Op) { ctx.SHLL(ops...) } +func VPSRAVD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPSRAVD_BCST_Z(m, xyz, k, xyz1) } -// SHLQ: Logical Shift Left. +// VPSRAVD_Z: Variable Shift Packed Doubleword Data Right Arithmetic (Zeroing Masking). // // Forms: // -// SHLQ 1 r64 -// SHLQ imm8 r64 -// SHLQ cl r64 -// SHLQ 1 m64 -// SHLQ imm8 m64 -// SHLQ cl m64 -// SHLQ imm8 r64 r64 -// SHLQ cl r64 r64 -// SHLQ imm8 r64 m64 -// SHLQ cl r64 m64 -// Construct and append a SHLQ instruction to the active function. -func (c *Context) SHLQ(ops ...operand.Op) { - if inst, err := x86.SHLQ(ops...); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRAVD.Z m128 xmm k xmm +// VPSRAVD.Z m256 ymm k ymm +// VPSRAVD.Z xmm xmm k xmm +// VPSRAVD.Z ymm ymm k ymm +// VPSRAVD.Z m512 zmm k zmm +// VPSRAVD.Z zmm zmm k zmm +// Construct and append a VPSRAVD.Z instruction to the active function. +func (c *Context) VPSRAVD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPSRAVD_Z(mxyz, xyz, k, xyz1)) } -// SHLQ: Logical Shift Left. +// VPSRAVD_Z: Variable Shift Packed Doubleword Data Right Arithmetic (Zeroing Masking). // // Forms: // -// SHLQ 1 r64 -// SHLQ imm8 r64 -// SHLQ cl r64 -// SHLQ 1 m64 -// SHLQ imm8 m64 -// SHLQ cl m64 -// SHLQ imm8 r64 r64 -// SHLQ cl r64 r64 -// SHLQ imm8 r64 m64 -// SHLQ cl r64 m64 -// Construct and append a SHLQ instruction to the active function. +// VPSRAVD.Z m128 xmm k xmm +// VPSRAVD.Z m256 ymm k ymm +// VPSRAVD.Z xmm xmm k xmm +// VPSRAVD.Z ymm ymm k ymm +// VPSRAVD.Z m512 zmm k zmm +// VPSRAVD.Z zmm zmm k zmm +// Construct and append a VPSRAVD.Z instruction to the active function. // Operates on the global context. -func SHLQ(ops ...operand.Op) { ctx.SHLQ(ops...) } +func VPSRAVD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPSRAVD_Z(mxyz, xyz, k, xyz1) } -// SHLW: Logical Shift Left. +// VPSRAVQ: Variable Shift Packed Quadword Data Right Arithmetic. // // Forms: // -// SHLW 1 r16 -// SHLW imm8 r16 -// SHLW cl r16 -// SHLW 1 m16 -// SHLW imm8 m16 -// SHLW cl m16 -// SHLW imm8 r16 r16 -// SHLW cl r16 r16 -// SHLW imm8 r16 m16 -// SHLW cl r16 m16 -// Construct and append a SHLW instruction to the active function. -func (c *Context) SHLW(ops ...operand.Op) { - if inst, err := x86.SHLW(ops...); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRAVQ m128 xmm k xmm +// VPSRAVQ m128 xmm xmm +// VPSRAVQ m256 ymm k ymm +// VPSRAVQ m256 ymm ymm +// VPSRAVQ xmm xmm k xmm +// VPSRAVQ xmm xmm xmm +// VPSRAVQ ymm ymm k ymm +// VPSRAVQ ymm ymm ymm +// VPSRAVQ m512 zmm k zmm +// VPSRAVQ m512 zmm zmm +// VPSRAVQ zmm zmm k zmm +// VPSRAVQ zmm zmm zmm +// Construct and append a VPSRAVQ instruction to the active function. +func (c *Context) VPSRAVQ(ops ...operand.Op) { + c.addinstruction(x86.VPSRAVQ(ops...)) } -// SHLW: Logical Shift Left. +// VPSRAVQ: Variable Shift Packed Quadword Data Right Arithmetic. // // Forms: // -// SHLW 1 r16 -// SHLW imm8 r16 -// SHLW cl r16 -// SHLW 1 m16 -// SHLW imm8 m16 -// SHLW cl m16 -// SHLW imm8 r16 r16 -// SHLW cl r16 r16 -// SHLW imm8 r16 m16 -// SHLW cl r16 m16 -// Construct and append a SHLW instruction to the active function. +// VPSRAVQ m128 xmm k xmm +// VPSRAVQ m128 xmm xmm +// VPSRAVQ m256 ymm k ymm +// VPSRAVQ m256 ymm ymm +// VPSRAVQ xmm xmm k xmm +// VPSRAVQ xmm xmm xmm +// VPSRAVQ ymm ymm k ymm +// VPSRAVQ ymm ymm ymm +// VPSRAVQ m512 zmm k zmm +// VPSRAVQ m512 zmm zmm +// VPSRAVQ zmm zmm k zmm +// VPSRAVQ zmm zmm zmm +// Construct and append a VPSRAVQ instruction to the active function. // Operates on the global context. -func SHLW(ops ...operand.Op) { ctx.SHLW(ops...) } +func VPSRAVQ(ops ...operand.Op) { ctx.VPSRAVQ(ops...) } -// SHLXL: Logical Shift Left Without Affecting Flags. +// VPSRAVQ_BCST: Variable Shift Packed Quadword Data Right Arithmetic (Broadcast). // // Forms: // -// SHLXL r32 r32 r32 -// SHLXL r32 m32 r32 -// Construct and append a SHLXL instruction to the active function. -func (c *Context) SHLXL(r, mr, r1 operand.Op) { - if inst, err := x86.SHLXL(r, mr, r1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRAVQ.BCST m64 xmm k xmm +// VPSRAVQ.BCST m64 xmm xmm +// VPSRAVQ.BCST m64 ymm k ymm +// VPSRAVQ.BCST m64 ymm ymm +// VPSRAVQ.BCST m64 zmm k zmm +// VPSRAVQ.BCST m64 zmm zmm +// Construct and append a VPSRAVQ.BCST instruction to the active function. +func (c *Context) VPSRAVQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPSRAVQ_BCST(ops...)) } -// SHLXL: Logical Shift Left Without Affecting Flags. +// VPSRAVQ_BCST: Variable Shift Packed Quadword Data Right Arithmetic (Broadcast). // // Forms: // -// SHLXL r32 r32 r32 -// SHLXL r32 m32 r32 -// Construct and append a SHLXL instruction to the active function. +// VPSRAVQ.BCST m64 xmm k xmm +// VPSRAVQ.BCST m64 xmm xmm +// VPSRAVQ.BCST m64 ymm k ymm +// VPSRAVQ.BCST m64 ymm ymm +// VPSRAVQ.BCST m64 zmm k zmm +// VPSRAVQ.BCST m64 zmm zmm +// Construct and append a VPSRAVQ.BCST instruction to the active function. // Operates on the global context. -func SHLXL(r, mr, r1 operand.Op) { ctx.SHLXL(r, mr, r1) } +func VPSRAVQ_BCST(ops ...operand.Op) { ctx.VPSRAVQ_BCST(ops...) } -// SHLXQ: Logical Shift Left Without Affecting Flags. +// VPSRAVQ_BCST_Z: Variable Shift Packed Quadword Data Right Arithmetic (Broadcast, Zeroing Masking). // // Forms: // -// SHLXQ r64 r64 r64 -// SHLXQ r64 m64 r64 -// Construct and append a SHLXQ instruction to the active function. -func (c *Context) SHLXQ(r, mr, r1 operand.Op) { - if inst, err := x86.SHLXQ(r, mr, r1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRAVQ.BCST.Z m64 xmm k xmm +// VPSRAVQ.BCST.Z m64 ymm k ymm +// VPSRAVQ.BCST.Z m64 zmm k zmm +// Construct and append a VPSRAVQ.BCST.Z instruction to the active function. +func (c *Context) VPSRAVQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPSRAVQ_BCST_Z(m, xyz, k, xyz1)) } -// SHLXQ: Logical Shift Left Without Affecting Flags. +// VPSRAVQ_BCST_Z: Variable Shift Packed Quadword Data Right Arithmetic (Broadcast, Zeroing Masking). // // Forms: // -// SHLXQ r64 r64 r64 -// SHLXQ r64 m64 r64 -// Construct and append a SHLXQ instruction to the active function. +// VPSRAVQ.BCST.Z m64 xmm k xmm +// VPSRAVQ.BCST.Z m64 ymm k ymm +// VPSRAVQ.BCST.Z m64 zmm k zmm +// Construct and append a VPSRAVQ.BCST.Z instruction to the active function. // Operates on the global context. -func SHLXQ(r, mr, r1 operand.Op) { ctx.SHLXQ(r, mr, r1) } +func VPSRAVQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPSRAVQ_BCST_Z(m, xyz, k, xyz1) } -// SHRB: Logical Shift Right. +// VPSRAVQ_Z: Variable Shift Packed Quadword Data Right Arithmetic (Zeroing Masking). // // Forms: // -// SHRB 1 r8 -// SHRB imm8 r8 -// SHRB cl r8 -// SHRB 1 m8 -// SHRB imm8 m8 -// SHRB cl m8 -// Construct and append a SHRB instruction to the active function. -func (c *Context) SHRB(ci, mr operand.Op) { - if inst, err := x86.SHRB(ci, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRAVQ.Z m128 xmm k xmm +// VPSRAVQ.Z m256 ymm k ymm +// VPSRAVQ.Z xmm xmm k xmm +// VPSRAVQ.Z ymm ymm k ymm +// VPSRAVQ.Z m512 zmm k zmm +// VPSRAVQ.Z zmm zmm k zmm +// Construct and append a VPSRAVQ.Z instruction to the active function. +func (c *Context) VPSRAVQ_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPSRAVQ_Z(mxyz, xyz, k, xyz1)) } -// SHRB: Logical Shift Right. +// VPSRAVQ_Z: Variable Shift Packed Quadword Data Right Arithmetic (Zeroing Masking). // // Forms: // -// SHRB 1 r8 -// SHRB imm8 r8 -// SHRB cl r8 -// SHRB 1 m8 -// SHRB imm8 m8 -// SHRB cl m8 -// Construct and append a SHRB instruction to the active function. +// VPSRAVQ.Z m128 xmm k xmm +// VPSRAVQ.Z m256 ymm k ymm +// VPSRAVQ.Z xmm xmm k xmm +// VPSRAVQ.Z ymm ymm k ymm +// VPSRAVQ.Z m512 zmm k zmm +// VPSRAVQ.Z zmm zmm k zmm +// Construct and append a VPSRAVQ.Z instruction to the active function. // Operates on the global context. -func SHRB(ci, mr operand.Op) { ctx.SHRB(ci, mr) } +func VPSRAVQ_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPSRAVQ_Z(mxyz, xyz, k, xyz1) } -// SHRL: Logical Shift Right. +// VPSRAVW: Variable Shift Packed Word Data Right Arithmetic. // // Forms: // -// SHRL 1 r32 -// SHRL imm8 r32 -// SHRL cl r32 -// SHRL 1 m32 -// SHRL imm8 m32 -// SHRL cl m32 -// SHRL imm8 r32 r32 -// SHRL cl r32 r32 -// SHRL imm8 r32 m32 -// SHRL cl r32 m32 -// Construct and append a SHRL instruction to the active function. -func (c *Context) SHRL(ops ...operand.Op) { - if inst, err := x86.SHRL(ops...); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRAVW m128 xmm k xmm +// VPSRAVW m128 xmm xmm +// VPSRAVW m256 ymm k ymm +// VPSRAVW m256 ymm ymm +// VPSRAVW xmm xmm k xmm +// VPSRAVW xmm xmm xmm +// VPSRAVW ymm ymm k ymm +// VPSRAVW ymm ymm ymm +// VPSRAVW m512 zmm k zmm +// VPSRAVW m512 zmm zmm +// VPSRAVW zmm zmm k zmm +// VPSRAVW zmm zmm zmm +// Construct and append a VPSRAVW instruction to the active function. +func (c *Context) VPSRAVW(ops ...operand.Op) { + c.addinstruction(x86.VPSRAVW(ops...)) } -// SHRL: Logical Shift Right. +// VPSRAVW: Variable Shift Packed Word Data Right Arithmetic. // // Forms: // -// SHRL 1 r32 -// SHRL imm8 r32 -// SHRL cl r32 -// SHRL 1 m32 -// SHRL imm8 m32 -// SHRL cl m32 -// SHRL imm8 r32 r32 -// SHRL cl r32 r32 -// SHRL imm8 r32 m32 -// SHRL cl r32 m32 -// Construct and append a SHRL instruction to the active function. +// VPSRAVW m128 xmm k xmm +// VPSRAVW m128 xmm xmm +// VPSRAVW m256 ymm k ymm +// VPSRAVW m256 ymm ymm +// VPSRAVW xmm xmm k xmm +// VPSRAVW xmm xmm xmm +// VPSRAVW ymm ymm k ymm +// VPSRAVW ymm ymm ymm +// VPSRAVW m512 zmm k zmm +// VPSRAVW m512 zmm zmm +// VPSRAVW zmm zmm k zmm +// VPSRAVW zmm zmm zmm +// Construct and append a VPSRAVW instruction to the active function. // Operates on the global context. -func SHRL(ops ...operand.Op) { ctx.SHRL(ops...) } +func VPSRAVW(ops ...operand.Op) { ctx.VPSRAVW(ops...) } -// SHRQ: Logical Shift Right. +// VPSRAVW_Z: Variable Shift Packed Word Data Right Arithmetic (Zeroing Masking). // // Forms: // -// SHRQ 1 r64 -// SHRQ imm8 r64 -// SHRQ cl r64 -// SHRQ 1 m64 -// SHRQ imm8 m64 -// SHRQ cl m64 -// SHRQ imm8 r64 r64 -// SHRQ cl r64 r64 -// SHRQ imm8 r64 m64 -// SHRQ cl r64 m64 -// Construct and append a SHRQ instruction to the active function. -func (c *Context) SHRQ(ops ...operand.Op) { - if inst, err := x86.SHRQ(ops...); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRAVW.Z m128 xmm k xmm +// VPSRAVW.Z m256 ymm k ymm +// VPSRAVW.Z xmm xmm k xmm +// VPSRAVW.Z ymm ymm k ymm +// VPSRAVW.Z m512 zmm k zmm +// VPSRAVW.Z zmm zmm k zmm +// Construct and append a VPSRAVW.Z instruction to the active function. +func (c *Context) VPSRAVW_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPSRAVW_Z(mxyz, xyz, k, xyz1)) } -// SHRQ: Logical Shift Right. +// VPSRAVW_Z: Variable Shift Packed Word Data Right Arithmetic (Zeroing Masking). // // Forms: // -// SHRQ 1 r64 -// SHRQ imm8 r64 -// SHRQ cl r64 -// SHRQ 1 m64 -// SHRQ imm8 m64 -// SHRQ cl m64 -// SHRQ imm8 r64 r64 -// SHRQ cl r64 r64 -// SHRQ imm8 r64 m64 -// SHRQ cl r64 m64 -// Construct and append a SHRQ instruction to the active function. +// VPSRAVW.Z m128 xmm k xmm +// VPSRAVW.Z m256 ymm k ymm +// VPSRAVW.Z xmm xmm k xmm +// VPSRAVW.Z ymm ymm k ymm +// VPSRAVW.Z m512 zmm k zmm +// VPSRAVW.Z zmm zmm k zmm +// Construct and append a VPSRAVW.Z instruction to the active function. // Operates on the global context. -func SHRQ(ops ...operand.Op) { ctx.SHRQ(ops...) } +func VPSRAVW_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPSRAVW_Z(mxyz, xyz, k, xyz1) } -// SHRW: Logical Shift Right. +// VPSRAW: Shift Packed Word Data Right Arithmetic. // // Forms: // -// SHRW 1 r16 -// SHRW imm8 r16 -// SHRW cl r16 -// SHRW 1 m16 -// SHRW imm8 m16 -// SHRW cl m16 -// SHRW imm8 r16 r16 -// SHRW cl r16 r16 -// SHRW imm8 r16 m16 -// SHRW cl r16 m16 -// Construct and append a SHRW instruction to the active function. -func (c *Context) SHRW(ops ...operand.Op) { - if inst, err := x86.SHRW(ops...); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRAW imm8 ymm ymm +// VPSRAW m128 ymm ymm +// VPSRAW xmm ymm ymm +// VPSRAW imm8 xmm xmm +// VPSRAW m128 xmm xmm +// VPSRAW xmm xmm xmm +// VPSRAW imm8 m128 k xmm +// VPSRAW imm8 m128 xmm +// VPSRAW imm8 m256 k ymm +// VPSRAW imm8 m256 ymm +// VPSRAW imm8 xmm k xmm +// VPSRAW imm8 ymm k ymm +// VPSRAW m128 xmm k xmm +// VPSRAW m128 ymm k ymm +// VPSRAW xmm xmm k xmm +// VPSRAW xmm ymm k ymm +// VPSRAW imm8 m512 k zmm +// VPSRAW imm8 m512 zmm +// VPSRAW imm8 zmm k zmm +// VPSRAW imm8 zmm zmm +// VPSRAW m128 zmm k zmm +// VPSRAW m128 zmm zmm +// VPSRAW xmm zmm k zmm +// VPSRAW xmm zmm zmm +// Construct and append a VPSRAW instruction to the active function. +func (c *Context) VPSRAW(ops ...operand.Op) { + c.addinstruction(x86.VPSRAW(ops...)) } -// SHRW: Logical Shift Right. +// VPSRAW: Shift Packed Word Data Right Arithmetic. // // Forms: // -// SHRW 1 r16 -// SHRW imm8 r16 -// SHRW cl r16 -// SHRW 1 m16 -// SHRW imm8 m16 -// SHRW cl m16 -// SHRW imm8 r16 r16 -// SHRW cl r16 r16 -// SHRW imm8 r16 m16 -// SHRW cl r16 m16 -// Construct and append a SHRW instruction to the active function. +// VPSRAW imm8 ymm ymm +// VPSRAW m128 ymm ymm +// VPSRAW xmm ymm ymm +// VPSRAW imm8 xmm xmm +// VPSRAW m128 xmm xmm +// VPSRAW xmm xmm xmm +// VPSRAW imm8 m128 k xmm +// VPSRAW imm8 m128 xmm +// VPSRAW imm8 m256 k ymm +// VPSRAW imm8 m256 ymm +// VPSRAW imm8 xmm k xmm +// VPSRAW imm8 ymm k ymm +// VPSRAW m128 xmm k xmm +// VPSRAW m128 ymm k ymm +// VPSRAW xmm xmm k xmm +// VPSRAW xmm ymm k ymm +// VPSRAW imm8 m512 k zmm +// VPSRAW imm8 m512 zmm +// VPSRAW imm8 zmm k zmm +// VPSRAW imm8 zmm zmm +// VPSRAW m128 zmm k zmm +// VPSRAW m128 zmm zmm +// VPSRAW xmm zmm k zmm +// VPSRAW xmm zmm zmm +// Construct and append a VPSRAW instruction to the active function. // Operates on the global context. -func SHRW(ops ...operand.Op) { ctx.SHRW(ops...) } +func VPSRAW(ops ...operand.Op) { ctx.VPSRAW(ops...) } -// SHRXL: Logical Shift Right Without Affecting Flags. +// VPSRAW_Z: Shift Packed Word Data Right Arithmetic (Zeroing Masking). // // Forms: // -// SHRXL r32 r32 r32 -// SHRXL r32 m32 r32 -// Construct and append a SHRXL instruction to the active function. -func (c *Context) SHRXL(r, mr, r1 operand.Op) { - if inst, err := x86.SHRXL(r, mr, r1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRAW.Z imm8 m128 k xmm +// VPSRAW.Z imm8 m256 k ymm +// VPSRAW.Z imm8 xmm k xmm +// VPSRAW.Z imm8 ymm k ymm +// VPSRAW.Z m128 xmm k xmm +// VPSRAW.Z m128 ymm k ymm +// VPSRAW.Z xmm xmm k xmm +// VPSRAW.Z xmm ymm k ymm +// VPSRAW.Z imm8 m512 k zmm +// VPSRAW.Z imm8 zmm k zmm +// VPSRAW.Z m128 zmm k zmm +// VPSRAW.Z xmm zmm k zmm +// Construct and append a VPSRAW.Z instruction to the active function. +func (c *Context) VPSRAW_Z(imx, mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPSRAW_Z(imx, mxyz, k, xyz)) } -// SHRXL: Logical Shift Right Without Affecting Flags. +// VPSRAW_Z: Shift Packed Word Data Right Arithmetic (Zeroing Masking). // // Forms: // -// SHRXL r32 r32 r32 -// SHRXL r32 m32 r32 -// Construct and append a SHRXL instruction to the active function. +// VPSRAW.Z imm8 m128 k xmm +// VPSRAW.Z imm8 m256 k ymm +// VPSRAW.Z imm8 xmm k xmm +// VPSRAW.Z imm8 ymm k ymm +// VPSRAW.Z m128 xmm k xmm +// VPSRAW.Z m128 ymm k ymm +// VPSRAW.Z xmm xmm k xmm +// VPSRAW.Z xmm ymm k ymm +// VPSRAW.Z imm8 m512 k zmm +// VPSRAW.Z imm8 zmm k zmm +// VPSRAW.Z m128 zmm k zmm +// VPSRAW.Z xmm zmm k zmm +// Construct and append a VPSRAW.Z instruction to the active function. // Operates on the global context. -func SHRXL(r, mr, r1 operand.Op) { ctx.SHRXL(r, mr, r1) } +func VPSRAW_Z(imx, mxyz, k, xyz operand.Op) { ctx.VPSRAW_Z(imx, mxyz, k, xyz) } -// SHRXQ: Logical Shift Right Without Affecting Flags. +// VPSRLD: Shift Packed Doubleword Data Right Logical. // // Forms: // -// SHRXQ r64 r64 r64 -// SHRXQ r64 m64 r64 -// Construct and append a SHRXQ instruction to the active function. -func (c *Context) SHRXQ(r, mr, r1 operand.Op) { - if inst, err := x86.SHRXQ(r, mr, r1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRLD imm8 ymm ymm +// VPSRLD m128 ymm ymm +// VPSRLD xmm ymm ymm +// VPSRLD imm8 xmm xmm +// VPSRLD m128 xmm xmm +// VPSRLD xmm xmm xmm +// VPSRLD imm8 m128 k xmm +// VPSRLD imm8 m128 xmm +// VPSRLD imm8 m256 k ymm +// VPSRLD imm8 m256 ymm +// VPSRLD imm8 xmm k xmm +// VPSRLD imm8 ymm k ymm +// VPSRLD m128 xmm k xmm +// VPSRLD m128 ymm k ymm +// VPSRLD xmm xmm k xmm +// VPSRLD xmm ymm k ymm +// VPSRLD imm8 m512 k zmm +// VPSRLD imm8 m512 zmm +// VPSRLD imm8 zmm k zmm +// VPSRLD imm8 zmm zmm +// VPSRLD m128 zmm k zmm +// VPSRLD m128 zmm zmm +// VPSRLD xmm zmm k zmm +// VPSRLD xmm zmm zmm +// Construct and append a VPSRLD instruction to the active function. +func (c *Context) VPSRLD(ops ...operand.Op) { + c.addinstruction(x86.VPSRLD(ops...)) } -// SHRXQ: Logical Shift Right Without Affecting Flags. +// VPSRLD: Shift Packed Doubleword Data Right Logical. // // Forms: // -// SHRXQ r64 r64 r64 -// SHRXQ r64 m64 r64 -// Construct and append a SHRXQ instruction to the active function. +// VPSRLD imm8 ymm ymm +// VPSRLD m128 ymm ymm +// VPSRLD xmm ymm ymm +// VPSRLD imm8 xmm xmm +// VPSRLD m128 xmm xmm +// VPSRLD xmm xmm xmm +// VPSRLD imm8 m128 k xmm +// VPSRLD imm8 m128 xmm +// VPSRLD imm8 m256 k ymm +// VPSRLD imm8 m256 ymm +// VPSRLD imm8 xmm k xmm +// VPSRLD imm8 ymm k ymm +// VPSRLD m128 xmm k xmm +// VPSRLD m128 ymm k ymm +// VPSRLD xmm xmm k xmm +// VPSRLD xmm ymm k ymm +// VPSRLD imm8 m512 k zmm +// VPSRLD imm8 m512 zmm +// VPSRLD imm8 zmm k zmm +// VPSRLD imm8 zmm zmm +// VPSRLD m128 zmm k zmm +// VPSRLD m128 zmm zmm +// VPSRLD xmm zmm k zmm +// VPSRLD xmm zmm zmm +// Construct and append a VPSRLD instruction to the active function. // Operates on the global context. -func SHRXQ(r, mr, r1 operand.Op) { ctx.SHRXQ(r, mr, r1) } +func VPSRLD(ops ...operand.Op) { ctx.VPSRLD(ops...) } -// SHUFPD: Shuffle Packed Double-Precision Floating-Point Values. +// VPSRLDQ: Shift Packed Double Quadword Right Logical. // // Forms: // -// SHUFPD imm8 xmm xmm -// SHUFPD imm8 m128 xmm -// Construct and append a SHUFPD instruction to the active function. -func (c *Context) SHUFPD(i, mx, x operand.Op) { - if inst, err := x86.SHUFPD(i, mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRLDQ imm8 ymm ymm +// VPSRLDQ imm8 xmm xmm +// VPSRLDQ imm8 m128 xmm +// VPSRLDQ imm8 m256 ymm +// VPSRLDQ imm8 m512 zmm +// VPSRLDQ imm8 zmm zmm +// Construct and append a VPSRLDQ instruction to the active function. +func (c *Context) VPSRLDQ(i, mxyz, xyz operand.Op) { + c.addinstruction(x86.VPSRLDQ(i, mxyz, xyz)) } -// SHUFPD: Shuffle Packed Double-Precision Floating-Point Values. +// VPSRLDQ: Shift Packed Double Quadword Right Logical. // // Forms: // -// SHUFPD imm8 xmm xmm -// SHUFPD imm8 m128 xmm -// Construct and append a SHUFPD instruction to the active function. +// VPSRLDQ imm8 ymm ymm +// VPSRLDQ imm8 xmm xmm +// VPSRLDQ imm8 m128 xmm +// VPSRLDQ imm8 m256 ymm +// VPSRLDQ imm8 m512 zmm +// VPSRLDQ imm8 zmm zmm +// Construct and append a VPSRLDQ instruction to the active function. // Operates on the global context. -func SHUFPD(i, mx, x operand.Op) { ctx.SHUFPD(i, mx, x) } +func VPSRLDQ(i, mxyz, xyz operand.Op) { ctx.VPSRLDQ(i, mxyz, xyz) } -// SHUFPS: Shuffle Packed Single-Precision Floating-Point Values. +// VPSRLD_BCST: Shift Packed Doubleword Data Right Logical (Broadcast). // // Forms: // -// SHUFPS imm8 xmm xmm -// SHUFPS imm8 m128 xmm -// Construct and append a SHUFPS instruction to the active function. -func (c *Context) SHUFPS(i, mx, x operand.Op) { - if inst, err := x86.SHUFPS(i, mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRLD.BCST imm8 m32 k xmm +// VPSRLD.BCST imm8 m32 k ymm +// VPSRLD.BCST imm8 m32 xmm +// VPSRLD.BCST imm8 m32 ymm +// VPSRLD.BCST imm8 m32 k zmm +// VPSRLD.BCST imm8 m32 zmm +// Construct and append a VPSRLD.BCST instruction to the active function. +func (c *Context) VPSRLD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPSRLD_BCST(ops...)) } -// SHUFPS: Shuffle Packed Single-Precision Floating-Point Values. +// VPSRLD_BCST: Shift Packed Doubleword Data Right Logical (Broadcast). // // Forms: // -// SHUFPS imm8 xmm xmm -// SHUFPS imm8 m128 xmm -// Construct and append a SHUFPS instruction to the active function. +// VPSRLD.BCST imm8 m32 k xmm +// VPSRLD.BCST imm8 m32 k ymm +// VPSRLD.BCST imm8 m32 xmm +// VPSRLD.BCST imm8 m32 ymm +// VPSRLD.BCST imm8 m32 k zmm +// VPSRLD.BCST imm8 m32 zmm +// Construct and append a VPSRLD.BCST instruction to the active function. // Operates on the global context. -func SHUFPS(i, mx, x operand.Op) { ctx.SHUFPS(i, mx, x) } +func VPSRLD_BCST(ops ...operand.Op) { ctx.VPSRLD_BCST(ops...) } -// SQRTPD: Compute Square Roots of Packed Double-Precision Floating-Point Values. +// VPSRLD_BCST_Z: Shift Packed Doubleword Data Right Logical (Broadcast, Zeroing Masking). // // Forms: // -// SQRTPD xmm xmm -// SQRTPD m128 xmm -// Construct and append a SQRTPD instruction to the active function. -func (c *Context) SQRTPD(mx, x operand.Op) { - if inst, err := x86.SQRTPD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRLD.BCST.Z imm8 m32 k xmm +// VPSRLD.BCST.Z imm8 m32 k ymm +// VPSRLD.BCST.Z imm8 m32 k zmm +// Construct and append a VPSRLD.BCST.Z instruction to the active function. +func (c *Context) VPSRLD_BCST_Z(i, m, k, xyz operand.Op) { + c.addinstruction(x86.VPSRLD_BCST_Z(i, m, k, xyz)) } -// SQRTPD: Compute Square Roots of Packed Double-Precision Floating-Point Values. +// VPSRLD_BCST_Z: Shift Packed Doubleword Data Right Logical (Broadcast, Zeroing Masking). // // Forms: // -// SQRTPD xmm xmm -// SQRTPD m128 xmm -// Construct and append a SQRTPD instruction to the active function. +// VPSRLD.BCST.Z imm8 m32 k xmm +// VPSRLD.BCST.Z imm8 m32 k ymm +// VPSRLD.BCST.Z imm8 m32 k zmm +// Construct and append a VPSRLD.BCST.Z instruction to the active function. // Operates on the global context. -func SQRTPD(mx, x operand.Op) { ctx.SQRTPD(mx, x) } +func VPSRLD_BCST_Z(i, m, k, xyz operand.Op) { ctx.VPSRLD_BCST_Z(i, m, k, xyz) } -// SQRTPS: Compute Square Roots of Packed Single-Precision Floating-Point Values. +// VPSRLD_Z: Shift Packed Doubleword Data Right Logical (Zeroing Masking). // // Forms: // -// SQRTPS xmm xmm -// SQRTPS m128 xmm -// Construct and append a SQRTPS instruction to the active function. -func (c *Context) SQRTPS(mx, x operand.Op) { - if inst, err := x86.SQRTPS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRLD.Z imm8 m128 k xmm +// VPSRLD.Z imm8 m256 k ymm +// VPSRLD.Z imm8 xmm k xmm +// VPSRLD.Z imm8 ymm k ymm +// VPSRLD.Z m128 xmm k xmm +// VPSRLD.Z m128 ymm k ymm +// VPSRLD.Z xmm xmm k xmm +// VPSRLD.Z xmm ymm k ymm +// VPSRLD.Z imm8 m512 k zmm +// VPSRLD.Z imm8 zmm k zmm +// VPSRLD.Z m128 zmm k zmm +// VPSRLD.Z xmm zmm k zmm +// Construct and append a VPSRLD.Z instruction to the active function. +func (c *Context) VPSRLD_Z(imx, mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPSRLD_Z(imx, mxyz, k, xyz)) } -// SQRTPS: Compute Square Roots of Packed Single-Precision Floating-Point Values. +// VPSRLD_Z: Shift Packed Doubleword Data Right Logical (Zeroing Masking). // // Forms: // -// SQRTPS xmm xmm -// SQRTPS m128 xmm -// Construct and append a SQRTPS instruction to the active function. +// VPSRLD.Z imm8 m128 k xmm +// VPSRLD.Z imm8 m256 k ymm +// VPSRLD.Z imm8 xmm k xmm +// VPSRLD.Z imm8 ymm k ymm +// VPSRLD.Z m128 xmm k xmm +// VPSRLD.Z m128 ymm k ymm +// VPSRLD.Z xmm xmm k xmm +// VPSRLD.Z xmm ymm k ymm +// VPSRLD.Z imm8 m512 k zmm +// VPSRLD.Z imm8 zmm k zmm +// VPSRLD.Z m128 zmm k zmm +// VPSRLD.Z xmm zmm k zmm +// Construct and append a VPSRLD.Z instruction to the active function. // Operates on the global context. -func SQRTPS(mx, x operand.Op) { ctx.SQRTPS(mx, x) } +func VPSRLD_Z(imx, mxyz, k, xyz operand.Op) { ctx.VPSRLD_Z(imx, mxyz, k, xyz) } -// SQRTSD: Compute Square Root of Scalar Double-Precision Floating-Point Value. +// VPSRLQ: Shift Packed Quadword Data Right Logical. // // Forms: // -// SQRTSD xmm xmm -// SQRTSD m64 xmm -// Construct and append a SQRTSD instruction to the active function. -func (c *Context) SQRTSD(mx, x operand.Op) { - if inst, err := x86.SQRTSD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRLQ imm8 ymm ymm +// VPSRLQ m128 ymm ymm +// VPSRLQ xmm ymm ymm +// VPSRLQ imm8 xmm xmm +// VPSRLQ m128 xmm xmm +// VPSRLQ xmm xmm xmm +// VPSRLQ imm8 m128 k xmm +// VPSRLQ imm8 m128 xmm +// VPSRLQ imm8 m256 k ymm +// VPSRLQ imm8 m256 ymm +// VPSRLQ imm8 xmm k xmm +// VPSRLQ imm8 ymm k ymm +// VPSRLQ m128 xmm k xmm +// VPSRLQ m128 ymm k ymm +// VPSRLQ xmm xmm k xmm +// VPSRLQ xmm ymm k ymm +// VPSRLQ imm8 m512 k zmm +// VPSRLQ imm8 m512 zmm +// VPSRLQ imm8 zmm k zmm +// VPSRLQ imm8 zmm zmm +// VPSRLQ m128 zmm k zmm +// VPSRLQ m128 zmm zmm +// VPSRLQ xmm zmm k zmm +// VPSRLQ xmm zmm zmm +// Construct and append a VPSRLQ instruction to the active function. +func (c *Context) VPSRLQ(ops ...operand.Op) { + c.addinstruction(x86.VPSRLQ(ops...)) } -// SQRTSD: Compute Square Root of Scalar Double-Precision Floating-Point Value. +// VPSRLQ: Shift Packed Quadword Data Right Logical. // // Forms: // -// SQRTSD xmm xmm -// SQRTSD m64 xmm -// Construct and append a SQRTSD instruction to the active function. +// VPSRLQ imm8 ymm ymm +// VPSRLQ m128 ymm ymm +// VPSRLQ xmm ymm ymm +// VPSRLQ imm8 xmm xmm +// VPSRLQ m128 xmm xmm +// VPSRLQ xmm xmm xmm +// VPSRLQ imm8 m128 k xmm +// VPSRLQ imm8 m128 xmm +// VPSRLQ imm8 m256 k ymm +// VPSRLQ imm8 m256 ymm +// VPSRLQ imm8 xmm k xmm +// VPSRLQ imm8 ymm k ymm +// VPSRLQ m128 xmm k xmm +// VPSRLQ m128 ymm k ymm +// VPSRLQ xmm xmm k xmm +// VPSRLQ xmm ymm k ymm +// VPSRLQ imm8 m512 k zmm +// VPSRLQ imm8 m512 zmm +// VPSRLQ imm8 zmm k zmm +// VPSRLQ imm8 zmm zmm +// VPSRLQ m128 zmm k zmm +// VPSRLQ m128 zmm zmm +// VPSRLQ xmm zmm k zmm +// VPSRLQ xmm zmm zmm +// Construct and append a VPSRLQ instruction to the active function. // Operates on the global context. -func SQRTSD(mx, x operand.Op) { ctx.SQRTSD(mx, x) } +func VPSRLQ(ops ...operand.Op) { ctx.VPSRLQ(ops...) } -// SQRTSS: Compute Square Root of Scalar Single-Precision Floating-Point Value. +// VPSRLQ_BCST: Shift Packed Quadword Data Right Logical (Broadcast). // // Forms: // -// SQRTSS xmm xmm -// SQRTSS m32 xmm -// Construct and append a SQRTSS instruction to the active function. -func (c *Context) SQRTSS(mx, x operand.Op) { - if inst, err := x86.SQRTSS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRLQ.BCST imm8 m64 k xmm +// VPSRLQ.BCST imm8 m64 k ymm +// VPSRLQ.BCST imm8 m64 xmm +// VPSRLQ.BCST imm8 m64 ymm +// VPSRLQ.BCST imm8 m64 k zmm +// VPSRLQ.BCST imm8 m64 zmm +// Construct and append a VPSRLQ.BCST instruction to the active function. +func (c *Context) VPSRLQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPSRLQ_BCST(ops...)) } -// SQRTSS: Compute Square Root of Scalar Single-Precision Floating-Point Value. +// VPSRLQ_BCST: Shift Packed Quadword Data Right Logical (Broadcast). // // Forms: // -// SQRTSS xmm xmm -// SQRTSS m32 xmm -// Construct and append a SQRTSS instruction to the active function. +// VPSRLQ.BCST imm8 m64 k xmm +// VPSRLQ.BCST imm8 m64 k ymm +// VPSRLQ.BCST imm8 m64 xmm +// VPSRLQ.BCST imm8 m64 ymm +// VPSRLQ.BCST imm8 m64 k zmm +// VPSRLQ.BCST imm8 m64 zmm +// Construct and append a VPSRLQ.BCST instruction to the active function. // Operates on the global context. -func SQRTSS(mx, x operand.Op) { ctx.SQRTSS(mx, x) } +func VPSRLQ_BCST(ops ...operand.Op) { ctx.VPSRLQ_BCST(ops...) } -// STC: Set Carry Flag. +// VPSRLQ_BCST_Z: Shift Packed Quadword Data Right Logical (Broadcast, Zeroing Masking). // // Forms: // -// STC -// Construct and append a STC instruction to the active function. -func (c *Context) STC() { - if inst, err := x86.STC(); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRLQ.BCST.Z imm8 m64 k xmm +// VPSRLQ.BCST.Z imm8 m64 k ymm +// VPSRLQ.BCST.Z imm8 m64 k zmm +// Construct and append a VPSRLQ.BCST.Z instruction to the active function. +func (c *Context) VPSRLQ_BCST_Z(i, m, k, xyz operand.Op) { + c.addinstruction(x86.VPSRLQ_BCST_Z(i, m, k, xyz)) } -// STC: Set Carry Flag. +// VPSRLQ_BCST_Z: Shift Packed Quadword Data Right Logical (Broadcast, Zeroing Masking). // // Forms: // -// STC -// Construct and append a STC instruction to the active function. +// VPSRLQ.BCST.Z imm8 m64 k xmm +// VPSRLQ.BCST.Z imm8 m64 k ymm +// VPSRLQ.BCST.Z imm8 m64 k zmm +// Construct and append a VPSRLQ.BCST.Z instruction to the active function. // Operates on the global context. -func STC() { ctx.STC() } +func VPSRLQ_BCST_Z(i, m, k, xyz operand.Op) { ctx.VPSRLQ_BCST_Z(i, m, k, xyz) } -// STD: Set Direction Flag. +// VPSRLQ_Z: Shift Packed Quadword Data Right Logical (Zeroing Masking). // // Forms: // -// STD -// Construct and append a STD instruction to the active function. -func (c *Context) STD() { - if inst, err := x86.STD(); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRLQ.Z imm8 m128 k xmm +// VPSRLQ.Z imm8 m256 k ymm +// VPSRLQ.Z imm8 xmm k xmm +// VPSRLQ.Z imm8 ymm k ymm +// VPSRLQ.Z m128 xmm k xmm +// VPSRLQ.Z m128 ymm k ymm +// VPSRLQ.Z xmm xmm k xmm +// VPSRLQ.Z xmm ymm k ymm +// VPSRLQ.Z imm8 m512 k zmm +// VPSRLQ.Z imm8 zmm k zmm +// VPSRLQ.Z m128 zmm k zmm +// VPSRLQ.Z xmm zmm k zmm +// Construct and append a VPSRLQ.Z instruction to the active function. +func (c *Context) VPSRLQ_Z(imx, mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPSRLQ_Z(imx, mxyz, k, xyz)) } -// STD: Set Direction Flag. +// VPSRLQ_Z: Shift Packed Quadword Data Right Logical (Zeroing Masking). // // Forms: // -// STD -// Construct and append a STD instruction to the active function. +// VPSRLQ.Z imm8 m128 k xmm +// VPSRLQ.Z imm8 m256 k ymm +// VPSRLQ.Z imm8 xmm k xmm +// VPSRLQ.Z imm8 ymm k ymm +// VPSRLQ.Z m128 xmm k xmm +// VPSRLQ.Z m128 ymm k ymm +// VPSRLQ.Z xmm xmm k xmm +// VPSRLQ.Z xmm ymm k ymm +// VPSRLQ.Z imm8 m512 k zmm +// VPSRLQ.Z imm8 zmm k zmm +// VPSRLQ.Z m128 zmm k zmm +// VPSRLQ.Z xmm zmm k zmm +// Construct and append a VPSRLQ.Z instruction to the active function. // Operates on the global context. -func STD() { ctx.STD() } +func VPSRLQ_Z(imx, mxyz, k, xyz operand.Op) { ctx.VPSRLQ_Z(imx, mxyz, k, xyz) } -// STMXCSR: Store MXCSR Register State. +// VPSRLVD: Variable Shift Packed Doubleword Data Right Logical. // // Forms: // -// STMXCSR m32 -// Construct and append a STMXCSR instruction to the active function. -func (c *Context) STMXCSR(m operand.Op) { - if inst, err := x86.STMXCSR(m); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRLVD m128 xmm xmm +// VPSRLVD m256 ymm ymm +// VPSRLVD xmm xmm xmm +// VPSRLVD ymm ymm ymm +// VPSRLVD m128 xmm k xmm +// VPSRLVD m256 ymm k ymm +// VPSRLVD xmm xmm k xmm +// VPSRLVD ymm ymm k ymm +// VPSRLVD m512 zmm k zmm +// VPSRLVD m512 zmm zmm +// VPSRLVD zmm zmm k zmm +// VPSRLVD zmm zmm zmm +// Construct and append a VPSRLVD instruction to the active function. +func (c *Context) VPSRLVD(ops ...operand.Op) { + c.addinstruction(x86.VPSRLVD(ops...)) } -// STMXCSR: Store MXCSR Register State. +// VPSRLVD: Variable Shift Packed Doubleword Data Right Logical. // // Forms: // -// STMXCSR m32 -// Construct and append a STMXCSR instruction to the active function. +// VPSRLVD m128 xmm xmm +// VPSRLVD m256 ymm ymm +// VPSRLVD xmm xmm xmm +// VPSRLVD ymm ymm ymm +// VPSRLVD m128 xmm k xmm +// VPSRLVD m256 ymm k ymm +// VPSRLVD xmm xmm k xmm +// VPSRLVD ymm ymm k ymm +// VPSRLVD m512 zmm k zmm +// VPSRLVD m512 zmm zmm +// VPSRLVD zmm zmm k zmm +// VPSRLVD zmm zmm zmm +// Construct and append a VPSRLVD instruction to the active function. // Operates on the global context. -func STMXCSR(m operand.Op) { ctx.STMXCSR(m) } +func VPSRLVD(ops ...operand.Op) { ctx.VPSRLVD(ops...) } -// SUBB: Subtract. +// VPSRLVD_BCST: Variable Shift Packed Doubleword Data Right Logical (Broadcast). // // Forms: // -// SUBB imm8 al -// SUBB imm8 r8 -// SUBB r8 r8 -// SUBB m8 r8 -// SUBB imm8 m8 -// SUBB r8 m8 -// Construct and append a SUBB instruction to the active function. -func (c *Context) SUBB(imr, amr operand.Op) { - if inst, err := x86.SUBB(imr, amr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRLVD.BCST m32 xmm k xmm +// VPSRLVD.BCST m32 xmm xmm +// VPSRLVD.BCST m32 ymm k ymm +// VPSRLVD.BCST m32 ymm ymm +// VPSRLVD.BCST m32 zmm k zmm +// VPSRLVD.BCST m32 zmm zmm +// Construct and append a VPSRLVD.BCST instruction to the active function. +func (c *Context) VPSRLVD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPSRLVD_BCST(ops...)) } -// SUBB: Subtract. +// VPSRLVD_BCST: Variable Shift Packed Doubleword Data Right Logical (Broadcast). // // Forms: // -// SUBB imm8 al -// SUBB imm8 r8 -// SUBB r8 r8 -// SUBB m8 r8 -// SUBB imm8 m8 -// SUBB r8 m8 -// Construct and append a SUBB instruction to the active function. +// VPSRLVD.BCST m32 xmm k xmm +// VPSRLVD.BCST m32 xmm xmm +// VPSRLVD.BCST m32 ymm k ymm +// VPSRLVD.BCST m32 ymm ymm +// VPSRLVD.BCST m32 zmm k zmm +// VPSRLVD.BCST m32 zmm zmm +// Construct and append a VPSRLVD.BCST instruction to the active function. // Operates on the global context. -func SUBB(imr, amr operand.Op) { ctx.SUBB(imr, amr) } +func VPSRLVD_BCST(ops ...operand.Op) { ctx.VPSRLVD_BCST(ops...) } -// SUBL: Subtract. +// VPSRLVD_BCST_Z: Variable Shift Packed Doubleword Data Right Logical (Broadcast, Zeroing Masking). // // Forms: // -// SUBL imm32 eax -// SUBL imm8 r32 -// SUBL imm32 r32 -// SUBL r32 r32 -// SUBL m32 r32 -// SUBL imm8 m32 -// SUBL imm32 m32 -// SUBL r32 m32 -// Construct and append a SUBL instruction to the active function. -func (c *Context) SUBL(imr, emr operand.Op) { - if inst, err := x86.SUBL(imr, emr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRLVD.BCST.Z m32 xmm k xmm +// VPSRLVD.BCST.Z m32 ymm k ymm +// VPSRLVD.BCST.Z m32 zmm k zmm +// Construct and append a VPSRLVD.BCST.Z instruction to the active function. +func (c *Context) VPSRLVD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPSRLVD_BCST_Z(m, xyz, k, xyz1)) } -// SUBL: Subtract. +// VPSRLVD_BCST_Z: Variable Shift Packed Doubleword Data Right Logical (Broadcast, Zeroing Masking). // // Forms: // -// SUBL imm32 eax -// SUBL imm8 r32 -// SUBL imm32 r32 -// SUBL r32 r32 -// SUBL m32 r32 -// SUBL imm8 m32 -// SUBL imm32 m32 -// SUBL r32 m32 -// Construct and append a SUBL instruction to the active function. +// VPSRLVD.BCST.Z m32 xmm k xmm +// VPSRLVD.BCST.Z m32 ymm k ymm +// VPSRLVD.BCST.Z m32 zmm k zmm +// Construct and append a VPSRLVD.BCST.Z instruction to the active function. // Operates on the global context. -func SUBL(imr, emr operand.Op) { ctx.SUBL(imr, emr) } +func VPSRLVD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPSRLVD_BCST_Z(m, xyz, k, xyz1) } -// SUBPD: Subtract Packed Double-Precision Floating-Point Values. +// VPSRLVD_Z: Variable Shift Packed Doubleword Data Right Logical (Zeroing Masking). // // Forms: // -// SUBPD xmm xmm -// SUBPD m128 xmm -// Construct and append a SUBPD instruction to the active function. -func (c *Context) SUBPD(mx, x operand.Op) { - if inst, err := x86.SUBPD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRLVD.Z m128 xmm k xmm +// VPSRLVD.Z m256 ymm k ymm +// VPSRLVD.Z xmm xmm k xmm +// VPSRLVD.Z ymm ymm k ymm +// VPSRLVD.Z m512 zmm k zmm +// VPSRLVD.Z zmm zmm k zmm +// Construct and append a VPSRLVD.Z instruction to the active function. +func (c *Context) VPSRLVD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPSRLVD_Z(mxyz, xyz, k, xyz1)) } -// SUBPD: Subtract Packed Double-Precision Floating-Point Values. +// VPSRLVD_Z: Variable Shift Packed Doubleword Data Right Logical (Zeroing Masking). // // Forms: // -// SUBPD xmm xmm -// SUBPD m128 xmm -// Construct and append a SUBPD instruction to the active function. +// VPSRLVD.Z m128 xmm k xmm +// VPSRLVD.Z m256 ymm k ymm +// VPSRLVD.Z xmm xmm k xmm +// VPSRLVD.Z ymm ymm k ymm +// VPSRLVD.Z m512 zmm k zmm +// VPSRLVD.Z zmm zmm k zmm +// Construct and append a VPSRLVD.Z instruction to the active function. // Operates on the global context. -func SUBPD(mx, x operand.Op) { ctx.SUBPD(mx, x) } +func VPSRLVD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPSRLVD_Z(mxyz, xyz, k, xyz1) } -// SUBPS: Subtract Packed Single-Precision Floating-Point Values. +// VPSRLVQ: Variable Shift Packed Quadword Data Right Logical. // // Forms: // -// SUBPS xmm xmm -// SUBPS m128 xmm -// Construct and append a SUBPS instruction to the active function. -func (c *Context) SUBPS(mx, x operand.Op) { - if inst, err := x86.SUBPS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRLVQ m128 xmm xmm +// VPSRLVQ m256 ymm ymm +// VPSRLVQ xmm xmm xmm +// VPSRLVQ ymm ymm ymm +// VPSRLVQ m128 xmm k xmm +// VPSRLVQ m256 ymm k ymm +// VPSRLVQ xmm xmm k xmm +// VPSRLVQ ymm ymm k ymm +// VPSRLVQ m512 zmm k zmm +// VPSRLVQ m512 zmm zmm +// VPSRLVQ zmm zmm k zmm +// VPSRLVQ zmm zmm zmm +// Construct and append a VPSRLVQ instruction to the active function. +func (c *Context) VPSRLVQ(ops ...operand.Op) { + c.addinstruction(x86.VPSRLVQ(ops...)) } -// SUBPS: Subtract Packed Single-Precision Floating-Point Values. +// VPSRLVQ: Variable Shift Packed Quadword Data Right Logical. // // Forms: // -// SUBPS xmm xmm -// SUBPS m128 xmm -// Construct and append a SUBPS instruction to the active function. +// VPSRLVQ m128 xmm xmm +// VPSRLVQ m256 ymm ymm +// VPSRLVQ xmm xmm xmm +// VPSRLVQ ymm ymm ymm +// VPSRLVQ m128 xmm k xmm +// VPSRLVQ m256 ymm k ymm +// VPSRLVQ xmm xmm k xmm +// VPSRLVQ ymm ymm k ymm +// VPSRLVQ m512 zmm k zmm +// VPSRLVQ m512 zmm zmm +// VPSRLVQ zmm zmm k zmm +// VPSRLVQ zmm zmm zmm +// Construct and append a VPSRLVQ instruction to the active function. // Operates on the global context. -func SUBPS(mx, x operand.Op) { ctx.SUBPS(mx, x) } +func VPSRLVQ(ops ...operand.Op) { ctx.VPSRLVQ(ops...) } -// SUBQ: Subtract. +// VPSRLVQ_BCST: Variable Shift Packed Quadword Data Right Logical (Broadcast). // // Forms: // -// SUBQ imm32 rax -// SUBQ imm8 r64 -// SUBQ imm32 r64 -// SUBQ r64 r64 -// SUBQ m64 r64 -// SUBQ imm8 m64 -// SUBQ imm32 m64 -// SUBQ r64 m64 -// Construct and append a SUBQ instruction to the active function. -func (c *Context) SUBQ(imr, mr operand.Op) { - if inst, err := x86.SUBQ(imr, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRLVQ.BCST m64 xmm k xmm +// VPSRLVQ.BCST m64 xmm xmm +// VPSRLVQ.BCST m64 ymm k ymm +// VPSRLVQ.BCST m64 ymm ymm +// VPSRLVQ.BCST m64 zmm k zmm +// VPSRLVQ.BCST m64 zmm zmm +// Construct and append a VPSRLVQ.BCST instruction to the active function. +func (c *Context) VPSRLVQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPSRLVQ_BCST(ops...)) } -// SUBQ: Subtract. +// VPSRLVQ_BCST: Variable Shift Packed Quadword Data Right Logical (Broadcast). // // Forms: // -// SUBQ imm32 rax -// SUBQ imm8 r64 -// SUBQ imm32 r64 -// SUBQ r64 r64 -// SUBQ m64 r64 -// SUBQ imm8 m64 -// SUBQ imm32 m64 -// SUBQ r64 m64 -// Construct and append a SUBQ instruction to the active function. +// VPSRLVQ.BCST m64 xmm k xmm +// VPSRLVQ.BCST m64 xmm xmm +// VPSRLVQ.BCST m64 ymm k ymm +// VPSRLVQ.BCST m64 ymm ymm +// VPSRLVQ.BCST m64 zmm k zmm +// VPSRLVQ.BCST m64 zmm zmm +// Construct and append a VPSRLVQ.BCST instruction to the active function. // Operates on the global context. -func SUBQ(imr, mr operand.Op) { ctx.SUBQ(imr, mr) } +func VPSRLVQ_BCST(ops ...operand.Op) { ctx.VPSRLVQ_BCST(ops...) } -// SUBSD: Subtract Scalar Double-Precision Floating-Point Values. +// VPSRLVQ_BCST_Z: Variable Shift Packed Quadword Data Right Logical (Broadcast, Zeroing Masking). // // Forms: // -// SUBSD xmm xmm -// SUBSD m64 xmm -// Construct and append a SUBSD instruction to the active function. -func (c *Context) SUBSD(mx, x operand.Op) { - if inst, err := x86.SUBSD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRLVQ.BCST.Z m64 xmm k xmm +// VPSRLVQ.BCST.Z m64 ymm k ymm +// VPSRLVQ.BCST.Z m64 zmm k zmm +// Construct and append a VPSRLVQ.BCST.Z instruction to the active function. +func (c *Context) VPSRLVQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPSRLVQ_BCST_Z(m, xyz, k, xyz1)) } -// SUBSD: Subtract Scalar Double-Precision Floating-Point Values. +// VPSRLVQ_BCST_Z: Variable Shift Packed Quadword Data Right Logical (Broadcast, Zeroing Masking). // // Forms: // -// SUBSD xmm xmm -// SUBSD m64 xmm -// Construct and append a SUBSD instruction to the active function. +// VPSRLVQ.BCST.Z m64 xmm k xmm +// VPSRLVQ.BCST.Z m64 ymm k ymm +// VPSRLVQ.BCST.Z m64 zmm k zmm +// Construct and append a VPSRLVQ.BCST.Z instruction to the active function. // Operates on the global context. -func SUBSD(mx, x operand.Op) { ctx.SUBSD(mx, x) } +func VPSRLVQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPSRLVQ_BCST_Z(m, xyz, k, xyz1) } -// SUBSS: Subtract Scalar Single-Precision Floating-Point Values. +// VPSRLVQ_Z: Variable Shift Packed Quadword Data Right Logical (Zeroing Masking). // // Forms: // -// SUBSS xmm xmm -// SUBSS m32 xmm -// Construct and append a SUBSS instruction to the active function. -func (c *Context) SUBSS(mx, x operand.Op) { - if inst, err := x86.SUBSS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRLVQ.Z m128 xmm k xmm +// VPSRLVQ.Z m256 ymm k ymm +// VPSRLVQ.Z xmm xmm k xmm +// VPSRLVQ.Z ymm ymm k ymm +// VPSRLVQ.Z m512 zmm k zmm +// VPSRLVQ.Z zmm zmm k zmm +// Construct and append a VPSRLVQ.Z instruction to the active function. +func (c *Context) VPSRLVQ_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPSRLVQ_Z(mxyz, xyz, k, xyz1)) } -// SUBSS: Subtract Scalar Single-Precision Floating-Point Values. +// VPSRLVQ_Z: Variable Shift Packed Quadword Data Right Logical (Zeroing Masking). // // Forms: // -// SUBSS xmm xmm -// SUBSS m32 xmm -// Construct and append a SUBSS instruction to the active function. +// VPSRLVQ.Z m128 xmm k xmm +// VPSRLVQ.Z m256 ymm k ymm +// VPSRLVQ.Z xmm xmm k xmm +// VPSRLVQ.Z ymm ymm k ymm +// VPSRLVQ.Z m512 zmm k zmm +// VPSRLVQ.Z zmm zmm k zmm +// Construct and append a VPSRLVQ.Z instruction to the active function. // Operates on the global context. -func SUBSS(mx, x operand.Op) { ctx.SUBSS(mx, x) } +func VPSRLVQ_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPSRLVQ_Z(mxyz, xyz, k, xyz1) } -// SUBW: Subtract. +// VPSRLVW: Variable Shift Packed Word Data Right Logical. // // Forms: // -// SUBW imm16 ax -// SUBW imm8 r16 -// SUBW imm16 r16 -// SUBW r16 r16 -// SUBW m16 r16 -// SUBW imm8 m16 -// SUBW imm16 m16 -// SUBW r16 m16 -// Construct and append a SUBW instruction to the active function. -func (c *Context) SUBW(imr, amr operand.Op) { - if inst, err := x86.SUBW(imr, amr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRLVW m128 xmm k xmm +// VPSRLVW m128 xmm xmm +// VPSRLVW m256 ymm k ymm +// VPSRLVW m256 ymm ymm +// VPSRLVW xmm xmm k xmm +// VPSRLVW xmm xmm xmm +// VPSRLVW ymm ymm k ymm +// VPSRLVW ymm ymm ymm +// VPSRLVW m512 zmm k zmm +// VPSRLVW m512 zmm zmm +// VPSRLVW zmm zmm k zmm +// VPSRLVW zmm zmm zmm +// Construct and append a VPSRLVW instruction to the active function. +func (c *Context) VPSRLVW(ops ...operand.Op) { + c.addinstruction(x86.VPSRLVW(ops...)) } -// SUBW: Subtract. +// VPSRLVW: Variable Shift Packed Word Data Right Logical. // // Forms: // -// SUBW imm16 ax -// SUBW imm8 r16 -// SUBW imm16 r16 -// SUBW r16 r16 -// SUBW m16 r16 -// SUBW imm8 m16 -// SUBW imm16 m16 -// SUBW r16 m16 -// Construct and append a SUBW instruction to the active function. +// VPSRLVW m128 xmm k xmm +// VPSRLVW m128 xmm xmm +// VPSRLVW m256 ymm k ymm +// VPSRLVW m256 ymm ymm +// VPSRLVW xmm xmm k xmm +// VPSRLVW xmm xmm xmm +// VPSRLVW ymm ymm k ymm +// VPSRLVW ymm ymm ymm +// VPSRLVW m512 zmm k zmm +// VPSRLVW m512 zmm zmm +// VPSRLVW zmm zmm k zmm +// VPSRLVW zmm zmm zmm +// Construct and append a VPSRLVW instruction to the active function. // Operates on the global context. -func SUBW(imr, amr operand.Op) { ctx.SUBW(imr, amr) } +func VPSRLVW(ops ...operand.Op) { ctx.VPSRLVW(ops...) } -// SYSCALL: Fast System Call. +// VPSRLVW_Z: Variable Shift Packed Word Data Right Logical (Zeroing Masking). // // Forms: // -// SYSCALL -// Construct and append a SYSCALL instruction to the active function. -func (c *Context) SYSCALL() { - if inst, err := x86.SYSCALL(); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRLVW.Z m128 xmm k xmm +// VPSRLVW.Z m256 ymm k ymm +// VPSRLVW.Z xmm xmm k xmm +// VPSRLVW.Z ymm ymm k ymm +// VPSRLVW.Z m512 zmm k zmm +// VPSRLVW.Z zmm zmm k zmm +// Construct and append a VPSRLVW.Z instruction to the active function. +func (c *Context) VPSRLVW_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPSRLVW_Z(mxyz, xyz, k, xyz1)) } -// SYSCALL: Fast System Call. +// VPSRLVW_Z: Variable Shift Packed Word Data Right Logical (Zeroing Masking). // // Forms: // -// SYSCALL -// Construct and append a SYSCALL instruction to the active function. +// VPSRLVW.Z m128 xmm k xmm +// VPSRLVW.Z m256 ymm k ymm +// VPSRLVW.Z xmm xmm k xmm +// VPSRLVW.Z ymm ymm k ymm +// VPSRLVW.Z m512 zmm k zmm +// VPSRLVW.Z zmm zmm k zmm +// Construct and append a VPSRLVW.Z instruction to the active function. // Operates on the global context. -func SYSCALL() { ctx.SYSCALL() } +func VPSRLVW_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPSRLVW_Z(mxyz, xyz, k, xyz1) } -// TESTB: Logical Compare. +// VPSRLW: Shift Packed Word Data Right Logical. // // Forms: // -// TESTB imm8 al -// TESTB imm8 r8 -// TESTB r8 r8 -// TESTB imm8 m8 -// TESTB r8 m8 -// Construct and append a TESTB instruction to the active function. -func (c *Context) TESTB(ir, amr operand.Op) { - if inst, err := x86.TESTB(ir, amr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRLW imm8 ymm ymm +// VPSRLW m128 ymm ymm +// VPSRLW xmm ymm ymm +// VPSRLW imm8 xmm xmm +// VPSRLW m128 xmm xmm +// VPSRLW xmm xmm xmm +// VPSRLW imm8 m128 k xmm +// VPSRLW imm8 m128 xmm +// VPSRLW imm8 m256 k ymm +// VPSRLW imm8 m256 ymm +// VPSRLW imm8 xmm k xmm +// VPSRLW imm8 ymm k ymm +// VPSRLW m128 xmm k xmm +// VPSRLW m128 ymm k ymm +// VPSRLW xmm xmm k xmm +// VPSRLW xmm ymm k ymm +// VPSRLW imm8 m512 k zmm +// VPSRLW imm8 m512 zmm +// VPSRLW imm8 zmm k zmm +// VPSRLW imm8 zmm zmm +// VPSRLW m128 zmm k zmm +// VPSRLW m128 zmm zmm +// VPSRLW xmm zmm k zmm +// VPSRLW xmm zmm zmm +// Construct and append a VPSRLW instruction to the active function. +func (c *Context) VPSRLW(ops ...operand.Op) { + c.addinstruction(x86.VPSRLW(ops...)) } -// TESTB: Logical Compare. +// VPSRLW: Shift Packed Word Data Right Logical. // // Forms: // -// TESTB imm8 al -// TESTB imm8 r8 -// TESTB r8 r8 -// TESTB imm8 m8 -// TESTB r8 m8 -// Construct and append a TESTB instruction to the active function. +// VPSRLW imm8 ymm ymm +// VPSRLW m128 ymm ymm +// VPSRLW xmm ymm ymm +// VPSRLW imm8 xmm xmm +// VPSRLW m128 xmm xmm +// VPSRLW xmm xmm xmm +// VPSRLW imm8 m128 k xmm +// VPSRLW imm8 m128 xmm +// VPSRLW imm8 m256 k ymm +// VPSRLW imm8 m256 ymm +// VPSRLW imm8 xmm k xmm +// VPSRLW imm8 ymm k ymm +// VPSRLW m128 xmm k xmm +// VPSRLW m128 ymm k ymm +// VPSRLW xmm xmm k xmm +// VPSRLW xmm ymm k ymm +// VPSRLW imm8 m512 k zmm +// VPSRLW imm8 m512 zmm +// VPSRLW imm8 zmm k zmm +// VPSRLW imm8 zmm zmm +// VPSRLW m128 zmm k zmm +// VPSRLW m128 zmm zmm +// VPSRLW xmm zmm k zmm +// VPSRLW xmm zmm zmm +// Construct and append a VPSRLW instruction to the active function. // Operates on the global context. -func TESTB(ir, amr operand.Op) { ctx.TESTB(ir, amr) } +func VPSRLW(ops ...operand.Op) { ctx.VPSRLW(ops...) } -// TESTL: Logical Compare. +// VPSRLW_Z: Shift Packed Word Data Right Logical (Zeroing Masking). // // Forms: // -// TESTL imm32 eax -// TESTL imm32 r32 -// TESTL r32 r32 -// TESTL imm32 m32 -// TESTL r32 m32 -// Construct and append a TESTL instruction to the active function. -func (c *Context) TESTL(ir, emr operand.Op) { - if inst, err := x86.TESTL(ir, emr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSRLW.Z imm8 m128 k xmm +// VPSRLW.Z imm8 m256 k ymm +// VPSRLW.Z imm8 xmm k xmm +// VPSRLW.Z imm8 ymm k ymm +// VPSRLW.Z m128 xmm k xmm +// VPSRLW.Z m128 ymm k ymm +// VPSRLW.Z xmm xmm k xmm +// VPSRLW.Z xmm ymm k ymm +// VPSRLW.Z imm8 m512 k zmm +// VPSRLW.Z imm8 zmm k zmm +// VPSRLW.Z m128 zmm k zmm +// VPSRLW.Z xmm zmm k zmm +// Construct and append a VPSRLW.Z instruction to the active function. +func (c *Context) VPSRLW_Z(imx, mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPSRLW_Z(imx, mxyz, k, xyz)) } -// TESTL: Logical Compare. +// VPSRLW_Z: Shift Packed Word Data Right Logical (Zeroing Masking). // // Forms: // -// TESTL imm32 eax -// TESTL imm32 r32 -// TESTL r32 r32 -// TESTL imm32 m32 -// TESTL r32 m32 -// Construct and append a TESTL instruction to the active function. +// VPSRLW.Z imm8 m128 k xmm +// VPSRLW.Z imm8 m256 k ymm +// VPSRLW.Z imm8 xmm k xmm +// VPSRLW.Z imm8 ymm k ymm +// VPSRLW.Z m128 xmm k xmm +// VPSRLW.Z m128 ymm k ymm +// VPSRLW.Z xmm xmm k xmm +// VPSRLW.Z xmm ymm k ymm +// VPSRLW.Z imm8 m512 k zmm +// VPSRLW.Z imm8 zmm k zmm +// VPSRLW.Z m128 zmm k zmm +// VPSRLW.Z xmm zmm k zmm +// Construct and append a VPSRLW.Z instruction to the active function. // Operates on the global context. -func TESTL(ir, emr operand.Op) { ctx.TESTL(ir, emr) } +func VPSRLW_Z(imx, mxyz, k, xyz operand.Op) { ctx.VPSRLW_Z(imx, mxyz, k, xyz) } -// TESTQ: Logical Compare. +// VPSUBB: Subtract Packed Byte Integers. // // Forms: // -// TESTQ imm32 rax -// TESTQ imm32 r64 -// TESTQ r64 r64 -// TESTQ imm32 m64 -// TESTQ r64 m64 -// Construct and append a TESTQ instruction to the active function. -func (c *Context) TESTQ(ir, mr operand.Op) { - if inst, err := x86.TESTQ(ir, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSUBB m256 ymm ymm +// VPSUBB ymm ymm ymm +// VPSUBB m128 xmm xmm +// VPSUBB xmm xmm xmm +// VPSUBB m128 xmm k xmm +// VPSUBB m256 ymm k ymm +// VPSUBB xmm xmm k xmm +// VPSUBB ymm ymm k ymm +// VPSUBB m512 zmm k zmm +// VPSUBB m512 zmm zmm +// VPSUBB zmm zmm k zmm +// VPSUBB zmm zmm zmm +// Construct and append a VPSUBB instruction to the active function. +func (c *Context) VPSUBB(ops ...operand.Op) { + c.addinstruction(x86.VPSUBB(ops...)) } -// TESTQ: Logical Compare. +// VPSUBB: Subtract Packed Byte Integers. // // Forms: // -// TESTQ imm32 rax -// TESTQ imm32 r64 -// TESTQ r64 r64 -// TESTQ imm32 m64 -// TESTQ r64 m64 -// Construct and append a TESTQ instruction to the active function. +// VPSUBB m256 ymm ymm +// VPSUBB ymm ymm ymm +// VPSUBB m128 xmm xmm +// VPSUBB xmm xmm xmm +// VPSUBB m128 xmm k xmm +// VPSUBB m256 ymm k ymm +// VPSUBB xmm xmm k xmm +// VPSUBB ymm ymm k ymm +// VPSUBB m512 zmm k zmm +// VPSUBB m512 zmm zmm +// VPSUBB zmm zmm k zmm +// VPSUBB zmm zmm zmm +// Construct and append a VPSUBB instruction to the active function. // Operates on the global context. -func TESTQ(ir, mr operand.Op) { ctx.TESTQ(ir, mr) } +func VPSUBB(ops ...operand.Op) { ctx.VPSUBB(ops...) } -// TESTW: Logical Compare. +// VPSUBB_Z: Subtract Packed Byte Integers (Zeroing Masking). // // Forms: // -// TESTW imm16 ax -// TESTW imm16 r16 -// TESTW r16 r16 -// TESTW imm16 m16 -// TESTW r16 m16 -// Construct and append a TESTW instruction to the active function. -func (c *Context) TESTW(ir, amr operand.Op) { - if inst, err := x86.TESTW(ir, amr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSUBB.Z m128 xmm k xmm +// VPSUBB.Z m256 ymm k ymm +// VPSUBB.Z xmm xmm k xmm +// VPSUBB.Z ymm ymm k ymm +// VPSUBB.Z m512 zmm k zmm +// VPSUBB.Z zmm zmm k zmm +// Construct and append a VPSUBB.Z instruction to the active function. +func (c *Context) VPSUBB_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPSUBB_Z(mxyz, xyz, k, xyz1)) } -// TESTW: Logical Compare. +// VPSUBB_Z: Subtract Packed Byte Integers (Zeroing Masking). // // Forms: // -// TESTW imm16 ax -// TESTW imm16 r16 -// TESTW r16 r16 -// TESTW imm16 m16 -// TESTW r16 m16 -// Construct and append a TESTW instruction to the active function. +// VPSUBB.Z m128 xmm k xmm +// VPSUBB.Z m256 ymm k ymm +// VPSUBB.Z xmm xmm k xmm +// VPSUBB.Z ymm ymm k ymm +// VPSUBB.Z m512 zmm k zmm +// VPSUBB.Z zmm zmm k zmm +// Construct and append a VPSUBB.Z instruction to the active function. // Operates on the global context. -func TESTW(ir, amr operand.Op) { ctx.TESTW(ir, amr) } +func VPSUBB_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPSUBB_Z(mxyz, xyz, k, xyz1) } -// TZCNTL: Count the Number of Trailing Zero Bits. +// VPSUBD: Subtract Packed Doubleword Integers. // // Forms: // -// TZCNTL r32 r32 -// TZCNTL m32 r32 -// Construct and append a TZCNTL instruction to the active function. -func (c *Context) TZCNTL(mr, r operand.Op) { - if inst, err := x86.TZCNTL(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSUBD m256 ymm ymm +// VPSUBD ymm ymm ymm +// VPSUBD m128 xmm xmm +// VPSUBD xmm xmm xmm +// VPSUBD m128 xmm k xmm +// VPSUBD m256 ymm k ymm +// VPSUBD xmm xmm k xmm +// VPSUBD ymm ymm k ymm +// VPSUBD m512 zmm k zmm +// VPSUBD m512 zmm zmm +// VPSUBD zmm zmm k zmm +// VPSUBD zmm zmm zmm +// Construct and append a VPSUBD instruction to the active function. +func (c *Context) VPSUBD(ops ...operand.Op) { + c.addinstruction(x86.VPSUBD(ops...)) } -// TZCNTL: Count the Number of Trailing Zero Bits. +// VPSUBD: Subtract Packed Doubleword Integers. // // Forms: // -// TZCNTL r32 r32 -// TZCNTL m32 r32 -// Construct and append a TZCNTL instruction to the active function. +// VPSUBD m256 ymm ymm +// VPSUBD ymm ymm ymm +// VPSUBD m128 xmm xmm +// VPSUBD xmm xmm xmm +// VPSUBD m128 xmm k xmm +// VPSUBD m256 ymm k ymm +// VPSUBD xmm xmm k xmm +// VPSUBD ymm ymm k ymm +// VPSUBD m512 zmm k zmm +// VPSUBD m512 zmm zmm +// VPSUBD zmm zmm k zmm +// VPSUBD zmm zmm zmm +// Construct and append a VPSUBD instruction to the active function. // Operates on the global context. -func TZCNTL(mr, r operand.Op) { ctx.TZCNTL(mr, r) } +func VPSUBD(ops ...operand.Op) { ctx.VPSUBD(ops...) } -// TZCNTQ: Count the Number of Trailing Zero Bits. +// VPSUBD_BCST: Subtract Packed Doubleword Integers (Broadcast). // // Forms: // -// TZCNTQ r64 r64 -// TZCNTQ m64 r64 -// Construct and append a TZCNTQ instruction to the active function. -func (c *Context) TZCNTQ(mr, r operand.Op) { - if inst, err := x86.TZCNTQ(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSUBD.BCST m32 xmm k xmm +// VPSUBD.BCST m32 xmm xmm +// VPSUBD.BCST m32 ymm k ymm +// VPSUBD.BCST m32 ymm ymm +// VPSUBD.BCST m32 zmm k zmm +// VPSUBD.BCST m32 zmm zmm +// Construct and append a VPSUBD.BCST instruction to the active function. +func (c *Context) VPSUBD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPSUBD_BCST(ops...)) } -// TZCNTQ: Count the Number of Trailing Zero Bits. +// VPSUBD_BCST: Subtract Packed Doubleword Integers (Broadcast). // // Forms: // -// TZCNTQ r64 r64 -// TZCNTQ m64 r64 -// Construct and append a TZCNTQ instruction to the active function. +// VPSUBD.BCST m32 xmm k xmm +// VPSUBD.BCST m32 xmm xmm +// VPSUBD.BCST m32 ymm k ymm +// VPSUBD.BCST m32 ymm ymm +// VPSUBD.BCST m32 zmm k zmm +// VPSUBD.BCST m32 zmm zmm +// Construct and append a VPSUBD.BCST instruction to the active function. // Operates on the global context. -func TZCNTQ(mr, r operand.Op) { ctx.TZCNTQ(mr, r) } +func VPSUBD_BCST(ops ...operand.Op) { ctx.VPSUBD_BCST(ops...) } -// TZCNTW: Count the Number of Trailing Zero Bits. +// VPSUBD_BCST_Z: Subtract Packed Doubleword Integers (Broadcast, Zeroing Masking). // // Forms: // -// TZCNTW r16 r16 -// TZCNTW m16 r16 -// Construct and append a TZCNTW instruction to the active function. -func (c *Context) TZCNTW(mr, r operand.Op) { - if inst, err := x86.TZCNTW(mr, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSUBD.BCST.Z m32 xmm k xmm +// VPSUBD.BCST.Z m32 ymm k ymm +// VPSUBD.BCST.Z m32 zmm k zmm +// Construct and append a VPSUBD.BCST.Z instruction to the active function. +func (c *Context) VPSUBD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPSUBD_BCST_Z(m, xyz, k, xyz1)) } -// TZCNTW: Count the Number of Trailing Zero Bits. +// VPSUBD_BCST_Z: Subtract Packed Doubleword Integers (Broadcast, Zeroing Masking). // // Forms: // -// TZCNTW r16 r16 -// TZCNTW m16 r16 -// Construct and append a TZCNTW instruction to the active function. +// VPSUBD.BCST.Z m32 xmm k xmm +// VPSUBD.BCST.Z m32 ymm k ymm +// VPSUBD.BCST.Z m32 zmm k zmm +// Construct and append a VPSUBD.BCST.Z instruction to the active function. // Operates on the global context. -func TZCNTW(mr, r operand.Op) { ctx.TZCNTW(mr, r) } +func VPSUBD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPSUBD_BCST_Z(m, xyz, k, xyz1) } -// UCOMISD: Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS. +// VPSUBD_Z: Subtract Packed Doubleword Integers (Zeroing Masking). // // Forms: // -// UCOMISD xmm xmm -// UCOMISD m64 xmm -// Construct and append a UCOMISD instruction to the active function. -func (c *Context) UCOMISD(mx, x operand.Op) { - if inst, err := x86.UCOMISD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSUBD.Z m128 xmm k xmm +// VPSUBD.Z m256 ymm k ymm +// VPSUBD.Z xmm xmm k xmm +// VPSUBD.Z ymm ymm k ymm +// VPSUBD.Z m512 zmm k zmm +// VPSUBD.Z zmm zmm k zmm +// Construct and append a VPSUBD.Z instruction to the active function. +func (c *Context) VPSUBD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPSUBD_Z(mxyz, xyz, k, xyz1)) } -// UCOMISD: Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS. +// VPSUBD_Z: Subtract Packed Doubleword Integers (Zeroing Masking). // // Forms: // -// UCOMISD xmm xmm -// UCOMISD m64 xmm -// Construct and append a UCOMISD instruction to the active function. +// VPSUBD.Z m128 xmm k xmm +// VPSUBD.Z m256 ymm k ymm +// VPSUBD.Z xmm xmm k xmm +// VPSUBD.Z ymm ymm k ymm +// VPSUBD.Z m512 zmm k zmm +// VPSUBD.Z zmm zmm k zmm +// Construct and append a VPSUBD.Z instruction to the active function. // Operates on the global context. -func UCOMISD(mx, x operand.Op) { ctx.UCOMISD(mx, x) } +func VPSUBD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPSUBD_Z(mxyz, xyz, k, xyz1) } -// UCOMISS: Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS. +// VPSUBQ: Subtract Packed Quadword Integers. // // Forms: // -// UCOMISS xmm xmm -// UCOMISS m32 xmm -// Construct and append a UCOMISS instruction to the active function. -func (c *Context) UCOMISS(mx, x operand.Op) { - if inst, err := x86.UCOMISS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSUBQ m256 ymm ymm +// VPSUBQ ymm ymm ymm +// VPSUBQ m128 xmm xmm +// VPSUBQ xmm xmm xmm +// VPSUBQ m128 xmm k xmm +// VPSUBQ m256 ymm k ymm +// VPSUBQ xmm xmm k xmm +// VPSUBQ ymm ymm k ymm +// VPSUBQ m512 zmm k zmm +// VPSUBQ m512 zmm zmm +// VPSUBQ zmm zmm k zmm +// VPSUBQ zmm zmm zmm +// Construct and append a VPSUBQ instruction to the active function. +func (c *Context) VPSUBQ(ops ...operand.Op) { + c.addinstruction(x86.VPSUBQ(ops...)) } -// UCOMISS: Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS. +// VPSUBQ: Subtract Packed Quadword Integers. // // Forms: // -// UCOMISS xmm xmm -// UCOMISS m32 xmm -// Construct and append a UCOMISS instruction to the active function. +// VPSUBQ m256 ymm ymm +// VPSUBQ ymm ymm ymm +// VPSUBQ m128 xmm xmm +// VPSUBQ xmm xmm xmm +// VPSUBQ m128 xmm k xmm +// VPSUBQ m256 ymm k ymm +// VPSUBQ xmm xmm k xmm +// VPSUBQ ymm ymm k ymm +// VPSUBQ m512 zmm k zmm +// VPSUBQ m512 zmm zmm +// VPSUBQ zmm zmm k zmm +// VPSUBQ zmm zmm zmm +// Construct and append a VPSUBQ instruction to the active function. // Operates on the global context. -func UCOMISS(mx, x operand.Op) { ctx.UCOMISS(mx, x) } +func VPSUBQ(ops ...operand.Op) { ctx.VPSUBQ(ops...) } -// UD2: Undefined Instruction. +// VPSUBQ_BCST: Subtract Packed Quadword Integers (Broadcast). // // Forms: // -// UD2 -// Construct and append a UD2 instruction to the active function. -func (c *Context) UD2() { - if inst, err := x86.UD2(); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSUBQ.BCST m64 xmm k xmm +// VPSUBQ.BCST m64 xmm xmm +// VPSUBQ.BCST m64 ymm k ymm +// VPSUBQ.BCST m64 ymm ymm +// VPSUBQ.BCST m64 zmm k zmm +// VPSUBQ.BCST m64 zmm zmm +// Construct and append a VPSUBQ.BCST instruction to the active function. +func (c *Context) VPSUBQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPSUBQ_BCST(ops...)) } -// UD2: Undefined Instruction. +// VPSUBQ_BCST: Subtract Packed Quadword Integers (Broadcast). // // Forms: // -// UD2 -// Construct and append a UD2 instruction to the active function. +// VPSUBQ.BCST m64 xmm k xmm +// VPSUBQ.BCST m64 xmm xmm +// VPSUBQ.BCST m64 ymm k ymm +// VPSUBQ.BCST m64 ymm ymm +// VPSUBQ.BCST m64 zmm k zmm +// VPSUBQ.BCST m64 zmm zmm +// Construct and append a VPSUBQ.BCST instruction to the active function. // Operates on the global context. -func UD2() { ctx.UD2() } +func VPSUBQ_BCST(ops ...operand.Op) { ctx.VPSUBQ_BCST(ops...) } -// UNPCKHPD: Unpack and Interleave High Packed Double-Precision Floating-Point Values. +// VPSUBQ_BCST_Z: Subtract Packed Quadword Integers (Broadcast, Zeroing Masking). // // Forms: // -// UNPCKHPD xmm xmm -// UNPCKHPD m128 xmm -// Construct and append a UNPCKHPD instruction to the active function. -func (c *Context) UNPCKHPD(mx, x operand.Op) { - if inst, err := x86.UNPCKHPD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSUBQ.BCST.Z m64 xmm k xmm +// VPSUBQ.BCST.Z m64 ymm k ymm +// VPSUBQ.BCST.Z m64 zmm k zmm +// Construct and append a VPSUBQ.BCST.Z instruction to the active function. +func (c *Context) VPSUBQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPSUBQ_BCST_Z(m, xyz, k, xyz1)) } -// UNPCKHPD: Unpack and Interleave High Packed Double-Precision Floating-Point Values. +// VPSUBQ_BCST_Z: Subtract Packed Quadword Integers (Broadcast, Zeroing Masking). // // Forms: // -// UNPCKHPD xmm xmm -// UNPCKHPD m128 xmm -// Construct and append a UNPCKHPD instruction to the active function. +// VPSUBQ.BCST.Z m64 xmm k xmm +// VPSUBQ.BCST.Z m64 ymm k ymm +// VPSUBQ.BCST.Z m64 zmm k zmm +// Construct and append a VPSUBQ.BCST.Z instruction to the active function. // Operates on the global context. -func UNPCKHPD(mx, x operand.Op) { ctx.UNPCKHPD(mx, x) } +func VPSUBQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPSUBQ_BCST_Z(m, xyz, k, xyz1) } -// UNPCKHPS: Unpack and Interleave High Packed Single-Precision Floating-Point Values. +// VPSUBQ_Z: Subtract Packed Quadword Integers (Zeroing Masking). // // Forms: // -// UNPCKHPS xmm xmm -// UNPCKHPS m128 xmm -// Construct and append a UNPCKHPS instruction to the active function. -func (c *Context) UNPCKHPS(mx, x operand.Op) { - if inst, err := x86.UNPCKHPS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSUBQ.Z m128 xmm k xmm +// VPSUBQ.Z m256 ymm k ymm +// VPSUBQ.Z xmm xmm k xmm +// VPSUBQ.Z ymm ymm k ymm +// VPSUBQ.Z m512 zmm k zmm +// VPSUBQ.Z zmm zmm k zmm +// Construct and append a VPSUBQ.Z instruction to the active function. +func (c *Context) VPSUBQ_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPSUBQ_Z(mxyz, xyz, k, xyz1)) } -// UNPCKHPS: Unpack and Interleave High Packed Single-Precision Floating-Point Values. +// VPSUBQ_Z: Subtract Packed Quadword Integers (Zeroing Masking). // // Forms: // -// UNPCKHPS xmm xmm -// UNPCKHPS m128 xmm -// Construct and append a UNPCKHPS instruction to the active function. +// VPSUBQ.Z m128 xmm k xmm +// VPSUBQ.Z m256 ymm k ymm +// VPSUBQ.Z xmm xmm k xmm +// VPSUBQ.Z ymm ymm k ymm +// VPSUBQ.Z m512 zmm k zmm +// VPSUBQ.Z zmm zmm k zmm +// Construct and append a VPSUBQ.Z instruction to the active function. // Operates on the global context. -func UNPCKHPS(mx, x operand.Op) { ctx.UNPCKHPS(mx, x) } +func VPSUBQ_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPSUBQ_Z(mxyz, xyz, k, xyz1) } -// UNPCKLPD: Unpack and Interleave Low Packed Double-Precision Floating-Point Values. +// VPSUBSB: Subtract Packed Signed Byte Integers with Signed Saturation. // // Forms: // -// UNPCKLPD xmm xmm -// UNPCKLPD m128 xmm -// Construct and append a UNPCKLPD instruction to the active function. -func (c *Context) UNPCKLPD(mx, x operand.Op) { - if inst, err := x86.UNPCKLPD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSUBSB m256 ymm ymm +// VPSUBSB ymm ymm ymm +// VPSUBSB m128 xmm xmm +// VPSUBSB xmm xmm xmm +// VPSUBSB m128 xmm k xmm +// VPSUBSB m256 ymm k ymm +// VPSUBSB xmm xmm k xmm +// VPSUBSB ymm ymm k ymm +// VPSUBSB m512 zmm k zmm +// VPSUBSB m512 zmm zmm +// VPSUBSB zmm zmm k zmm +// VPSUBSB zmm zmm zmm +// Construct and append a VPSUBSB instruction to the active function. +func (c *Context) VPSUBSB(ops ...operand.Op) { + c.addinstruction(x86.VPSUBSB(ops...)) } -// UNPCKLPD: Unpack and Interleave Low Packed Double-Precision Floating-Point Values. +// VPSUBSB: Subtract Packed Signed Byte Integers with Signed Saturation. // // Forms: // -// UNPCKLPD xmm xmm -// UNPCKLPD m128 xmm -// Construct and append a UNPCKLPD instruction to the active function. +// VPSUBSB m256 ymm ymm +// VPSUBSB ymm ymm ymm +// VPSUBSB m128 xmm xmm +// VPSUBSB xmm xmm xmm +// VPSUBSB m128 xmm k xmm +// VPSUBSB m256 ymm k ymm +// VPSUBSB xmm xmm k xmm +// VPSUBSB ymm ymm k ymm +// VPSUBSB m512 zmm k zmm +// VPSUBSB m512 zmm zmm +// VPSUBSB zmm zmm k zmm +// VPSUBSB zmm zmm zmm +// Construct and append a VPSUBSB instruction to the active function. // Operates on the global context. -func UNPCKLPD(mx, x operand.Op) { ctx.UNPCKLPD(mx, x) } +func VPSUBSB(ops ...operand.Op) { ctx.VPSUBSB(ops...) } -// UNPCKLPS: Unpack and Interleave Low Packed Single-Precision Floating-Point Values. +// VPSUBSB_Z: Subtract Packed Signed Byte Integers with Signed Saturation (Zeroing Masking). // // Forms: // -// UNPCKLPS xmm xmm -// UNPCKLPS m128 xmm -// Construct and append a UNPCKLPS instruction to the active function. -func (c *Context) UNPCKLPS(mx, x operand.Op) { - if inst, err := x86.UNPCKLPS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSUBSB.Z m128 xmm k xmm +// VPSUBSB.Z m256 ymm k ymm +// VPSUBSB.Z xmm xmm k xmm +// VPSUBSB.Z ymm ymm k ymm +// VPSUBSB.Z m512 zmm k zmm +// VPSUBSB.Z zmm zmm k zmm +// Construct and append a VPSUBSB.Z instruction to the active function. +func (c *Context) VPSUBSB_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPSUBSB_Z(mxyz, xyz, k, xyz1)) } -// UNPCKLPS: Unpack and Interleave Low Packed Single-Precision Floating-Point Values. +// VPSUBSB_Z: Subtract Packed Signed Byte Integers with Signed Saturation (Zeroing Masking). // // Forms: // -// UNPCKLPS xmm xmm -// UNPCKLPS m128 xmm -// Construct and append a UNPCKLPS instruction to the active function. +// VPSUBSB.Z m128 xmm k xmm +// VPSUBSB.Z m256 ymm k ymm +// VPSUBSB.Z xmm xmm k xmm +// VPSUBSB.Z ymm ymm k ymm +// VPSUBSB.Z m512 zmm k zmm +// VPSUBSB.Z zmm zmm k zmm +// Construct and append a VPSUBSB.Z instruction to the active function. // Operates on the global context. -func UNPCKLPS(mx, x operand.Op) { ctx.UNPCKLPS(mx, x) } +func VPSUBSB_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPSUBSB_Z(mxyz, xyz, k, xyz1) } -// VADDPD: Add Packed Double-Precision Floating-Point Values. +// VPSUBSW: Subtract Packed Signed Word Integers with Signed Saturation. // // Forms: // -// VADDPD xmm xmm xmm -// VADDPD m128 xmm xmm -// VADDPD ymm ymm ymm -// VADDPD m256 ymm ymm -// Construct and append a VADDPD instruction to the active function. -func (c *Context) VADDPD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VADDPD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSUBSW m256 ymm ymm +// VPSUBSW ymm ymm ymm +// VPSUBSW m128 xmm xmm +// VPSUBSW xmm xmm xmm +// VPSUBSW m128 xmm k xmm +// VPSUBSW m256 ymm k ymm +// VPSUBSW xmm xmm k xmm +// VPSUBSW ymm ymm k ymm +// VPSUBSW m512 zmm k zmm +// VPSUBSW m512 zmm zmm +// VPSUBSW zmm zmm k zmm +// VPSUBSW zmm zmm zmm +// Construct and append a VPSUBSW instruction to the active function. +func (c *Context) VPSUBSW(ops ...operand.Op) { + c.addinstruction(x86.VPSUBSW(ops...)) } -// VADDPD: Add Packed Double-Precision Floating-Point Values. +// VPSUBSW: Subtract Packed Signed Word Integers with Signed Saturation. // // Forms: // -// VADDPD xmm xmm xmm -// VADDPD m128 xmm xmm -// VADDPD ymm ymm ymm -// VADDPD m256 ymm ymm -// Construct and append a VADDPD instruction to the active function. +// VPSUBSW m256 ymm ymm +// VPSUBSW ymm ymm ymm +// VPSUBSW m128 xmm xmm +// VPSUBSW xmm xmm xmm +// VPSUBSW m128 xmm k xmm +// VPSUBSW m256 ymm k ymm +// VPSUBSW xmm xmm k xmm +// VPSUBSW ymm ymm k ymm +// VPSUBSW m512 zmm k zmm +// VPSUBSW m512 zmm zmm +// VPSUBSW zmm zmm k zmm +// VPSUBSW zmm zmm zmm +// Construct and append a VPSUBSW instruction to the active function. // Operates on the global context. -func VADDPD(mxy, xy, xy1 operand.Op) { ctx.VADDPD(mxy, xy, xy1) } +func VPSUBSW(ops ...operand.Op) { ctx.VPSUBSW(ops...) } -// VADDPS: Add Packed Single-Precision Floating-Point Values. +// VPSUBSW_Z: Subtract Packed Signed Word Integers with Signed Saturation (Zeroing Masking). // // Forms: // -// VADDPS xmm xmm xmm -// VADDPS m128 xmm xmm -// VADDPS ymm ymm ymm -// VADDPS m256 ymm ymm -// Construct and append a VADDPS instruction to the active function. -func (c *Context) VADDPS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VADDPS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSUBSW.Z m128 xmm k xmm +// VPSUBSW.Z m256 ymm k ymm +// VPSUBSW.Z xmm xmm k xmm +// VPSUBSW.Z ymm ymm k ymm +// VPSUBSW.Z m512 zmm k zmm +// VPSUBSW.Z zmm zmm k zmm +// Construct and append a VPSUBSW.Z instruction to the active function. +func (c *Context) VPSUBSW_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPSUBSW_Z(mxyz, xyz, k, xyz1)) } -// VADDPS: Add Packed Single-Precision Floating-Point Values. +// VPSUBSW_Z: Subtract Packed Signed Word Integers with Signed Saturation (Zeroing Masking). // // Forms: // -// VADDPS xmm xmm xmm -// VADDPS m128 xmm xmm -// VADDPS ymm ymm ymm -// VADDPS m256 ymm ymm -// Construct and append a VADDPS instruction to the active function. +// VPSUBSW.Z m128 xmm k xmm +// VPSUBSW.Z m256 ymm k ymm +// VPSUBSW.Z xmm xmm k xmm +// VPSUBSW.Z ymm ymm k ymm +// VPSUBSW.Z m512 zmm k zmm +// VPSUBSW.Z zmm zmm k zmm +// Construct and append a VPSUBSW.Z instruction to the active function. // Operates on the global context. -func VADDPS(mxy, xy, xy1 operand.Op) { ctx.VADDPS(mxy, xy, xy1) } +func VPSUBSW_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPSUBSW_Z(mxyz, xyz, k, xyz1) } -// VADDSD: Add Scalar Double-Precision Floating-Point Values. +// VPSUBUSB: Subtract Packed Unsigned Byte Integers with Unsigned Saturation. // // Forms: // -// VADDSD xmm xmm xmm -// VADDSD m64 xmm xmm -// Construct and append a VADDSD instruction to the active function. -func (c *Context) VADDSD(mx, x, x1 operand.Op) { - if inst, err := x86.VADDSD(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSUBUSB m256 ymm ymm +// VPSUBUSB ymm ymm ymm +// VPSUBUSB m128 xmm xmm +// VPSUBUSB xmm xmm xmm +// VPSUBUSB m128 xmm k xmm +// VPSUBUSB m256 ymm k ymm +// VPSUBUSB xmm xmm k xmm +// VPSUBUSB ymm ymm k ymm +// VPSUBUSB m512 zmm k zmm +// VPSUBUSB m512 zmm zmm +// VPSUBUSB zmm zmm k zmm +// VPSUBUSB zmm zmm zmm +// Construct and append a VPSUBUSB instruction to the active function. +func (c *Context) VPSUBUSB(ops ...operand.Op) { + c.addinstruction(x86.VPSUBUSB(ops...)) } -// VADDSD: Add Scalar Double-Precision Floating-Point Values. +// VPSUBUSB: Subtract Packed Unsigned Byte Integers with Unsigned Saturation. // // Forms: // -// VADDSD xmm xmm xmm -// VADDSD m64 xmm xmm -// Construct and append a VADDSD instruction to the active function. +// VPSUBUSB m256 ymm ymm +// VPSUBUSB ymm ymm ymm +// VPSUBUSB m128 xmm xmm +// VPSUBUSB xmm xmm xmm +// VPSUBUSB m128 xmm k xmm +// VPSUBUSB m256 ymm k ymm +// VPSUBUSB xmm xmm k xmm +// VPSUBUSB ymm ymm k ymm +// VPSUBUSB m512 zmm k zmm +// VPSUBUSB m512 zmm zmm +// VPSUBUSB zmm zmm k zmm +// VPSUBUSB zmm zmm zmm +// Construct and append a VPSUBUSB instruction to the active function. // Operates on the global context. -func VADDSD(mx, x, x1 operand.Op) { ctx.VADDSD(mx, x, x1) } +func VPSUBUSB(ops ...operand.Op) { ctx.VPSUBUSB(ops...) } -// VADDSS: Add Scalar Single-Precision Floating-Point Values. +// VPSUBUSB_Z: Subtract Packed Unsigned Byte Integers with Unsigned Saturation (Zeroing Masking). // // Forms: // -// VADDSS xmm xmm xmm -// VADDSS m32 xmm xmm -// Construct and append a VADDSS instruction to the active function. -func (c *Context) VADDSS(mx, x, x1 operand.Op) { - if inst, err := x86.VADDSS(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSUBUSB.Z m128 xmm k xmm +// VPSUBUSB.Z m256 ymm k ymm +// VPSUBUSB.Z xmm xmm k xmm +// VPSUBUSB.Z ymm ymm k ymm +// VPSUBUSB.Z m512 zmm k zmm +// VPSUBUSB.Z zmm zmm k zmm +// Construct and append a VPSUBUSB.Z instruction to the active function. +func (c *Context) VPSUBUSB_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPSUBUSB_Z(mxyz, xyz, k, xyz1)) } -// VADDSS: Add Scalar Single-Precision Floating-Point Values. +// VPSUBUSB_Z: Subtract Packed Unsigned Byte Integers with Unsigned Saturation (Zeroing Masking). // // Forms: // -// VADDSS xmm xmm xmm -// VADDSS m32 xmm xmm -// Construct and append a VADDSS instruction to the active function. +// VPSUBUSB.Z m128 xmm k xmm +// VPSUBUSB.Z m256 ymm k ymm +// VPSUBUSB.Z xmm xmm k xmm +// VPSUBUSB.Z ymm ymm k ymm +// VPSUBUSB.Z m512 zmm k zmm +// VPSUBUSB.Z zmm zmm k zmm +// Construct and append a VPSUBUSB.Z instruction to the active function. // Operates on the global context. -func VADDSS(mx, x, x1 operand.Op) { ctx.VADDSS(mx, x, x1) } +func VPSUBUSB_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPSUBUSB_Z(mxyz, xyz, k, xyz1) } -// VADDSUBPD: Packed Double-FP Add/Subtract. +// VPSUBUSW: Subtract Packed Unsigned Word Integers with Unsigned Saturation. // // Forms: // -// VADDSUBPD xmm xmm xmm -// VADDSUBPD m128 xmm xmm -// VADDSUBPD ymm ymm ymm -// VADDSUBPD m256 ymm ymm -// Construct and append a VADDSUBPD instruction to the active function. -func (c *Context) VADDSUBPD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VADDSUBPD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSUBUSW m256 ymm ymm +// VPSUBUSW ymm ymm ymm +// VPSUBUSW m128 xmm xmm +// VPSUBUSW xmm xmm xmm +// VPSUBUSW m128 xmm k xmm +// VPSUBUSW m256 ymm k ymm +// VPSUBUSW xmm xmm k xmm +// VPSUBUSW ymm ymm k ymm +// VPSUBUSW m512 zmm k zmm +// VPSUBUSW m512 zmm zmm +// VPSUBUSW zmm zmm k zmm +// VPSUBUSW zmm zmm zmm +// Construct and append a VPSUBUSW instruction to the active function. +func (c *Context) VPSUBUSW(ops ...operand.Op) { + c.addinstruction(x86.VPSUBUSW(ops...)) } -// VADDSUBPD: Packed Double-FP Add/Subtract. +// VPSUBUSW: Subtract Packed Unsigned Word Integers with Unsigned Saturation. // // Forms: // -// VADDSUBPD xmm xmm xmm -// VADDSUBPD m128 xmm xmm -// VADDSUBPD ymm ymm ymm -// VADDSUBPD m256 ymm ymm -// Construct and append a VADDSUBPD instruction to the active function. +// VPSUBUSW m256 ymm ymm +// VPSUBUSW ymm ymm ymm +// VPSUBUSW m128 xmm xmm +// VPSUBUSW xmm xmm xmm +// VPSUBUSW m128 xmm k xmm +// VPSUBUSW m256 ymm k ymm +// VPSUBUSW xmm xmm k xmm +// VPSUBUSW ymm ymm k ymm +// VPSUBUSW m512 zmm k zmm +// VPSUBUSW m512 zmm zmm +// VPSUBUSW zmm zmm k zmm +// VPSUBUSW zmm zmm zmm +// Construct and append a VPSUBUSW instruction to the active function. // Operates on the global context. -func VADDSUBPD(mxy, xy, xy1 operand.Op) { ctx.VADDSUBPD(mxy, xy, xy1) } +func VPSUBUSW(ops ...operand.Op) { ctx.VPSUBUSW(ops...) } -// VADDSUBPS: Packed Single-FP Add/Subtract. +// VPSUBUSW_Z: Subtract Packed Unsigned Word Integers with Unsigned Saturation (Zeroing Masking). // // Forms: // -// VADDSUBPS xmm xmm xmm -// VADDSUBPS m128 xmm xmm -// VADDSUBPS ymm ymm ymm -// VADDSUBPS m256 ymm ymm -// Construct and append a VADDSUBPS instruction to the active function. -func (c *Context) VADDSUBPS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VADDSUBPS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSUBUSW.Z m128 xmm k xmm +// VPSUBUSW.Z m256 ymm k ymm +// VPSUBUSW.Z xmm xmm k xmm +// VPSUBUSW.Z ymm ymm k ymm +// VPSUBUSW.Z m512 zmm k zmm +// VPSUBUSW.Z zmm zmm k zmm +// Construct and append a VPSUBUSW.Z instruction to the active function. +func (c *Context) VPSUBUSW_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPSUBUSW_Z(mxyz, xyz, k, xyz1)) } -// VADDSUBPS: Packed Single-FP Add/Subtract. +// VPSUBUSW_Z: Subtract Packed Unsigned Word Integers with Unsigned Saturation (Zeroing Masking). // // Forms: // -// VADDSUBPS xmm xmm xmm -// VADDSUBPS m128 xmm xmm -// VADDSUBPS ymm ymm ymm -// VADDSUBPS m256 ymm ymm -// Construct and append a VADDSUBPS instruction to the active function. +// VPSUBUSW.Z m128 xmm k xmm +// VPSUBUSW.Z m256 ymm k ymm +// VPSUBUSW.Z xmm xmm k xmm +// VPSUBUSW.Z ymm ymm k ymm +// VPSUBUSW.Z m512 zmm k zmm +// VPSUBUSW.Z zmm zmm k zmm +// Construct and append a VPSUBUSW.Z instruction to the active function. // Operates on the global context. -func VADDSUBPS(mxy, xy, xy1 operand.Op) { ctx.VADDSUBPS(mxy, xy, xy1) } +func VPSUBUSW_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPSUBUSW_Z(mxyz, xyz, k, xyz1) } -// VAESDEC: Perform One Round of an AES Decryption Flow. +// VPSUBW: Subtract Packed Word Integers. // // Forms: // -// VAESDEC xmm xmm xmm -// VAESDEC m128 xmm xmm -// Construct and append a VAESDEC instruction to the active function. -func (c *Context) VAESDEC(mx, x, x1 operand.Op) { - if inst, err := x86.VAESDEC(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSUBW m256 ymm ymm +// VPSUBW ymm ymm ymm +// VPSUBW m128 xmm xmm +// VPSUBW xmm xmm xmm +// VPSUBW m128 xmm k xmm +// VPSUBW m256 ymm k ymm +// VPSUBW xmm xmm k xmm +// VPSUBW ymm ymm k ymm +// VPSUBW m512 zmm k zmm +// VPSUBW m512 zmm zmm +// VPSUBW zmm zmm k zmm +// VPSUBW zmm zmm zmm +// Construct and append a VPSUBW instruction to the active function. +func (c *Context) VPSUBW(ops ...operand.Op) { + c.addinstruction(x86.VPSUBW(ops...)) } -// VAESDEC: Perform One Round of an AES Decryption Flow. +// VPSUBW: Subtract Packed Word Integers. // // Forms: // -// VAESDEC xmm xmm xmm -// VAESDEC m128 xmm xmm -// Construct and append a VAESDEC instruction to the active function. +// VPSUBW m256 ymm ymm +// VPSUBW ymm ymm ymm +// VPSUBW m128 xmm xmm +// VPSUBW xmm xmm xmm +// VPSUBW m128 xmm k xmm +// VPSUBW m256 ymm k ymm +// VPSUBW xmm xmm k xmm +// VPSUBW ymm ymm k ymm +// VPSUBW m512 zmm k zmm +// VPSUBW m512 zmm zmm +// VPSUBW zmm zmm k zmm +// VPSUBW zmm zmm zmm +// Construct and append a VPSUBW instruction to the active function. // Operates on the global context. -func VAESDEC(mx, x, x1 operand.Op) { ctx.VAESDEC(mx, x, x1) } +func VPSUBW(ops ...operand.Op) { ctx.VPSUBW(ops...) } -// VAESDECLAST: Perform Last Round of an AES Decryption Flow. +// VPSUBW_Z: Subtract Packed Word Integers (Zeroing Masking). // // Forms: // -// VAESDECLAST xmm xmm xmm -// VAESDECLAST m128 xmm xmm -// Construct and append a VAESDECLAST instruction to the active function. -func (c *Context) VAESDECLAST(mx, x, x1 operand.Op) { - if inst, err := x86.VAESDECLAST(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPSUBW.Z m128 xmm k xmm +// VPSUBW.Z m256 ymm k ymm +// VPSUBW.Z xmm xmm k xmm +// VPSUBW.Z ymm ymm k ymm +// VPSUBW.Z m512 zmm k zmm +// VPSUBW.Z zmm zmm k zmm +// Construct and append a VPSUBW.Z instruction to the active function. +func (c *Context) VPSUBW_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPSUBW_Z(mxyz, xyz, k, xyz1)) } -// VAESDECLAST: Perform Last Round of an AES Decryption Flow. +// VPSUBW_Z: Subtract Packed Word Integers (Zeroing Masking). // // Forms: // -// VAESDECLAST xmm xmm xmm -// VAESDECLAST m128 xmm xmm -// Construct and append a VAESDECLAST instruction to the active function. +// VPSUBW.Z m128 xmm k xmm +// VPSUBW.Z m256 ymm k ymm +// VPSUBW.Z xmm xmm k xmm +// VPSUBW.Z ymm ymm k ymm +// VPSUBW.Z m512 zmm k zmm +// VPSUBW.Z zmm zmm k zmm +// Construct and append a VPSUBW.Z instruction to the active function. // Operates on the global context. -func VAESDECLAST(mx, x, x1 operand.Op) { ctx.VAESDECLAST(mx, x, x1) } +func VPSUBW_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPSUBW_Z(mxyz, xyz, k, xyz1) } -// VAESENC: Perform One Round of an AES Encryption Flow. +// VPTERNLOGD: Bitwise Ternary Logical Operation on Doubleword Values. // // Forms: // -// VAESENC xmm xmm xmm -// VAESENC m128 xmm xmm -// Construct and append a VAESENC instruction to the active function. -func (c *Context) VAESENC(mx, x, x1 operand.Op) { - if inst, err := x86.VAESENC(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPTERNLOGD imm8 m128 xmm k xmm +// VPTERNLOGD imm8 m128 xmm xmm +// VPTERNLOGD imm8 m256 ymm k ymm +// VPTERNLOGD imm8 m256 ymm ymm +// VPTERNLOGD imm8 xmm xmm k xmm +// VPTERNLOGD imm8 xmm xmm xmm +// VPTERNLOGD imm8 ymm ymm k ymm +// VPTERNLOGD imm8 ymm ymm ymm +// VPTERNLOGD imm8 m512 zmm k zmm +// VPTERNLOGD imm8 m512 zmm zmm +// VPTERNLOGD imm8 zmm zmm k zmm +// VPTERNLOGD imm8 zmm zmm zmm +// Construct and append a VPTERNLOGD instruction to the active function. +func (c *Context) VPTERNLOGD(ops ...operand.Op) { + c.addinstruction(x86.VPTERNLOGD(ops...)) } -// VAESENC: Perform One Round of an AES Encryption Flow. +// VPTERNLOGD: Bitwise Ternary Logical Operation on Doubleword Values. // // Forms: // -// VAESENC xmm xmm xmm -// VAESENC m128 xmm xmm -// Construct and append a VAESENC instruction to the active function. +// VPTERNLOGD imm8 m128 xmm k xmm +// VPTERNLOGD imm8 m128 xmm xmm +// VPTERNLOGD imm8 m256 ymm k ymm +// VPTERNLOGD imm8 m256 ymm ymm +// VPTERNLOGD imm8 xmm xmm k xmm +// VPTERNLOGD imm8 xmm xmm xmm +// VPTERNLOGD imm8 ymm ymm k ymm +// VPTERNLOGD imm8 ymm ymm ymm +// VPTERNLOGD imm8 m512 zmm k zmm +// VPTERNLOGD imm8 m512 zmm zmm +// VPTERNLOGD imm8 zmm zmm k zmm +// VPTERNLOGD imm8 zmm zmm zmm +// Construct and append a VPTERNLOGD instruction to the active function. // Operates on the global context. -func VAESENC(mx, x, x1 operand.Op) { ctx.VAESENC(mx, x, x1) } +func VPTERNLOGD(ops ...operand.Op) { ctx.VPTERNLOGD(ops...) } -// VAESENCLAST: Perform Last Round of an AES Encryption Flow. +// VPTERNLOGD_BCST: Bitwise Ternary Logical Operation on Doubleword Values (Broadcast). // // Forms: // -// VAESENCLAST xmm xmm xmm -// VAESENCLAST m128 xmm xmm -// Construct and append a VAESENCLAST instruction to the active function. -func (c *Context) VAESENCLAST(mx, x, x1 operand.Op) { - if inst, err := x86.VAESENCLAST(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPTERNLOGD.BCST imm8 m32 xmm k xmm +// VPTERNLOGD.BCST imm8 m32 xmm xmm +// VPTERNLOGD.BCST imm8 m32 ymm k ymm +// VPTERNLOGD.BCST imm8 m32 ymm ymm +// VPTERNLOGD.BCST imm8 m32 zmm k zmm +// VPTERNLOGD.BCST imm8 m32 zmm zmm +// Construct and append a VPTERNLOGD.BCST instruction to the active function. +func (c *Context) VPTERNLOGD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPTERNLOGD_BCST(ops...)) } -// VAESENCLAST: Perform Last Round of an AES Encryption Flow. +// VPTERNLOGD_BCST: Bitwise Ternary Logical Operation on Doubleword Values (Broadcast). // // Forms: // -// VAESENCLAST xmm xmm xmm -// VAESENCLAST m128 xmm xmm -// Construct and append a VAESENCLAST instruction to the active function. +// VPTERNLOGD.BCST imm8 m32 xmm k xmm +// VPTERNLOGD.BCST imm8 m32 xmm xmm +// VPTERNLOGD.BCST imm8 m32 ymm k ymm +// VPTERNLOGD.BCST imm8 m32 ymm ymm +// VPTERNLOGD.BCST imm8 m32 zmm k zmm +// VPTERNLOGD.BCST imm8 m32 zmm zmm +// Construct and append a VPTERNLOGD.BCST instruction to the active function. // Operates on the global context. -func VAESENCLAST(mx, x, x1 operand.Op) { ctx.VAESENCLAST(mx, x, x1) } +func VPTERNLOGD_BCST(ops ...operand.Op) { ctx.VPTERNLOGD_BCST(ops...) } -// VAESIMC: Perform the AES InvMixColumn Transformation. +// VPTERNLOGD_BCST_Z: Bitwise Ternary Logical Operation on Doubleword Values (Broadcast, Zeroing Masking). // // Forms: // -// VAESIMC xmm xmm -// VAESIMC m128 xmm -// Construct and append a VAESIMC instruction to the active function. -func (c *Context) VAESIMC(mx, x operand.Op) { - if inst, err := x86.VAESIMC(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPTERNLOGD.BCST.Z imm8 m32 xmm k xmm +// VPTERNLOGD.BCST.Z imm8 m32 ymm k ymm +// VPTERNLOGD.BCST.Z imm8 m32 zmm k zmm +// Construct and append a VPTERNLOGD.BCST.Z instruction to the active function. +func (c *Context) VPTERNLOGD_BCST_Z(i, m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPTERNLOGD_BCST_Z(i, m, xyz, k, xyz1)) } -// VAESIMC: Perform the AES InvMixColumn Transformation. +// VPTERNLOGD_BCST_Z: Bitwise Ternary Logical Operation on Doubleword Values (Broadcast, Zeroing Masking). // // Forms: // -// VAESIMC xmm xmm -// VAESIMC m128 xmm -// Construct and append a VAESIMC instruction to the active function. +// VPTERNLOGD.BCST.Z imm8 m32 xmm k xmm +// VPTERNLOGD.BCST.Z imm8 m32 ymm k ymm +// VPTERNLOGD.BCST.Z imm8 m32 zmm k zmm +// Construct and append a VPTERNLOGD.BCST.Z instruction to the active function. // Operates on the global context. -func VAESIMC(mx, x operand.Op) { ctx.VAESIMC(mx, x) } +func VPTERNLOGD_BCST_Z(i, m, xyz, k, xyz1 operand.Op) { ctx.VPTERNLOGD_BCST_Z(i, m, xyz, k, xyz1) } -// VAESKEYGENASSIST: AES Round Key Generation Assist. +// VPTERNLOGD_Z: Bitwise Ternary Logical Operation on Doubleword Values (Zeroing Masking). // // Forms: // -// VAESKEYGENASSIST imm8 xmm xmm -// VAESKEYGENASSIST imm8 m128 xmm -// Construct and append a VAESKEYGENASSIST instruction to the active function. -func (c *Context) VAESKEYGENASSIST(i, mx, x operand.Op) { - if inst, err := x86.VAESKEYGENASSIST(i, mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPTERNLOGD.Z imm8 m128 xmm k xmm +// VPTERNLOGD.Z imm8 m256 ymm k ymm +// VPTERNLOGD.Z imm8 xmm xmm k xmm +// VPTERNLOGD.Z imm8 ymm ymm k ymm +// VPTERNLOGD.Z imm8 m512 zmm k zmm +// VPTERNLOGD.Z imm8 zmm zmm k zmm +// Construct and append a VPTERNLOGD.Z instruction to the active function. +func (c *Context) VPTERNLOGD_Z(i, mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPTERNLOGD_Z(i, mxyz, xyz, k, xyz1)) } -// VAESKEYGENASSIST: AES Round Key Generation Assist. +// VPTERNLOGD_Z: Bitwise Ternary Logical Operation on Doubleword Values (Zeroing Masking). // // Forms: // -// VAESKEYGENASSIST imm8 xmm xmm -// VAESKEYGENASSIST imm8 m128 xmm -// Construct and append a VAESKEYGENASSIST instruction to the active function. +// VPTERNLOGD.Z imm8 m128 xmm k xmm +// VPTERNLOGD.Z imm8 m256 ymm k ymm +// VPTERNLOGD.Z imm8 xmm xmm k xmm +// VPTERNLOGD.Z imm8 ymm ymm k ymm +// VPTERNLOGD.Z imm8 m512 zmm k zmm +// VPTERNLOGD.Z imm8 zmm zmm k zmm +// Construct and append a VPTERNLOGD.Z instruction to the active function. // Operates on the global context. -func VAESKEYGENASSIST(i, mx, x operand.Op) { ctx.VAESKEYGENASSIST(i, mx, x) } +func VPTERNLOGD_Z(i, mxyz, xyz, k, xyz1 operand.Op) { ctx.VPTERNLOGD_Z(i, mxyz, xyz, k, xyz1) } -// VANDNPD: Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values. +// VPTERNLOGQ: Bitwise Ternary Logical Operation on Quadword Values. // // Forms: // -// VANDNPD xmm xmm xmm -// VANDNPD m128 xmm xmm -// VANDNPD ymm ymm ymm -// VANDNPD m256 ymm ymm -// Construct and append a VANDNPD instruction to the active function. -func (c *Context) VANDNPD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VANDNPD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPTERNLOGQ imm8 m128 xmm k xmm +// VPTERNLOGQ imm8 m128 xmm xmm +// VPTERNLOGQ imm8 m256 ymm k ymm +// VPTERNLOGQ imm8 m256 ymm ymm +// VPTERNLOGQ imm8 xmm xmm k xmm +// VPTERNLOGQ imm8 xmm xmm xmm +// VPTERNLOGQ imm8 ymm ymm k ymm +// VPTERNLOGQ imm8 ymm ymm ymm +// VPTERNLOGQ imm8 m512 zmm k zmm +// VPTERNLOGQ imm8 m512 zmm zmm +// VPTERNLOGQ imm8 zmm zmm k zmm +// VPTERNLOGQ imm8 zmm zmm zmm +// Construct and append a VPTERNLOGQ instruction to the active function. +func (c *Context) VPTERNLOGQ(ops ...operand.Op) { + c.addinstruction(x86.VPTERNLOGQ(ops...)) } -// VANDNPD: Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values. +// VPTERNLOGQ: Bitwise Ternary Logical Operation on Quadword Values. // // Forms: // -// VANDNPD xmm xmm xmm -// VANDNPD m128 xmm xmm -// VANDNPD ymm ymm ymm -// VANDNPD m256 ymm ymm -// Construct and append a VANDNPD instruction to the active function. +// VPTERNLOGQ imm8 m128 xmm k xmm +// VPTERNLOGQ imm8 m128 xmm xmm +// VPTERNLOGQ imm8 m256 ymm k ymm +// VPTERNLOGQ imm8 m256 ymm ymm +// VPTERNLOGQ imm8 xmm xmm k xmm +// VPTERNLOGQ imm8 xmm xmm xmm +// VPTERNLOGQ imm8 ymm ymm k ymm +// VPTERNLOGQ imm8 ymm ymm ymm +// VPTERNLOGQ imm8 m512 zmm k zmm +// VPTERNLOGQ imm8 m512 zmm zmm +// VPTERNLOGQ imm8 zmm zmm k zmm +// VPTERNLOGQ imm8 zmm zmm zmm +// Construct and append a VPTERNLOGQ instruction to the active function. // Operates on the global context. -func VANDNPD(mxy, xy, xy1 operand.Op) { ctx.VANDNPD(mxy, xy, xy1) } +func VPTERNLOGQ(ops ...operand.Op) { ctx.VPTERNLOGQ(ops...) } -// VANDNPS: Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values. +// VPTERNLOGQ_BCST: Bitwise Ternary Logical Operation on Quadword Values (Broadcast). // // Forms: // -// VANDNPS xmm xmm xmm -// VANDNPS m128 xmm xmm -// VANDNPS ymm ymm ymm -// VANDNPS m256 ymm ymm -// Construct and append a VANDNPS instruction to the active function. -func (c *Context) VANDNPS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VANDNPS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPTERNLOGQ.BCST imm8 m64 xmm k xmm +// VPTERNLOGQ.BCST imm8 m64 xmm xmm +// VPTERNLOGQ.BCST imm8 m64 ymm k ymm +// VPTERNLOGQ.BCST imm8 m64 ymm ymm +// VPTERNLOGQ.BCST imm8 m64 zmm k zmm +// VPTERNLOGQ.BCST imm8 m64 zmm zmm +// Construct and append a VPTERNLOGQ.BCST instruction to the active function. +func (c *Context) VPTERNLOGQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPTERNLOGQ_BCST(ops...)) } -// VANDNPS: Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values. +// VPTERNLOGQ_BCST: Bitwise Ternary Logical Operation on Quadword Values (Broadcast). // // Forms: // -// VANDNPS xmm xmm xmm -// VANDNPS m128 xmm xmm -// VANDNPS ymm ymm ymm -// VANDNPS m256 ymm ymm -// Construct and append a VANDNPS instruction to the active function. +// VPTERNLOGQ.BCST imm8 m64 xmm k xmm +// VPTERNLOGQ.BCST imm8 m64 xmm xmm +// VPTERNLOGQ.BCST imm8 m64 ymm k ymm +// VPTERNLOGQ.BCST imm8 m64 ymm ymm +// VPTERNLOGQ.BCST imm8 m64 zmm k zmm +// VPTERNLOGQ.BCST imm8 m64 zmm zmm +// Construct and append a VPTERNLOGQ.BCST instruction to the active function. // Operates on the global context. -func VANDNPS(mxy, xy, xy1 operand.Op) { ctx.VANDNPS(mxy, xy, xy1) } +func VPTERNLOGQ_BCST(ops ...operand.Op) { ctx.VPTERNLOGQ_BCST(ops...) } -// VANDPD: Bitwise Logical AND of Packed Double-Precision Floating-Point Values. +// VPTERNLOGQ_BCST_Z: Bitwise Ternary Logical Operation on Quadword Values (Broadcast, Zeroing Masking). // // Forms: // -// VANDPD xmm xmm xmm -// VANDPD m128 xmm xmm -// VANDPD ymm ymm ymm -// VANDPD m256 ymm ymm -// Construct and append a VANDPD instruction to the active function. -func (c *Context) VANDPD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VANDPD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPTERNLOGQ.BCST.Z imm8 m64 xmm k xmm +// VPTERNLOGQ.BCST.Z imm8 m64 ymm k ymm +// VPTERNLOGQ.BCST.Z imm8 m64 zmm k zmm +// Construct and append a VPTERNLOGQ.BCST.Z instruction to the active function. +func (c *Context) VPTERNLOGQ_BCST_Z(i, m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPTERNLOGQ_BCST_Z(i, m, xyz, k, xyz1)) } -// VANDPD: Bitwise Logical AND of Packed Double-Precision Floating-Point Values. +// VPTERNLOGQ_BCST_Z: Bitwise Ternary Logical Operation on Quadword Values (Broadcast, Zeroing Masking). // // Forms: // -// VANDPD xmm xmm xmm -// VANDPD m128 xmm xmm -// VANDPD ymm ymm ymm -// VANDPD m256 ymm ymm -// Construct and append a VANDPD instruction to the active function. +// VPTERNLOGQ.BCST.Z imm8 m64 xmm k xmm +// VPTERNLOGQ.BCST.Z imm8 m64 ymm k ymm +// VPTERNLOGQ.BCST.Z imm8 m64 zmm k zmm +// Construct and append a VPTERNLOGQ.BCST.Z instruction to the active function. // Operates on the global context. -func VANDPD(mxy, xy, xy1 operand.Op) { ctx.VANDPD(mxy, xy, xy1) } +func VPTERNLOGQ_BCST_Z(i, m, xyz, k, xyz1 operand.Op) { ctx.VPTERNLOGQ_BCST_Z(i, m, xyz, k, xyz1) } -// VANDPS: Bitwise Logical AND of Packed Single-Precision Floating-Point Values. +// VPTERNLOGQ_Z: Bitwise Ternary Logical Operation on Quadword Values (Zeroing Masking). // // Forms: // -// VANDPS xmm xmm xmm -// VANDPS m128 xmm xmm -// VANDPS ymm ymm ymm -// VANDPS m256 ymm ymm -// Construct and append a VANDPS instruction to the active function. -func (c *Context) VANDPS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VANDPS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPTERNLOGQ.Z imm8 m128 xmm k xmm +// VPTERNLOGQ.Z imm8 m256 ymm k ymm +// VPTERNLOGQ.Z imm8 xmm xmm k xmm +// VPTERNLOGQ.Z imm8 ymm ymm k ymm +// VPTERNLOGQ.Z imm8 m512 zmm k zmm +// VPTERNLOGQ.Z imm8 zmm zmm k zmm +// Construct and append a VPTERNLOGQ.Z instruction to the active function. +func (c *Context) VPTERNLOGQ_Z(i, mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPTERNLOGQ_Z(i, mxyz, xyz, k, xyz1)) } -// VANDPS: Bitwise Logical AND of Packed Single-Precision Floating-Point Values. +// VPTERNLOGQ_Z: Bitwise Ternary Logical Operation on Quadword Values (Zeroing Masking). // // Forms: // -// VANDPS xmm xmm xmm -// VANDPS m128 xmm xmm -// VANDPS ymm ymm ymm -// VANDPS m256 ymm ymm -// Construct and append a VANDPS instruction to the active function. +// VPTERNLOGQ.Z imm8 m128 xmm k xmm +// VPTERNLOGQ.Z imm8 m256 ymm k ymm +// VPTERNLOGQ.Z imm8 xmm xmm k xmm +// VPTERNLOGQ.Z imm8 ymm ymm k ymm +// VPTERNLOGQ.Z imm8 m512 zmm k zmm +// VPTERNLOGQ.Z imm8 zmm zmm k zmm +// Construct and append a VPTERNLOGQ.Z instruction to the active function. // Operates on the global context. -func VANDPS(mxy, xy, xy1 operand.Op) { ctx.VANDPS(mxy, xy, xy1) } +func VPTERNLOGQ_Z(i, mxyz, xyz, k, xyz1 operand.Op) { ctx.VPTERNLOGQ_Z(i, mxyz, xyz, k, xyz1) } -// VBLENDPD: Blend Packed Double Precision Floating-Point Values. +// VPTEST: Packed Logical Compare. // // Forms: // -// VBLENDPD imm8 xmm xmm xmm -// VBLENDPD imm8 m128 xmm xmm -// VBLENDPD imm8 ymm ymm ymm -// VBLENDPD imm8 m256 ymm ymm -// Construct and append a VBLENDPD instruction to the active function. -func (c *Context) VBLENDPD(i, mxy, xy, xy1 operand.Op) { - if inst, err := x86.VBLENDPD(i, mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPTEST m128 xmm +// VPTEST m256 ymm +// VPTEST xmm xmm +// VPTEST ymm ymm +// Construct and append a VPTEST instruction to the active function. +func (c *Context) VPTEST(mxy, xy operand.Op) { + c.addinstruction(x86.VPTEST(mxy, xy)) } -// VBLENDPD: Blend Packed Double Precision Floating-Point Values. +// VPTEST: Packed Logical Compare. // // Forms: // -// VBLENDPD imm8 xmm xmm xmm -// VBLENDPD imm8 m128 xmm xmm -// VBLENDPD imm8 ymm ymm ymm -// VBLENDPD imm8 m256 ymm ymm -// Construct and append a VBLENDPD instruction to the active function. +// VPTEST m128 xmm +// VPTEST m256 ymm +// VPTEST xmm xmm +// VPTEST ymm ymm +// Construct and append a VPTEST instruction to the active function. // Operates on the global context. -func VBLENDPD(i, mxy, xy, xy1 operand.Op) { ctx.VBLENDPD(i, mxy, xy, xy1) } +func VPTEST(mxy, xy operand.Op) { ctx.VPTEST(mxy, xy) } -// VBLENDPS: Blend Packed Single Precision Floating-Point Values. +// VPTESTMB: Logical AND of Packed Byte Integer Values and Set Mask. // // Forms: // -// VBLENDPS imm8 xmm xmm xmm -// VBLENDPS imm8 m128 xmm xmm -// VBLENDPS imm8 ymm ymm ymm -// VBLENDPS imm8 m256 ymm ymm -// Construct and append a VBLENDPS instruction to the active function. -func (c *Context) VBLENDPS(i, mxy, xy, xy1 operand.Op) { - if inst, err := x86.VBLENDPS(i, mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPTESTMB m128 xmm k k +// VPTESTMB m128 xmm k +// VPTESTMB m256 ymm k k +// VPTESTMB m256 ymm k +// VPTESTMB xmm xmm k k +// VPTESTMB xmm xmm k +// VPTESTMB ymm ymm k k +// VPTESTMB ymm ymm k +// VPTESTMB m512 zmm k k +// VPTESTMB m512 zmm k +// VPTESTMB zmm zmm k k +// VPTESTMB zmm zmm k +// Construct and append a VPTESTMB instruction to the active function. +func (c *Context) VPTESTMB(ops ...operand.Op) { + c.addinstruction(x86.VPTESTMB(ops...)) } -// VBLENDPS: Blend Packed Single Precision Floating-Point Values. +// VPTESTMB: Logical AND of Packed Byte Integer Values and Set Mask. // // Forms: // -// VBLENDPS imm8 xmm xmm xmm -// VBLENDPS imm8 m128 xmm xmm -// VBLENDPS imm8 ymm ymm ymm -// VBLENDPS imm8 m256 ymm ymm -// Construct and append a VBLENDPS instruction to the active function. +// VPTESTMB m128 xmm k k +// VPTESTMB m128 xmm k +// VPTESTMB m256 ymm k k +// VPTESTMB m256 ymm k +// VPTESTMB xmm xmm k k +// VPTESTMB xmm xmm k +// VPTESTMB ymm ymm k k +// VPTESTMB ymm ymm k +// VPTESTMB m512 zmm k k +// VPTESTMB m512 zmm k +// VPTESTMB zmm zmm k k +// VPTESTMB zmm zmm k +// Construct and append a VPTESTMB instruction to the active function. // Operates on the global context. -func VBLENDPS(i, mxy, xy, xy1 operand.Op) { ctx.VBLENDPS(i, mxy, xy, xy1) } +func VPTESTMB(ops ...operand.Op) { ctx.VPTESTMB(ops...) } -// VBLENDVPD: Variable Blend Packed Double Precision Floating-Point Values. +// VPTESTMD: Logical AND of Packed Doubleword Integer Values and Set Mask. // // Forms: // -// VBLENDVPD xmm xmm xmm xmm -// VBLENDVPD xmm m128 xmm xmm -// VBLENDVPD ymm ymm ymm ymm -// VBLENDVPD ymm m256 ymm ymm -// Construct and append a VBLENDVPD instruction to the active function. -func (c *Context) VBLENDVPD(xy, mxy, xy1, xy2 operand.Op) { - if inst, err := x86.VBLENDVPD(xy, mxy, xy1, xy2); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPTESTMD m128 xmm k k +// VPTESTMD m128 xmm k +// VPTESTMD m256 ymm k k +// VPTESTMD m256 ymm k +// VPTESTMD xmm xmm k k +// VPTESTMD xmm xmm k +// VPTESTMD ymm ymm k k +// VPTESTMD ymm ymm k +// VPTESTMD m512 zmm k k +// VPTESTMD m512 zmm k +// VPTESTMD zmm zmm k k +// VPTESTMD zmm zmm k +// Construct and append a VPTESTMD instruction to the active function. +func (c *Context) VPTESTMD(ops ...operand.Op) { + c.addinstruction(x86.VPTESTMD(ops...)) } -// VBLENDVPD: Variable Blend Packed Double Precision Floating-Point Values. +// VPTESTMD: Logical AND of Packed Doubleword Integer Values and Set Mask. // // Forms: // -// VBLENDVPD xmm xmm xmm xmm -// VBLENDVPD xmm m128 xmm xmm -// VBLENDVPD ymm ymm ymm ymm -// VBLENDVPD ymm m256 ymm ymm -// Construct and append a VBLENDVPD instruction to the active function. +// VPTESTMD m128 xmm k k +// VPTESTMD m128 xmm k +// VPTESTMD m256 ymm k k +// VPTESTMD m256 ymm k +// VPTESTMD xmm xmm k k +// VPTESTMD xmm xmm k +// VPTESTMD ymm ymm k k +// VPTESTMD ymm ymm k +// VPTESTMD m512 zmm k k +// VPTESTMD m512 zmm k +// VPTESTMD zmm zmm k k +// VPTESTMD zmm zmm k +// Construct and append a VPTESTMD instruction to the active function. // Operates on the global context. -func VBLENDVPD(xy, mxy, xy1, xy2 operand.Op) { ctx.VBLENDVPD(xy, mxy, xy1, xy2) } +func VPTESTMD(ops ...operand.Op) { ctx.VPTESTMD(ops...) } -// VBLENDVPS: Variable Blend Packed Single Precision Floating-Point Values. +// VPTESTMD_BCST: Logical AND of Packed Doubleword Integer Values and Set Mask (Broadcast). // // Forms: // -// VBLENDVPS xmm xmm xmm xmm -// VBLENDVPS xmm m128 xmm xmm -// VBLENDVPS ymm ymm ymm ymm -// VBLENDVPS ymm m256 ymm ymm -// Construct and append a VBLENDVPS instruction to the active function. -func (c *Context) VBLENDVPS(xy, mxy, xy1, xy2 operand.Op) { - if inst, err := x86.VBLENDVPS(xy, mxy, xy1, xy2); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPTESTMD.BCST m32 xmm k k +// VPTESTMD.BCST m32 xmm k +// VPTESTMD.BCST m32 ymm k k +// VPTESTMD.BCST m32 ymm k +// VPTESTMD.BCST m32 zmm k k +// VPTESTMD.BCST m32 zmm k +// Construct and append a VPTESTMD.BCST instruction to the active function. +func (c *Context) VPTESTMD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPTESTMD_BCST(ops...)) } -// VBLENDVPS: Variable Blend Packed Single Precision Floating-Point Values. +// VPTESTMD_BCST: Logical AND of Packed Doubleword Integer Values and Set Mask (Broadcast). // // Forms: // -// VBLENDVPS xmm xmm xmm xmm -// VBLENDVPS xmm m128 xmm xmm -// VBLENDVPS ymm ymm ymm ymm -// VBLENDVPS ymm m256 ymm ymm -// Construct and append a VBLENDVPS instruction to the active function. +// VPTESTMD.BCST m32 xmm k k +// VPTESTMD.BCST m32 xmm k +// VPTESTMD.BCST m32 ymm k k +// VPTESTMD.BCST m32 ymm k +// VPTESTMD.BCST m32 zmm k k +// VPTESTMD.BCST m32 zmm k +// Construct and append a VPTESTMD.BCST instruction to the active function. // Operates on the global context. -func VBLENDVPS(xy, mxy, xy1, xy2 operand.Op) { ctx.VBLENDVPS(xy, mxy, xy1, xy2) } +func VPTESTMD_BCST(ops ...operand.Op) { ctx.VPTESTMD_BCST(ops...) } -// VBROADCASTF128: Broadcast 128 Bit of Floating-Point Data. +// VPTESTMQ: Logical AND of Packed Quadword Integer Values and Set Mask. // // Forms: // -// VBROADCASTF128 m128 ymm -// Construct and append a VBROADCASTF128 instruction to the active function. -func (c *Context) VBROADCASTF128(m, y operand.Op) { - if inst, err := x86.VBROADCASTF128(m, y); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPTESTMQ m128 xmm k k +// VPTESTMQ m128 xmm k +// VPTESTMQ m256 ymm k k +// VPTESTMQ m256 ymm k +// VPTESTMQ xmm xmm k k +// VPTESTMQ xmm xmm k +// VPTESTMQ ymm ymm k k +// VPTESTMQ ymm ymm k +// VPTESTMQ m512 zmm k k +// VPTESTMQ m512 zmm k +// VPTESTMQ zmm zmm k k +// VPTESTMQ zmm zmm k +// Construct and append a VPTESTMQ instruction to the active function. +func (c *Context) VPTESTMQ(ops ...operand.Op) { + c.addinstruction(x86.VPTESTMQ(ops...)) } -// VBROADCASTF128: Broadcast 128 Bit of Floating-Point Data. +// VPTESTMQ: Logical AND of Packed Quadword Integer Values and Set Mask. // // Forms: // -// VBROADCASTF128 m128 ymm -// Construct and append a VBROADCASTF128 instruction to the active function. +// VPTESTMQ m128 xmm k k +// VPTESTMQ m128 xmm k +// VPTESTMQ m256 ymm k k +// VPTESTMQ m256 ymm k +// VPTESTMQ xmm xmm k k +// VPTESTMQ xmm xmm k +// VPTESTMQ ymm ymm k k +// VPTESTMQ ymm ymm k +// VPTESTMQ m512 zmm k k +// VPTESTMQ m512 zmm k +// VPTESTMQ zmm zmm k k +// VPTESTMQ zmm zmm k +// Construct and append a VPTESTMQ instruction to the active function. // Operates on the global context. -func VBROADCASTF128(m, y operand.Op) { ctx.VBROADCASTF128(m, y) } +func VPTESTMQ(ops ...operand.Op) { ctx.VPTESTMQ(ops...) } -// VBROADCASTI128: Broadcast 128 Bits of Integer Data. +// VPTESTMQ_BCST: Logical AND of Packed Quadword Integer Values and Set Mask (Broadcast). // // Forms: // -// VBROADCASTI128 m128 ymm -// Construct and append a VBROADCASTI128 instruction to the active function. -func (c *Context) VBROADCASTI128(m, y operand.Op) { - if inst, err := x86.VBROADCASTI128(m, y); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPTESTMQ.BCST m64 xmm k k +// VPTESTMQ.BCST m64 xmm k +// VPTESTMQ.BCST m64 ymm k k +// VPTESTMQ.BCST m64 ymm k +// VPTESTMQ.BCST m64 zmm k k +// VPTESTMQ.BCST m64 zmm k +// Construct and append a VPTESTMQ.BCST instruction to the active function. +func (c *Context) VPTESTMQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPTESTMQ_BCST(ops...)) } -// VBROADCASTI128: Broadcast 128 Bits of Integer Data. +// VPTESTMQ_BCST: Logical AND of Packed Quadword Integer Values and Set Mask (Broadcast). // // Forms: // -// VBROADCASTI128 m128 ymm -// Construct and append a VBROADCASTI128 instruction to the active function. +// VPTESTMQ.BCST m64 xmm k k +// VPTESTMQ.BCST m64 xmm k +// VPTESTMQ.BCST m64 ymm k k +// VPTESTMQ.BCST m64 ymm k +// VPTESTMQ.BCST m64 zmm k k +// VPTESTMQ.BCST m64 zmm k +// Construct and append a VPTESTMQ.BCST instruction to the active function. // Operates on the global context. -func VBROADCASTI128(m, y operand.Op) { ctx.VBROADCASTI128(m, y) } +func VPTESTMQ_BCST(ops ...operand.Op) { ctx.VPTESTMQ_BCST(ops...) } -// VBROADCASTSD: Broadcast Double-Precision Floating-Point Element. +// VPTESTMW: Logical AND of Packed Word Integer Values and Set Mask. // // Forms: // -// VBROADCASTSD xmm ymm -// VBROADCASTSD m64 ymm -// Construct and append a VBROADCASTSD instruction to the active function. -func (c *Context) VBROADCASTSD(mx, y operand.Op) { - if inst, err := x86.VBROADCASTSD(mx, y); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPTESTMW m128 xmm k k +// VPTESTMW m128 xmm k +// VPTESTMW m256 ymm k k +// VPTESTMW m256 ymm k +// VPTESTMW xmm xmm k k +// VPTESTMW xmm xmm k +// VPTESTMW ymm ymm k k +// VPTESTMW ymm ymm k +// VPTESTMW m512 zmm k k +// VPTESTMW m512 zmm k +// VPTESTMW zmm zmm k k +// VPTESTMW zmm zmm k +// Construct and append a VPTESTMW instruction to the active function. +func (c *Context) VPTESTMW(ops ...operand.Op) { + c.addinstruction(x86.VPTESTMW(ops...)) } -// VBROADCASTSD: Broadcast Double-Precision Floating-Point Element. +// VPTESTMW: Logical AND of Packed Word Integer Values and Set Mask. // // Forms: // -// VBROADCASTSD xmm ymm -// VBROADCASTSD m64 ymm -// Construct and append a VBROADCASTSD instruction to the active function. +// VPTESTMW m128 xmm k k +// VPTESTMW m128 xmm k +// VPTESTMW m256 ymm k k +// VPTESTMW m256 ymm k +// VPTESTMW xmm xmm k k +// VPTESTMW xmm xmm k +// VPTESTMW ymm ymm k k +// VPTESTMW ymm ymm k +// VPTESTMW m512 zmm k k +// VPTESTMW m512 zmm k +// VPTESTMW zmm zmm k k +// VPTESTMW zmm zmm k +// Construct and append a VPTESTMW instruction to the active function. // Operates on the global context. -func VBROADCASTSD(mx, y operand.Op) { ctx.VBROADCASTSD(mx, y) } +func VPTESTMW(ops ...operand.Op) { ctx.VPTESTMW(ops...) } -// VBROADCASTSS: Broadcast Single-Precision Floating-Point Element. +// VPTESTNMB: Logical NAND of Packed Byte Integer Values and Set Mask. // // Forms: // -// VBROADCASTSS xmm xmm -// VBROADCASTSS m32 xmm -// VBROADCASTSS xmm ymm -// VBROADCASTSS m32 ymm -// Construct and append a VBROADCASTSS instruction to the active function. -func (c *Context) VBROADCASTSS(mx, xy operand.Op) { - if inst, err := x86.VBROADCASTSS(mx, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPTESTNMB m512 zmm k k +// VPTESTNMB m512 zmm k +// VPTESTNMB zmm zmm k k +// VPTESTNMB zmm zmm k +// VPTESTNMB m128 xmm k k +// VPTESTNMB m128 xmm k +// VPTESTNMB m256 ymm k k +// VPTESTNMB m256 ymm k +// VPTESTNMB xmm xmm k k +// VPTESTNMB xmm xmm k +// VPTESTNMB ymm ymm k k +// VPTESTNMB ymm ymm k +// Construct and append a VPTESTNMB instruction to the active function. +func (c *Context) VPTESTNMB(ops ...operand.Op) { + c.addinstruction(x86.VPTESTNMB(ops...)) } -// VBROADCASTSS: Broadcast Single-Precision Floating-Point Element. +// VPTESTNMB: Logical NAND of Packed Byte Integer Values and Set Mask. // // Forms: // -// VBROADCASTSS xmm xmm -// VBROADCASTSS m32 xmm -// VBROADCASTSS xmm ymm -// VBROADCASTSS m32 ymm -// Construct and append a VBROADCASTSS instruction to the active function. +// VPTESTNMB m512 zmm k k +// VPTESTNMB m512 zmm k +// VPTESTNMB zmm zmm k k +// VPTESTNMB zmm zmm k +// VPTESTNMB m128 xmm k k +// VPTESTNMB m128 xmm k +// VPTESTNMB m256 ymm k k +// VPTESTNMB m256 ymm k +// VPTESTNMB xmm xmm k k +// VPTESTNMB xmm xmm k +// VPTESTNMB ymm ymm k k +// VPTESTNMB ymm ymm k +// Construct and append a VPTESTNMB instruction to the active function. // Operates on the global context. -func VBROADCASTSS(mx, xy operand.Op) { ctx.VBROADCASTSS(mx, xy) } +func VPTESTNMB(ops ...operand.Op) { ctx.VPTESTNMB(ops...) } -// VCMPPD: Compare Packed Double-Precision Floating-Point Values. +// VPTESTNMD: Logical NAND of Packed Doubleword Integer Values and Set Mask. // // Forms: // -// VCMPPD imm8 xmm xmm xmm -// VCMPPD imm8 m128 xmm xmm -// VCMPPD imm8 ymm ymm ymm -// VCMPPD imm8 m256 ymm ymm -// Construct and append a VCMPPD instruction to the active function. -func (c *Context) VCMPPD(i, mxy, xy, xy1 operand.Op) { - if inst, err := x86.VCMPPD(i, mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPTESTNMD m128 xmm k k +// VPTESTNMD m128 xmm k +// VPTESTNMD m256 ymm k k +// VPTESTNMD m256 ymm k +// VPTESTNMD xmm xmm k k +// VPTESTNMD xmm xmm k +// VPTESTNMD ymm ymm k k +// VPTESTNMD ymm ymm k +// VPTESTNMD m512 zmm k k +// VPTESTNMD m512 zmm k +// VPTESTNMD zmm zmm k k +// VPTESTNMD zmm zmm k +// Construct and append a VPTESTNMD instruction to the active function. +func (c *Context) VPTESTNMD(ops ...operand.Op) { + c.addinstruction(x86.VPTESTNMD(ops...)) } -// VCMPPD: Compare Packed Double-Precision Floating-Point Values. +// VPTESTNMD: Logical NAND of Packed Doubleword Integer Values and Set Mask. // // Forms: // -// VCMPPD imm8 xmm xmm xmm -// VCMPPD imm8 m128 xmm xmm -// VCMPPD imm8 ymm ymm ymm -// VCMPPD imm8 m256 ymm ymm -// Construct and append a VCMPPD instruction to the active function. +// VPTESTNMD m128 xmm k k +// VPTESTNMD m128 xmm k +// VPTESTNMD m256 ymm k k +// VPTESTNMD m256 ymm k +// VPTESTNMD xmm xmm k k +// VPTESTNMD xmm xmm k +// VPTESTNMD ymm ymm k k +// VPTESTNMD ymm ymm k +// VPTESTNMD m512 zmm k k +// VPTESTNMD m512 zmm k +// VPTESTNMD zmm zmm k k +// VPTESTNMD zmm zmm k +// Construct and append a VPTESTNMD instruction to the active function. // Operates on the global context. -func VCMPPD(i, mxy, xy, xy1 operand.Op) { ctx.VCMPPD(i, mxy, xy, xy1) } +func VPTESTNMD(ops ...operand.Op) { ctx.VPTESTNMD(ops...) } -// VCMPPS: Compare Packed Single-Precision Floating-Point Values. +// VPTESTNMD_BCST: Logical NAND of Packed Doubleword Integer Values and Set Mask (Broadcast). // // Forms: // -// VCMPPS imm8 xmm xmm xmm -// VCMPPS imm8 m128 xmm xmm -// VCMPPS imm8 ymm ymm ymm -// VCMPPS imm8 m256 ymm ymm -// Construct and append a VCMPPS instruction to the active function. -func (c *Context) VCMPPS(i, mxy, xy, xy1 operand.Op) { - if inst, err := x86.VCMPPS(i, mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPTESTNMD.BCST m32 xmm k k +// VPTESTNMD.BCST m32 xmm k +// VPTESTNMD.BCST m32 ymm k k +// VPTESTNMD.BCST m32 ymm k +// VPTESTNMD.BCST m32 zmm k k +// VPTESTNMD.BCST m32 zmm k +// Construct and append a VPTESTNMD.BCST instruction to the active function. +func (c *Context) VPTESTNMD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPTESTNMD_BCST(ops...)) } -// VCMPPS: Compare Packed Single-Precision Floating-Point Values. +// VPTESTNMD_BCST: Logical NAND of Packed Doubleword Integer Values and Set Mask (Broadcast). // // Forms: // -// VCMPPS imm8 xmm xmm xmm -// VCMPPS imm8 m128 xmm xmm -// VCMPPS imm8 ymm ymm ymm -// VCMPPS imm8 m256 ymm ymm -// Construct and append a VCMPPS instruction to the active function. +// VPTESTNMD.BCST m32 xmm k k +// VPTESTNMD.BCST m32 xmm k +// VPTESTNMD.BCST m32 ymm k k +// VPTESTNMD.BCST m32 ymm k +// VPTESTNMD.BCST m32 zmm k k +// VPTESTNMD.BCST m32 zmm k +// Construct and append a VPTESTNMD.BCST instruction to the active function. // Operates on the global context. -func VCMPPS(i, mxy, xy, xy1 operand.Op) { ctx.VCMPPS(i, mxy, xy, xy1) } +func VPTESTNMD_BCST(ops ...operand.Op) { ctx.VPTESTNMD_BCST(ops...) } -// VCMPSD: Compare Scalar Double-Precision Floating-Point Values. +// VPTESTNMQ: Logical NAND of Packed Quadword Integer Values and Set Mask. // // Forms: // -// VCMPSD imm8 xmm xmm xmm -// VCMPSD imm8 m64 xmm xmm -// Construct and append a VCMPSD instruction to the active function. -func (c *Context) VCMPSD(i, mx, x, x1 operand.Op) { - if inst, err := x86.VCMPSD(i, mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPTESTNMQ m128 xmm k k +// VPTESTNMQ m128 xmm k +// VPTESTNMQ m256 ymm k k +// VPTESTNMQ m256 ymm k +// VPTESTNMQ xmm xmm k k +// VPTESTNMQ xmm xmm k +// VPTESTNMQ ymm ymm k k +// VPTESTNMQ ymm ymm k +// VPTESTNMQ m512 zmm k k +// VPTESTNMQ m512 zmm k +// VPTESTNMQ zmm zmm k k +// VPTESTNMQ zmm zmm k +// Construct and append a VPTESTNMQ instruction to the active function. +func (c *Context) VPTESTNMQ(ops ...operand.Op) { + c.addinstruction(x86.VPTESTNMQ(ops...)) } -// VCMPSD: Compare Scalar Double-Precision Floating-Point Values. +// VPTESTNMQ: Logical NAND of Packed Quadword Integer Values and Set Mask. // // Forms: // -// VCMPSD imm8 xmm xmm xmm -// VCMPSD imm8 m64 xmm xmm -// Construct and append a VCMPSD instruction to the active function. +// VPTESTNMQ m128 xmm k k +// VPTESTNMQ m128 xmm k +// VPTESTNMQ m256 ymm k k +// VPTESTNMQ m256 ymm k +// VPTESTNMQ xmm xmm k k +// VPTESTNMQ xmm xmm k +// VPTESTNMQ ymm ymm k k +// VPTESTNMQ ymm ymm k +// VPTESTNMQ m512 zmm k k +// VPTESTNMQ m512 zmm k +// VPTESTNMQ zmm zmm k k +// VPTESTNMQ zmm zmm k +// Construct and append a VPTESTNMQ instruction to the active function. // Operates on the global context. -func VCMPSD(i, mx, x, x1 operand.Op) { ctx.VCMPSD(i, mx, x, x1) } +func VPTESTNMQ(ops ...operand.Op) { ctx.VPTESTNMQ(ops...) } -// VCMPSS: Compare Scalar Single-Precision Floating-Point Values. +// VPTESTNMQ_BCST: Logical NAND of Packed Quadword Integer Values and Set Mask (Broadcast). // // Forms: // -// VCMPSS imm8 xmm xmm xmm -// VCMPSS imm8 m32 xmm xmm -// Construct and append a VCMPSS instruction to the active function. -func (c *Context) VCMPSS(i, mx, x, x1 operand.Op) { - if inst, err := x86.VCMPSS(i, mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPTESTNMQ.BCST m64 xmm k k +// VPTESTNMQ.BCST m64 xmm k +// VPTESTNMQ.BCST m64 ymm k k +// VPTESTNMQ.BCST m64 ymm k +// VPTESTNMQ.BCST m64 zmm k k +// VPTESTNMQ.BCST m64 zmm k +// Construct and append a VPTESTNMQ.BCST instruction to the active function. +func (c *Context) VPTESTNMQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPTESTNMQ_BCST(ops...)) } -// VCMPSS: Compare Scalar Single-Precision Floating-Point Values. +// VPTESTNMQ_BCST: Logical NAND of Packed Quadword Integer Values and Set Mask (Broadcast). // // Forms: // -// VCMPSS imm8 xmm xmm xmm -// VCMPSS imm8 m32 xmm xmm -// Construct and append a VCMPSS instruction to the active function. +// VPTESTNMQ.BCST m64 xmm k k +// VPTESTNMQ.BCST m64 xmm k +// VPTESTNMQ.BCST m64 ymm k k +// VPTESTNMQ.BCST m64 ymm k +// VPTESTNMQ.BCST m64 zmm k k +// VPTESTNMQ.BCST m64 zmm k +// Construct and append a VPTESTNMQ.BCST instruction to the active function. // Operates on the global context. -func VCMPSS(i, mx, x, x1 operand.Op) { ctx.VCMPSS(i, mx, x, x1) } +func VPTESTNMQ_BCST(ops ...operand.Op) { ctx.VPTESTNMQ_BCST(ops...) } -// VCOMISD: Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS. +// VPTESTNMW: Logical NAND of Packed Word Integer Values and Set Mask. // // Forms: // -// VCOMISD xmm xmm -// VCOMISD m64 xmm -// Construct and append a VCOMISD instruction to the active function. -func (c *Context) VCOMISD(mx, x operand.Op) { - if inst, err := x86.VCOMISD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPTESTNMW m512 zmm k k +// VPTESTNMW m512 zmm k +// VPTESTNMW zmm zmm k k +// VPTESTNMW zmm zmm k +// VPTESTNMW m128 xmm k k +// VPTESTNMW m128 xmm k +// VPTESTNMW m256 ymm k k +// VPTESTNMW m256 ymm k +// VPTESTNMW xmm xmm k k +// VPTESTNMW xmm xmm k +// VPTESTNMW ymm ymm k k +// VPTESTNMW ymm ymm k +// Construct and append a VPTESTNMW instruction to the active function. +func (c *Context) VPTESTNMW(ops ...operand.Op) { + c.addinstruction(x86.VPTESTNMW(ops...)) } -// VCOMISD: Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS. +// VPTESTNMW: Logical NAND of Packed Word Integer Values and Set Mask. // // Forms: // -// VCOMISD xmm xmm -// VCOMISD m64 xmm -// Construct and append a VCOMISD instruction to the active function. +// VPTESTNMW m512 zmm k k +// VPTESTNMW m512 zmm k +// VPTESTNMW zmm zmm k k +// VPTESTNMW zmm zmm k +// VPTESTNMW m128 xmm k k +// VPTESTNMW m128 xmm k +// VPTESTNMW m256 ymm k k +// VPTESTNMW m256 ymm k +// VPTESTNMW xmm xmm k k +// VPTESTNMW xmm xmm k +// VPTESTNMW ymm ymm k k +// VPTESTNMW ymm ymm k +// Construct and append a VPTESTNMW instruction to the active function. // Operates on the global context. -func VCOMISD(mx, x operand.Op) { ctx.VCOMISD(mx, x) } +func VPTESTNMW(ops ...operand.Op) { ctx.VPTESTNMW(ops...) } -// VCOMISS: Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS. +// VPUNPCKHBW: Unpack and Interleave High-Order Bytes into Words. // // Forms: // -// VCOMISS xmm xmm -// VCOMISS m32 xmm -// Construct and append a VCOMISS instruction to the active function. -func (c *Context) VCOMISS(mx, x operand.Op) { - if inst, err := x86.VCOMISS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPUNPCKHBW m256 ymm ymm +// VPUNPCKHBW ymm ymm ymm +// VPUNPCKHBW m128 xmm xmm +// VPUNPCKHBW xmm xmm xmm +// VPUNPCKHBW m128 xmm k xmm +// VPUNPCKHBW m256 ymm k ymm +// VPUNPCKHBW xmm xmm k xmm +// VPUNPCKHBW ymm ymm k ymm +// VPUNPCKHBW m512 zmm k zmm +// VPUNPCKHBW m512 zmm zmm +// VPUNPCKHBW zmm zmm k zmm +// VPUNPCKHBW zmm zmm zmm +// Construct and append a VPUNPCKHBW instruction to the active function. +func (c *Context) VPUNPCKHBW(ops ...operand.Op) { + c.addinstruction(x86.VPUNPCKHBW(ops...)) } -// VCOMISS: Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS. +// VPUNPCKHBW: Unpack and Interleave High-Order Bytes into Words. // // Forms: // -// VCOMISS xmm xmm -// VCOMISS m32 xmm -// Construct and append a VCOMISS instruction to the active function. +// VPUNPCKHBW m256 ymm ymm +// VPUNPCKHBW ymm ymm ymm +// VPUNPCKHBW m128 xmm xmm +// VPUNPCKHBW xmm xmm xmm +// VPUNPCKHBW m128 xmm k xmm +// VPUNPCKHBW m256 ymm k ymm +// VPUNPCKHBW xmm xmm k xmm +// VPUNPCKHBW ymm ymm k ymm +// VPUNPCKHBW m512 zmm k zmm +// VPUNPCKHBW m512 zmm zmm +// VPUNPCKHBW zmm zmm k zmm +// VPUNPCKHBW zmm zmm zmm +// Construct and append a VPUNPCKHBW instruction to the active function. // Operates on the global context. -func VCOMISS(mx, x operand.Op) { ctx.VCOMISS(mx, x) } +func VPUNPCKHBW(ops ...operand.Op) { ctx.VPUNPCKHBW(ops...) } -// VCVTDQ2PD: Convert Packed Dword Integers to Packed Double-Precision FP Values. +// VPUNPCKHBW_Z: Unpack and Interleave High-Order Bytes into Words (Zeroing Masking). // // Forms: // -// VCVTDQ2PD xmm xmm -// VCVTDQ2PD m64 xmm -// VCVTDQ2PD xmm ymm -// VCVTDQ2PD m128 ymm -// Construct and append a VCVTDQ2PD instruction to the active function. -func (c *Context) VCVTDQ2PD(mx, xy operand.Op) { - if inst, err := x86.VCVTDQ2PD(mx, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPUNPCKHBW.Z m128 xmm k xmm +// VPUNPCKHBW.Z m256 ymm k ymm +// VPUNPCKHBW.Z xmm xmm k xmm +// VPUNPCKHBW.Z ymm ymm k ymm +// VPUNPCKHBW.Z m512 zmm k zmm +// VPUNPCKHBW.Z zmm zmm k zmm +// Construct and append a VPUNPCKHBW.Z instruction to the active function. +func (c *Context) VPUNPCKHBW_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPUNPCKHBW_Z(mxyz, xyz, k, xyz1)) } -// VCVTDQ2PD: Convert Packed Dword Integers to Packed Double-Precision FP Values. +// VPUNPCKHBW_Z: Unpack and Interleave High-Order Bytes into Words (Zeroing Masking). // // Forms: // -// VCVTDQ2PD xmm xmm -// VCVTDQ2PD m64 xmm -// VCVTDQ2PD xmm ymm -// VCVTDQ2PD m128 ymm -// Construct and append a VCVTDQ2PD instruction to the active function. +// VPUNPCKHBW.Z m128 xmm k xmm +// VPUNPCKHBW.Z m256 ymm k ymm +// VPUNPCKHBW.Z xmm xmm k xmm +// VPUNPCKHBW.Z ymm ymm k ymm +// VPUNPCKHBW.Z m512 zmm k zmm +// VPUNPCKHBW.Z zmm zmm k zmm +// Construct and append a VPUNPCKHBW.Z instruction to the active function. // Operates on the global context. -func VCVTDQ2PD(mx, xy operand.Op) { ctx.VCVTDQ2PD(mx, xy) } +func VPUNPCKHBW_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPUNPCKHBW_Z(mxyz, xyz, k, xyz1) } -// VCVTDQ2PS: Convert Packed Dword Integers to Packed Single-Precision FP Values. +// VPUNPCKHDQ: Unpack and Interleave High-Order Doublewords into Quadwords. // // Forms: // -// VCVTDQ2PS xmm xmm -// VCVTDQ2PS m128 xmm -// VCVTDQ2PS ymm ymm -// VCVTDQ2PS m256 ymm -// Construct and append a VCVTDQ2PS instruction to the active function. -func (c *Context) VCVTDQ2PS(mxy, xy operand.Op) { - if inst, err := x86.VCVTDQ2PS(mxy, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPUNPCKHDQ m256 ymm ymm +// VPUNPCKHDQ ymm ymm ymm +// VPUNPCKHDQ m128 xmm xmm +// VPUNPCKHDQ xmm xmm xmm +// VPUNPCKHDQ m128 xmm k xmm +// VPUNPCKHDQ m256 ymm k ymm +// VPUNPCKHDQ xmm xmm k xmm +// VPUNPCKHDQ ymm ymm k ymm +// VPUNPCKHDQ m512 zmm k zmm +// VPUNPCKHDQ m512 zmm zmm +// VPUNPCKHDQ zmm zmm k zmm +// VPUNPCKHDQ zmm zmm zmm +// Construct and append a VPUNPCKHDQ instruction to the active function. +func (c *Context) VPUNPCKHDQ(ops ...operand.Op) { + c.addinstruction(x86.VPUNPCKHDQ(ops...)) } -// VCVTDQ2PS: Convert Packed Dword Integers to Packed Single-Precision FP Values. +// VPUNPCKHDQ: Unpack and Interleave High-Order Doublewords into Quadwords. // // Forms: // -// VCVTDQ2PS xmm xmm -// VCVTDQ2PS m128 xmm -// VCVTDQ2PS ymm ymm -// VCVTDQ2PS m256 ymm -// Construct and append a VCVTDQ2PS instruction to the active function. +// VPUNPCKHDQ m256 ymm ymm +// VPUNPCKHDQ ymm ymm ymm +// VPUNPCKHDQ m128 xmm xmm +// VPUNPCKHDQ xmm xmm xmm +// VPUNPCKHDQ m128 xmm k xmm +// VPUNPCKHDQ m256 ymm k ymm +// VPUNPCKHDQ xmm xmm k xmm +// VPUNPCKHDQ ymm ymm k ymm +// VPUNPCKHDQ m512 zmm k zmm +// VPUNPCKHDQ m512 zmm zmm +// VPUNPCKHDQ zmm zmm k zmm +// VPUNPCKHDQ zmm zmm zmm +// Construct and append a VPUNPCKHDQ instruction to the active function. // Operates on the global context. -func VCVTDQ2PS(mxy, xy operand.Op) { ctx.VCVTDQ2PS(mxy, xy) } +func VPUNPCKHDQ(ops ...operand.Op) { ctx.VPUNPCKHDQ(ops...) } -// VCVTPD2DQX: Convert Packed Double-Precision FP Values to Packed Dword Integers. +// VPUNPCKHDQ_BCST: Unpack and Interleave High-Order Doublewords into Quadwords (Broadcast). // // Forms: // -// VCVTPD2DQX xmm xmm -// VCVTPD2DQX m128 xmm -// Construct and append a VCVTPD2DQX instruction to the active function. -func (c *Context) VCVTPD2DQX(mx, x operand.Op) { - if inst, err := x86.VCVTPD2DQX(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPUNPCKHDQ.BCST m32 xmm k xmm +// VPUNPCKHDQ.BCST m32 xmm xmm +// VPUNPCKHDQ.BCST m32 ymm k ymm +// VPUNPCKHDQ.BCST m32 ymm ymm +// VPUNPCKHDQ.BCST m32 zmm k zmm +// VPUNPCKHDQ.BCST m32 zmm zmm +// Construct and append a VPUNPCKHDQ.BCST instruction to the active function. +func (c *Context) VPUNPCKHDQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPUNPCKHDQ_BCST(ops...)) } -// VCVTPD2DQX: Convert Packed Double-Precision FP Values to Packed Dword Integers. +// VPUNPCKHDQ_BCST: Unpack and Interleave High-Order Doublewords into Quadwords (Broadcast). // // Forms: // -// VCVTPD2DQX xmm xmm -// VCVTPD2DQX m128 xmm -// Construct and append a VCVTPD2DQX instruction to the active function. +// VPUNPCKHDQ.BCST m32 xmm k xmm +// VPUNPCKHDQ.BCST m32 xmm xmm +// VPUNPCKHDQ.BCST m32 ymm k ymm +// VPUNPCKHDQ.BCST m32 ymm ymm +// VPUNPCKHDQ.BCST m32 zmm k zmm +// VPUNPCKHDQ.BCST m32 zmm zmm +// Construct and append a VPUNPCKHDQ.BCST instruction to the active function. // Operates on the global context. -func VCVTPD2DQX(mx, x operand.Op) { ctx.VCVTPD2DQX(mx, x) } +func VPUNPCKHDQ_BCST(ops ...operand.Op) { ctx.VPUNPCKHDQ_BCST(ops...) } -// VCVTPD2DQY: Convert Packed Double-Precision FP Values to Packed Dword Integers. +// VPUNPCKHDQ_BCST_Z: Unpack and Interleave High-Order Doublewords into Quadwords (Broadcast, Zeroing Masking). // // Forms: // -// VCVTPD2DQY ymm xmm -// VCVTPD2DQY m256 xmm -// Construct and append a VCVTPD2DQY instruction to the active function. -func (c *Context) VCVTPD2DQY(my, x operand.Op) { - if inst, err := x86.VCVTPD2DQY(my, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPUNPCKHDQ.BCST.Z m32 xmm k xmm +// VPUNPCKHDQ.BCST.Z m32 ymm k ymm +// VPUNPCKHDQ.BCST.Z m32 zmm k zmm +// Construct and append a VPUNPCKHDQ.BCST.Z instruction to the active function. +func (c *Context) VPUNPCKHDQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPUNPCKHDQ_BCST_Z(m, xyz, k, xyz1)) } -// VCVTPD2DQY: Convert Packed Double-Precision FP Values to Packed Dword Integers. +// VPUNPCKHDQ_BCST_Z: Unpack and Interleave High-Order Doublewords into Quadwords (Broadcast, Zeroing Masking). // // Forms: // -// VCVTPD2DQY ymm xmm -// VCVTPD2DQY m256 xmm -// Construct and append a VCVTPD2DQY instruction to the active function. +// VPUNPCKHDQ.BCST.Z m32 xmm k xmm +// VPUNPCKHDQ.BCST.Z m32 ymm k ymm +// VPUNPCKHDQ.BCST.Z m32 zmm k zmm +// Construct and append a VPUNPCKHDQ.BCST.Z instruction to the active function. // Operates on the global context. -func VCVTPD2DQY(my, x operand.Op) { ctx.VCVTPD2DQY(my, x) } +func VPUNPCKHDQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPUNPCKHDQ_BCST_Z(m, xyz, k, xyz1) } -// VCVTPD2PSX: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values. +// VPUNPCKHDQ_Z: Unpack and Interleave High-Order Doublewords into Quadwords (Zeroing Masking). // // Forms: // -// VCVTPD2PSX xmm xmm -// VCVTPD2PSX m128 xmm -// Construct and append a VCVTPD2PSX instruction to the active function. -func (c *Context) VCVTPD2PSX(mx, x operand.Op) { - if inst, err := x86.VCVTPD2PSX(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPUNPCKHDQ.Z m128 xmm k xmm +// VPUNPCKHDQ.Z m256 ymm k ymm +// VPUNPCKHDQ.Z xmm xmm k xmm +// VPUNPCKHDQ.Z ymm ymm k ymm +// VPUNPCKHDQ.Z m512 zmm k zmm +// VPUNPCKHDQ.Z zmm zmm k zmm +// Construct and append a VPUNPCKHDQ.Z instruction to the active function. +func (c *Context) VPUNPCKHDQ_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPUNPCKHDQ_Z(mxyz, xyz, k, xyz1)) } -// VCVTPD2PSX: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values. +// VPUNPCKHDQ_Z: Unpack and Interleave High-Order Doublewords into Quadwords (Zeroing Masking). // // Forms: // -// VCVTPD2PSX xmm xmm -// VCVTPD2PSX m128 xmm -// Construct and append a VCVTPD2PSX instruction to the active function. +// VPUNPCKHDQ.Z m128 xmm k xmm +// VPUNPCKHDQ.Z m256 ymm k ymm +// VPUNPCKHDQ.Z xmm xmm k xmm +// VPUNPCKHDQ.Z ymm ymm k ymm +// VPUNPCKHDQ.Z m512 zmm k zmm +// VPUNPCKHDQ.Z zmm zmm k zmm +// Construct and append a VPUNPCKHDQ.Z instruction to the active function. // Operates on the global context. -func VCVTPD2PSX(mx, x operand.Op) { ctx.VCVTPD2PSX(mx, x) } +func VPUNPCKHDQ_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPUNPCKHDQ_Z(mxyz, xyz, k, xyz1) } -// VCVTPD2PSY: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values. +// VPUNPCKHQDQ: Unpack and Interleave High-Order Quadwords into Double Quadwords. // // Forms: // -// VCVTPD2PSY ymm xmm -// VCVTPD2PSY m256 xmm -// Construct and append a VCVTPD2PSY instruction to the active function. -func (c *Context) VCVTPD2PSY(my, x operand.Op) { - if inst, err := x86.VCVTPD2PSY(my, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPUNPCKHQDQ m256 ymm ymm +// VPUNPCKHQDQ ymm ymm ymm +// VPUNPCKHQDQ m128 xmm xmm +// VPUNPCKHQDQ xmm xmm xmm +// VPUNPCKHQDQ m128 xmm k xmm +// VPUNPCKHQDQ m256 ymm k ymm +// VPUNPCKHQDQ xmm xmm k xmm +// VPUNPCKHQDQ ymm ymm k ymm +// VPUNPCKHQDQ m512 zmm k zmm +// VPUNPCKHQDQ m512 zmm zmm +// VPUNPCKHQDQ zmm zmm k zmm +// VPUNPCKHQDQ zmm zmm zmm +// Construct and append a VPUNPCKHQDQ instruction to the active function. +func (c *Context) VPUNPCKHQDQ(ops ...operand.Op) { + c.addinstruction(x86.VPUNPCKHQDQ(ops...)) } -// VCVTPD2PSY: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values. +// VPUNPCKHQDQ: Unpack and Interleave High-Order Quadwords into Double Quadwords. // // Forms: // -// VCVTPD2PSY ymm xmm -// VCVTPD2PSY m256 xmm -// Construct and append a VCVTPD2PSY instruction to the active function. +// VPUNPCKHQDQ m256 ymm ymm +// VPUNPCKHQDQ ymm ymm ymm +// VPUNPCKHQDQ m128 xmm xmm +// VPUNPCKHQDQ xmm xmm xmm +// VPUNPCKHQDQ m128 xmm k xmm +// VPUNPCKHQDQ m256 ymm k ymm +// VPUNPCKHQDQ xmm xmm k xmm +// VPUNPCKHQDQ ymm ymm k ymm +// VPUNPCKHQDQ m512 zmm k zmm +// VPUNPCKHQDQ m512 zmm zmm +// VPUNPCKHQDQ zmm zmm k zmm +// VPUNPCKHQDQ zmm zmm zmm +// Construct and append a VPUNPCKHQDQ instruction to the active function. // Operates on the global context. -func VCVTPD2PSY(my, x operand.Op) { ctx.VCVTPD2PSY(my, x) } +func VPUNPCKHQDQ(ops ...operand.Op) { ctx.VPUNPCKHQDQ(ops...) } -// VCVTPH2PS: Convert Half-Precision FP Values to Single-Precision FP Values. +// VPUNPCKHQDQ_BCST: Unpack and Interleave High-Order Quadwords into Double Quadwords (Broadcast). // // Forms: // -// VCVTPH2PS xmm xmm -// VCVTPH2PS m64 xmm -// VCVTPH2PS xmm ymm -// VCVTPH2PS m128 ymm -// Construct and append a VCVTPH2PS instruction to the active function. -func (c *Context) VCVTPH2PS(mx, xy operand.Op) { - if inst, err := x86.VCVTPH2PS(mx, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPUNPCKHQDQ.BCST m64 xmm k xmm +// VPUNPCKHQDQ.BCST m64 xmm xmm +// VPUNPCKHQDQ.BCST m64 ymm k ymm +// VPUNPCKHQDQ.BCST m64 ymm ymm +// VPUNPCKHQDQ.BCST m64 zmm k zmm +// VPUNPCKHQDQ.BCST m64 zmm zmm +// Construct and append a VPUNPCKHQDQ.BCST instruction to the active function. +func (c *Context) VPUNPCKHQDQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPUNPCKHQDQ_BCST(ops...)) } -// VCVTPH2PS: Convert Half-Precision FP Values to Single-Precision FP Values. +// VPUNPCKHQDQ_BCST: Unpack and Interleave High-Order Quadwords into Double Quadwords (Broadcast). // // Forms: // -// VCVTPH2PS xmm xmm -// VCVTPH2PS m64 xmm -// VCVTPH2PS xmm ymm -// VCVTPH2PS m128 ymm -// Construct and append a VCVTPH2PS instruction to the active function. +// VPUNPCKHQDQ.BCST m64 xmm k xmm +// VPUNPCKHQDQ.BCST m64 xmm xmm +// VPUNPCKHQDQ.BCST m64 ymm k ymm +// VPUNPCKHQDQ.BCST m64 ymm ymm +// VPUNPCKHQDQ.BCST m64 zmm k zmm +// VPUNPCKHQDQ.BCST m64 zmm zmm +// Construct and append a VPUNPCKHQDQ.BCST instruction to the active function. // Operates on the global context. -func VCVTPH2PS(mx, xy operand.Op) { ctx.VCVTPH2PS(mx, xy) } +func VPUNPCKHQDQ_BCST(ops ...operand.Op) { ctx.VPUNPCKHQDQ_BCST(ops...) } -// VCVTPS2DQ: Convert Packed Single-Precision FP Values to Packed Dword Integers. +// VPUNPCKHQDQ_BCST_Z: Unpack and Interleave High-Order Quadwords into Double Quadwords (Broadcast, Zeroing Masking). // // Forms: // -// VCVTPS2DQ xmm xmm -// VCVTPS2DQ m128 xmm -// VCVTPS2DQ ymm ymm -// VCVTPS2DQ m256 ymm -// Construct and append a VCVTPS2DQ instruction to the active function. -func (c *Context) VCVTPS2DQ(mxy, xy operand.Op) { - if inst, err := x86.VCVTPS2DQ(mxy, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPUNPCKHQDQ.BCST.Z m64 xmm k xmm +// VPUNPCKHQDQ.BCST.Z m64 ymm k ymm +// VPUNPCKHQDQ.BCST.Z m64 zmm k zmm +// Construct and append a VPUNPCKHQDQ.BCST.Z instruction to the active function. +func (c *Context) VPUNPCKHQDQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPUNPCKHQDQ_BCST_Z(m, xyz, k, xyz1)) } -// VCVTPS2DQ: Convert Packed Single-Precision FP Values to Packed Dword Integers. +// VPUNPCKHQDQ_BCST_Z: Unpack and Interleave High-Order Quadwords into Double Quadwords (Broadcast, Zeroing Masking). // // Forms: // -// VCVTPS2DQ xmm xmm -// VCVTPS2DQ m128 xmm -// VCVTPS2DQ ymm ymm -// VCVTPS2DQ m256 ymm -// Construct and append a VCVTPS2DQ instruction to the active function. +// VPUNPCKHQDQ.BCST.Z m64 xmm k xmm +// VPUNPCKHQDQ.BCST.Z m64 ymm k ymm +// VPUNPCKHQDQ.BCST.Z m64 zmm k zmm +// Construct and append a VPUNPCKHQDQ.BCST.Z instruction to the active function. // Operates on the global context. -func VCVTPS2DQ(mxy, xy operand.Op) { ctx.VCVTPS2DQ(mxy, xy) } +func VPUNPCKHQDQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPUNPCKHQDQ_BCST_Z(m, xyz, k, xyz1) } -// VCVTPS2PD: Convert Packed Single-Precision FP Values to Packed Double-Precision FP Values. +// VPUNPCKHQDQ_Z: Unpack and Interleave High-Order Quadwords into Double Quadwords (Zeroing Masking). // // Forms: // -// VCVTPS2PD xmm xmm -// VCVTPS2PD m64 xmm -// VCVTPS2PD xmm ymm -// VCVTPS2PD m128 ymm -// Construct and append a VCVTPS2PD instruction to the active function. -func (c *Context) VCVTPS2PD(mx, xy operand.Op) { - if inst, err := x86.VCVTPS2PD(mx, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPUNPCKHQDQ.Z m128 xmm k xmm +// VPUNPCKHQDQ.Z m256 ymm k ymm +// VPUNPCKHQDQ.Z xmm xmm k xmm +// VPUNPCKHQDQ.Z ymm ymm k ymm +// VPUNPCKHQDQ.Z m512 zmm k zmm +// VPUNPCKHQDQ.Z zmm zmm k zmm +// Construct and append a VPUNPCKHQDQ.Z instruction to the active function. +func (c *Context) VPUNPCKHQDQ_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPUNPCKHQDQ_Z(mxyz, xyz, k, xyz1)) } -// VCVTPS2PD: Convert Packed Single-Precision FP Values to Packed Double-Precision FP Values. +// VPUNPCKHQDQ_Z: Unpack and Interleave High-Order Quadwords into Double Quadwords (Zeroing Masking). // // Forms: // -// VCVTPS2PD xmm xmm -// VCVTPS2PD m64 xmm -// VCVTPS2PD xmm ymm -// VCVTPS2PD m128 ymm -// Construct and append a VCVTPS2PD instruction to the active function. +// VPUNPCKHQDQ.Z m128 xmm k xmm +// VPUNPCKHQDQ.Z m256 ymm k ymm +// VPUNPCKHQDQ.Z xmm xmm k xmm +// VPUNPCKHQDQ.Z ymm ymm k ymm +// VPUNPCKHQDQ.Z m512 zmm k zmm +// VPUNPCKHQDQ.Z zmm zmm k zmm +// Construct and append a VPUNPCKHQDQ.Z instruction to the active function. // Operates on the global context. -func VCVTPS2PD(mx, xy operand.Op) { ctx.VCVTPS2PD(mx, xy) } +func VPUNPCKHQDQ_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPUNPCKHQDQ_Z(mxyz, xyz, k, xyz1) } -// VCVTPS2PH: Convert Single-Precision FP value to Half-Precision FP value. +// VPUNPCKHWD: Unpack and Interleave High-Order Words into Doublewords. // // Forms: // -// VCVTPS2PH imm8 xmm xmm -// VCVTPS2PH imm8 ymm xmm -// VCVTPS2PH imm8 xmm m64 -// VCVTPS2PH imm8 ymm m128 -// Construct and append a VCVTPS2PH instruction to the active function. -func (c *Context) VCVTPS2PH(i, xy, mx operand.Op) { - if inst, err := x86.VCVTPS2PH(i, xy, mx); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPUNPCKHWD m256 ymm ymm +// VPUNPCKHWD ymm ymm ymm +// VPUNPCKHWD m128 xmm xmm +// VPUNPCKHWD xmm xmm xmm +// VPUNPCKHWD m128 xmm k xmm +// VPUNPCKHWD m256 ymm k ymm +// VPUNPCKHWD xmm xmm k xmm +// VPUNPCKHWD ymm ymm k ymm +// VPUNPCKHWD m512 zmm k zmm +// VPUNPCKHWD m512 zmm zmm +// VPUNPCKHWD zmm zmm k zmm +// VPUNPCKHWD zmm zmm zmm +// Construct and append a VPUNPCKHWD instruction to the active function. +func (c *Context) VPUNPCKHWD(ops ...operand.Op) { + c.addinstruction(x86.VPUNPCKHWD(ops...)) } -// VCVTPS2PH: Convert Single-Precision FP value to Half-Precision FP value. +// VPUNPCKHWD: Unpack and Interleave High-Order Words into Doublewords. // // Forms: // -// VCVTPS2PH imm8 xmm xmm -// VCVTPS2PH imm8 ymm xmm -// VCVTPS2PH imm8 xmm m64 -// VCVTPS2PH imm8 ymm m128 -// Construct and append a VCVTPS2PH instruction to the active function. +// VPUNPCKHWD m256 ymm ymm +// VPUNPCKHWD ymm ymm ymm +// VPUNPCKHWD m128 xmm xmm +// VPUNPCKHWD xmm xmm xmm +// VPUNPCKHWD m128 xmm k xmm +// VPUNPCKHWD m256 ymm k ymm +// VPUNPCKHWD xmm xmm k xmm +// VPUNPCKHWD ymm ymm k ymm +// VPUNPCKHWD m512 zmm k zmm +// VPUNPCKHWD m512 zmm zmm +// VPUNPCKHWD zmm zmm k zmm +// VPUNPCKHWD zmm zmm zmm +// Construct and append a VPUNPCKHWD instruction to the active function. // Operates on the global context. -func VCVTPS2PH(i, xy, mx operand.Op) { ctx.VCVTPS2PH(i, xy, mx) } +func VPUNPCKHWD(ops ...operand.Op) { ctx.VPUNPCKHWD(ops...) } -// VCVTSD2SI: Convert Scalar Double-Precision FP Value to Integer. +// VPUNPCKHWD_Z: Unpack and Interleave High-Order Words into Doublewords (Zeroing Masking). // // Forms: // -// VCVTSD2SI xmm r32 -// VCVTSD2SI m64 r32 -// Construct and append a VCVTSD2SI instruction to the active function. -func (c *Context) VCVTSD2SI(mx, r operand.Op) { - if inst, err := x86.VCVTSD2SI(mx, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPUNPCKHWD.Z m128 xmm k xmm +// VPUNPCKHWD.Z m256 ymm k ymm +// VPUNPCKHWD.Z xmm xmm k xmm +// VPUNPCKHWD.Z ymm ymm k ymm +// VPUNPCKHWD.Z m512 zmm k zmm +// VPUNPCKHWD.Z zmm zmm k zmm +// Construct and append a VPUNPCKHWD.Z instruction to the active function. +func (c *Context) VPUNPCKHWD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPUNPCKHWD_Z(mxyz, xyz, k, xyz1)) } -// VCVTSD2SI: Convert Scalar Double-Precision FP Value to Integer. +// VPUNPCKHWD_Z: Unpack and Interleave High-Order Words into Doublewords (Zeroing Masking). // // Forms: // -// VCVTSD2SI xmm r32 -// VCVTSD2SI m64 r32 -// Construct and append a VCVTSD2SI instruction to the active function. +// VPUNPCKHWD.Z m128 xmm k xmm +// VPUNPCKHWD.Z m256 ymm k ymm +// VPUNPCKHWD.Z xmm xmm k xmm +// VPUNPCKHWD.Z ymm ymm k ymm +// VPUNPCKHWD.Z m512 zmm k zmm +// VPUNPCKHWD.Z zmm zmm k zmm +// Construct and append a VPUNPCKHWD.Z instruction to the active function. // Operates on the global context. -func VCVTSD2SI(mx, r operand.Op) { ctx.VCVTSD2SI(mx, r) } +func VPUNPCKHWD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPUNPCKHWD_Z(mxyz, xyz, k, xyz1) } -// VCVTSD2SIQ: Convert Scalar Double-Precision FP Value to Integer. +// VPUNPCKLBW: Unpack and Interleave Low-Order Bytes into Words. // // Forms: // -// VCVTSD2SIQ xmm r64 -// VCVTSD2SIQ m64 r64 -// Construct and append a VCVTSD2SIQ instruction to the active function. -func (c *Context) VCVTSD2SIQ(mx, r operand.Op) { - if inst, err := x86.VCVTSD2SIQ(mx, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPUNPCKLBW m256 ymm ymm +// VPUNPCKLBW ymm ymm ymm +// VPUNPCKLBW m128 xmm xmm +// VPUNPCKLBW xmm xmm xmm +// VPUNPCKLBW m128 xmm k xmm +// VPUNPCKLBW m256 ymm k ymm +// VPUNPCKLBW xmm xmm k xmm +// VPUNPCKLBW ymm ymm k ymm +// VPUNPCKLBW m512 zmm k zmm +// VPUNPCKLBW m512 zmm zmm +// VPUNPCKLBW zmm zmm k zmm +// VPUNPCKLBW zmm zmm zmm +// Construct and append a VPUNPCKLBW instruction to the active function. +func (c *Context) VPUNPCKLBW(ops ...operand.Op) { + c.addinstruction(x86.VPUNPCKLBW(ops...)) } -// VCVTSD2SIQ: Convert Scalar Double-Precision FP Value to Integer. +// VPUNPCKLBW: Unpack and Interleave Low-Order Bytes into Words. // // Forms: // -// VCVTSD2SIQ xmm r64 -// VCVTSD2SIQ m64 r64 -// Construct and append a VCVTSD2SIQ instruction to the active function. +// VPUNPCKLBW m256 ymm ymm +// VPUNPCKLBW ymm ymm ymm +// VPUNPCKLBW m128 xmm xmm +// VPUNPCKLBW xmm xmm xmm +// VPUNPCKLBW m128 xmm k xmm +// VPUNPCKLBW m256 ymm k ymm +// VPUNPCKLBW xmm xmm k xmm +// VPUNPCKLBW ymm ymm k ymm +// VPUNPCKLBW m512 zmm k zmm +// VPUNPCKLBW m512 zmm zmm +// VPUNPCKLBW zmm zmm k zmm +// VPUNPCKLBW zmm zmm zmm +// Construct and append a VPUNPCKLBW instruction to the active function. // Operates on the global context. -func VCVTSD2SIQ(mx, r operand.Op) { ctx.VCVTSD2SIQ(mx, r) } +func VPUNPCKLBW(ops ...operand.Op) { ctx.VPUNPCKLBW(ops...) } -// VCVTSD2SS: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value. +// VPUNPCKLBW_Z: Unpack and Interleave Low-Order Bytes into Words (Zeroing Masking). // // Forms: // -// VCVTSD2SS xmm xmm xmm -// VCVTSD2SS m64 xmm xmm -// Construct and append a VCVTSD2SS instruction to the active function. -func (c *Context) VCVTSD2SS(mx, x, x1 operand.Op) { - if inst, err := x86.VCVTSD2SS(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPUNPCKLBW.Z m128 xmm k xmm +// VPUNPCKLBW.Z m256 ymm k ymm +// VPUNPCKLBW.Z xmm xmm k xmm +// VPUNPCKLBW.Z ymm ymm k ymm +// VPUNPCKLBW.Z m512 zmm k zmm +// VPUNPCKLBW.Z zmm zmm k zmm +// Construct and append a VPUNPCKLBW.Z instruction to the active function. +func (c *Context) VPUNPCKLBW_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPUNPCKLBW_Z(mxyz, xyz, k, xyz1)) } -// VCVTSD2SS: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value. +// VPUNPCKLBW_Z: Unpack and Interleave Low-Order Bytes into Words (Zeroing Masking). // // Forms: // -// VCVTSD2SS xmm xmm xmm -// VCVTSD2SS m64 xmm xmm -// Construct and append a VCVTSD2SS instruction to the active function. +// VPUNPCKLBW.Z m128 xmm k xmm +// VPUNPCKLBW.Z m256 ymm k ymm +// VPUNPCKLBW.Z xmm xmm k xmm +// VPUNPCKLBW.Z ymm ymm k ymm +// VPUNPCKLBW.Z m512 zmm k zmm +// VPUNPCKLBW.Z zmm zmm k zmm +// Construct and append a VPUNPCKLBW.Z instruction to the active function. // Operates on the global context. -func VCVTSD2SS(mx, x, x1 operand.Op) { ctx.VCVTSD2SS(mx, x, x1) } +func VPUNPCKLBW_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPUNPCKLBW_Z(mxyz, xyz, k, xyz1) } -// VCVTSI2SDL: Convert Dword Integer to Scalar Double-Precision FP Value. +// VPUNPCKLDQ: Unpack and Interleave Low-Order Doublewords into Quadwords. // // Forms: // -// VCVTSI2SDL r32 xmm xmm -// VCVTSI2SDL m32 xmm xmm -// Construct and append a VCVTSI2SDL instruction to the active function. -func (c *Context) VCVTSI2SDL(mr, x, x1 operand.Op) { - if inst, err := x86.VCVTSI2SDL(mr, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPUNPCKLDQ m256 ymm ymm +// VPUNPCKLDQ ymm ymm ymm +// VPUNPCKLDQ m128 xmm xmm +// VPUNPCKLDQ xmm xmm xmm +// VPUNPCKLDQ m128 xmm k xmm +// VPUNPCKLDQ m256 ymm k ymm +// VPUNPCKLDQ xmm xmm k xmm +// VPUNPCKLDQ ymm ymm k ymm +// VPUNPCKLDQ m512 zmm k zmm +// VPUNPCKLDQ m512 zmm zmm +// VPUNPCKLDQ zmm zmm k zmm +// VPUNPCKLDQ zmm zmm zmm +// Construct and append a VPUNPCKLDQ instruction to the active function. +func (c *Context) VPUNPCKLDQ(ops ...operand.Op) { + c.addinstruction(x86.VPUNPCKLDQ(ops...)) } -// VCVTSI2SDL: Convert Dword Integer to Scalar Double-Precision FP Value. +// VPUNPCKLDQ: Unpack and Interleave Low-Order Doublewords into Quadwords. // // Forms: // -// VCVTSI2SDL r32 xmm xmm -// VCVTSI2SDL m32 xmm xmm -// Construct and append a VCVTSI2SDL instruction to the active function. +// VPUNPCKLDQ m256 ymm ymm +// VPUNPCKLDQ ymm ymm ymm +// VPUNPCKLDQ m128 xmm xmm +// VPUNPCKLDQ xmm xmm xmm +// VPUNPCKLDQ m128 xmm k xmm +// VPUNPCKLDQ m256 ymm k ymm +// VPUNPCKLDQ xmm xmm k xmm +// VPUNPCKLDQ ymm ymm k ymm +// VPUNPCKLDQ m512 zmm k zmm +// VPUNPCKLDQ m512 zmm zmm +// VPUNPCKLDQ zmm zmm k zmm +// VPUNPCKLDQ zmm zmm zmm +// Construct and append a VPUNPCKLDQ instruction to the active function. // Operates on the global context. -func VCVTSI2SDL(mr, x, x1 operand.Op) { ctx.VCVTSI2SDL(mr, x, x1) } +func VPUNPCKLDQ(ops ...operand.Op) { ctx.VPUNPCKLDQ(ops...) } -// VCVTSI2SDQ: Convert Dword Integer to Scalar Double-Precision FP Value. +// VPUNPCKLDQ_BCST: Unpack and Interleave Low-Order Doublewords into Quadwords (Broadcast). // // Forms: // -// VCVTSI2SDQ r64 xmm xmm -// VCVTSI2SDQ m64 xmm xmm -// Construct and append a VCVTSI2SDQ instruction to the active function. -func (c *Context) VCVTSI2SDQ(mr, x, x1 operand.Op) { - if inst, err := x86.VCVTSI2SDQ(mr, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPUNPCKLDQ.BCST m32 xmm k xmm +// VPUNPCKLDQ.BCST m32 xmm xmm +// VPUNPCKLDQ.BCST m32 ymm k ymm +// VPUNPCKLDQ.BCST m32 ymm ymm +// VPUNPCKLDQ.BCST m32 zmm k zmm +// VPUNPCKLDQ.BCST m32 zmm zmm +// Construct and append a VPUNPCKLDQ.BCST instruction to the active function. +func (c *Context) VPUNPCKLDQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPUNPCKLDQ_BCST(ops...)) } -// VCVTSI2SDQ: Convert Dword Integer to Scalar Double-Precision FP Value. +// VPUNPCKLDQ_BCST: Unpack and Interleave Low-Order Doublewords into Quadwords (Broadcast). // // Forms: // -// VCVTSI2SDQ r64 xmm xmm -// VCVTSI2SDQ m64 xmm xmm -// Construct and append a VCVTSI2SDQ instruction to the active function. +// VPUNPCKLDQ.BCST m32 xmm k xmm +// VPUNPCKLDQ.BCST m32 xmm xmm +// VPUNPCKLDQ.BCST m32 ymm k ymm +// VPUNPCKLDQ.BCST m32 ymm ymm +// VPUNPCKLDQ.BCST m32 zmm k zmm +// VPUNPCKLDQ.BCST m32 zmm zmm +// Construct and append a VPUNPCKLDQ.BCST instruction to the active function. // Operates on the global context. -func VCVTSI2SDQ(mr, x, x1 operand.Op) { ctx.VCVTSI2SDQ(mr, x, x1) } +func VPUNPCKLDQ_BCST(ops ...operand.Op) { ctx.VPUNPCKLDQ_BCST(ops...) } -// VCVTSI2SSL: Convert Dword Integer to Scalar Single-Precision FP Value. +// VPUNPCKLDQ_BCST_Z: Unpack and Interleave Low-Order Doublewords into Quadwords (Broadcast, Zeroing Masking). // // Forms: // -// VCVTSI2SSL r32 xmm xmm -// VCVTSI2SSL m32 xmm xmm -// Construct and append a VCVTSI2SSL instruction to the active function. -func (c *Context) VCVTSI2SSL(mr, x, x1 operand.Op) { - if inst, err := x86.VCVTSI2SSL(mr, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPUNPCKLDQ.BCST.Z m32 xmm k xmm +// VPUNPCKLDQ.BCST.Z m32 ymm k ymm +// VPUNPCKLDQ.BCST.Z m32 zmm k zmm +// Construct and append a VPUNPCKLDQ.BCST.Z instruction to the active function. +func (c *Context) VPUNPCKLDQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPUNPCKLDQ_BCST_Z(m, xyz, k, xyz1)) } -// VCVTSI2SSL: Convert Dword Integer to Scalar Single-Precision FP Value. +// VPUNPCKLDQ_BCST_Z: Unpack and Interleave Low-Order Doublewords into Quadwords (Broadcast, Zeroing Masking). // // Forms: // -// VCVTSI2SSL r32 xmm xmm -// VCVTSI2SSL m32 xmm xmm -// Construct and append a VCVTSI2SSL instruction to the active function. +// VPUNPCKLDQ.BCST.Z m32 xmm k xmm +// VPUNPCKLDQ.BCST.Z m32 ymm k ymm +// VPUNPCKLDQ.BCST.Z m32 zmm k zmm +// Construct and append a VPUNPCKLDQ.BCST.Z instruction to the active function. // Operates on the global context. -func VCVTSI2SSL(mr, x, x1 operand.Op) { ctx.VCVTSI2SSL(mr, x, x1) } +func VPUNPCKLDQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPUNPCKLDQ_BCST_Z(m, xyz, k, xyz1) } -// VCVTSI2SSQ: Convert Dword Integer to Scalar Single-Precision FP Value. +// VPUNPCKLDQ_Z: Unpack and Interleave Low-Order Doublewords into Quadwords (Zeroing Masking). // // Forms: // -// VCVTSI2SSQ r64 xmm xmm -// VCVTSI2SSQ m64 xmm xmm -// Construct and append a VCVTSI2SSQ instruction to the active function. -func (c *Context) VCVTSI2SSQ(mr, x, x1 operand.Op) { - if inst, err := x86.VCVTSI2SSQ(mr, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPUNPCKLDQ.Z m128 xmm k xmm +// VPUNPCKLDQ.Z m256 ymm k ymm +// VPUNPCKLDQ.Z xmm xmm k xmm +// VPUNPCKLDQ.Z ymm ymm k ymm +// VPUNPCKLDQ.Z m512 zmm k zmm +// VPUNPCKLDQ.Z zmm zmm k zmm +// Construct and append a VPUNPCKLDQ.Z instruction to the active function. +func (c *Context) VPUNPCKLDQ_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPUNPCKLDQ_Z(mxyz, xyz, k, xyz1)) } -// VCVTSI2SSQ: Convert Dword Integer to Scalar Single-Precision FP Value. +// VPUNPCKLDQ_Z: Unpack and Interleave Low-Order Doublewords into Quadwords (Zeroing Masking). // // Forms: // -// VCVTSI2SSQ r64 xmm xmm -// VCVTSI2SSQ m64 xmm xmm -// Construct and append a VCVTSI2SSQ instruction to the active function. +// VPUNPCKLDQ.Z m128 xmm k xmm +// VPUNPCKLDQ.Z m256 ymm k ymm +// VPUNPCKLDQ.Z xmm xmm k xmm +// VPUNPCKLDQ.Z ymm ymm k ymm +// VPUNPCKLDQ.Z m512 zmm k zmm +// VPUNPCKLDQ.Z zmm zmm k zmm +// Construct and append a VPUNPCKLDQ.Z instruction to the active function. // Operates on the global context. -func VCVTSI2SSQ(mr, x, x1 operand.Op) { ctx.VCVTSI2SSQ(mr, x, x1) } +func VPUNPCKLDQ_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPUNPCKLDQ_Z(mxyz, xyz, k, xyz1) } -// VCVTSS2SD: Convert Scalar Single-Precision FP Value to Scalar Double-Precision FP Value. +// VPUNPCKLQDQ: Unpack and Interleave Low-Order Quadwords into Double Quadwords. // // Forms: // -// VCVTSS2SD xmm xmm xmm -// VCVTSS2SD m32 xmm xmm -// Construct and append a VCVTSS2SD instruction to the active function. -func (c *Context) VCVTSS2SD(mx, x, x1 operand.Op) { - if inst, err := x86.VCVTSS2SD(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPUNPCKLQDQ m256 ymm ymm +// VPUNPCKLQDQ ymm ymm ymm +// VPUNPCKLQDQ m128 xmm xmm +// VPUNPCKLQDQ xmm xmm xmm +// VPUNPCKLQDQ m128 xmm k xmm +// VPUNPCKLQDQ m256 ymm k ymm +// VPUNPCKLQDQ xmm xmm k xmm +// VPUNPCKLQDQ ymm ymm k ymm +// VPUNPCKLQDQ m512 zmm k zmm +// VPUNPCKLQDQ m512 zmm zmm +// VPUNPCKLQDQ zmm zmm k zmm +// VPUNPCKLQDQ zmm zmm zmm +// Construct and append a VPUNPCKLQDQ instruction to the active function. +func (c *Context) VPUNPCKLQDQ(ops ...operand.Op) { + c.addinstruction(x86.VPUNPCKLQDQ(ops...)) } -// VCVTSS2SD: Convert Scalar Single-Precision FP Value to Scalar Double-Precision FP Value. +// VPUNPCKLQDQ: Unpack and Interleave Low-Order Quadwords into Double Quadwords. // // Forms: // -// VCVTSS2SD xmm xmm xmm -// VCVTSS2SD m32 xmm xmm -// Construct and append a VCVTSS2SD instruction to the active function. +// VPUNPCKLQDQ m256 ymm ymm +// VPUNPCKLQDQ ymm ymm ymm +// VPUNPCKLQDQ m128 xmm xmm +// VPUNPCKLQDQ xmm xmm xmm +// VPUNPCKLQDQ m128 xmm k xmm +// VPUNPCKLQDQ m256 ymm k ymm +// VPUNPCKLQDQ xmm xmm k xmm +// VPUNPCKLQDQ ymm ymm k ymm +// VPUNPCKLQDQ m512 zmm k zmm +// VPUNPCKLQDQ m512 zmm zmm +// VPUNPCKLQDQ zmm zmm k zmm +// VPUNPCKLQDQ zmm zmm zmm +// Construct and append a VPUNPCKLQDQ instruction to the active function. // Operates on the global context. -func VCVTSS2SD(mx, x, x1 operand.Op) { ctx.VCVTSS2SD(mx, x, x1) } +func VPUNPCKLQDQ(ops ...operand.Op) { ctx.VPUNPCKLQDQ(ops...) } -// VCVTSS2SI: Convert Scalar Single-Precision FP Value to Dword Integer. +// VPUNPCKLQDQ_BCST: Unpack and Interleave Low-Order Quadwords into Double Quadwords (Broadcast). // // Forms: // -// VCVTSS2SI xmm r32 -// VCVTSS2SI m32 r32 -// Construct and append a VCVTSS2SI instruction to the active function. -func (c *Context) VCVTSS2SI(mx, r operand.Op) { - if inst, err := x86.VCVTSS2SI(mx, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPUNPCKLQDQ.BCST m64 xmm k xmm +// VPUNPCKLQDQ.BCST m64 xmm xmm +// VPUNPCKLQDQ.BCST m64 ymm k ymm +// VPUNPCKLQDQ.BCST m64 ymm ymm +// VPUNPCKLQDQ.BCST m64 zmm k zmm +// VPUNPCKLQDQ.BCST m64 zmm zmm +// Construct and append a VPUNPCKLQDQ.BCST instruction to the active function. +func (c *Context) VPUNPCKLQDQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPUNPCKLQDQ_BCST(ops...)) } -// VCVTSS2SI: Convert Scalar Single-Precision FP Value to Dword Integer. +// VPUNPCKLQDQ_BCST: Unpack and Interleave Low-Order Quadwords into Double Quadwords (Broadcast). // // Forms: // -// VCVTSS2SI xmm r32 -// VCVTSS2SI m32 r32 -// Construct and append a VCVTSS2SI instruction to the active function. +// VPUNPCKLQDQ.BCST m64 xmm k xmm +// VPUNPCKLQDQ.BCST m64 xmm xmm +// VPUNPCKLQDQ.BCST m64 ymm k ymm +// VPUNPCKLQDQ.BCST m64 ymm ymm +// VPUNPCKLQDQ.BCST m64 zmm k zmm +// VPUNPCKLQDQ.BCST m64 zmm zmm +// Construct and append a VPUNPCKLQDQ.BCST instruction to the active function. // Operates on the global context. -func VCVTSS2SI(mx, r operand.Op) { ctx.VCVTSS2SI(mx, r) } +func VPUNPCKLQDQ_BCST(ops ...operand.Op) { ctx.VPUNPCKLQDQ_BCST(ops...) } -// VCVTSS2SIQ: Convert Scalar Single-Precision FP Value to Dword Integer. +// VPUNPCKLQDQ_BCST_Z: Unpack and Interleave Low-Order Quadwords into Double Quadwords (Broadcast, Zeroing Masking). // // Forms: // -// VCVTSS2SIQ xmm r64 -// VCVTSS2SIQ m32 r64 -// Construct and append a VCVTSS2SIQ instruction to the active function. -func (c *Context) VCVTSS2SIQ(mx, r operand.Op) { - if inst, err := x86.VCVTSS2SIQ(mx, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPUNPCKLQDQ.BCST.Z m64 xmm k xmm +// VPUNPCKLQDQ.BCST.Z m64 ymm k ymm +// VPUNPCKLQDQ.BCST.Z m64 zmm k zmm +// Construct and append a VPUNPCKLQDQ.BCST.Z instruction to the active function. +func (c *Context) VPUNPCKLQDQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPUNPCKLQDQ_BCST_Z(m, xyz, k, xyz1)) } -// VCVTSS2SIQ: Convert Scalar Single-Precision FP Value to Dword Integer. +// VPUNPCKLQDQ_BCST_Z: Unpack and Interleave Low-Order Quadwords into Double Quadwords (Broadcast, Zeroing Masking). // // Forms: // -// VCVTSS2SIQ xmm r64 -// VCVTSS2SIQ m32 r64 -// Construct and append a VCVTSS2SIQ instruction to the active function. +// VPUNPCKLQDQ.BCST.Z m64 xmm k xmm +// VPUNPCKLQDQ.BCST.Z m64 ymm k ymm +// VPUNPCKLQDQ.BCST.Z m64 zmm k zmm +// Construct and append a VPUNPCKLQDQ.BCST.Z instruction to the active function. // Operates on the global context. -func VCVTSS2SIQ(mx, r operand.Op) { ctx.VCVTSS2SIQ(mx, r) } +func VPUNPCKLQDQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPUNPCKLQDQ_BCST_Z(m, xyz, k, xyz1) } -// VCVTTPD2DQX: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers. +// VPUNPCKLQDQ_Z: Unpack and Interleave Low-Order Quadwords into Double Quadwords (Zeroing Masking). // // Forms: // -// VCVTTPD2DQX xmm xmm -// VCVTTPD2DQX m128 xmm -// Construct and append a VCVTTPD2DQX instruction to the active function. -func (c *Context) VCVTTPD2DQX(mx, x operand.Op) { - if inst, err := x86.VCVTTPD2DQX(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPUNPCKLQDQ.Z m128 xmm k xmm +// VPUNPCKLQDQ.Z m256 ymm k ymm +// VPUNPCKLQDQ.Z xmm xmm k xmm +// VPUNPCKLQDQ.Z ymm ymm k ymm +// VPUNPCKLQDQ.Z m512 zmm k zmm +// VPUNPCKLQDQ.Z zmm zmm k zmm +// Construct and append a VPUNPCKLQDQ.Z instruction to the active function. +func (c *Context) VPUNPCKLQDQ_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPUNPCKLQDQ_Z(mxyz, xyz, k, xyz1)) } -// VCVTTPD2DQX: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers. +// VPUNPCKLQDQ_Z: Unpack and Interleave Low-Order Quadwords into Double Quadwords (Zeroing Masking). // // Forms: // -// VCVTTPD2DQX xmm xmm -// VCVTTPD2DQX m128 xmm -// Construct and append a VCVTTPD2DQX instruction to the active function. +// VPUNPCKLQDQ.Z m128 xmm k xmm +// VPUNPCKLQDQ.Z m256 ymm k ymm +// VPUNPCKLQDQ.Z xmm xmm k xmm +// VPUNPCKLQDQ.Z ymm ymm k ymm +// VPUNPCKLQDQ.Z m512 zmm k zmm +// VPUNPCKLQDQ.Z zmm zmm k zmm +// Construct and append a VPUNPCKLQDQ.Z instruction to the active function. // Operates on the global context. -func VCVTTPD2DQX(mx, x operand.Op) { ctx.VCVTTPD2DQX(mx, x) } +func VPUNPCKLQDQ_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPUNPCKLQDQ_Z(mxyz, xyz, k, xyz1) } -// VCVTTPD2DQY: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers. +// VPUNPCKLWD: Unpack and Interleave Low-Order Words into Doublewords. // // Forms: // -// VCVTTPD2DQY ymm xmm -// VCVTTPD2DQY m256 xmm -// Construct and append a VCVTTPD2DQY instruction to the active function. -func (c *Context) VCVTTPD2DQY(my, x operand.Op) { - if inst, err := x86.VCVTTPD2DQY(my, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPUNPCKLWD m256 ymm ymm +// VPUNPCKLWD ymm ymm ymm +// VPUNPCKLWD m128 xmm xmm +// VPUNPCKLWD xmm xmm xmm +// VPUNPCKLWD m128 xmm k xmm +// VPUNPCKLWD m256 ymm k ymm +// VPUNPCKLWD xmm xmm k xmm +// VPUNPCKLWD ymm ymm k ymm +// VPUNPCKLWD m512 zmm k zmm +// VPUNPCKLWD m512 zmm zmm +// VPUNPCKLWD zmm zmm k zmm +// VPUNPCKLWD zmm zmm zmm +// Construct and append a VPUNPCKLWD instruction to the active function. +func (c *Context) VPUNPCKLWD(ops ...operand.Op) { + c.addinstruction(x86.VPUNPCKLWD(ops...)) } -// VCVTTPD2DQY: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers. +// VPUNPCKLWD: Unpack and Interleave Low-Order Words into Doublewords. // // Forms: // -// VCVTTPD2DQY ymm xmm -// VCVTTPD2DQY m256 xmm -// Construct and append a VCVTTPD2DQY instruction to the active function. +// VPUNPCKLWD m256 ymm ymm +// VPUNPCKLWD ymm ymm ymm +// VPUNPCKLWD m128 xmm xmm +// VPUNPCKLWD xmm xmm xmm +// VPUNPCKLWD m128 xmm k xmm +// VPUNPCKLWD m256 ymm k ymm +// VPUNPCKLWD xmm xmm k xmm +// VPUNPCKLWD ymm ymm k ymm +// VPUNPCKLWD m512 zmm k zmm +// VPUNPCKLWD m512 zmm zmm +// VPUNPCKLWD zmm zmm k zmm +// VPUNPCKLWD zmm zmm zmm +// Construct and append a VPUNPCKLWD instruction to the active function. // Operates on the global context. -func VCVTTPD2DQY(my, x operand.Op) { ctx.VCVTTPD2DQY(my, x) } +func VPUNPCKLWD(ops ...operand.Op) { ctx.VPUNPCKLWD(ops...) } -// VCVTTPS2DQ: Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers. +// VPUNPCKLWD_Z: Unpack and Interleave Low-Order Words into Doublewords (Zeroing Masking). // // Forms: // -// VCVTTPS2DQ xmm xmm -// VCVTTPS2DQ m128 xmm -// VCVTTPS2DQ ymm ymm -// VCVTTPS2DQ m256 ymm -// Construct and append a VCVTTPS2DQ instruction to the active function. -func (c *Context) VCVTTPS2DQ(mxy, xy operand.Op) { - if inst, err := x86.VCVTTPS2DQ(mxy, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPUNPCKLWD.Z m128 xmm k xmm +// VPUNPCKLWD.Z m256 ymm k ymm +// VPUNPCKLWD.Z xmm xmm k xmm +// VPUNPCKLWD.Z ymm ymm k ymm +// VPUNPCKLWD.Z m512 zmm k zmm +// VPUNPCKLWD.Z zmm zmm k zmm +// Construct and append a VPUNPCKLWD.Z instruction to the active function. +func (c *Context) VPUNPCKLWD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPUNPCKLWD_Z(mxyz, xyz, k, xyz1)) } -// VCVTTPS2DQ: Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers. +// VPUNPCKLWD_Z: Unpack and Interleave Low-Order Words into Doublewords (Zeroing Masking). // // Forms: // -// VCVTTPS2DQ xmm xmm -// VCVTTPS2DQ m128 xmm -// VCVTTPS2DQ ymm ymm -// VCVTTPS2DQ m256 ymm -// Construct and append a VCVTTPS2DQ instruction to the active function. +// VPUNPCKLWD.Z m128 xmm k xmm +// VPUNPCKLWD.Z m256 ymm k ymm +// VPUNPCKLWD.Z xmm xmm k xmm +// VPUNPCKLWD.Z ymm ymm k ymm +// VPUNPCKLWD.Z m512 zmm k zmm +// VPUNPCKLWD.Z zmm zmm k zmm +// Construct and append a VPUNPCKLWD.Z instruction to the active function. // Operates on the global context. -func VCVTTPS2DQ(mxy, xy operand.Op) { ctx.VCVTTPS2DQ(mxy, xy) } +func VPUNPCKLWD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPUNPCKLWD_Z(mxyz, xyz, k, xyz1) } -// VCVTTSD2SI: Convert with Truncation Scalar Double-Precision FP Value to Signed Integer. +// VPXOR: Packed Bitwise Logical Exclusive OR. // // Forms: // -// VCVTTSD2SI xmm r32 -// VCVTTSD2SI m64 r32 -// Construct and append a VCVTTSD2SI instruction to the active function. -func (c *Context) VCVTTSD2SI(mx, r operand.Op) { - if inst, err := x86.VCVTTSD2SI(mx, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPXOR m256 ymm ymm +// VPXOR ymm ymm ymm +// VPXOR m128 xmm xmm +// VPXOR xmm xmm xmm +// Construct and append a VPXOR instruction to the active function. +func (c *Context) VPXOR(mxy, xy, xy1 operand.Op) { + c.addinstruction(x86.VPXOR(mxy, xy, xy1)) } -// VCVTTSD2SI: Convert with Truncation Scalar Double-Precision FP Value to Signed Integer. +// VPXOR: Packed Bitwise Logical Exclusive OR. // // Forms: // -// VCVTTSD2SI xmm r32 -// VCVTTSD2SI m64 r32 -// Construct and append a VCVTTSD2SI instruction to the active function. +// VPXOR m256 ymm ymm +// VPXOR ymm ymm ymm +// VPXOR m128 xmm xmm +// VPXOR xmm xmm xmm +// Construct and append a VPXOR instruction to the active function. // Operates on the global context. -func VCVTTSD2SI(mx, r operand.Op) { ctx.VCVTTSD2SI(mx, r) } +func VPXOR(mxy, xy, xy1 operand.Op) { ctx.VPXOR(mxy, xy, xy1) } -// VCVTTSD2SIQ: Convert with Truncation Scalar Double-Precision FP Value to Signed Integer. +// VPXORD: Bitwise Logical Exclusive OR of Packed Doubleword Integers. // // Forms: // -// VCVTTSD2SIQ xmm r64 -// VCVTTSD2SIQ m64 r64 -// Construct and append a VCVTTSD2SIQ instruction to the active function. -func (c *Context) VCVTTSD2SIQ(mx, r operand.Op) { - if inst, err := x86.VCVTTSD2SIQ(mx, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPXORD m128 xmm k xmm +// VPXORD m128 xmm xmm +// VPXORD m256 ymm k ymm +// VPXORD m256 ymm ymm +// VPXORD xmm xmm k xmm +// VPXORD xmm xmm xmm +// VPXORD ymm ymm k ymm +// VPXORD ymm ymm ymm +// VPXORD m512 zmm k zmm +// VPXORD m512 zmm zmm +// VPXORD zmm zmm k zmm +// VPXORD zmm zmm zmm +// Construct and append a VPXORD instruction to the active function. +func (c *Context) VPXORD(ops ...operand.Op) { + c.addinstruction(x86.VPXORD(ops...)) } -// VCVTTSD2SIQ: Convert with Truncation Scalar Double-Precision FP Value to Signed Integer. +// VPXORD: Bitwise Logical Exclusive OR of Packed Doubleword Integers. // // Forms: // -// VCVTTSD2SIQ xmm r64 -// VCVTTSD2SIQ m64 r64 -// Construct and append a VCVTTSD2SIQ instruction to the active function. +// VPXORD m128 xmm k xmm +// VPXORD m128 xmm xmm +// VPXORD m256 ymm k ymm +// VPXORD m256 ymm ymm +// VPXORD xmm xmm k xmm +// VPXORD xmm xmm xmm +// VPXORD ymm ymm k ymm +// VPXORD ymm ymm ymm +// VPXORD m512 zmm k zmm +// VPXORD m512 zmm zmm +// VPXORD zmm zmm k zmm +// VPXORD zmm zmm zmm +// Construct and append a VPXORD instruction to the active function. // Operates on the global context. -func VCVTTSD2SIQ(mx, r operand.Op) { ctx.VCVTTSD2SIQ(mx, r) } +func VPXORD(ops ...operand.Op) { ctx.VPXORD(ops...) } -// VCVTTSS2SI: Convert with Truncation Scalar Single-Precision FP Value to Dword Integer. +// VPXORD_BCST: Bitwise Logical Exclusive OR of Packed Doubleword Integers (Broadcast). // // Forms: // -// VCVTTSS2SI xmm r32 -// VCVTTSS2SI m32 r32 -// Construct and append a VCVTTSS2SI instruction to the active function. -func (c *Context) VCVTTSS2SI(mx, r operand.Op) { - if inst, err := x86.VCVTTSS2SI(mx, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPXORD.BCST m32 xmm k xmm +// VPXORD.BCST m32 xmm xmm +// VPXORD.BCST m32 ymm k ymm +// VPXORD.BCST m32 ymm ymm +// VPXORD.BCST m32 zmm k zmm +// VPXORD.BCST m32 zmm zmm +// Construct and append a VPXORD.BCST instruction to the active function. +func (c *Context) VPXORD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPXORD_BCST(ops...)) } -// VCVTTSS2SI: Convert with Truncation Scalar Single-Precision FP Value to Dword Integer. +// VPXORD_BCST: Bitwise Logical Exclusive OR of Packed Doubleword Integers (Broadcast). // // Forms: // -// VCVTTSS2SI xmm r32 -// VCVTTSS2SI m32 r32 -// Construct and append a VCVTTSS2SI instruction to the active function. +// VPXORD.BCST m32 xmm k xmm +// VPXORD.BCST m32 xmm xmm +// VPXORD.BCST m32 ymm k ymm +// VPXORD.BCST m32 ymm ymm +// VPXORD.BCST m32 zmm k zmm +// VPXORD.BCST m32 zmm zmm +// Construct and append a VPXORD.BCST instruction to the active function. // Operates on the global context. -func VCVTTSS2SI(mx, r operand.Op) { ctx.VCVTTSS2SI(mx, r) } +func VPXORD_BCST(ops ...operand.Op) { ctx.VPXORD_BCST(ops...) } -// VCVTTSS2SIQ: Convert with Truncation Scalar Single-Precision FP Value to Dword Integer. +// VPXORD_BCST_Z: Bitwise Logical Exclusive OR of Packed Doubleword Integers (Broadcast, Zeroing Masking). // // Forms: // -// VCVTTSS2SIQ xmm r64 -// VCVTTSS2SIQ m32 r64 -// Construct and append a VCVTTSS2SIQ instruction to the active function. -func (c *Context) VCVTTSS2SIQ(mx, r operand.Op) { - if inst, err := x86.VCVTTSS2SIQ(mx, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPXORD.BCST.Z m32 xmm k xmm +// VPXORD.BCST.Z m32 ymm k ymm +// VPXORD.BCST.Z m32 zmm k zmm +// Construct and append a VPXORD.BCST.Z instruction to the active function. +func (c *Context) VPXORD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPXORD_BCST_Z(m, xyz, k, xyz1)) } -// VCVTTSS2SIQ: Convert with Truncation Scalar Single-Precision FP Value to Dword Integer. +// VPXORD_BCST_Z: Bitwise Logical Exclusive OR of Packed Doubleword Integers (Broadcast, Zeroing Masking). // // Forms: // -// VCVTTSS2SIQ xmm r64 -// VCVTTSS2SIQ m32 r64 -// Construct and append a VCVTTSS2SIQ instruction to the active function. +// VPXORD.BCST.Z m32 xmm k xmm +// VPXORD.BCST.Z m32 ymm k ymm +// VPXORD.BCST.Z m32 zmm k zmm +// Construct and append a VPXORD.BCST.Z instruction to the active function. // Operates on the global context. -func VCVTTSS2SIQ(mx, r operand.Op) { ctx.VCVTTSS2SIQ(mx, r) } +func VPXORD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPXORD_BCST_Z(m, xyz, k, xyz1) } -// VDIVPD: Divide Packed Double-Precision Floating-Point Values. +// VPXORD_Z: Bitwise Logical Exclusive OR of Packed Doubleword Integers (Zeroing Masking). // // Forms: // -// VDIVPD xmm xmm xmm -// VDIVPD m128 xmm xmm -// VDIVPD ymm ymm ymm -// VDIVPD m256 ymm ymm -// Construct and append a VDIVPD instruction to the active function. -func (c *Context) VDIVPD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VDIVPD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPXORD.Z m128 xmm k xmm +// VPXORD.Z m256 ymm k ymm +// VPXORD.Z xmm xmm k xmm +// VPXORD.Z ymm ymm k ymm +// VPXORD.Z m512 zmm k zmm +// VPXORD.Z zmm zmm k zmm +// Construct and append a VPXORD.Z instruction to the active function. +func (c *Context) VPXORD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPXORD_Z(mxyz, xyz, k, xyz1)) } -// VDIVPD: Divide Packed Double-Precision Floating-Point Values. +// VPXORD_Z: Bitwise Logical Exclusive OR of Packed Doubleword Integers (Zeroing Masking). // // Forms: // -// VDIVPD xmm xmm xmm -// VDIVPD m128 xmm xmm -// VDIVPD ymm ymm ymm -// VDIVPD m256 ymm ymm -// Construct and append a VDIVPD instruction to the active function. +// VPXORD.Z m128 xmm k xmm +// VPXORD.Z m256 ymm k ymm +// VPXORD.Z xmm xmm k xmm +// VPXORD.Z ymm ymm k ymm +// VPXORD.Z m512 zmm k zmm +// VPXORD.Z zmm zmm k zmm +// Construct and append a VPXORD.Z instruction to the active function. // Operates on the global context. -func VDIVPD(mxy, xy, xy1 operand.Op) { ctx.VDIVPD(mxy, xy, xy1) } +func VPXORD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPXORD_Z(mxyz, xyz, k, xyz1) } -// VDIVPS: Divide Packed Single-Precision Floating-Point Values. +// VPXORQ: Bitwise Logical Exclusive OR of Packed Quadword Integers. // // Forms: // -// VDIVPS xmm xmm xmm -// VDIVPS m128 xmm xmm -// VDIVPS ymm ymm ymm -// VDIVPS m256 ymm ymm -// Construct and append a VDIVPS instruction to the active function. -func (c *Context) VDIVPS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VDIVPS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPXORQ m128 xmm k xmm +// VPXORQ m128 xmm xmm +// VPXORQ m256 ymm k ymm +// VPXORQ m256 ymm ymm +// VPXORQ xmm xmm k xmm +// VPXORQ xmm xmm xmm +// VPXORQ ymm ymm k ymm +// VPXORQ ymm ymm ymm +// VPXORQ m512 zmm k zmm +// VPXORQ m512 zmm zmm +// VPXORQ zmm zmm k zmm +// VPXORQ zmm zmm zmm +// Construct and append a VPXORQ instruction to the active function. +func (c *Context) VPXORQ(ops ...operand.Op) { + c.addinstruction(x86.VPXORQ(ops...)) } -// VDIVPS: Divide Packed Single-Precision Floating-Point Values. +// VPXORQ: Bitwise Logical Exclusive OR of Packed Quadword Integers. // // Forms: // -// VDIVPS xmm xmm xmm -// VDIVPS m128 xmm xmm -// VDIVPS ymm ymm ymm -// VDIVPS m256 ymm ymm -// Construct and append a VDIVPS instruction to the active function. +// VPXORQ m128 xmm k xmm +// VPXORQ m128 xmm xmm +// VPXORQ m256 ymm k ymm +// VPXORQ m256 ymm ymm +// VPXORQ xmm xmm k xmm +// VPXORQ xmm xmm xmm +// VPXORQ ymm ymm k ymm +// VPXORQ ymm ymm ymm +// VPXORQ m512 zmm k zmm +// VPXORQ m512 zmm zmm +// VPXORQ zmm zmm k zmm +// VPXORQ zmm zmm zmm +// Construct and append a VPXORQ instruction to the active function. // Operates on the global context. -func VDIVPS(mxy, xy, xy1 operand.Op) { ctx.VDIVPS(mxy, xy, xy1) } +func VPXORQ(ops ...operand.Op) { ctx.VPXORQ(ops...) } -// VDIVSD: Divide Scalar Double-Precision Floating-Point Values. +// VPXORQ_BCST: Bitwise Logical Exclusive OR of Packed Quadword Integers (Broadcast). // // Forms: // -// VDIVSD xmm xmm xmm -// VDIVSD m64 xmm xmm -// Construct and append a VDIVSD instruction to the active function. -func (c *Context) VDIVSD(mx, x, x1 operand.Op) { - if inst, err := x86.VDIVSD(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPXORQ.BCST m64 xmm k xmm +// VPXORQ.BCST m64 xmm xmm +// VPXORQ.BCST m64 ymm k ymm +// VPXORQ.BCST m64 ymm ymm +// VPXORQ.BCST m64 zmm k zmm +// VPXORQ.BCST m64 zmm zmm +// Construct and append a VPXORQ.BCST instruction to the active function. +func (c *Context) VPXORQ_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPXORQ_BCST(ops...)) } -// VDIVSD: Divide Scalar Double-Precision Floating-Point Values. +// VPXORQ_BCST: Bitwise Logical Exclusive OR of Packed Quadword Integers (Broadcast). // // Forms: // -// VDIVSD xmm xmm xmm -// VDIVSD m64 xmm xmm -// Construct and append a VDIVSD instruction to the active function. +// VPXORQ.BCST m64 xmm k xmm +// VPXORQ.BCST m64 xmm xmm +// VPXORQ.BCST m64 ymm k ymm +// VPXORQ.BCST m64 ymm ymm +// VPXORQ.BCST m64 zmm k zmm +// VPXORQ.BCST m64 zmm zmm +// Construct and append a VPXORQ.BCST instruction to the active function. // Operates on the global context. -func VDIVSD(mx, x, x1 operand.Op) { ctx.VDIVSD(mx, x, x1) } +func VPXORQ_BCST(ops ...operand.Op) { ctx.VPXORQ_BCST(ops...) } -// VDIVSS: Divide Scalar Single-Precision Floating-Point Values. +// VPXORQ_BCST_Z: Bitwise Logical Exclusive OR of Packed Quadword Integers (Broadcast, Zeroing Masking). // // Forms: // -// VDIVSS xmm xmm xmm -// VDIVSS m32 xmm xmm -// Construct and append a VDIVSS instruction to the active function. -func (c *Context) VDIVSS(mx, x, x1 operand.Op) { - if inst, err := x86.VDIVSS(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPXORQ.BCST.Z m64 xmm k xmm +// VPXORQ.BCST.Z m64 ymm k ymm +// VPXORQ.BCST.Z m64 zmm k zmm +// Construct and append a VPXORQ.BCST.Z instruction to the active function. +func (c *Context) VPXORQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPXORQ_BCST_Z(m, xyz, k, xyz1)) } -// VDIVSS: Divide Scalar Single-Precision Floating-Point Values. +// VPXORQ_BCST_Z: Bitwise Logical Exclusive OR of Packed Quadword Integers (Broadcast, Zeroing Masking). // // Forms: // -// VDIVSS xmm xmm xmm -// VDIVSS m32 xmm xmm -// Construct and append a VDIVSS instruction to the active function. +// VPXORQ.BCST.Z m64 xmm k xmm +// VPXORQ.BCST.Z m64 ymm k ymm +// VPXORQ.BCST.Z m64 zmm k zmm +// Construct and append a VPXORQ.BCST.Z instruction to the active function. // Operates on the global context. -func VDIVSS(mx, x, x1 operand.Op) { ctx.VDIVSS(mx, x, x1) } +func VPXORQ_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPXORQ_BCST_Z(m, xyz, k, xyz1) } -// VDPPD: Dot Product of Packed Double Precision Floating-Point Values. +// VPXORQ_Z: Bitwise Logical Exclusive OR of Packed Quadword Integers (Zeroing Masking). // // Forms: // -// VDPPD imm8 xmm xmm xmm -// VDPPD imm8 m128 xmm xmm -// Construct and append a VDPPD instruction to the active function. -func (c *Context) VDPPD(i, mx, x, x1 operand.Op) { - if inst, err := x86.VDPPD(i, mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VPXORQ.Z m128 xmm k xmm +// VPXORQ.Z m256 ymm k ymm +// VPXORQ.Z xmm xmm k xmm +// VPXORQ.Z ymm ymm k ymm +// VPXORQ.Z m512 zmm k zmm +// VPXORQ.Z zmm zmm k zmm +// Construct and append a VPXORQ.Z instruction to the active function. +func (c *Context) VPXORQ_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPXORQ_Z(mxyz, xyz, k, xyz1)) } -// VDPPD: Dot Product of Packed Double Precision Floating-Point Values. +// VPXORQ_Z: Bitwise Logical Exclusive OR of Packed Quadword Integers (Zeroing Masking). // // Forms: // -// VDPPD imm8 xmm xmm xmm -// VDPPD imm8 m128 xmm xmm -// Construct and append a VDPPD instruction to the active function. +// VPXORQ.Z m128 xmm k xmm +// VPXORQ.Z m256 ymm k ymm +// VPXORQ.Z xmm xmm k xmm +// VPXORQ.Z ymm ymm k ymm +// VPXORQ.Z m512 zmm k zmm +// VPXORQ.Z zmm zmm k zmm +// Construct and append a VPXORQ.Z instruction to the active function. // Operates on the global context. -func VDPPD(i, mx, x, x1 operand.Op) { ctx.VDPPD(i, mx, x, x1) } +func VPXORQ_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPXORQ_Z(mxyz, xyz, k, xyz1) } -// VDPPS: Dot Product of Packed Single Precision Floating-Point Values. +// VRANGEPD: Range Restriction Calculation For Packed Pairs of Double-Precision Floating-Point Values. // // Forms: // -// VDPPS imm8 xmm xmm xmm -// VDPPS imm8 m128 xmm xmm -// VDPPS imm8 ymm ymm ymm -// VDPPS imm8 m256 ymm ymm -// Construct and append a VDPPS instruction to the active function. -func (c *Context) VDPPS(i, mxy, xy, xy1 operand.Op) { - if inst, err := x86.VDPPS(i, mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRANGEPD imm8 m128 xmm k xmm +// VRANGEPD imm8 m128 xmm xmm +// VRANGEPD imm8 m256 ymm k ymm +// VRANGEPD imm8 m256 ymm ymm +// VRANGEPD imm8 xmm xmm k xmm +// VRANGEPD imm8 xmm xmm xmm +// VRANGEPD imm8 ymm ymm k ymm +// VRANGEPD imm8 ymm ymm ymm +// VRANGEPD imm8 m512 zmm k zmm +// VRANGEPD imm8 m512 zmm zmm +// VRANGEPD imm8 zmm zmm k zmm +// VRANGEPD imm8 zmm zmm zmm +// Construct and append a VRANGEPD instruction to the active function. +func (c *Context) VRANGEPD(ops ...operand.Op) { + c.addinstruction(x86.VRANGEPD(ops...)) } -// VDPPS: Dot Product of Packed Single Precision Floating-Point Values. +// VRANGEPD: Range Restriction Calculation For Packed Pairs of Double-Precision Floating-Point Values. // // Forms: // -// VDPPS imm8 xmm xmm xmm -// VDPPS imm8 m128 xmm xmm -// VDPPS imm8 ymm ymm ymm -// VDPPS imm8 m256 ymm ymm -// Construct and append a VDPPS instruction to the active function. +// VRANGEPD imm8 m128 xmm k xmm +// VRANGEPD imm8 m128 xmm xmm +// VRANGEPD imm8 m256 ymm k ymm +// VRANGEPD imm8 m256 ymm ymm +// VRANGEPD imm8 xmm xmm k xmm +// VRANGEPD imm8 xmm xmm xmm +// VRANGEPD imm8 ymm ymm k ymm +// VRANGEPD imm8 ymm ymm ymm +// VRANGEPD imm8 m512 zmm k zmm +// VRANGEPD imm8 m512 zmm zmm +// VRANGEPD imm8 zmm zmm k zmm +// VRANGEPD imm8 zmm zmm zmm +// Construct and append a VRANGEPD instruction to the active function. // Operates on the global context. -func VDPPS(i, mxy, xy, xy1 operand.Op) { ctx.VDPPS(i, mxy, xy, xy1) } +func VRANGEPD(ops ...operand.Op) { ctx.VRANGEPD(ops...) } -// VEXTRACTF128: Extract Packed Floating-Point Values. +// VRANGEPD_BCST: Range Restriction Calculation For Packed Pairs of Double-Precision Floating-Point Values (Broadcast). // // Forms: // -// VEXTRACTF128 imm8 ymm xmm -// VEXTRACTF128 imm8 ymm m128 -// Construct and append a VEXTRACTF128 instruction to the active function. -func (c *Context) VEXTRACTF128(i, y, mx operand.Op) { - if inst, err := x86.VEXTRACTF128(i, y, mx); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRANGEPD.BCST imm8 m64 xmm k xmm +// VRANGEPD.BCST imm8 m64 xmm xmm +// VRANGEPD.BCST imm8 m64 ymm k ymm +// VRANGEPD.BCST imm8 m64 ymm ymm +// VRANGEPD.BCST imm8 m64 zmm k zmm +// VRANGEPD.BCST imm8 m64 zmm zmm +// Construct and append a VRANGEPD.BCST instruction to the active function. +func (c *Context) VRANGEPD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VRANGEPD_BCST(ops...)) } -// VEXTRACTF128: Extract Packed Floating-Point Values. +// VRANGEPD_BCST: Range Restriction Calculation For Packed Pairs of Double-Precision Floating-Point Values (Broadcast). // // Forms: // -// VEXTRACTF128 imm8 ymm xmm -// VEXTRACTF128 imm8 ymm m128 -// Construct and append a VEXTRACTF128 instruction to the active function. +// VRANGEPD.BCST imm8 m64 xmm k xmm +// VRANGEPD.BCST imm8 m64 xmm xmm +// VRANGEPD.BCST imm8 m64 ymm k ymm +// VRANGEPD.BCST imm8 m64 ymm ymm +// VRANGEPD.BCST imm8 m64 zmm k zmm +// VRANGEPD.BCST imm8 m64 zmm zmm +// Construct and append a VRANGEPD.BCST instruction to the active function. // Operates on the global context. -func VEXTRACTF128(i, y, mx operand.Op) { ctx.VEXTRACTF128(i, y, mx) } +func VRANGEPD_BCST(ops ...operand.Op) { ctx.VRANGEPD_BCST(ops...) } -// VEXTRACTI128: Extract Packed Integer Values. +// VRANGEPD_BCST_Z: Range Restriction Calculation For Packed Pairs of Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VEXTRACTI128 imm8 ymm xmm -// VEXTRACTI128 imm8 ymm m128 -// Construct and append a VEXTRACTI128 instruction to the active function. -func (c *Context) VEXTRACTI128(i, y, mx operand.Op) { - if inst, err := x86.VEXTRACTI128(i, y, mx); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRANGEPD.BCST.Z imm8 m64 xmm k xmm +// VRANGEPD.BCST.Z imm8 m64 ymm k ymm +// VRANGEPD.BCST.Z imm8 m64 zmm k zmm +// Construct and append a VRANGEPD.BCST.Z instruction to the active function. +func (c *Context) VRANGEPD_BCST_Z(i, m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VRANGEPD_BCST_Z(i, m, xyz, k, xyz1)) } -// VEXTRACTI128: Extract Packed Integer Values. +// VRANGEPD_BCST_Z: Range Restriction Calculation For Packed Pairs of Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VEXTRACTI128 imm8 ymm xmm -// VEXTRACTI128 imm8 ymm m128 -// Construct and append a VEXTRACTI128 instruction to the active function. +// VRANGEPD.BCST.Z imm8 m64 xmm k xmm +// VRANGEPD.BCST.Z imm8 m64 ymm k ymm +// VRANGEPD.BCST.Z imm8 m64 zmm k zmm +// Construct and append a VRANGEPD.BCST.Z instruction to the active function. // Operates on the global context. -func VEXTRACTI128(i, y, mx operand.Op) { ctx.VEXTRACTI128(i, y, mx) } +func VRANGEPD_BCST_Z(i, m, xyz, k, xyz1 operand.Op) { ctx.VRANGEPD_BCST_Z(i, m, xyz, k, xyz1) } -// VEXTRACTPS: Extract Packed Single Precision Floating-Point Value. +// VRANGEPD_SAE: Range Restriction Calculation For Packed Pairs of Double-Precision Floating-Point Values (Suppress All Exceptions). // // Forms: // -// VEXTRACTPS imm8 xmm r32 -// VEXTRACTPS imm8 xmm m32 -// Construct and append a VEXTRACTPS instruction to the active function. -func (c *Context) VEXTRACTPS(i, x, mr operand.Op) { - if inst, err := x86.VEXTRACTPS(i, x, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRANGEPD.SAE imm8 zmm zmm k zmm +// VRANGEPD.SAE imm8 zmm zmm zmm +// Construct and append a VRANGEPD.SAE instruction to the active function. +func (c *Context) VRANGEPD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VRANGEPD_SAE(ops...)) } -// VEXTRACTPS: Extract Packed Single Precision Floating-Point Value. +// VRANGEPD_SAE: Range Restriction Calculation For Packed Pairs of Double-Precision Floating-Point Values (Suppress All Exceptions). // // Forms: // -// VEXTRACTPS imm8 xmm r32 -// VEXTRACTPS imm8 xmm m32 -// Construct and append a VEXTRACTPS instruction to the active function. +// VRANGEPD.SAE imm8 zmm zmm k zmm +// VRANGEPD.SAE imm8 zmm zmm zmm +// Construct and append a VRANGEPD.SAE instruction to the active function. // Operates on the global context. -func VEXTRACTPS(i, x, mr operand.Op) { ctx.VEXTRACTPS(i, x, mr) } +func VRANGEPD_SAE(ops ...operand.Op) { ctx.VRANGEPD_SAE(ops...) } -// VFMADD132PD: Fused Multiply-Add of Packed Double-Precision Floating-Point Values. +// VRANGEPD_SAE_Z: Range Restriction Calculation For Packed Pairs of Double-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VFMADD132PD xmm xmm xmm -// VFMADD132PD m128 xmm xmm -// VFMADD132PD ymm ymm ymm -// VFMADD132PD m256 ymm ymm -// Construct and append a VFMADD132PD instruction to the active function. -func (c *Context) VFMADD132PD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFMADD132PD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRANGEPD.SAE.Z imm8 zmm zmm k zmm +// Construct and append a VRANGEPD.SAE.Z instruction to the active function. +func (c *Context) VRANGEPD_SAE_Z(i, z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VRANGEPD_SAE_Z(i, z, z1, k, z2)) } -// VFMADD132PD: Fused Multiply-Add of Packed Double-Precision Floating-Point Values. +// VRANGEPD_SAE_Z: Range Restriction Calculation For Packed Pairs of Double-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VFMADD132PD xmm xmm xmm -// VFMADD132PD m128 xmm xmm -// VFMADD132PD ymm ymm ymm -// VFMADD132PD m256 ymm ymm -// Construct and append a VFMADD132PD instruction to the active function. +// VRANGEPD.SAE.Z imm8 zmm zmm k zmm +// Construct and append a VRANGEPD.SAE.Z instruction to the active function. // Operates on the global context. -func VFMADD132PD(mxy, xy, xy1 operand.Op) { ctx.VFMADD132PD(mxy, xy, xy1) } +func VRANGEPD_SAE_Z(i, z, z1, k, z2 operand.Op) { ctx.VRANGEPD_SAE_Z(i, z, z1, k, z2) } -// VFMADD132PS: Fused Multiply-Add of Packed Single-Precision Floating-Point Values. +// VRANGEPD_Z: Range Restriction Calculation For Packed Pairs of Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VFMADD132PS xmm xmm xmm -// VFMADD132PS m128 xmm xmm -// VFMADD132PS ymm ymm ymm -// VFMADD132PS m256 ymm ymm -// Construct and append a VFMADD132PS instruction to the active function. -func (c *Context) VFMADD132PS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFMADD132PS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRANGEPD.Z imm8 m128 xmm k xmm +// VRANGEPD.Z imm8 m256 ymm k ymm +// VRANGEPD.Z imm8 xmm xmm k xmm +// VRANGEPD.Z imm8 ymm ymm k ymm +// VRANGEPD.Z imm8 m512 zmm k zmm +// VRANGEPD.Z imm8 zmm zmm k zmm +// Construct and append a VRANGEPD.Z instruction to the active function. +func (c *Context) VRANGEPD_Z(i, mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VRANGEPD_Z(i, mxyz, xyz, k, xyz1)) } -// VFMADD132PS: Fused Multiply-Add of Packed Single-Precision Floating-Point Values. +// VRANGEPD_Z: Range Restriction Calculation For Packed Pairs of Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VFMADD132PS xmm xmm xmm -// VFMADD132PS m128 xmm xmm -// VFMADD132PS ymm ymm ymm -// VFMADD132PS m256 ymm ymm -// Construct and append a VFMADD132PS instruction to the active function. +// VRANGEPD.Z imm8 m128 xmm k xmm +// VRANGEPD.Z imm8 m256 ymm k ymm +// VRANGEPD.Z imm8 xmm xmm k xmm +// VRANGEPD.Z imm8 ymm ymm k ymm +// VRANGEPD.Z imm8 m512 zmm k zmm +// VRANGEPD.Z imm8 zmm zmm k zmm +// Construct and append a VRANGEPD.Z instruction to the active function. // Operates on the global context. -func VFMADD132PS(mxy, xy, xy1 operand.Op) { ctx.VFMADD132PS(mxy, xy, xy1) } +func VRANGEPD_Z(i, mxyz, xyz, k, xyz1 operand.Op) { ctx.VRANGEPD_Z(i, mxyz, xyz, k, xyz1) } -// VFMADD132SD: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values. +// VRANGEPS: Range Restriction Calculation For Packed Pairs of Single-Precision Floating-Point Values. // // Forms: // -// VFMADD132SD xmm xmm xmm -// VFMADD132SD m64 xmm xmm -// Construct and append a VFMADD132SD instruction to the active function. -func (c *Context) VFMADD132SD(mx, x, x1 operand.Op) { - if inst, err := x86.VFMADD132SD(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRANGEPS imm8 m128 xmm k xmm +// VRANGEPS imm8 m128 xmm xmm +// VRANGEPS imm8 m256 ymm k ymm +// VRANGEPS imm8 m256 ymm ymm +// VRANGEPS imm8 xmm xmm k xmm +// VRANGEPS imm8 xmm xmm xmm +// VRANGEPS imm8 ymm ymm k ymm +// VRANGEPS imm8 ymm ymm ymm +// VRANGEPS imm8 m512 zmm k zmm +// VRANGEPS imm8 m512 zmm zmm +// VRANGEPS imm8 zmm zmm k zmm +// VRANGEPS imm8 zmm zmm zmm +// Construct and append a VRANGEPS instruction to the active function. +func (c *Context) VRANGEPS(ops ...operand.Op) { + c.addinstruction(x86.VRANGEPS(ops...)) } -// VFMADD132SD: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values. +// VRANGEPS: Range Restriction Calculation For Packed Pairs of Single-Precision Floating-Point Values. // // Forms: // -// VFMADD132SD xmm xmm xmm -// VFMADD132SD m64 xmm xmm -// Construct and append a VFMADD132SD instruction to the active function. +// VRANGEPS imm8 m128 xmm k xmm +// VRANGEPS imm8 m128 xmm xmm +// VRANGEPS imm8 m256 ymm k ymm +// VRANGEPS imm8 m256 ymm ymm +// VRANGEPS imm8 xmm xmm k xmm +// VRANGEPS imm8 xmm xmm xmm +// VRANGEPS imm8 ymm ymm k ymm +// VRANGEPS imm8 ymm ymm ymm +// VRANGEPS imm8 m512 zmm k zmm +// VRANGEPS imm8 m512 zmm zmm +// VRANGEPS imm8 zmm zmm k zmm +// VRANGEPS imm8 zmm zmm zmm +// Construct and append a VRANGEPS instruction to the active function. // Operates on the global context. -func VFMADD132SD(mx, x, x1 operand.Op) { ctx.VFMADD132SD(mx, x, x1) } +func VRANGEPS(ops ...operand.Op) { ctx.VRANGEPS(ops...) } -// VFMADD132SS: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values. +// VRANGEPS_BCST: Range Restriction Calculation For Packed Pairs of Single-Precision Floating-Point Values (Broadcast). // // Forms: // -// VFMADD132SS xmm xmm xmm -// VFMADD132SS m32 xmm xmm -// Construct and append a VFMADD132SS instruction to the active function. -func (c *Context) VFMADD132SS(mx, x, x1 operand.Op) { - if inst, err := x86.VFMADD132SS(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRANGEPS.BCST imm8 m32 xmm k xmm +// VRANGEPS.BCST imm8 m32 xmm xmm +// VRANGEPS.BCST imm8 m32 ymm k ymm +// VRANGEPS.BCST imm8 m32 ymm ymm +// VRANGEPS.BCST imm8 m32 zmm k zmm +// VRANGEPS.BCST imm8 m32 zmm zmm +// Construct and append a VRANGEPS.BCST instruction to the active function. +func (c *Context) VRANGEPS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VRANGEPS_BCST(ops...)) } -// VFMADD132SS: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values. +// VRANGEPS_BCST: Range Restriction Calculation For Packed Pairs of Single-Precision Floating-Point Values (Broadcast). // // Forms: // -// VFMADD132SS xmm xmm xmm -// VFMADD132SS m32 xmm xmm -// Construct and append a VFMADD132SS instruction to the active function. +// VRANGEPS.BCST imm8 m32 xmm k xmm +// VRANGEPS.BCST imm8 m32 xmm xmm +// VRANGEPS.BCST imm8 m32 ymm k ymm +// VRANGEPS.BCST imm8 m32 ymm ymm +// VRANGEPS.BCST imm8 m32 zmm k zmm +// VRANGEPS.BCST imm8 m32 zmm zmm +// Construct and append a VRANGEPS.BCST instruction to the active function. // Operates on the global context. -func VFMADD132SS(mx, x, x1 operand.Op) { ctx.VFMADD132SS(mx, x, x1) } +func VRANGEPS_BCST(ops ...operand.Op) { ctx.VRANGEPS_BCST(ops...) } -// VFMADD213PD: Fused Multiply-Add of Packed Double-Precision Floating-Point Values. +// VRANGEPS_BCST_Z: Range Restriction Calculation For Packed Pairs of Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VFMADD213PD xmm xmm xmm -// VFMADD213PD m128 xmm xmm -// VFMADD213PD ymm ymm ymm -// VFMADD213PD m256 ymm ymm -// Construct and append a VFMADD213PD instruction to the active function. -func (c *Context) VFMADD213PD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFMADD213PD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRANGEPS.BCST.Z imm8 m32 xmm k xmm +// VRANGEPS.BCST.Z imm8 m32 ymm k ymm +// VRANGEPS.BCST.Z imm8 m32 zmm k zmm +// Construct and append a VRANGEPS.BCST.Z instruction to the active function. +func (c *Context) VRANGEPS_BCST_Z(i, m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VRANGEPS_BCST_Z(i, m, xyz, k, xyz1)) } -// VFMADD213PD: Fused Multiply-Add of Packed Double-Precision Floating-Point Values. +// VRANGEPS_BCST_Z: Range Restriction Calculation For Packed Pairs of Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VFMADD213PD xmm xmm xmm -// VFMADD213PD m128 xmm xmm -// VFMADD213PD ymm ymm ymm -// VFMADD213PD m256 ymm ymm -// Construct and append a VFMADD213PD instruction to the active function. +// VRANGEPS.BCST.Z imm8 m32 xmm k xmm +// VRANGEPS.BCST.Z imm8 m32 ymm k ymm +// VRANGEPS.BCST.Z imm8 m32 zmm k zmm +// Construct and append a VRANGEPS.BCST.Z instruction to the active function. // Operates on the global context. -func VFMADD213PD(mxy, xy, xy1 operand.Op) { ctx.VFMADD213PD(mxy, xy, xy1) } +func VRANGEPS_BCST_Z(i, m, xyz, k, xyz1 operand.Op) { ctx.VRANGEPS_BCST_Z(i, m, xyz, k, xyz1) } -// VFMADD213PS: Fused Multiply-Add of Packed Single-Precision Floating-Point Values. +// VRANGEPS_SAE: Range Restriction Calculation For Packed Pairs of Single-Precision Floating-Point Values (Suppress All Exceptions). // // Forms: // -// VFMADD213PS xmm xmm xmm -// VFMADD213PS m128 xmm xmm -// VFMADD213PS ymm ymm ymm -// VFMADD213PS m256 ymm ymm -// Construct and append a VFMADD213PS instruction to the active function. -func (c *Context) VFMADD213PS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFMADD213PS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRANGEPS.SAE imm8 zmm zmm k zmm +// VRANGEPS.SAE imm8 zmm zmm zmm +// Construct and append a VRANGEPS.SAE instruction to the active function. +func (c *Context) VRANGEPS_SAE(ops ...operand.Op) { + c.addinstruction(x86.VRANGEPS_SAE(ops...)) } -// VFMADD213PS: Fused Multiply-Add of Packed Single-Precision Floating-Point Values. +// VRANGEPS_SAE: Range Restriction Calculation For Packed Pairs of Single-Precision Floating-Point Values (Suppress All Exceptions). // // Forms: // -// VFMADD213PS xmm xmm xmm -// VFMADD213PS m128 xmm xmm -// VFMADD213PS ymm ymm ymm -// VFMADD213PS m256 ymm ymm -// Construct and append a VFMADD213PS instruction to the active function. +// VRANGEPS.SAE imm8 zmm zmm k zmm +// VRANGEPS.SAE imm8 zmm zmm zmm +// Construct and append a VRANGEPS.SAE instruction to the active function. // Operates on the global context. -func VFMADD213PS(mxy, xy, xy1 operand.Op) { ctx.VFMADD213PS(mxy, xy, xy1) } +func VRANGEPS_SAE(ops ...operand.Op) { ctx.VRANGEPS_SAE(ops...) } -// VFMADD213SD: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values. +// VRANGEPS_SAE_Z: Range Restriction Calculation For Packed Pairs of Single-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VFMADD213SD xmm xmm xmm -// VFMADD213SD m64 xmm xmm -// Construct and append a VFMADD213SD instruction to the active function. -func (c *Context) VFMADD213SD(mx, x, x1 operand.Op) { - if inst, err := x86.VFMADD213SD(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRANGEPS.SAE.Z imm8 zmm zmm k zmm +// Construct and append a VRANGEPS.SAE.Z instruction to the active function. +func (c *Context) VRANGEPS_SAE_Z(i, z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VRANGEPS_SAE_Z(i, z, z1, k, z2)) } -// VFMADD213SD: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values. +// VRANGEPS_SAE_Z: Range Restriction Calculation For Packed Pairs of Single-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VFMADD213SD xmm xmm xmm -// VFMADD213SD m64 xmm xmm -// Construct and append a VFMADD213SD instruction to the active function. +// VRANGEPS.SAE.Z imm8 zmm zmm k zmm +// Construct and append a VRANGEPS.SAE.Z instruction to the active function. // Operates on the global context. -func VFMADD213SD(mx, x, x1 operand.Op) { ctx.VFMADD213SD(mx, x, x1) } +func VRANGEPS_SAE_Z(i, z, z1, k, z2 operand.Op) { ctx.VRANGEPS_SAE_Z(i, z, z1, k, z2) } -// VFMADD213SS: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values. +// VRANGEPS_Z: Range Restriction Calculation For Packed Pairs of Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VFMADD213SS xmm xmm xmm -// VFMADD213SS m32 xmm xmm -// Construct and append a VFMADD213SS instruction to the active function. -func (c *Context) VFMADD213SS(mx, x, x1 operand.Op) { - if inst, err := x86.VFMADD213SS(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRANGEPS.Z imm8 m128 xmm k xmm +// VRANGEPS.Z imm8 m256 ymm k ymm +// VRANGEPS.Z imm8 xmm xmm k xmm +// VRANGEPS.Z imm8 ymm ymm k ymm +// VRANGEPS.Z imm8 m512 zmm k zmm +// VRANGEPS.Z imm8 zmm zmm k zmm +// Construct and append a VRANGEPS.Z instruction to the active function. +func (c *Context) VRANGEPS_Z(i, mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VRANGEPS_Z(i, mxyz, xyz, k, xyz1)) } -// VFMADD213SS: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values. +// VRANGEPS_Z: Range Restriction Calculation For Packed Pairs of Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VFMADD213SS xmm xmm xmm -// VFMADD213SS m32 xmm xmm -// Construct and append a VFMADD213SS instruction to the active function. +// VRANGEPS.Z imm8 m128 xmm k xmm +// VRANGEPS.Z imm8 m256 ymm k ymm +// VRANGEPS.Z imm8 xmm xmm k xmm +// VRANGEPS.Z imm8 ymm ymm k ymm +// VRANGEPS.Z imm8 m512 zmm k zmm +// VRANGEPS.Z imm8 zmm zmm k zmm +// Construct and append a VRANGEPS.Z instruction to the active function. // Operates on the global context. -func VFMADD213SS(mx, x, x1 operand.Op) { ctx.VFMADD213SS(mx, x, x1) } +func VRANGEPS_Z(i, mxyz, xyz, k, xyz1 operand.Op) { ctx.VRANGEPS_Z(i, mxyz, xyz, k, xyz1) } -// VFMADD231PD: Fused Multiply-Add of Packed Double-Precision Floating-Point Values. +// VRANGESD: Range Restriction Calculation For a pair of Scalar Double-Precision Floating-Point Values. // // Forms: // -// VFMADD231PD xmm xmm xmm -// VFMADD231PD m128 xmm xmm -// VFMADD231PD ymm ymm ymm -// VFMADD231PD m256 ymm ymm -// Construct and append a VFMADD231PD instruction to the active function. -func (c *Context) VFMADD231PD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFMADD231PD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRANGESD imm8 m64 xmm k xmm +// VRANGESD imm8 m64 xmm xmm +// VRANGESD imm8 xmm xmm k xmm +// VRANGESD imm8 xmm xmm xmm +// Construct and append a VRANGESD instruction to the active function. +func (c *Context) VRANGESD(ops ...operand.Op) { + c.addinstruction(x86.VRANGESD(ops...)) } -// VFMADD231PD: Fused Multiply-Add of Packed Double-Precision Floating-Point Values. +// VRANGESD: Range Restriction Calculation For a pair of Scalar Double-Precision Floating-Point Values. // // Forms: // -// VFMADD231PD xmm xmm xmm -// VFMADD231PD m128 xmm xmm -// VFMADD231PD ymm ymm ymm -// VFMADD231PD m256 ymm ymm -// Construct and append a VFMADD231PD instruction to the active function. +// VRANGESD imm8 m64 xmm k xmm +// VRANGESD imm8 m64 xmm xmm +// VRANGESD imm8 xmm xmm k xmm +// VRANGESD imm8 xmm xmm xmm +// Construct and append a VRANGESD instruction to the active function. // Operates on the global context. -func VFMADD231PD(mxy, xy, xy1 operand.Op) { ctx.VFMADD231PD(mxy, xy, xy1) } +func VRANGESD(ops ...operand.Op) { ctx.VRANGESD(ops...) } -// VFMADD231PS: Fused Multiply-Add of Packed Single-Precision Floating-Point Values. +// VRANGESD_SAE: Range Restriction Calculation For a pair of Scalar Double-Precision Floating-Point Values (Suppress All Exceptions). // // Forms: // -// VFMADD231PS xmm xmm xmm -// VFMADD231PS m128 xmm xmm -// VFMADD231PS ymm ymm ymm -// VFMADD231PS m256 ymm ymm -// Construct and append a VFMADD231PS instruction to the active function. -func (c *Context) VFMADD231PS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFMADD231PS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRANGESD.SAE imm8 xmm xmm k xmm +// VRANGESD.SAE imm8 xmm xmm xmm +// Construct and append a VRANGESD.SAE instruction to the active function. +func (c *Context) VRANGESD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VRANGESD_SAE(ops...)) } -// VFMADD231PS: Fused Multiply-Add of Packed Single-Precision Floating-Point Values. +// VRANGESD_SAE: Range Restriction Calculation For a pair of Scalar Double-Precision Floating-Point Values (Suppress All Exceptions). // // Forms: // -// VFMADD231PS xmm xmm xmm -// VFMADD231PS m128 xmm xmm -// VFMADD231PS ymm ymm ymm -// VFMADD231PS m256 ymm ymm -// Construct and append a VFMADD231PS instruction to the active function. +// VRANGESD.SAE imm8 xmm xmm k xmm +// VRANGESD.SAE imm8 xmm xmm xmm +// Construct and append a VRANGESD.SAE instruction to the active function. // Operates on the global context. -func VFMADD231PS(mxy, xy, xy1 operand.Op) { ctx.VFMADD231PS(mxy, xy, xy1) } +func VRANGESD_SAE(ops ...operand.Op) { ctx.VRANGESD_SAE(ops...) } -// VFMADD231SD: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values. +// VRANGESD_SAE_Z: Range Restriction Calculation For a pair of Scalar Double-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VFMADD231SD xmm xmm xmm -// VFMADD231SD m64 xmm xmm -// Construct and append a VFMADD231SD instruction to the active function. -func (c *Context) VFMADD231SD(mx, x, x1 operand.Op) { - if inst, err := x86.VFMADD231SD(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRANGESD.SAE.Z imm8 xmm xmm k xmm +// Construct and append a VRANGESD.SAE.Z instruction to the active function. +func (c *Context) VRANGESD_SAE_Z(i, x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VRANGESD_SAE_Z(i, x, x1, k, x2)) } -// VFMADD231SD: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values. +// VRANGESD_SAE_Z: Range Restriction Calculation For a pair of Scalar Double-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VFMADD231SD xmm xmm xmm -// VFMADD231SD m64 xmm xmm -// Construct and append a VFMADD231SD instruction to the active function. +// VRANGESD.SAE.Z imm8 xmm xmm k xmm +// Construct and append a VRANGESD.SAE.Z instruction to the active function. // Operates on the global context. -func VFMADD231SD(mx, x, x1 operand.Op) { ctx.VFMADD231SD(mx, x, x1) } +func VRANGESD_SAE_Z(i, x, x1, k, x2 operand.Op) { ctx.VRANGESD_SAE_Z(i, x, x1, k, x2) } -// VFMADD231SS: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values. +// VRANGESD_Z: Range Restriction Calculation For a pair of Scalar Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VFMADD231SS xmm xmm xmm -// VFMADD231SS m32 xmm xmm -// Construct and append a VFMADD231SS instruction to the active function. -func (c *Context) VFMADD231SS(mx, x, x1 operand.Op) { - if inst, err := x86.VFMADD231SS(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRANGESD.Z imm8 m64 xmm k xmm +// VRANGESD.Z imm8 xmm xmm k xmm +// Construct and append a VRANGESD.Z instruction to the active function. +func (c *Context) VRANGESD_Z(i, mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VRANGESD_Z(i, mx, x, k, x1)) } -// VFMADD231SS: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values. +// VRANGESD_Z: Range Restriction Calculation For a pair of Scalar Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VFMADD231SS xmm xmm xmm -// VFMADD231SS m32 xmm xmm -// Construct and append a VFMADD231SS instruction to the active function. +// VRANGESD.Z imm8 m64 xmm k xmm +// VRANGESD.Z imm8 xmm xmm k xmm +// Construct and append a VRANGESD.Z instruction to the active function. // Operates on the global context. -func VFMADD231SS(mx, x, x1 operand.Op) { ctx.VFMADD231SS(mx, x, x1) } +func VRANGESD_Z(i, mx, x, k, x1 operand.Op) { ctx.VRANGESD_Z(i, mx, x, k, x1) } -// VFMADDSUB132PD: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values. +// VRANGESS: Range Restriction Calculation For a pair of Scalar Single-Precision Floating-Point Values. // // Forms: // -// VFMADDSUB132PD xmm xmm xmm -// VFMADDSUB132PD m128 xmm xmm -// VFMADDSUB132PD ymm ymm ymm -// VFMADDSUB132PD m256 ymm ymm -// Construct and append a VFMADDSUB132PD instruction to the active function. -func (c *Context) VFMADDSUB132PD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFMADDSUB132PD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRANGESS imm8 m32 xmm k xmm +// VRANGESS imm8 m32 xmm xmm +// VRANGESS imm8 xmm xmm k xmm +// VRANGESS imm8 xmm xmm xmm +// Construct and append a VRANGESS instruction to the active function. +func (c *Context) VRANGESS(ops ...operand.Op) { + c.addinstruction(x86.VRANGESS(ops...)) } -// VFMADDSUB132PD: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values. +// VRANGESS: Range Restriction Calculation For a pair of Scalar Single-Precision Floating-Point Values. // // Forms: // -// VFMADDSUB132PD xmm xmm xmm -// VFMADDSUB132PD m128 xmm xmm -// VFMADDSUB132PD ymm ymm ymm -// VFMADDSUB132PD m256 ymm ymm -// Construct and append a VFMADDSUB132PD instruction to the active function. +// VRANGESS imm8 m32 xmm k xmm +// VRANGESS imm8 m32 xmm xmm +// VRANGESS imm8 xmm xmm k xmm +// VRANGESS imm8 xmm xmm xmm +// Construct and append a VRANGESS instruction to the active function. // Operates on the global context. -func VFMADDSUB132PD(mxy, xy, xy1 operand.Op) { ctx.VFMADDSUB132PD(mxy, xy, xy1) } +func VRANGESS(ops ...operand.Op) { ctx.VRANGESS(ops...) } -// VFMADDSUB132PS: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values. +// VRANGESS_SAE: Range Restriction Calculation For a pair of Scalar Single-Precision Floating-Point Values (Suppress All Exceptions). // // Forms: // -// VFMADDSUB132PS xmm xmm xmm -// VFMADDSUB132PS m128 xmm xmm -// VFMADDSUB132PS ymm ymm ymm -// VFMADDSUB132PS m256 ymm ymm -// Construct and append a VFMADDSUB132PS instruction to the active function. -func (c *Context) VFMADDSUB132PS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFMADDSUB132PS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRANGESS.SAE imm8 xmm xmm k xmm +// VRANGESS.SAE imm8 xmm xmm xmm +// Construct and append a VRANGESS.SAE instruction to the active function. +func (c *Context) VRANGESS_SAE(ops ...operand.Op) { + c.addinstruction(x86.VRANGESS_SAE(ops...)) } -// VFMADDSUB132PS: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values. +// VRANGESS_SAE: Range Restriction Calculation For a pair of Scalar Single-Precision Floating-Point Values (Suppress All Exceptions). // // Forms: // -// VFMADDSUB132PS xmm xmm xmm -// VFMADDSUB132PS m128 xmm xmm -// VFMADDSUB132PS ymm ymm ymm -// VFMADDSUB132PS m256 ymm ymm -// Construct and append a VFMADDSUB132PS instruction to the active function. +// VRANGESS.SAE imm8 xmm xmm k xmm +// VRANGESS.SAE imm8 xmm xmm xmm +// Construct and append a VRANGESS.SAE instruction to the active function. // Operates on the global context. -func VFMADDSUB132PS(mxy, xy, xy1 operand.Op) { ctx.VFMADDSUB132PS(mxy, xy, xy1) } +func VRANGESS_SAE(ops ...operand.Op) { ctx.VRANGESS_SAE(ops...) } -// VFMADDSUB213PD: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values. +// VRANGESS_SAE_Z: Range Restriction Calculation For a pair of Scalar Single-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VFMADDSUB213PD xmm xmm xmm -// VFMADDSUB213PD m128 xmm xmm -// VFMADDSUB213PD ymm ymm ymm -// VFMADDSUB213PD m256 ymm ymm -// Construct and append a VFMADDSUB213PD instruction to the active function. -func (c *Context) VFMADDSUB213PD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFMADDSUB213PD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRANGESS.SAE.Z imm8 xmm xmm k xmm +// Construct and append a VRANGESS.SAE.Z instruction to the active function. +func (c *Context) VRANGESS_SAE_Z(i, x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VRANGESS_SAE_Z(i, x, x1, k, x2)) } -// VFMADDSUB213PD: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values. +// VRANGESS_SAE_Z: Range Restriction Calculation For a pair of Scalar Single-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VFMADDSUB213PD xmm xmm xmm -// VFMADDSUB213PD m128 xmm xmm -// VFMADDSUB213PD ymm ymm ymm -// VFMADDSUB213PD m256 ymm ymm -// Construct and append a VFMADDSUB213PD instruction to the active function. +// VRANGESS.SAE.Z imm8 xmm xmm k xmm +// Construct and append a VRANGESS.SAE.Z instruction to the active function. // Operates on the global context. -func VFMADDSUB213PD(mxy, xy, xy1 operand.Op) { ctx.VFMADDSUB213PD(mxy, xy, xy1) } +func VRANGESS_SAE_Z(i, x, x1, k, x2 operand.Op) { ctx.VRANGESS_SAE_Z(i, x, x1, k, x2) } -// VFMADDSUB213PS: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values. +// VRANGESS_Z: Range Restriction Calculation For a pair of Scalar Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VFMADDSUB213PS xmm xmm xmm -// VFMADDSUB213PS m128 xmm xmm -// VFMADDSUB213PS ymm ymm ymm -// VFMADDSUB213PS m256 ymm ymm -// Construct and append a VFMADDSUB213PS instruction to the active function. -func (c *Context) VFMADDSUB213PS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFMADDSUB213PS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRANGESS.Z imm8 m32 xmm k xmm +// VRANGESS.Z imm8 xmm xmm k xmm +// Construct and append a VRANGESS.Z instruction to the active function. +func (c *Context) VRANGESS_Z(i, mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VRANGESS_Z(i, mx, x, k, x1)) } -// VFMADDSUB213PS: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values. +// VRANGESS_Z: Range Restriction Calculation For a pair of Scalar Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VFMADDSUB213PS xmm xmm xmm -// VFMADDSUB213PS m128 xmm xmm -// VFMADDSUB213PS ymm ymm ymm -// VFMADDSUB213PS m256 ymm ymm -// Construct and append a VFMADDSUB213PS instruction to the active function. +// VRANGESS.Z imm8 m32 xmm k xmm +// VRANGESS.Z imm8 xmm xmm k xmm +// Construct and append a VRANGESS.Z instruction to the active function. // Operates on the global context. -func VFMADDSUB213PS(mxy, xy, xy1 operand.Op) { ctx.VFMADDSUB213PS(mxy, xy, xy1) } +func VRANGESS_Z(i, mx, x, k, x1 operand.Op) { ctx.VRANGESS_Z(i, mx, x, k, x1) } -// VFMADDSUB231PD: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values. +// VRCP14PD: Compute Approximate Reciprocals of Packed Double-Precision Floating-Point Values. // // Forms: // -// VFMADDSUB231PD xmm xmm xmm -// VFMADDSUB231PD m128 xmm xmm -// VFMADDSUB231PD ymm ymm ymm -// VFMADDSUB231PD m256 ymm ymm -// Construct and append a VFMADDSUB231PD instruction to the active function. -func (c *Context) VFMADDSUB231PD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFMADDSUB231PD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP14PD m128 k xmm +// VRCP14PD m128 xmm +// VRCP14PD m256 k ymm +// VRCP14PD m256 ymm +// VRCP14PD xmm k xmm +// VRCP14PD xmm xmm +// VRCP14PD ymm k ymm +// VRCP14PD ymm ymm +// VRCP14PD m512 k zmm +// VRCP14PD m512 zmm +// VRCP14PD zmm k zmm +// VRCP14PD zmm zmm +// Construct and append a VRCP14PD instruction to the active function. +func (c *Context) VRCP14PD(ops ...operand.Op) { + c.addinstruction(x86.VRCP14PD(ops...)) } -// VFMADDSUB231PD: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values. +// VRCP14PD: Compute Approximate Reciprocals of Packed Double-Precision Floating-Point Values. // // Forms: // -// VFMADDSUB231PD xmm xmm xmm -// VFMADDSUB231PD m128 xmm xmm -// VFMADDSUB231PD ymm ymm ymm -// VFMADDSUB231PD m256 ymm ymm -// Construct and append a VFMADDSUB231PD instruction to the active function. +// VRCP14PD m128 k xmm +// VRCP14PD m128 xmm +// VRCP14PD m256 k ymm +// VRCP14PD m256 ymm +// VRCP14PD xmm k xmm +// VRCP14PD xmm xmm +// VRCP14PD ymm k ymm +// VRCP14PD ymm ymm +// VRCP14PD m512 k zmm +// VRCP14PD m512 zmm +// VRCP14PD zmm k zmm +// VRCP14PD zmm zmm +// Construct and append a VRCP14PD instruction to the active function. // Operates on the global context. -func VFMADDSUB231PD(mxy, xy, xy1 operand.Op) { ctx.VFMADDSUB231PD(mxy, xy, xy1) } +func VRCP14PD(ops ...operand.Op) { ctx.VRCP14PD(ops...) } -// VFMADDSUB231PS: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values. +// VRCP14PD_BCST: Compute Approximate Reciprocals of Packed Double-Precision Floating-Point Values (Broadcast). // // Forms: // -// VFMADDSUB231PS xmm xmm xmm -// VFMADDSUB231PS m128 xmm xmm -// VFMADDSUB231PS ymm ymm ymm -// VFMADDSUB231PS m256 ymm ymm -// Construct and append a VFMADDSUB231PS instruction to the active function. -func (c *Context) VFMADDSUB231PS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFMADDSUB231PS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP14PD.BCST m64 k xmm +// VRCP14PD.BCST m64 k ymm +// VRCP14PD.BCST m64 xmm +// VRCP14PD.BCST m64 ymm +// VRCP14PD.BCST m64 k zmm +// VRCP14PD.BCST m64 zmm +// Construct and append a VRCP14PD.BCST instruction to the active function. +func (c *Context) VRCP14PD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VRCP14PD_BCST(ops...)) } -// VFMADDSUB231PS: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values. +// VRCP14PD_BCST: Compute Approximate Reciprocals of Packed Double-Precision Floating-Point Values (Broadcast). // // Forms: // -// VFMADDSUB231PS xmm xmm xmm -// VFMADDSUB231PS m128 xmm xmm -// VFMADDSUB231PS ymm ymm ymm -// VFMADDSUB231PS m256 ymm ymm -// Construct and append a VFMADDSUB231PS instruction to the active function. +// VRCP14PD.BCST m64 k xmm +// VRCP14PD.BCST m64 k ymm +// VRCP14PD.BCST m64 xmm +// VRCP14PD.BCST m64 ymm +// VRCP14PD.BCST m64 k zmm +// VRCP14PD.BCST m64 zmm +// Construct and append a VRCP14PD.BCST instruction to the active function. // Operates on the global context. -func VFMADDSUB231PS(mxy, xy, xy1 operand.Op) { ctx.VFMADDSUB231PS(mxy, xy, xy1) } +func VRCP14PD_BCST(ops ...operand.Op) { ctx.VRCP14PD_BCST(ops...) } -// VFMSUB132PD: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// VRCP14PD_BCST_Z: Compute Approximate Reciprocals of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VFMSUB132PD xmm xmm xmm -// VFMSUB132PD m128 xmm xmm -// VFMSUB132PD ymm ymm ymm -// VFMSUB132PD m256 ymm ymm -// Construct and append a VFMSUB132PD instruction to the active function. -func (c *Context) VFMSUB132PD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFMSUB132PD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP14PD.BCST.Z m64 k xmm +// VRCP14PD.BCST.Z m64 k ymm +// VRCP14PD.BCST.Z m64 k zmm +// Construct and append a VRCP14PD.BCST.Z instruction to the active function. +func (c *Context) VRCP14PD_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VRCP14PD_BCST_Z(m, k, xyz)) } -// VFMSUB132PD: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// VRCP14PD_BCST_Z: Compute Approximate Reciprocals of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VFMSUB132PD xmm xmm xmm -// VFMSUB132PD m128 xmm xmm -// VFMSUB132PD ymm ymm ymm -// VFMSUB132PD m256 ymm ymm -// Construct and append a VFMSUB132PD instruction to the active function. +// VRCP14PD.BCST.Z m64 k xmm +// VRCP14PD.BCST.Z m64 k ymm +// VRCP14PD.BCST.Z m64 k zmm +// Construct and append a VRCP14PD.BCST.Z instruction to the active function. // Operates on the global context. -func VFMSUB132PD(mxy, xy, xy1 operand.Op) { ctx.VFMSUB132PD(mxy, xy, xy1) } +func VRCP14PD_BCST_Z(m, k, xyz operand.Op) { ctx.VRCP14PD_BCST_Z(m, k, xyz) } -// VFMSUB132PS: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// VRCP14PD_Z: Compute Approximate Reciprocals of Packed Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VFMSUB132PS xmm xmm xmm -// VFMSUB132PS m128 xmm xmm -// VFMSUB132PS ymm ymm ymm -// VFMSUB132PS m256 ymm ymm -// Construct and append a VFMSUB132PS instruction to the active function. -func (c *Context) VFMSUB132PS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFMSUB132PS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP14PD.Z m128 k xmm +// VRCP14PD.Z m256 k ymm +// VRCP14PD.Z xmm k xmm +// VRCP14PD.Z ymm k ymm +// VRCP14PD.Z m512 k zmm +// VRCP14PD.Z zmm k zmm +// Construct and append a VRCP14PD.Z instruction to the active function. +func (c *Context) VRCP14PD_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VRCP14PD_Z(mxyz, k, xyz)) } -// VFMSUB132PS: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// VRCP14PD_Z: Compute Approximate Reciprocals of Packed Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VFMSUB132PS xmm xmm xmm -// VFMSUB132PS m128 xmm xmm -// VFMSUB132PS ymm ymm ymm -// VFMSUB132PS m256 ymm ymm -// Construct and append a VFMSUB132PS instruction to the active function. +// VRCP14PD.Z m128 k xmm +// VRCP14PD.Z m256 k ymm +// VRCP14PD.Z xmm k xmm +// VRCP14PD.Z ymm k ymm +// VRCP14PD.Z m512 k zmm +// VRCP14PD.Z zmm k zmm +// Construct and append a VRCP14PD.Z instruction to the active function. // Operates on the global context. -func VFMSUB132PS(mxy, xy, xy1 operand.Op) { ctx.VFMSUB132PS(mxy, xy, xy1) } +func VRCP14PD_Z(mxyz, k, xyz operand.Op) { ctx.VRCP14PD_Z(mxyz, k, xyz) } -// VFMSUB132SD: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// VRCP14PS: Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values. // // Forms: // -// VFMSUB132SD xmm xmm xmm -// VFMSUB132SD m64 xmm xmm -// Construct and append a VFMSUB132SD instruction to the active function. -func (c *Context) VFMSUB132SD(mx, x, x1 operand.Op) { - if inst, err := x86.VFMSUB132SD(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP14PS m128 k xmm +// VRCP14PS m128 xmm +// VRCP14PS m256 k ymm +// VRCP14PS m256 ymm +// VRCP14PS xmm k xmm +// VRCP14PS xmm xmm +// VRCP14PS ymm k ymm +// VRCP14PS ymm ymm +// VRCP14PS m512 k zmm +// VRCP14PS m512 zmm +// VRCP14PS zmm k zmm +// VRCP14PS zmm zmm +// Construct and append a VRCP14PS instruction to the active function. +func (c *Context) VRCP14PS(ops ...operand.Op) { + c.addinstruction(x86.VRCP14PS(ops...)) } -// VFMSUB132SD: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// VRCP14PS: Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values. // // Forms: // -// VFMSUB132SD xmm xmm xmm -// VFMSUB132SD m64 xmm xmm -// Construct and append a VFMSUB132SD instruction to the active function. +// VRCP14PS m128 k xmm +// VRCP14PS m128 xmm +// VRCP14PS m256 k ymm +// VRCP14PS m256 ymm +// VRCP14PS xmm k xmm +// VRCP14PS xmm xmm +// VRCP14PS ymm k ymm +// VRCP14PS ymm ymm +// VRCP14PS m512 k zmm +// VRCP14PS m512 zmm +// VRCP14PS zmm k zmm +// VRCP14PS zmm zmm +// Construct and append a VRCP14PS instruction to the active function. // Operates on the global context. -func VFMSUB132SD(mx, x, x1 operand.Op) { ctx.VFMSUB132SD(mx, x, x1) } +func VRCP14PS(ops ...operand.Op) { ctx.VRCP14PS(ops...) } -// VFMSUB132SS: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// VRCP14PS_BCST: Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values (Broadcast). // // Forms: // -// VFMSUB132SS xmm xmm xmm -// VFMSUB132SS m32 xmm xmm -// Construct and append a VFMSUB132SS instruction to the active function. -func (c *Context) VFMSUB132SS(mx, x, x1 operand.Op) { - if inst, err := x86.VFMSUB132SS(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP14PS.BCST m32 k xmm +// VRCP14PS.BCST m32 k ymm +// VRCP14PS.BCST m32 xmm +// VRCP14PS.BCST m32 ymm +// VRCP14PS.BCST m32 k zmm +// VRCP14PS.BCST m32 zmm +// Construct and append a VRCP14PS.BCST instruction to the active function. +func (c *Context) VRCP14PS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VRCP14PS_BCST(ops...)) } -// VFMSUB132SS: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// VRCP14PS_BCST: Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values (Broadcast). // // Forms: // -// VFMSUB132SS xmm xmm xmm -// VFMSUB132SS m32 xmm xmm -// Construct and append a VFMSUB132SS instruction to the active function. +// VRCP14PS.BCST m32 k xmm +// VRCP14PS.BCST m32 k ymm +// VRCP14PS.BCST m32 xmm +// VRCP14PS.BCST m32 ymm +// VRCP14PS.BCST m32 k zmm +// VRCP14PS.BCST m32 zmm +// Construct and append a VRCP14PS.BCST instruction to the active function. // Operates on the global context. -func VFMSUB132SS(mx, x, x1 operand.Op) { ctx.VFMSUB132SS(mx, x, x1) } +func VRCP14PS_BCST(ops ...operand.Op) { ctx.VRCP14PS_BCST(ops...) } -// VFMSUB213PD: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// VRCP14PS_BCST_Z: Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VFMSUB213PD xmm xmm xmm -// VFMSUB213PD m128 xmm xmm -// VFMSUB213PD ymm ymm ymm -// VFMSUB213PD m256 ymm ymm -// Construct and append a VFMSUB213PD instruction to the active function. -func (c *Context) VFMSUB213PD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFMSUB213PD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP14PS.BCST.Z m32 k xmm +// VRCP14PS.BCST.Z m32 k ymm +// VRCP14PS.BCST.Z m32 k zmm +// Construct and append a VRCP14PS.BCST.Z instruction to the active function. +func (c *Context) VRCP14PS_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VRCP14PS_BCST_Z(m, k, xyz)) } -// VFMSUB213PD: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// VRCP14PS_BCST_Z: Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VFMSUB213PD xmm xmm xmm -// VFMSUB213PD m128 xmm xmm -// VFMSUB213PD ymm ymm ymm -// VFMSUB213PD m256 ymm ymm -// Construct and append a VFMSUB213PD instruction to the active function. +// VRCP14PS.BCST.Z m32 k xmm +// VRCP14PS.BCST.Z m32 k ymm +// VRCP14PS.BCST.Z m32 k zmm +// Construct and append a VRCP14PS.BCST.Z instruction to the active function. // Operates on the global context. -func VFMSUB213PD(mxy, xy, xy1 operand.Op) { ctx.VFMSUB213PD(mxy, xy, xy1) } +func VRCP14PS_BCST_Z(m, k, xyz operand.Op) { ctx.VRCP14PS_BCST_Z(m, k, xyz) } -// VFMSUB213PS: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// VRCP14PS_Z: Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VFMSUB213PS xmm xmm xmm -// VFMSUB213PS m128 xmm xmm -// VFMSUB213PS ymm ymm ymm -// VFMSUB213PS m256 ymm ymm -// Construct and append a VFMSUB213PS instruction to the active function. -func (c *Context) VFMSUB213PS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFMSUB213PS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP14PS.Z m128 k xmm +// VRCP14PS.Z m256 k ymm +// VRCP14PS.Z xmm k xmm +// VRCP14PS.Z ymm k ymm +// VRCP14PS.Z m512 k zmm +// VRCP14PS.Z zmm k zmm +// Construct and append a VRCP14PS.Z instruction to the active function. +func (c *Context) VRCP14PS_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VRCP14PS_Z(mxyz, k, xyz)) } -// VFMSUB213PS: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// VRCP14PS_Z: Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VFMSUB213PS xmm xmm xmm -// VFMSUB213PS m128 xmm xmm -// VFMSUB213PS ymm ymm ymm -// VFMSUB213PS m256 ymm ymm -// Construct and append a VFMSUB213PS instruction to the active function. +// VRCP14PS.Z m128 k xmm +// VRCP14PS.Z m256 k ymm +// VRCP14PS.Z xmm k xmm +// VRCP14PS.Z ymm k ymm +// VRCP14PS.Z m512 k zmm +// VRCP14PS.Z zmm k zmm +// Construct and append a VRCP14PS.Z instruction to the active function. // Operates on the global context. -func VFMSUB213PS(mxy, xy, xy1 operand.Op) { ctx.VFMSUB213PS(mxy, xy, xy1) } +func VRCP14PS_Z(mxyz, k, xyz operand.Op) { ctx.VRCP14PS_Z(mxyz, k, xyz) } -// VFMSUB213SD: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// VRCP14SD: Compute Approximate Reciprocal of a Scalar Double-Precision Floating-Point Value. // // Forms: // -// VFMSUB213SD xmm xmm xmm -// VFMSUB213SD m64 xmm xmm -// Construct and append a VFMSUB213SD instruction to the active function. -func (c *Context) VFMSUB213SD(mx, x, x1 operand.Op) { - if inst, err := x86.VFMSUB213SD(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP14SD m64 xmm k xmm +// VRCP14SD m64 xmm xmm +// VRCP14SD xmm xmm k xmm +// VRCP14SD xmm xmm xmm +// Construct and append a VRCP14SD instruction to the active function. +func (c *Context) VRCP14SD(ops ...operand.Op) { + c.addinstruction(x86.VRCP14SD(ops...)) } -// VFMSUB213SD: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// VRCP14SD: Compute Approximate Reciprocal of a Scalar Double-Precision Floating-Point Value. // // Forms: // -// VFMSUB213SD xmm xmm xmm -// VFMSUB213SD m64 xmm xmm -// Construct and append a VFMSUB213SD instruction to the active function. +// VRCP14SD m64 xmm k xmm +// VRCP14SD m64 xmm xmm +// VRCP14SD xmm xmm k xmm +// VRCP14SD xmm xmm xmm +// Construct and append a VRCP14SD instruction to the active function. // Operates on the global context. -func VFMSUB213SD(mx, x, x1 operand.Op) { ctx.VFMSUB213SD(mx, x, x1) } +func VRCP14SD(ops ...operand.Op) { ctx.VRCP14SD(ops...) } -// VFMSUB213SS: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// VRCP14SD_Z: Compute Approximate Reciprocal of a Scalar Double-Precision Floating-Point Value (Zeroing Masking). // // Forms: // -// VFMSUB213SS xmm xmm xmm -// VFMSUB213SS m32 xmm xmm -// Construct and append a VFMSUB213SS instruction to the active function. -func (c *Context) VFMSUB213SS(mx, x, x1 operand.Op) { - if inst, err := x86.VFMSUB213SS(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP14SD.Z m64 xmm k xmm +// VRCP14SD.Z xmm xmm k xmm +// Construct and append a VRCP14SD.Z instruction to the active function. +func (c *Context) VRCP14SD_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VRCP14SD_Z(mx, x, k, x1)) } -// VFMSUB213SS: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// VRCP14SD_Z: Compute Approximate Reciprocal of a Scalar Double-Precision Floating-Point Value (Zeroing Masking). // // Forms: // -// VFMSUB213SS xmm xmm xmm -// VFMSUB213SS m32 xmm xmm -// Construct and append a VFMSUB213SS instruction to the active function. +// VRCP14SD.Z m64 xmm k xmm +// VRCP14SD.Z xmm xmm k xmm +// Construct and append a VRCP14SD.Z instruction to the active function. // Operates on the global context. -func VFMSUB213SS(mx, x, x1 operand.Op) { ctx.VFMSUB213SS(mx, x, x1) } +func VRCP14SD_Z(mx, x, k, x1 operand.Op) { ctx.VRCP14SD_Z(mx, x, k, x1) } -// VFMSUB231PD: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// VRCP14SS: Compute Approximate Reciprocal of a Scalar Single-Precision Floating-Point Value. // // Forms: // -// VFMSUB231PD xmm xmm xmm -// VFMSUB231PD m128 xmm xmm -// VFMSUB231PD ymm ymm ymm -// VFMSUB231PD m256 ymm ymm -// Construct and append a VFMSUB231PD instruction to the active function. -func (c *Context) VFMSUB231PD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFMSUB231PD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP14SS m32 xmm k xmm +// VRCP14SS m32 xmm xmm +// VRCP14SS xmm xmm k xmm +// VRCP14SS xmm xmm xmm +// Construct and append a VRCP14SS instruction to the active function. +func (c *Context) VRCP14SS(ops ...operand.Op) { + c.addinstruction(x86.VRCP14SS(ops...)) } -// VFMSUB231PD: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// VRCP14SS: Compute Approximate Reciprocal of a Scalar Single-Precision Floating-Point Value. // // Forms: // -// VFMSUB231PD xmm xmm xmm -// VFMSUB231PD m128 xmm xmm -// VFMSUB231PD ymm ymm ymm -// VFMSUB231PD m256 ymm ymm -// Construct and append a VFMSUB231PD instruction to the active function. +// VRCP14SS m32 xmm k xmm +// VRCP14SS m32 xmm xmm +// VRCP14SS xmm xmm k xmm +// VRCP14SS xmm xmm xmm +// Construct and append a VRCP14SS instruction to the active function. // Operates on the global context. -func VFMSUB231PD(mxy, xy, xy1 operand.Op) { ctx.VFMSUB231PD(mxy, xy, xy1) } +func VRCP14SS(ops ...operand.Op) { ctx.VRCP14SS(ops...) } -// VFMSUB231PS: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// VRCP14SS_Z: Compute Approximate Reciprocal of a Scalar Single-Precision Floating-Point Value (Zeroing Masking). // // Forms: // -// VFMSUB231PS xmm xmm xmm -// VFMSUB231PS m128 xmm xmm -// VFMSUB231PS ymm ymm ymm -// VFMSUB231PS m256 ymm ymm -// Construct and append a VFMSUB231PS instruction to the active function. -func (c *Context) VFMSUB231PS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFMSUB231PS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP14SS.Z m32 xmm k xmm +// VRCP14SS.Z xmm xmm k xmm +// Construct and append a VRCP14SS.Z instruction to the active function. +func (c *Context) VRCP14SS_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VRCP14SS_Z(mx, x, k, x1)) } -// VFMSUB231PS: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// VRCP14SS_Z: Compute Approximate Reciprocal of a Scalar Single-Precision Floating-Point Value (Zeroing Masking). // // Forms: // -// VFMSUB231PS xmm xmm xmm -// VFMSUB231PS m128 xmm xmm -// VFMSUB231PS ymm ymm ymm -// VFMSUB231PS m256 ymm ymm -// Construct and append a VFMSUB231PS instruction to the active function. +// VRCP14SS.Z m32 xmm k xmm +// VRCP14SS.Z xmm xmm k xmm +// Construct and append a VRCP14SS.Z instruction to the active function. // Operates on the global context. -func VFMSUB231PS(mxy, xy, xy1 operand.Op) { ctx.VFMSUB231PS(mxy, xy, xy1) } +func VRCP14SS_Z(mx, x, k, x1 operand.Op) { ctx.VRCP14SS_Z(mx, x, k, x1) } -// VFMSUB231SD: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// VRCP28PD: Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error. // // Forms: // -// VFMSUB231SD xmm xmm xmm -// VFMSUB231SD m64 xmm xmm -// Construct and append a VFMSUB231SD instruction to the active function. -func (c *Context) VFMSUB231SD(mx, x, x1 operand.Op) { - if inst, err := x86.VFMSUB231SD(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP28PD m512 k zmm +// VRCP28PD m512 zmm +// VRCP28PD zmm k zmm +// VRCP28PD zmm zmm +// Construct and append a VRCP28PD instruction to the active function. +func (c *Context) VRCP28PD(ops ...operand.Op) { + c.addinstruction(x86.VRCP28PD(ops...)) } -// VFMSUB231SD: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// VRCP28PD: Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error. // // Forms: // -// VFMSUB231SD xmm xmm xmm -// VFMSUB231SD m64 xmm xmm -// Construct and append a VFMSUB231SD instruction to the active function. +// VRCP28PD m512 k zmm +// VRCP28PD m512 zmm +// VRCP28PD zmm k zmm +// VRCP28PD zmm zmm +// Construct and append a VRCP28PD instruction to the active function. // Operates on the global context. -func VFMSUB231SD(mx, x, x1 operand.Op) { ctx.VFMSUB231SD(mx, x, x1) } +func VRCP28PD(ops ...operand.Op) { ctx.VRCP28PD(ops...) } -// VFMSUB231SS: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// VRCP28PD_BCST: Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Broadcast). // // Forms: // -// VFMSUB231SS xmm xmm xmm -// VFMSUB231SS m32 xmm xmm -// Construct and append a VFMSUB231SS instruction to the active function. -func (c *Context) VFMSUB231SS(mx, x, x1 operand.Op) { - if inst, err := x86.VFMSUB231SS(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP28PD.BCST m64 k zmm +// VRCP28PD.BCST m64 zmm +// Construct and append a VRCP28PD.BCST instruction to the active function. +func (c *Context) VRCP28PD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VRCP28PD_BCST(ops...)) } -// VFMSUB231SS: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// VRCP28PD_BCST: Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Broadcast). // // Forms: // -// VFMSUB231SS xmm xmm xmm -// VFMSUB231SS m32 xmm xmm -// Construct and append a VFMSUB231SS instruction to the active function. +// VRCP28PD.BCST m64 k zmm +// VRCP28PD.BCST m64 zmm +// Construct and append a VRCP28PD.BCST instruction to the active function. // Operates on the global context. -func VFMSUB231SS(mx, x, x1 operand.Op) { ctx.VFMSUB231SS(mx, x, x1) } +func VRCP28PD_BCST(ops ...operand.Op) { ctx.VRCP28PD_BCST(ops...) } -// VFMSUBADD132PD: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values. +// VRCP28PD_BCST_Z: Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Broadcast, Zeroing Masking). // // Forms: // -// VFMSUBADD132PD xmm xmm xmm -// VFMSUBADD132PD m128 xmm xmm -// VFMSUBADD132PD ymm ymm ymm -// VFMSUBADD132PD m256 ymm ymm -// Construct and append a VFMSUBADD132PD instruction to the active function. -func (c *Context) VFMSUBADD132PD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFMSUBADD132PD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP28PD.BCST.Z m64 k zmm +// Construct and append a VRCP28PD.BCST.Z instruction to the active function. +func (c *Context) VRCP28PD_BCST_Z(m, k, z operand.Op) { + c.addinstruction(x86.VRCP28PD_BCST_Z(m, k, z)) } -// VFMSUBADD132PD: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values. +// VRCP28PD_BCST_Z: Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Broadcast, Zeroing Masking). // // Forms: // -// VFMSUBADD132PD xmm xmm xmm -// VFMSUBADD132PD m128 xmm xmm -// VFMSUBADD132PD ymm ymm ymm -// VFMSUBADD132PD m256 ymm ymm -// Construct and append a VFMSUBADD132PD instruction to the active function. +// VRCP28PD.BCST.Z m64 k zmm +// Construct and append a VRCP28PD.BCST.Z instruction to the active function. // Operates on the global context. -func VFMSUBADD132PD(mxy, xy, xy1 operand.Op) { ctx.VFMSUBADD132PD(mxy, xy, xy1) } +func VRCP28PD_BCST_Z(m, k, z operand.Op) { ctx.VRCP28PD_BCST_Z(m, k, z) } -// VFMSUBADD132PS: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values. +// VRCP28PD_SAE: Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Suppress All Exceptions). // // Forms: // -// VFMSUBADD132PS xmm xmm xmm -// VFMSUBADD132PS m128 xmm xmm -// VFMSUBADD132PS ymm ymm ymm -// VFMSUBADD132PS m256 ymm ymm -// Construct and append a VFMSUBADD132PS instruction to the active function. -func (c *Context) VFMSUBADD132PS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFMSUBADD132PS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP28PD.SAE zmm k zmm +// VRCP28PD.SAE zmm zmm +// Construct and append a VRCP28PD.SAE instruction to the active function. +func (c *Context) VRCP28PD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VRCP28PD_SAE(ops...)) } -// VFMSUBADD132PS: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values. +// VRCP28PD_SAE: Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Suppress All Exceptions). // // Forms: // -// VFMSUBADD132PS xmm xmm xmm -// VFMSUBADD132PS m128 xmm xmm -// VFMSUBADD132PS ymm ymm ymm -// VFMSUBADD132PS m256 ymm ymm -// Construct and append a VFMSUBADD132PS instruction to the active function. +// VRCP28PD.SAE zmm k zmm +// VRCP28PD.SAE zmm zmm +// Construct and append a VRCP28PD.SAE instruction to the active function. // Operates on the global context. -func VFMSUBADD132PS(mxy, xy, xy1 operand.Op) { ctx.VFMSUBADD132PS(mxy, xy, xy1) } +func VRCP28PD_SAE(ops ...operand.Op) { ctx.VRCP28PD_SAE(ops...) } -// VFMSUBADD213PD: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values. +// VRCP28PD_SAE_Z: Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VFMSUBADD213PD xmm xmm xmm -// VFMSUBADD213PD m128 xmm xmm -// VFMSUBADD213PD ymm ymm ymm -// VFMSUBADD213PD m256 ymm ymm -// Construct and append a VFMSUBADD213PD instruction to the active function. -func (c *Context) VFMSUBADD213PD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFMSUBADD213PD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP28PD.SAE.Z zmm k zmm +// Construct and append a VRCP28PD.SAE.Z instruction to the active function. +func (c *Context) VRCP28PD_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VRCP28PD_SAE_Z(z, k, z1)) } -// VFMSUBADD213PD: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values. +// VRCP28PD_SAE_Z: Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VFMSUBADD213PD xmm xmm xmm -// VFMSUBADD213PD m128 xmm xmm -// VFMSUBADD213PD ymm ymm ymm -// VFMSUBADD213PD m256 ymm ymm -// Construct and append a VFMSUBADD213PD instruction to the active function. +// VRCP28PD.SAE.Z zmm k zmm +// Construct and append a VRCP28PD.SAE.Z instruction to the active function. // Operates on the global context. -func VFMSUBADD213PD(mxy, xy, xy1 operand.Op) { ctx.VFMSUBADD213PD(mxy, xy, xy1) } +func VRCP28PD_SAE_Z(z, k, z1 operand.Op) { ctx.VRCP28PD_SAE_Z(z, k, z1) } -// VFMSUBADD213PS: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values. +// VRCP28PD_Z: Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Zeroing Masking). // // Forms: // -// VFMSUBADD213PS xmm xmm xmm -// VFMSUBADD213PS m128 xmm xmm -// VFMSUBADD213PS ymm ymm ymm -// VFMSUBADD213PS m256 ymm ymm -// Construct and append a VFMSUBADD213PS instruction to the active function. -func (c *Context) VFMSUBADD213PS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFMSUBADD213PS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP28PD.Z m512 k zmm +// VRCP28PD.Z zmm k zmm +// Construct and append a VRCP28PD.Z instruction to the active function. +func (c *Context) VRCP28PD_Z(mz, k, z operand.Op) { + c.addinstruction(x86.VRCP28PD_Z(mz, k, z)) } -// VFMSUBADD213PS: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values. +// VRCP28PD_Z: Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Zeroing Masking). // // Forms: // -// VFMSUBADD213PS xmm xmm xmm -// VFMSUBADD213PS m128 xmm xmm -// VFMSUBADD213PS ymm ymm ymm -// VFMSUBADD213PS m256 ymm ymm -// Construct and append a VFMSUBADD213PS instruction to the active function. +// VRCP28PD.Z m512 k zmm +// VRCP28PD.Z zmm k zmm +// Construct and append a VRCP28PD.Z instruction to the active function. // Operates on the global context. -func VFMSUBADD213PS(mxy, xy, xy1 operand.Op) { ctx.VFMSUBADD213PS(mxy, xy, xy1) } +func VRCP28PD_Z(mz, k, z operand.Op) { ctx.VRCP28PD_Z(mz, k, z) } -// VFMSUBADD231PD: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values. +// VRCP28PS: Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error. // // Forms: // -// VFMSUBADD231PD xmm xmm xmm -// VFMSUBADD231PD m128 xmm xmm -// VFMSUBADD231PD ymm ymm ymm -// VFMSUBADD231PD m256 ymm ymm -// Construct and append a VFMSUBADD231PD instruction to the active function. -func (c *Context) VFMSUBADD231PD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFMSUBADD231PD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP28PS m512 k zmm +// VRCP28PS m512 zmm +// VRCP28PS zmm k zmm +// VRCP28PS zmm zmm +// Construct and append a VRCP28PS instruction to the active function. +func (c *Context) VRCP28PS(ops ...operand.Op) { + c.addinstruction(x86.VRCP28PS(ops...)) } -// VFMSUBADD231PD: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values. +// VRCP28PS: Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error. // // Forms: // -// VFMSUBADD231PD xmm xmm xmm -// VFMSUBADD231PD m128 xmm xmm -// VFMSUBADD231PD ymm ymm ymm -// VFMSUBADD231PD m256 ymm ymm -// Construct and append a VFMSUBADD231PD instruction to the active function. +// VRCP28PS m512 k zmm +// VRCP28PS m512 zmm +// VRCP28PS zmm k zmm +// VRCP28PS zmm zmm +// Construct and append a VRCP28PS instruction to the active function. // Operates on the global context. -func VFMSUBADD231PD(mxy, xy, xy1 operand.Op) { ctx.VFMSUBADD231PD(mxy, xy, xy1) } +func VRCP28PS(ops ...operand.Op) { ctx.VRCP28PS(ops...) } -// VFMSUBADD231PS: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values. +// VRCP28PS_BCST: Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Broadcast). // // Forms: // -// VFMSUBADD231PS xmm xmm xmm -// VFMSUBADD231PS m128 xmm xmm -// VFMSUBADD231PS ymm ymm ymm -// VFMSUBADD231PS m256 ymm ymm -// Construct and append a VFMSUBADD231PS instruction to the active function. -func (c *Context) VFMSUBADD231PS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFMSUBADD231PS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP28PS.BCST m32 k zmm +// VRCP28PS.BCST m32 zmm +// Construct and append a VRCP28PS.BCST instruction to the active function. +func (c *Context) VRCP28PS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VRCP28PS_BCST(ops...)) } -// VFMSUBADD231PS: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values. +// VRCP28PS_BCST: Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Broadcast). // // Forms: // -// VFMSUBADD231PS xmm xmm xmm -// VFMSUBADD231PS m128 xmm xmm -// VFMSUBADD231PS ymm ymm ymm -// VFMSUBADD231PS m256 ymm ymm -// Construct and append a VFMSUBADD231PS instruction to the active function. +// VRCP28PS.BCST m32 k zmm +// VRCP28PS.BCST m32 zmm +// Construct and append a VRCP28PS.BCST instruction to the active function. // Operates on the global context. -func VFMSUBADD231PS(mxy, xy, xy1 operand.Op) { ctx.VFMSUBADD231PS(mxy, xy, xy1) } +func VRCP28PS_BCST(ops ...operand.Op) { ctx.VRCP28PS_BCST(ops...) } -// VFNMADD132PD: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values. +// VRCP28PS_BCST_Z: Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Broadcast, Zeroing Masking). // // Forms: // -// VFNMADD132PD xmm xmm xmm -// VFNMADD132PD m128 xmm xmm -// VFNMADD132PD ymm ymm ymm -// VFNMADD132PD m256 ymm ymm -// Construct and append a VFNMADD132PD instruction to the active function. -func (c *Context) VFNMADD132PD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFNMADD132PD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP28PS.BCST.Z m32 k zmm +// Construct and append a VRCP28PS.BCST.Z instruction to the active function. +func (c *Context) VRCP28PS_BCST_Z(m, k, z operand.Op) { + c.addinstruction(x86.VRCP28PS_BCST_Z(m, k, z)) } -// VFNMADD132PD: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values. +// VRCP28PS_BCST_Z: Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Broadcast, Zeroing Masking). // // Forms: // -// VFNMADD132PD xmm xmm xmm -// VFNMADD132PD m128 xmm xmm -// VFNMADD132PD ymm ymm ymm -// VFNMADD132PD m256 ymm ymm -// Construct and append a VFNMADD132PD instruction to the active function. +// VRCP28PS.BCST.Z m32 k zmm +// Construct and append a VRCP28PS.BCST.Z instruction to the active function. // Operates on the global context. -func VFNMADD132PD(mxy, xy, xy1 operand.Op) { ctx.VFNMADD132PD(mxy, xy, xy1) } +func VRCP28PS_BCST_Z(m, k, z operand.Op) { ctx.VRCP28PS_BCST_Z(m, k, z) } -// VFNMADD132PS: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values. +// VRCP28PS_SAE: Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Suppress All Exceptions). // // Forms: // -// VFNMADD132PS xmm xmm xmm -// VFNMADD132PS m128 xmm xmm -// VFNMADD132PS ymm ymm ymm -// VFNMADD132PS m256 ymm ymm -// Construct and append a VFNMADD132PS instruction to the active function. -func (c *Context) VFNMADD132PS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFNMADD132PS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP28PS.SAE zmm k zmm +// VRCP28PS.SAE zmm zmm +// Construct and append a VRCP28PS.SAE instruction to the active function. +func (c *Context) VRCP28PS_SAE(ops ...operand.Op) { + c.addinstruction(x86.VRCP28PS_SAE(ops...)) } -// VFNMADD132PS: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values. +// VRCP28PS_SAE: Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Suppress All Exceptions). // // Forms: // -// VFNMADD132PS xmm xmm xmm -// VFNMADD132PS m128 xmm xmm -// VFNMADD132PS ymm ymm ymm -// VFNMADD132PS m256 ymm ymm -// Construct and append a VFNMADD132PS instruction to the active function. +// VRCP28PS.SAE zmm k zmm +// VRCP28PS.SAE zmm zmm +// Construct and append a VRCP28PS.SAE instruction to the active function. // Operates on the global context. -func VFNMADD132PS(mxy, xy, xy1 operand.Op) { ctx.VFNMADD132PS(mxy, xy, xy1) } +func VRCP28PS_SAE(ops ...operand.Op) { ctx.VRCP28PS_SAE(ops...) } -// VFNMADD132SD: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values. +// VRCP28PS_SAE_Z: Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VFNMADD132SD xmm xmm xmm -// VFNMADD132SD m64 xmm xmm -// Construct and append a VFNMADD132SD instruction to the active function. -func (c *Context) VFNMADD132SD(mx, x, x1 operand.Op) { - if inst, err := x86.VFNMADD132SD(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP28PS.SAE.Z zmm k zmm +// Construct and append a VRCP28PS.SAE.Z instruction to the active function. +func (c *Context) VRCP28PS_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VRCP28PS_SAE_Z(z, k, z1)) } -// VFNMADD132SD: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values. +// VRCP28PS_SAE_Z: Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VFNMADD132SD xmm xmm xmm -// VFNMADD132SD m64 xmm xmm -// Construct and append a VFNMADD132SD instruction to the active function. +// VRCP28PS.SAE.Z zmm k zmm +// Construct and append a VRCP28PS.SAE.Z instruction to the active function. // Operates on the global context. -func VFNMADD132SD(mx, x, x1 operand.Op) { ctx.VFNMADD132SD(mx, x, x1) } +func VRCP28PS_SAE_Z(z, k, z1 operand.Op) { ctx.VRCP28PS_SAE_Z(z, k, z1) } -// VFNMADD132SS: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values. +// VRCP28PS_Z: Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Zeroing Masking). // // Forms: // -// VFNMADD132SS xmm xmm xmm -// VFNMADD132SS m32 xmm xmm -// Construct and append a VFNMADD132SS instruction to the active function. -func (c *Context) VFNMADD132SS(mx, x, x1 operand.Op) { - if inst, err := x86.VFNMADD132SS(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP28PS.Z m512 k zmm +// VRCP28PS.Z zmm k zmm +// Construct and append a VRCP28PS.Z instruction to the active function. +func (c *Context) VRCP28PS_Z(mz, k, z operand.Op) { + c.addinstruction(x86.VRCP28PS_Z(mz, k, z)) } -// VFNMADD132SS: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values. +// VRCP28PS_Z: Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Zeroing Masking). // // Forms: // -// VFNMADD132SS xmm xmm xmm -// VFNMADD132SS m32 xmm xmm -// Construct and append a VFNMADD132SS instruction to the active function. +// VRCP28PS.Z m512 k zmm +// VRCP28PS.Z zmm k zmm +// Construct and append a VRCP28PS.Z instruction to the active function. // Operates on the global context. -func VFNMADD132SS(mx, x, x1 operand.Op) { ctx.VFNMADD132SS(mx, x, x1) } +func VRCP28PS_Z(mz, k, z operand.Op) { ctx.VRCP28PS_Z(mz, k, z) } -// VFNMADD213PD: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values. +// VRCP28SD: Approximation to the Reciprocal of a Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error. // // Forms: // -// VFNMADD213PD xmm xmm xmm -// VFNMADD213PD m128 xmm xmm -// VFNMADD213PD ymm ymm ymm -// VFNMADD213PD m256 ymm ymm -// Construct and append a VFNMADD213PD instruction to the active function. -func (c *Context) VFNMADD213PD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFNMADD213PD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP28SD m64 xmm k xmm +// VRCP28SD m64 xmm xmm +// VRCP28SD xmm xmm k xmm +// VRCP28SD xmm xmm xmm +// Construct and append a VRCP28SD instruction to the active function. +func (c *Context) VRCP28SD(ops ...operand.Op) { + c.addinstruction(x86.VRCP28SD(ops...)) } -// VFNMADD213PD: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values. +// VRCP28SD: Approximation to the Reciprocal of a Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error. // // Forms: // -// VFNMADD213PD xmm xmm xmm -// VFNMADD213PD m128 xmm xmm -// VFNMADD213PD ymm ymm ymm -// VFNMADD213PD m256 ymm ymm -// Construct and append a VFNMADD213PD instruction to the active function. +// VRCP28SD m64 xmm k xmm +// VRCP28SD m64 xmm xmm +// VRCP28SD xmm xmm k xmm +// VRCP28SD xmm xmm xmm +// Construct and append a VRCP28SD instruction to the active function. // Operates on the global context. -func VFNMADD213PD(mxy, xy, xy1 operand.Op) { ctx.VFNMADD213PD(mxy, xy, xy1) } +func VRCP28SD(ops ...operand.Op) { ctx.VRCP28SD(ops...) } -// VFNMADD213PS: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values. +// VRCP28SD_SAE: Approximation to the Reciprocal of a Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Suppress All Exceptions). // // Forms: // -// VFNMADD213PS xmm xmm xmm -// VFNMADD213PS m128 xmm xmm -// VFNMADD213PS ymm ymm ymm -// VFNMADD213PS m256 ymm ymm -// Construct and append a VFNMADD213PS instruction to the active function. -func (c *Context) VFNMADD213PS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFNMADD213PS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP28SD.SAE xmm xmm k xmm +// VRCP28SD.SAE xmm xmm xmm +// Construct and append a VRCP28SD.SAE instruction to the active function. +func (c *Context) VRCP28SD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VRCP28SD_SAE(ops...)) } -// VFNMADD213PS: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values. +// VRCP28SD_SAE: Approximation to the Reciprocal of a Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Suppress All Exceptions). // // Forms: // -// VFNMADD213PS xmm xmm xmm -// VFNMADD213PS m128 xmm xmm -// VFNMADD213PS ymm ymm ymm -// VFNMADD213PS m256 ymm ymm -// Construct and append a VFNMADD213PS instruction to the active function. +// VRCP28SD.SAE xmm xmm k xmm +// VRCP28SD.SAE xmm xmm xmm +// Construct and append a VRCP28SD.SAE instruction to the active function. // Operates on the global context. -func VFNMADD213PS(mxy, xy, xy1 operand.Op) { ctx.VFNMADD213PS(mxy, xy, xy1) } +func VRCP28SD_SAE(ops ...operand.Op) { ctx.VRCP28SD_SAE(ops...) } -// VFNMADD213SD: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values. +// VRCP28SD_SAE_Z: Approximation to the Reciprocal of a Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VFNMADD213SD xmm xmm xmm -// VFNMADD213SD m64 xmm xmm -// Construct and append a VFNMADD213SD instruction to the active function. -func (c *Context) VFNMADD213SD(mx, x, x1 operand.Op) { - if inst, err := x86.VFNMADD213SD(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP28SD.SAE.Z xmm xmm k xmm +// Construct and append a VRCP28SD.SAE.Z instruction to the active function. +func (c *Context) VRCP28SD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VRCP28SD_SAE_Z(x, x1, k, x2)) } -// VFNMADD213SD: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values. +// VRCP28SD_SAE_Z: Approximation to the Reciprocal of a Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VFNMADD213SD xmm xmm xmm -// VFNMADD213SD m64 xmm xmm -// Construct and append a VFNMADD213SD instruction to the active function. +// VRCP28SD.SAE.Z xmm xmm k xmm +// Construct and append a VRCP28SD.SAE.Z instruction to the active function. // Operates on the global context. -func VFNMADD213SD(mx, x, x1 operand.Op) { ctx.VFNMADD213SD(mx, x, x1) } +func VRCP28SD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VRCP28SD_SAE_Z(x, x1, k, x2) } -// VFNMADD213SS: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values. +// VRCP28SD_Z: Approximation to the Reciprocal of a Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Zeroing Masking). // // Forms: // -// VFNMADD213SS xmm xmm xmm -// VFNMADD213SS m32 xmm xmm -// Construct and append a VFNMADD213SS instruction to the active function. -func (c *Context) VFNMADD213SS(mx, x, x1 operand.Op) { - if inst, err := x86.VFNMADD213SS(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP28SD.Z m64 xmm k xmm +// VRCP28SD.Z xmm xmm k xmm +// Construct and append a VRCP28SD.Z instruction to the active function. +func (c *Context) VRCP28SD_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VRCP28SD_Z(mx, x, k, x1)) } -// VFNMADD213SS: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values. +// VRCP28SD_Z: Approximation to the Reciprocal of a Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Zeroing Masking). // // Forms: // -// VFNMADD213SS xmm xmm xmm -// VFNMADD213SS m32 xmm xmm -// Construct and append a VFNMADD213SS instruction to the active function. +// VRCP28SD.Z m64 xmm k xmm +// VRCP28SD.Z xmm xmm k xmm +// Construct and append a VRCP28SD.Z instruction to the active function. // Operates on the global context. -func VFNMADD213SS(mx, x, x1 operand.Op) { ctx.VFNMADD213SS(mx, x, x1) } +func VRCP28SD_Z(mx, x, k, x1 operand.Op) { ctx.VRCP28SD_Z(mx, x, k, x1) } -// VFNMADD231PD: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values. +// VRCP28SS: Approximation to the Reciprocal of a Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error. // // Forms: // -// VFNMADD231PD xmm xmm xmm -// VFNMADD231PD m128 xmm xmm -// VFNMADD231PD ymm ymm ymm -// VFNMADD231PD m256 ymm ymm -// Construct and append a VFNMADD231PD instruction to the active function. -func (c *Context) VFNMADD231PD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFNMADD231PD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP28SS m32 xmm k xmm +// VRCP28SS m32 xmm xmm +// VRCP28SS xmm xmm k xmm +// VRCP28SS xmm xmm xmm +// Construct and append a VRCP28SS instruction to the active function. +func (c *Context) VRCP28SS(ops ...operand.Op) { + c.addinstruction(x86.VRCP28SS(ops...)) } -// VFNMADD231PD: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values. +// VRCP28SS: Approximation to the Reciprocal of a Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error. // // Forms: // -// VFNMADD231PD xmm xmm xmm -// VFNMADD231PD m128 xmm xmm -// VFNMADD231PD ymm ymm ymm -// VFNMADD231PD m256 ymm ymm -// Construct and append a VFNMADD231PD instruction to the active function. +// VRCP28SS m32 xmm k xmm +// VRCP28SS m32 xmm xmm +// VRCP28SS xmm xmm k xmm +// VRCP28SS xmm xmm xmm +// Construct and append a VRCP28SS instruction to the active function. // Operates on the global context. -func VFNMADD231PD(mxy, xy, xy1 operand.Op) { ctx.VFNMADD231PD(mxy, xy, xy1) } +func VRCP28SS(ops ...operand.Op) { ctx.VRCP28SS(ops...) } -// VFNMADD231PS: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values. +// VRCP28SS_SAE: Approximation to the Reciprocal of a Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Suppress All Exceptions). // // Forms: // -// VFNMADD231PS xmm xmm xmm -// VFNMADD231PS m128 xmm xmm -// VFNMADD231PS ymm ymm ymm -// VFNMADD231PS m256 ymm ymm -// Construct and append a VFNMADD231PS instruction to the active function. -func (c *Context) VFNMADD231PS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFNMADD231PS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP28SS.SAE xmm xmm k xmm +// VRCP28SS.SAE xmm xmm xmm +// Construct and append a VRCP28SS.SAE instruction to the active function. +func (c *Context) VRCP28SS_SAE(ops ...operand.Op) { + c.addinstruction(x86.VRCP28SS_SAE(ops...)) } -// VFNMADD231PS: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values. +// VRCP28SS_SAE: Approximation to the Reciprocal of a Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Suppress All Exceptions). // // Forms: // -// VFNMADD231PS xmm xmm xmm -// VFNMADD231PS m128 xmm xmm -// VFNMADD231PS ymm ymm ymm -// VFNMADD231PS m256 ymm ymm -// Construct and append a VFNMADD231PS instruction to the active function. +// VRCP28SS.SAE xmm xmm k xmm +// VRCP28SS.SAE xmm xmm xmm +// Construct and append a VRCP28SS.SAE instruction to the active function. // Operates on the global context. -func VFNMADD231PS(mxy, xy, xy1 operand.Op) { ctx.VFNMADD231PS(mxy, xy, xy1) } +func VRCP28SS_SAE(ops ...operand.Op) { ctx.VRCP28SS_SAE(ops...) } -// VFNMADD231SD: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values. +// VRCP28SS_SAE_Z: Approximation to the Reciprocal of a Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VFNMADD231SD xmm xmm xmm -// VFNMADD231SD m64 xmm xmm -// Construct and append a VFNMADD231SD instruction to the active function. -func (c *Context) VFNMADD231SD(mx, x, x1 operand.Op) { - if inst, err := x86.VFNMADD231SD(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP28SS.SAE.Z xmm xmm k xmm +// Construct and append a VRCP28SS.SAE.Z instruction to the active function. +func (c *Context) VRCP28SS_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VRCP28SS_SAE_Z(x, x1, k, x2)) } -// VFNMADD231SD: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values. +// VRCP28SS_SAE_Z: Approximation to the Reciprocal of a Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VFNMADD231SD xmm xmm xmm -// VFNMADD231SD m64 xmm xmm -// Construct and append a VFNMADD231SD instruction to the active function. +// VRCP28SS.SAE.Z xmm xmm k xmm +// Construct and append a VRCP28SS.SAE.Z instruction to the active function. // Operates on the global context. -func VFNMADD231SD(mx, x, x1 operand.Op) { ctx.VFNMADD231SD(mx, x, x1) } +func VRCP28SS_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VRCP28SS_SAE_Z(x, x1, k, x2) } -// VFNMADD231SS: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values. +// VRCP28SS_Z: Approximation to the Reciprocal of a Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Zeroing Masking). // // Forms: // -// VFNMADD231SS xmm xmm xmm -// VFNMADD231SS m32 xmm xmm -// Construct and append a VFNMADD231SS instruction to the active function. -func (c *Context) VFNMADD231SS(mx, x, x1 operand.Op) { - if inst, err := x86.VFNMADD231SS(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCP28SS.Z m32 xmm k xmm +// VRCP28SS.Z xmm xmm k xmm +// Construct and append a VRCP28SS.Z instruction to the active function. +func (c *Context) VRCP28SS_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VRCP28SS_Z(mx, x, k, x1)) } -// VFNMADD231SS: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values. +// VRCP28SS_Z: Approximation to the Reciprocal of a Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Zeroing Masking). // // Forms: // -// VFNMADD231SS xmm xmm xmm -// VFNMADD231SS m32 xmm xmm -// Construct and append a VFNMADD231SS instruction to the active function. +// VRCP28SS.Z m32 xmm k xmm +// VRCP28SS.Z xmm xmm k xmm +// Construct and append a VRCP28SS.Z instruction to the active function. // Operates on the global context. -func VFNMADD231SS(mx, x, x1 operand.Op) { ctx.VFNMADD231SS(mx, x, x1) } +func VRCP28SS_Z(mx, x, k, x1 operand.Op) { ctx.VRCP28SS_Z(mx, x, k, x1) } -// VFNMSUB132PD: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// VRCPPS: Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values. // // Forms: // -// VFNMSUB132PD xmm xmm xmm -// VFNMSUB132PD m128 xmm xmm -// VFNMSUB132PD ymm ymm ymm -// VFNMSUB132PD m256 ymm ymm -// Construct and append a VFNMSUB132PD instruction to the active function. -func (c *Context) VFNMSUB132PD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFNMSUB132PD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCPPS m128 xmm +// VRCPPS m256 ymm +// VRCPPS xmm xmm +// VRCPPS ymm ymm +// Construct and append a VRCPPS instruction to the active function. +func (c *Context) VRCPPS(mxy, xy operand.Op) { + c.addinstruction(x86.VRCPPS(mxy, xy)) } -// VFNMSUB132PD: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// VRCPPS: Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values. // // Forms: // -// VFNMSUB132PD xmm xmm xmm -// VFNMSUB132PD m128 xmm xmm -// VFNMSUB132PD ymm ymm ymm -// VFNMSUB132PD m256 ymm ymm -// Construct and append a VFNMSUB132PD instruction to the active function. +// VRCPPS m128 xmm +// VRCPPS m256 ymm +// VRCPPS xmm xmm +// VRCPPS ymm ymm +// Construct and append a VRCPPS instruction to the active function. // Operates on the global context. -func VFNMSUB132PD(mxy, xy, xy1 operand.Op) { ctx.VFNMSUB132PD(mxy, xy, xy1) } +func VRCPPS(mxy, xy operand.Op) { ctx.VRCPPS(mxy, xy) } -// VFNMSUB132PS: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// VRCPSS: Compute Approximate Reciprocal of Scalar Single-Precision Floating-Point Values. // // Forms: // -// VFNMSUB132PS xmm xmm xmm -// VFNMSUB132PS m128 xmm xmm -// VFNMSUB132PS ymm ymm ymm -// VFNMSUB132PS m256 ymm ymm -// Construct and append a VFNMSUB132PS instruction to the active function. -func (c *Context) VFNMSUB132PS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFNMSUB132PS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRCPSS m32 xmm xmm +// VRCPSS xmm xmm xmm +// Construct and append a VRCPSS instruction to the active function. +func (c *Context) VRCPSS(mx, x, x1 operand.Op) { + c.addinstruction(x86.VRCPSS(mx, x, x1)) } -// VFNMSUB132PS: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// VRCPSS: Compute Approximate Reciprocal of Scalar Single-Precision Floating-Point Values. // // Forms: // -// VFNMSUB132PS xmm xmm xmm -// VFNMSUB132PS m128 xmm xmm -// VFNMSUB132PS ymm ymm ymm -// VFNMSUB132PS m256 ymm ymm -// Construct and append a VFNMSUB132PS instruction to the active function. +// VRCPSS m32 xmm xmm +// VRCPSS xmm xmm xmm +// Construct and append a VRCPSS instruction to the active function. // Operates on the global context. -func VFNMSUB132PS(mxy, xy, xy1 operand.Op) { ctx.VFNMSUB132PS(mxy, xy, xy1) } +func VRCPSS(mx, x, x1 operand.Op) { ctx.VRCPSS(mx, x, x1) } -// VFNMSUB132SD: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// VREDUCEPD: Perform Reduction Transformation on Packed Double-Precision Floating-Point Values. // // Forms: // -// VFNMSUB132SD xmm xmm xmm -// VFNMSUB132SD m64 xmm xmm -// Construct and append a VFNMSUB132SD instruction to the active function. -func (c *Context) VFNMSUB132SD(mx, x, x1 operand.Op) { - if inst, err := x86.VFNMSUB132SD(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VREDUCEPD imm8 m128 k xmm +// VREDUCEPD imm8 m128 xmm +// VREDUCEPD imm8 m256 k ymm +// VREDUCEPD imm8 m256 ymm +// VREDUCEPD imm8 xmm k xmm +// VREDUCEPD imm8 xmm xmm +// VREDUCEPD imm8 ymm k ymm +// VREDUCEPD imm8 ymm ymm +// VREDUCEPD imm8 m512 k zmm +// VREDUCEPD imm8 m512 zmm +// VREDUCEPD imm8 zmm k zmm +// VREDUCEPD imm8 zmm zmm +// Construct and append a VREDUCEPD instruction to the active function. +func (c *Context) VREDUCEPD(ops ...operand.Op) { + c.addinstruction(x86.VREDUCEPD(ops...)) } -// VFNMSUB132SD: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// VREDUCEPD: Perform Reduction Transformation on Packed Double-Precision Floating-Point Values. // // Forms: // -// VFNMSUB132SD xmm xmm xmm -// VFNMSUB132SD m64 xmm xmm -// Construct and append a VFNMSUB132SD instruction to the active function. +// VREDUCEPD imm8 m128 k xmm +// VREDUCEPD imm8 m128 xmm +// VREDUCEPD imm8 m256 k ymm +// VREDUCEPD imm8 m256 ymm +// VREDUCEPD imm8 xmm k xmm +// VREDUCEPD imm8 xmm xmm +// VREDUCEPD imm8 ymm k ymm +// VREDUCEPD imm8 ymm ymm +// VREDUCEPD imm8 m512 k zmm +// VREDUCEPD imm8 m512 zmm +// VREDUCEPD imm8 zmm k zmm +// VREDUCEPD imm8 zmm zmm +// Construct and append a VREDUCEPD instruction to the active function. // Operates on the global context. -func VFNMSUB132SD(mx, x, x1 operand.Op) { ctx.VFNMSUB132SD(mx, x, x1) } +func VREDUCEPD(ops ...operand.Op) { ctx.VREDUCEPD(ops...) } -// VFNMSUB132SS: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// VREDUCEPD_BCST: Perform Reduction Transformation on Packed Double-Precision Floating-Point Values (Broadcast). // // Forms: // -// VFNMSUB132SS xmm xmm xmm -// VFNMSUB132SS m32 xmm xmm -// Construct and append a VFNMSUB132SS instruction to the active function. -func (c *Context) VFNMSUB132SS(mx, x, x1 operand.Op) { - if inst, err := x86.VFNMSUB132SS(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VREDUCEPD.BCST imm8 m64 k xmm +// VREDUCEPD.BCST imm8 m64 k ymm +// VREDUCEPD.BCST imm8 m64 xmm +// VREDUCEPD.BCST imm8 m64 ymm +// VREDUCEPD.BCST imm8 m64 k zmm +// VREDUCEPD.BCST imm8 m64 zmm +// Construct and append a VREDUCEPD.BCST instruction to the active function. +func (c *Context) VREDUCEPD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VREDUCEPD_BCST(ops...)) } -// VFNMSUB132SS: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// VREDUCEPD_BCST: Perform Reduction Transformation on Packed Double-Precision Floating-Point Values (Broadcast). // // Forms: // -// VFNMSUB132SS xmm xmm xmm -// VFNMSUB132SS m32 xmm xmm -// Construct and append a VFNMSUB132SS instruction to the active function. +// VREDUCEPD.BCST imm8 m64 k xmm +// VREDUCEPD.BCST imm8 m64 k ymm +// VREDUCEPD.BCST imm8 m64 xmm +// VREDUCEPD.BCST imm8 m64 ymm +// VREDUCEPD.BCST imm8 m64 k zmm +// VREDUCEPD.BCST imm8 m64 zmm +// Construct and append a VREDUCEPD.BCST instruction to the active function. // Operates on the global context. -func VFNMSUB132SS(mx, x, x1 operand.Op) { ctx.VFNMSUB132SS(mx, x, x1) } +func VREDUCEPD_BCST(ops ...operand.Op) { ctx.VREDUCEPD_BCST(ops...) } -// VFNMSUB213PD: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// VREDUCEPD_BCST_Z: Perform Reduction Transformation on Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VFNMSUB213PD xmm xmm xmm -// VFNMSUB213PD m128 xmm xmm -// VFNMSUB213PD ymm ymm ymm -// VFNMSUB213PD m256 ymm ymm -// Construct and append a VFNMSUB213PD instruction to the active function. -func (c *Context) VFNMSUB213PD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFNMSUB213PD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VREDUCEPD.BCST.Z imm8 m64 k xmm +// VREDUCEPD.BCST.Z imm8 m64 k ymm +// VREDUCEPD.BCST.Z imm8 m64 k zmm +// Construct and append a VREDUCEPD.BCST.Z instruction to the active function. +func (c *Context) VREDUCEPD_BCST_Z(i, m, k, xyz operand.Op) { + c.addinstruction(x86.VREDUCEPD_BCST_Z(i, m, k, xyz)) } -// VFNMSUB213PD: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// VREDUCEPD_BCST_Z: Perform Reduction Transformation on Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VFNMSUB213PD xmm xmm xmm -// VFNMSUB213PD m128 xmm xmm -// VFNMSUB213PD ymm ymm ymm -// VFNMSUB213PD m256 ymm ymm -// Construct and append a VFNMSUB213PD instruction to the active function. +// VREDUCEPD.BCST.Z imm8 m64 k xmm +// VREDUCEPD.BCST.Z imm8 m64 k ymm +// VREDUCEPD.BCST.Z imm8 m64 k zmm +// Construct and append a VREDUCEPD.BCST.Z instruction to the active function. // Operates on the global context. -func VFNMSUB213PD(mxy, xy, xy1 operand.Op) { ctx.VFNMSUB213PD(mxy, xy, xy1) } +func VREDUCEPD_BCST_Z(i, m, k, xyz operand.Op) { ctx.VREDUCEPD_BCST_Z(i, m, k, xyz) } -// VFNMSUB213PS: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// VREDUCEPD_Z: Perform Reduction Transformation on Packed Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VFNMSUB213PS xmm xmm xmm -// VFNMSUB213PS m128 xmm xmm -// VFNMSUB213PS ymm ymm ymm -// VFNMSUB213PS m256 ymm ymm -// Construct and append a VFNMSUB213PS instruction to the active function. -func (c *Context) VFNMSUB213PS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFNMSUB213PS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VREDUCEPD.Z imm8 m128 k xmm +// VREDUCEPD.Z imm8 m256 k ymm +// VREDUCEPD.Z imm8 xmm k xmm +// VREDUCEPD.Z imm8 ymm k ymm +// VREDUCEPD.Z imm8 m512 k zmm +// VREDUCEPD.Z imm8 zmm k zmm +// Construct and append a VREDUCEPD.Z instruction to the active function. +func (c *Context) VREDUCEPD_Z(i, mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VREDUCEPD_Z(i, mxyz, k, xyz)) } -// VFNMSUB213PS: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// VREDUCEPD_Z: Perform Reduction Transformation on Packed Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VFNMSUB213PS xmm xmm xmm -// VFNMSUB213PS m128 xmm xmm -// VFNMSUB213PS ymm ymm ymm -// VFNMSUB213PS m256 ymm ymm -// Construct and append a VFNMSUB213PS instruction to the active function. +// VREDUCEPD.Z imm8 m128 k xmm +// VREDUCEPD.Z imm8 m256 k ymm +// VREDUCEPD.Z imm8 xmm k xmm +// VREDUCEPD.Z imm8 ymm k ymm +// VREDUCEPD.Z imm8 m512 k zmm +// VREDUCEPD.Z imm8 zmm k zmm +// Construct and append a VREDUCEPD.Z instruction to the active function. // Operates on the global context. -func VFNMSUB213PS(mxy, xy, xy1 operand.Op) { ctx.VFNMSUB213PS(mxy, xy, xy1) } +func VREDUCEPD_Z(i, mxyz, k, xyz operand.Op) { ctx.VREDUCEPD_Z(i, mxyz, k, xyz) } -// VFNMSUB213SD: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// VREDUCEPS: Perform Reduction Transformation on Packed Single-Precision Floating-Point Values. // // Forms: // -// VFNMSUB213SD xmm xmm xmm -// VFNMSUB213SD m64 xmm xmm -// Construct and append a VFNMSUB213SD instruction to the active function. -func (c *Context) VFNMSUB213SD(mx, x, x1 operand.Op) { - if inst, err := x86.VFNMSUB213SD(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VREDUCEPS imm8 m128 k xmm +// VREDUCEPS imm8 m128 xmm +// VREDUCEPS imm8 m256 k ymm +// VREDUCEPS imm8 m256 ymm +// VREDUCEPS imm8 xmm k xmm +// VREDUCEPS imm8 xmm xmm +// VREDUCEPS imm8 ymm k ymm +// VREDUCEPS imm8 ymm ymm +// VREDUCEPS imm8 m512 k zmm +// VREDUCEPS imm8 m512 zmm +// VREDUCEPS imm8 zmm k zmm +// VREDUCEPS imm8 zmm zmm +// Construct and append a VREDUCEPS instruction to the active function. +func (c *Context) VREDUCEPS(ops ...operand.Op) { + c.addinstruction(x86.VREDUCEPS(ops...)) } -// VFNMSUB213SD: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// VREDUCEPS: Perform Reduction Transformation on Packed Single-Precision Floating-Point Values. // // Forms: // -// VFNMSUB213SD xmm xmm xmm -// VFNMSUB213SD m64 xmm xmm -// Construct and append a VFNMSUB213SD instruction to the active function. +// VREDUCEPS imm8 m128 k xmm +// VREDUCEPS imm8 m128 xmm +// VREDUCEPS imm8 m256 k ymm +// VREDUCEPS imm8 m256 ymm +// VREDUCEPS imm8 xmm k xmm +// VREDUCEPS imm8 xmm xmm +// VREDUCEPS imm8 ymm k ymm +// VREDUCEPS imm8 ymm ymm +// VREDUCEPS imm8 m512 k zmm +// VREDUCEPS imm8 m512 zmm +// VREDUCEPS imm8 zmm k zmm +// VREDUCEPS imm8 zmm zmm +// Construct and append a VREDUCEPS instruction to the active function. // Operates on the global context. -func VFNMSUB213SD(mx, x, x1 operand.Op) { ctx.VFNMSUB213SD(mx, x, x1) } +func VREDUCEPS(ops ...operand.Op) { ctx.VREDUCEPS(ops...) } -// VFNMSUB213SS: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// VREDUCEPS_BCST: Perform Reduction Transformation on Packed Single-Precision Floating-Point Values (Broadcast). // // Forms: // -// VFNMSUB213SS xmm xmm xmm -// VFNMSUB213SS m32 xmm xmm -// Construct and append a VFNMSUB213SS instruction to the active function. -func (c *Context) VFNMSUB213SS(mx, x, x1 operand.Op) { - if inst, err := x86.VFNMSUB213SS(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VREDUCEPS.BCST imm8 m32 k xmm +// VREDUCEPS.BCST imm8 m32 k ymm +// VREDUCEPS.BCST imm8 m32 xmm +// VREDUCEPS.BCST imm8 m32 ymm +// VREDUCEPS.BCST imm8 m32 k zmm +// VREDUCEPS.BCST imm8 m32 zmm +// Construct and append a VREDUCEPS.BCST instruction to the active function. +func (c *Context) VREDUCEPS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VREDUCEPS_BCST(ops...)) } -// VFNMSUB213SS: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// VREDUCEPS_BCST: Perform Reduction Transformation on Packed Single-Precision Floating-Point Values (Broadcast). // // Forms: // -// VFNMSUB213SS xmm xmm xmm -// VFNMSUB213SS m32 xmm xmm -// Construct and append a VFNMSUB213SS instruction to the active function. +// VREDUCEPS.BCST imm8 m32 k xmm +// VREDUCEPS.BCST imm8 m32 k ymm +// VREDUCEPS.BCST imm8 m32 xmm +// VREDUCEPS.BCST imm8 m32 ymm +// VREDUCEPS.BCST imm8 m32 k zmm +// VREDUCEPS.BCST imm8 m32 zmm +// Construct and append a VREDUCEPS.BCST instruction to the active function. // Operates on the global context. -func VFNMSUB213SS(mx, x, x1 operand.Op) { ctx.VFNMSUB213SS(mx, x, x1) } +func VREDUCEPS_BCST(ops ...operand.Op) { ctx.VREDUCEPS_BCST(ops...) } -// VFNMSUB231PD: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// VREDUCEPS_BCST_Z: Perform Reduction Transformation on Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VFNMSUB231PD xmm xmm xmm -// VFNMSUB231PD m128 xmm xmm -// VFNMSUB231PD ymm ymm ymm -// VFNMSUB231PD m256 ymm ymm -// Construct and append a VFNMSUB231PD instruction to the active function. -func (c *Context) VFNMSUB231PD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFNMSUB231PD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VREDUCEPS.BCST.Z imm8 m32 k xmm +// VREDUCEPS.BCST.Z imm8 m32 k ymm +// VREDUCEPS.BCST.Z imm8 m32 k zmm +// Construct and append a VREDUCEPS.BCST.Z instruction to the active function. +func (c *Context) VREDUCEPS_BCST_Z(i, m, k, xyz operand.Op) { + c.addinstruction(x86.VREDUCEPS_BCST_Z(i, m, k, xyz)) } -// VFNMSUB231PD: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// VREDUCEPS_BCST_Z: Perform Reduction Transformation on Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VFNMSUB231PD xmm xmm xmm -// VFNMSUB231PD m128 xmm xmm -// VFNMSUB231PD ymm ymm ymm -// VFNMSUB231PD m256 ymm ymm -// Construct and append a VFNMSUB231PD instruction to the active function. +// VREDUCEPS.BCST.Z imm8 m32 k xmm +// VREDUCEPS.BCST.Z imm8 m32 k ymm +// VREDUCEPS.BCST.Z imm8 m32 k zmm +// Construct and append a VREDUCEPS.BCST.Z instruction to the active function. // Operates on the global context. -func VFNMSUB231PD(mxy, xy, xy1 operand.Op) { ctx.VFNMSUB231PD(mxy, xy, xy1) } +func VREDUCEPS_BCST_Z(i, m, k, xyz operand.Op) { ctx.VREDUCEPS_BCST_Z(i, m, k, xyz) } -// VFNMSUB231PS: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// VREDUCEPS_Z: Perform Reduction Transformation on Packed Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VFNMSUB231PS xmm xmm xmm -// VFNMSUB231PS m128 xmm xmm -// VFNMSUB231PS ymm ymm ymm -// VFNMSUB231PS m256 ymm ymm -// Construct and append a VFNMSUB231PS instruction to the active function. -func (c *Context) VFNMSUB231PS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VFNMSUB231PS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VREDUCEPS.Z imm8 m128 k xmm +// VREDUCEPS.Z imm8 m256 k ymm +// VREDUCEPS.Z imm8 xmm k xmm +// VREDUCEPS.Z imm8 ymm k ymm +// VREDUCEPS.Z imm8 m512 k zmm +// VREDUCEPS.Z imm8 zmm k zmm +// Construct and append a VREDUCEPS.Z instruction to the active function. +func (c *Context) VREDUCEPS_Z(i, mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VREDUCEPS_Z(i, mxyz, k, xyz)) } -// VFNMSUB231PS: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// VREDUCEPS_Z: Perform Reduction Transformation on Packed Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VFNMSUB231PS xmm xmm xmm -// VFNMSUB231PS m128 xmm xmm -// VFNMSUB231PS ymm ymm ymm -// VFNMSUB231PS m256 ymm ymm -// Construct and append a VFNMSUB231PS instruction to the active function. +// VREDUCEPS.Z imm8 m128 k xmm +// VREDUCEPS.Z imm8 m256 k ymm +// VREDUCEPS.Z imm8 xmm k xmm +// VREDUCEPS.Z imm8 ymm k ymm +// VREDUCEPS.Z imm8 m512 k zmm +// VREDUCEPS.Z imm8 zmm k zmm +// Construct and append a VREDUCEPS.Z instruction to the active function. // Operates on the global context. -func VFNMSUB231PS(mxy, xy, xy1 operand.Op) { ctx.VFNMSUB231PS(mxy, xy, xy1) } +func VREDUCEPS_Z(i, mxyz, k, xyz operand.Op) { ctx.VREDUCEPS_Z(i, mxyz, k, xyz) } -// VFNMSUB231SD: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// VREDUCESD: Perform Reduction Transformation on a Scalar Double-Precision Floating-Point Value. // // Forms: // -// VFNMSUB231SD xmm xmm xmm -// VFNMSUB231SD m64 xmm xmm -// Construct and append a VFNMSUB231SD instruction to the active function. -func (c *Context) VFNMSUB231SD(mx, x, x1 operand.Op) { - if inst, err := x86.VFNMSUB231SD(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VREDUCESD imm8 m64 xmm k xmm +// VREDUCESD imm8 m64 xmm xmm +// VREDUCESD imm8 xmm xmm k xmm +// VREDUCESD imm8 xmm xmm xmm +// Construct and append a VREDUCESD instruction to the active function. +func (c *Context) VREDUCESD(ops ...operand.Op) { + c.addinstruction(x86.VREDUCESD(ops...)) } -// VFNMSUB231SD: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// VREDUCESD: Perform Reduction Transformation on a Scalar Double-Precision Floating-Point Value. // // Forms: // -// VFNMSUB231SD xmm xmm xmm -// VFNMSUB231SD m64 xmm xmm -// Construct and append a VFNMSUB231SD instruction to the active function. +// VREDUCESD imm8 m64 xmm k xmm +// VREDUCESD imm8 m64 xmm xmm +// VREDUCESD imm8 xmm xmm k xmm +// VREDUCESD imm8 xmm xmm xmm +// Construct and append a VREDUCESD instruction to the active function. // Operates on the global context. -func VFNMSUB231SD(mx, x, x1 operand.Op) { ctx.VFNMSUB231SD(mx, x, x1) } +func VREDUCESD(ops ...operand.Op) { ctx.VREDUCESD(ops...) } -// VFNMSUB231SS: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// VREDUCESD_Z: Perform Reduction Transformation on a Scalar Double-Precision Floating-Point Value (Zeroing Masking). // // Forms: // -// VFNMSUB231SS xmm xmm xmm -// VFNMSUB231SS m32 xmm xmm -// Construct and append a VFNMSUB231SS instruction to the active function. -func (c *Context) VFNMSUB231SS(mx, x, x1 operand.Op) { - if inst, err := x86.VFNMSUB231SS(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VREDUCESD.Z imm8 m64 xmm k xmm +// VREDUCESD.Z imm8 xmm xmm k xmm +// Construct and append a VREDUCESD.Z instruction to the active function. +func (c *Context) VREDUCESD_Z(i, mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VREDUCESD_Z(i, mx, x, k, x1)) } -// VFNMSUB231SS: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// VREDUCESD_Z: Perform Reduction Transformation on a Scalar Double-Precision Floating-Point Value (Zeroing Masking). // // Forms: // -// VFNMSUB231SS xmm xmm xmm -// VFNMSUB231SS m32 xmm xmm -// Construct and append a VFNMSUB231SS instruction to the active function. +// VREDUCESD.Z imm8 m64 xmm k xmm +// VREDUCESD.Z imm8 xmm xmm k xmm +// Construct and append a VREDUCESD.Z instruction to the active function. // Operates on the global context. -func VFNMSUB231SS(mx, x, x1 operand.Op) { ctx.VFNMSUB231SS(mx, x, x1) } +func VREDUCESD_Z(i, mx, x, k, x1 operand.Op) { ctx.VREDUCESD_Z(i, mx, x, k, x1) } -// VGATHERDPD: Gather Packed Double-Precision Floating-Point Values Using Signed Doubleword Indices. +// VREDUCESS: Perform Reduction Transformation on a Scalar Single-Precision Floating-Point Value. // // Forms: // -// VGATHERDPD xmm vm32x xmm -// VGATHERDPD ymm vm32x ymm -// Construct and append a VGATHERDPD instruction to the active function. -func (c *Context) VGATHERDPD(xy, v, xy1 operand.Op) { - if inst, err := x86.VGATHERDPD(xy, v, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VREDUCESS imm8 m32 xmm k xmm +// VREDUCESS imm8 m32 xmm xmm +// VREDUCESS imm8 xmm xmm k xmm +// VREDUCESS imm8 xmm xmm xmm +// Construct and append a VREDUCESS instruction to the active function. +func (c *Context) VREDUCESS(ops ...operand.Op) { + c.addinstruction(x86.VREDUCESS(ops...)) } -// VGATHERDPD: Gather Packed Double-Precision Floating-Point Values Using Signed Doubleword Indices. +// VREDUCESS: Perform Reduction Transformation on a Scalar Single-Precision Floating-Point Value. // // Forms: // -// VGATHERDPD xmm vm32x xmm -// VGATHERDPD ymm vm32x ymm -// Construct and append a VGATHERDPD instruction to the active function. +// VREDUCESS imm8 m32 xmm k xmm +// VREDUCESS imm8 m32 xmm xmm +// VREDUCESS imm8 xmm xmm k xmm +// VREDUCESS imm8 xmm xmm xmm +// Construct and append a VREDUCESS instruction to the active function. // Operates on the global context. -func VGATHERDPD(xy, v, xy1 operand.Op) { ctx.VGATHERDPD(xy, v, xy1) } +func VREDUCESS(ops ...operand.Op) { ctx.VREDUCESS(ops...) } -// VGATHERDPS: Gather Packed Single-Precision Floating-Point Values Using Signed Doubleword Indices. +// VREDUCESS_Z: Perform Reduction Transformation on a Scalar Single-Precision Floating-Point Value (Zeroing Masking). // // Forms: // -// VGATHERDPS xmm vm32x xmm -// VGATHERDPS ymm vm32y ymm -// Construct and append a VGATHERDPS instruction to the active function. -func (c *Context) VGATHERDPS(xy, v, xy1 operand.Op) { - if inst, err := x86.VGATHERDPS(xy, v, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VREDUCESS.Z imm8 m32 xmm k xmm +// VREDUCESS.Z imm8 xmm xmm k xmm +// Construct and append a VREDUCESS.Z instruction to the active function. +func (c *Context) VREDUCESS_Z(i, mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VREDUCESS_Z(i, mx, x, k, x1)) } -// VGATHERDPS: Gather Packed Single-Precision Floating-Point Values Using Signed Doubleword Indices. +// VREDUCESS_Z: Perform Reduction Transformation on a Scalar Single-Precision Floating-Point Value (Zeroing Masking). // // Forms: // -// VGATHERDPS xmm vm32x xmm -// VGATHERDPS ymm vm32y ymm -// Construct and append a VGATHERDPS instruction to the active function. +// VREDUCESS.Z imm8 m32 xmm k xmm +// VREDUCESS.Z imm8 xmm xmm k xmm +// Construct and append a VREDUCESS.Z instruction to the active function. // Operates on the global context. -func VGATHERDPS(xy, v, xy1 operand.Op) { ctx.VGATHERDPS(xy, v, xy1) } +func VREDUCESS_Z(i, mx, x, k, x1 operand.Op) { ctx.VREDUCESS_Z(i, mx, x, k, x1) } -// VGATHERQPD: Gather Packed Double-Precision Floating-Point Values Using Signed Quadword Indices. +// VRNDSCALEPD: Round Packed Double-Precision Floating-Point Values To Include A Given Number Of Fraction Bits. // // Forms: // -// VGATHERQPD xmm vm64x xmm -// VGATHERQPD ymm vm64y ymm -// Construct and append a VGATHERQPD instruction to the active function. -func (c *Context) VGATHERQPD(xy, v, xy1 operand.Op) { - if inst, err := x86.VGATHERQPD(xy, v, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRNDSCALEPD imm8 m128 k xmm +// VRNDSCALEPD imm8 m128 xmm +// VRNDSCALEPD imm8 m256 k ymm +// VRNDSCALEPD imm8 m256 ymm +// VRNDSCALEPD imm8 xmm k xmm +// VRNDSCALEPD imm8 xmm xmm +// VRNDSCALEPD imm8 ymm k ymm +// VRNDSCALEPD imm8 ymm ymm +// VRNDSCALEPD imm8 m512 k zmm +// VRNDSCALEPD imm8 m512 zmm +// VRNDSCALEPD imm8 zmm k zmm +// VRNDSCALEPD imm8 zmm zmm +// Construct and append a VRNDSCALEPD instruction to the active function. +func (c *Context) VRNDSCALEPD(ops ...operand.Op) { + c.addinstruction(x86.VRNDSCALEPD(ops...)) } -// VGATHERQPD: Gather Packed Double-Precision Floating-Point Values Using Signed Quadword Indices. +// VRNDSCALEPD: Round Packed Double-Precision Floating-Point Values To Include A Given Number Of Fraction Bits. // // Forms: // -// VGATHERQPD xmm vm64x xmm -// VGATHERQPD ymm vm64y ymm -// Construct and append a VGATHERQPD instruction to the active function. +// VRNDSCALEPD imm8 m128 k xmm +// VRNDSCALEPD imm8 m128 xmm +// VRNDSCALEPD imm8 m256 k ymm +// VRNDSCALEPD imm8 m256 ymm +// VRNDSCALEPD imm8 xmm k xmm +// VRNDSCALEPD imm8 xmm xmm +// VRNDSCALEPD imm8 ymm k ymm +// VRNDSCALEPD imm8 ymm ymm +// VRNDSCALEPD imm8 m512 k zmm +// VRNDSCALEPD imm8 m512 zmm +// VRNDSCALEPD imm8 zmm k zmm +// VRNDSCALEPD imm8 zmm zmm +// Construct and append a VRNDSCALEPD instruction to the active function. // Operates on the global context. -func VGATHERQPD(xy, v, xy1 operand.Op) { ctx.VGATHERQPD(xy, v, xy1) } +func VRNDSCALEPD(ops ...operand.Op) { ctx.VRNDSCALEPD(ops...) } -// VGATHERQPS: Gather Packed Single-Precision Floating-Point Values Using Signed Quadword Indices. +// VRNDSCALEPD_BCST: Round Packed Double-Precision Floating-Point Values To Include A Given Number Of Fraction Bits (Broadcast). // // Forms: // -// VGATHERQPS xmm vm64x xmm -// VGATHERQPS xmm vm64y xmm -// Construct and append a VGATHERQPS instruction to the active function. -func (c *Context) VGATHERQPS(x, v, x1 operand.Op) { - if inst, err := x86.VGATHERQPS(x, v, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRNDSCALEPD.BCST imm8 m64 k xmm +// VRNDSCALEPD.BCST imm8 m64 k ymm +// VRNDSCALEPD.BCST imm8 m64 xmm +// VRNDSCALEPD.BCST imm8 m64 ymm +// VRNDSCALEPD.BCST imm8 m64 k zmm +// VRNDSCALEPD.BCST imm8 m64 zmm +// Construct and append a VRNDSCALEPD.BCST instruction to the active function. +func (c *Context) VRNDSCALEPD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VRNDSCALEPD_BCST(ops...)) } -// VGATHERQPS: Gather Packed Single-Precision Floating-Point Values Using Signed Quadword Indices. +// VRNDSCALEPD_BCST: Round Packed Double-Precision Floating-Point Values To Include A Given Number Of Fraction Bits (Broadcast). // // Forms: // -// VGATHERQPS xmm vm64x xmm -// VGATHERQPS xmm vm64y xmm -// Construct and append a VGATHERQPS instruction to the active function. +// VRNDSCALEPD.BCST imm8 m64 k xmm +// VRNDSCALEPD.BCST imm8 m64 k ymm +// VRNDSCALEPD.BCST imm8 m64 xmm +// VRNDSCALEPD.BCST imm8 m64 ymm +// VRNDSCALEPD.BCST imm8 m64 k zmm +// VRNDSCALEPD.BCST imm8 m64 zmm +// Construct and append a VRNDSCALEPD.BCST instruction to the active function. // Operates on the global context. -func VGATHERQPS(x, v, x1 operand.Op) { ctx.VGATHERQPS(x, v, x1) } +func VRNDSCALEPD_BCST(ops ...operand.Op) { ctx.VRNDSCALEPD_BCST(ops...) } -// VHADDPD: Packed Double-FP Horizontal Add. +// VRNDSCALEPD_BCST_Z: Round Packed Double-Precision Floating-Point Values To Include A Given Number Of Fraction Bits (Broadcast, Zeroing Masking). // // Forms: // -// VHADDPD xmm xmm xmm -// VHADDPD m128 xmm xmm -// VHADDPD ymm ymm ymm -// VHADDPD m256 ymm ymm -// Construct and append a VHADDPD instruction to the active function. -func (c *Context) VHADDPD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VHADDPD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRNDSCALEPD.BCST.Z imm8 m64 k xmm +// VRNDSCALEPD.BCST.Z imm8 m64 k ymm +// VRNDSCALEPD.BCST.Z imm8 m64 k zmm +// Construct and append a VRNDSCALEPD.BCST.Z instruction to the active function. +func (c *Context) VRNDSCALEPD_BCST_Z(i, m, k, xyz operand.Op) { + c.addinstruction(x86.VRNDSCALEPD_BCST_Z(i, m, k, xyz)) } -// VHADDPD: Packed Double-FP Horizontal Add. +// VRNDSCALEPD_BCST_Z: Round Packed Double-Precision Floating-Point Values To Include A Given Number Of Fraction Bits (Broadcast, Zeroing Masking). // // Forms: // -// VHADDPD xmm xmm xmm -// VHADDPD m128 xmm xmm -// VHADDPD ymm ymm ymm -// VHADDPD m256 ymm ymm -// Construct and append a VHADDPD instruction to the active function. +// VRNDSCALEPD.BCST.Z imm8 m64 k xmm +// VRNDSCALEPD.BCST.Z imm8 m64 k ymm +// VRNDSCALEPD.BCST.Z imm8 m64 k zmm +// Construct and append a VRNDSCALEPD.BCST.Z instruction to the active function. // Operates on the global context. -func VHADDPD(mxy, xy, xy1 operand.Op) { ctx.VHADDPD(mxy, xy, xy1) } +func VRNDSCALEPD_BCST_Z(i, m, k, xyz operand.Op) { ctx.VRNDSCALEPD_BCST_Z(i, m, k, xyz) } -// VHADDPS: Packed Single-FP Horizontal Add. +// VRNDSCALEPD_SAE: Round Packed Double-Precision Floating-Point Values To Include A Given Number Of Fraction Bits (Suppress All Exceptions). // // Forms: // -// VHADDPS xmm xmm xmm -// VHADDPS m128 xmm xmm -// VHADDPS ymm ymm ymm -// VHADDPS m256 ymm ymm -// Construct and append a VHADDPS instruction to the active function. -func (c *Context) VHADDPS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VHADDPS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRNDSCALEPD.SAE imm8 zmm k zmm +// VRNDSCALEPD.SAE imm8 zmm zmm +// Construct and append a VRNDSCALEPD.SAE instruction to the active function. +func (c *Context) VRNDSCALEPD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VRNDSCALEPD_SAE(ops...)) } -// VHADDPS: Packed Single-FP Horizontal Add. +// VRNDSCALEPD_SAE: Round Packed Double-Precision Floating-Point Values To Include A Given Number Of Fraction Bits (Suppress All Exceptions). // // Forms: // -// VHADDPS xmm xmm xmm -// VHADDPS m128 xmm xmm -// VHADDPS ymm ymm ymm -// VHADDPS m256 ymm ymm -// Construct and append a VHADDPS instruction to the active function. +// VRNDSCALEPD.SAE imm8 zmm k zmm +// VRNDSCALEPD.SAE imm8 zmm zmm +// Construct and append a VRNDSCALEPD.SAE instruction to the active function. // Operates on the global context. -func VHADDPS(mxy, xy, xy1 operand.Op) { ctx.VHADDPS(mxy, xy, xy1) } +func VRNDSCALEPD_SAE(ops ...operand.Op) { ctx.VRNDSCALEPD_SAE(ops...) } -// VHSUBPD: Packed Double-FP Horizontal Subtract. +// VRNDSCALEPD_SAE_Z: Round Packed Double-Precision Floating-Point Values To Include A Given Number Of Fraction Bits (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VHSUBPD xmm xmm xmm -// VHSUBPD m128 xmm xmm -// VHSUBPD ymm ymm ymm -// VHSUBPD m256 ymm ymm -// Construct and append a VHSUBPD instruction to the active function. -func (c *Context) VHSUBPD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VHSUBPD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRNDSCALEPD.SAE.Z imm8 zmm k zmm +// Construct and append a VRNDSCALEPD.SAE.Z instruction to the active function. +func (c *Context) VRNDSCALEPD_SAE_Z(i, z, k, z1 operand.Op) { + c.addinstruction(x86.VRNDSCALEPD_SAE_Z(i, z, k, z1)) } -// VHSUBPD: Packed Double-FP Horizontal Subtract. +// VRNDSCALEPD_SAE_Z: Round Packed Double-Precision Floating-Point Values To Include A Given Number Of Fraction Bits (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VHSUBPD xmm xmm xmm -// VHSUBPD m128 xmm xmm -// VHSUBPD ymm ymm ymm -// VHSUBPD m256 ymm ymm -// Construct and append a VHSUBPD instruction to the active function. +// VRNDSCALEPD.SAE.Z imm8 zmm k zmm +// Construct and append a VRNDSCALEPD.SAE.Z instruction to the active function. // Operates on the global context. -func VHSUBPD(mxy, xy, xy1 operand.Op) { ctx.VHSUBPD(mxy, xy, xy1) } +func VRNDSCALEPD_SAE_Z(i, z, k, z1 operand.Op) { ctx.VRNDSCALEPD_SAE_Z(i, z, k, z1) } -// VHSUBPS: Packed Single-FP Horizontal Subtract. +// VRNDSCALEPD_Z: Round Packed Double-Precision Floating-Point Values To Include A Given Number Of Fraction Bits (Zeroing Masking). // // Forms: // -// VHSUBPS xmm xmm xmm -// VHSUBPS m128 xmm xmm -// VHSUBPS ymm ymm ymm -// VHSUBPS m256 ymm ymm -// Construct and append a VHSUBPS instruction to the active function. -func (c *Context) VHSUBPS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VHSUBPS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRNDSCALEPD.Z imm8 m128 k xmm +// VRNDSCALEPD.Z imm8 m256 k ymm +// VRNDSCALEPD.Z imm8 xmm k xmm +// VRNDSCALEPD.Z imm8 ymm k ymm +// VRNDSCALEPD.Z imm8 m512 k zmm +// VRNDSCALEPD.Z imm8 zmm k zmm +// Construct and append a VRNDSCALEPD.Z instruction to the active function. +func (c *Context) VRNDSCALEPD_Z(i, mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VRNDSCALEPD_Z(i, mxyz, k, xyz)) } -// VHSUBPS: Packed Single-FP Horizontal Subtract. +// VRNDSCALEPD_Z: Round Packed Double-Precision Floating-Point Values To Include A Given Number Of Fraction Bits (Zeroing Masking). // // Forms: // -// VHSUBPS xmm xmm xmm -// VHSUBPS m128 xmm xmm -// VHSUBPS ymm ymm ymm -// VHSUBPS m256 ymm ymm -// Construct and append a VHSUBPS instruction to the active function. +// VRNDSCALEPD.Z imm8 m128 k xmm +// VRNDSCALEPD.Z imm8 m256 k ymm +// VRNDSCALEPD.Z imm8 xmm k xmm +// VRNDSCALEPD.Z imm8 ymm k ymm +// VRNDSCALEPD.Z imm8 m512 k zmm +// VRNDSCALEPD.Z imm8 zmm k zmm +// Construct and append a VRNDSCALEPD.Z instruction to the active function. // Operates on the global context. -func VHSUBPS(mxy, xy, xy1 operand.Op) { ctx.VHSUBPS(mxy, xy, xy1) } +func VRNDSCALEPD_Z(i, mxyz, k, xyz operand.Op) { ctx.VRNDSCALEPD_Z(i, mxyz, k, xyz) } -// VINSERTF128: Insert Packed Floating-Point Values. +// VRNDSCALEPS: Round Packed Single-Precision Floating-Point Values To Include A Given Number Of Fraction Bits. // // Forms: // -// VINSERTF128 imm8 xmm ymm ymm -// VINSERTF128 imm8 m128 ymm ymm -// Construct and append a VINSERTF128 instruction to the active function. -func (c *Context) VINSERTF128(i, mx, y, y1 operand.Op) { - if inst, err := x86.VINSERTF128(i, mx, y, y1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRNDSCALEPS imm8 m128 k xmm +// VRNDSCALEPS imm8 m128 xmm +// VRNDSCALEPS imm8 m256 k ymm +// VRNDSCALEPS imm8 m256 ymm +// VRNDSCALEPS imm8 xmm k xmm +// VRNDSCALEPS imm8 xmm xmm +// VRNDSCALEPS imm8 ymm k ymm +// VRNDSCALEPS imm8 ymm ymm +// VRNDSCALEPS imm8 m512 k zmm +// VRNDSCALEPS imm8 m512 zmm +// VRNDSCALEPS imm8 zmm k zmm +// VRNDSCALEPS imm8 zmm zmm +// Construct and append a VRNDSCALEPS instruction to the active function. +func (c *Context) VRNDSCALEPS(ops ...operand.Op) { + c.addinstruction(x86.VRNDSCALEPS(ops...)) } -// VINSERTF128: Insert Packed Floating-Point Values. +// VRNDSCALEPS: Round Packed Single-Precision Floating-Point Values To Include A Given Number Of Fraction Bits. // // Forms: // -// VINSERTF128 imm8 xmm ymm ymm -// VINSERTF128 imm8 m128 ymm ymm -// Construct and append a VINSERTF128 instruction to the active function. +// VRNDSCALEPS imm8 m128 k xmm +// VRNDSCALEPS imm8 m128 xmm +// VRNDSCALEPS imm8 m256 k ymm +// VRNDSCALEPS imm8 m256 ymm +// VRNDSCALEPS imm8 xmm k xmm +// VRNDSCALEPS imm8 xmm xmm +// VRNDSCALEPS imm8 ymm k ymm +// VRNDSCALEPS imm8 ymm ymm +// VRNDSCALEPS imm8 m512 k zmm +// VRNDSCALEPS imm8 m512 zmm +// VRNDSCALEPS imm8 zmm k zmm +// VRNDSCALEPS imm8 zmm zmm +// Construct and append a VRNDSCALEPS instruction to the active function. // Operates on the global context. -func VINSERTF128(i, mx, y, y1 operand.Op) { ctx.VINSERTF128(i, mx, y, y1) } +func VRNDSCALEPS(ops ...operand.Op) { ctx.VRNDSCALEPS(ops...) } -// VINSERTI128: Insert Packed Integer Values. +// VRNDSCALEPS_BCST: Round Packed Single-Precision Floating-Point Values To Include A Given Number Of Fraction Bits (Broadcast). // // Forms: // -// VINSERTI128 imm8 xmm ymm ymm -// VINSERTI128 imm8 m128 ymm ymm -// Construct and append a VINSERTI128 instruction to the active function. -func (c *Context) VINSERTI128(i, mx, y, y1 operand.Op) { - if inst, err := x86.VINSERTI128(i, mx, y, y1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRNDSCALEPS.BCST imm8 m32 k xmm +// VRNDSCALEPS.BCST imm8 m32 k ymm +// VRNDSCALEPS.BCST imm8 m32 xmm +// VRNDSCALEPS.BCST imm8 m32 ymm +// VRNDSCALEPS.BCST imm8 m32 k zmm +// VRNDSCALEPS.BCST imm8 m32 zmm +// Construct and append a VRNDSCALEPS.BCST instruction to the active function. +func (c *Context) VRNDSCALEPS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VRNDSCALEPS_BCST(ops...)) } -// VINSERTI128: Insert Packed Integer Values. +// VRNDSCALEPS_BCST: Round Packed Single-Precision Floating-Point Values To Include A Given Number Of Fraction Bits (Broadcast). // // Forms: // -// VINSERTI128 imm8 xmm ymm ymm -// VINSERTI128 imm8 m128 ymm ymm -// Construct and append a VINSERTI128 instruction to the active function. +// VRNDSCALEPS.BCST imm8 m32 k xmm +// VRNDSCALEPS.BCST imm8 m32 k ymm +// VRNDSCALEPS.BCST imm8 m32 xmm +// VRNDSCALEPS.BCST imm8 m32 ymm +// VRNDSCALEPS.BCST imm8 m32 k zmm +// VRNDSCALEPS.BCST imm8 m32 zmm +// Construct and append a VRNDSCALEPS.BCST instruction to the active function. // Operates on the global context. -func VINSERTI128(i, mx, y, y1 operand.Op) { ctx.VINSERTI128(i, mx, y, y1) } +func VRNDSCALEPS_BCST(ops ...operand.Op) { ctx.VRNDSCALEPS_BCST(ops...) } -// VINSERTPS: Insert Packed Single Precision Floating-Point Value. +// VRNDSCALEPS_BCST_Z: Round Packed Single-Precision Floating-Point Values To Include A Given Number Of Fraction Bits (Broadcast, Zeroing Masking). // // Forms: // -// VINSERTPS imm8 xmm xmm xmm -// VINSERTPS imm8 m32 xmm xmm -// Construct and append a VINSERTPS instruction to the active function. -func (c *Context) VINSERTPS(i, mx, x, x1 operand.Op) { - if inst, err := x86.VINSERTPS(i, mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRNDSCALEPS.BCST.Z imm8 m32 k xmm +// VRNDSCALEPS.BCST.Z imm8 m32 k ymm +// VRNDSCALEPS.BCST.Z imm8 m32 k zmm +// Construct and append a VRNDSCALEPS.BCST.Z instruction to the active function. +func (c *Context) VRNDSCALEPS_BCST_Z(i, m, k, xyz operand.Op) { + c.addinstruction(x86.VRNDSCALEPS_BCST_Z(i, m, k, xyz)) } -// VINSERTPS: Insert Packed Single Precision Floating-Point Value. +// VRNDSCALEPS_BCST_Z: Round Packed Single-Precision Floating-Point Values To Include A Given Number Of Fraction Bits (Broadcast, Zeroing Masking). // // Forms: // -// VINSERTPS imm8 xmm xmm xmm -// VINSERTPS imm8 m32 xmm xmm -// Construct and append a VINSERTPS instruction to the active function. +// VRNDSCALEPS.BCST.Z imm8 m32 k xmm +// VRNDSCALEPS.BCST.Z imm8 m32 k ymm +// VRNDSCALEPS.BCST.Z imm8 m32 k zmm +// Construct and append a VRNDSCALEPS.BCST.Z instruction to the active function. // Operates on the global context. -func VINSERTPS(i, mx, x, x1 operand.Op) { ctx.VINSERTPS(i, mx, x, x1) } +func VRNDSCALEPS_BCST_Z(i, m, k, xyz operand.Op) { ctx.VRNDSCALEPS_BCST_Z(i, m, k, xyz) } -// VLDDQU: Load Unaligned Integer 128 Bits. +// VRNDSCALEPS_SAE: Round Packed Single-Precision Floating-Point Values To Include A Given Number Of Fraction Bits (Suppress All Exceptions). // // Forms: // -// VLDDQU m128 xmm -// VLDDQU m256 ymm -// Construct and append a VLDDQU instruction to the active function. -func (c *Context) VLDDQU(m, xy operand.Op) { - if inst, err := x86.VLDDQU(m, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRNDSCALEPS.SAE imm8 zmm k zmm +// VRNDSCALEPS.SAE imm8 zmm zmm +// Construct and append a VRNDSCALEPS.SAE instruction to the active function. +func (c *Context) VRNDSCALEPS_SAE(ops ...operand.Op) { + c.addinstruction(x86.VRNDSCALEPS_SAE(ops...)) } -// VLDDQU: Load Unaligned Integer 128 Bits. +// VRNDSCALEPS_SAE: Round Packed Single-Precision Floating-Point Values To Include A Given Number Of Fraction Bits (Suppress All Exceptions). // // Forms: // -// VLDDQU m128 xmm -// VLDDQU m256 ymm -// Construct and append a VLDDQU instruction to the active function. +// VRNDSCALEPS.SAE imm8 zmm k zmm +// VRNDSCALEPS.SAE imm8 zmm zmm +// Construct and append a VRNDSCALEPS.SAE instruction to the active function. // Operates on the global context. -func VLDDQU(m, xy operand.Op) { ctx.VLDDQU(m, xy) } +func VRNDSCALEPS_SAE(ops ...operand.Op) { ctx.VRNDSCALEPS_SAE(ops...) } -// VLDMXCSR: Load MXCSR Register. +// VRNDSCALEPS_SAE_Z: Round Packed Single-Precision Floating-Point Values To Include A Given Number Of Fraction Bits (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VLDMXCSR m32 -// Construct and append a VLDMXCSR instruction to the active function. -func (c *Context) VLDMXCSR(m operand.Op) { - if inst, err := x86.VLDMXCSR(m); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRNDSCALEPS.SAE.Z imm8 zmm k zmm +// Construct and append a VRNDSCALEPS.SAE.Z instruction to the active function. +func (c *Context) VRNDSCALEPS_SAE_Z(i, z, k, z1 operand.Op) { + c.addinstruction(x86.VRNDSCALEPS_SAE_Z(i, z, k, z1)) } -// VLDMXCSR: Load MXCSR Register. +// VRNDSCALEPS_SAE_Z: Round Packed Single-Precision Floating-Point Values To Include A Given Number Of Fraction Bits (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VLDMXCSR m32 -// Construct and append a VLDMXCSR instruction to the active function. +// VRNDSCALEPS.SAE.Z imm8 zmm k zmm +// Construct and append a VRNDSCALEPS.SAE.Z instruction to the active function. // Operates on the global context. -func VLDMXCSR(m operand.Op) { ctx.VLDMXCSR(m) } +func VRNDSCALEPS_SAE_Z(i, z, k, z1 operand.Op) { ctx.VRNDSCALEPS_SAE_Z(i, z, k, z1) } -// VMASKMOVDQU: Store Selected Bytes of Double Quadword. +// VRNDSCALEPS_Z: Round Packed Single-Precision Floating-Point Values To Include A Given Number Of Fraction Bits (Zeroing Masking). // // Forms: // -// VMASKMOVDQU xmm xmm -// Construct and append a VMASKMOVDQU instruction to the active function. -func (c *Context) VMASKMOVDQU(x, x1 operand.Op) { - if inst, err := x86.VMASKMOVDQU(x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRNDSCALEPS.Z imm8 m128 k xmm +// VRNDSCALEPS.Z imm8 m256 k ymm +// VRNDSCALEPS.Z imm8 xmm k xmm +// VRNDSCALEPS.Z imm8 ymm k ymm +// VRNDSCALEPS.Z imm8 m512 k zmm +// VRNDSCALEPS.Z imm8 zmm k zmm +// Construct and append a VRNDSCALEPS.Z instruction to the active function. +func (c *Context) VRNDSCALEPS_Z(i, mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VRNDSCALEPS_Z(i, mxyz, k, xyz)) } -// VMASKMOVDQU: Store Selected Bytes of Double Quadword. +// VRNDSCALEPS_Z: Round Packed Single-Precision Floating-Point Values To Include A Given Number Of Fraction Bits (Zeroing Masking). // // Forms: // -// VMASKMOVDQU xmm xmm -// Construct and append a VMASKMOVDQU instruction to the active function. +// VRNDSCALEPS.Z imm8 m128 k xmm +// VRNDSCALEPS.Z imm8 m256 k ymm +// VRNDSCALEPS.Z imm8 xmm k xmm +// VRNDSCALEPS.Z imm8 ymm k ymm +// VRNDSCALEPS.Z imm8 m512 k zmm +// VRNDSCALEPS.Z imm8 zmm k zmm +// Construct and append a VRNDSCALEPS.Z instruction to the active function. // Operates on the global context. -func VMASKMOVDQU(x, x1 operand.Op) { ctx.VMASKMOVDQU(x, x1) } +func VRNDSCALEPS_Z(i, mxyz, k, xyz operand.Op) { ctx.VRNDSCALEPS_Z(i, mxyz, k, xyz) } -// VMASKMOVPD: Conditional Move Packed Double-Precision Floating-Point Values. +// VRNDSCALESD: Round Scalar Double-Precision Floating-Point Value To Include A Given Number Of Fraction Bits. // // Forms: // -// VMASKMOVPD m128 xmm xmm -// VMASKMOVPD m256 ymm ymm -// VMASKMOVPD xmm xmm m128 -// VMASKMOVPD ymm ymm m256 -// Construct and append a VMASKMOVPD instruction to the active function. -func (c *Context) VMASKMOVPD(mxy, xy, mxy1 operand.Op) { - if inst, err := x86.VMASKMOVPD(mxy, xy, mxy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRNDSCALESD imm8 m64 xmm k xmm +// VRNDSCALESD imm8 m64 xmm xmm +// VRNDSCALESD imm8 xmm xmm k xmm +// VRNDSCALESD imm8 xmm xmm xmm +// Construct and append a VRNDSCALESD instruction to the active function. +func (c *Context) VRNDSCALESD(ops ...operand.Op) { + c.addinstruction(x86.VRNDSCALESD(ops...)) } -// VMASKMOVPD: Conditional Move Packed Double-Precision Floating-Point Values. +// VRNDSCALESD: Round Scalar Double-Precision Floating-Point Value To Include A Given Number Of Fraction Bits. // // Forms: // -// VMASKMOVPD m128 xmm xmm -// VMASKMOVPD m256 ymm ymm -// VMASKMOVPD xmm xmm m128 -// VMASKMOVPD ymm ymm m256 -// Construct and append a VMASKMOVPD instruction to the active function. +// VRNDSCALESD imm8 m64 xmm k xmm +// VRNDSCALESD imm8 m64 xmm xmm +// VRNDSCALESD imm8 xmm xmm k xmm +// VRNDSCALESD imm8 xmm xmm xmm +// Construct and append a VRNDSCALESD instruction to the active function. // Operates on the global context. -func VMASKMOVPD(mxy, xy, mxy1 operand.Op) { ctx.VMASKMOVPD(mxy, xy, mxy1) } +func VRNDSCALESD(ops ...operand.Op) { ctx.VRNDSCALESD(ops...) } -// VMASKMOVPS: Conditional Move Packed Single-Precision Floating-Point Values. +// VRNDSCALESD_SAE: Round Scalar Double-Precision Floating-Point Value To Include A Given Number Of Fraction Bits (Suppress All Exceptions). // // Forms: // -// VMASKMOVPS m128 xmm xmm -// VMASKMOVPS m256 ymm ymm -// VMASKMOVPS xmm xmm m128 -// VMASKMOVPS ymm ymm m256 -// Construct and append a VMASKMOVPS instruction to the active function. -func (c *Context) VMASKMOVPS(mxy, xy, mxy1 operand.Op) { - if inst, err := x86.VMASKMOVPS(mxy, xy, mxy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRNDSCALESD.SAE imm8 xmm xmm k xmm +// VRNDSCALESD.SAE imm8 xmm xmm xmm +// Construct and append a VRNDSCALESD.SAE instruction to the active function. +func (c *Context) VRNDSCALESD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VRNDSCALESD_SAE(ops...)) } -// VMASKMOVPS: Conditional Move Packed Single-Precision Floating-Point Values. +// VRNDSCALESD_SAE: Round Scalar Double-Precision Floating-Point Value To Include A Given Number Of Fraction Bits (Suppress All Exceptions). // // Forms: // -// VMASKMOVPS m128 xmm xmm -// VMASKMOVPS m256 ymm ymm -// VMASKMOVPS xmm xmm m128 -// VMASKMOVPS ymm ymm m256 -// Construct and append a VMASKMOVPS instruction to the active function. +// VRNDSCALESD.SAE imm8 xmm xmm k xmm +// VRNDSCALESD.SAE imm8 xmm xmm xmm +// Construct and append a VRNDSCALESD.SAE instruction to the active function. // Operates on the global context. -func VMASKMOVPS(mxy, xy, mxy1 operand.Op) { ctx.VMASKMOVPS(mxy, xy, mxy1) } +func VRNDSCALESD_SAE(ops ...operand.Op) { ctx.VRNDSCALESD_SAE(ops...) } -// VMAXPD: Return Maximum Packed Double-Precision Floating-Point Values. +// VRNDSCALESD_SAE_Z: Round Scalar Double-Precision Floating-Point Value To Include A Given Number Of Fraction Bits (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VMAXPD xmm xmm xmm -// VMAXPD m128 xmm xmm -// VMAXPD ymm ymm ymm -// VMAXPD m256 ymm ymm -// Construct and append a VMAXPD instruction to the active function. -func (c *Context) VMAXPD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VMAXPD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRNDSCALESD.SAE.Z imm8 xmm xmm k xmm +// Construct and append a VRNDSCALESD.SAE.Z instruction to the active function. +func (c *Context) VRNDSCALESD_SAE_Z(i, x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VRNDSCALESD_SAE_Z(i, x, x1, k, x2)) } -// VMAXPD: Return Maximum Packed Double-Precision Floating-Point Values. +// VRNDSCALESD_SAE_Z: Round Scalar Double-Precision Floating-Point Value To Include A Given Number Of Fraction Bits (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VMAXPD xmm xmm xmm -// VMAXPD m128 xmm xmm -// VMAXPD ymm ymm ymm -// VMAXPD m256 ymm ymm -// Construct and append a VMAXPD instruction to the active function. +// VRNDSCALESD.SAE.Z imm8 xmm xmm k xmm +// Construct and append a VRNDSCALESD.SAE.Z instruction to the active function. // Operates on the global context. -func VMAXPD(mxy, xy, xy1 operand.Op) { ctx.VMAXPD(mxy, xy, xy1) } +func VRNDSCALESD_SAE_Z(i, x, x1, k, x2 operand.Op) { ctx.VRNDSCALESD_SAE_Z(i, x, x1, k, x2) } -// VMAXPS: Return Maximum Packed Single-Precision Floating-Point Values. +// VRNDSCALESD_Z: Round Scalar Double-Precision Floating-Point Value To Include A Given Number Of Fraction Bits (Zeroing Masking). // // Forms: // -// VMAXPS xmm xmm xmm -// VMAXPS m128 xmm xmm -// VMAXPS ymm ymm ymm -// VMAXPS m256 ymm ymm -// Construct and append a VMAXPS instruction to the active function. -func (c *Context) VMAXPS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VMAXPS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRNDSCALESD.Z imm8 m64 xmm k xmm +// VRNDSCALESD.Z imm8 xmm xmm k xmm +// Construct and append a VRNDSCALESD.Z instruction to the active function. +func (c *Context) VRNDSCALESD_Z(i, mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VRNDSCALESD_Z(i, mx, x, k, x1)) } -// VMAXPS: Return Maximum Packed Single-Precision Floating-Point Values. +// VRNDSCALESD_Z: Round Scalar Double-Precision Floating-Point Value To Include A Given Number Of Fraction Bits (Zeroing Masking). // // Forms: // -// VMAXPS xmm xmm xmm -// VMAXPS m128 xmm xmm -// VMAXPS ymm ymm ymm -// VMAXPS m256 ymm ymm -// Construct and append a VMAXPS instruction to the active function. +// VRNDSCALESD.Z imm8 m64 xmm k xmm +// VRNDSCALESD.Z imm8 xmm xmm k xmm +// Construct and append a VRNDSCALESD.Z instruction to the active function. // Operates on the global context. -func VMAXPS(mxy, xy, xy1 operand.Op) { ctx.VMAXPS(mxy, xy, xy1) } +func VRNDSCALESD_Z(i, mx, x, k, x1 operand.Op) { ctx.VRNDSCALESD_Z(i, mx, x, k, x1) } -// VMAXSD: Return Maximum Scalar Double-Precision Floating-Point Value. +// VRNDSCALESS: Round Scalar Single-Precision Floating-Point Value To Include A Given Number Of Fraction Bits. // // Forms: // -// VMAXSD xmm xmm xmm -// VMAXSD m64 xmm xmm -// Construct and append a VMAXSD instruction to the active function. -func (c *Context) VMAXSD(mx, x, x1 operand.Op) { - if inst, err := x86.VMAXSD(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRNDSCALESS imm8 m32 xmm k xmm +// VRNDSCALESS imm8 m32 xmm xmm +// VRNDSCALESS imm8 xmm xmm k xmm +// VRNDSCALESS imm8 xmm xmm xmm +// Construct and append a VRNDSCALESS instruction to the active function. +func (c *Context) VRNDSCALESS(ops ...operand.Op) { + c.addinstruction(x86.VRNDSCALESS(ops...)) } -// VMAXSD: Return Maximum Scalar Double-Precision Floating-Point Value. +// VRNDSCALESS: Round Scalar Single-Precision Floating-Point Value To Include A Given Number Of Fraction Bits. // // Forms: // -// VMAXSD xmm xmm xmm -// VMAXSD m64 xmm xmm -// Construct and append a VMAXSD instruction to the active function. +// VRNDSCALESS imm8 m32 xmm k xmm +// VRNDSCALESS imm8 m32 xmm xmm +// VRNDSCALESS imm8 xmm xmm k xmm +// VRNDSCALESS imm8 xmm xmm xmm +// Construct and append a VRNDSCALESS instruction to the active function. // Operates on the global context. -func VMAXSD(mx, x, x1 operand.Op) { ctx.VMAXSD(mx, x, x1) } +func VRNDSCALESS(ops ...operand.Op) { ctx.VRNDSCALESS(ops...) } -// VMAXSS: Return Maximum Scalar Single-Precision Floating-Point Value. +// VRNDSCALESS_SAE: Round Scalar Single-Precision Floating-Point Value To Include A Given Number Of Fraction Bits (Suppress All Exceptions). // // Forms: // -// VMAXSS xmm xmm xmm -// VMAXSS m32 xmm xmm -// Construct and append a VMAXSS instruction to the active function. -func (c *Context) VMAXSS(mx, x, x1 operand.Op) { - if inst, err := x86.VMAXSS(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRNDSCALESS.SAE imm8 xmm xmm k xmm +// VRNDSCALESS.SAE imm8 xmm xmm xmm +// Construct and append a VRNDSCALESS.SAE instruction to the active function. +func (c *Context) VRNDSCALESS_SAE(ops ...operand.Op) { + c.addinstruction(x86.VRNDSCALESS_SAE(ops...)) } -// VMAXSS: Return Maximum Scalar Single-Precision Floating-Point Value. +// VRNDSCALESS_SAE: Round Scalar Single-Precision Floating-Point Value To Include A Given Number Of Fraction Bits (Suppress All Exceptions). // // Forms: // -// VMAXSS xmm xmm xmm -// VMAXSS m32 xmm xmm -// Construct and append a VMAXSS instruction to the active function. +// VRNDSCALESS.SAE imm8 xmm xmm k xmm +// VRNDSCALESS.SAE imm8 xmm xmm xmm +// Construct and append a VRNDSCALESS.SAE instruction to the active function. // Operates on the global context. -func VMAXSS(mx, x, x1 operand.Op) { ctx.VMAXSS(mx, x, x1) } +func VRNDSCALESS_SAE(ops ...operand.Op) { ctx.VRNDSCALESS_SAE(ops...) } -// VMINPD: Return Minimum Packed Double-Precision Floating-Point Values. +// VRNDSCALESS_SAE_Z: Round Scalar Single-Precision Floating-Point Value To Include A Given Number Of Fraction Bits (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VMINPD xmm xmm xmm -// VMINPD m128 xmm xmm -// VMINPD ymm ymm ymm -// VMINPD m256 ymm ymm -// Construct and append a VMINPD instruction to the active function. -func (c *Context) VMINPD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VMINPD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRNDSCALESS.SAE.Z imm8 xmm xmm k xmm +// Construct and append a VRNDSCALESS.SAE.Z instruction to the active function. +func (c *Context) VRNDSCALESS_SAE_Z(i, x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VRNDSCALESS_SAE_Z(i, x, x1, k, x2)) } -// VMINPD: Return Minimum Packed Double-Precision Floating-Point Values. +// VRNDSCALESS_SAE_Z: Round Scalar Single-Precision Floating-Point Value To Include A Given Number Of Fraction Bits (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VMINPD xmm xmm xmm -// VMINPD m128 xmm xmm -// VMINPD ymm ymm ymm -// VMINPD m256 ymm ymm -// Construct and append a VMINPD instruction to the active function. +// VRNDSCALESS.SAE.Z imm8 xmm xmm k xmm +// Construct and append a VRNDSCALESS.SAE.Z instruction to the active function. // Operates on the global context. -func VMINPD(mxy, xy, xy1 operand.Op) { ctx.VMINPD(mxy, xy, xy1) } +func VRNDSCALESS_SAE_Z(i, x, x1, k, x2 operand.Op) { ctx.VRNDSCALESS_SAE_Z(i, x, x1, k, x2) } -// VMINPS: Return Minimum Packed Single-Precision Floating-Point Values. +// VRNDSCALESS_Z: Round Scalar Single-Precision Floating-Point Value To Include A Given Number Of Fraction Bits (Zeroing Masking). // // Forms: // -// VMINPS xmm xmm xmm -// VMINPS m128 xmm xmm -// VMINPS ymm ymm ymm -// VMINPS m256 ymm ymm -// Construct and append a VMINPS instruction to the active function. -func (c *Context) VMINPS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VMINPS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRNDSCALESS.Z imm8 m32 xmm k xmm +// VRNDSCALESS.Z imm8 xmm xmm k xmm +// Construct and append a VRNDSCALESS.Z instruction to the active function. +func (c *Context) VRNDSCALESS_Z(i, mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VRNDSCALESS_Z(i, mx, x, k, x1)) } -// VMINPS: Return Minimum Packed Single-Precision Floating-Point Values. +// VRNDSCALESS_Z: Round Scalar Single-Precision Floating-Point Value To Include A Given Number Of Fraction Bits (Zeroing Masking). // // Forms: // -// VMINPS xmm xmm xmm -// VMINPS m128 xmm xmm -// VMINPS ymm ymm ymm -// VMINPS m256 ymm ymm -// Construct and append a VMINPS instruction to the active function. +// VRNDSCALESS.Z imm8 m32 xmm k xmm +// VRNDSCALESS.Z imm8 xmm xmm k xmm +// Construct and append a VRNDSCALESS.Z instruction to the active function. // Operates on the global context. -func VMINPS(mxy, xy, xy1 operand.Op) { ctx.VMINPS(mxy, xy, xy1) } +func VRNDSCALESS_Z(i, mx, x, k, x1 operand.Op) { ctx.VRNDSCALESS_Z(i, mx, x, k, x1) } -// VMINSD: Return Minimum Scalar Double-Precision Floating-Point Value. +// VROUNDPD: Round Packed Double Precision Floating-Point Values. // // Forms: // -// VMINSD xmm xmm xmm -// VMINSD m64 xmm xmm -// Construct and append a VMINSD instruction to the active function. -func (c *Context) VMINSD(mx, x, x1 operand.Op) { - if inst, err := x86.VMINSD(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VROUNDPD imm8 m128 xmm +// VROUNDPD imm8 m256 ymm +// VROUNDPD imm8 xmm xmm +// VROUNDPD imm8 ymm ymm +// Construct and append a VROUNDPD instruction to the active function. +func (c *Context) VROUNDPD(i, mxy, xy operand.Op) { + c.addinstruction(x86.VROUNDPD(i, mxy, xy)) } -// VMINSD: Return Minimum Scalar Double-Precision Floating-Point Value. +// VROUNDPD: Round Packed Double Precision Floating-Point Values. // // Forms: // -// VMINSD xmm xmm xmm -// VMINSD m64 xmm xmm -// Construct and append a VMINSD instruction to the active function. +// VROUNDPD imm8 m128 xmm +// VROUNDPD imm8 m256 ymm +// VROUNDPD imm8 xmm xmm +// VROUNDPD imm8 ymm ymm +// Construct and append a VROUNDPD instruction to the active function. // Operates on the global context. -func VMINSD(mx, x, x1 operand.Op) { ctx.VMINSD(mx, x, x1) } +func VROUNDPD(i, mxy, xy operand.Op) { ctx.VROUNDPD(i, mxy, xy) } -// VMINSS: Return Minimum Scalar Single-Precision Floating-Point Value. +// VROUNDPS: Round Packed Single Precision Floating-Point Values. // // Forms: // -// VMINSS xmm xmm xmm -// VMINSS m32 xmm xmm -// Construct and append a VMINSS instruction to the active function. -func (c *Context) VMINSS(mx, x, x1 operand.Op) { - if inst, err := x86.VMINSS(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VROUNDPS imm8 m128 xmm +// VROUNDPS imm8 m256 ymm +// VROUNDPS imm8 xmm xmm +// VROUNDPS imm8 ymm ymm +// Construct and append a VROUNDPS instruction to the active function. +func (c *Context) VROUNDPS(i, mxy, xy operand.Op) { + c.addinstruction(x86.VROUNDPS(i, mxy, xy)) } -// VMINSS: Return Minimum Scalar Single-Precision Floating-Point Value. +// VROUNDPS: Round Packed Single Precision Floating-Point Values. // // Forms: // -// VMINSS xmm xmm xmm -// VMINSS m32 xmm xmm -// Construct and append a VMINSS instruction to the active function. +// VROUNDPS imm8 m128 xmm +// VROUNDPS imm8 m256 ymm +// VROUNDPS imm8 xmm xmm +// VROUNDPS imm8 ymm ymm +// Construct and append a VROUNDPS instruction to the active function. // Operates on the global context. -func VMINSS(mx, x, x1 operand.Op) { ctx.VMINSS(mx, x, x1) } +func VROUNDPS(i, mxy, xy operand.Op) { ctx.VROUNDPS(i, mxy, xy) } -// VMOVAPD: Move Aligned Packed Double-Precision Floating-Point Values. +// VROUNDSD: Round Scalar Double Precision Floating-Point Values. // // Forms: // -// VMOVAPD xmm xmm -// VMOVAPD m128 xmm -// VMOVAPD ymm ymm -// VMOVAPD m256 ymm -// VMOVAPD xmm m128 -// VMOVAPD ymm m256 -// Construct and append a VMOVAPD instruction to the active function. -func (c *Context) VMOVAPD(mxy, mxy1 operand.Op) { - if inst, err := x86.VMOVAPD(mxy, mxy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VROUNDSD imm8 m64 xmm xmm +// VROUNDSD imm8 xmm xmm xmm +// Construct and append a VROUNDSD instruction to the active function. +func (c *Context) VROUNDSD(i, mx, x, x1 operand.Op) { + c.addinstruction(x86.VROUNDSD(i, mx, x, x1)) } -// VMOVAPD: Move Aligned Packed Double-Precision Floating-Point Values. +// VROUNDSD: Round Scalar Double Precision Floating-Point Values. // // Forms: // -// VMOVAPD xmm xmm -// VMOVAPD m128 xmm -// VMOVAPD ymm ymm -// VMOVAPD m256 ymm -// VMOVAPD xmm m128 -// VMOVAPD ymm m256 -// Construct and append a VMOVAPD instruction to the active function. +// VROUNDSD imm8 m64 xmm xmm +// VROUNDSD imm8 xmm xmm xmm +// Construct and append a VROUNDSD instruction to the active function. // Operates on the global context. -func VMOVAPD(mxy, mxy1 operand.Op) { ctx.VMOVAPD(mxy, mxy1) } +func VROUNDSD(i, mx, x, x1 operand.Op) { ctx.VROUNDSD(i, mx, x, x1) } -// VMOVAPS: Move Aligned Packed Single-Precision Floating-Point Values. +// VROUNDSS: Round Scalar Single Precision Floating-Point Values. // // Forms: // -// VMOVAPS xmm xmm -// VMOVAPS m128 xmm -// VMOVAPS ymm ymm -// VMOVAPS m256 ymm -// VMOVAPS xmm m128 -// VMOVAPS ymm m256 -// Construct and append a VMOVAPS instruction to the active function. -func (c *Context) VMOVAPS(mxy, mxy1 operand.Op) { - if inst, err := x86.VMOVAPS(mxy, mxy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VROUNDSS imm8 m32 xmm xmm +// VROUNDSS imm8 xmm xmm xmm +// Construct and append a VROUNDSS instruction to the active function. +func (c *Context) VROUNDSS(i, mx, x, x1 operand.Op) { + c.addinstruction(x86.VROUNDSS(i, mx, x, x1)) } -// VMOVAPS: Move Aligned Packed Single-Precision Floating-Point Values. +// VROUNDSS: Round Scalar Single Precision Floating-Point Values. // // Forms: // -// VMOVAPS xmm xmm -// VMOVAPS m128 xmm -// VMOVAPS ymm ymm -// VMOVAPS m256 ymm -// VMOVAPS xmm m128 -// VMOVAPS ymm m256 -// Construct and append a VMOVAPS instruction to the active function. +// VROUNDSS imm8 m32 xmm xmm +// VROUNDSS imm8 xmm xmm xmm +// Construct and append a VROUNDSS instruction to the active function. // Operates on the global context. -func VMOVAPS(mxy, mxy1 operand.Op) { ctx.VMOVAPS(mxy, mxy1) } +func VROUNDSS(i, mx, x, x1 operand.Op) { ctx.VROUNDSS(i, mx, x, x1) } -// VMOVD: Move Doubleword. +// VRSQRT14PD: Compute Approximate Reciprocals of Square Roots of Packed Double-Precision Floating-Point Values. // // Forms: // -// VMOVD xmm r32 -// VMOVD r32 xmm -// VMOVD m32 xmm -// VMOVD xmm m32 -// Construct and append a VMOVD instruction to the active function. -func (c *Context) VMOVD(mrx, mrx1 operand.Op) { - if inst, err := x86.VMOVD(mrx, mrx1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRT14PD m128 k xmm +// VRSQRT14PD m128 xmm +// VRSQRT14PD m256 k ymm +// VRSQRT14PD m256 ymm +// VRSQRT14PD xmm k xmm +// VRSQRT14PD xmm xmm +// VRSQRT14PD ymm k ymm +// VRSQRT14PD ymm ymm +// VRSQRT14PD m512 k zmm +// VRSQRT14PD m512 zmm +// VRSQRT14PD zmm k zmm +// VRSQRT14PD zmm zmm +// Construct and append a VRSQRT14PD instruction to the active function. +func (c *Context) VRSQRT14PD(ops ...operand.Op) { + c.addinstruction(x86.VRSQRT14PD(ops...)) } -// VMOVD: Move Doubleword. +// VRSQRT14PD: Compute Approximate Reciprocals of Square Roots of Packed Double-Precision Floating-Point Values. // // Forms: // -// VMOVD xmm r32 -// VMOVD r32 xmm -// VMOVD m32 xmm -// VMOVD xmm m32 -// Construct and append a VMOVD instruction to the active function. +// VRSQRT14PD m128 k xmm +// VRSQRT14PD m128 xmm +// VRSQRT14PD m256 k ymm +// VRSQRT14PD m256 ymm +// VRSQRT14PD xmm k xmm +// VRSQRT14PD xmm xmm +// VRSQRT14PD ymm k ymm +// VRSQRT14PD ymm ymm +// VRSQRT14PD m512 k zmm +// VRSQRT14PD m512 zmm +// VRSQRT14PD zmm k zmm +// VRSQRT14PD zmm zmm +// Construct and append a VRSQRT14PD instruction to the active function. // Operates on the global context. -func VMOVD(mrx, mrx1 operand.Op) { ctx.VMOVD(mrx, mrx1) } +func VRSQRT14PD(ops ...operand.Op) { ctx.VRSQRT14PD(ops...) } -// VMOVDDUP: Move One Double-FP and Duplicate. +// VRSQRT14PD_BCST: Compute Approximate Reciprocals of Square Roots of Packed Double-Precision Floating-Point Values (Broadcast). // // Forms: // -// VMOVDDUP xmm xmm -// VMOVDDUP m64 xmm -// VMOVDDUP ymm ymm -// VMOVDDUP m256 ymm -// Construct and append a VMOVDDUP instruction to the active function. -func (c *Context) VMOVDDUP(mxy, xy operand.Op) { - if inst, err := x86.VMOVDDUP(mxy, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRT14PD.BCST m64 k xmm +// VRSQRT14PD.BCST m64 k ymm +// VRSQRT14PD.BCST m64 xmm +// VRSQRT14PD.BCST m64 ymm +// VRSQRT14PD.BCST m64 k zmm +// VRSQRT14PD.BCST m64 zmm +// Construct and append a VRSQRT14PD.BCST instruction to the active function. +func (c *Context) VRSQRT14PD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VRSQRT14PD_BCST(ops...)) } -// VMOVDDUP: Move One Double-FP and Duplicate. +// VRSQRT14PD_BCST: Compute Approximate Reciprocals of Square Roots of Packed Double-Precision Floating-Point Values (Broadcast). // // Forms: // -// VMOVDDUP xmm xmm -// VMOVDDUP m64 xmm -// VMOVDDUP ymm ymm -// VMOVDDUP m256 ymm -// Construct and append a VMOVDDUP instruction to the active function. +// VRSQRT14PD.BCST m64 k xmm +// VRSQRT14PD.BCST m64 k ymm +// VRSQRT14PD.BCST m64 xmm +// VRSQRT14PD.BCST m64 ymm +// VRSQRT14PD.BCST m64 k zmm +// VRSQRT14PD.BCST m64 zmm +// Construct and append a VRSQRT14PD.BCST instruction to the active function. // Operates on the global context. -func VMOVDDUP(mxy, xy operand.Op) { ctx.VMOVDDUP(mxy, xy) } +func VRSQRT14PD_BCST(ops ...operand.Op) { ctx.VRSQRT14PD_BCST(ops...) } -// VMOVDQA: Move Aligned Double Quadword. +// VRSQRT14PD_BCST_Z: Compute Approximate Reciprocals of Square Roots of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VMOVDQA xmm xmm -// VMOVDQA m128 xmm -// VMOVDQA ymm ymm -// VMOVDQA m256 ymm -// VMOVDQA xmm m128 -// VMOVDQA ymm m256 -// Construct and append a VMOVDQA instruction to the active function. -func (c *Context) VMOVDQA(mxy, mxy1 operand.Op) { - if inst, err := x86.VMOVDQA(mxy, mxy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRT14PD.BCST.Z m64 k xmm +// VRSQRT14PD.BCST.Z m64 k ymm +// VRSQRT14PD.BCST.Z m64 k zmm +// Construct and append a VRSQRT14PD.BCST.Z instruction to the active function. +func (c *Context) VRSQRT14PD_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VRSQRT14PD_BCST_Z(m, k, xyz)) } -// VMOVDQA: Move Aligned Double Quadword. +// VRSQRT14PD_BCST_Z: Compute Approximate Reciprocals of Square Roots of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VMOVDQA xmm xmm -// VMOVDQA m128 xmm -// VMOVDQA ymm ymm -// VMOVDQA m256 ymm -// VMOVDQA xmm m128 -// VMOVDQA ymm m256 -// Construct and append a VMOVDQA instruction to the active function. +// VRSQRT14PD.BCST.Z m64 k xmm +// VRSQRT14PD.BCST.Z m64 k ymm +// VRSQRT14PD.BCST.Z m64 k zmm +// Construct and append a VRSQRT14PD.BCST.Z instruction to the active function. // Operates on the global context. -func VMOVDQA(mxy, mxy1 operand.Op) { ctx.VMOVDQA(mxy, mxy1) } +func VRSQRT14PD_BCST_Z(m, k, xyz operand.Op) { ctx.VRSQRT14PD_BCST_Z(m, k, xyz) } -// VMOVDQU: Move Unaligned Double Quadword. +// VRSQRT14PD_Z: Compute Approximate Reciprocals of Square Roots of Packed Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VMOVDQU xmm xmm -// VMOVDQU m128 xmm -// VMOVDQU ymm ymm -// VMOVDQU m256 ymm -// VMOVDQU xmm m128 -// VMOVDQU ymm m256 -// Construct and append a VMOVDQU instruction to the active function. -func (c *Context) VMOVDQU(mxy, mxy1 operand.Op) { - if inst, err := x86.VMOVDQU(mxy, mxy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRT14PD.Z m128 k xmm +// VRSQRT14PD.Z m256 k ymm +// VRSQRT14PD.Z xmm k xmm +// VRSQRT14PD.Z ymm k ymm +// VRSQRT14PD.Z m512 k zmm +// VRSQRT14PD.Z zmm k zmm +// Construct and append a VRSQRT14PD.Z instruction to the active function. +func (c *Context) VRSQRT14PD_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VRSQRT14PD_Z(mxyz, k, xyz)) } -// VMOVDQU: Move Unaligned Double Quadword. +// VRSQRT14PD_Z: Compute Approximate Reciprocals of Square Roots of Packed Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VMOVDQU xmm xmm -// VMOVDQU m128 xmm -// VMOVDQU ymm ymm -// VMOVDQU m256 ymm -// VMOVDQU xmm m128 -// VMOVDQU ymm m256 -// Construct and append a VMOVDQU instruction to the active function. +// VRSQRT14PD.Z m128 k xmm +// VRSQRT14PD.Z m256 k ymm +// VRSQRT14PD.Z xmm k xmm +// VRSQRT14PD.Z ymm k ymm +// VRSQRT14PD.Z m512 k zmm +// VRSQRT14PD.Z zmm k zmm +// Construct and append a VRSQRT14PD.Z instruction to the active function. // Operates on the global context. -func VMOVDQU(mxy, mxy1 operand.Op) { ctx.VMOVDQU(mxy, mxy1) } +func VRSQRT14PD_Z(mxyz, k, xyz operand.Op) { ctx.VRSQRT14PD_Z(mxyz, k, xyz) } -// VMOVHLPS: Move Packed Single-Precision Floating-Point Values High to Low. +// VRSQRT14PS: Compute Approximate Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values. // // Forms: // -// VMOVHLPS xmm xmm xmm -// Construct and append a VMOVHLPS instruction to the active function. -func (c *Context) VMOVHLPS(x, x1, x2 operand.Op) { - if inst, err := x86.VMOVHLPS(x, x1, x2); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRT14PS m128 k xmm +// VRSQRT14PS m128 xmm +// VRSQRT14PS m256 k ymm +// VRSQRT14PS m256 ymm +// VRSQRT14PS xmm k xmm +// VRSQRT14PS xmm xmm +// VRSQRT14PS ymm k ymm +// VRSQRT14PS ymm ymm +// VRSQRT14PS m512 k zmm +// VRSQRT14PS m512 zmm +// VRSQRT14PS zmm k zmm +// VRSQRT14PS zmm zmm +// Construct and append a VRSQRT14PS instruction to the active function. +func (c *Context) VRSQRT14PS(ops ...operand.Op) { + c.addinstruction(x86.VRSQRT14PS(ops...)) } -// VMOVHLPS: Move Packed Single-Precision Floating-Point Values High to Low. +// VRSQRT14PS: Compute Approximate Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values. // // Forms: // -// VMOVHLPS xmm xmm xmm -// Construct and append a VMOVHLPS instruction to the active function. +// VRSQRT14PS m128 k xmm +// VRSQRT14PS m128 xmm +// VRSQRT14PS m256 k ymm +// VRSQRT14PS m256 ymm +// VRSQRT14PS xmm k xmm +// VRSQRT14PS xmm xmm +// VRSQRT14PS ymm k ymm +// VRSQRT14PS ymm ymm +// VRSQRT14PS m512 k zmm +// VRSQRT14PS m512 zmm +// VRSQRT14PS zmm k zmm +// VRSQRT14PS zmm zmm +// Construct and append a VRSQRT14PS instruction to the active function. // Operates on the global context. -func VMOVHLPS(x, x1, x2 operand.Op) { ctx.VMOVHLPS(x, x1, x2) } +func VRSQRT14PS(ops ...operand.Op) { ctx.VRSQRT14PS(ops...) } -// VMOVHPD: Move High Packed Double-Precision Floating-Point Value. +// VRSQRT14PS_BCST: Compute Approximate Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values (Broadcast). // // Forms: // -// VMOVHPD xmm m64 -// VMOVHPD m64 xmm xmm -// Construct and append a VMOVHPD instruction to the active function. -func (c *Context) VMOVHPD(ops ...operand.Op) { - if inst, err := x86.VMOVHPD(ops...); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRT14PS.BCST m32 k xmm +// VRSQRT14PS.BCST m32 k ymm +// VRSQRT14PS.BCST m32 xmm +// VRSQRT14PS.BCST m32 ymm +// VRSQRT14PS.BCST m32 k zmm +// VRSQRT14PS.BCST m32 zmm +// Construct and append a VRSQRT14PS.BCST instruction to the active function. +func (c *Context) VRSQRT14PS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VRSQRT14PS_BCST(ops...)) } -// VMOVHPD: Move High Packed Double-Precision Floating-Point Value. +// VRSQRT14PS_BCST: Compute Approximate Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values (Broadcast). // // Forms: // -// VMOVHPD xmm m64 -// VMOVHPD m64 xmm xmm -// Construct and append a VMOVHPD instruction to the active function. +// VRSQRT14PS.BCST m32 k xmm +// VRSQRT14PS.BCST m32 k ymm +// VRSQRT14PS.BCST m32 xmm +// VRSQRT14PS.BCST m32 ymm +// VRSQRT14PS.BCST m32 k zmm +// VRSQRT14PS.BCST m32 zmm +// Construct and append a VRSQRT14PS.BCST instruction to the active function. // Operates on the global context. -func VMOVHPD(ops ...operand.Op) { ctx.VMOVHPD(ops...) } +func VRSQRT14PS_BCST(ops ...operand.Op) { ctx.VRSQRT14PS_BCST(ops...) } -// VMOVHPS: Move High Packed Single-Precision Floating-Point Values. +// VRSQRT14PS_BCST_Z: Compute Approximate Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VMOVHPS xmm m64 -// VMOVHPS m64 xmm xmm -// Construct and append a VMOVHPS instruction to the active function. -func (c *Context) VMOVHPS(ops ...operand.Op) { - if inst, err := x86.VMOVHPS(ops...); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRT14PS.BCST.Z m32 k xmm +// VRSQRT14PS.BCST.Z m32 k ymm +// VRSQRT14PS.BCST.Z m32 k zmm +// Construct and append a VRSQRT14PS.BCST.Z instruction to the active function. +func (c *Context) VRSQRT14PS_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VRSQRT14PS_BCST_Z(m, k, xyz)) } -// VMOVHPS: Move High Packed Single-Precision Floating-Point Values. +// VRSQRT14PS_BCST_Z: Compute Approximate Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VMOVHPS xmm m64 -// VMOVHPS m64 xmm xmm -// Construct and append a VMOVHPS instruction to the active function. +// VRSQRT14PS.BCST.Z m32 k xmm +// VRSQRT14PS.BCST.Z m32 k ymm +// VRSQRT14PS.BCST.Z m32 k zmm +// Construct and append a VRSQRT14PS.BCST.Z instruction to the active function. // Operates on the global context. -func VMOVHPS(ops ...operand.Op) { ctx.VMOVHPS(ops...) } +func VRSQRT14PS_BCST_Z(m, k, xyz operand.Op) { ctx.VRSQRT14PS_BCST_Z(m, k, xyz) } -// VMOVLHPS: Move Packed Single-Precision Floating-Point Values Low to High. +// VRSQRT14PS_Z: Compute Approximate Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VMOVLHPS xmm xmm xmm -// Construct and append a VMOVLHPS instruction to the active function. -func (c *Context) VMOVLHPS(x, x1, x2 operand.Op) { - if inst, err := x86.VMOVLHPS(x, x1, x2); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRT14PS.Z m128 k xmm +// VRSQRT14PS.Z m256 k ymm +// VRSQRT14PS.Z xmm k xmm +// VRSQRT14PS.Z ymm k ymm +// VRSQRT14PS.Z m512 k zmm +// VRSQRT14PS.Z zmm k zmm +// Construct and append a VRSQRT14PS.Z instruction to the active function. +func (c *Context) VRSQRT14PS_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VRSQRT14PS_Z(mxyz, k, xyz)) } -// VMOVLHPS: Move Packed Single-Precision Floating-Point Values Low to High. +// VRSQRT14PS_Z: Compute Approximate Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VMOVLHPS xmm xmm xmm -// Construct and append a VMOVLHPS instruction to the active function. +// VRSQRT14PS.Z m128 k xmm +// VRSQRT14PS.Z m256 k ymm +// VRSQRT14PS.Z xmm k xmm +// VRSQRT14PS.Z ymm k ymm +// VRSQRT14PS.Z m512 k zmm +// VRSQRT14PS.Z zmm k zmm +// Construct and append a VRSQRT14PS.Z instruction to the active function. // Operates on the global context. -func VMOVLHPS(x, x1, x2 operand.Op) { ctx.VMOVLHPS(x, x1, x2) } +func VRSQRT14PS_Z(mxyz, k, xyz operand.Op) { ctx.VRSQRT14PS_Z(mxyz, k, xyz) } -// VMOVLPD: Move Low Packed Double-Precision Floating-Point Value. +// VRSQRT14SD: Compute Approximate Reciprocal of a Square Root of a Scalar Double-Precision Floating-Point Value. // // Forms: // -// VMOVLPD xmm m64 -// VMOVLPD m64 xmm xmm -// Construct and append a VMOVLPD instruction to the active function. -func (c *Context) VMOVLPD(ops ...operand.Op) { - if inst, err := x86.VMOVLPD(ops...); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRT14SD m64 xmm k xmm +// VRSQRT14SD m64 xmm xmm +// VRSQRT14SD xmm xmm k xmm +// VRSQRT14SD xmm xmm xmm +// Construct and append a VRSQRT14SD instruction to the active function. +func (c *Context) VRSQRT14SD(ops ...operand.Op) { + c.addinstruction(x86.VRSQRT14SD(ops...)) } -// VMOVLPD: Move Low Packed Double-Precision Floating-Point Value. +// VRSQRT14SD: Compute Approximate Reciprocal of a Square Root of a Scalar Double-Precision Floating-Point Value. // // Forms: // -// VMOVLPD xmm m64 -// VMOVLPD m64 xmm xmm -// Construct and append a VMOVLPD instruction to the active function. +// VRSQRT14SD m64 xmm k xmm +// VRSQRT14SD m64 xmm xmm +// VRSQRT14SD xmm xmm k xmm +// VRSQRT14SD xmm xmm xmm +// Construct and append a VRSQRT14SD instruction to the active function. // Operates on the global context. -func VMOVLPD(ops ...operand.Op) { ctx.VMOVLPD(ops...) } +func VRSQRT14SD(ops ...operand.Op) { ctx.VRSQRT14SD(ops...) } -// VMOVLPS: Move Low Packed Single-Precision Floating-Point Values. +// VRSQRT14SD_Z: Compute Approximate Reciprocal of a Square Root of a Scalar Double-Precision Floating-Point Value (Zeroing Masking). // // Forms: // -// VMOVLPS xmm m64 -// VMOVLPS m64 xmm xmm -// Construct and append a VMOVLPS instruction to the active function. -func (c *Context) VMOVLPS(ops ...operand.Op) { - if inst, err := x86.VMOVLPS(ops...); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRT14SD.Z m64 xmm k xmm +// VRSQRT14SD.Z xmm xmm k xmm +// Construct and append a VRSQRT14SD.Z instruction to the active function. +func (c *Context) VRSQRT14SD_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VRSQRT14SD_Z(mx, x, k, x1)) } -// VMOVLPS: Move Low Packed Single-Precision Floating-Point Values. +// VRSQRT14SD_Z: Compute Approximate Reciprocal of a Square Root of a Scalar Double-Precision Floating-Point Value (Zeroing Masking). // // Forms: // -// VMOVLPS xmm m64 -// VMOVLPS m64 xmm xmm -// Construct and append a VMOVLPS instruction to the active function. +// VRSQRT14SD.Z m64 xmm k xmm +// VRSQRT14SD.Z xmm xmm k xmm +// Construct and append a VRSQRT14SD.Z instruction to the active function. // Operates on the global context. -func VMOVLPS(ops ...operand.Op) { ctx.VMOVLPS(ops...) } +func VRSQRT14SD_Z(mx, x, k, x1 operand.Op) { ctx.VRSQRT14SD_Z(mx, x, k, x1) } -// VMOVMSKPD: Extract Packed Double-Precision Floating-Point Sign Mask. +// VRSQRT14SS: Compute Approximate Reciprocal of a Square Root of a Scalar Single-Precision Floating-Point Value. // // Forms: // -// VMOVMSKPD xmm r32 -// VMOVMSKPD ymm r32 -// Construct and append a VMOVMSKPD instruction to the active function. -func (c *Context) VMOVMSKPD(xy, r operand.Op) { - if inst, err := x86.VMOVMSKPD(xy, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRT14SS m32 xmm k xmm +// VRSQRT14SS m32 xmm xmm +// VRSQRT14SS xmm xmm k xmm +// VRSQRT14SS xmm xmm xmm +// Construct and append a VRSQRT14SS instruction to the active function. +func (c *Context) VRSQRT14SS(ops ...operand.Op) { + c.addinstruction(x86.VRSQRT14SS(ops...)) } -// VMOVMSKPD: Extract Packed Double-Precision Floating-Point Sign Mask. +// VRSQRT14SS: Compute Approximate Reciprocal of a Square Root of a Scalar Single-Precision Floating-Point Value. // // Forms: // -// VMOVMSKPD xmm r32 -// VMOVMSKPD ymm r32 -// Construct and append a VMOVMSKPD instruction to the active function. +// VRSQRT14SS m32 xmm k xmm +// VRSQRT14SS m32 xmm xmm +// VRSQRT14SS xmm xmm k xmm +// VRSQRT14SS xmm xmm xmm +// Construct and append a VRSQRT14SS instruction to the active function. // Operates on the global context. -func VMOVMSKPD(xy, r operand.Op) { ctx.VMOVMSKPD(xy, r) } +func VRSQRT14SS(ops ...operand.Op) { ctx.VRSQRT14SS(ops...) } -// VMOVMSKPS: Extract Packed Single-Precision Floating-Point Sign Mask. +// VRSQRT14SS_Z: Compute Approximate Reciprocal of a Square Root of a Scalar Single-Precision Floating-Point Value (Zeroing Masking). // // Forms: // -// VMOVMSKPS xmm r32 -// VMOVMSKPS ymm r32 -// Construct and append a VMOVMSKPS instruction to the active function. -func (c *Context) VMOVMSKPS(xy, r operand.Op) { - if inst, err := x86.VMOVMSKPS(xy, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRT14SS.Z m32 xmm k xmm +// VRSQRT14SS.Z xmm xmm k xmm +// Construct and append a VRSQRT14SS.Z instruction to the active function. +func (c *Context) VRSQRT14SS_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VRSQRT14SS_Z(mx, x, k, x1)) } -// VMOVMSKPS: Extract Packed Single-Precision Floating-Point Sign Mask. +// VRSQRT14SS_Z: Compute Approximate Reciprocal of a Square Root of a Scalar Single-Precision Floating-Point Value (Zeroing Masking). // // Forms: // -// VMOVMSKPS xmm r32 -// VMOVMSKPS ymm r32 -// Construct and append a VMOVMSKPS instruction to the active function. +// VRSQRT14SS.Z m32 xmm k xmm +// VRSQRT14SS.Z xmm xmm k xmm +// Construct and append a VRSQRT14SS.Z instruction to the active function. // Operates on the global context. -func VMOVMSKPS(xy, r operand.Op) { ctx.VMOVMSKPS(xy, r) } +func VRSQRT14SS_Z(mx, x, k, x1 operand.Op) { ctx.VRSQRT14SS_Z(mx, x, k, x1) } -// VMOVNTDQ: Store Double Quadword Using Non-Temporal Hint. +// VRSQRT28PD: Approximation to the Reciprocal Square Root of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error. // // Forms: // -// VMOVNTDQ xmm m128 -// VMOVNTDQ ymm m256 -// Construct and append a VMOVNTDQ instruction to the active function. -func (c *Context) VMOVNTDQ(xy, m operand.Op) { - if inst, err := x86.VMOVNTDQ(xy, m); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRT28PD m512 k zmm +// VRSQRT28PD m512 zmm +// VRSQRT28PD zmm k zmm +// VRSQRT28PD zmm zmm +// Construct and append a VRSQRT28PD instruction to the active function. +func (c *Context) VRSQRT28PD(ops ...operand.Op) { + c.addinstruction(x86.VRSQRT28PD(ops...)) } -// VMOVNTDQ: Store Double Quadword Using Non-Temporal Hint. +// VRSQRT28PD: Approximation to the Reciprocal Square Root of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error. // // Forms: // -// VMOVNTDQ xmm m128 -// VMOVNTDQ ymm m256 -// Construct and append a VMOVNTDQ instruction to the active function. +// VRSQRT28PD m512 k zmm +// VRSQRT28PD m512 zmm +// VRSQRT28PD zmm k zmm +// VRSQRT28PD zmm zmm +// Construct and append a VRSQRT28PD instruction to the active function. // Operates on the global context. -func VMOVNTDQ(xy, m operand.Op) { ctx.VMOVNTDQ(xy, m) } +func VRSQRT28PD(ops ...operand.Op) { ctx.VRSQRT28PD(ops...) } -// VMOVNTDQA: Load Double Quadword Non-Temporal Aligned Hint. +// VRSQRT28PD_BCST: Approximation to the Reciprocal Square Root of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Broadcast). // // Forms: // -// VMOVNTDQA m128 xmm -// VMOVNTDQA m256 ymm -// Construct and append a VMOVNTDQA instruction to the active function. -func (c *Context) VMOVNTDQA(m, xy operand.Op) { - if inst, err := x86.VMOVNTDQA(m, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRT28PD.BCST m64 k zmm +// VRSQRT28PD.BCST m64 zmm +// Construct and append a VRSQRT28PD.BCST instruction to the active function. +func (c *Context) VRSQRT28PD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VRSQRT28PD_BCST(ops...)) } -// VMOVNTDQA: Load Double Quadword Non-Temporal Aligned Hint. +// VRSQRT28PD_BCST: Approximation to the Reciprocal Square Root of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Broadcast). // // Forms: // -// VMOVNTDQA m128 xmm -// VMOVNTDQA m256 ymm -// Construct and append a VMOVNTDQA instruction to the active function. +// VRSQRT28PD.BCST m64 k zmm +// VRSQRT28PD.BCST m64 zmm +// Construct and append a VRSQRT28PD.BCST instruction to the active function. // Operates on the global context. -func VMOVNTDQA(m, xy operand.Op) { ctx.VMOVNTDQA(m, xy) } +func VRSQRT28PD_BCST(ops ...operand.Op) { ctx.VRSQRT28PD_BCST(ops...) } -// VMOVNTPD: Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint. +// VRSQRT28PD_BCST_Z: Approximation to the Reciprocal Square Root of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Broadcast, Zeroing Masking). // // Forms: // -// VMOVNTPD xmm m128 -// VMOVNTPD ymm m256 -// Construct and append a VMOVNTPD instruction to the active function. -func (c *Context) VMOVNTPD(xy, m operand.Op) { - if inst, err := x86.VMOVNTPD(xy, m); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRT28PD.BCST.Z m64 k zmm +// Construct and append a VRSQRT28PD.BCST.Z instruction to the active function. +func (c *Context) VRSQRT28PD_BCST_Z(m, k, z operand.Op) { + c.addinstruction(x86.VRSQRT28PD_BCST_Z(m, k, z)) } -// VMOVNTPD: Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint. +// VRSQRT28PD_BCST_Z: Approximation to the Reciprocal Square Root of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Broadcast, Zeroing Masking). // // Forms: // -// VMOVNTPD xmm m128 -// VMOVNTPD ymm m256 -// Construct and append a VMOVNTPD instruction to the active function. +// VRSQRT28PD.BCST.Z m64 k zmm +// Construct and append a VRSQRT28PD.BCST.Z instruction to the active function. // Operates on the global context. -func VMOVNTPD(xy, m operand.Op) { ctx.VMOVNTPD(xy, m) } +func VRSQRT28PD_BCST_Z(m, k, z operand.Op) { ctx.VRSQRT28PD_BCST_Z(m, k, z) } -// VMOVNTPS: Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint. +// VRSQRT28PD_SAE: Approximation to the Reciprocal Square Root of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Suppress All Exceptions). // // Forms: // -// VMOVNTPS xmm m128 -// VMOVNTPS ymm m256 -// Construct and append a VMOVNTPS instruction to the active function. -func (c *Context) VMOVNTPS(xy, m operand.Op) { - if inst, err := x86.VMOVNTPS(xy, m); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRT28PD.SAE zmm k zmm +// VRSQRT28PD.SAE zmm zmm +// Construct and append a VRSQRT28PD.SAE instruction to the active function. +func (c *Context) VRSQRT28PD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VRSQRT28PD_SAE(ops...)) } -// VMOVNTPS: Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint. +// VRSQRT28PD_SAE: Approximation to the Reciprocal Square Root of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Suppress All Exceptions). // // Forms: // -// VMOVNTPS xmm m128 -// VMOVNTPS ymm m256 -// Construct and append a VMOVNTPS instruction to the active function. +// VRSQRT28PD.SAE zmm k zmm +// VRSQRT28PD.SAE zmm zmm +// Construct and append a VRSQRT28PD.SAE instruction to the active function. // Operates on the global context. -func VMOVNTPS(xy, m operand.Op) { ctx.VMOVNTPS(xy, m) } +func VRSQRT28PD_SAE(ops ...operand.Op) { ctx.VRSQRT28PD_SAE(ops...) } -// VMOVQ: Move Quadword. +// VRSQRT28PD_SAE_Z: Approximation to the Reciprocal Square Root of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VMOVQ xmm r64 -// VMOVQ r64 xmm -// VMOVQ xmm xmm -// VMOVQ m64 xmm -// VMOVQ xmm m64 -// Construct and append a VMOVQ instruction to the active function. -func (c *Context) VMOVQ(mrx, mrx1 operand.Op) { - if inst, err := x86.VMOVQ(mrx, mrx1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRT28PD.SAE.Z zmm k zmm +// Construct and append a VRSQRT28PD.SAE.Z instruction to the active function. +func (c *Context) VRSQRT28PD_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VRSQRT28PD_SAE_Z(z, k, z1)) } -// VMOVQ: Move Quadword. +// VRSQRT28PD_SAE_Z: Approximation to the Reciprocal Square Root of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VMOVQ xmm r64 -// VMOVQ r64 xmm -// VMOVQ xmm xmm -// VMOVQ m64 xmm -// VMOVQ xmm m64 -// Construct and append a VMOVQ instruction to the active function. +// VRSQRT28PD.SAE.Z zmm k zmm +// Construct and append a VRSQRT28PD.SAE.Z instruction to the active function. // Operates on the global context. -func VMOVQ(mrx, mrx1 operand.Op) { ctx.VMOVQ(mrx, mrx1) } +func VRSQRT28PD_SAE_Z(z, k, z1 operand.Op) { ctx.VRSQRT28PD_SAE_Z(z, k, z1) } -// VMOVSD: Move Scalar Double-Precision Floating-Point Value. +// VRSQRT28PD_Z: Approximation to the Reciprocal Square Root of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Zeroing Masking). // // Forms: // -// VMOVSD m64 xmm -// VMOVSD xmm m64 -// VMOVSD xmm xmm xmm -// Construct and append a VMOVSD instruction to the active function. -func (c *Context) VMOVSD(ops ...operand.Op) { - if inst, err := x86.VMOVSD(ops...); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRT28PD.Z m512 k zmm +// VRSQRT28PD.Z zmm k zmm +// Construct and append a VRSQRT28PD.Z instruction to the active function. +func (c *Context) VRSQRT28PD_Z(mz, k, z operand.Op) { + c.addinstruction(x86.VRSQRT28PD_Z(mz, k, z)) } -// VMOVSD: Move Scalar Double-Precision Floating-Point Value. +// VRSQRT28PD_Z: Approximation to the Reciprocal Square Root of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Zeroing Masking). // // Forms: // -// VMOVSD m64 xmm -// VMOVSD xmm m64 -// VMOVSD xmm xmm xmm -// Construct and append a VMOVSD instruction to the active function. +// VRSQRT28PD.Z m512 k zmm +// VRSQRT28PD.Z zmm k zmm +// Construct and append a VRSQRT28PD.Z instruction to the active function. // Operates on the global context. -func VMOVSD(ops ...operand.Op) { ctx.VMOVSD(ops...) } +func VRSQRT28PD_Z(mz, k, z operand.Op) { ctx.VRSQRT28PD_Z(mz, k, z) } -// VMOVSHDUP: Move Packed Single-FP High and Duplicate. +// VRSQRT28PS: Approximation to the Reciprocal Square Root of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error. // // Forms: // -// VMOVSHDUP xmm xmm -// VMOVSHDUP m128 xmm -// VMOVSHDUP ymm ymm -// VMOVSHDUP m256 ymm -// Construct and append a VMOVSHDUP instruction to the active function. -func (c *Context) VMOVSHDUP(mxy, xy operand.Op) { - if inst, err := x86.VMOVSHDUP(mxy, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRT28PS m512 k zmm +// VRSQRT28PS m512 zmm +// VRSQRT28PS zmm k zmm +// VRSQRT28PS zmm zmm +// Construct and append a VRSQRT28PS instruction to the active function. +func (c *Context) VRSQRT28PS(ops ...operand.Op) { + c.addinstruction(x86.VRSQRT28PS(ops...)) } -// VMOVSHDUP: Move Packed Single-FP High and Duplicate. +// VRSQRT28PS: Approximation to the Reciprocal Square Root of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error. // // Forms: // -// VMOVSHDUP xmm xmm -// VMOVSHDUP m128 xmm -// VMOVSHDUP ymm ymm -// VMOVSHDUP m256 ymm -// Construct and append a VMOVSHDUP instruction to the active function. +// VRSQRT28PS m512 k zmm +// VRSQRT28PS m512 zmm +// VRSQRT28PS zmm k zmm +// VRSQRT28PS zmm zmm +// Construct and append a VRSQRT28PS instruction to the active function. // Operates on the global context. -func VMOVSHDUP(mxy, xy operand.Op) { ctx.VMOVSHDUP(mxy, xy) } +func VRSQRT28PS(ops ...operand.Op) { ctx.VRSQRT28PS(ops...) } -// VMOVSLDUP: Move Packed Single-FP Low and Duplicate. +// VRSQRT28PS_BCST: Approximation to the Reciprocal Square Root of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Broadcast). // // Forms: // -// VMOVSLDUP xmm xmm -// VMOVSLDUP m128 xmm -// VMOVSLDUP ymm ymm -// VMOVSLDUP m256 ymm -// Construct and append a VMOVSLDUP instruction to the active function. -func (c *Context) VMOVSLDUP(mxy, xy operand.Op) { - if inst, err := x86.VMOVSLDUP(mxy, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRT28PS.BCST m32 k zmm +// VRSQRT28PS.BCST m32 zmm +// Construct and append a VRSQRT28PS.BCST instruction to the active function. +func (c *Context) VRSQRT28PS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VRSQRT28PS_BCST(ops...)) } -// VMOVSLDUP: Move Packed Single-FP Low and Duplicate. +// VRSQRT28PS_BCST: Approximation to the Reciprocal Square Root of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Broadcast). // // Forms: // -// VMOVSLDUP xmm xmm -// VMOVSLDUP m128 xmm -// VMOVSLDUP ymm ymm -// VMOVSLDUP m256 ymm -// Construct and append a VMOVSLDUP instruction to the active function. +// VRSQRT28PS.BCST m32 k zmm +// VRSQRT28PS.BCST m32 zmm +// Construct and append a VRSQRT28PS.BCST instruction to the active function. +// Operates on the global context. +func VRSQRT28PS_BCST(ops ...operand.Op) { ctx.VRSQRT28PS_BCST(ops...) } + +// VRSQRT28PS_BCST_Z: Approximation to the Reciprocal Square Root of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Broadcast, Zeroing Masking). +// +// Forms: +// +// VRSQRT28PS.BCST.Z m32 k zmm +// Construct and append a VRSQRT28PS.BCST.Z instruction to the active function. +func (c *Context) VRSQRT28PS_BCST_Z(m, k, z operand.Op) { + c.addinstruction(x86.VRSQRT28PS_BCST_Z(m, k, z)) +} + +// VRSQRT28PS_BCST_Z: Approximation to the Reciprocal Square Root of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Broadcast, Zeroing Masking). +// +// Forms: +// +// VRSQRT28PS.BCST.Z m32 k zmm +// Construct and append a VRSQRT28PS.BCST.Z instruction to the active function. // Operates on the global context. -func VMOVSLDUP(mxy, xy operand.Op) { ctx.VMOVSLDUP(mxy, xy) } +func VRSQRT28PS_BCST_Z(m, k, z operand.Op) { ctx.VRSQRT28PS_BCST_Z(m, k, z) } -// VMOVSS: Move Scalar Single-Precision Floating-Point Values. +// VRSQRT28PS_SAE: Approximation to the Reciprocal Square Root of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Suppress All Exceptions). // // Forms: // -// VMOVSS m32 xmm -// VMOVSS xmm m32 -// VMOVSS xmm xmm xmm -// Construct and append a VMOVSS instruction to the active function. -func (c *Context) VMOVSS(ops ...operand.Op) { - if inst, err := x86.VMOVSS(ops...); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRT28PS.SAE zmm k zmm +// VRSQRT28PS.SAE zmm zmm +// Construct and append a VRSQRT28PS.SAE instruction to the active function. +func (c *Context) VRSQRT28PS_SAE(ops ...operand.Op) { + c.addinstruction(x86.VRSQRT28PS_SAE(ops...)) } -// VMOVSS: Move Scalar Single-Precision Floating-Point Values. +// VRSQRT28PS_SAE: Approximation to the Reciprocal Square Root of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Suppress All Exceptions). // // Forms: // -// VMOVSS m32 xmm -// VMOVSS xmm m32 -// VMOVSS xmm xmm xmm -// Construct and append a VMOVSS instruction to the active function. +// VRSQRT28PS.SAE zmm k zmm +// VRSQRT28PS.SAE zmm zmm +// Construct and append a VRSQRT28PS.SAE instruction to the active function. // Operates on the global context. -func VMOVSS(ops ...operand.Op) { ctx.VMOVSS(ops...) } +func VRSQRT28PS_SAE(ops ...operand.Op) { ctx.VRSQRT28PS_SAE(ops...) } -// VMOVUPD: Move Unaligned Packed Double-Precision Floating-Point Values. +// VRSQRT28PS_SAE_Z: Approximation to the Reciprocal Square Root of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VMOVUPD xmm xmm -// VMOVUPD m128 xmm -// VMOVUPD ymm ymm -// VMOVUPD m256 ymm -// VMOVUPD xmm m128 -// VMOVUPD ymm m256 -// Construct and append a VMOVUPD instruction to the active function. -func (c *Context) VMOVUPD(mxy, mxy1 operand.Op) { - if inst, err := x86.VMOVUPD(mxy, mxy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRT28PS.SAE.Z zmm k zmm +// Construct and append a VRSQRT28PS.SAE.Z instruction to the active function. +func (c *Context) VRSQRT28PS_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VRSQRT28PS_SAE_Z(z, k, z1)) } -// VMOVUPD: Move Unaligned Packed Double-Precision Floating-Point Values. +// VRSQRT28PS_SAE_Z: Approximation to the Reciprocal Square Root of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VMOVUPD xmm xmm -// VMOVUPD m128 xmm -// VMOVUPD ymm ymm -// VMOVUPD m256 ymm -// VMOVUPD xmm m128 -// VMOVUPD ymm m256 -// Construct and append a VMOVUPD instruction to the active function. +// VRSQRT28PS.SAE.Z zmm k zmm +// Construct and append a VRSQRT28PS.SAE.Z instruction to the active function. // Operates on the global context. -func VMOVUPD(mxy, mxy1 operand.Op) { ctx.VMOVUPD(mxy, mxy1) } +func VRSQRT28PS_SAE_Z(z, k, z1 operand.Op) { ctx.VRSQRT28PS_SAE_Z(z, k, z1) } -// VMOVUPS: Move Unaligned Packed Single-Precision Floating-Point Values. +// VRSQRT28PS_Z: Approximation to the Reciprocal Square Root of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Zeroing Masking). // // Forms: // -// VMOVUPS xmm xmm -// VMOVUPS m128 xmm -// VMOVUPS ymm ymm -// VMOVUPS m256 ymm -// VMOVUPS xmm m128 -// VMOVUPS ymm m256 -// Construct and append a VMOVUPS instruction to the active function. -func (c *Context) VMOVUPS(mxy, mxy1 operand.Op) { - if inst, err := x86.VMOVUPS(mxy, mxy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRT28PS.Z m512 k zmm +// VRSQRT28PS.Z zmm k zmm +// Construct and append a VRSQRT28PS.Z instruction to the active function. +func (c *Context) VRSQRT28PS_Z(mz, k, z operand.Op) { + c.addinstruction(x86.VRSQRT28PS_Z(mz, k, z)) } -// VMOVUPS: Move Unaligned Packed Single-Precision Floating-Point Values. +// VRSQRT28PS_Z: Approximation to the Reciprocal Square Root of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Zeroing Masking). // // Forms: // -// VMOVUPS xmm xmm -// VMOVUPS m128 xmm -// VMOVUPS ymm ymm -// VMOVUPS m256 ymm -// VMOVUPS xmm m128 -// VMOVUPS ymm m256 -// Construct and append a VMOVUPS instruction to the active function. +// VRSQRT28PS.Z m512 k zmm +// VRSQRT28PS.Z zmm k zmm +// Construct and append a VRSQRT28PS.Z instruction to the active function. // Operates on the global context. -func VMOVUPS(mxy, mxy1 operand.Op) { ctx.VMOVUPS(mxy, mxy1) } +func VRSQRT28PS_Z(mz, k, z operand.Op) { ctx.VRSQRT28PS_Z(mz, k, z) } -// VMPSADBW: Compute Multiple Packed Sums of Absolute Difference. +// VRSQRT28SD: Approximation to the Reciprocal Square Root of a Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error. // // Forms: // -// VMPSADBW imm8 xmm xmm xmm -// VMPSADBW imm8 m128 xmm xmm -// VMPSADBW imm8 ymm ymm ymm -// VMPSADBW imm8 m256 ymm ymm -// Construct and append a VMPSADBW instruction to the active function. -func (c *Context) VMPSADBW(i, mxy, xy, xy1 operand.Op) { - if inst, err := x86.VMPSADBW(i, mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRT28SD m64 xmm k xmm +// VRSQRT28SD m64 xmm xmm +// VRSQRT28SD xmm xmm k xmm +// VRSQRT28SD xmm xmm xmm +// Construct and append a VRSQRT28SD instruction to the active function. +func (c *Context) VRSQRT28SD(ops ...operand.Op) { + c.addinstruction(x86.VRSQRT28SD(ops...)) } -// VMPSADBW: Compute Multiple Packed Sums of Absolute Difference. +// VRSQRT28SD: Approximation to the Reciprocal Square Root of a Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error. // // Forms: // -// VMPSADBW imm8 xmm xmm xmm -// VMPSADBW imm8 m128 xmm xmm -// VMPSADBW imm8 ymm ymm ymm -// VMPSADBW imm8 m256 ymm ymm -// Construct and append a VMPSADBW instruction to the active function. +// VRSQRT28SD m64 xmm k xmm +// VRSQRT28SD m64 xmm xmm +// VRSQRT28SD xmm xmm k xmm +// VRSQRT28SD xmm xmm xmm +// Construct and append a VRSQRT28SD instruction to the active function. // Operates on the global context. -func VMPSADBW(i, mxy, xy, xy1 operand.Op) { ctx.VMPSADBW(i, mxy, xy, xy1) } +func VRSQRT28SD(ops ...operand.Op) { ctx.VRSQRT28SD(ops...) } -// VMULPD: Multiply Packed Double-Precision Floating-Point Values. +// VRSQRT28SD_SAE: Approximation to the Reciprocal Square Root of a Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Suppress All Exceptions). // // Forms: // -// VMULPD xmm xmm xmm -// VMULPD m128 xmm xmm -// VMULPD ymm ymm ymm -// VMULPD m256 ymm ymm -// Construct and append a VMULPD instruction to the active function. -func (c *Context) VMULPD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VMULPD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRT28SD.SAE xmm xmm k xmm +// VRSQRT28SD.SAE xmm xmm xmm +// Construct and append a VRSQRT28SD.SAE instruction to the active function. +func (c *Context) VRSQRT28SD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VRSQRT28SD_SAE(ops...)) } -// VMULPD: Multiply Packed Double-Precision Floating-Point Values. +// VRSQRT28SD_SAE: Approximation to the Reciprocal Square Root of a Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Suppress All Exceptions). // // Forms: // -// VMULPD xmm xmm xmm -// VMULPD m128 xmm xmm -// VMULPD ymm ymm ymm -// VMULPD m256 ymm ymm -// Construct and append a VMULPD instruction to the active function. +// VRSQRT28SD.SAE xmm xmm k xmm +// VRSQRT28SD.SAE xmm xmm xmm +// Construct and append a VRSQRT28SD.SAE instruction to the active function. // Operates on the global context. -func VMULPD(mxy, xy, xy1 operand.Op) { ctx.VMULPD(mxy, xy, xy1) } +func VRSQRT28SD_SAE(ops ...operand.Op) { ctx.VRSQRT28SD_SAE(ops...) } -// VMULPS: Multiply Packed Single-Precision Floating-Point Values. +// VRSQRT28SD_SAE_Z: Approximation to the Reciprocal Square Root of a Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VMULPS xmm xmm xmm -// VMULPS m128 xmm xmm -// VMULPS ymm ymm ymm -// VMULPS m256 ymm ymm -// Construct and append a VMULPS instruction to the active function. -func (c *Context) VMULPS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VMULPS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRT28SD.SAE.Z xmm xmm k xmm +// Construct and append a VRSQRT28SD.SAE.Z instruction to the active function. +func (c *Context) VRSQRT28SD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VRSQRT28SD_SAE_Z(x, x1, k, x2)) } -// VMULPS: Multiply Packed Single-Precision Floating-Point Values. +// VRSQRT28SD_SAE_Z: Approximation to the Reciprocal Square Root of a Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VMULPS xmm xmm xmm -// VMULPS m128 xmm xmm -// VMULPS ymm ymm ymm -// VMULPS m256 ymm ymm -// Construct and append a VMULPS instruction to the active function. +// VRSQRT28SD.SAE.Z xmm xmm k xmm +// Construct and append a VRSQRT28SD.SAE.Z instruction to the active function. // Operates on the global context. -func VMULPS(mxy, xy, xy1 operand.Op) { ctx.VMULPS(mxy, xy, xy1) } +func VRSQRT28SD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VRSQRT28SD_SAE_Z(x, x1, k, x2) } -// VMULSD: Multiply Scalar Double-Precision Floating-Point Values. +// VRSQRT28SD_Z: Approximation to the Reciprocal Square Root of a Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Zeroing Masking). // // Forms: // -// VMULSD xmm xmm xmm -// VMULSD m64 xmm xmm -// Construct and append a VMULSD instruction to the active function. -func (c *Context) VMULSD(mx, x, x1 operand.Op) { - if inst, err := x86.VMULSD(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRT28SD.Z m64 xmm k xmm +// VRSQRT28SD.Z xmm xmm k xmm +// Construct and append a VRSQRT28SD.Z instruction to the active function. +func (c *Context) VRSQRT28SD_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VRSQRT28SD_Z(mx, x, k, x1)) } -// VMULSD: Multiply Scalar Double-Precision Floating-Point Values. +// VRSQRT28SD_Z: Approximation to the Reciprocal Square Root of a Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Zeroing Masking). // // Forms: // -// VMULSD xmm xmm xmm -// VMULSD m64 xmm xmm -// Construct and append a VMULSD instruction to the active function. +// VRSQRT28SD.Z m64 xmm k xmm +// VRSQRT28SD.Z xmm xmm k xmm +// Construct and append a VRSQRT28SD.Z instruction to the active function. // Operates on the global context. -func VMULSD(mx, x, x1 operand.Op) { ctx.VMULSD(mx, x, x1) } +func VRSQRT28SD_Z(mx, x, k, x1 operand.Op) { ctx.VRSQRT28SD_Z(mx, x, k, x1) } -// VMULSS: Multiply Scalar Single-Precision Floating-Point Values. +// VRSQRT28SS: Approximation to the Reciprocal Square Root of a Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error. // // Forms: // -// VMULSS xmm xmm xmm -// VMULSS m32 xmm xmm -// Construct and append a VMULSS instruction to the active function. -func (c *Context) VMULSS(mx, x, x1 operand.Op) { - if inst, err := x86.VMULSS(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRT28SS m32 xmm k xmm +// VRSQRT28SS m32 xmm xmm +// VRSQRT28SS xmm xmm k xmm +// VRSQRT28SS xmm xmm xmm +// Construct and append a VRSQRT28SS instruction to the active function. +func (c *Context) VRSQRT28SS(ops ...operand.Op) { + c.addinstruction(x86.VRSQRT28SS(ops...)) } -// VMULSS: Multiply Scalar Single-Precision Floating-Point Values. +// VRSQRT28SS: Approximation to the Reciprocal Square Root of a Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error. // // Forms: // -// VMULSS xmm xmm xmm -// VMULSS m32 xmm xmm -// Construct and append a VMULSS instruction to the active function. +// VRSQRT28SS m32 xmm k xmm +// VRSQRT28SS m32 xmm xmm +// VRSQRT28SS xmm xmm k xmm +// VRSQRT28SS xmm xmm xmm +// Construct and append a VRSQRT28SS instruction to the active function. // Operates on the global context. -func VMULSS(mx, x, x1 operand.Op) { ctx.VMULSS(mx, x, x1) } +func VRSQRT28SS(ops ...operand.Op) { ctx.VRSQRT28SS(ops...) } -// VORPD: Bitwise Logical OR of Double-Precision Floating-Point Values. +// VRSQRT28SS_SAE: Approximation to the Reciprocal Square Root of a Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Suppress All Exceptions). // // Forms: // -// VORPD xmm xmm xmm -// VORPD m128 xmm xmm -// VORPD ymm ymm ymm -// VORPD m256 ymm ymm -// Construct and append a VORPD instruction to the active function. -func (c *Context) VORPD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VORPD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRT28SS.SAE xmm xmm k xmm +// VRSQRT28SS.SAE xmm xmm xmm +// Construct and append a VRSQRT28SS.SAE instruction to the active function. +func (c *Context) VRSQRT28SS_SAE(ops ...operand.Op) { + c.addinstruction(x86.VRSQRT28SS_SAE(ops...)) } -// VORPD: Bitwise Logical OR of Double-Precision Floating-Point Values. +// VRSQRT28SS_SAE: Approximation to the Reciprocal Square Root of a Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Suppress All Exceptions). // // Forms: // -// VORPD xmm xmm xmm -// VORPD m128 xmm xmm -// VORPD ymm ymm ymm -// VORPD m256 ymm ymm -// Construct and append a VORPD instruction to the active function. +// VRSQRT28SS.SAE xmm xmm k xmm +// VRSQRT28SS.SAE xmm xmm xmm +// Construct and append a VRSQRT28SS.SAE instruction to the active function. // Operates on the global context. -func VORPD(mxy, xy, xy1 operand.Op) { ctx.VORPD(mxy, xy, xy1) } +func VRSQRT28SS_SAE(ops ...operand.Op) { ctx.VRSQRT28SS_SAE(ops...) } -// VORPS: Bitwise Logical OR of Single-Precision Floating-Point Values. +// VRSQRT28SS_SAE_Z: Approximation to the Reciprocal Square Root of a Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VORPS xmm xmm xmm -// VORPS m128 xmm xmm -// VORPS ymm ymm ymm -// VORPS m256 ymm ymm -// Construct and append a VORPS instruction to the active function. -func (c *Context) VORPS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VORPS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRT28SS.SAE.Z xmm xmm k xmm +// Construct and append a VRSQRT28SS.SAE.Z instruction to the active function. +func (c *Context) VRSQRT28SS_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VRSQRT28SS_SAE_Z(x, x1, k, x2)) } -// VORPS: Bitwise Logical OR of Single-Precision Floating-Point Values. +// VRSQRT28SS_SAE_Z: Approximation to the Reciprocal Square Root of a Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VORPS xmm xmm xmm -// VORPS m128 xmm xmm -// VORPS ymm ymm ymm -// VORPS m256 ymm ymm -// Construct and append a VORPS instruction to the active function. +// VRSQRT28SS.SAE.Z xmm xmm k xmm +// Construct and append a VRSQRT28SS.SAE.Z instruction to the active function. // Operates on the global context. -func VORPS(mxy, xy, xy1 operand.Op) { ctx.VORPS(mxy, xy, xy1) } +func VRSQRT28SS_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VRSQRT28SS_SAE_Z(x, x1, k, x2) } -// VPABSB: Packed Absolute Value of Byte Integers. +// VRSQRT28SS_Z: Approximation to the Reciprocal Square Root of a Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Zeroing Masking). // // Forms: // -// VPABSB xmm xmm -// VPABSB m128 xmm -// VPABSB ymm ymm -// VPABSB m256 ymm -// Construct and append a VPABSB instruction to the active function. -func (c *Context) VPABSB(mxy, xy operand.Op) { - if inst, err := x86.VPABSB(mxy, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRT28SS.Z m32 xmm k xmm +// VRSQRT28SS.Z xmm xmm k xmm +// Construct and append a VRSQRT28SS.Z instruction to the active function. +func (c *Context) VRSQRT28SS_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VRSQRT28SS_Z(mx, x, k, x1)) } -// VPABSB: Packed Absolute Value of Byte Integers. +// VRSQRT28SS_Z: Approximation to the Reciprocal Square Root of a Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Zeroing Masking). // // Forms: // -// VPABSB xmm xmm -// VPABSB m128 xmm -// VPABSB ymm ymm -// VPABSB m256 ymm -// Construct and append a VPABSB instruction to the active function. +// VRSQRT28SS.Z m32 xmm k xmm +// VRSQRT28SS.Z xmm xmm k xmm +// Construct and append a VRSQRT28SS.Z instruction to the active function. // Operates on the global context. -func VPABSB(mxy, xy operand.Op) { ctx.VPABSB(mxy, xy) } +func VRSQRT28SS_Z(mx, x, k, x1 operand.Op) { ctx.VRSQRT28SS_Z(mx, x, k, x1) } -// VPABSD: Packed Absolute Value of Doubleword Integers. +// VRSQRTPS: Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values. // // Forms: // -// VPABSD xmm xmm -// VPABSD m128 xmm -// VPABSD ymm ymm -// VPABSD m256 ymm -// Construct and append a VPABSD instruction to the active function. -func (c *Context) VPABSD(mxy, xy operand.Op) { - if inst, err := x86.VPABSD(mxy, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRTPS m128 xmm +// VRSQRTPS m256 ymm +// VRSQRTPS xmm xmm +// VRSQRTPS ymm ymm +// Construct and append a VRSQRTPS instruction to the active function. +func (c *Context) VRSQRTPS(mxy, xy operand.Op) { + c.addinstruction(x86.VRSQRTPS(mxy, xy)) } -// VPABSD: Packed Absolute Value of Doubleword Integers. +// VRSQRTPS: Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values. // // Forms: // -// VPABSD xmm xmm -// VPABSD m128 xmm -// VPABSD ymm ymm -// VPABSD m256 ymm -// Construct and append a VPABSD instruction to the active function. +// VRSQRTPS m128 xmm +// VRSQRTPS m256 ymm +// VRSQRTPS xmm xmm +// VRSQRTPS ymm ymm +// Construct and append a VRSQRTPS instruction to the active function. // Operates on the global context. -func VPABSD(mxy, xy operand.Op) { ctx.VPABSD(mxy, xy) } +func VRSQRTPS(mxy, xy operand.Op) { ctx.VRSQRTPS(mxy, xy) } -// VPABSW: Packed Absolute Value of Word Integers. +// VRSQRTSS: Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value. // // Forms: // -// VPABSW xmm xmm -// VPABSW m128 xmm -// VPABSW ymm ymm -// VPABSW m256 ymm -// Construct and append a VPABSW instruction to the active function. -func (c *Context) VPABSW(mxy, xy operand.Op) { - if inst, err := x86.VPABSW(mxy, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VRSQRTSS m32 xmm xmm +// VRSQRTSS xmm xmm xmm +// Construct and append a VRSQRTSS instruction to the active function. +func (c *Context) VRSQRTSS(mx, x, x1 operand.Op) { + c.addinstruction(x86.VRSQRTSS(mx, x, x1)) } -// VPABSW: Packed Absolute Value of Word Integers. +// VRSQRTSS: Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value. // // Forms: // -// VPABSW xmm xmm -// VPABSW m128 xmm -// VPABSW ymm ymm -// VPABSW m256 ymm -// Construct and append a VPABSW instruction to the active function. +// VRSQRTSS m32 xmm xmm +// VRSQRTSS xmm xmm xmm +// Construct and append a VRSQRTSS instruction to the active function. // Operates on the global context. -func VPABSW(mxy, xy operand.Op) { ctx.VPABSW(mxy, xy) } +func VRSQRTSS(mx, x, x1 operand.Op) { ctx.VRSQRTSS(mx, x, x1) } -// VPACKSSDW: Pack Doublewords into Words with Signed Saturation. +// VSCALEFPD: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values. // // Forms: // -// VPACKSSDW xmm xmm xmm -// VPACKSSDW m128 xmm xmm -// VPACKSSDW ymm ymm ymm -// VPACKSSDW m256 ymm ymm -// Construct and append a VPACKSSDW instruction to the active function. -func (c *Context) VPACKSSDW(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPACKSSDW(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFPD m128 xmm k xmm +// VSCALEFPD m128 xmm xmm +// VSCALEFPD m256 ymm k ymm +// VSCALEFPD m256 ymm ymm +// VSCALEFPD xmm xmm k xmm +// VSCALEFPD xmm xmm xmm +// VSCALEFPD ymm ymm k ymm +// VSCALEFPD ymm ymm ymm +// VSCALEFPD m512 zmm k zmm +// VSCALEFPD m512 zmm zmm +// VSCALEFPD zmm zmm k zmm +// VSCALEFPD zmm zmm zmm +// Construct and append a VSCALEFPD instruction to the active function. +func (c *Context) VSCALEFPD(ops ...operand.Op) { + c.addinstruction(x86.VSCALEFPD(ops...)) } -// VPACKSSDW: Pack Doublewords into Words with Signed Saturation. +// VSCALEFPD: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values. // // Forms: // -// VPACKSSDW xmm xmm xmm -// VPACKSSDW m128 xmm xmm -// VPACKSSDW ymm ymm ymm -// VPACKSSDW m256 ymm ymm -// Construct and append a VPACKSSDW instruction to the active function. +// VSCALEFPD m128 xmm k xmm +// VSCALEFPD m128 xmm xmm +// VSCALEFPD m256 ymm k ymm +// VSCALEFPD m256 ymm ymm +// VSCALEFPD xmm xmm k xmm +// VSCALEFPD xmm xmm xmm +// VSCALEFPD ymm ymm k ymm +// VSCALEFPD ymm ymm ymm +// VSCALEFPD m512 zmm k zmm +// VSCALEFPD m512 zmm zmm +// VSCALEFPD zmm zmm k zmm +// VSCALEFPD zmm zmm zmm +// Construct and append a VSCALEFPD instruction to the active function. // Operates on the global context. -func VPACKSSDW(mxy, xy, xy1 operand.Op) { ctx.VPACKSSDW(mxy, xy, xy1) } +func VSCALEFPD(ops ...operand.Op) { ctx.VSCALEFPD(ops...) } -// VPACKSSWB: Pack Words into Bytes with Signed Saturation. +// VSCALEFPD_BCST: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Broadcast). // // Forms: // -// VPACKSSWB xmm xmm xmm -// VPACKSSWB m128 xmm xmm -// VPACKSSWB ymm ymm ymm -// VPACKSSWB m256 ymm ymm -// Construct and append a VPACKSSWB instruction to the active function. -func (c *Context) VPACKSSWB(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPACKSSWB(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFPD.BCST m64 xmm k xmm +// VSCALEFPD.BCST m64 xmm xmm +// VSCALEFPD.BCST m64 ymm k ymm +// VSCALEFPD.BCST m64 ymm ymm +// VSCALEFPD.BCST m64 zmm k zmm +// VSCALEFPD.BCST m64 zmm zmm +// Construct and append a VSCALEFPD.BCST instruction to the active function. +func (c *Context) VSCALEFPD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VSCALEFPD_BCST(ops...)) } -// VPACKSSWB: Pack Words into Bytes with Signed Saturation. +// VSCALEFPD_BCST: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Broadcast). // // Forms: // -// VPACKSSWB xmm xmm xmm -// VPACKSSWB m128 xmm xmm -// VPACKSSWB ymm ymm ymm -// VPACKSSWB m256 ymm ymm -// Construct and append a VPACKSSWB instruction to the active function. +// VSCALEFPD.BCST m64 xmm k xmm +// VSCALEFPD.BCST m64 xmm xmm +// VSCALEFPD.BCST m64 ymm k ymm +// VSCALEFPD.BCST m64 ymm ymm +// VSCALEFPD.BCST m64 zmm k zmm +// VSCALEFPD.BCST m64 zmm zmm +// Construct and append a VSCALEFPD.BCST instruction to the active function. // Operates on the global context. -func VPACKSSWB(mxy, xy, xy1 operand.Op) { ctx.VPACKSSWB(mxy, xy, xy1) } +func VSCALEFPD_BCST(ops ...operand.Op) { ctx.VSCALEFPD_BCST(ops...) } -// VPACKUSDW: Pack Doublewords into Words with Unsigned Saturation. +// VSCALEFPD_BCST_Z: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VPACKUSDW xmm xmm xmm -// VPACKUSDW m128 xmm xmm -// VPACKUSDW ymm ymm ymm -// VPACKUSDW m256 ymm ymm -// Construct and append a VPACKUSDW instruction to the active function. -func (c *Context) VPACKUSDW(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPACKUSDW(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFPD.BCST.Z m64 xmm k xmm +// VSCALEFPD.BCST.Z m64 ymm k ymm +// VSCALEFPD.BCST.Z m64 zmm k zmm +// Construct and append a VSCALEFPD.BCST.Z instruction to the active function. +func (c *Context) VSCALEFPD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VSCALEFPD_BCST_Z(m, xyz, k, xyz1)) } -// VPACKUSDW: Pack Doublewords into Words with Unsigned Saturation. +// VSCALEFPD_BCST_Z: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VPACKUSDW xmm xmm xmm -// VPACKUSDW m128 xmm xmm -// VPACKUSDW ymm ymm ymm -// VPACKUSDW m256 ymm ymm -// Construct and append a VPACKUSDW instruction to the active function. +// VSCALEFPD.BCST.Z m64 xmm k xmm +// VSCALEFPD.BCST.Z m64 ymm k ymm +// VSCALEFPD.BCST.Z m64 zmm k zmm +// Construct and append a VSCALEFPD.BCST.Z instruction to the active function. // Operates on the global context. -func VPACKUSDW(mxy, xy, xy1 operand.Op) { ctx.VPACKUSDW(mxy, xy, xy1) } +func VSCALEFPD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VSCALEFPD_BCST_Z(m, xyz, k, xyz1) } -// VPACKUSWB: Pack Words into Bytes with Unsigned Saturation. +// VSCALEFPD_RD_SAE: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Round Towards Negative Infinity). // // Forms: // -// VPACKUSWB xmm xmm xmm -// VPACKUSWB m128 xmm xmm -// VPACKUSWB ymm ymm ymm -// VPACKUSWB m256 ymm ymm -// Construct and append a VPACKUSWB instruction to the active function. -func (c *Context) VPACKUSWB(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPACKUSWB(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFPD.RD_SAE zmm zmm k zmm +// VSCALEFPD.RD_SAE zmm zmm zmm +// Construct and append a VSCALEFPD.RD_SAE instruction to the active function. +func (c *Context) VSCALEFPD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSCALEFPD_RD_SAE(ops...)) } -// VPACKUSWB: Pack Words into Bytes with Unsigned Saturation. +// VSCALEFPD_RD_SAE: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Round Towards Negative Infinity). // // Forms: // -// VPACKUSWB xmm xmm xmm -// VPACKUSWB m128 xmm xmm -// VPACKUSWB ymm ymm ymm -// VPACKUSWB m256 ymm ymm -// Construct and append a VPACKUSWB instruction to the active function. +// VSCALEFPD.RD_SAE zmm zmm k zmm +// VSCALEFPD.RD_SAE zmm zmm zmm +// Construct and append a VSCALEFPD.RD_SAE instruction to the active function. // Operates on the global context. -func VPACKUSWB(mxy, xy, xy1 operand.Op) { ctx.VPACKUSWB(mxy, xy, xy1) } +func VSCALEFPD_RD_SAE(ops ...operand.Op) { ctx.VSCALEFPD_RD_SAE(ops...) } -// VPADDB: Add Packed Byte Integers. +// VSCALEFPD_RD_SAE_Z: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VPADDB xmm xmm xmm -// VPADDB m128 xmm xmm -// VPADDB ymm ymm ymm -// VPADDB m256 ymm ymm -// Construct and append a VPADDB instruction to the active function. -func (c *Context) VPADDB(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPADDB(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFPD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VSCALEFPD.RD_SAE.Z instruction to the active function. +func (c *Context) VSCALEFPD_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VSCALEFPD_RD_SAE_Z(z, z1, k, z2)) } -// VPADDB: Add Packed Byte Integers. +// VSCALEFPD_RD_SAE_Z: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VPADDB xmm xmm xmm -// VPADDB m128 xmm xmm -// VPADDB ymm ymm ymm -// VPADDB m256 ymm ymm -// Construct and append a VPADDB instruction to the active function. +// VSCALEFPD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VSCALEFPD.RD_SAE.Z instruction to the active function. // Operates on the global context. -func VPADDB(mxy, xy, xy1 operand.Op) { ctx.VPADDB(mxy, xy, xy1) } +func VSCALEFPD_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VSCALEFPD_RD_SAE_Z(z, z1, k, z2) } -// VPADDD: Add Packed Doubleword Integers. +// VSCALEFPD_RN_SAE: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Round Towards Nearest). // // Forms: // -// VPADDD xmm xmm xmm -// VPADDD m128 xmm xmm -// VPADDD ymm ymm ymm -// VPADDD m256 ymm ymm -// Construct and append a VPADDD instruction to the active function. -func (c *Context) VPADDD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPADDD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFPD.RN_SAE zmm zmm k zmm +// VSCALEFPD.RN_SAE zmm zmm zmm +// Construct and append a VSCALEFPD.RN_SAE instruction to the active function. +func (c *Context) VSCALEFPD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSCALEFPD_RN_SAE(ops...)) } -// VPADDD: Add Packed Doubleword Integers. +// VSCALEFPD_RN_SAE: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Round Towards Nearest). // // Forms: // -// VPADDD xmm xmm xmm -// VPADDD m128 xmm xmm -// VPADDD ymm ymm ymm -// VPADDD m256 ymm ymm -// Construct and append a VPADDD instruction to the active function. +// VSCALEFPD.RN_SAE zmm zmm k zmm +// VSCALEFPD.RN_SAE zmm zmm zmm +// Construct and append a VSCALEFPD.RN_SAE instruction to the active function. // Operates on the global context. -func VPADDD(mxy, xy, xy1 operand.Op) { ctx.VPADDD(mxy, xy, xy1) } +func VSCALEFPD_RN_SAE(ops ...operand.Op) { ctx.VSCALEFPD_RN_SAE(ops...) } -// VPADDQ: Add Packed Quadword Integers. +// VSCALEFPD_RN_SAE_Z: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VPADDQ xmm xmm xmm -// VPADDQ m128 xmm xmm -// VPADDQ ymm ymm ymm -// VPADDQ m256 ymm ymm -// Construct and append a VPADDQ instruction to the active function. -func (c *Context) VPADDQ(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPADDQ(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFPD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VSCALEFPD.RN_SAE.Z instruction to the active function. +func (c *Context) VSCALEFPD_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VSCALEFPD_RN_SAE_Z(z, z1, k, z2)) } -// VPADDQ: Add Packed Quadword Integers. +// VSCALEFPD_RN_SAE_Z: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VPADDQ xmm xmm xmm -// VPADDQ m128 xmm xmm -// VPADDQ ymm ymm ymm -// VPADDQ m256 ymm ymm -// Construct and append a VPADDQ instruction to the active function. +// VSCALEFPD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VSCALEFPD.RN_SAE.Z instruction to the active function. // Operates on the global context. -func VPADDQ(mxy, xy, xy1 operand.Op) { ctx.VPADDQ(mxy, xy, xy1) } +func VSCALEFPD_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VSCALEFPD_RN_SAE_Z(z, z1, k, z2) } -// VPADDSB: Add Packed Signed Byte Integers with Signed Saturation. +// VSCALEFPD_RU_SAE: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Round Towards Positive Infinity). // // Forms: // -// VPADDSB xmm xmm xmm -// VPADDSB m128 xmm xmm -// VPADDSB ymm ymm ymm -// VPADDSB m256 ymm ymm -// Construct and append a VPADDSB instruction to the active function. -func (c *Context) VPADDSB(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPADDSB(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFPD.RU_SAE zmm zmm k zmm +// VSCALEFPD.RU_SAE zmm zmm zmm +// Construct and append a VSCALEFPD.RU_SAE instruction to the active function. +func (c *Context) VSCALEFPD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSCALEFPD_RU_SAE(ops...)) } -// VPADDSB: Add Packed Signed Byte Integers with Signed Saturation. +// VSCALEFPD_RU_SAE: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Round Towards Positive Infinity). // // Forms: // -// VPADDSB xmm xmm xmm -// VPADDSB m128 xmm xmm -// VPADDSB ymm ymm ymm -// VPADDSB m256 ymm ymm -// Construct and append a VPADDSB instruction to the active function. +// VSCALEFPD.RU_SAE zmm zmm k zmm +// VSCALEFPD.RU_SAE zmm zmm zmm +// Construct and append a VSCALEFPD.RU_SAE instruction to the active function. // Operates on the global context. -func VPADDSB(mxy, xy, xy1 operand.Op) { ctx.VPADDSB(mxy, xy, xy1) } +func VSCALEFPD_RU_SAE(ops ...operand.Op) { ctx.VSCALEFPD_RU_SAE(ops...) } -// VPADDSW: Add Packed Signed Word Integers with Signed Saturation. +// VSCALEFPD_RU_SAE_Z: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VPADDSW xmm xmm xmm -// VPADDSW m128 xmm xmm -// VPADDSW ymm ymm ymm -// VPADDSW m256 ymm ymm -// Construct and append a VPADDSW instruction to the active function. -func (c *Context) VPADDSW(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPADDSW(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFPD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VSCALEFPD.RU_SAE.Z instruction to the active function. +func (c *Context) VSCALEFPD_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VSCALEFPD_RU_SAE_Z(z, z1, k, z2)) } -// VPADDSW: Add Packed Signed Word Integers with Signed Saturation. +// VSCALEFPD_RU_SAE_Z: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VPADDSW xmm xmm xmm -// VPADDSW m128 xmm xmm -// VPADDSW ymm ymm ymm -// VPADDSW m256 ymm ymm -// Construct and append a VPADDSW instruction to the active function. +// VSCALEFPD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VSCALEFPD.RU_SAE.Z instruction to the active function. // Operates on the global context. -func VPADDSW(mxy, xy, xy1 operand.Op) { ctx.VPADDSW(mxy, xy, xy1) } +func VSCALEFPD_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VSCALEFPD_RU_SAE_Z(z, z1, k, z2) } -// VPADDUSB: Add Packed Unsigned Byte Integers with Unsigned Saturation. +// VSCALEFPD_RZ_SAE: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Round Towards Zero). // // Forms: // -// VPADDUSB xmm xmm xmm -// VPADDUSB m128 xmm xmm -// VPADDUSB ymm ymm ymm -// VPADDUSB m256 ymm ymm -// Construct and append a VPADDUSB instruction to the active function. -func (c *Context) VPADDUSB(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPADDUSB(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFPD.RZ_SAE zmm zmm k zmm +// VSCALEFPD.RZ_SAE zmm zmm zmm +// Construct and append a VSCALEFPD.RZ_SAE instruction to the active function. +func (c *Context) VSCALEFPD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSCALEFPD_RZ_SAE(ops...)) } -// VPADDUSB: Add Packed Unsigned Byte Integers with Unsigned Saturation. +// VSCALEFPD_RZ_SAE: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Round Towards Zero). // // Forms: // -// VPADDUSB xmm xmm xmm -// VPADDUSB m128 xmm xmm -// VPADDUSB ymm ymm ymm -// VPADDUSB m256 ymm ymm -// Construct and append a VPADDUSB instruction to the active function. +// VSCALEFPD.RZ_SAE zmm zmm k zmm +// VSCALEFPD.RZ_SAE zmm zmm zmm +// Construct and append a VSCALEFPD.RZ_SAE instruction to the active function. // Operates on the global context. -func VPADDUSB(mxy, xy, xy1 operand.Op) { ctx.VPADDUSB(mxy, xy, xy1) } +func VSCALEFPD_RZ_SAE(ops ...operand.Op) { ctx.VSCALEFPD_RZ_SAE(ops...) } -// VPADDUSW: Add Packed Unsigned Word Integers with Unsigned Saturation. +// VSCALEFPD_RZ_SAE_Z: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). // // Forms: // -// VPADDUSW xmm xmm xmm -// VPADDUSW m128 xmm xmm -// VPADDUSW ymm ymm ymm -// VPADDUSW m256 ymm ymm -// Construct and append a VPADDUSW instruction to the active function. -func (c *Context) VPADDUSW(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPADDUSW(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFPD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VSCALEFPD.RZ_SAE.Z instruction to the active function. +func (c *Context) VSCALEFPD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VSCALEFPD_RZ_SAE_Z(z, z1, k, z2)) } -// VPADDUSW: Add Packed Unsigned Word Integers with Unsigned Saturation. +// VSCALEFPD_RZ_SAE_Z: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). // // Forms: // -// VPADDUSW xmm xmm xmm -// VPADDUSW m128 xmm xmm -// VPADDUSW ymm ymm ymm -// VPADDUSW m256 ymm ymm -// Construct and append a VPADDUSW instruction to the active function. +// VSCALEFPD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VSCALEFPD.RZ_SAE.Z instruction to the active function. // Operates on the global context. -func VPADDUSW(mxy, xy, xy1 operand.Op) { ctx.VPADDUSW(mxy, xy, xy1) } +func VSCALEFPD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VSCALEFPD_RZ_SAE_Z(z, z1, k, z2) } -// VPADDW: Add Packed Word Integers. +// VSCALEFPD_Z: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VPADDW xmm xmm xmm -// VPADDW m128 xmm xmm -// VPADDW ymm ymm ymm -// VPADDW m256 ymm ymm -// Construct and append a VPADDW instruction to the active function. -func (c *Context) VPADDW(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPADDW(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFPD.Z m128 xmm k xmm +// VSCALEFPD.Z m256 ymm k ymm +// VSCALEFPD.Z xmm xmm k xmm +// VSCALEFPD.Z ymm ymm k ymm +// VSCALEFPD.Z m512 zmm k zmm +// VSCALEFPD.Z zmm zmm k zmm +// Construct and append a VSCALEFPD.Z instruction to the active function. +func (c *Context) VSCALEFPD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VSCALEFPD_Z(mxyz, xyz, k, xyz1)) } -// VPADDW: Add Packed Word Integers. +// VSCALEFPD_Z: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VPADDW xmm xmm xmm -// VPADDW m128 xmm xmm -// VPADDW ymm ymm ymm -// VPADDW m256 ymm ymm -// Construct and append a VPADDW instruction to the active function. +// VSCALEFPD.Z m128 xmm k xmm +// VSCALEFPD.Z m256 ymm k ymm +// VSCALEFPD.Z xmm xmm k xmm +// VSCALEFPD.Z ymm ymm k ymm +// VSCALEFPD.Z m512 zmm k zmm +// VSCALEFPD.Z zmm zmm k zmm +// Construct and append a VSCALEFPD.Z instruction to the active function. // Operates on the global context. -func VPADDW(mxy, xy, xy1 operand.Op) { ctx.VPADDW(mxy, xy, xy1) } +func VSCALEFPD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VSCALEFPD_Z(mxyz, xyz, k, xyz1) } -// VPALIGNR: Packed Align Right. +// VSCALEFPS: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values. // // Forms: // -// VPALIGNR imm8 xmm xmm xmm -// VPALIGNR imm8 m128 xmm xmm -// VPALIGNR imm8 ymm ymm ymm -// VPALIGNR imm8 m256 ymm ymm -// Construct and append a VPALIGNR instruction to the active function. -func (c *Context) VPALIGNR(i, mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPALIGNR(i, mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFPS m128 xmm k xmm +// VSCALEFPS m128 xmm xmm +// VSCALEFPS m256 ymm k ymm +// VSCALEFPS m256 ymm ymm +// VSCALEFPS xmm xmm k xmm +// VSCALEFPS xmm xmm xmm +// VSCALEFPS ymm ymm k ymm +// VSCALEFPS ymm ymm ymm +// VSCALEFPS m512 zmm k zmm +// VSCALEFPS m512 zmm zmm +// VSCALEFPS zmm zmm k zmm +// VSCALEFPS zmm zmm zmm +// Construct and append a VSCALEFPS instruction to the active function. +func (c *Context) VSCALEFPS(ops ...operand.Op) { + c.addinstruction(x86.VSCALEFPS(ops...)) } -// VPALIGNR: Packed Align Right. +// VSCALEFPS: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values. // // Forms: // -// VPALIGNR imm8 xmm xmm xmm -// VPALIGNR imm8 m128 xmm xmm -// VPALIGNR imm8 ymm ymm ymm -// VPALIGNR imm8 m256 ymm ymm -// Construct and append a VPALIGNR instruction to the active function. +// VSCALEFPS m128 xmm k xmm +// VSCALEFPS m128 xmm xmm +// VSCALEFPS m256 ymm k ymm +// VSCALEFPS m256 ymm ymm +// VSCALEFPS xmm xmm k xmm +// VSCALEFPS xmm xmm xmm +// VSCALEFPS ymm ymm k ymm +// VSCALEFPS ymm ymm ymm +// VSCALEFPS m512 zmm k zmm +// VSCALEFPS m512 zmm zmm +// VSCALEFPS zmm zmm k zmm +// VSCALEFPS zmm zmm zmm +// Construct and append a VSCALEFPS instruction to the active function. // Operates on the global context. -func VPALIGNR(i, mxy, xy, xy1 operand.Op) { ctx.VPALIGNR(i, mxy, xy, xy1) } +func VSCALEFPS(ops ...operand.Op) { ctx.VSCALEFPS(ops...) } -// VPAND: Packed Bitwise Logical AND. +// VSCALEFPS_BCST: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Broadcast). // // Forms: // -// VPAND xmm xmm xmm -// VPAND m128 xmm xmm -// VPAND ymm ymm ymm -// VPAND m256 ymm ymm -// Construct and append a VPAND instruction to the active function. -func (c *Context) VPAND(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPAND(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFPS.BCST m32 xmm k xmm +// VSCALEFPS.BCST m32 xmm xmm +// VSCALEFPS.BCST m32 ymm k ymm +// VSCALEFPS.BCST m32 ymm ymm +// VSCALEFPS.BCST m32 zmm k zmm +// VSCALEFPS.BCST m32 zmm zmm +// Construct and append a VSCALEFPS.BCST instruction to the active function. +func (c *Context) VSCALEFPS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VSCALEFPS_BCST(ops...)) } -// VPAND: Packed Bitwise Logical AND. +// VSCALEFPS_BCST: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Broadcast). // // Forms: // -// VPAND xmm xmm xmm -// VPAND m128 xmm xmm -// VPAND ymm ymm ymm -// VPAND m256 ymm ymm -// Construct and append a VPAND instruction to the active function. +// VSCALEFPS.BCST m32 xmm k xmm +// VSCALEFPS.BCST m32 xmm xmm +// VSCALEFPS.BCST m32 ymm k ymm +// VSCALEFPS.BCST m32 ymm ymm +// VSCALEFPS.BCST m32 zmm k zmm +// VSCALEFPS.BCST m32 zmm zmm +// Construct and append a VSCALEFPS.BCST instruction to the active function. // Operates on the global context. -func VPAND(mxy, xy, xy1 operand.Op) { ctx.VPAND(mxy, xy, xy1) } +func VSCALEFPS_BCST(ops ...operand.Op) { ctx.VSCALEFPS_BCST(ops...) } -// VPANDN: Packed Bitwise Logical AND NOT. +// VSCALEFPS_BCST_Z: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VPANDN xmm xmm xmm -// VPANDN m128 xmm xmm -// VPANDN ymm ymm ymm -// VPANDN m256 ymm ymm -// Construct and append a VPANDN instruction to the active function. -func (c *Context) VPANDN(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPANDN(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFPS.BCST.Z m32 xmm k xmm +// VSCALEFPS.BCST.Z m32 ymm k ymm +// VSCALEFPS.BCST.Z m32 zmm k zmm +// Construct and append a VSCALEFPS.BCST.Z instruction to the active function. +func (c *Context) VSCALEFPS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VSCALEFPS_BCST_Z(m, xyz, k, xyz1)) } -// VPANDN: Packed Bitwise Logical AND NOT. +// VSCALEFPS_BCST_Z: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VPANDN xmm xmm xmm -// VPANDN m128 xmm xmm -// VPANDN ymm ymm ymm -// VPANDN m256 ymm ymm -// Construct and append a VPANDN instruction to the active function. +// VSCALEFPS.BCST.Z m32 xmm k xmm +// VSCALEFPS.BCST.Z m32 ymm k ymm +// VSCALEFPS.BCST.Z m32 zmm k zmm +// Construct and append a VSCALEFPS.BCST.Z instruction to the active function. // Operates on the global context. -func VPANDN(mxy, xy, xy1 operand.Op) { ctx.VPANDN(mxy, xy, xy1) } +func VSCALEFPS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VSCALEFPS_BCST_Z(m, xyz, k, xyz1) } -// VPAVGB: Average Packed Byte Integers. +// VSCALEFPS_RD_SAE: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Round Towards Negative Infinity). // // Forms: // -// VPAVGB xmm xmm xmm -// VPAVGB m128 xmm xmm -// VPAVGB ymm ymm ymm -// VPAVGB m256 ymm ymm -// Construct and append a VPAVGB instruction to the active function. -func (c *Context) VPAVGB(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPAVGB(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFPS.RD_SAE zmm zmm k zmm +// VSCALEFPS.RD_SAE zmm zmm zmm +// Construct and append a VSCALEFPS.RD_SAE instruction to the active function. +func (c *Context) VSCALEFPS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSCALEFPS_RD_SAE(ops...)) } -// VPAVGB: Average Packed Byte Integers. +// VSCALEFPS_RD_SAE: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Round Towards Negative Infinity). // // Forms: // -// VPAVGB xmm xmm xmm -// VPAVGB m128 xmm xmm -// VPAVGB ymm ymm ymm -// VPAVGB m256 ymm ymm -// Construct and append a VPAVGB instruction to the active function. +// VSCALEFPS.RD_SAE zmm zmm k zmm +// VSCALEFPS.RD_SAE zmm zmm zmm +// Construct and append a VSCALEFPS.RD_SAE instruction to the active function. // Operates on the global context. -func VPAVGB(mxy, xy, xy1 operand.Op) { ctx.VPAVGB(mxy, xy, xy1) } +func VSCALEFPS_RD_SAE(ops ...operand.Op) { ctx.VSCALEFPS_RD_SAE(ops...) } -// VPAVGW: Average Packed Word Integers. +// VSCALEFPS_RD_SAE_Z: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VPAVGW xmm xmm xmm -// VPAVGW m128 xmm xmm -// VPAVGW ymm ymm ymm -// VPAVGW m256 ymm ymm -// Construct and append a VPAVGW instruction to the active function. -func (c *Context) VPAVGW(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPAVGW(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFPS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VSCALEFPS.RD_SAE.Z instruction to the active function. +func (c *Context) VSCALEFPS_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VSCALEFPS_RD_SAE_Z(z, z1, k, z2)) } -// VPAVGW: Average Packed Word Integers. +// VSCALEFPS_RD_SAE_Z: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VPAVGW xmm xmm xmm -// VPAVGW m128 xmm xmm -// VPAVGW ymm ymm ymm -// VPAVGW m256 ymm ymm -// Construct and append a VPAVGW instruction to the active function. +// VSCALEFPS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VSCALEFPS.RD_SAE.Z instruction to the active function. // Operates on the global context. -func VPAVGW(mxy, xy, xy1 operand.Op) { ctx.VPAVGW(mxy, xy, xy1) } +func VSCALEFPS_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VSCALEFPS_RD_SAE_Z(z, z1, k, z2) } -// VPBLENDD: Blend Packed Doublewords. +// VSCALEFPS_RN_SAE: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Round Towards Nearest). // // Forms: // -// VPBLENDD imm8 xmm xmm xmm -// VPBLENDD imm8 m128 xmm xmm -// VPBLENDD imm8 ymm ymm ymm -// VPBLENDD imm8 m256 ymm ymm -// Construct and append a VPBLENDD instruction to the active function. -func (c *Context) VPBLENDD(i, mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPBLENDD(i, mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFPS.RN_SAE zmm zmm k zmm +// VSCALEFPS.RN_SAE zmm zmm zmm +// Construct and append a VSCALEFPS.RN_SAE instruction to the active function. +func (c *Context) VSCALEFPS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSCALEFPS_RN_SAE(ops...)) } -// VPBLENDD: Blend Packed Doublewords. +// VSCALEFPS_RN_SAE: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Round Towards Nearest). // // Forms: // -// VPBLENDD imm8 xmm xmm xmm -// VPBLENDD imm8 m128 xmm xmm -// VPBLENDD imm8 ymm ymm ymm -// VPBLENDD imm8 m256 ymm ymm -// Construct and append a VPBLENDD instruction to the active function. +// VSCALEFPS.RN_SAE zmm zmm k zmm +// VSCALEFPS.RN_SAE zmm zmm zmm +// Construct and append a VSCALEFPS.RN_SAE instruction to the active function. // Operates on the global context. -func VPBLENDD(i, mxy, xy, xy1 operand.Op) { ctx.VPBLENDD(i, mxy, xy, xy1) } +func VSCALEFPS_RN_SAE(ops ...operand.Op) { ctx.VSCALEFPS_RN_SAE(ops...) } -// VPBLENDVB: Variable Blend Packed Bytes. +// VSCALEFPS_RN_SAE_Z: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). // // Forms: -// -// VPBLENDVB xmm xmm xmm xmm -// VPBLENDVB xmm m128 xmm xmm -// VPBLENDVB ymm ymm ymm ymm -// VPBLENDVB ymm m256 ymm ymm -// Construct and append a VPBLENDVB instruction to the active function. -func (c *Context) VPBLENDVB(xy, mxy, xy1, xy2 operand.Op) { - if inst, err := x86.VPBLENDVB(xy, mxy, xy1, xy2); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// +// VSCALEFPS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VSCALEFPS.RN_SAE.Z instruction to the active function. +func (c *Context) VSCALEFPS_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VSCALEFPS_RN_SAE_Z(z, z1, k, z2)) } -// VPBLENDVB: Variable Blend Packed Bytes. +// VSCALEFPS_RN_SAE_Z: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VPBLENDVB xmm xmm xmm xmm -// VPBLENDVB xmm m128 xmm xmm -// VPBLENDVB ymm ymm ymm ymm -// VPBLENDVB ymm m256 ymm ymm -// Construct and append a VPBLENDVB instruction to the active function. +// VSCALEFPS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VSCALEFPS.RN_SAE.Z instruction to the active function. // Operates on the global context. -func VPBLENDVB(xy, mxy, xy1, xy2 operand.Op) { ctx.VPBLENDVB(xy, mxy, xy1, xy2) } +func VSCALEFPS_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VSCALEFPS_RN_SAE_Z(z, z1, k, z2) } -// VPBLENDW: Blend Packed Words. +// VSCALEFPS_RU_SAE: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Round Towards Positive Infinity). // // Forms: // -// VPBLENDW imm8 xmm xmm xmm -// VPBLENDW imm8 m128 xmm xmm -// VPBLENDW imm8 ymm ymm ymm -// VPBLENDW imm8 m256 ymm ymm -// Construct and append a VPBLENDW instruction to the active function. -func (c *Context) VPBLENDW(i, mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPBLENDW(i, mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFPS.RU_SAE zmm zmm k zmm +// VSCALEFPS.RU_SAE zmm zmm zmm +// Construct and append a VSCALEFPS.RU_SAE instruction to the active function. +func (c *Context) VSCALEFPS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSCALEFPS_RU_SAE(ops...)) } -// VPBLENDW: Blend Packed Words. +// VSCALEFPS_RU_SAE: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Round Towards Positive Infinity). // // Forms: // -// VPBLENDW imm8 xmm xmm xmm -// VPBLENDW imm8 m128 xmm xmm -// VPBLENDW imm8 ymm ymm ymm -// VPBLENDW imm8 m256 ymm ymm -// Construct and append a VPBLENDW instruction to the active function. +// VSCALEFPS.RU_SAE zmm zmm k zmm +// VSCALEFPS.RU_SAE zmm zmm zmm +// Construct and append a VSCALEFPS.RU_SAE instruction to the active function. // Operates on the global context. -func VPBLENDW(i, mxy, xy, xy1 operand.Op) { ctx.VPBLENDW(i, mxy, xy, xy1) } +func VSCALEFPS_RU_SAE(ops ...operand.Op) { ctx.VSCALEFPS_RU_SAE(ops...) } -// VPBROADCASTB: Broadcast Byte Integer. +// VSCALEFPS_RU_SAE_Z: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VPBROADCASTB xmm xmm -// VPBROADCASTB m8 xmm -// VPBROADCASTB xmm ymm -// VPBROADCASTB m8 ymm -// Construct and append a VPBROADCASTB instruction to the active function. -func (c *Context) VPBROADCASTB(mx, xy operand.Op) { - if inst, err := x86.VPBROADCASTB(mx, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFPS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VSCALEFPS.RU_SAE.Z instruction to the active function. +func (c *Context) VSCALEFPS_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VSCALEFPS_RU_SAE_Z(z, z1, k, z2)) } -// VPBROADCASTB: Broadcast Byte Integer. +// VSCALEFPS_RU_SAE_Z: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VPBROADCASTB xmm xmm -// VPBROADCASTB m8 xmm -// VPBROADCASTB xmm ymm -// VPBROADCASTB m8 ymm -// Construct and append a VPBROADCASTB instruction to the active function. +// VSCALEFPS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VSCALEFPS.RU_SAE.Z instruction to the active function. // Operates on the global context. -func VPBROADCASTB(mx, xy operand.Op) { ctx.VPBROADCASTB(mx, xy) } +func VSCALEFPS_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VSCALEFPS_RU_SAE_Z(z, z1, k, z2) } -// VPBROADCASTD: Broadcast Doubleword Integer. +// VSCALEFPS_RZ_SAE: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Round Towards Zero). // // Forms: // -// VPBROADCASTD xmm xmm -// VPBROADCASTD m32 xmm -// VPBROADCASTD xmm ymm -// VPBROADCASTD m32 ymm -// Construct and append a VPBROADCASTD instruction to the active function. -func (c *Context) VPBROADCASTD(mx, xy operand.Op) { - if inst, err := x86.VPBROADCASTD(mx, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFPS.RZ_SAE zmm zmm k zmm +// VSCALEFPS.RZ_SAE zmm zmm zmm +// Construct and append a VSCALEFPS.RZ_SAE instruction to the active function. +func (c *Context) VSCALEFPS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSCALEFPS_RZ_SAE(ops...)) } -// VPBROADCASTD: Broadcast Doubleword Integer. +// VSCALEFPS_RZ_SAE: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Round Towards Zero). // // Forms: // -// VPBROADCASTD xmm xmm -// VPBROADCASTD m32 xmm -// VPBROADCASTD xmm ymm -// VPBROADCASTD m32 ymm -// Construct and append a VPBROADCASTD instruction to the active function. +// VSCALEFPS.RZ_SAE zmm zmm k zmm +// VSCALEFPS.RZ_SAE zmm zmm zmm +// Construct and append a VSCALEFPS.RZ_SAE instruction to the active function. // Operates on the global context. -func VPBROADCASTD(mx, xy operand.Op) { ctx.VPBROADCASTD(mx, xy) } +func VSCALEFPS_RZ_SAE(ops ...operand.Op) { ctx.VSCALEFPS_RZ_SAE(ops...) } -// VPBROADCASTQ: Broadcast Quadword Integer. +// VSCALEFPS_RZ_SAE_Z: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). // // Forms: // -// VPBROADCASTQ xmm xmm -// VPBROADCASTQ m64 xmm -// VPBROADCASTQ xmm ymm -// VPBROADCASTQ m64 ymm -// Construct and append a VPBROADCASTQ instruction to the active function. -func (c *Context) VPBROADCASTQ(mx, xy operand.Op) { - if inst, err := x86.VPBROADCASTQ(mx, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFPS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VSCALEFPS.RZ_SAE.Z instruction to the active function. +func (c *Context) VSCALEFPS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VSCALEFPS_RZ_SAE_Z(z, z1, k, z2)) } -// VPBROADCASTQ: Broadcast Quadword Integer. +// VSCALEFPS_RZ_SAE_Z: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). // // Forms: // -// VPBROADCASTQ xmm xmm -// VPBROADCASTQ m64 xmm -// VPBROADCASTQ xmm ymm -// VPBROADCASTQ m64 ymm -// Construct and append a VPBROADCASTQ instruction to the active function. +// VSCALEFPS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VSCALEFPS.RZ_SAE.Z instruction to the active function. // Operates on the global context. -func VPBROADCASTQ(mx, xy operand.Op) { ctx.VPBROADCASTQ(mx, xy) } +func VSCALEFPS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VSCALEFPS_RZ_SAE_Z(z, z1, k, z2) } -// VPBROADCASTW: Broadcast Word Integer. +// VSCALEFPS_Z: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VPBROADCASTW xmm xmm -// VPBROADCASTW m16 xmm -// VPBROADCASTW xmm ymm -// VPBROADCASTW m16 ymm -// Construct and append a VPBROADCASTW instruction to the active function. -func (c *Context) VPBROADCASTW(mx, xy operand.Op) { - if inst, err := x86.VPBROADCASTW(mx, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFPS.Z m128 xmm k xmm +// VSCALEFPS.Z m256 ymm k ymm +// VSCALEFPS.Z xmm xmm k xmm +// VSCALEFPS.Z ymm ymm k ymm +// VSCALEFPS.Z m512 zmm k zmm +// VSCALEFPS.Z zmm zmm k zmm +// Construct and append a VSCALEFPS.Z instruction to the active function. +func (c *Context) VSCALEFPS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VSCALEFPS_Z(mxyz, xyz, k, xyz1)) } -// VPBROADCASTW: Broadcast Word Integer. +// VSCALEFPS_Z: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VPBROADCASTW xmm xmm -// VPBROADCASTW m16 xmm -// VPBROADCASTW xmm ymm -// VPBROADCASTW m16 ymm -// Construct and append a VPBROADCASTW instruction to the active function. +// VSCALEFPS.Z m128 xmm k xmm +// VSCALEFPS.Z m256 ymm k ymm +// VSCALEFPS.Z xmm xmm k xmm +// VSCALEFPS.Z ymm ymm k ymm +// VSCALEFPS.Z m512 zmm k zmm +// VSCALEFPS.Z zmm zmm k zmm +// Construct and append a VSCALEFPS.Z instruction to the active function. // Operates on the global context. -func VPBROADCASTW(mx, xy operand.Op) { ctx.VPBROADCASTW(mx, xy) } +func VSCALEFPS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VSCALEFPS_Z(mxyz, xyz, k, xyz1) } -// VPCLMULQDQ: Carry-Less Quadword Multiplication. +// VSCALEFSD: Scale Scalar Double-Precision Floating-Point Value With a Double-Precision Floating-Point Value. // // Forms: // -// VPCLMULQDQ imm8 xmm xmm xmm -// VPCLMULQDQ imm8 m128 xmm xmm -// Construct and append a VPCLMULQDQ instruction to the active function. -func (c *Context) VPCLMULQDQ(i, mx, x, x1 operand.Op) { - if inst, err := x86.VPCLMULQDQ(i, mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFSD m64 xmm k xmm +// VSCALEFSD m64 xmm xmm +// VSCALEFSD xmm xmm k xmm +// VSCALEFSD xmm xmm xmm +// Construct and append a VSCALEFSD instruction to the active function. +func (c *Context) VSCALEFSD(ops ...operand.Op) { + c.addinstruction(x86.VSCALEFSD(ops...)) } -// VPCLMULQDQ: Carry-Less Quadword Multiplication. +// VSCALEFSD: Scale Scalar Double-Precision Floating-Point Value With a Double-Precision Floating-Point Value. // // Forms: // -// VPCLMULQDQ imm8 xmm xmm xmm -// VPCLMULQDQ imm8 m128 xmm xmm -// Construct and append a VPCLMULQDQ instruction to the active function. +// VSCALEFSD m64 xmm k xmm +// VSCALEFSD m64 xmm xmm +// VSCALEFSD xmm xmm k xmm +// VSCALEFSD xmm xmm xmm +// Construct and append a VSCALEFSD instruction to the active function. // Operates on the global context. -func VPCLMULQDQ(i, mx, x, x1 operand.Op) { ctx.VPCLMULQDQ(i, mx, x, x1) } +func VSCALEFSD(ops ...operand.Op) { ctx.VSCALEFSD(ops...) } -// VPCMPEQB: Compare Packed Byte Data for Equality. +// VSCALEFSD_RD_SAE: Scale Scalar Double-Precision Floating-Point Value With a Double-Precision Floating-Point Value (Round Towards Negative Infinity). // // Forms: // -// VPCMPEQB xmm xmm xmm -// VPCMPEQB m128 xmm xmm -// VPCMPEQB ymm ymm ymm -// VPCMPEQB m256 ymm ymm -// Construct and append a VPCMPEQB instruction to the active function. -func (c *Context) VPCMPEQB(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPCMPEQB(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFSD.RD_SAE xmm xmm k xmm +// VSCALEFSD.RD_SAE xmm xmm xmm +// Construct and append a VSCALEFSD.RD_SAE instruction to the active function. +func (c *Context) VSCALEFSD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSCALEFSD_RD_SAE(ops...)) } -// VPCMPEQB: Compare Packed Byte Data for Equality. +// VSCALEFSD_RD_SAE: Scale Scalar Double-Precision Floating-Point Value With a Double-Precision Floating-Point Value (Round Towards Negative Infinity). // // Forms: // -// VPCMPEQB xmm xmm xmm -// VPCMPEQB m128 xmm xmm -// VPCMPEQB ymm ymm ymm -// VPCMPEQB m256 ymm ymm -// Construct and append a VPCMPEQB instruction to the active function. +// VSCALEFSD.RD_SAE xmm xmm k xmm +// VSCALEFSD.RD_SAE xmm xmm xmm +// Construct and append a VSCALEFSD.RD_SAE instruction to the active function. // Operates on the global context. -func VPCMPEQB(mxy, xy, xy1 operand.Op) { ctx.VPCMPEQB(mxy, xy, xy1) } +func VSCALEFSD_RD_SAE(ops ...operand.Op) { ctx.VSCALEFSD_RD_SAE(ops...) } -// VPCMPEQD: Compare Packed Doubleword Data for Equality. +// VSCALEFSD_RD_SAE_Z: Scale Scalar Double-Precision Floating-Point Value With a Double-Precision Floating-Point Value (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VPCMPEQD xmm xmm xmm -// VPCMPEQD m128 xmm xmm -// VPCMPEQD ymm ymm ymm -// VPCMPEQD m256 ymm ymm -// Construct and append a VPCMPEQD instruction to the active function. -func (c *Context) VPCMPEQD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPCMPEQD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFSD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VSCALEFSD.RD_SAE.Z instruction to the active function. +func (c *Context) VSCALEFSD_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VSCALEFSD_RD_SAE_Z(x, x1, k, x2)) } -// VPCMPEQD: Compare Packed Doubleword Data for Equality. +// VSCALEFSD_RD_SAE_Z: Scale Scalar Double-Precision Floating-Point Value With a Double-Precision Floating-Point Value (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VPCMPEQD xmm xmm xmm -// VPCMPEQD m128 xmm xmm -// VPCMPEQD ymm ymm ymm -// VPCMPEQD m256 ymm ymm -// Construct and append a VPCMPEQD instruction to the active function. +// VSCALEFSD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VSCALEFSD.RD_SAE.Z instruction to the active function. // Operates on the global context. -func VPCMPEQD(mxy, xy, xy1 operand.Op) { ctx.VPCMPEQD(mxy, xy, xy1) } +func VSCALEFSD_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VSCALEFSD_RD_SAE_Z(x, x1, k, x2) } -// VPCMPEQQ: Compare Packed Quadword Data for Equality. +// VSCALEFSD_RN_SAE: Scale Scalar Double-Precision Floating-Point Value With a Double-Precision Floating-Point Value (Round Towards Nearest). // // Forms: // -// VPCMPEQQ xmm xmm xmm -// VPCMPEQQ m128 xmm xmm -// VPCMPEQQ ymm ymm ymm -// VPCMPEQQ m256 ymm ymm -// Construct and append a VPCMPEQQ instruction to the active function. -func (c *Context) VPCMPEQQ(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPCMPEQQ(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFSD.RN_SAE xmm xmm k xmm +// VSCALEFSD.RN_SAE xmm xmm xmm +// Construct and append a VSCALEFSD.RN_SAE instruction to the active function. +func (c *Context) VSCALEFSD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSCALEFSD_RN_SAE(ops...)) } -// VPCMPEQQ: Compare Packed Quadword Data for Equality. +// VSCALEFSD_RN_SAE: Scale Scalar Double-Precision Floating-Point Value With a Double-Precision Floating-Point Value (Round Towards Nearest). // // Forms: // -// VPCMPEQQ xmm xmm xmm -// VPCMPEQQ m128 xmm xmm -// VPCMPEQQ ymm ymm ymm -// VPCMPEQQ m256 ymm ymm -// Construct and append a VPCMPEQQ instruction to the active function. +// VSCALEFSD.RN_SAE xmm xmm k xmm +// VSCALEFSD.RN_SAE xmm xmm xmm +// Construct and append a VSCALEFSD.RN_SAE instruction to the active function. // Operates on the global context. -func VPCMPEQQ(mxy, xy, xy1 operand.Op) { ctx.VPCMPEQQ(mxy, xy, xy1) } +func VSCALEFSD_RN_SAE(ops ...operand.Op) { ctx.VSCALEFSD_RN_SAE(ops...) } -// VPCMPEQW: Compare Packed Word Data for Equality. +// VSCALEFSD_RN_SAE_Z: Scale Scalar Double-Precision Floating-Point Value With a Double-Precision Floating-Point Value (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VPCMPEQW xmm xmm xmm -// VPCMPEQW m128 xmm xmm -// VPCMPEQW ymm ymm ymm -// VPCMPEQW m256 ymm ymm -// Construct and append a VPCMPEQW instruction to the active function. -func (c *Context) VPCMPEQW(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPCMPEQW(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFSD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VSCALEFSD.RN_SAE.Z instruction to the active function. +func (c *Context) VSCALEFSD_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VSCALEFSD_RN_SAE_Z(x, x1, k, x2)) } -// VPCMPEQW: Compare Packed Word Data for Equality. +// VSCALEFSD_RN_SAE_Z: Scale Scalar Double-Precision Floating-Point Value With a Double-Precision Floating-Point Value (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VPCMPEQW xmm xmm xmm -// VPCMPEQW m128 xmm xmm -// VPCMPEQW ymm ymm ymm -// VPCMPEQW m256 ymm ymm -// Construct and append a VPCMPEQW instruction to the active function. +// VSCALEFSD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VSCALEFSD.RN_SAE.Z instruction to the active function. // Operates on the global context. -func VPCMPEQW(mxy, xy, xy1 operand.Op) { ctx.VPCMPEQW(mxy, xy, xy1) } +func VSCALEFSD_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VSCALEFSD_RN_SAE_Z(x, x1, k, x2) } -// VPCMPESTRI: Packed Compare Explicit Length Strings, Return Index. +// VSCALEFSD_RU_SAE: Scale Scalar Double-Precision Floating-Point Value With a Double-Precision Floating-Point Value (Round Towards Positive Infinity). // // Forms: // -// VPCMPESTRI imm8 xmm xmm -// VPCMPESTRI imm8 m128 xmm -// Construct and append a VPCMPESTRI instruction to the active function. -func (c *Context) VPCMPESTRI(i, mx, x operand.Op) { - if inst, err := x86.VPCMPESTRI(i, mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFSD.RU_SAE xmm xmm k xmm +// VSCALEFSD.RU_SAE xmm xmm xmm +// Construct and append a VSCALEFSD.RU_SAE instruction to the active function. +func (c *Context) VSCALEFSD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSCALEFSD_RU_SAE(ops...)) } -// VPCMPESTRI: Packed Compare Explicit Length Strings, Return Index. +// VSCALEFSD_RU_SAE: Scale Scalar Double-Precision Floating-Point Value With a Double-Precision Floating-Point Value (Round Towards Positive Infinity). // // Forms: // -// VPCMPESTRI imm8 xmm xmm -// VPCMPESTRI imm8 m128 xmm -// Construct and append a VPCMPESTRI instruction to the active function. +// VSCALEFSD.RU_SAE xmm xmm k xmm +// VSCALEFSD.RU_SAE xmm xmm xmm +// Construct and append a VSCALEFSD.RU_SAE instruction to the active function. // Operates on the global context. -func VPCMPESTRI(i, mx, x operand.Op) { ctx.VPCMPESTRI(i, mx, x) } +func VSCALEFSD_RU_SAE(ops ...operand.Op) { ctx.VSCALEFSD_RU_SAE(ops...) } -// VPCMPESTRM: Packed Compare Explicit Length Strings, Return Mask. +// VSCALEFSD_RU_SAE_Z: Scale Scalar Double-Precision Floating-Point Value With a Double-Precision Floating-Point Value (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VPCMPESTRM imm8 xmm xmm -// VPCMPESTRM imm8 m128 xmm -// Construct and append a VPCMPESTRM instruction to the active function. -func (c *Context) VPCMPESTRM(i, mx, x operand.Op) { - if inst, err := x86.VPCMPESTRM(i, mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFSD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VSCALEFSD.RU_SAE.Z instruction to the active function. +func (c *Context) VSCALEFSD_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VSCALEFSD_RU_SAE_Z(x, x1, k, x2)) } -// VPCMPESTRM: Packed Compare Explicit Length Strings, Return Mask. +// VSCALEFSD_RU_SAE_Z: Scale Scalar Double-Precision Floating-Point Value With a Double-Precision Floating-Point Value (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VPCMPESTRM imm8 xmm xmm -// VPCMPESTRM imm8 m128 xmm -// Construct and append a VPCMPESTRM instruction to the active function. +// VSCALEFSD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VSCALEFSD.RU_SAE.Z instruction to the active function. // Operates on the global context. -func VPCMPESTRM(i, mx, x operand.Op) { ctx.VPCMPESTRM(i, mx, x) } +func VSCALEFSD_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VSCALEFSD_RU_SAE_Z(x, x1, k, x2) } -// VPCMPGTB: Compare Packed Signed Byte Integers for Greater Than. +// VSCALEFSD_RZ_SAE: Scale Scalar Double-Precision Floating-Point Value With a Double-Precision Floating-Point Value (Round Towards Zero). // // Forms: // -// VPCMPGTB xmm xmm xmm -// VPCMPGTB m128 xmm xmm -// VPCMPGTB ymm ymm ymm -// VPCMPGTB m256 ymm ymm -// Construct and append a VPCMPGTB instruction to the active function. -func (c *Context) VPCMPGTB(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPCMPGTB(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFSD.RZ_SAE xmm xmm k xmm +// VSCALEFSD.RZ_SAE xmm xmm xmm +// Construct and append a VSCALEFSD.RZ_SAE instruction to the active function. +func (c *Context) VSCALEFSD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSCALEFSD_RZ_SAE(ops...)) } -// VPCMPGTB: Compare Packed Signed Byte Integers for Greater Than. +// VSCALEFSD_RZ_SAE: Scale Scalar Double-Precision Floating-Point Value With a Double-Precision Floating-Point Value (Round Towards Zero). // // Forms: // -// VPCMPGTB xmm xmm xmm -// VPCMPGTB m128 xmm xmm -// VPCMPGTB ymm ymm ymm -// VPCMPGTB m256 ymm ymm -// Construct and append a VPCMPGTB instruction to the active function. +// VSCALEFSD.RZ_SAE xmm xmm k xmm +// VSCALEFSD.RZ_SAE xmm xmm xmm +// Construct and append a VSCALEFSD.RZ_SAE instruction to the active function. // Operates on the global context. -func VPCMPGTB(mxy, xy, xy1 operand.Op) { ctx.VPCMPGTB(mxy, xy, xy1) } +func VSCALEFSD_RZ_SAE(ops ...operand.Op) { ctx.VSCALEFSD_RZ_SAE(ops...) } -// VPCMPGTD: Compare Packed Signed Doubleword Integers for Greater Than. +// VSCALEFSD_RZ_SAE_Z: Scale Scalar Double-Precision Floating-Point Value With a Double-Precision Floating-Point Value (Round Towards Zero, Zeroing Masking). // // Forms: // -// VPCMPGTD xmm xmm xmm -// VPCMPGTD m128 xmm xmm -// VPCMPGTD ymm ymm ymm -// VPCMPGTD m256 ymm ymm -// Construct and append a VPCMPGTD instruction to the active function. -func (c *Context) VPCMPGTD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPCMPGTD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFSD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VSCALEFSD.RZ_SAE.Z instruction to the active function. +func (c *Context) VSCALEFSD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VSCALEFSD_RZ_SAE_Z(x, x1, k, x2)) } -// VPCMPGTD: Compare Packed Signed Doubleword Integers for Greater Than. +// VSCALEFSD_RZ_SAE_Z: Scale Scalar Double-Precision Floating-Point Value With a Double-Precision Floating-Point Value (Round Towards Zero, Zeroing Masking). // // Forms: // -// VPCMPGTD xmm xmm xmm -// VPCMPGTD m128 xmm xmm -// VPCMPGTD ymm ymm ymm -// VPCMPGTD m256 ymm ymm -// Construct and append a VPCMPGTD instruction to the active function. +// VSCALEFSD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VSCALEFSD.RZ_SAE.Z instruction to the active function. // Operates on the global context. -func VPCMPGTD(mxy, xy, xy1 operand.Op) { ctx.VPCMPGTD(mxy, xy, xy1) } +func VSCALEFSD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VSCALEFSD_RZ_SAE_Z(x, x1, k, x2) } -// VPCMPGTQ: Compare Packed Data for Greater Than. +// VSCALEFSD_Z: Scale Scalar Double-Precision Floating-Point Value With a Double-Precision Floating-Point Value (Zeroing Masking). // // Forms: // -// VPCMPGTQ xmm xmm xmm -// VPCMPGTQ m128 xmm xmm -// VPCMPGTQ ymm ymm ymm -// VPCMPGTQ m256 ymm ymm -// Construct and append a VPCMPGTQ instruction to the active function. -func (c *Context) VPCMPGTQ(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPCMPGTQ(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFSD.Z m64 xmm k xmm +// VSCALEFSD.Z xmm xmm k xmm +// Construct and append a VSCALEFSD.Z instruction to the active function. +func (c *Context) VSCALEFSD_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VSCALEFSD_Z(mx, x, k, x1)) } -// VPCMPGTQ: Compare Packed Data for Greater Than. +// VSCALEFSD_Z: Scale Scalar Double-Precision Floating-Point Value With a Double-Precision Floating-Point Value (Zeroing Masking). // // Forms: // -// VPCMPGTQ xmm xmm xmm -// VPCMPGTQ m128 xmm xmm -// VPCMPGTQ ymm ymm ymm -// VPCMPGTQ m256 ymm ymm -// Construct and append a VPCMPGTQ instruction to the active function. +// VSCALEFSD.Z m64 xmm k xmm +// VSCALEFSD.Z xmm xmm k xmm +// Construct and append a VSCALEFSD.Z instruction to the active function. // Operates on the global context. -func VPCMPGTQ(mxy, xy, xy1 operand.Op) { ctx.VPCMPGTQ(mxy, xy, xy1) } +func VSCALEFSD_Z(mx, x, k, x1 operand.Op) { ctx.VSCALEFSD_Z(mx, x, k, x1) } -// VPCMPGTW: Compare Packed Signed Word Integers for Greater Than. +// VSCALEFSS: Scale Scalar Single-Precision Floating-Point Value With a Single-Precision Floating-Point Value. // // Forms: // -// VPCMPGTW xmm xmm xmm -// VPCMPGTW m128 xmm xmm -// VPCMPGTW ymm ymm ymm -// VPCMPGTW m256 ymm ymm -// Construct and append a VPCMPGTW instruction to the active function. -func (c *Context) VPCMPGTW(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPCMPGTW(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFSS m32 xmm k xmm +// VSCALEFSS m32 xmm xmm +// VSCALEFSS xmm xmm k xmm +// VSCALEFSS xmm xmm xmm +// Construct and append a VSCALEFSS instruction to the active function. +func (c *Context) VSCALEFSS(ops ...operand.Op) { + c.addinstruction(x86.VSCALEFSS(ops...)) } -// VPCMPGTW: Compare Packed Signed Word Integers for Greater Than. +// VSCALEFSS: Scale Scalar Single-Precision Floating-Point Value With a Single-Precision Floating-Point Value. // // Forms: // -// VPCMPGTW xmm xmm xmm -// VPCMPGTW m128 xmm xmm -// VPCMPGTW ymm ymm ymm -// VPCMPGTW m256 ymm ymm -// Construct and append a VPCMPGTW instruction to the active function. +// VSCALEFSS m32 xmm k xmm +// VSCALEFSS m32 xmm xmm +// VSCALEFSS xmm xmm k xmm +// VSCALEFSS xmm xmm xmm +// Construct and append a VSCALEFSS instruction to the active function. // Operates on the global context. -func VPCMPGTW(mxy, xy, xy1 operand.Op) { ctx.VPCMPGTW(mxy, xy, xy1) } +func VSCALEFSS(ops ...operand.Op) { ctx.VSCALEFSS(ops...) } -// VPCMPISTRI: Packed Compare Implicit Length Strings, Return Index. +// VSCALEFSS_RD_SAE: Scale Scalar Single-Precision Floating-Point Value With a Single-Precision Floating-Point Value (Round Towards Negative Infinity). // // Forms: // -// VPCMPISTRI imm8 xmm xmm -// VPCMPISTRI imm8 m128 xmm -// Construct and append a VPCMPISTRI instruction to the active function. -func (c *Context) VPCMPISTRI(i, mx, x operand.Op) { - if inst, err := x86.VPCMPISTRI(i, mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFSS.RD_SAE xmm xmm k xmm +// VSCALEFSS.RD_SAE xmm xmm xmm +// Construct and append a VSCALEFSS.RD_SAE instruction to the active function. +func (c *Context) VSCALEFSS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSCALEFSS_RD_SAE(ops...)) } -// VPCMPISTRI: Packed Compare Implicit Length Strings, Return Index. +// VSCALEFSS_RD_SAE: Scale Scalar Single-Precision Floating-Point Value With a Single-Precision Floating-Point Value (Round Towards Negative Infinity). // // Forms: // -// VPCMPISTRI imm8 xmm xmm -// VPCMPISTRI imm8 m128 xmm -// Construct and append a VPCMPISTRI instruction to the active function. +// VSCALEFSS.RD_SAE xmm xmm k xmm +// VSCALEFSS.RD_SAE xmm xmm xmm +// Construct and append a VSCALEFSS.RD_SAE instruction to the active function. // Operates on the global context. -func VPCMPISTRI(i, mx, x operand.Op) { ctx.VPCMPISTRI(i, mx, x) } +func VSCALEFSS_RD_SAE(ops ...operand.Op) { ctx.VSCALEFSS_RD_SAE(ops...) } -// VPCMPISTRM: Packed Compare Implicit Length Strings, Return Mask. +// VSCALEFSS_RD_SAE_Z: Scale Scalar Single-Precision Floating-Point Value With a Single-Precision Floating-Point Value (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VPCMPISTRM imm8 xmm xmm -// VPCMPISTRM imm8 m128 xmm -// Construct and append a VPCMPISTRM instruction to the active function. -func (c *Context) VPCMPISTRM(i, mx, x operand.Op) { - if inst, err := x86.VPCMPISTRM(i, mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFSS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VSCALEFSS.RD_SAE.Z instruction to the active function. +func (c *Context) VSCALEFSS_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VSCALEFSS_RD_SAE_Z(x, x1, k, x2)) } -// VPCMPISTRM: Packed Compare Implicit Length Strings, Return Mask. +// VSCALEFSS_RD_SAE_Z: Scale Scalar Single-Precision Floating-Point Value With a Single-Precision Floating-Point Value (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VPCMPISTRM imm8 xmm xmm -// VPCMPISTRM imm8 m128 xmm -// Construct and append a VPCMPISTRM instruction to the active function. +// VSCALEFSS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VSCALEFSS.RD_SAE.Z instruction to the active function. // Operates on the global context. -func VPCMPISTRM(i, mx, x operand.Op) { ctx.VPCMPISTRM(i, mx, x) } +func VSCALEFSS_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VSCALEFSS_RD_SAE_Z(x, x1, k, x2) } -// VPERM2F128: Permute Floating-Point Values. +// VSCALEFSS_RN_SAE: Scale Scalar Single-Precision Floating-Point Value With a Single-Precision Floating-Point Value (Round Towards Nearest). // // Forms: // -// VPERM2F128 imm8 ymm ymm ymm -// VPERM2F128 imm8 m256 ymm ymm -// Construct and append a VPERM2F128 instruction to the active function. -func (c *Context) VPERM2F128(i, my, y, y1 operand.Op) { - if inst, err := x86.VPERM2F128(i, my, y, y1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFSS.RN_SAE xmm xmm k xmm +// VSCALEFSS.RN_SAE xmm xmm xmm +// Construct and append a VSCALEFSS.RN_SAE instruction to the active function. +func (c *Context) VSCALEFSS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSCALEFSS_RN_SAE(ops...)) } -// VPERM2F128: Permute Floating-Point Values. +// VSCALEFSS_RN_SAE: Scale Scalar Single-Precision Floating-Point Value With a Single-Precision Floating-Point Value (Round Towards Nearest). // // Forms: // -// VPERM2F128 imm8 ymm ymm ymm -// VPERM2F128 imm8 m256 ymm ymm -// Construct and append a VPERM2F128 instruction to the active function. +// VSCALEFSS.RN_SAE xmm xmm k xmm +// VSCALEFSS.RN_SAE xmm xmm xmm +// Construct and append a VSCALEFSS.RN_SAE instruction to the active function. // Operates on the global context. -func VPERM2F128(i, my, y, y1 operand.Op) { ctx.VPERM2F128(i, my, y, y1) } +func VSCALEFSS_RN_SAE(ops ...operand.Op) { ctx.VSCALEFSS_RN_SAE(ops...) } -// VPERM2I128: Permute 128-Bit Integer Values. +// VSCALEFSS_RN_SAE_Z: Scale Scalar Single-Precision Floating-Point Value With a Single-Precision Floating-Point Value (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VPERM2I128 imm8 ymm ymm ymm -// VPERM2I128 imm8 m256 ymm ymm -// Construct and append a VPERM2I128 instruction to the active function. -func (c *Context) VPERM2I128(i, my, y, y1 operand.Op) { - if inst, err := x86.VPERM2I128(i, my, y, y1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFSS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VSCALEFSS.RN_SAE.Z instruction to the active function. +func (c *Context) VSCALEFSS_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VSCALEFSS_RN_SAE_Z(x, x1, k, x2)) } -// VPERM2I128: Permute 128-Bit Integer Values. +// VSCALEFSS_RN_SAE_Z: Scale Scalar Single-Precision Floating-Point Value With a Single-Precision Floating-Point Value (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VPERM2I128 imm8 ymm ymm ymm -// VPERM2I128 imm8 m256 ymm ymm -// Construct and append a VPERM2I128 instruction to the active function. +// VSCALEFSS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VSCALEFSS.RN_SAE.Z instruction to the active function. // Operates on the global context. -func VPERM2I128(i, my, y, y1 operand.Op) { ctx.VPERM2I128(i, my, y, y1) } +func VSCALEFSS_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VSCALEFSS_RN_SAE_Z(x, x1, k, x2) } -// VPERMD: Permute Doubleword Integers. +// VSCALEFSS_RU_SAE: Scale Scalar Single-Precision Floating-Point Value With a Single-Precision Floating-Point Value (Round Towards Positive Infinity). // // Forms: // -// VPERMD ymm ymm ymm -// VPERMD m256 ymm ymm -// Construct and append a VPERMD instruction to the active function. -func (c *Context) VPERMD(my, y, y1 operand.Op) { - if inst, err := x86.VPERMD(my, y, y1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFSS.RU_SAE xmm xmm k xmm +// VSCALEFSS.RU_SAE xmm xmm xmm +// Construct and append a VSCALEFSS.RU_SAE instruction to the active function. +func (c *Context) VSCALEFSS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSCALEFSS_RU_SAE(ops...)) } -// VPERMD: Permute Doubleword Integers. +// VSCALEFSS_RU_SAE: Scale Scalar Single-Precision Floating-Point Value With a Single-Precision Floating-Point Value (Round Towards Positive Infinity). // // Forms: // -// VPERMD ymm ymm ymm -// VPERMD m256 ymm ymm -// Construct and append a VPERMD instruction to the active function. +// VSCALEFSS.RU_SAE xmm xmm k xmm +// VSCALEFSS.RU_SAE xmm xmm xmm +// Construct and append a VSCALEFSS.RU_SAE instruction to the active function. // Operates on the global context. -func VPERMD(my, y, y1 operand.Op) { ctx.VPERMD(my, y, y1) } +func VSCALEFSS_RU_SAE(ops ...operand.Op) { ctx.VSCALEFSS_RU_SAE(ops...) } -// VPERMILPD: Permute Double-Precision Floating-Point Values. +// VSCALEFSS_RU_SAE_Z: Scale Scalar Single-Precision Floating-Point Value With a Single-Precision Floating-Point Value (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VPERMILPD imm8 xmm xmm -// VPERMILPD xmm xmm xmm -// VPERMILPD m128 xmm xmm -// VPERMILPD imm8 m128 xmm -// VPERMILPD imm8 ymm ymm -// VPERMILPD ymm ymm ymm -// VPERMILPD m256 ymm ymm -// VPERMILPD imm8 m256 ymm -// Construct and append a VPERMILPD instruction to the active function. -func (c *Context) VPERMILPD(imxy, mxy, xy operand.Op) { - if inst, err := x86.VPERMILPD(imxy, mxy, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFSS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VSCALEFSS.RU_SAE.Z instruction to the active function. +func (c *Context) VSCALEFSS_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VSCALEFSS_RU_SAE_Z(x, x1, k, x2)) } -// VPERMILPD: Permute Double-Precision Floating-Point Values. +// VSCALEFSS_RU_SAE_Z: Scale Scalar Single-Precision Floating-Point Value With a Single-Precision Floating-Point Value (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VPERMILPD imm8 xmm xmm -// VPERMILPD xmm xmm xmm -// VPERMILPD m128 xmm xmm -// VPERMILPD imm8 m128 xmm -// VPERMILPD imm8 ymm ymm -// VPERMILPD ymm ymm ymm -// VPERMILPD m256 ymm ymm -// VPERMILPD imm8 m256 ymm -// Construct and append a VPERMILPD instruction to the active function. +// VSCALEFSS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VSCALEFSS.RU_SAE.Z instruction to the active function. // Operates on the global context. -func VPERMILPD(imxy, mxy, xy operand.Op) { ctx.VPERMILPD(imxy, mxy, xy) } +func VSCALEFSS_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VSCALEFSS_RU_SAE_Z(x, x1, k, x2) } -// VPERMILPS: Permute Single-Precision Floating-Point Values. +// VSCALEFSS_RZ_SAE: Scale Scalar Single-Precision Floating-Point Value With a Single-Precision Floating-Point Value (Round Towards Zero). // // Forms: // -// VPERMILPS imm8 xmm xmm -// VPERMILPS xmm xmm xmm -// VPERMILPS m128 xmm xmm -// VPERMILPS imm8 m128 xmm -// VPERMILPS imm8 ymm ymm -// VPERMILPS ymm ymm ymm -// VPERMILPS m256 ymm ymm -// VPERMILPS imm8 m256 ymm -// Construct and append a VPERMILPS instruction to the active function. -func (c *Context) VPERMILPS(imxy, mxy, xy operand.Op) { - if inst, err := x86.VPERMILPS(imxy, mxy, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFSS.RZ_SAE xmm xmm k xmm +// VSCALEFSS.RZ_SAE xmm xmm xmm +// Construct and append a VSCALEFSS.RZ_SAE instruction to the active function. +func (c *Context) VSCALEFSS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSCALEFSS_RZ_SAE(ops...)) } -// VPERMILPS: Permute Single-Precision Floating-Point Values. +// VSCALEFSS_RZ_SAE: Scale Scalar Single-Precision Floating-Point Value With a Single-Precision Floating-Point Value (Round Towards Zero). // // Forms: // -// VPERMILPS imm8 xmm xmm -// VPERMILPS xmm xmm xmm -// VPERMILPS m128 xmm xmm -// VPERMILPS imm8 m128 xmm -// VPERMILPS imm8 ymm ymm -// VPERMILPS ymm ymm ymm -// VPERMILPS m256 ymm ymm -// VPERMILPS imm8 m256 ymm -// Construct and append a VPERMILPS instruction to the active function. +// VSCALEFSS.RZ_SAE xmm xmm k xmm +// VSCALEFSS.RZ_SAE xmm xmm xmm +// Construct and append a VSCALEFSS.RZ_SAE instruction to the active function. // Operates on the global context. -func VPERMILPS(imxy, mxy, xy operand.Op) { ctx.VPERMILPS(imxy, mxy, xy) } +func VSCALEFSS_RZ_SAE(ops ...operand.Op) { ctx.VSCALEFSS_RZ_SAE(ops...) } -// VPERMPD: Permute Double-Precision Floating-Point Elements. +// VSCALEFSS_RZ_SAE_Z: Scale Scalar Single-Precision Floating-Point Value With a Single-Precision Floating-Point Value (Round Towards Zero, Zeroing Masking). // // Forms: // -// VPERMPD imm8 ymm ymm -// VPERMPD imm8 m256 ymm -// Construct and append a VPERMPD instruction to the active function. -func (c *Context) VPERMPD(i, my, y operand.Op) { - if inst, err := x86.VPERMPD(i, my, y); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFSS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VSCALEFSS.RZ_SAE.Z instruction to the active function. +func (c *Context) VSCALEFSS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VSCALEFSS_RZ_SAE_Z(x, x1, k, x2)) } -// VPERMPD: Permute Double-Precision Floating-Point Elements. +// VSCALEFSS_RZ_SAE_Z: Scale Scalar Single-Precision Floating-Point Value With a Single-Precision Floating-Point Value (Round Towards Zero, Zeroing Masking). // // Forms: // -// VPERMPD imm8 ymm ymm -// VPERMPD imm8 m256 ymm -// Construct and append a VPERMPD instruction to the active function. +// VSCALEFSS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VSCALEFSS.RZ_SAE.Z instruction to the active function. // Operates on the global context. -func VPERMPD(i, my, y operand.Op) { ctx.VPERMPD(i, my, y) } +func VSCALEFSS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VSCALEFSS_RZ_SAE_Z(x, x1, k, x2) } -// VPERMPS: Permute Single-Precision Floating-Point Elements. +// VSCALEFSS_Z: Scale Scalar Single-Precision Floating-Point Value With a Single-Precision Floating-Point Value (Zeroing Masking). // // Forms: // -// VPERMPS ymm ymm ymm -// VPERMPS m256 ymm ymm -// Construct and append a VPERMPS instruction to the active function. -func (c *Context) VPERMPS(my, y, y1 operand.Op) { - if inst, err := x86.VPERMPS(my, y, y1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCALEFSS.Z m32 xmm k xmm +// VSCALEFSS.Z xmm xmm k xmm +// Construct and append a VSCALEFSS.Z instruction to the active function. +func (c *Context) VSCALEFSS_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VSCALEFSS_Z(mx, x, k, x1)) } -// VPERMPS: Permute Single-Precision Floating-Point Elements. +// VSCALEFSS_Z: Scale Scalar Single-Precision Floating-Point Value With a Single-Precision Floating-Point Value (Zeroing Masking). // // Forms: // -// VPERMPS ymm ymm ymm -// VPERMPS m256 ymm ymm -// Construct and append a VPERMPS instruction to the active function. +// VSCALEFSS.Z m32 xmm k xmm +// VSCALEFSS.Z xmm xmm k xmm +// Construct and append a VSCALEFSS.Z instruction to the active function. // Operates on the global context. -func VPERMPS(my, y, y1 operand.Op) { ctx.VPERMPS(my, y, y1) } +func VSCALEFSS_Z(mx, x, k, x1 operand.Op) { ctx.VSCALEFSS_Z(mx, x, k, x1) } -// VPERMQ: Permute Quadword Integers. +// VSCATTERDPD: Scatter Packed Double-Precision Floating-Point Values with Signed Doubleword Indices. // // Forms: // -// VPERMQ imm8 ymm ymm -// VPERMQ imm8 m256 ymm -// Construct and append a VPERMQ instruction to the active function. -func (c *Context) VPERMQ(i, my, y operand.Op) { - if inst, err := x86.VPERMQ(i, my, y); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCATTERDPD xmm k vm32x +// VSCATTERDPD ymm k vm32x +// VSCATTERDPD zmm k vm32y +// Construct and append a VSCATTERDPD instruction to the active function. +func (c *Context) VSCATTERDPD(xyz, k, v operand.Op) { + c.addinstruction(x86.VSCATTERDPD(xyz, k, v)) } -// VPERMQ: Permute Quadword Integers. +// VSCATTERDPD: Scatter Packed Double-Precision Floating-Point Values with Signed Doubleword Indices. // // Forms: // -// VPERMQ imm8 ymm ymm -// VPERMQ imm8 m256 ymm -// Construct and append a VPERMQ instruction to the active function. +// VSCATTERDPD xmm k vm32x +// VSCATTERDPD ymm k vm32x +// VSCATTERDPD zmm k vm32y +// Construct and append a VSCATTERDPD instruction to the active function. // Operates on the global context. -func VPERMQ(i, my, y operand.Op) { ctx.VPERMQ(i, my, y) } +func VSCATTERDPD(xyz, k, v operand.Op) { ctx.VSCATTERDPD(xyz, k, v) } -// VPEXTRB: Extract Byte. +// VSCATTERDPS: Scatter Packed Single-Precision Floating-Point Values with Signed Doubleword Indices. // // Forms: // -// VPEXTRB imm8 xmm r32 -// VPEXTRB imm8 xmm m8 -// Construct and append a VPEXTRB instruction to the active function. -func (c *Context) VPEXTRB(i, x, mr operand.Op) { - if inst, err := x86.VPEXTRB(i, x, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCATTERDPS xmm k vm32x +// VSCATTERDPS ymm k vm32y +// VSCATTERDPS zmm k vm32z +// Construct and append a VSCATTERDPS instruction to the active function. +func (c *Context) VSCATTERDPS(xyz, k, v operand.Op) { + c.addinstruction(x86.VSCATTERDPS(xyz, k, v)) } -// VPEXTRB: Extract Byte. +// VSCATTERDPS: Scatter Packed Single-Precision Floating-Point Values with Signed Doubleword Indices. // // Forms: // -// VPEXTRB imm8 xmm r32 -// VPEXTRB imm8 xmm m8 -// Construct and append a VPEXTRB instruction to the active function. +// VSCATTERDPS xmm k vm32x +// VSCATTERDPS ymm k vm32y +// VSCATTERDPS zmm k vm32z +// Construct and append a VSCATTERDPS instruction to the active function. // Operates on the global context. -func VPEXTRB(i, x, mr operand.Op) { ctx.VPEXTRB(i, x, mr) } +func VSCATTERDPS(xyz, k, v operand.Op) { ctx.VSCATTERDPS(xyz, k, v) } -// VPEXTRD: Extract Doubleword. +// VSCATTERQPD: Scatter Packed Double-Precision Floating-Point Values with Signed Quadword Indices. // // Forms: // -// VPEXTRD imm8 xmm r32 -// VPEXTRD imm8 xmm m32 -// Construct and append a VPEXTRD instruction to the active function. -func (c *Context) VPEXTRD(i, x, mr operand.Op) { - if inst, err := x86.VPEXTRD(i, x, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCATTERQPD xmm k vm64x +// VSCATTERQPD ymm k vm64y +// VSCATTERQPD zmm k vm64z +// Construct and append a VSCATTERQPD instruction to the active function. +func (c *Context) VSCATTERQPD(xyz, k, v operand.Op) { + c.addinstruction(x86.VSCATTERQPD(xyz, k, v)) } -// VPEXTRD: Extract Doubleword. +// VSCATTERQPD: Scatter Packed Double-Precision Floating-Point Values with Signed Quadword Indices. // // Forms: // -// VPEXTRD imm8 xmm r32 -// VPEXTRD imm8 xmm m32 -// Construct and append a VPEXTRD instruction to the active function. +// VSCATTERQPD xmm k vm64x +// VSCATTERQPD ymm k vm64y +// VSCATTERQPD zmm k vm64z +// Construct and append a VSCATTERQPD instruction to the active function. // Operates on the global context. -func VPEXTRD(i, x, mr operand.Op) { ctx.VPEXTRD(i, x, mr) } +func VSCATTERQPD(xyz, k, v operand.Op) { ctx.VSCATTERQPD(xyz, k, v) } -// VPEXTRQ: Extract Quadword. +// VSCATTERQPS: Scatter Packed Single-Precision Floating-Point Values with Signed Quadword Indices. // // Forms: // -// VPEXTRQ imm8 xmm r64 -// VPEXTRQ imm8 xmm m64 -// Construct and append a VPEXTRQ instruction to the active function. -func (c *Context) VPEXTRQ(i, x, mr operand.Op) { - if inst, err := x86.VPEXTRQ(i, x, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSCATTERQPS xmm k vm64x +// VSCATTERQPS xmm k vm64y +// VSCATTERQPS ymm k vm64z +// Construct and append a VSCATTERQPS instruction to the active function. +func (c *Context) VSCATTERQPS(xy, k, v operand.Op) { + c.addinstruction(x86.VSCATTERQPS(xy, k, v)) } -// VPEXTRQ: Extract Quadword. +// VSCATTERQPS: Scatter Packed Single-Precision Floating-Point Values with Signed Quadword Indices. // // Forms: // -// VPEXTRQ imm8 xmm r64 -// VPEXTRQ imm8 xmm m64 -// Construct and append a VPEXTRQ instruction to the active function. +// VSCATTERQPS xmm k vm64x +// VSCATTERQPS xmm k vm64y +// VSCATTERQPS ymm k vm64z +// Construct and append a VSCATTERQPS instruction to the active function. // Operates on the global context. -func VPEXTRQ(i, x, mr operand.Op) { ctx.VPEXTRQ(i, x, mr) } +func VSCATTERQPS(xy, k, v operand.Op) { ctx.VSCATTERQPS(xy, k, v) } -// VPEXTRW: Extract Word. +// VSHUFF32X4: Shuffle 128-Bit Packed Single-Precision Floating-Point Values. // // Forms: // -// VPEXTRW imm8 xmm r32 -// VPEXTRW imm8 xmm m16 -// Construct and append a VPEXTRW instruction to the active function. -func (c *Context) VPEXTRW(i, x, mr operand.Op) { - if inst, err := x86.VPEXTRW(i, x, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSHUFF32X4 imm8 m256 ymm k ymm +// VSHUFF32X4 imm8 m256 ymm ymm +// VSHUFF32X4 imm8 ymm ymm k ymm +// VSHUFF32X4 imm8 ymm ymm ymm +// VSHUFF32X4 imm8 m512 zmm k zmm +// VSHUFF32X4 imm8 m512 zmm zmm +// VSHUFF32X4 imm8 zmm zmm k zmm +// VSHUFF32X4 imm8 zmm zmm zmm +// Construct and append a VSHUFF32X4 instruction to the active function. +func (c *Context) VSHUFF32X4(ops ...operand.Op) { + c.addinstruction(x86.VSHUFF32X4(ops...)) } -// VPEXTRW: Extract Word. +// VSHUFF32X4: Shuffle 128-Bit Packed Single-Precision Floating-Point Values. // // Forms: // -// VPEXTRW imm8 xmm r32 -// VPEXTRW imm8 xmm m16 -// Construct and append a VPEXTRW instruction to the active function. +// VSHUFF32X4 imm8 m256 ymm k ymm +// VSHUFF32X4 imm8 m256 ymm ymm +// VSHUFF32X4 imm8 ymm ymm k ymm +// VSHUFF32X4 imm8 ymm ymm ymm +// VSHUFF32X4 imm8 m512 zmm k zmm +// VSHUFF32X4 imm8 m512 zmm zmm +// VSHUFF32X4 imm8 zmm zmm k zmm +// VSHUFF32X4 imm8 zmm zmm zmm +// Construct and append a VSHUFF32X4 instruction to the active function. // Operates on the global context. -func VPEXTRW(i, x, mr operand.Op) { ctx.VPEXTRW(i, x, mr) } +func VSHUFF32X4(ops ...operand.Op) { ctx.VSHUFF32X4(ops...) } -// VPGATHERDD: Gather Packed Doubleword Values Using Signed Doubleword Indices. +// VSHUFF32X4_BCST: Shuffle 128-Bit Packed Single-Precision Floating-Point Values (Broadcast). // // Forms: // -// VPGATHERDD xmm vm32x xmm -// VPGATHERDD ymm vm32y ymm -// Construct and append a VPGATHERDD instruction to the active function. -func (c *Context) VPGATHERDD(xy, v, xy1 operand.Op) { - if inst, err := x86.VPGATHERDD(xy, v, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSHUFF32X4.BCST imm8 m32 ymm k ymm +// VSHUFF32X4.BCST imm8 m32 ymm ymm +// VSHUFF32X4.BCST imm8 m32 zmm k zmm +// VSHUFF32X4.BCST imm8 m32 zmm zmm +// Construct and append a VSHUFF32X4.BCST instruction to the active function. +func (c *Context) VSHUFF32X4_BCST(ops ...operand.Op) { + c.addinstruction(x86.VSHUFF32X4_BCST(ops...)) } -// VPGATHERDD: Gather Packed Doubleword Values Using Signed Doubleword Indices. +// VSHUFF32X4_BCST: Shuffle 128-Bit Packed Single-Precision Floating-Point Values (Broadcast). // // Forms: // -// VPGATHERDD xmm vm32x xmm -// VPGATHERDD ymm vm32y ymm -// Construct and append a VPGATHERDD instruction to the active function. +// VSHUFF32X4.BCST imm8 m32 ymm k ymm +// VSHUFF32X4.BCST imm8 m32 ymm ymm +// VSHUFF32X4.BCST imm8 m32 zmm k zmm +// VSHUFF32X4.BCST imm8 m32 zmm zmm +// Construct and append a VSHUFF32X4.BCST instruction to the active function. // Operates on the global context. -func VPGATHERDD(xy, v, xy1 operand.Op) { ctx.VPGATHERDD(xy, v, xy1) } +func VSHUFF32X4_BCST(ops ...operand.Op) { ctx.VSHUFF32X4_BCST(ops...) } -// VPGATHERDQ: Gather Packed Quadword Values Using Signed Doubleword Indices. +// VSHUFF32X4_BCST_Z: Shuffle 128-Bit Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VPGATHERDQ xmm vm32x xmm -// VPGATHERDQ ymm vm32x ymm -// Construct and append a VPGATHERDQ instruction to the active function. -func (c *Context) VPGATHERDQ(xy, v, xy1 operand.Op) { - if inst, err := x86.VPGATHERDQ(xy, v, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSHUFF32X4.BCST.Z imm8 m32 ymm k ymm +// VSHUFF32X4.BCST.Z imm8 m32 zmm k zmm +// Construct and append a VSHUFF32X4.BCST.Z instruction to the active function. +func (c *Context) VSHUFF32X4_BCST_Z(i, m, yz, k, yz1 operand.Op) { + c.addinstruction(x86.VSHUFF32X4_BCST_Z(i, m, yz, k, yz1)) } -// VPGATHERDQ: Gather Packed Quadword Values Using Signed Doubleword Indices. +// VSHUFF32X4_BCST_Z: Shuffle 128-Bit Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VPGATHERDQ xmm vm32x xmm -// VPGATHERDQ ymm vm32x ymm -// Construct and append a VPGATHERDQ instruction to the active function. +// VSHUFF32X4.BCST.Z imm8 m32 ymm k ymm +// VSHUFF32X4.BCST.Z imm8 m32 zmm k zmm +// Construct and append a VSHUFF32X4.BCST.Z instruction to the active function. // Operates on the global context. -func VPGATHERDQ(xy, v, xy1 operand.Op) { ctx.VPGATHERDQ(xy, v, xy1) } +func VSHUFF32X4_BCST_Z(i, m, yz, k, yz1 operand.Op) { ctx.VSHUFF32X4_BCST_Z(i, m, yz, k, yz1) } -// VPGATHERQD: Gather Packed Doubleword Values Using Signed Quadword Indices. +// VSHUFF32X4_Z: Shuffle 128-Bit Packed Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VPGATHERQD xmm vm64x xmm -// VPGATHERQD xmm vm64y xmm -// Construct and append a VPGATHERQD instruction to the active function. -func (c *Context) VPGATHERQD(x, v, x1 operand.Op) { - if inst, err := x86.VPGATHERQD(x, v, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSHUFF32X4.Z imm8 m256 ymm k ymm +// VSHUFF32X4.Z imm8 ymm ymm k ymm +// VSHUFF32X4.Z imm8 m512 zmm k zmm +// VSHUFF32X4.Z imm8 zmm zmm k zmm +// Construct and append a VSHUFF32X4.Z instruction to the active function. +func (c *Context) VSHUFF32X4_Z(i, myz, yz, k, yz1 operand.Op) { + c.addinstruction(x86.VSHUFF32X4_Z(i, myz, yz, k, yz1)) } -// VPGATHERQD: Gather Packed Doubleword Values Using Signed Quadword Indices. +// VSHUFF32X4_Z: Shuffle 128-Bit Packed Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VPGATHERQD xmm vm64x xmm -// VPGATHERQD xmm vm64y xmm -// Construct and append a VPGATHERQD instruction to the active function. +// VSHUFF32X4.Z imm8 m256 ymm k ymm +// VSHUFF32X4.Z imm8 ymm ymm k ymm +// VSHUFF32X4.Z imm8 m512 zmm k zmm +// VSHUFF32X4.Z imm8 zmm zmm k zmm +// Construct and append a VSHUFF32X4.Z instruction to the active function. // Operates on the global context. -func VPGATHERQD(x, v, x1 operand.Op) { ctx.VPGATHERQD(x, v, x1) } +func VSHUFF32X4_Z(i, myz, yz, k, yz1 operand.Op) { ctx.VSHUFF32X4_Z(i, myz, yz, k, yz1) } -// VPGATHERQQ: Gather Packed Quadword Values Using Signed Quadword Indices. +// VSHUFF64X2: Shuffle 128-Bit Packed Double-Precision Floating-Point Values. // // Forms: // -// VPGATHERQQ xmm vm64x xmm -// VPGATHERQQ ymm vm64y ymm -// Construct and append a VPGATHERQQ instruction to the active function. -func (c *Context) VPGATHERQQ(xy, v, xy1 operand.Op) { - if inst, err := x86.VPGATHERQQ(xy, v, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSHUFF64X2 imm8 m256 ymm k ymm +// VSHUFF64X2 imm8 m256 ymm ymm +// VSHUFF64X2 imm8 ymm ymm k ymm +// VSHUFF64X2 imm8 ymm ymm ymm +// VSHUFF64X2 imm8 m512 zmm k zmm +// VSHUFF64X2 imm8 m512 zmm zmm +// VSHUFF64X2 imm8 zmm zmm k zmm +// VSHUFF64X2 imm8 zmm zmm zmm +// Construct and append a VSHUFF64X2 instruction to the active function. +func (c *Context) VSHUFF64X2(ops ...operand.Op) { + c.addinstruction(x86.VSHUFF64X2(ops...)) } -// VPGATHERQQ: Gather Packed Quadword Values Using Signed Quadword Indices. +// VSHUFF64X2: Shuffle 128-Bit Packed Double-Precision Floating-Point Values. // // Forms: // -// VPGATHERQQ xmm vm64x xmm -// VPGATHERQQ ymm vm64y ymm -// Construct and append a VPGATHERQQ instruction to the active function. +// VSHUFF64X2 imm8 m256 ymm k ymm +// VSHUFF64X2 imm8 m256 ymm ymm +// VSHUFF64X2 imm8 ymm ymm k ymm +// VSHUFF64X2 imm8 ymm ymm ymm +// VSHUFF64X2 imm8 m512 zmm k zmm +// VSHUFF64X2 imm8 m512 zmm zmm +// VSHUFF64X2 imm8 zmm zmm k zmm +// VSHUFF64X2 imm8 zmm zmm zmm +// Construct and append a VSHUFF64X2 instruction to the active function. // Operates on the global context. -func VPGATHERQQ(xy, v, xy1 operand.Op) { ctx.VPGATHERQQ(xy, v, xy1) } +func VSHUFF64X2(ops ...operand.Op) { ctx.VSHUFF64X2(ops...) } -// VPHADDD: Packed Horizontal Add Doubleword Integer. +// VSHUFF64X2_BCST: Shuffle 128-Bit Packed Double-Precision Floating-Point Values (Broadcast). // // Forms: // -// VPHADDD xmm xmm xmm -// VPHADDD m128 xmm xmm -// VPHADDD ymm ymm ymm -// VPHADDD m256 ymm ymm -// Construct and append a VPHADDD instruction to the active function. -func (c *Context) VPHADDD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPHADDD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSHUFF64X2.BCST imm8 m64 ymm k ymm +// VSHUFF64X2.BCST imm8 m64 ymm ymm +// VSHUFF64X2.BCST imm8 m64 zmm k zmm +// VSHUFF64X2.BCST imm8 m64 zmm zmm +// Construct and append a VSHUFF64X2.BCST instruction to the active function. +func (c *Context) VSHUFF64X2_BCST(ops ...operand.Op) { + c.addinstruction(x86.VSHUFF64X2_BCST(ops...)) } -// VPHADDD: Packed Horizontal Add Doubleword Integer. +// VSHUFF64X2_BCST: Shuffle 128-Bit Packed Double-Precision Floating-Point Values (Broadcast). // // Forms: // -// VPHADDD xmm xmm xmm -// VPHADDD m128 xmm xmm -// VPHADDD ymm ymm ymm -// VPHADDD m256 ymm ymm -// Construct and append a VPHADDD instruction to the active function. +// VSHUFF64X2.BCST imm8 m64 ymm k ymm +// VSHUFF64X2.BCST imm8 m64 ymm ymm +// VSHUFF64X2.BCST imm8 m64 zmm k zmm +// VSHUFF64X2.BCST imm8 m64 zmm zmm +// Construct and append a VSHUFF64X2.BCST instruction to the active function. // Operates on the global context. -func VPHADDD(mxy, xy, xy1 operand.Op) { ctx.VPHADDD(mxy, xy, xy1) } +func VSHUFF64X2_BCST(ops ...operand.Op) { ctx.VSHUFF64X2_BCST(ops...) } -// VPHADDSW: Packed Horizontal Add Signed Word Integers with Signed Saturation. +// VSHUFF64X2_BCST_Z: Shuffle 128-Bit Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VPHADDSW xmm xmm xmm -// VPHADDSW m128 xmm xmm -// VPHADDSW ymm ymm ymm -// VPHADDSW m256 ymm ymm -// Construct and append a VPHADDSW instruction to the active function. -func (c *Context) VPHADDSW(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPHADDSW(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSHUFF64X2.BCST.Z imm8 m64 ymm k ymm +// VSHUFF64X2.BCST.Z imm8 m64 zmm k zmm +// Construct and append a VSHUFF64X2.BCST.Z instruction to the active function. +func (c *Context) VSHUFF64X2_BCST_Z(i, m, yz, k, yz1 operand.Op) { + c.addinstruction(x86.VSHUFF64X2_BCST_Z(i, m, yz, k, yz1)) } -// VPHADDSW: Packed Horizontal Add Signed Word Integers with Signed Saturation. +// VSHUFF64X2_BCST_Z: Shuffle 128-Bit Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VPHADDSW xmm xmm xmm -// VPHADDSW m128 xmm xmm -// VPHADDSW ymm ymm ymm -// VPHADDSW m256 ymm ymm -// Construct and append a VPHADDSW instruction to the active function. +// VSHUFF64X2.BCST.Z imm8 m64 ymm k ymm +// VSHUFF64X2.BCST.Z imm8 m64 zmm k zmm +// Construct and append a VSHUFF64X2.BCST.Z instruction to the active function. // Operates on the global context. -func VPHADDSW(mxy, xy, xy1 operand.Op) { ctx.VPHADDSW(mxy, xy, xy1) } +func VSHUFF64X2_BCST_Z(i, m, yz, k, yz1 operand.Op) { ctx.VSHUFF64X2_BCST_Z(i, m, yz, k, yz1) } -// VPHADDW: Packed Horizontal Add Word Integers. -// -// Forms: +// VSHUFF64X2_Z: Shuffle 128-Bit Packed Double-Precision Floating-Point Values (Zeroing Masking). // -// VPHADDW xmm xmm xmm -// VPHADDW m128 xmm xmm -// VPHADDW ymm ymm ymm -// VPHADDW m256 ymm ymm -// Construct and append a VPHADDW instruction to the active function. -func (c *Context) VPHADDW(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPHADDW(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// Forms: +// +// VSHUFF64X2.Z imm8 m256 ymm k ymm +// VSHUFF64X2.Z imm8 ymm ymm k ymm +// VSHUFF64X2.Z imm8 m512 zmm k zmm +// VSHUFF64X2.Z imm8 zmm zmm k zmm +// Construct and append a VSHUFF64X2.Z instruction to the active function. +func (c *Context) VSHUFF64X2_Z(i, myz, yz, k, yz1 operand.Op) { + c.addinstruction(x86.VSHUFF64X2_Z(i, myz, yz, k, yz1)) } -// VPHADDW: Packed Horizontal Add Word Integers. +// VSHUFF64X2_Z: Shuffle 128-Bit Packed Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VPHADDW xmm xmm xmm -// VPHADDW m128 xmm xmm -// VPHADDW ymm ymm ymm -// VPHADDW m256 ymm ymm -// Construct and append a VPHADDW instruction to the active function. +// VSHUFF64X2.Z imm8 m256 ymm k ymm +// VSHUFF64X2.Z imm8 ymm ymm k ymm +// VSHUFF64X2.Z imm8 m512 zmm k zmm +// VSHUFF64X2.Z imm8 zmm zmm k zmm +// Construct and append a VSHUFF64X2.Z instruction to the active function. // Operates on the global context. -func VPHADDW(mxy, xy, xy1 operand.Op) { ctx.VPHADDW(mxy, xy, xy1) } +func VSHUFF64X2_Z(i, myz, yz, k, yz1 operand.Op) { ctx.VSHUFF64X2_Z(i, myz, yz, k, yz1) } -// VPHMINPOSUW: Packed Horizontal Minimum of Unsigned Word Integers. +// VSHUFI32X4: Shuffle 128-Bit Packed Doubleword Integer Values. // // Forms: // -// VPHMINPOSUW xmm xmm -// VPHMINPOSUW m128 xmm -// Construct and append a VPHMINPOSUW instruction to the active function. -func (c *Context) VPHMINPOSUW(mx, x operand.Op) { - if inst, err := x86.VPHMINPOSUW(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSHUFI32X4 imm8 m256 ymm k ymm +// VSHUFI32X4 imm8 m256 ymm ymm +// VSHUFI32X4 imm8 ymm ymm k ymm +// VSHUFI32X4 imm8 ymm ymm ymm +// VSHUFI32X4 imm8 m512 zmm k zmm +// VSHUFI32X4 imm8 m512 zmm zmm +// VSHUFI32X4 imm8 zmm zmm k zmm +// VSHUFI32X4 imm8 zmm zmm zmm +// Construct and append a VSHUFI32X4 instruction to the active function. +func (c *Context) VSHUFI32X4(ops ...operand.Op) { + c.addinstruction(x86.VSHUFI32X4(ops...)) } -// VPHMINPOSUW: Packed Horizontal Minimum of Unsigned Word Integers. +// VSHUFI32X4: Shuffle 128-Bit Packed Doubleword Integer Values. // // Forms: // -// VPHMINPOSUW xmm xmm -// VPHMINPOSUW m128 xmm -// Construct and append a VPHMINPOSUW instruction to the active function. +// VSHUFI32X4 imm8 m256 ymm k ymm +// VSHUFI32X4 imm8 m256 ymm ymm +// VSHUFI32X4 imm8 ymm ymm k ymm +// VSHUFI32X4 imm8 ymm ymm ymm +// VSHUFI32X4 imm8 m512 zmm k zmm +// VSHUFI32X4 imm8 m512 zmm zmm +// VSHUFI32X4 imm8 zmm zmm k zmm +// VSHUFI32X4 imm8 zmm zmm zmm +// Construct and append a VSHUFI32X4 instruction to the active function. // Operates on the global context. -func VPHMINPOSUW(mx, x operand.Op) { ctx.VPHMINPOSUW(mx, x) } +func VSHUFI32X4(ops ...operand.Op) { ctx.VSHUFI32X4(ops...) } -// VPHSUBD: Packed Horizontal Subtract Doubleword Integers. +// VSHUFI32X4_BCST: Shuffle 128-Bit Packed Doubleword Integer Values (Broadcast). // // Forms: // -// VPHSUBD xmm xmm xmm -// VPHSUBD m128 xmm xmm -// VPHSUBD ymm ymm ymm -// VPHSUBD m256 ymm ymm -// Construct and append a VPHSUBD instruction to the active function. -func (c *Context) VPHSUBD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPHSUBD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSHUFI32X4.BCST imm8 m32 ymm k ymm +// VSHUFI32X4.BCST imm8 m32 ymm ymm +// VSHUFI32X4.BCST imm8 m32 zmm k zmm +// VSHUFI32X4.BCST imm8 m32 zmm zmm +// Construct and append a VSHUFI32X4.BCST instruction to the active function. +func (c *Context) VSHUFI32X4_BCST(ops ...operand.Op) { + c.addinstruction(x86.VSHUFI32X4_BCST(ops...)) } -// VPHSUBD: Packed Horizontal Subtract Doubleword Integers. +// VSHUFI32X4_BCST: Shuffle 128-Bit Packed Doubleword Integer Values (Broadcast). // // Forms: // -// VPHSUBD xmm xmm xmm -// VPHSUBD m128 xmm xmm -// VPHSUBD ymm ymm ymm -// VPHSUBD m256 ymm ymm -// Construct and append a VPHSUBD instruction to the active function. +// VSHUFI32X4.BCST imm8 m32 ymm k ymm +// VSHUFI32X4.BCST imm8 m32 ymm ymm +// VSHUFI32X4.BCST imm8 m32 zmm k zmm +// VSHUFI32X4.BCST imm8 m32 zmm zmm +// Construct and append a VSHUFI32X4.BCST instruction to the active function. // Operates on the global context. -func VPHSUBD(mxy, xy, xy1 operand.Op) { ctx.VPHSUBD(mxy, xy, xy1) } +func VSHUFI32X4_BCST(ops ...operand.Op) { ctx.VSHUFI32X4_BCST(ops...) } -// VPHSUBSW: Packed Horizontal Subtract Signed Word Integers with Signed Saturation. +// VSHUFI32X4_BCST_Z: Shuffle 128-Bit Packed Doubleword Integer Values (Broadcast, Zeroing Masking). // // Forms: // -// VPHSUBSW xmm xmm xmm -// VPHSUBSW m128 xmm xmm -// VPHSUBSW ymm ymm ymm -// VPHSUBSW m256 ymm ymm -// Construct and append a VPHSUBSW instruction to the active function. -func (c *Context) VPHSUBSW(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPHSUBSW(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSHUFI32X4.BCST.Z imm8 m32 ymm k ymm +// VSHUFI32X4.BCST.Z imm8 m32 zmm k zmm +// Construct and append a VSHUFI32X4.BCST.Z instruction to the active function. +func (c *Context) VSHUFI32X4_BCST_Z(i, m, yz, k, yz1 operand.Op) { + c.addinstruction(x86.VSHUFI32X4_BCST_Z(i, m, yz, k, yz1)) } -// VPHSUBSW: Packed Horizontal Subtract Signed Word Integers with Signed Saturation. +// VSHUFI32X4_BCST_Z: Shuffle 128-Bit Packed Doubleword Integer Values (Broadcast, Zeroing Masking). // // Forms: // -// VPHSUBSW xmm xmm xmm -// VPHSUBSW m128 xmm xmm -// VPHSUBSW ymm ymm ymm -// VPHSUBSW m256 ymm ymm -// Construct and append a VPHSUBSW instruction to the active function. +// VSHUFI32X4.BCST.Z imm8 m32 ymm k ymm +// VSHUFI32X4.BCST.Z imm8 m32 zmm k zmm +// Construct and append a VSHUFI32X4.BCST.Z instruction to the active function. // Operates on the global context. -func VPHSUBSW(mxy, xy, xy1 operand.Op) { ctx.VPHSUBSW(mxy, xy, xy1) } +func VSHUFI32X4_BCST_Z(i, m, yz, k, yz1 operand.Op) { ctx.VSHUFI32X4_BCST_Z(i, m, yz, k, yz1) } -// VPHSUBW: Packed Horizontal Subtract Word Integers. +// VSHUFI32X4_Z: Shuffle 128-Bit Packed Doubleword Integer Values (Zeroing Masking). // // Forms: // -// VPHSUBW xmm xmm xmm -// VPHSUBW m128 xmm xmm -// VPHSUBW ymm ymm ymm -// VPHSUBW m256 ymm ymm -// Construct and append a VPHSUBW instruction to the active function. -func (c *Context) VPHSUBW(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPHSUBW(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSHUFI32X4.Z imm8 m256 ymm k ymm +// VSHUFI32X4.Z imm8 ymm ymm k ymm +// VSHUFI32X4.Z imm8 m512 zmm k zmm +// VSHUFI32X4.Z imm8 zmm zmm k zmm +// Construct and append a VSHUFI32X4.Z instruction to the active function. +func (c *Context) VSHUFI32X4_Z(i, myz, yz, k, yz1 operand.Op) { + c.addinstruction(x86.VSHUFI32X4_Z(i, myz, yz, k, yz1)) } -// VPHSUBW: Packed Horizontal Subtract Word Integers. +// VSHUFI32X4_Z: Shuffle 128-Bit Packed Doubleword Integer Values (Zeroing Masking). // // Forms: // -// VPHSUBW xmm xmm xmm -// VPHSUBW m128 xmm xmm -// VPHSUBW ymm ymm ymm -// VPHSUBW m256 ymm ymm -// Construct and append a VPHSUBW instruction to the active function. +// VSHUFI32X4.Z imm8 m256 ymm k ymm +// VSHUFI32X4.Z imm8 ymm ymm k ymm +// VSHUFI32X4.Z imm8 m512 zmm k zmm +// VSHUFI32X4.Z imm8 zmm zmm k zmm +// Construct and append a VSHUFI32X4.Z instruction to the active function. // Operates on the global context. -func VPHSUBW(mxy, xy, xy1 operand.Op) { ctx.VPHSUBW(mxy, xy, xy1) } +func VSHUFI32X4_Z(i, myz, yz, k, yz1 operand.Op) { ctx.VSHUFI32X4_Z(i, myz, yz, k, yz1) } -// VPINSRB: Insert Byte. +// VSHUFI64X2: Shuffle 128-Bit Packed Quadword Integer Values. // // Forms: // -// VPINSRB imm8 r32 xmm xmm -// VPINSRB imm8 m8 xmm xmm -// Construct and append a VPINSRB instruction to the active function. -func (c *Context) VPINSRB(i, mr, x, x1 operand.Op) { - if inst, err := x86.VPINSRB(i, mr, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSHUFI64X2 imm8 m256 ymm k ymm +// VSHUFI64X2 imm8 m256 ymm ymm +// VSHUFI64X2 imm8 ymm ymm k ymm +// VSHUFI64X2 imm8 ymm ymm ymm +// VSHUFI64X2 imm8 m512 zmm k zmm +// VSHUFI64X2 imm8 m512 zmm zmm +// VSHUFI64X2 imm8 zmm zmm k zmm +// VSHUFI64X2 imm8 zmm zmm zmm +// Construct and append a VSHUFI64X2 instruction to the active function. +func (c *Context) VSHUFI64X2(ops ...operand.Op) { + c.addinstruction(x86.VSHUFI64X2(ops...)) } -// VPINSRB: Insert Byte. +// VSHUFI64X2: Shuffle 128-Bit Packed Quadword Integer Values. // // Forms: // -// VPINSRB imm8 r32 xmm xmm -// VPINSRB imm8 m8 xmm xmm -// Construct and append a VPINSRB instruction to the active function. +// VSHUFI64X2 imm8 m256 ymm k ymm +// VSHUFI64X2 imm8 m256 ymm ymm +// VSHUFI64X2 imm8 ymm ymm k ymm +// VSHUFI64X2 imm8 ymm ymm ymm +// VSHUFI64X2 imm8 m512 zmm k zmm +// VSHUFI64X2 imm8 m512 zmm zmm +// VSHUFI64X2 imm8 zmm zmm k zmm +// VSHUFI64X2 imm8 zmm zmm zmm +// Construct and append a VSHUFI64X2 instruction to the active function. // Operates on the global context. -func VPINSRB(i, mr, x, x1 operand.Op) { ctx.VPINSRB(i, mr, x, x1) } +func VSHUFI64X2(ops ...operand.Op) { ctx.VSHUFI64X2(ops...) } -// VPINSRD: Insert Doubleword. +// VSHUFI64X2_BCST: Shuffle 128-Bit Packed Quadword Integer Values (Broadcast). // // Forms: // -// VPINSRD imm8 r32 xmm xmm -// VPINSRD imm8 m32 xmm xmm -// Construct and append a VPINSRD instruction to the active function. -func (c *Context) VPINSRD(i, mr, x, x1 operand.Op) { - if inst, err := x86.VPINSRD(i, mr, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSHUFI64X2.BCST imm8 m64 ymm k ymm +// VSHUFI64X2.BCST imm8 m64 ymm ymm +// VSHUFI64X2.BCST imm8 m64 zmm k zmm +// VSHUFI64X2.BCST imm8 m64 zmm zmm +// Construct and append a VSHUFI64X2.BCST instruction to the active function. +func (c *Context) VSHUFI64X2_BCST(ops ...operand.Op) { + c.addinstruction(x86.VSHUFI64X2_BCST(ops...)) } -// VPINSRD: Insert Doubleword. +// VSHUFI64X2_BCST: Shuffle 128-Bit Packed Quadword Integer Values (Broadcast). // // Forms: // -// VPINSRD imm8 r32 xmm xmm -// VPINSRD imm8 m32 xmm xmm -// Construct and append a VPINSRD instruction to the active function. +// VSHUFI64X2.BCST imm8 m64 ymm k ymm +// VSHUFI64X2.BCST imm8 m64 ymm ymm +// VSHUFI64X2.BCST imm8 m64 zmm k zmm +// VSHUFI64X2.BCST imm8 m64 zmm zmm +// Construct and append a VSHUFI64X2.BCST instruction to the active function. // Operates on the global context. -func VPINSRD(i, mr, x, x1 operand.Op) { ctx.VPINSRD(i, mr, x, x1) } +func VSHUFI64X2_BCST(ops ...operand.Op) { ctx.VSHUFI64X2_BCST(ops...) } -// VPINSRQ: Insert Quadword. +// VSHUFI64X2_BCST_Z: Shuffle 128-Bit Packed Quadword Integer Values (Broadcast, Zeroing Masking). // // Forms: // -// VPINSRQ imm8 r64 xmm xmm -// VPINSRQ imm8 m64 xmm xmm -// Construct and append a VPINSRQ instruction to the active function. -func (c *Context) VPINSRQ(i, mr, x, x1 operand.Op) { - if inst, err := x86.VPINSRQ(i, mr, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSHUFI64X2.BCST.Z imm8 m64 ymm k ymm +// VSHUFI64X2.BCST.Z imm8 m64 zmm k zmm +// Construct and append a VSHUFI64X2.BCST.Z instruction to the active function. +func (c *Context) VSHUFI64X2_BCST_Z(i, m, yz, k, yz1 operand.Op) { + c.addinstruction(x86.VSHUFI64X2_BCST_Z(i, m, yz, k, yz1)) } -// VPINSRQ: Insert Quadword. +// VSHUFI64X2_BCST_Z: Shuffle 128-Bit Packed Quadword Integer Values (Broadcast, Zeroing Masking). // // Forms: // -// VPINSRQ imm8 r64 xmm xmm -// VPINSRQ imm8 m64 xmm xmm -// Construct and append a VPINSRQ instruction to the active function. +// VSHUFI64X2.BCST.Z imm8 m64 ymm k ymm +// VSHUFI64X2.BCST.Z imm8 m64 zmm k zmm +// Construct and append a VSHUFI64X2.BCST.Z instruction to the active function. // Operates on the global context. -func VPINSRQ(i, mr, x, x1 operand.Op) { ctx.VPINSRQ(i, mr, x, x1) } +func VSHUFI64X2_BCST_Z(i, m, yz, k, yz1 operand.Op) { ctx.VSHUFI64X2_BCST_Z(i, m, yz, k, yz1) } -// VPINSRW: Insert Word. +// VSHUFI64X2_Z: Shuffle 128-Bit Packed Quadword Integer Values (Zeroing Masking). // // Forms: // -// VPINSRW imm8 r32 xmm xmm -// VPINSRW imm8 m16 xmm xmm -// Construct and append a VPINSRW instruction to the active function. -func (c *Context) VPINSRW(i, mr, x, x1 operand.Op) { - if inst, err := x86.VPINSRW(i, mr, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSHUFI64X2.Z imm8 m256 ymm k ymm +// VSHUFI64X2.Z imm8 ymm ymm k ymm +// VSHUFI64X2.Z imm8 m512 zmm k zmm +// VSHUFI64X2.Z imm8 zmm zmm k zmm +// Construct and append a VSHUFI64X2.Z instruction to the active function. +func (c *Context) VSHUFI64X2_Z(i, myz, yz, k, yz1 operand.Op) { + c.addinstruction(x86.VSHUFI64X2_Z(i, myz, yz, k, yz1)) } -// VPINSRW: Insert Word. +// VSHUFI64X2_Z: Shuffle 128-Bit Packed Quadword Integer Values (Zeroing Masking). // // Forms: // -// VPINSRW imm8 r32 xmm xmm -// VPINSRW imm8 m16 xmm xmm -// Construct and append a VPINSRW instruction to the active function. +// VSHUFI64X2.Z imm8 m256 ymm k ymm +// VSHUFI64X2.Z imm8 ymm ymm k ymm +// VSHUFI64X2.Z imm8 m512 zmm k zmm +// VSHUFI64X2.Z imm8 zmm zmm k zmm +// Construct and append a VSHUFI64X2.Z instruction to the active function. // Operates on the global context. -func VPINSRW(i, mr, x, x1 operand.Op) { ctx.VPINSRW(i, mr, x, x1) } +func VSHUFI64X2_Z(i, myz, yz, k, yz1 operand.Op) { ctx.VSHUFI64X2_Z(i, myz, yz, k, yz1) } -// VPMADDUBSW: Multiply and Add Packed Signed and Unsigned Byte Integers. +// VSHUFPD: Shuffle Packed Double-Precision Floating-Point Values. // // Forms: // -// VPMADDUBSW xmm xmm xmm -// VPMADDUBSW m128 xmm xmm -// VPMADDUBSW ymm ymm ymm -// VPMADDUBSW m256 ymm ymm -// Construct and append a VPMADDUBSW instruction to the active function. -func (c *Context) VPMADDUBSW(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPMADDUBSW(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSHUFPD imm8 m128 xmm xmm +// VSHUFPD imm8 m256 ymm ymm +// VSHUFPD imm8 xmm xmm xmm +// VSHUFPD imm8 ymm ymm ymm +// VSHUFPD imm8 m128 xmm k xmm +// VSHUFPD imm8 m256 ymm k ymm +// VSHUFPD imm8 xmm xmm k xmm +// VSHUFPD imm8 ymm ymm k ymm +// VSHUFPD imm8 m512 zmm k zmm +// VSHUFPD imm8 m512 zmm zmm +// VSHUFPD imm8 zmm zmm k zmm +// VSHUFPD imm8 zmm zmm zmm +// Construct and append a VSHUFPD instruction to the active function. +func (c *Context) VSHUFPD(ops ...operand.Op) { + c.addinstruction(x86.VSHUFPD(ops...)) } -// VPMADDUBSW: Multiply and Add Packed Signed and Unsigned Byte Integers. +// VSHUFPD: Shuffle Packed Double-Precision Floating-Point Values. // // Forms: // -// VPMADDUBSW xmm xmm xmm -// VPMADDUBSW m128 xmm xmm -// VPMADDUBSW ymm ymm ymm -// VPMADDUBSW m256 ymm ymm -// Construct and append a VPMADDUBSW instruction to the active function. +// VSHUFPD imm8 m128 xmm xmm +// VSHUFPD imm8 m256 ymm ymm +// VSHUFPD imm8 xmm xmm xmm +// VSHUFPD imm8 ymm ymm ymm +// VSHUFPD imm8 m128 xmm k xmm +// VSHUFPD imm8 m256 ymm k ymm +// VSHUFPD imm8 xmm xmm k xmm +// VSHUFPD imm8 ymm ymm k ymm +// VSHUFPD imm8 m512 zmm k zmm +// VSHUFPD imm8 m512 zmm zmm +// VSHUFPD imm8 zmm zmm k zmm +// VSHUFPD imm8 zmm zmm zmm +// Construct and append a VSHUFPD instruction to the active function. // Operates on the global context. -func VPMADDUBSW(mxy, xy, xy1 operand.Op) { ctx.VPMADDUBSW(mxy, xy, xy1) } +func VSHUFPD(ops ...operand.Op) { ctx.VSHUFPD(ops...) } -// VPMADDWD: Multiply and Add Packed Signed Word Integers. +// VSHUFPD_BCST: Shuffle Packed Double-Precision Floating-Point Values (Broadcast). // // Forms: // -// VPMADDWD xmm xmm xmm -// VPMADDWD m128 xmm xmm -// VPMADDWD ymm ymm ymm -// VPMADDWD m256 ymm ymm -// Construct and append a VPMADDWD instruction to the active function. -func (c *Context) VPMADDWD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPMADDWD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSHUFPD.BCST imm8 m64 xmm k xmm +// VSHUFPD.BCST imm8 m64 xmm xmm +// VSHUFPD.BCST imm8 m64 ymm k ymm +// VSHUFPD.BCST imm8 m64 ymm ymm +// VSHUFPD.BCST imm8 m64 zmm k zmm +// VSHUFPD.BCST imm8 m64 zmm zmm +// Construct and append a VSHUFPD.BCST instruction to the active function. +func (c *Context) VSHUFPD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VSHUFPD_BCST(ops...)) } -// VPMADDWD: Multiply and Add Packed Signed Word Integers. +// VSHUFPD_BCST: Shuffle Packed Double-Precision Floating-Point Values (Broadcast). // // Forms: // -// VPMADDWD xmm xmm xmm -// VPMADDWD m128 xmm xmm -// VPMADDWD ymm ymm ymm -// VPMADDWD m256 ymm ymm -// Construct and append a VPMADDWD instruction to the active function. +// VSHUFPD.BCST imm8 m64 xmm k xmm +// VSHUFPD.BCST imm8 m64 xmm xmm +// VSHUFPD.BCST imm8 m64 ymm k ymm +// VSHUFPD.BCST imm8 m64 ymm ymm +// VSHUFPD.BCST imm8 m64 zmm k zmm +// VSHUFPD.BCST imm8 m64 zmm zmm +// Construct and append a VSHUFPD.BCST instruction to the active function. // Operates on the global context. -func VPMADDWD(mxy, xy, xy1 operand.Op) { ctx.VPMADDWD(mxy, xy, xy1) } +func VSHUFPD_BCST(ops ...operand.Op) { ctx.VSHUFPD_BCST(ops...) } -// VPMASKMOVD: Conditional Move Packed Doubleword Integers. +// VSHUFPD_BCST_Z: Shuffle Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VPMASKMOVD m128 xmm xmm -// VPMASKMOVD m256 ymm ymm -// VPMASKMOVD xmm xmm m128 -// VPMASKMOVD ymm ymm m256 -// Construct and append a VPMASKMOVD instruction to the active function. -func (c *Context) VPMASKMOVD(mxy, xy, mxy1 operand.Op) { - if inst, err := x86.VPMASKMOVD(mxy, xy, mxy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSHUFPD.BCST.Z imm8 m64 xmm k xmm +// VSHUFPD.BCST.Z imm8 m64 ymm k ymm +// VSHUFPD.BCST.Z imm8 m64 zmm k zmm +// Construct and append a VSHUFPD.BCST.Z instruction to the active function. +func (c *Context) VSHUFPD_BCST_Z(i, m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VSHUFPD_BCST_Z(i, m, xyz, k, xyz1)) } -// VPMASKMOVD: Conditional Move Packed Doubleword Integers. +// VSHUFPD_BCST_Z: Shuffle Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VPMASKMOVD m128 xmm xmm -// VPMASKMOVD m256 ymm ymm -// VPMASKMOVD xmm xmm m128 -// VPMASKMOVD ymm ymm m256 -// Construct and append a VPMASKMOVD instruction to the active function. +// VSHUFPD.BCST.Z imm8 m64 xmm k xmm +// VSHUFPD.BCST.Z imm8 m64 ymm k ymm +// VSHUFPD.BCST.Z imm8 m64 zmm k zmm +// Construct and append a VSHUFPD.BCST.Z instruction to the active function. // Operates on the global context. -func VPMASKMOVD(mxy, xy, mxy1 operand.Op) { ctx.VPMASKMOVD(mxy, xy, mxy1) } +func VSHUFPD_BCST_Z(i, m, xyz, k, xyz1 operand.Op) { ctx.VSHUFPD_BCST_Z(i, m, xyz, k, xyz1) } -// VPMASKMOVQ: Conditional Move Packed Quadword Integers. +// VSHUFPD_Z: Shuffle Packed Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VPMASKMOVQ m128 xmm xmm -// VPMASKMOVQ m256 ymm ymm -// VPMASKMOVQ xmm xmm m128 -// VPMASKMOVQ ymm ymm m256 -// Construct and append a VPMASKMOVQ instruction to the active function. -func (c *Context) VPMASKMOVQ(mxy, xy, mxy1 operand.Op) { - if inst, err := x86.VPMASKMOVQ(mxy, xy, mxy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSHUFPD.Z imm8 m128 xmm k xmm +// VSHUFPD.Z imm8 m256 ymm k ymm +// VSHUFPD.Z imm8 xmm xmm k xmm +// VSHUFPD.Z imm8 ymm ymm k ymm +// VSHUFPD.Z imm8 m512 zmm k zmm +// VSHUFPD.Z imm8 zmm zmm k zmm +// Construct and append a VSHUFPD.Z instruction to the active function. +func (c *Context) VSHUFPD_Z(i, mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VSHUFPD_Z(i, mxyz, xyz, k, xyz1)) } -// VPMASKMOVQ: Conditional Move Packed Quadword Integers. +// VSHUFPD_Z: Shuffle Packed Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VPMASKMOVQ m128 xmm xmm -// VPMASKMOVQ m256 ymm ymm -// VPMASKMOVQ xmm xmm m128 -// VPMASKMOVQ ymm ymm m256 -// Construct and append a VPMASKMOVQ instruction to the active function. +// VSHUFPD.Z imm8 m128 xmm k xmm +// VSHUFPD.Z imm8 m256 ymm k ymm +// VSHUFPD.Z imm8 xmm xmm k xmm +// VSHUFPD.Z imm8 ymm ymm k ymm +// VSHUFPD.Z imm8 m512 zmm k zmm +// VSHUFPD.Z imm8 zmm zmm k zmm +// Construct and append a VSHUFPD.Z instruction to the active function. // Operates on the global context. -func VPMASKMOVQ(mxy, xy, mxy1 operand.Op) { ctx.VPMASKMOVQ(mxy, xy, mxy1) } +func VSHUFPD_Z(i, mxyz, xyz, k, xyz1 operand.Op) { ctx.VSHUFPD_Z(i, mxyz, xyz, k, xyz1) } -// VPMAXSB: Maximum of Packed Signed Byte Integers. +// VSHUFPS: Shuffle Packed Single-Precision Floating-Point Values. // // Forms: // -// VPMAXSB xmm xmm xmm -// VPMAXSB m128 xmm xmm -// VPMAXSB ymm ymm ymm -// VPMAXSB m256 ymm ymm -// Construct and append a VPMAXSB instruction to the active function. -func (c *Context) VPMAXSB(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPMAXSB(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSHUFPS imm8 m128 xmm xmm +// VSHUFPS imm8 m256 ymm ymm +// VSHUFPS imm8 xmm xmm xmm +// VSHUFPS imm8 ymm ymm ymm +// VSHUFPS imm8 m128 xmm k xmm +// VSHUFPS imm8 m256 ymm k ymm +// VSHUFPS imm8 xmm xmm k xmm +// VSHUFPS imm8 ymm ymm k ymm +// VSHUFPS imm8 m512 zmm k zmm +// VSHUFPS imm8 m512 zmm zmm +// VSHUFPS imm8 zmm zmm k zmm +// VSHUFPS imm8 zmm zmm zmm +// Construct and append a VSHUFPS instruction to the active function. +func (c *Context) VSHUFPS(ops ...operand.Op) { + c.addinstruction(x86.VSHUFPS(ops...)) } -// VPMAXSB: Maximum of Packed Signed Byte Integers. +// VSHUFPS: Shuffle Packed Single-Precision Floating-Point Values. // // Forms: // -// VPMAXSB xmm xmm xmm -// VPMAXSB m128 xmm xmm -// VPMAXSB ymm ymm ymm -// VPMAXSB m256 ymm ymm -// Construct and append a VPMAXSB instruction to the active function. +// VSHUFPS imm8 m128 xmm xmm +// VSHUFPS imm8 m256 ymm ymm +// VSHUFPS imm8 xmm xmm xmm +// VSHUFPS imm8 ymm ymm ymm +// VSHUFPS imm8 m128 xmm k xmm +// VSHUFPS imm8 m256 ymm k ymm +// VSHUFPS imm8 xmm xmm k xmm +// VSHUFPS imm8 ymm ymm k ymm +// VSHUFPS imm8 m512 zmm k zmm +// VSHUFPS imm8 m512 zmm zmm +// VSHUFPS imm8 zmm zmm k zmm +// VSHUFPS imm8 zmm zmm zmm +// Construct and append a VSHUFPS instruction to the active function. // Operates on the global context. -func VPMAXSB(mxy, xy, xy1 operand.Op) { ctx.VPMAXSB(mxy, xy, xy1) } +func VSHUFPS(ops ...operand.Op) { ctx.VSHUFPS(ops...) } -// VPMAXSD: Maximum of Packed Signed Doubleword Integers. +// VSHUFPS_BCST: Shuffle Packed Single-Precision Floating-Point Values (Broadcast). // // Forms: // -// VPMAXSD xmm xmm xmm -// VPMAXSD m128 xmm xmm -// VPMAXSD ymm ymm ymm -// VPMAXSD m256 ymm ymm -// Construct and append a VPMAXSD instruction to the active function. -func (c *Context) VPMAXSD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPMAXSD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSHUFPS.BCST imm8 m32 xmm k xmm +// VSHUFPS.BCST imm8 m32 xmm xmm +// VSHUFPS.BCST imm8 m32 ymm k ymm +// VSHUFPS.BCST imm8 m32 ymm ymm +// VSHUFPS.BCST imm8 m32 zmm k zmm +// VSHUFPS.BCST imm8 m32 zmm zmm +// Construct and append a VSHUFPS.BCST instruction to the active function. +func (c *Context) VSHUFPS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VSHUFPS_BCST(ops...)) } -// VPMAXSD: Maximum of Packed Signed Doubleword Integers. +// VSHUFPS_BCST: Shuffle Packed Single-Precision Floating-Point Values (Broadcast). // // Forms: // -// VPMAXSD xmm xmm xmm -// VPMAXSD m128 xmm xmm -// VPMAXSD ymm ymm ymm -// VPMAXSD m256 ymm ymm -// Construct and append a VPMAXSD instruction to the active function. +// VSHUFPS.BCST imm8 m32 xmm k xmm +// VSHUFPS.BCST imm8 m32 xmm xmm +// VSHUFPS.BCST imm8 m32 ymm k ymm +// VSHUFPS.BCST imm8 m32 ymm ymm +// VSHUFPS.BCST imm8 m32 zmm k zmm +// VSHUFPS.BCST imm8 m32 zmm zmm +// Construct and append a VSHUFPS.BCST instruction to the active function. // Operates on the global context. -func VPMAXSD(mxy, xy, xy1 operand.Op) { ctx.VPMAXSD(mxy, xy, xy1) } +func VSHUFPS_BCST(ops ...operand.Op) { ctx.VSHUFPS_BCST(ops...) } -// VPMAXSW: Maximum of Packed Signed Word Integers. +// VSHUFPS_BCST_Z: Shuffle Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VPMAXSW xmm xmm xmm -// VPMAXSW m128 xmm xmm -// VPMAXSW ymm ymm ymm -// VPMAXSW m256 ymm ymm -// Construct and append a VPMAXSW instruction to the active function. -func (c *Context) VPMAXSW(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPMAXSW(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSHUFPS.BCST.Z imm8 m32 xmm k xmm +// VSHUFPS.BCST.Z imm8 m32 ymm k ymm +// VSHUFPS.BCST.Z imm8 m32 zmm k zmm +// Construct and append a VSHUFPS.BCST.Z instruction to the active function. +func (c *Context) VSHUFPS_BCST_Z(i, m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VSHUFPS_BCST_Z(i, m, xyz, k, xyz1)) } -// VPMAXSW: Maximum of Packed Signed Word Integers. +// VSHUFPS_BCST_Z: Shuffle Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VPMAXSW xmm xmm xmm -// VPMAXSW m128 xmm xmm -// VPMAXSW ymm ymm ymm -// VPMAXSW m256 ymm ymm -// Construct and append a VPMAXSW instruction to the active function. +// VSHUFPS.BCST.Z imm8 m32 xmm k xmm +// VSHUFPS.BCST.Z imm8 m32 ymm k ymm +// VSHUFPS.BCST.Z imm8 m32 zmm k zmm +// Construct and append a VSHUFPS.BCST.Z instruction to the active function. // Operates on the global context. -func VPMAXSW(mxy, xy, xy1 operand.Op) { ctx.VPMAXSW(mxy, xy, xy1) } +func VSHUFPS_BCST_Z(i, m, xyz, k, xyz1 operand.Op) { ctx.VSHUFPS_BCST_Z(i, m, xyz, k, xyz1) } -// VPMAXUB: Maximum of Packed Unsigned Byte Integers. +// VSHUFPS_Z: Shuffle Packed Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VPMAXUB xmm xmm xmm -// VPMAXUB m128 xmm xmm -// VPMAXUB ymm ymm ymm -// VPMAXUB m256 ymm ymm -// Construct and append a VPMAXUB instruction to the active function. -func (c *Context) VPMAXUB(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPMAXUB(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSHUFPS.Z imm8 m128 xmm k xmm +// VSHUFPS.Z imm8 m256 ymm k ymm +// VSHUFPS.Z imm8 xmm xmm k xmm +// VSHUFPS.Z imm8 ymm ymm k ymm +// VSHUFPS.Z imm8 m512 zmm k zmm +// VSHUFPS.Z imm8 zmm zmm k zmm +// Construct and append a VSHUFPS.Z instruction to the active function. +func (c *Context) VSHUFPS_Z(i, mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VSHUFPS_Z(i, mxyz, xyz, k, xyz1)) } -// VPMAXUB: Maximum of Packed Unsigned Byte Integers. +// VSHUFPS_Z: Shuffle Packed Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VPMAXUB xmm xmm xmm -// VPMAXUB m128 xmm xmm -// VPMAXUB ymm ymm ymm -// VPMAXUB m256 ymm ymm -// Construct and append a VPMAXUB instruction to the active function. +// VSHUFPS.Z imm8 m128 xmm k xmm +// VSHUFPS.Z imm8 m256 ymm k ymm +// VSHUFPS.Z imm8 xmm xmm k xmm +// VSHUFPS.Z imm8 ymm ymm k ymm +// VSHUFPS.Z imm8 m512 zmm k zmm +// VSHUFPS.Z imm8 zmm zmm k zmm +// Construct and append a VSHUFPS.Z instruction to the active function. // Operates on the global context. -func VPMAXUB(mxy, xy, xy1 operand.Op) { ctx.VPMAXUB(mxy, xy, xy1) } +func VSHUFPS_Z(i, mxyz, xyz, k, xyz1 operand.Op) { ctx.VSHUFPS_Z(i, mxyz, xyz, k, xyz1) } -// VPMAXUD: Maximum of Packed Unsigned Doubleword Integers. +// VSQRTPD: Compute Square Roots of Packed Double-Precision Floating-Point Values. // // Forms: // -// VPMAXUD xmm xmm xmm -// VPMAXUD m128 xmm xmm -// VPMAXUD ymm ymm ymm -// VPMAXUD m256 ymm ymm -// Construct and append a VPMAXUD instruction to the active function. -func (c *Context) VPMAXUD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPMAXUD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTPD m128 xmm +// VSQRTPD m256 ymm +// VSQRTPD xmm xmm +// VSQRTPD ymm ymm +// VSQRTPD m128 k xmm +// VSQRTPD m256 k ymm +// VSQRTPD xmm k xmm +// VSQRTPD ymm k ymm +// VSQRTPD m512 k zmm +// VSQRTPD m512 zmm +// VSQRTPD zmm k zmm +// VSQRTPD zmm zmm +// Construct and append a VSQRTPD instruction to the active function. +func (c *Context) VSQRTPD(ops ...operand.Op) { + c.addinstruction(x86.VSQRTPD(ops...)) } -// VPMAXUD: Maximum of Packed Unsigned Doubleword Integers. +// VSQRTPD: Compute Square Roots of Packed Double-Precision Floating-Point Values. // // Forms: // -// VPMAXUD xmm xmm xmm -// VPMAXUD m128 xmm xmm -// VPMAXUD ymm ymm ymm -// VPMAXUD m256 ymm ymm -// Construct and append a VPMAXUD instruction to the active function. +// VSQRTPD m128 xmm +// VSQRTPD m256 ymm +// VSQRTPD xmm xmm +// VSQRTPD ymm ymm +// VSQRTPD m128 k xmm +// VSQRTPD m256 k ymm +// VSQRTPD xmm k xmm +// VSQRTPD ymm k ymm +// VSQRTPD m512 k zmm +// VSQRTPD m512 zmm +// VSQRTPD zmm k zmm +// VSQRTPD zmm zmm +// Construct and append a VSQRTPD instruction to the active function. // Operates on the global context. -func VPMAXUD(mxy, xy, xy1 operand.Op) { ctx.VPMAXUD(mxy, xy, xy1) } +func VSQRTPD(ops ...operand.Op) { ctx.VSQRTPD(ops...) } -// VPMAXUW: Maximum of Packed Unsigned Word Integers. +// VSQRTPD_BCST: Compute Square Roots of Packed Double-Precision Floating-Point Values (Broadcast). // // Forms: // -// VPMAXUW xmm xmm xmm -// VPMAXUW m128 xmm xmm -// VPMAXUW ymm ymm ymm -// VPMAXUW m256 ymm ymm -// Construct and append a VPMAXUW instruction to the active function. -func (c *Context) VPMAXUW(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPMAXUW(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTPD.BCST m32 k xmm +// VSQRTPD.BCST m32 k ymm +// VSQRTPD.BCST m32 xmm +// VSQRTPD.BCST m32 ymm +// VSQRTPD.BCST m64 k zmm +// VSQRTPD.BCST m64 zmm +// Construct and append a VSQRTPD.BCST instruction to the active function. +func (c *Context) VSQRTPD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VSQRTPD_BCST(ops...)) } -// VPMAXUW: Maximum of Packed Unsigned Word Integers. +// VSQRTPD_BCST: Compute Square Roots of Packed Double-Precision Floating-Point Values (Broadcast). // // Forms: // -// VPMAXUW xmm xmm xmm -// VPMAXUW m128 xmm xmm -// VPMAXUW ymm ymm ymm -// VPMAXUW m256 ymm ymm -// Construct and append a VPMAXUW instruction to the active function. +// VSQRTPD.BCST m32 k xmm +// VSQRTPD.BCST m32 k ymm +// VSQRTPD.BCST m32 xmm +// VSQRTPD.BCST m32 ymm +// VSQRTPD.BCST m64 k zmm +// VSQRTPD.BCST m64 zmm +// Construct and append a VSQRTPD.BCST instruction to the active function. // Operates on the global context. -func VPMAXUW(mxy, xy, xy1 operand.Op) { ctx.VPMAXUW(mxy, xy, xy1) } +func VSQRTPD_BCST(ops ...operand.Op) { ctx.VSQRTPD_BCST(ops...) } -// VPMINSB: Minimum of Packed Signed Byte Integers. +// VSQRTPD_BCST_Z: Compute Square Roots of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VPMINSB xmm xmm xmm -// VPMINSB m128 xmm xmm -// VPMINSB ymm ymm ymm -// VPMINSB m256 ymm ymm -// Construct and append a VPMINSB instruction to the active function. -func (c *Context) VPMINSB(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPMINSB(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTPD.BCST.Z m32 k xmm +// VSQRTPD.BCST.Z m32 k ymm +// VSQRTPD.BCST.Z m64 k zmm +// Construct and append a VSQRTPD.BCST.Z instruction to the active function. +func (c *Context) VSQRTPD_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VSQRTPD_BCST_Z(m, k, xyz)) } -// VPMINSB: Minimum of Packed Signed Byte Integers. +// VSQRTPD_BCST_Z: Compute Square Roots of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VPMINSB xmm xmm xmm -// VPMINSB m128 xmm xmm -// VPMINSB ymm ymm ymm -// VPMINSB m256 ymm ymm -// Construct and append a VPMINSB instruction to the active function. +// VSQRTPD.BCST.Z m32 k xmm +// VSQRTPD.BCST.Z m32 k ymm +// VSQRTPD.BCST.Z m64 k zmm +// Construct and append a VSQRTPD.BCST.Z instruction to the active function. // Operates on the global context. -func VPMINSB(mxy, xy, xy1 operand.Op) { ctx.VPMINSB(mxy, xy, xy1) } +func VSQRTPD_BCST_Z(m, k, xyz operand.Op) { ctx.VSQRTPD_BCST_Z(m, k, xyz) } -// VPMINSD: Minimum of Packed Signed Doubleword Integers. +// VSQRTPD_RD_SAE: Compute Square Roots of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). // // Forms: // -// VPMINSD xmm xmm xmm -// VPMINSD m128 xmm xmm -// VPMINSD ymm ymm ymm -// VPMINSD m256 ymm ymm -// Construct and append a VPMINSD instruction to the active function. -func (c *Context) VPMINSD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPMINSD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTPD.RD_SAE zmm k zmm +// VSQRTPD.RD_SAE zmm zmm +// Construct and append a VSQRTPD.RD_SAE instruction to the active function. +func (c *Context) VSQRTPD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSQRTPD_RD_SAE(ops...)) } -// VPMINSD: Minimum of Packed Signed Doubleword Integers. +// VSQRTPD_RD_SAE: Compute Square Roots of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). // // Forms: // -// VPMINSD xmm xmm xmm -// VPMINSD m128 xmm xmm -// VPMINSD ymm ymm ymm -// VPMINSD m256 ymm ymm -// Construct and append a VPMINSD instruction to the active function. +// VSQRTPD.RD_SAE zmm k zmm +// VSQRTPD.RD_SAE zmm zmm +// Construct and append a VSQRTPD.RD_SAE instruction to the active function. // Operates on the global context. -func VPMINSD(mxy, xy, xy1 operand.Op) { ctx.VPMINSD(mxy, xy, xy1) } +func VSQRTPD_RD_SAE(ops ...operand.Op) { ctx.VSQRTPD_RD_SAE(ops...) } -// VPMINSW: Minimum of Packed Signed Word Integers. +// VSQRTPD_RD_SAE_Z: Compute Square Roots of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VPMINSW xmm xmm xmm -// VPMINSW m128 xmm xmm -// VPMINSW ymm ymm ymm -// VPMINSW m256 ymm ymm -// Construct and append a VPMINSW instruction to the active function. -func (c *Context) VPMINSW(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPMINSW(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTPD.RD_SAE.Z zmm k zmm +// Construct and append a VSQRTPD.RD_SAE.Z instruction to the active function. +func (c *Context) VSQRTPD_RD_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VSQRTPD_RD_SAE_Z(z, k, z1)) } -// VPMINSW: Minimum of Packed Signed Word Integers. +// VSQRTPD_RD_SAE_Z: Compute Square Roots of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VPMINSW xmm xmm xmm -// VPMINSW m128 xmm xmm -// VPMINSW ymm ymm ymm -// VPMINSW m256 ymm ymm -// Construct and append a VPMINSW instruction to the active function. +// VSQRTPD.RD_SAE.Z zmm k zmm +// Construct and append a VSQRTPD.RD_SAE.Z instruction to the active function. // Operates on the global context. -func VPMINSW(mxy, xy, xy1 operand.Op) { ctx.VPMINSW(mxy, xy, xy1) } +func VSQRTPD_RD_SAE_Z(z, k, z1 operand.Op) { ctx.VSQRTPD_RD_SAE_Z(z, k, z1) } -// VPMINUB: Minimum of Packed Unsigned Byte Integers. +// VSQRTPD_RN_SAE: Compute Square Roots of Packed Double-Precision Floating-Point Values (Round Towards Nearest). // // Forms: // -// VPMINUB xmm xmm xmm -// VPMINUB m128 xmm xmm -// VPMINUB ymm ymm ymm -// VPMINUB m256 ymm ymm -// Construct and append a VPMINUB instruction to the active function. -func (c *Context) VPMINUB(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPMINUB(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTPD.RN_SAE zmm k zmm +// VSQRTPD.RN_SAE zmm zmm +// Construct and append a VSQRTPD.RN_SAE instruction to the active function. +func (c *Context) VSQRTPD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSQRTPD_RN_SAE(ops...)) } -// VPMINUB: Minimum of Packed Unsigned Byte Integers. +// VSQRTPD_RN_SAE: Compute Square Roots of Packed Double-Precision Floating-Point Values (Round Towards Nearest). // // Forms: // -// VPMINUB xmm xmm xmm -// VPMINUB m128 xmm xmm -// VPMINUB ymm ymm ymm -// VPMINUB m256 ymm ymm -// Construct and append a VPMINUB instruction to the active function. +// VSQRTPD.RN_SAE zmm k zmm +// VSQRTPD.RN_SAE zmm zmm +// Construct and append a VSQRTPD.RN_SAE instruction to the active function. // Operates on the global context. -func VPMINUB(mxy, xy, xy1 operand.Op) { ctx.VPMINUB(mxy, xy, xy1) } +func VSQRTPD_RN_SAE(ops ...operand.Op) { ctx.VSQRTPD_RN_SAE(ops...) } -// VPMINUD: Minimum of Packed Unsigned Doubleword Integers. +// VSQRTPD_RN_SAE_Z: Compute Square Roots of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VPMINUD xmm xmm xmm -// VPMINUD m128 xmm xmm -// VPMINUD ymm ymm ymm -// VPMINUD m256 ymm ymm -// Construct and append a VPMINUD instruction to the active function. -func (c *Context) VPMINUD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPMINUD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTPD.RN_SAE.Z zmm k zmm +// Construct and append a VSQRTPD.RN_SAE.Z instruction to the active function. +func (c *Context) VSQRTPD_RN_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VSQRTPD_RN_SAE_Z(z, k, z1)) } -// VPMINUD: Minimum of Packed Unsigned Doubleword Integers. +// VSQRTPD_RN_SAE_Z: Compute Square Roots of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VPMINUD xmm xmm xmm -// VPMINUD m128 xmm xmm -// VPMINUD ymm ymm ymm -// VPMINUD m256 ymm ymm -// Construct and append a VPMINUD instruction to the active function. +// VSQRTPD.RN_SAE.Z zmm k zmm +// Construct and append a VSQRTPD.RN_SAE.Z instruction to the active function. // Operates on the global context. -func VPMINUD(mxy, xy, xy1 operand.Op) { ctx.VPMINUD(mxy, xy, xy1) } +func VSQRTPD_RN_SAE_Z(z, k, z1 operand.Op) { ctx.VSQRTPD_RN_SAE_Z(z, k, z1) } -// VPMINUW: Minimum of Packed Unsigned Word Integers. +// VSQRTPD_RU_SAE: Compute Square Roots of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). // // Forms: // -// VPMINUW xmm xmm xmm -// VPMINUW m128 xmm xmm -// VPMINUW ymm ymm ymm -// VPMINUW m256 ymm ymm -// Construct and append a VPMINUW instruction to the active function. -func (c *Context) VPMINUW(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPMINUW(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTPD.RU_SAE zmm k zmm +// VSQRTPD.RU_SAE zmm zmm +// Construct and append a VSQRTPD.RU_SAE instruction to the active function. +func (c *Context) VSQRTPD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSQRTPD_RU_SAE(ops...)) } -// VPMINUW: Minimum of Packed Unsigned Word Integers. +// VSQRTPD_RU_SAE: Compute Square Roots of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). // // Forms: // -// VPMINUW xmm xmm xmm -// VPMINUW m128 xmm xmm -// VPMINUW ymm ymm ymm -// VPMINUW m256 ymm ymm -// Construct and append a VPMINUW instruction to the active function. +// VSQRTPD.RU_SAE zmm k zmm +// VSQRTPD.RU_SAE zmm zmm +// Construct and append a VSQRTPD.RU_SAE instruction to the active function. // Operates on the global context. -func VPMINUW(mxy, xy, xy1 operand.Op) { ctx.VPMINUW(mxy, xy, xy1) } +func VSQRTPD_RU_SAE(ops ...operand.Op) { ctx.VSQRTPD_RU_SAE(ops...) } -// VPMOVMSKB: Move Byte Mask. +// VSQRTPD_RU_SAE_Z: Compute Square Roots of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VPMOVMSKB xmm r32 -// VPMOVMSKB ymm r32 -// Construct and append a VPMOVMSKB instruction to the active function. -func (c *Context) VPMOVMSKB(xy, r operand.Op) { - if inst, err := x86.VPMOVMSKB(xy, r); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTPD.RU_SAE.Z zmm k zmm +// Construct and append a VSQRTPD.RU_SAE.Z instruction to the active function. +func (c *Context) VSQRTPD_RU_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VSQRTPD_RU_SAE_Z(z, k, z1)) } -// VPMOVMSKB: Move Byte Mask. +// VSQRTPD_RU_SAE_Z: Compute Square Roots of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VPMOVMSKB xmm r32 -// VPMOVMSKB ymm r32 -// Construct and append a VPMOVMSKB instruction to the active function. +// VSQRTPD.RU_SAE.Z zmm k zmm +// Construct and append a VSQRTPD.RU_SAE.Z instruction to the active function. // Operates on the global context. -func VPMOVMSKB(xy, r operand.Op) { ctx.VPMOVMSKB(xy, r) } +func VSQRTPD_RU_SAE_Z(z, k, z1 operand.Op) { ctx.VSQRTPD_RU_SAE_Z(z, k, z1) } -// VPMOVSXBD: Move Packed Byte Integers to Doubleword Integers with Sign Extension. +// VSQRTPD_RZ_SAE: Compute Square Roots of Packed Double-Precision Floating-Point Values (Round Towards Zero). // // Forms: // -// VPMOVSXBD xmm xmm -// VPMOVSXBD m32 xmm -// VPMOVSXBD xmm ymm -// VPMOVSXBD m64 ymm -// Construct and append a VPMOVSXBD instruction to the active function. -func (c *Context) VPMOVSXBD(mx, xy operand.Op) { - if inst, err := x86.VPMOVSXBD(mx, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTPD.RZ_SAE zmm k zmm +// VSQRTPD.RZ_SAE zmm zmm +// Construct and append a VSQRTPD.RZ_SAE instruction to the active function. +func (c *Context) VSQRTPD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSQRTPD_RZ_SAE(ops...)) } -// VPMOVSXBD: Move Packed Byte Integers to Doubleword Integers with Sign Extension. +// VSQRTPD_RZ_SAE: Compute Square Roots of Packed Double-Precision Floating-Point Values (Round Towards Zero). // // Forms: // -// VPMOVSXBD xmm xmm -// VPMOVSXBD m32 xmm -// VPMOVSXBD xmm ymm -// VPMOVSXBD m64 ymm -// Construct and append a VPMOVSXBD instruction to the active function. +// VSQRTPD.RZ_SAE zmm k zmm +// VSQRTPD.RZ_SAE zmm zmm +// Construct and append a VSQRTPD.RZ_SAE instruction to the active function. // Operates on the global context. -func VPMOVSXBD(mx, xy operand.Op) { ctx.VPMOVSXBD(mx, xy) } +func VSQRTPD_RZ_SAE(ops ...operand.Op) { ctx.VSQRTPD_RZ_SAE(ops...) } -// VPMOVSXBQ: Move Packed Byte Integers to Quadword Integers with Sign Extension. +// VSQRTPD_RZ_SAE_Z: Compute Square Roots of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). // // Forms: // -// VPMOVSXBQ xmm xmm -// VPMOVSXBQ m16 xmm -// VPMOVSXBQ xmm ymm -// VPMOVSXBQ m32 ymm -// Construct and append a VPMOVSXBQ instruction to the active function. -func (c *Context) VPMOVSXBQ(mx, xy operand.Op) { - if inst, err := x86.VPMOVSXBQ(mx, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTPD.RZ_SAE.Z zmm k zmm +// Construct and append a VSQRTPD.RZ_SAE.Z instruction to the active function. +func (c *Context) VSQRTPD_RZ_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VSQRTPD_RZ_SAE_Z(z, k, z1)) } -// VPMOVSXBQ: Move Packed Byte Integers to Quadword Integers with Sign Extension. +// VSQRTPD_RZ_SAE_Z: Compute Square Roots of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). // // Forms: // -// VPMOVSXBQ xmm xmm -// VPMOVSXBQ m16 xmm -// VPMOVSXBQ xmm ymm -// VPMOVSXBQ m32 ymm -// Construct and append a VPMOVSXBQ instruction to the active function. +// VSQRTPD.RZ_SAE.Z zmm k zmm +// Construct and append a VSQRTPD.RZ_SAE.Z instruction to the active function. // Operates on the global context. -func VPMOVSXBQ(mx, xy operand.Op) { ctx.VPMOVSXBQ(mx, xy) } +func VSQRTPD_RZ_SAE_Z(z, k, z1 operand.Op) { ctx.VSQRTPD_RZ_SAE_Z(z, k, z1) } -// VPMOVSXBW: Move Packed Byte Integers to Word Integers with Sign Extension. +// VSQRTPD_Z: Compute Square Roots of Packed Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VPMOVSXBW xmm xmm -// VPMOVSXBW m64 xmm -// VPMOVSXBW xmm ymm -// VPMOVSXBW m128 ymm -// Construct and append a VPMOVSXBW instruction to the active function. -func (c *Context) VPMOVSXBW(mx, xy operand.Op) { - if inst, err := x86.VPMOVSXBW(mx, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTPD.Z m128 k xmm +// VSQRTPD.Z m256 k ymm +// VSQRTPD.Z xmm k xmm +// VSQRTPD.Z ymm k ymm +// VSQRTPD.Z m512 k zmm +// VSQRTPD.Z zmm k zmm +// Construct and append a VSQRTPD.Z instruction to the active function. +func (c *Context) VSQRTPD_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VSQRTPD_Z(mxyz, k, xyz)) } -// VPMOVSXBW: Move Packed Byte Integers to Word Integers with Sign Extension. +// VSQRTPD_Z: Compute Square Roots of Packed Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VPMOVSXBW xmm xmm -// VPMOVSXBW m64 xmm -// VPMOVSXBW xmm ymm -// VPMOVSXBW m128 ymm -// Construct and append a VPMOVSXBW instruction to the active function. +// VSQRTPD.Z m128 k xmm +// VSQRTPD.Z m256 k ymm +// VSQRTPD.Z xmm k xmm +// VSQRTPD.Z ymm k ymm +// VSQRTPD.Z m512 k zmm +// VSQRTPD.Z zmm k zmm +// Construct and append a VSQRTPD.Z instruction to the active function. // Operates on the global context. -func VPMOVSXBW(mx, xy operand.Op) { ctx.VPMOVSXBW(mx, xy) } +func VSQRTPD_Z(mxyz, k, xyz operand.Op) { ctx.VSQRTPD_Z(mxyz, k, xyz) } -// VPMOVSXDQ: Move Packed Doubleword Integers to Quadword Integers with Sign Extension. +// VSQRTPS: Compute Square Roots of Packed Single-Precision Floating-Point Values. // // Forms: // -// VPMOVSXDQ xmm xmm -// VPMOVSXDQ m64 xmm -// VPMOVSXDQ xmm ymm -// VPMOVSXDQ m128 ymm -// Construct and append a VPMOVSXDQ instruction to the active function. -func (c *Context) VPMOVSXDQ(mx, xy operand.Op) { - if inst, err := x86.VPMOVSXDQ(mx, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTPS m128 xmm +// VSQRTPS m256 ymm +// VSQRTPS xmm xmm +// VSQRTPS ymm ymm +// VSQRTPS m128 k xmm +// VSQRTPS m256 k ymm +// VSQRTPS xmm k xmm +// VSQRTPS ymm k ymm +// VSQRTPS m512 k zmm +// VSQRTPS m512 zmm +// VSQRTPS zmm k zmm +// VSQRTPS zmm zmm +// Construct and append a VSQRTPS instruction to the active function. +func (c *Context) VSQRTPS(ops ...operand.Op) { + c.addinstruction(x86.VSQRTPS(ops...)) } -// VPMOVSXDQ: Move Packed Doubleword Integers to Quadword Integers with Sign Extension. +// VSQRTPS: Compute Square Roots of Packed Single-Precision Floating-Point Values. // // Forms: // -// VPMOVSXDQ xmm xmm -// VPMOVSXDQ m64 xmm -// VPMOVSXDQ xmm ymm -// VPMOVSXDQ m128 ymm -// Construct and append a VPMOVSXDQ instruction to the active function. +// VSQRTPS m128 xmm +// VSQRTPS m256 ymm +// VSQRTPS xmm xmm +// VSQRTPS ymm ymm +// VSQRTPS m128 k xmm +// VSQRTPS m256 k ymm +// VSQRTPS xmm k xmm +// VSQRTPS ymm k ymm +// VSQRTPS m512 k zmm +// VSQRTPS m512 zmm +// VSQRTPS zmm k zmm +// VSQRTPS zmm zmm +// Construct and append a VSQRTPS instruction to the active function. // Operates on the global context. -func VPMOVSXDQ(mx, xy operand.Op) { ctx.VPMOVSXDQ(mx, xy) } +func VSQRTPS(ops ...operand.Op) { ctx.VSQRTPS(ops...) } -// VPMOVSXWD: Move Packed Word Integers to Doubleword Integers with Sign Extension. +// VSQRTPS_BCST: Compute Square Roots of Packed Single-Precision Floating-Point Values (Broadcast). // // Forms: // -// VPMOVSXWD xmm xmm -// VPMOVSXWD m64 xmm -// VPMOVSXWD xmm ymm -// VPMOVSXWD m128 ymm -// Construct and append a VPMOVSXWD instruction to the active function. -func (c *Context) VPMOVSXWD(mx, xy operand.Op) { - if inst, err := x86.VPMOVSXWD(mx, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTPS.BCST m32 k xmm +// VSQRTPS.BCST m32 k ymm +// VSQRTPS.BCST m32 xmm +// VSQRTPS.BCST m32 ymm +// VSQRTPS.BCST m32 k zmm +// VSQRTPS.BCST m32 zmm +// Construct and append a VSQRTPS.BCST instruction to the active function. +func (c *Context) VSQRTPS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VSQRTPS_BCST(ops...)) } -// VPMOVSXWD: Move Packed Word Integers to Doubleword Integers with Sign Extension. +// VSQRTPS_BCST: Compute Square Roots of Packed Single-Precision Floating-Point Values (Broadcast). // // Forms: // -// VPMOVSXWD xmm xmm -// VPMOVSXWD m64 xmm -// VPMOVSXWD xmm ymm -// VPMOVSXWD m128 ymm -// Construct and append a VPMOVSXWD instruction to the active function. +// VSQRTPS.BCST m32 k xmm +// VSQRTPS.BCST m32 k ymm +// VSQRTPS.BCST m32 xmm +// VSQRTPS.BCST m32 ymm +// VSQRTPS.BCST m32 k zmm +// VSQRTPS.BCST m32 zmm +// Construct and append a VSQRTPS.BCST instruction to the active function. // Operates on the global context. -func VPMOVSXWD(mx, xy operand.Op) { ctx.VPMOVSXWD(mx, xy) } +func VSQRTPS_BCST(ops ...operand.Op) { ctx.VSQRTPS_BCST(ops...) } -// VPMOVSXWQ: Move Packed Word Integers to Quadword Integers with Sign Extension. +// VSQRTPS_BCST_Z: Compute Square Roots of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VPMOVSXWQ xmm xmm -// VPMOVSXWQ m32 xmm -// VPMOVSXWQ xmm ymm -// VPMOVSXWQ m64 ymm -// Construct and append a VPMOVSXWQ instruction to the active function. -func (c *Context) VPMOVSXWQ(mx, xy operand.Op) { - if inst, err := x86.VPMOVSXWQ(mx, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTPS.BCST.Z m32 k xmm +// VSQRTPS.BCST.Z m32 k ymm +// VSQRTPS.BCST.Z m32 k zmm +// Construct and append a VSQRTPS.BCST.Z instruction to the active function. +func (c *Context) VSQRTPS_BCST_Z(m, k, xyz operand.Op) { + c.addinstruction(x86.VSQRTPS_BCST_Z(m, k, xyz)) } -// VPMOVSXWQ: Move Packed Word Integers to Quadword Integers with Sign Extension. +// VSQRTPS_BCST_Z: Compute Square Roots of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VPMOVSXWQ xmm xmm -// VPMOVSXWQ m32 xmm -// VPMOVSXWQ xmm ymm -// VPMOVSXWQ m64 ymm -// Construct and append a VPMOVSXWQ instruction to the active function. +// VSQRTPS.BCST.Z m32 k xmm +// VSQRTPS.BCST.Z m32 k ymm +// VSQRTPS.BCST.Z m32 k zmm +// Construct and append a VSQRTPS.BCST.Z instruction to the active function. // Operates on the global context. -func VPMOVSXWQ(mx, xy operand.Op) { ctx.VPMOVSXWQ(mx, xy) } +func VSQRTPS_BCST_Z(m, k, xyz operand.Op) { ctx.VSQRTPS_BCST_Z(m, k, xyz) } -// VPMOVZXBD: Move Packed Byte Integers to Doubleword Integers with Zero Extension. +// VSQRTPS_RD_SAE: Compute Square Roots of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). // // Forms: // -// VPMOVZXBD xmm xmm -// VPMOVZXBD m32 xmm -// VPMOVZXBD xmm ymm -// VPMOVZXBD m64 ymm -// Construct and append a VPMOVZXBD instruction to the active function. -func (c *Context) VPMOVZXBD(mx, xy operand.Op) { - if inst, err := x86.VPMOVZXBD(mx, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTPS.RD_SAE zmm k zmm +// VSQRTPS.RD_SAE zmm zmm +// Construct and append a VSQRTPS.RD_SAE instruction to the active function. +func (c *Context) VSQRTPS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSQRTPS_RD_SAE(ops...)) } -// VPMOVZXBD: Move Packed Byte Integers to Doubleword Integers with Zero Extension. +// VSQRTPS_RD_SAE: Compute Square Roots of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). // // Forms: // -// VPMOVZXBD xmm xmm -// VPMOVZXBD m32 xmm -// VPMOVZXBD xmm ymm -// VPMOVZXBD m64 ymm -// Construct and append a VPMOVZXBD instruction to the active function. +// VSQRTPS.RD_SAE zmm k zmm +// VSQRTPS.RD_SAE zmm zmm +// Construct and append a VSQRTPS.RD_SAE instruction to the active function. // Operates on the global context. -func VPMOVZXBD(mx, xy operand.Op) { ctx.VPMOVZXBD(mx, xy) } +func VSQRTPS_RD_SAE(ops ...operand.Op) { ctx.VSQRTPS_RD_SAE(ops...) } -// VPMOVZXBQ: Move Packed Byte Integers to Quadword Integers with Zero Extension. +// VSQRTPS_RD_SAE_Z: Compute Square Roots of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VPMOVZXBQ xmm xmm -// VPMOVZXBQ m16 xmm -// VPMOVZXBQ xmm ymm -// VPMOVZXBQ m32 ymm -// Construct and append a VPMOVZXBQ instruction to the active function. -func (c *Context) VPMOVZXBQ(mx, xy operand.Op) { - if inst, err := x86.VPMOVZXBQ(mx, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTPS.RD_SAE.Z zmm k zmm +// Construct and append a VSQRTPS.RD_SAE.Z instruction to the active function. +func (c *Context) VSQRTPS_RD_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VSQRTPS_RD_SAE_Z(z, k, z1)) } -// VPMOVZXBQ: Move Packed Byte Integers to Quadword Integers with Zero Extension. +// VSQRTPS_RD_SAE_Z: Compute Square Roots of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VPMOVZXBQ xmm xmm -// VPMOVZXBQ m16 xmm -// VPMOVZXBQ xmm ymm -// VPMOVZXBQ m32 ymm -// Construct and append a VPMOVZXBQ instruction to the active function. +// VSQRTPS.RD_SAE.Z zmm k zmm +// Construct and append a VSQRTPS.RD_SAE.Z instruction to the active function. // Operates on the global context. -func VPMOVZXBQ(mx, xy operand.Op) { ctx.VPMOVZXBQ(mx, xy) } +func VSQRTPS_RD_SAE_Z(z, k, z1 operand.Op) { ctx.VSQRTPS_RD_SAE_Z(z, k, z1) } -// VPMOVZXBW: Move Packed Byte Integers to Word Integers with Zero Extension. +// VSQRTPS_RN_SAE: Compute Square Roots of Packed Single-Precision Floating-Point Values (Round Towards Nearest). // // Forms: // -// VPMOVZXBW xmm xmm -// VPMOVZXBW m64 xmm -// VPMOVZXBW xmm ymm -// VPMOVZXBW m128 ymm -// Construct and append a VPMOVZXBW instruction to the active function. -func (c *Context) VPMOVZXBW(mx, xy operand.Op) { - if inst, err := x86.VPMOVZXBW(mx, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTPS.RN_SAE zmm k zmm +// VSQRTPS.RN_SAE zmm zmm +// Construct and append a VSQRTPS.RN_SAE instruction to the active function. +func (c *Context) VSQRTPS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSQRTPS_RN_SAE(ops...)) } -// VPMOVZXBW: Move Packed Byte Integers to Word Integers with Zero Extension. +// VSQRTPS_RN_SAE: Compute Square Roots of Packed Single-Precision Floating-Point Values (Round Towards Nearest). // // Forms: // -// VPMOVZXBW xmm xmm -// VPMOVZXBW m64 xmm -// VPMOVZXBW xmm ymm -// VPMOVZXBW m128 ymm -// Construct and append a VPMOVZXBW instruction to the active function. +// VSQRTPS.RN_SAE zmm k zmm +// VSQRTPS.RN_SAE zmm zmm +// Construct and append a VSQRTPS.RN_SAE instruction to the active function. // Operates on the global context. -func VPMOVZXBW(mx, xy operand.Op) { ctx.VPMOVZXBW(mx, xy) } +func VSQRTPS_RN_SAE(ops ...operand.Op) { ctx.VSQRTPS_RN_SAE(ops...) } -// VPMOVZXDQ: Move Packed Doubleword Integers to Quadword Integers with Zero Extension. +// VSQRTPS_RN_SAE_Z: Compute Square Roots of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VPMOVZXDQ xmm xmm -// VPMOVZXDQ m64 xmm -// VPMOVZXDQ xmm ymm -// VPMOVZXDQ m128 ymm -// Construct and append a VPMOVZXDQ instruction to the active function. -func (c *Context) VPMOVZXDQ(mx, xy operand.Op) { - if inst, err := x86.VPMOVZXDQ(mx, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTPS.RN_SAE.Z zmm k zmm +// Construct and append a VSQRTPS.RN_SAE.Z instruction to the active function. +func (c *Context) VSQRTPS_RN_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VSQRTPS_RN_SAE_Z(z, k, z1)) } -// VPMOVZXDQ: Move Packed Doubleword Integers to Quadword Integers with Zero Extension. +// VSQRTPS_RN_SAE_Z: Compute Square Roots of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VPMOVZXDQ xmm xmm -// VPMOVZXDQ m64 xmm -// VPMOVZXDQ xmm ymm -// VPMOVZXDQ m128 ymm -// Construct and append a VPMOVZXDQ instruction to the active function. +// VSQRTPS.RN_SAE.Z zmm k zmm +// Construct and append a VSQRTPS.RN_SAE.Z instruction to the active function. // Operates on the global context. -func VPMOVZXDQ(mx, xy operand.Op) { ctx.VPMOVZXDQ(mx, xy) } +func VSQRTPS_RN_SAE_Z(z, k, z1 operand.Op) { ctx.VSQRTPS_RN_SAE_Z(z, k, z1) } -// VPMOVZXWD: Move Packed Word Integers to Doubleword Integers with Zero Extension. +// VSQRTPS_RU_SAE: Compute Square Roots of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). // // Forms: // -// VPMOVZXWD xmm xmm -// VPMOVZXWD m64 xmm -// VPMOVZXWD xmm ymm -// VPMOVZXWD m128 ymm -// Construct and append a VPMOVZXWD instruction to the active function. -func (c *Context) VPMOVZXWD(mx, xy operand.Op) { - if inst, err := x86.VPMOVZXWD(mx, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTPS.RU_SAE zmm k zmm +// VSQRTPS.RU_SAE zmm zmm +// Construct and append a VSQRTPS.RU_SAE instruction to the active function. +func (c *Context) VSQRTPS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSQRTPS_RU_SAE(ops...)) } -// VPMOVZXWD: Move Packed Word Integers to Doubleword Integers with Zero Extension. +// VSQRTPS_RU_SAE: Compute Square Roots of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). // // Forms: // -// VPMOVZXWD xmm xmm -// VPMOVZXWD m64 xmm -// VPMOVZXWD xmm ymm -// VPMOVZXWD m128 ymm -// Construct and append a VPMOVZXWD instruction to the active function. +// VSQRTPS.RU_SAE zmm k zmm +// VSQRTPS.RU_SAE zmm zmm +// Construct and append a VSQRTPS.RU_SAE instruction to the active function. // Operates on the global context. -func VPMOVZXWD(mx, xy operand.Op) { ctx.VPMOVZXWD(mx, xy) } +func VSQRTPS_RU_SAE(ops ...operand.Op) { ctx.VSQRTPS_RU_SAE(ops...) } -// VPMOVZXWQ: Move Packed Word Integers to Quadword Integers with Zero Extension. +// VSQRTPS_RU_SAE_Z: Compute Square Roots of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VPMOVZXWQ xmm xmm -// VPMOVZXWQ m32 xmm -// VPMOVZXWQ xmm ymm -// VPMOVZXWQ m64 ymm -// Construct and append a VPMOVZXWQ instruction to the active function. -func (c *Context) VPMOVZXWQ(mx, xy operand.Op) { - if inst, err := x86.VPMOVZXWQ(mx, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTPS.RU_SAE.Z zmm k zmm +// Construct and append a VSQRTPS.RU_SAE.Z instruction to the active function. +func (c *Context) VSQRTPS_RU_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VSQRTPS_RU_SAE_Z(z, k, z1)) } -// VPMOVZXWQ: Move Packed Word Integers to Quadword Integers with Zero Extension. +// VSQRTPS_RU_SAE_Z: Compute Square Roots of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VPMOVZXWQ xmm xmm -// VPMOVZXWQ m32 xmm -// VPMOVZXWQ xmm ymm -// VPMOVZXWQ m64 ymm -// Construct and append a VPMOVZXWQ instruction to the active function. +// VSQRTPS.RU_SAE.Z zmm k zmm +// Construct and append a VSQRTPS.RU_SAE.Z instruction to the active function. // Operates on the global context. -func VPMOVZXWQ(mx, xy operand.Op) { ctx.VPMOVZXWQ(mx, xy) } +func VSQRTPS_RU_SAE_Z(z, k, z1 operand.Op) { ctx.VSQRTPS_RU_SAE_Z(z, k, z1) } -// VPMULDQ: Multiply Packed Signed Doubleword Integers and Store Quadword Result. +// VSQRTPS_RZ_SAE: Compute Square Roots of Packed Single-Precision Floating-Point Values (Round Towards Zero). // // Forms: // -// VPMULDQ xmm xmm xmm -// VPMULDQ m128 xmm xmm -// VPMULDQ ymm ymm ymm -// VPMULDQ m256 ymm ymm -// Construct and append a VPMULDQ instruction to the active function. -func (c *Context) VPMULDQ(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPMULDQ(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTPS.RZ_SAE zmm k zmm +// VSQRTPS.RZ_SAE zmm zmm +// Construct and append a VSQRTPS.RZ_SAE instruction to the active function. +func (c *Context) VSQRTPS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSQRTPS_RZ_SAE(ops...)) } -// VPMULDQ: Multiply Packed Signed Doubleword Integers and Store Quadword Result. +// VSQRTPS_RZ_SAE: Compute Square Roots of Packed Single-Precision Floating-Point Values (Round Towards Zero). // // Forms: // -// VPMULDQ xmm xmm xmm -// VPMULDQ m128 xmm xmm -// VPMULDQ ymm ymm ymm -// VPMULDQ m256 ymm ymm -// Construct and append a VPMULDQ instruction to the active function. +// VSQRTPS.RZ_SAE zmm k zmm +// VSQRTPS.RZ_SAE zmm zmm +// Construct and append a VSQRTPS.RZ_SAE instruction to the active function. // Operates on the global context. -func VPMULDQ(mxy, xy, xy1 operand.Op) { ctx.VPMULDQ(mxy, xy, xy1) } +func VSQRTPS_RZ_SAE(ops ...operand.Op) { ctx.VSQRTPS_RZ_SAE(ops...) } -// VPMULHRSW: Packed Multiply Signed Word Integers and Store High Result with Round and Scale. +// VSQRTPS_RZ_SAE_Z: Compute Square Roots of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). // // Forms: // -// VPMULHRSW xmm xmm xmm -// VPMULHRSW m128 xmm xmm -// VPMULHRSW ymm ymm ymm -// VPMULHRSW m256 ymm ymm -// Construct and append a VPMULHRSW instruction to the active function. -func (c *Context) VPMULHRSW(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPMULHRSW(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTPS.RZ_SAE.Z zmm k zmm +// Construct and append a VSQRTPS.RZ_SAE.Z instruction to the active function. +func (c *Context) VSQRTPS_RZ_SAE_Z(z, k, z1 operand.Op) { + c.addinstruction(x86.VSQRTPS_RZ_SAE_Z(z, k, z1)) } -// VPMULHRSW: Packed Multiply Signed Word Integers and Store High Result with Round and Scale. +// VSQRTPS_RZ_SAE_Z: Compute Square Roots of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). // // Forms: // -// VPMULHRSW xmm xmm xmm -// VPMULHRSW m128 xmm xmm -// VPMULHRSW ymm ymm ymm -// VPMULHRSW m256 ymm ymm -// Construct and append a VPMULHRSW instruction to the active function. +// VSQRTPS.RZ_SAE.Z zmm k zmm +// Construct and append a VSQRTPS.RZ_SAE.Z instruction to the active function. // Operates on the global context. -func VPMULHRSW(mxy, xy, xy1 operand.Op) { ctx.VPMULHRSW(mxy, xy, xy1) } +func VSQRTPS_RZ_SAE_Z(z, k, z1 operand.Op) { ctx.VSQRTPS_RZ_SAE_Z(z, k, z1) } -// VPMULHUW: Multiply Packed Unsigned Word Integers and Store High Result. +// VSQRTPS_Z: Compute Square Roots of Packed Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VPMULHUW xmm xmm xmm -// VPMULHUW m128 xmm xmm -// VPMULHUW ymm ymm ymm -// VPMULHUW m256 ymm ymm -// Construct and append a VPMULHUW instruction to the active function. -func (c *Context) VPMULHUW(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPMULHUW(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTPS.Z m128 k xmm +// VSQRTPS.Z m256 k ymm +// VSQRTPS.Z xmm k xmm +// VSQRTPS.Z ymm k ymm +// VSQRTPS.Z m512 k zmm +// VSQRTPS.Z zmm k zmm +// Construct and append a VSQRTPS.Z instruction to the active function. +func (c *Context) VSQRTPS_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VSQRTPS_Z(mxyz, k, xyz)) } -// VPMULHUW: Multiply Packed Unsigned Word Integers and Store High Result. +// VSQRTPS_Z: Compute Square Roots of Packed Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VPMULHUW xmm xmm xmm -// VPMULHUW m128 xmm xmm -// VPMULHUW ymm ymm ymm -// VPMULHUW m256 ymm ymm -// Construct and append a VPMULHUW instruction to the active function. +// VSQRTPS.Z m128 k xmm +// VSQRTPS.Z m256 k ymm +// VSQRTPS.Z xmm k xmm +// VSQRTPS.Z ymm k ymm +// VSQRTPS.Z m512 k zmm +// VSQRTPS.Z zmm k zmm +// Construct and append a VSQRTPS.Z instruction to the active function. // Operates on the global context. -func VPMULHUW(mxy, xy, xy1 operand.Op) { ctx.VPMULHUW(mxy, xy, xy1) } +func VSQRTPS_Z(mxyz, k, xyz operand.Op) { ctx.VSQRTPS_Z(mxyz, k, xyz) } -// VPMULHW: Multiply Packed Signed Word Integers and Store High Result. +// VSQRTSD: Compute Square Root of Scalar Double-Precision Floating-Point Value. // // Forms: // -// VPMULHW xmm xmm xmm -// VPMULHW m128 xmm xmm -// VPMULHW ymm ymm ymm -// VPMULHW m256 ymm ymm -// Construct and append a VPMULHW instruction to the active function. -func (c *Context) VPMULHW(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPMULHW(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTSD m64 xmm xmm +// VSQRTSD xmm xmm xmm +// VSQRTSD m64 xmm k xmm +// VSQRTSD xmm xmm k xmm +// Construct and append a VSQRTSD instruction to the active function. +func (c *Context) VSQRTSD(ops ...operand.Op) { + c.addinstruction(x86.VSQRTSD(ops...)) } -// VPMULHW: Multiply Packed Signed Word Integers and Store High Result. +// VSQRTSD: Compute Square Root of Scalar Double-Precision Floating-Point Value. // // Forms: // -// VPMULHW xmm xmm xmm -// VPMULHW m128 xmm xmm -// VPMULHW ymm ymm ymm -// VPMULHW m256 ymm ymm -// Construct and append a VPMULHW instruction to the active function. +// VSQRTSD m64 xmm xmm +// VSQRTSD xmm xmm xmm +// VSQRTSD m64 xmm k xmm +// VSQRTSD xmm xmm k xmm +// Construct and append a VSQRTSD instruction to the active function. // Operates on the global context. -func VPMULHW(mxy, xy, xy1 operand.Op) { ctx.VPMULHW(mxy, xy, xy1) } +func VSQRTSD(ops ...operand.Op) { ctx.VSQRTSD(ops...) } -// VPMULLD: Multiply Packed Signed Doubleword Integers and Store Low Result. +// VSQRTSD_RD_SAE: Compute Square Root of Scalar Double-Precision Floating-Point Value (Round Towards Negative Infinity). // // Forms: // -// VPMULLD xmm xmm xmm -// VPMULLD m128 xmm xmm -// VPMULLD ymm ymm ymm -// VPMULLD m256 ymm ymm -// Construct and append a VPMULLD instruction to the active function. -func (c *Context) VPMULLD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPMULLD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTSD.RD_SAE xmm xmm k xmm +// VSQRTSD.RD_SAE xmm xmm xmm +// Construct and append a VSQRTSD.RD_SAE instruction to the active function. +func (c *Context) VSQRTSD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSQRTSD_RD_SAE(ops...)) } -// VPMULLD: Multiply Packed Signed Doubleword Integers and Store Low Result. +// VSQRTSD_RD_SAE: Compute Square Root of Scalar Double-Precision Floating-Point Value (Round Towards Negative Infinity). // // Forms: // -// VPMULLD xmm xmm xmm -// VPMULLD m128 xmm xmm -// VPMULLD ymm ymm ymm -// VPMULLD m256 ymm ymm -// Construct and append a VPMULLD instruction to the active function. +// VSQRTSD.RD_SAE xmm xmm k xmm +// VSQRTSD.RD_SAE xmm xmm xmm +// Construct and append a VSQRTSD.RD_SAE instruction to the active function. // Operates on the global context. -func VPMULLD(mxy, xy, xy1 operand.Op) { ctx.VPMULLD(mxy, xy, xy1) } +func VSQRTSD_RD_SAE(ops ...operand.Op) { ctx.VSQRTSD_RD_SAE(ops...) } -// VPMULLW: Multiply Packed Signed Word Integers and Store Low Result. +// VSQRTSD_RD_SAE_Z: Compute Square Root of Scalar Double-Precision Floating-Point Value (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VPMULLW xmm xmm xmm -// VPMULLW m128 xmm xmm -// VPMULLW ymm ymm ymm -// VPMULLW m256 ymm ymm -// Construct and append a VPMULLW instruction to the active function. -func (c *Context) VPMULLW(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPMULLW(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTSD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VSQRTSD.RD_SAE.Z instruction to the active function. +func (c *Context) VSQRTSD_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VSQRTSD_RD_SAE_Z(x, x1, k, x2)) } -// VPMULLW: Multiply Packed Signed Word Integers and Store Low Result. +// VSQRTSD_RD_SAE_Z: Compute Square Root of Scalar Double-Precision Floating-Point Value (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VPMULLW xmm xmm xmm -// VPMULLW m128 xmm xmm -// VPMULLW ymm ymm ymm -// VPMULLW m256 ymm ymm -// Construct and append a VPMULLW instruction to the active function. +// VSQRTSD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VSQRTSD.RD_SAE.Z instruction to the active function. // Operates on the global context. -func VPMULLW(mxy, xy, xy1 operand.Op) { ctx.VPMULLW(mxy, xy, xy1) } +func VSQRTSD_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VSQRTSD_RD_SAE_Z(x, x1, k, x2) } -// VPMULUDQ: Multiply Packed Unsigned Doubleword Integers. +// VSQRTSD_RN_SAE: Compute Square Root of Scalar Double-Precision Floating-Point Value (Round Towards Nearest). // // Forms: // -// VPMULUDQ xmm xmm xmm -// VPMULUDQ m128 xmm xmm -// VPMULUDQ ymm ymm ymm -// VPMULUDQ m256 ymm ymm -// Construct and append a VPMULUDQ instruction to the active function. -func (c *Context) VPMULUDQ(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPMULUDQ(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTSD.RN_SAE xmm xmm k xmm +// VSQRTSD.RN_SAE xmm xmm xmm +// Construct and append a VSQRTSD.RN_SAE instruction to the active function. +func (c *Context) VSQRTSD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSQRTSD_RN_SAE(ops...)) } -// VPMULUDQ: Multiply Packed Unsigned Doubleword Integers. +// VSQRTSD_RN_SAE: Compute Square Root of Scalar Double-Precision Floating-Point Value (Round Towards Nearest). // // Forms: // -// VPMULUDQ xmm xmm xmm -// VPMULUDQ m128 xmm xmm -// VPMULUDQ ymm ymm ymm -// VPMULUDQ m256 ymm ymm -// Construct and append a VPMULUDQ instruction to the active function. +// VSQRTSD.RN_SAE xmm xmm k xmm +// VSQRTSD.RN_SAE xmm xmm xmm +// Construct and append a VSQRTSD.RN_SAE instruction to the active function. // Operates on the global context. -func VPMULUDQ(mxy, xy, xy1 operand.Op) { ctx.VPMULUDQ(mxy, xy, xy1) } +func VSQRTSD_RN_SAE(ops ...operand.Op) { ctx.VSQRTSD_RN_SAE(ops...) } -// VPOR: Packed Bitwise Logical OR. +// VSQRTSD_RN_SAE_Z: Compute Square Root of Scalar Double-Precision Floating-Point Value (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VPOR xmm xmm xmm -// VPOR m128 xmm xmm -// VPOR ymm ymm ymm -// VPOR m256 ymm ymm -// Construct and append a VPOR instruction to the active function. -func (c *Context) VPOR(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPOR(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTSD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VSQRTSD.RN_SAE.Z instruction to the active function. +func (c *Context) VSQRTSD_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VSQRTSD_RN_SAE_Z(x, x1, k, x2)) } -// VPOR: Packed Bitwise Logical OR. +// VSQRTSD_RN_SAE_Z: Compute Square Root of Scalar Double-Precision Floating-Point Value (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VPOR xmm xmm xmm -// VPOR m128 xmm xmm -// VPOR ymm ymm ymm -// VPOR m256 ymm ymm -// Construct and append a VPOR instruction to the active function. +// VSQRTSD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VSQRTSD.RN_SAE.Z instruction to the active function. // Operates on the global context. -func VPOR(mxy, xy, xy1 operand.Op) { ctx.VPOR(mxy, xy, xy1) } +func VSQRTSD_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VSQRTSD_RN_SAE_Z(x, x1, k, x2) } -// VPSADBW: Compute Sum of Absolute Differences. +// VSQRTSD_RU_SAE: Compute Square Root of Scalar Double-Precision Floating-Point Value (Round Towards Positive Infinity). // // Forms: // -// VPSADBW xmm xmm xmm -// VPSADBW m128 xmm xmm -// VPSADBW ymm ymm ymm -// VPSADBW m256 ymm ymm -// Construct and append a VPSADBW instruction to the active function. -func (c *Context) VPSADBW(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPSADBW(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTSD.RU_SAE xmm xmm k xmm +// VSQRTSD.RU_SAE xmm xmm xmm +// Construct and append a VSQRTSD.RU_SAE instruction to the active function. +func (c *Context) VSQRTSD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSQRTSD_RU_SAE(ops...)) } -// VPSADBW: Compute Sum of Absolute Differences. +// VSQRTSD_RU_SAE: Compute Square Root of Scalar Double-Precision Floating-Point Value (Round Towards Positive Infinity). // // Forms: // -// VPSADBW xmm xmm xmm -// VPSADBW m128 xmm xmm -// VPSADBW ymm ymm ymm -// VPSADBW m256 ymm ymm -// Construct and append a VPSADBW instruction to the active function. +// VSQRTSD.RU_SAE xmm xmm k xmm +// VSQRTSD.RU_SAE xmm xmm xmm +// Construct and append a VSQRTSD.RU_SAE instruction to the active function. // Operates on the global context. -func VPSADBW(mxy, xy, xy1 operand.Op) { ctx.VPSADBW(mxy, xy, xy1) } +func VSQRTSD_RU_SAE(ops ...operand.Op) { ctx.VSQRTSD_RU_SAE(ops...) } -// VPSHUFB: Packed Shuffle Bytes. +// VSQRTSD_RU_SAE_Z: Compute Square Root of Scalar Double-Precision Floating-Point Value (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VPSHUFB xmm xmm xmm -// VPSHUFB m128 xmm xmm -// VPSHUFB ymm ymm ymm -// VPSHUFB m256 ymm ymm -// Construct and append a VPSHUFB instruction to the active function. -func (c *Context) VPSHUFB(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPSHUFB(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTSD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VSQRTSD.RU_SAE.Z instruction to the active function. +func (c *Context) VSQRTSD_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VSQRTSD_RU_SAE_Z(x, x1, k, x2)) } -// VPSHUFB: Packed Shuffle Bytes. +// VSQRTSD_RU_SAE_Z: Compute Square Root of Scalar Double-Precision Floating-Point Value (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VPSHUFB xmm xmm xmm -// VPSHUFB m128 xmm xmm -// VPSHUFB ymm ymm ymm -// VPSHUFB m256 ymm ymm -// Construct and append a VPSHUFB instruction to the active function. +// VSQRTSD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VSQRTSD.RU_SAE.Z instruction to the active function. // Operates on the global context. -func VPSHUFB(mxy, xy, xy1 operand.Op) { ctx.VPSHUFB(mxy, xy, xy1) } +func VSQRTSD_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VSQRTSD_RU_SAE_Z(x, x1, k, x2) } -// VPSHUFD: Shuffle Packed Doublewords. +// VSQRTSD_RZ_SAE: Compute Square Root of Scalar Double-Precision Floating-Point Value (Round Towards Zero). // // Forms: // -// VPSHUFD imm8 xmm xmm -// VPSHUFD imm8 m128 xmm -// VPSHUFD imm8 ymm ymm -// VPSHUFD imm8 m256 ymm -// Construct and append a VPSHUFD instruction to the active function. -func (c *Context) VPSHUFD(i, mxy, xy operand.Op) { - if inst, err := x86.VPSHUFD(i, mxy, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTSD.RZ_SAE xmm xmm k xmm +// VSQRTSD.RZ_SAE xmm xmm xmm +// Construct and append a VSQRTSD.RZ_SAE instruction to the active function. +func (c *Context) VSQRTSD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSQRTSD_RZ_SAE(ops...)) } -// VPSHUFD: Shuffle Packed Doublewords. +// VSQRTSD_RZ_SAE: Compute Square Root of Scalar Double-Precision Floating-Point Value (Round Towards Zero). // // Forms: // -// VPSHUFD imm8 xmm xmm -// VPSHUFD imm8 m128 xmm -// VPSHUFD imm8 ymm ymm -// VPSHUFD imm8 m256 ymm -// Construct and append a VPSHUFD instruction to the active function. +// VSQRTSD.RZ_SAE xmm xmm k xmm +// VSQRTSD.RZ_SAE xmm xmm xmm +// Construct and append a VSQRTSD.RZ_SAE instruction to the active function. // Operates on the global context. -func VPSHUFD(i, mxy, xy operand.Op) { ctx.VPSHUFD(i, mxy, xy) } +func VSQRTSD_RZ_SAE(ops ...operand.Op) { ctx.VSQRTSD_RZ_SAE(ops...) } -// VPSHUFHW: Shuffle Packed High Words. +// VSQRTSD_RZ_SAE_Z: Compute Square Root of Scalar Double-Precision Floating-Point Value (Round Towards Zero, Zeroing Masking). // // Forms: // -// VPSHUFHW imm8 xmm xmm -// VPSHUFHW imm8 m128 xmm -// VPSHUFHW imm8 ymm ymm -// VPSHUFHW imm8 m256 ymm -// Construct and append a VPSHUFHW instruction to the active function. -func (c *Context) VPSHUFHW(i, mxy, xy operand.Op) { - if inst, err := x86.VPSHUFHW(i, mxy, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTSD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VSQRTSD.RZ_SAE.Z instruction to the active function. +func (c *Context) VSQRTSD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VSQRTSD_RZ_SAE_Z(x, x1, k, x2)) } -// VPSHUFHW: Shuffle Packed High Words. +// VSQRTSD_RZ_SAE_Z: Compute Square Root of Scalar Double-Precision Floating-Point Value (Round Towards Zero, Zeroing Masking). // // Forms: // -// VPSHUFHW imm8 xmm xmm -// VPSHUFHW imm8 m128 xmm -// VPSHUFHW imm8 ymm ymm -// VPSHUFHW imm8 m256 ymm -// Construct and append a VPSHUFHW instruction to the active function. +// VSQRTSD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VSQRTSD.RZ_SAE.Z instruction to the active function. // Operates on the global context. -func VPSHUFHW(i, mxy, xy operand.Op) { ctx.VPSHUFHW(i, mxy, xy) } +func VSQRTSD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VSQRTSD_RZ_SAE_Z(x, x1, k, x2) } -// VPSHUFLW: Shuffle Packed Low Words. +// VSQRTSD_Z: Compute Square Root of Scalar Double-Precision Floating-Point Value (Zeroing Masking). // // Forms: // -// VPSHUFLW imm8 xmm xmm -// VPSHUFLW imm8 m128 xmm -// VPSHUFLW imm8 ymm ymm -// VPSHUFLW imm8 m256 ymm -// Construct and append a VPSHUFLW instruction to the active function. -func (c *Context) VPSHUFLW(i, mxy, xy operand.Op) { - if inst, err := x86.VPSHUFLW(i, mxy, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTSD.Z m64 xmm k xmm +// VSQRTSD.Z xmm xmm k xmm +// Construct and append a VSQRTSD.Z instruction to the active function. +func (c *Context) VSQRTSD_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VSQRTSD_Z(mx, x, k, x1)) } -// VPSHUFLW: Shuffle Packed Low Words. +// VSQRTSD_Z: Compute Square Root of Scalar Double-Precision Floating-Point Value (Zeroing Masking). // // Forms: // -// VPSHUFLW imm8 xmm xmm -// VPSHUFLW imm8 m128 xmm -// VPSHUFLW imm8 ymm ymm -// VPSHUFLW imm8 m256 ymm -// Construct and append a VPSHUFLW instruction to the active function. +// VSQRTSD.Z m64 xmm k xmm +// VSQRTSD.Z xmm xmm k xmm +// Construct and append a VSQRTSD.Z instruction to the active function. // Operates on the global context. -func VPSHUFLW(i, mxy, xy operand.Op) { ctx.VPSHUFLW(i, mxy, xy) } +func VSQRTSD_Z(mx, x, k, x1 operand.Op) { ctx.VSQRTSD_Z(mx, x, k, x1) } -// VPSIGNB: Packed Sign of Byte Integers. +// VSQRTSS: Compute Square Root of Scalar Single-Precision Floating-Point Value. // // Forms: // -// VPSIGNB xmm xmm xmm -// VPSIGNB m128 xmm xmm -// VPSIGNB ymm ymm ymm -// VPSIGNB m256 ymm ymm -// Construct and append a VPSIGNB instruction to the active function. -func (c *Context) VPSIGNB(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPSIGNB(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTSS m32 xmm xmm +// VSQRTSS xmm xmm xmm +// VSQRTSS m32 xmm k xmm +// VSQRTSS xmm xmm k xmm +// Construct and append a VSQRTSS instruction to the active function. +func (c *Context) VSQRTSS(ops ...operand.Op) { + c.addinstruction(x86.VSQRTSS(ops...)) } -// VPSIGNB: Packed Sign of Byte Integers. +// VSQRTSS: Compute Square Root of Scalar Single-Precision Floating-Point Value. // // Forms: // -// VPSIGNB xmm xmm xmm -// VPSIGNB m128 xmm xmm -// VPSIGNB ymm ymm ymm -// VPSIGNB m256 ymm ymm -// Construct and append a VPSIGNB instruction to the active function. +// VSQRTSS m32 xmm xmm +// VSQRTSS xmm xmm xmm +// VSQRTSS m32 xmm k xmm +// VSQRTSS xmm xmm k xmm +// Construct and append a VSQRTSS instruction to the active function. // Operates on the global context. -func VPSIGNB(mxy, xy, xy1 operand.Op) { ctx.VPSIGNB(mxy, xy, xy1) } +func VSQRTSS(ops ...operand.Op) { ctx.VSQRTSS(ops...) } -// VPSIGND: Packed Sign of Doubleword Integers. +// VSQRTSS_RD_SAE: Compute Square Root of Scalar Single-Precision Floating-Point Value (Round Towards Negative Infinity). // // Forms: // -// VPSIGND xmm xmm xmm -// VPSIGND m128 xmm xmm -// VPSIGND ymm ymm ymm -// VPSIGND m256 ymm ymm -// Construct and append a VPSIGND instruction to the active function. -func (c *Context) VPSIGND(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPSIGND(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTSS.RD_SAE xmm xmm k xmm +// VSQRTSS.RD_SAE xmm xmm xmm +// Construct and append a VSQRTSS.RD_SAE instruction to the active function. +func (c *Context) VSQRTSS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSQRTSS_RD_SAE(ops...)) } -// VPSIGND: Packed Sign of Doubleword Integers. +// VSQRTSS_RD_SAE: Compute Square Root of Scalar Single-Precision Floating-Point Value (Round Towards Negative Infinity). // // Forms: // -// VPSIGND xmm xmm xmm -// VPSIGND m128 xmm xmm -// VPSIGND ymm ymm ymm -// VPSIGND m256 ymm ymm -// Construct and append a VPSIGND instruction to the active function. +// VSQRTSS.RD_SAE xmm xmm k xmm +// VSQRTSS.RD_SAE xmm xmm xmm +// Construct and append a VSQRTSS.RD_SAE instruction to the active function. // Operates on the global context. -func VPSIGND(mxy, xy, xy1 operand.Op) { ctx.VPSIGND(mxy, xy, xy1) } +func VSQRTSS_RD_SAE(ops ...operand.Op) { ctx.VSQRTSS_RD_SAE(ops...) } -// VPSIGNW: Packed Sign of Word Integers. +// VSQRTSS_RD_SAE_Z: Compute Square Root of Scalar Single-Precision Floating-Point Value (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VPSIGNW xmm xmm xmm -// VPSIGNW m128 xmm xmm -// VPSIGNW ymm ymm ymm -// VPSIGNW m256 ymm ymm -// Construct and append a VPSIGNW instruction to the active function. -func (c *Context) VPSIGNW(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPSIGNW(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTSS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VSQRTSS.RD_SAE.Z instruction to the active function. +func (c *Context) VSQRTSS_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VSQRTSS_RD_SAE_Z(x, x1, k, x2)) } -// VPSIGNW: Packed Sign of Word Integers. +// VSQRTSS_RD_SAE_Z: Compute Square Root of Scalar Single-Precision Floating-Point Value (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VPSIGNW xmm xmm xmm -// VPSIGNW m128 xmm xmm -// VPSIGNW ymm ymm ymm -// VPSIGNW m256 ymm ymm -// Construct and append a VPSIGNW instruction to the active function. +// VSQRTSS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VSQRTSS.RD_SAE.Z instruction to the active function. // Operates on the global context. -func VPSIGNW(mxy, xy, xy1 operand.Op) { ctx.VPSIGNW(mxy, xy, xy1) } +func VSQRTSS_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VSQRTSS_RD_SAE_Z(x, x1, k, x2) } -// VPSLLD: Shift Packed Doubleword Data Left Logical. +// VSQRTSS_RN_SAE: Compute Square Root of Scalar Single-Precision Floating-Point Value (Round Towards Nearest). // // Forms: // -// VPSLLD imm8 xmm xmm -// VPSLLD xmm xmm xmm -// VPSLLD m128 xmm xmm -// VPSLLD imm8 ymm ymm -// VPSLLD xmm ymm ymm -// VPSLLD m128 ymm ymm -// Construct and append a VPSLLD instruction to the active function. -func (c *Context) VPSLLD(imx, xy, xy1 operand.Op) { - if inst, err := x86.VPSLLD(imx, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTSS.RN_SAE xmm xmm k xmm +// VSQRTSS.RN_SAE xmm xmm xmm +// Construct and append a VSQRTSS.RN_SAE instruction to the active function. +func (c *Context) VSQRTSS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSQRTSS_RN_SAE(ops...)) } -// VPSLLD: Shift Packed Doubleword Data Left Logical. +// VSQRTSS_RN_SAE: Compute Square Root of Scalar Single-Precision Floating-Point Value (Round Towards Nearest). // // Forms: // -// VPSLLD imm8 xmm xmm -// VPSLLD xmm xmm xmm -// VPSLLD m128 xmm xmm -// VPSLLD imm8 ymm ymm -// VPSLLD xmm ymm ymm -// VPSLLD m128 ymm ymm -// Construct and append a VPSLLD instruction to the active function. +// VSQRTSS.RN_SAE xmm xmm k xmm +// VSQRTSS.RN_SAE xmm xmm xmm +// Construct and append a VSQRTSS.RN_SAE instruction to the active function. // Operates on the global context. -func VPSLLD(imx, xy, xy1 operand.Op) { ctx.VPSLLD(imx, xy, xy1) } +func VSQRTSS_RN_SAE(ops ...operand.Op) { ctx.VSQRTSS_RN_SAE(ops...) } -// VPSLLDQ: Shift Packed Double Quadword Left Logical. +// VSQRTSS_RN_SAE_Z: Compute Square Root of Scalar Single-Precision Floating-Point Value (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VPSLLDQ imm8 xmm xmm -// VPSLLDQ imm8 ymm ymm -// Construct and append a VPSLLDQ instruction to the active function. -func (c *Context) VPSLLDQ(i, xy, xy1 operand.Op) { - if inst, err := x86.VPSLLDQ(i, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTSS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VSQRTSS.RN_SAE.Z instruction to the active function. +func (c *Context) VSQRTSS_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VSQRTSS_RN_SAE_Z(x, x1, k, x2)) } -// VPSLLDQ: Shift Packed Double Quadword Left Logical. +// VSQRTSS_RN_SAE_Z: Compute Square Root of Scalar Single-Precision Floating-Point Value (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VPSLLDQ imm8 xmm xmm -// VPSLLDQ imm8 ymm ymm -// Construct and append a VPSLLDQ instruction to the active function. +// VSQRTSS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VSQRTSS.RN_SAE.Z instruction to the active function. // Operates on the global context. -func VPSLLDQ(i, xy, xy1 operand.Op) { ctx.VPSLLDQ(i, xy, xy1) } +func VSQRTSS_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VSQRTSS_RN_SAE_Z(x, x1, k, x2) } -// VPSLLQ: Shift Packed Quadword Data Left Logical. +// VSQRTSS_RU_SAE: Compute Square Root of Scalar Single-Precision Floating-Point Value (Round Towards Positive Infinity). // // Forms: // -// VPSLLQ imm8 xmm xmm -// VPSLLQ xmm xmm xmm -// VPSLLQ m128 xmm xmm -// VPSLLQ imm8 ymm ymm -// VPSLLQ xmm ymm ymm -// VPSLLQ m128 ymm ymm -// Construct and append a VPSLLQ instruction to the active function. -func (c *Context) VPSLLQ(imx, xy, xy1 operand.Op) { - if inst, err := x86.VPSLLQ(imx, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTSS.RU_SAE xmm xmm k xmm +// VSQRTSS.RU_SAE xmm xmm xmm +// Construct and append a VSQRTSS.RU_SAE instruction to the active function. +func (c *Context) VSQRTSS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSQRTSS_RU_SAE(ops...)) } -// VPSLLQ: Shift Packed Quadword Data Left Logical. +// VSQRTSS_RU_SAE: Compute Square Root of Scalar Single-Precision Floating-Point Value (Round Towards Positive Infinity). // // Forms: // -// VPSLLQ imm8 xmm xmm -// VPSLLQ xmm xmm xmm -// VPSLLQ m128 xmm xmm -// VPSLLQ imm8 ymm ymm -// VPSLLQ xmm ymm ymm -// VPSLLQ m128 ymm ymm -// Construct and append a VPSLLQ instruction to the active function. +// VSQRTSS.RU_SAE xmm xmm k xmm +// VSQRTSS.RU_SAE xmm xmm xmm +// Construct and append a VSQRTSS.RU_SAE instruction to the active function. // Operates on the global context. -func VPSLLQ(imx, xy, xy1 operand.Op) { ctx.VPSLLQ(imx, xy, xy1) } +func VSQRTSS_RU_SAE(ops ...operand.Op) { ctx.VSQRTSS_RU_SAE(ops...) } -// VPSLLVD: Variable Shift Packed Doubleword Data Left Logical. +// VSQRTSS_RU_SAE_Z: Compute Square Root of Scalar Single-Precision Floating-Point Value (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VPSLLVD xmm xmm xmm -// VPSLLVD m128 xmm xmm -// VPSLLVD ymm ymm ymm -// VPSLLVD m256 ymm ymm -// Construct and append a VPSLLVD instruction to the active function. -func (c *Context) VPSLLVD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPSLLVD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTSS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VSQRTSS.RU_SAE.Z instruction to the active function. +func (c *Context) VSQRTSS_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VSQRTSS_RU_SAE_Z(x, x1, k, x2)) } -// VPSLLVD: Variable Shift Packed Doubleword Data Left Logical. +// VSQRTSS_RU_SAE_Z: Compute Square Root of Scalar Single-Precision Floating-Point Value (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VPSLLVD xmm xmm xmm -// VPSLLVD m128 xmm xmm -// VPSLLVD ymm ymm ymm -// VPSLLVD m256 ymm ymm -// Construct and append a VPSLLVD instruction to the active function. +// VSQRTSS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VSQRTSS.RU_SAE.Z instruction to the active function. // Operates on the global context. -func VPSLLVD(mxy, xy, xy1 operand.Op) { ctx.VPSLLVD(mxy, xy, xy1) } +func VSQRTSS_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VSQRTSS_RU_SAE_Z(x, x1, k, x2) } -// VPSLLVQ: Variable Shift Packed Quadword Data Left Logical. +// VSQRTSS_RZ_SAE: Compute Square Root of Scalar Single-Precision Floating-Point Value (Round Towards Zero). // // Forms: // -// VPSLLVQ xmm xmm xmm -// VPSLLVQ m128 xmm xmm -// VPSLLVQ ymm ymm ymm -// VPSLLVQ m256 ymm ymm -// Construct and append a VPSLLVQ instruction to the active function. -func (c *Context) VPSLLVQ(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPSLLVQ(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTSS.RZ_SAE xmm xmm k xmm +// VSQRTSS.RZ_SAE xmm xmm xmm +// Construct and append a VSQRTSS.RZ_SAE instruction to the active function. +func (c *Context) VSQRTSS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSQRTSS_RZ_SAE(ops...)) } -// VPSLLVQ: Variable Shift Packed Quadword Data Left Logical. +// VSQRTSS_RZ_SAE: Compute Square Root of Scalar Single-Precision Floating-Point Value (Round Towards Zero). // // Forms: // -// VPSLLVQ xmm xmm xmm -// VPSLLVQ m128 xmm xmm -// VPSLLVQ ymm ymm ymm -// VPSLLVQ m256 ymm ymm -// Construct and append a VPSLLVQ instruction to the active function. +// VSQRTSS.RZ_SAE xmm xmm k xmm +// VSQRTSS.RZ_SAE xmm xmm xmm +// Construct and append a VSQRTSS.RZ_SAE instruction to the active function. // Operates on the global context. -func VPSLLVQ(mxy, xy, xy1 operand.Op) { ctx.VPSLLVQ(mxy, xy, xy1) } +func VSQRTSS_RZ_SAE(ops ...operand.Op) { ctx.VSQRTSS_RZ_SAE(ops...) } -// VPSLLW: Shift Packed Word Data Left Logical. +// VSQRTSS_RZ_SAE_Z: Compute Square Root of Scalar Single-Precision Floating-Point Value (Round Towards Zero, Zeroing Masking). // // Forms: // -// VPSLLW imm8 xmm xmm -// VPSLLW xmm xmm xmm -// VPSLLW m128 xmm xmm -// VPSLLW imm8 ymm ymm -// VPSLLW xmm ymm ymm -// VPSLLW m128 ymm ymm -// Construct and append a VPSLLW instruction to the active function. -func (c *Context) VPSLLW(imx, xy, xy1 operand.Op) { - if inst, err := x86.VPSLLW(imx, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTSS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VSQRTSS.RZ_SAE.Z instruction to the active function. +func (c *Context) VSQRTSS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VSQRTSS_RZ_SAE_Z(x, x1, k, x2)) } -// VPSLLW: Shift Packed Word Data Left Logical. +// VSQRTSS_RZ_SAE_Z: Compute Square Root of Scalar Single-Precision Floating-Point Value (Round Towards Zero, Zeroing Masking). // // Forms: // -// VPSLLW imm8 xmm xmm -// VPSLLW xmm xmm xmm -// VPSLLW m128 xmm xmm -// VPSLLW imm8 ymm ymm -// VPSLLW xmm ymm ymm -// VPSLLW m128 ymm ymm -// Construct and append a VPSLLW instruction to the active function. +// VSQRTSS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VSQRTSS.RZ_SAE.Z instruction to the active function. // Operates on the global context. -func VPSLLW(imx, xy, xy1 operand.Op) { ctx.VPSLLW(imx, xy, xy1) } +func VSQRTSS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VSQRTSS_RZ_SAE_Z(x, x1, k, x2) } -// VPSRAD: Shift Packed Doubleword Data Right Arithmetic. +// VSQRTSS_Z: Compute Square Root of Scalar Single-Precision Floating-Point Value (Zeroing Masking). // // Forms: // -// VPSRAD imm8 xmm xmm -// VPSRAD xmm xmm xmm -// VPSRAD m128 xmm xmm -// VPSRAD imm8 ymm ymm -// VPSRAD xmm ymm ymm -// VPSRAD m128 ymm ymm -// Construct and append a VPSRAD instruction to the active function. -func (c *Context) VPSRAD(imx, xy, xy1 operand.Op) { - if inst, err := x86.VPSRAD(imx, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSQRTSS.Z m32 xmm k xmm +// VSQRTSS.Z xmm xmm k xmm +// Construct and append a VSQRTSS.Z instruction to the active function. +func (c *Context) VSQRTSS_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VSQRTSS_Z(mx, x, k, x1)) } -// VPSRAD: Shift Packed Doubleword Data Right Arithmetic. +// VSQRTSS_Z: Compute Square Root of Scalar Single-Precision Floating-Point Value (Zeroing Masking). // // Forms: // -// VPSRAD imm8 xmm xmm -// VPSRAD xmm xmm xmm -// VPSRAD m128 xmm xmm -// VPSRAD imm8 ymm ymm -// VPSRAD xmm ymm ymm -// VPSRAD m128 ymm ymm -// Construct and append a VPSRAD instruction to the active function. +// VSQRTSS.Z m32 xmm k xmm +// VSQRTSS.Z xmm xmm k xmm +// Construct and append a VSQRTSS.Z instruction to the active function. // Operates on the global context. -func VPSRAD(imx, xy, xy1 operand.Op) { ctx.VPSRAD(imx, xy, xy1) } +func VSQRTSS_Z(mx, x, k, x1 operand.Op) { ctx.VSQRTSS_Z(mx, x, k, x1) } -// VPSRAVD: Variable Shift Packed Doubleword Data Right Arithmetic. +// VSTMXCSR: Store MXCSR Register State. // // Forms: // -// VPSRAVD xmm xmm xmm -// VPSRAVD m128 xmm xmm -// VPSRAVD ymm ymm ymm -// VPSRAVD m256 ymm ymm -// Construct and append a VPSRAVD instruction to the active function. -func (c *Context) VPSRAVD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPSRAVD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSTMXCSR m32 +// Construct and append a VSTMXCSR instruction to the active function. +func (c *Context) VSTMXCSR(m operand.Op) { + c.addinstruction(x86.VSTMXCSR(m)) } -// VPSRAVD: Variable Shift Packed Doubleword Data Right Arithmetic. +// VSTMXCSR: Store MXCSR Register State. // // Forms: // -// VPSRAVD xmm xmm xmm -// VPSRAVD m128 xmm xmm -// VPSRAVD ymm ymm ymm -// VPSRAVD m256 ymm ymm -// Construct and append a VPSRAVD instruction to the active function. +// VSTMXCSR m32 +// Construct and append a VSTMXCSR instruction to the active function. // Operates on the global context. -func VPSRAVD(mxy, xy, xy1 operand.Op) { ctx.VPSRAVD(mxy, xy, xy1) } +func VSTMXCSR(m operand.Op) { ctx.VSTMXCSR(m) } -// VPSRAW: Shift Packed Word Data Right Arithmetic. +// VSUBPD: Subtract Packed Double-Precision Floating-Point Values. // // Forms: // -// VPSRAW imm8 xmm xmm -// VPSRAW xmm xmm xmm -// VPSRAW m128 xmm xmm -// VPSRAW imm8 ymm ymm -// VPSRAW xmm ymm ymm -// VPSRAW m128 ymm ymm -// Construct and append a VPSRAW instruction to the active function. -func (c *Context) VPSRAW(imx, xy, xy1 operand.Op) { - if inst, err := x86.VPSRAW(imx, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBPD m128 xmm xmm +// VSUBPD m256 ymm ymm +// VSUBPD xmm xmm xmm +// VSUBPD ymm ymm ymm +// VSUBPD m128 xmm k xmm +// VSUBPD m256 ymm k ymm +// VSUBPD xmm xmm k xmm +// VSUBPD ymm ymm k ymm +// VSUBPD m512 zmm k zmm +// VSUBPD m512 zmm zmm +// VSUBPD zmm zmm k zmm +// VSUBPD zmm zmm zmm +// Construct and append a VSUBPD instruction to the active function. +func (c *Context) VSUBPD(ops ...operand.Op) { + c.addinstruction(x86.VSUBPD(ops...)) } -// VPSRAW: Shift Packed Word Data Right Arithmetic. +// VSUBPD: Subtract Packed Double-Precision Floating-Point Values. // // Forms: // -// VPSRAW imm8 xmm xmm -// VPSRAW xmm xmm xmm -// VPSRAW m128 xmm xmm -// VPSRAW imm8 ymm ymm -// VPSRAW xmm ymm ymm -// VPSRAW m128 ymm ymm -// Construct and append a VPSRAW instruction to the active function. +// VSUBPD m128 xmm xmm +// VSUBPD m256 ymm ymm +// VSUBPD xmm xmm xmm +// VSUBPD ymm ymm ymm +// VSUBPD m128 xmm k xmm +// VSUBPD m256 ymm k ymm +// VSUBPD xmm xmm k xmm +// VSUBPD ymm ymm k ymm +// VSUBPD m512 zmm k zmm +// VSUBPD m512 zmm zmm +// VSUBPD zmm zmm k zmm +// VSUBPD zmm zmm zmm +// Construct and append a VSUBPD instruction to the active function. // Operates on the global context. -func VPSRAW(imx, xy, xy1 operand.Op) { ctx.VPSRAW(imx, xy, xy1) } +func VSUBPD(ops ...operand.Op) { ctx.VSUBPD(ops...) } -// VPSRLD: Shift Packed Doubleword Data Right Logical. +// VSUBPD_BCST: Subtract Packed Double-Precision Floating-Point Values (Broadcast). // // Forms: // -// VPSRLD imm8 xmm xmm -// VPSRLD xmm xmm xmm -// VPSRLD m128 xmm xmm -// VPSRLD imm8 ymm ymm -// VPSRLD xmm ymm ymm -// VPSRLD m128 ymm ymm -// Construct and append a VPSRLD instruction to the active function. -func (c *Context) VPSRLD(imx, xy, xy1 operand.Op) { - if inst, err := x86.VPSRLD(imx, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBPD.BCST m64 xmm k xmm +// VSUBPD.BCST m64 xmm xmm +// VSUBPD.BCST m64 ymm k ymm +// VSUBPD.BCST m64 ymm ymm +// VSUBPD.BCST m64 zmm k zmm +// VSUBPD.BCST m64 zmm zmm +// Construct and append a VSUBPD.BCST instruction to the active function. +func (c *Context) VSUBPD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VSUBPD_BCST(ops...)) } -// VPSRLD: Shift Packed Doubleword Data Right Logical. +// VSUBPD_BCST: Subtract Packed Double-Precision Floating-Point Values (Broadcast). // // Forms: // -// VPSRLD imm8 xmm xmm -// VPSRLD xmm xmm xmm -// VPSRLD m128 xmm xmm -// VPSRLD imm8 ymm ymm -// VPSRLD xmm ymm ymm -// VPSRLD m128 ymm ymm -// Construct and append a VPSRLD instruction to the active function. +// VSUBPD.BCST m64 xmm k xmm +// VSUBPD.BCST m64 xmm xmm +// VSUBPD.BCST m64 ymm k ymm +// VSUBPD.BCST m64 ymm ymm +// VSUBPD.BCST m64 zmm k zmm +// VSUBPD.BCST m64 zmm zmm +// Construct and append a VSUBPD.BCST instruction to the active function. // Operates on the global context. -func VPSRLD(imx, xy, xy1 operand.Op) { ctx.VPSRLD(imx, xy, xy1) } +func VSUBPD_BCST(ops ...operand.Op) { ctx.VSUBPD_BCST(ops...) } -// VPSRLDQ: Shift Packed Double Quadword Right Logical. +// VSUBPD_BCST_Z: Subtract Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VPSRLDQ imm8 xmm xmm -// VPSRLDQ imm8 ymm ymm -// Construct and append a VPSRLDQ instruction to the active function. -func (c *Context) VPSRLDQ(i, xy, xy1 operand.Op) { - if inst, err := x86.VPSRLDQ(i, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBPD.BCST.Z m64 xmm k xmm +// VSUBPD.BCST.Z m64 ymm k ymm +// VSUBPD.BCST.Z m64 zmm k zmm +// Construct and append a VSUBPD.BCST.Z instruction to the active function. +func (c *Context) VSUBPD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VSUBPD_BCST_Z(m, xyz, k, xyz1)) } -// VPSRLDQ: Shift Packed Double Quadword Right Logical. +// VSUBPD_BCST_Z: Subtract Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VPSRLDQ imm8 xmm xmm -// VPSRLDQ imm8 ymm ymm -// Construct and append a VPSRLDQ instruction to the active function. +// VSUBPD.BCST.Z m64 xmm k xmm +// VSUBPD.BCST.Z m64 ymm k ymm +// VSUBPD.BCST.Z m64 zmm k zmm +// Construct and append a VSUBPD.BCST.Z instruction to the active function. // Operates on the global context. -func VPSRLDQ(i, xy, xy1 operand.Op) { ctx.VPSRLDQ(i, xy, xy1) } +func VSUBPD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VSUBPD_BCST_Z(m, xyz, k, xyz1) } -// VPSRLQ: Shift Packed Quadword Data Right Logical. +// VSUBPD_RD_SAE: Subtract Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). // // Forms: // -// VPSRLQ imm8 xmm xmm -// VPSRLQ xmm xmm xmm -// VPSRLQ m128 xmm xmm -// VPSRLQ imm8 ymm ymm -// VPSRLQ xmm ymm ymm -// VPSRLQ m128 ymm ymm -// Construct and append a VPSRLQ instruction to the active function. -func (c *Context) VPSRLQ(imx, xy, xy1 operand.Op) { - if inst, err := x86.VPSRLQ(imx, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBPD.RD_SAE zmm zmm k zmm +// VSUBPD.RD_SAE zmm zmm zmm +// Construct and append a VSUBPD.RD_SAE instruction to the active function. +func (c *Context) VSUBPD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSUBPD_RD_SAE(ops...)) } -// VPSRLQ: Shift Packed Quadword Data Right Logical. +// VSUBPD_RD_SAE: Subtract Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). // // Forms: // -// VPSRLQ imm8 xmm xmm -// VPSRLQ xmm xmm xmm -// VPSRLQ m128 xmm xmm -// VPSRLQ imm8 ymm ymm -// VPSRLQ xmm ymm ymm -// VPSRLQ m128 ymm ymm -// Construct and append a VPSRLQ instruction to the active function. +// VSUBPD.RD_SAE zmm zmm k zmm +// VSUBPD.RD_SAE zmm zmm zmm +// Construct and append a VSUBPD.RD_SAE instruction to the active function. // Operates on the global context. -func VPSRLQ(imx, xy, xy1 operand.Op) { ctx.VPSRLQ(imx, xy, xy1) } +func VSUBPD_RD_SAE(ops ...operand.Op) { ctx.VSUBPD_RD_SAE(ops...) } -// VPSRLVD: Variable Shift Packed Doubleword Data Right Logical. +// VSUBPD_RD_SAE_Z: Subtract Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VPSRLVD xmm xmm xmm -// VPSRLVD m128 xmm xmm -// VPSRLVD ymm ymm ymm -// VPSRLVD m256 ymm ymm -// Construct and append a VPSRLVD instruction to the active function. -func (c *Context) VPSRLVD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPSRLVD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBPD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VSUBPD.RD_SAE.Z instruction to the active function. +func (c *Context) VSUBPD_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VSUBPD_RD_SAE_Z(z, z1, k, z2)) } -// VPSRLVD: Variable Shift Packed Doubleword Data Right Logical. +// VSUBPD_RD_SAE_Z: Subtract Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VPSRLVD xmm xmm xmm -// VPSRLVD m128 xmm xmm -// VPSRLVD ymm ymm ymm -// VPSRLVD m256 ymm ymm -// Construct and append a VPSRLVD instruction to the active function. +// VSUBPD.RD_SAE.Z zmm zmm k zmm +// Construct and append a VSUBPD.RD_SAE.Z instruction to the active function. // Operates on the global context. -func VPSRLVD(mxy, xy, xy1 operand.Op) { ctx.VPSRLVD(mxy, xy, xy1) } +func VSUBPD_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VSUBPD_RD_SAE_Z(z, z1, k, z2) } -// VPSRLVQ: Variable Shift Packed Quadword Data Right Logical. +// VSUBPD_RN_SAE: Subtract Packed Double-Precision Floating-Point Values (Round Towards Nearest). // // Forms: // -// VPSRLVQ xmm xmm xmm -// VPSRLVQ m128 xmm xmm -// VPSRLVQ ymm ymm ymm -// VPSRLVQ m256 ymm ymm -// Construct and append a VPSRLVQ instruction to the active function. -func (c *Context) VPSRLVQ(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPSRLVQ(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBPD.RN_SAE zmm zmm k zmm +// VSUBPD.RN_SAE zmm zmm zmm +// Construct and append a VSUBPD.RN_SAE instruction to the active function. +func (c *Context) VSUBPD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSUBPD_RN_SAE(ops...)) } -// VPSRLVQ: Variable Shift Packed Quadword Data Right Logical. +// VSUBPD_RN_SAE: Subtract Packed Double-Precision Floating-Point Values (Round Towards Nearest). // // Forms: // -// VPSRLVQ xmm xmm xmm -// VPSRLVQ m128 xmm xmm -// VPSRLVQ ymm ymm ymm -// VPSRLVQ m256 ymm ymm -// Construct and append a VPSRLVQ instruction to the active function. +// VSUBPD.RN_SAE zmm zmm k zmm +// VSUBPD.RN_SAE zmm zmm zmm +// Construct and append a VSUBPD.RN_SAE instruction to the active function. // Operates on the global context. -func VPSRLVQ(mxy, xy, xy1 operand.Op) { ctx.VPSRLVQ(mxy, xy, xy1) } +func VSUBPD_RN_SAE(ops ...operand.Op) { ctx.VSUBPD_RN_SAE(ops...) } -// VPSRLW: Shift Packed Word Data Right Logical. +// VSUBPD_RN_SAE_Z: Subtract Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VPSRLW imm8 xmm xmm -// VPSRLW xmm xmm xmm -// VPSRLW m128 xmm xmm -// VPSRLW imm8 ymm ymm -// VPSRLW xmm ymm ymm -// VPSRLW m128 ymm ymm -// Construct and append a VPSRLW instruction to the active function. -func (c *Context) VPSRLW(imx, xy, xy1 operand.Op) { - if inst, err := x86.VPSRLW(imx, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBPD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VSUBPD.RN_SAE.Z instruction to the active function. +func (c *Context) VSUBPD_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VSUBPD_RN_SAE_Z(z, z1, k, z2)) } -// VPSRLW: Shift Packed Word Data Right Logical. +// VSUBPD_RN_SAE_Z: Subtract Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VPSRLW imm8 xmm xmm -// VPSRLW xmm xmm xmm -// VPSRLW m128 xmm xmm -// VPSRLW imm8 ymm ymm -// VPSRLW xmm ymm ymm -// VPSRLW m128 ymm ymm -// Construct and append a VPSRLW instruction to the active function. +// VSUBPD.RN_SAE.Z zmm zmm k zmm +// Construct and append a VSUBPD.RN_SAE.Z instruction to the active function. // Operates on the global context. -func VPSRLW(imx, xy, xy1 operand.Op) { ctx.VPSRLW(imx, xy, xy1) } +func VSUBPD_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VSUBPD_RN_SAE_Z(z, z1, k, z2) } -// VPSUBB: Subtract Packed Byte Integers. +// VSUBPD_RU_SAE: Subtract Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). // // Forms: // -// VPSUBB xmm xmm xmm -// VPSUBB m128 xmm xmm -// VPSUBB ymm ymm ymm -// VPSUBB m256 ymm ymm -// Construct and append a VPSUBB instruction to the active function. -func (c *Context) VPSUBB(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPSUBB(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBPD.RU_SAE zmm zmm k zmm +// VSUBPD.RU_SAE zmm zmm zmm +// Construct and append a VSUBPD.RU_SAE instruction to the active function. +func (c *Context) VSUBPD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSUBPD_RU_SAE(ops...)) } -// VPSUBB: Subtract Packed Byte Integers. -// -// Forms: +// VSUBPD_RU_SAE: Subtract Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). // -// VPSUBB xmm xmm xmm -// VPSUBB m128 xmm xmm -// VPSUBB ymm ymm ymm -// VPSUBB m256 ymm ymm -// Construct and append a VPSUBB instruction to the active function. +// Forms: +// +// VSUBPD.RU_SAE zmm zmm k zmm +// VSUBPD.RU_SAE zmm zmm zmm +// Construct and append a VSUBPD.RU_SAE instruction to the active function. // Operates on the global context. -func VPSUBB(mxy, xy, xy1 operand.Op) { ctx.VPSUBB(mxy, xy, xy1) } +func VSUBPD_RU_SAE(ops ...operand.Op) { ctx.VSUBPD_RU_SAE(ops...) } -// VPSUBD: Subtract Packed Doubleword Integers. +// VSUBPD_RU_SAE_Z: Subtract Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VPSUBD xmm xmm xmm -// VPSUBD m128 xmm xmm -// VPSUBD ymm ymm ymm -// VPSUBD m256 ymm ymm -// Construct and append a VPSUBD instruction to the active function. -func (c *Context) VPSUBD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPSUBD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBPD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VSUBPD.RU_SAE.Z instruction to the active function. +func (c *Context) VSUBPD_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VSUBPD_RU_SAE_Z(z, z1, k, z2)) } -// VPSUBD: Subtract Packed Doubleword Integers. +// VSUBPD_RU_SAE_Z: Subtract Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VPSUBD xmm xmm xmm -// VPSUBD m128 xmm xmm -// VPSUBD ymm ymm ymm -// VPSUBD m256 ymm ymm -// Construct and append a VPSUBD instruction to the active function. +// VSUBPD.RU_SAE.Z zmm zmm k zmm +// Construct and append a VSUBPD.RU_SAE.Z instruction to the active function. // Operates on the global context. -func VPSUBD(mxy, xy, xy1 operand.Op) { ctx.VPSUBD(mxy, xy, xy1) } +func VSUBPD_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VSUBPD_RU_SAE_Z(z, z1, k, z2) } -// VPSUBQ: Subtract Packed Quadword Integers. +// VSUBPD_RZ_SAE: Subtract Packed Double-Precision Floating-Point Values (Round Towards Zero). // // Forms: // -// VPSUBQ xmm xmm xmm -// VPSUBQ m128 xmm xmm -// VPSUBQ ymm ymm ymm -// VPSUBQ m256 ymm ymm -// Construct and append a VPSUBQ instruction to the active function. -func (c *Context) VPSUBQ(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPSUBQ(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBPD.RZ_SAE zmm zmm k zmm +// VSUBPD.RZ_SAE zmm zmm zmm +// Construct and append a VSUBPD.RZ_SAE instruction to the active function. +func (c *Context) VSUBPD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSUBPD_RZ_SAE(ops...)) } -// VPSUBQ: Subtract Packed Quadword Integers. +// VSUBPD_RZ_SAE: Subtract Packed Double-Precision Floating-Point Values (Round Towards Zero). // // Forms: // -// VPSUBQ xmm xmm xmm -// VPSUBQ m128 xmm xmm -// VPSUBQ ymm ymm ymm -// VPSUBQ m256 ymm ymm -// Construct and append a VPSUBQ instruction to the active function. +// VSUBPD.RZ_SAE zmm zmm k zmm +// VSUBPD.RZ_SAE zmm zmm zmm +// Construct and append a VSUBPD.RZ_SAE instruction to the active function. // Operates on the global context. -func VPSUBQ(mxy, xy, xy1 operand.Op) { ctx.VPSUBQ(mxy, xy, xy1) } +func VSUBPD_RZ_SAE(ops ...operand.Op) { ctx.VSUBPD_RZ_SAE(ops...) } -// VPSUBSB: Subtract Packed Signed Byte Integers with Signed Saturation. +// VSUBPD_RZ_SAE_Z: Subtract Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). // // Forms: // -// VPSUBSB xmm xmm xmm -// VPSUBSB m128 xmm xmm -// VPSUBSB ymm ymm ymm -// VPSUBSB m256 ymm ymm -// Construct and append a VPSUBSB instruction to the active function. -func (c *Context) VPSUBSB(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPSUBSB(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBPD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VSUBPD.RZ_SAE.Z instruction to the active function. +func (c *Context) VSUBPD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VSUBPD_RZ_SAE_Z(z, z1, k, z2)) } -// VPSUBSB: Subtract Packed Signed Byte Integers with Signed Saturation. +// VSUBPD_RZ_SAE_Z: Subtract Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). // // Forms: // -// VPSUBSB xmm xmm xmm -// VPSUBSB m128 xmm xmm -// VPSUBSB ymm ymm ymm -// VPSUBSB m256 ymm ymm -// Construct and append a VPSUBSB instruction to the active function. +// VSUBPD.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VSUBPD.RZ_SAE.Z instruction to the active function. // Operates on the global context. -func VPSUBSB(mxy, xy, xy1 operand.Op) { ctx.VPSUBSB(mxy, xy, xy1) } +func VSUBPD_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VSUBPD_RZ_SAE_Z(z, z1, k, z2) } -// VPSUBSW: Subtract Packed Signed Word Integers with Signed Saturation. +// VSUBPD_Z: Subtract Packed Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VPSUBSW xmm xmm xmm -// VPSUBSW m128 xmm xmm -// VPSUBSW ymm ymm ymm -// VPSUBSW m256 ymm ymm -// Construct and append a VPSUBSW instruction to the active function. -func (c *Context) VPSUBSW(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPSUBSW(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBPD.Z m128 xmm k xmm +// VSUBPD.Z m256 ymm k ymm +// VSUBPD.Z xmm xmm k xmm +// VSUBPD.Z ymm ymm k ymm +// VSUBPD.Z m512 zmm k zmm +// VSUBPD.Z zmm zmm k zmm +// Construct and append a VSUBPD.Z instruction to the active function. +func (c *Context) VSUBPD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VSUBPD_Z(mxyz, xyz, k, xyz1)) } -// VPSUBSW: Subtract Packed Signed Word Integers with Signed Saturation. +// VSUBPD_Z: Subtract Packed Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VPSUBSW xmm xmm xmm -// VPSUBSW m128 xmm xmm -// VPSUBSW ymm ymm ymm -// VPSUBSW m256 ymm ymm -// Construct and append a VPSUBSW instruction to the active function. +// VSUBPD.Z m128 xmm k xmm +// VSUBPD.Z m256 ymm k ymm +// VSUBPD.Z xmm xmm k xmm +// VSUBPD.Z ymm ymm k ymm +// VSUBPD.Z m512 zmm k zmm +// VSUBPD.Z zmm zmm k zmm +// Construct and append a VSUBPD.Z instruction to the active function. // Operates on the global context. -func VPSUBSW(mxy, xy, xy1 operand.Op) { ctx.VPSUBSW(mxy, xy, xy1) } +func VSUBPD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VSUBPD_Z(mxyz, xyz, k, xyz1) } -// VPSUBUSB: Subtract Packed Unsigned Byte Integers with Unsigned Saturation. +// VSUBPS: Subtract Packed Single-Precision Floating-Point Values. // // Forms: // -// VPSUBUSB xmm xmm xmm -// VPSUBUSB m128 xmm xmm -// VPSUBUSB ymm ymm ymm -// VPSUBUSB m256 ymm ymm -// Construct and append a VPSUBUSB instruction to the active function. -func (c *Context) VPSUBUSB(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPSUBUSB(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBPS m128 xmm xmm +// VSUBPS m256 ymm ymm +// VSUBPS xmm xmm xmm +// VSUBPS ymm ymm ymm +// VSUBPS m128 xmm k xmm +// VSUBPS m256 ymm k ymm +// VSUBPS xmm xmm k xmm +// VSUBPS ymm ymm k ymm +// VSUBPS m512 zmm k zmm +// VSUBPS m512 zmm zmm +// VSUBPS zmm zmm k zmm +// VSUBPS zmm zmm zmm +// Construct and append a VSUBPS instruction to the active function. +func (c *Context) VSUBPS(ops ...operand.Op) { + c.addinstruction(x86.VSUBPS(ops...)) } -// VPSUBUSB: Subtract Packed Unsigned Byte Integers with Unsigned Saturation. +// VSUBPS: Subtract Packed Single-Precision Floating-Point Values. // // Forms: // -// VPSUBUSB xmm xmm xmm -// VPSUBUSB m128 xmm xmm -// VPSUBUSB ymm ymm ymm -// VPSUBUSB m256 ymm ymm -// Construct and append a VPSUBUSB instruction to the active function. +// VSUBPS m128 xmm xmm +// VSUBPS m256 ymm ymm +// VSUBPS xmm xmm xmm +// VSUBPS ymm ymm ymm +// VSUBPS m128 xmm k xmm +// VSUBPS m256 ymm k ymm +// VSUBPS xmm xmm k xmm +// VSUBPS ymm ymm k ymm +// VSUBPS m512 zmm k zmm +// VSUBPS m512 zmm zmm +// VSUBPS zmm zmm k zmm +// VSUBPS zmm zmm zmm +// Construct and append a VSUBPS instruction to the active function. // Operates on the global context. -func VPSUBUSB(mxy, xy, xy1 operand.Op) { ctx.VPSUBUSB(mxy, xy, xy1) } +func VSUBPS(ops ...operand.Op) { ctx.VSUBPS(ops...) } -// VPSUBUSW: Subtract Packed Unsigned Word Integers with Unsigned Saturation. +// VSUBPS_BCST: Subtract Packed Single-Precision Floating-Point Values (Broadcast). // // Forms: // -// VPSUBUSW xmm xmm xmm -// VPSUBUSW m128 xmm xmm -// VPSUBUSW ymm ymm ymm -// VPSUBUSW m256 ymm ymm -// Construct and append a VPSUBUSW instruction to the active function. -func (c *Context) VPSUBUSW(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPSUBUSW(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBPS.BCST m32 xmm k xmm +// VSUBPS.BCST m32 xmm xmm +// VSUBPS.BCST m32 ymm k ymm +// VSUBPS.BCST m32 ymm ymm +// VSUBPS.BCST m32 zmm k zmm +// VSUBPS.BCST m32 zmm zmm +// Construct and append a VSUBPS.BCST instruction to the active function. +func (c *Context) VSUBPS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VSUBPS_BCST(ops...)) } -// VPSUBUSW: Subtract Packed Unsigned Word Integers with Unsigned Saturation. +// VSUBPS_BCST: Subtract Packed Single-Precision Floating-Point Values (Broadcast). // // Forms: // -// VPSUBUSW xmm xmm xmm -// VPSUBUSW m128 xmm xmm -// VPSUBUSW ymm ymm ymm -// VPSUBUSW m256 ymm ymm -// Construct and append a VPSUBUSW instruction to the active function. +// VSUBPS.BCST m32 xmm k xmm +// VSUBPS.BCST m32 xmm xmm +// VSUBPS.BCST m32 ymm k ymm +// VSUBPS.BCST m32 ymm ymm +// VSUBPS.BCST m32 zmm k zmm +// VSUBPS.BCST m32 zmm zmm +// Construct and append a VSUBPS.BCST instruction to the active function. // Operates on the global context. -func VPSUBUSW(mxy, xy, xy1 operand.Op) { ctx.VPSUBUSW(mxy, xy, xy1) } +func VSUBPS_BCST(ops ...operand.Op) { ctx.VSUBPS_BCST(ops...) } -// VPSUBW: Subtract Packed Word Integers. +// VSUBPS_BCST_Z: Subtract Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VPSUBW xmm xmm xmm -// VPSUBW m128 xmm xmm -// VPSUBW ymm ymm ymm -// VPSUBW m256 ymm ymm -// Construct and append a VPSUBW instruction to the active function. -func (c *Context) VPSUBW(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPSUBW(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBPS.BCST.Z m32 xmm k xmm +// VSUBPS.BCST.Z m32 ymm k ymm +// VSUBPS.BCST.Z m32 zmm k zmm +// Construct and append a VSUBPS.BCST.Z instruction to the active function. +func (c *Context) VSUBPS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VSUBPS_BCST_Z(m, xyz, k, xyz1)) } -// VPSUBW: Subtract Packed Word Integers. +// VSUBPS_BCST_Z: Subtract Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VPSUBW xmm xmm xmm -// VPSUBW m128 xmm xmm -// VPSUBW ymm ymm ymm -// VPSUBW m256 ymm ymm -// Construct and append a VPSUBW instruction to the active function. +// VSUBPS.BCST.Z m32 xmm k xmm +// VSUBPS.BCST.Z m32 ymm k ymm +// VSUBPS.BCST.Z m32 zmm k zmm +// Construct and append a VSUBPS.BCST.Z instruction to the active function. // Operates on the global context. -func VPSUBW(mxy, xy, xy1 operand.Op) { ctx.VPSUBW(mxy, xy, xy1) } +func VSUBPS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VSUBPS_BCST_Z(m, xyz, k, xyz1) } -// VPTEST: Packed Logical Compare. +// VSUBPS_RD_SAE: Subtract Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). // // Forms: // -// VPTEST xmm xmm -// VPTEST m128 xmm -// VPTEST ymm ymm -// VPTEST m256 ymm -// Construct and append a VPTEST instruction to the active function. -func (c *Context) VPTEST(mxy, xy operand.Op) { - if inst, err := x86.VPTEST(mxy, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBPS.RD_SAE zmm zmm k zmm +// VSUBPS.RD_SAE zmm zmm zmm +// Construct and append a VSUBPS.RD_SAE instruction to the active function. +func (c *Context) VSUBPS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSUBPS_RD_SAE(ops...)) } -// VPTEST: Packed Logical Compare. +// VSUBPS_RD_SAE: Subtract Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). // // Forms: // -// VPTEST xmm xmm -// VPTEST m128 xmm -// VPTEST ymm ymm -// VPTEST m256 ymm -// Construct and append a VPTEST instruction to the active function. +// VSUBPS.RD_SAE zmm zmm k zmm +// VSUBPS.RD_SAE zmm zmm zmm +// Construct and append a VSUBPS.RD_SAE instruction to the active function. // Operates on the global context. -func VPTEST(mxy, xy operand.Op) { ctx.VPTEST(mxy, xy) } +func VSUBPS_RD_SAE(ops ...operand.Op) { ctx.VSUBPS_RD_SAE(ops...) } -// VPUNPCKHBW: Unpack and Interleave High-Order Bytes into Words. +// VSUBPS_RD_SAE_Z: Subtract Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VPUNPCKHBW xmm xmm xmm -// VPUNPCKHBW m128 xmm xmm -// VPUNPCKHBW ymm ymm ymm -// VPUNPCKHBW m256 ymm ymm -// Construct and append a VPUNPCKHBW instruction to the active function. -func (c *Context) VPUNPCKHBW(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPUNPCKHBW(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBPS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VSUBPS.RD_SAE.Z instruction to the active function. +func (c *Context) VSUBPS_RD_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VSUBPS_RD_SAE_Z(z, z1, k, z2)) } -// VPUNPCKHBW: Unpack and Interleave High-Order Bytes into Words. +// VSUBPS_RD_SAE_Z: Subtract Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VPUNPCKHBW xmm xmm xmm -// VPUNPCKHBW m128 xmm xmm -// VPUNPCKHBW ymm ymm ymm -// VPUNPCKHBW m256 ymm ymm -// Construct and append a VPUNPCKHBW instruction to the active function. +// VSUBPS.RD_SAE.Z zmm zmm k zmm +// Construct and append a VSUBPS.RD_SAE.Z instruction to the active function. // Operates on the global context. -func VPUNPCKHBW(mxy, xy, xy1 operand.Op) { ctx.VPUNPCKHBW(mxy, xy, xy1) } +func VSUBPS_RD_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VSUBPS_RD_SAE_Z(z, z1, k, z2) } -// VPUNPCKHDQ: Unpack and Interleave High-Order Doublewords into Quadwords. +// VSUBPS_RN_SAE: Subtract Packed Single-Precision Floating-Point Values (Round Towards Nearest). // // Forms: // -// VPUNPCKHDQ xmm xmm xmm -// VPUNPCKHDQ m128 xmm xmm -// VPUNPCKHDQ ymm ymm ymm -// VPUNPCKHDQ m256 ymm ymm -// Construct and append a VPUNPCKHDQ instruction to the active function. -func (c *Context) VPUNPCKHDQ(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPUNPCKHDQ(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBPS.RN_SAE zmm zmm k zmm +// VSUBPS.RN_SAE zmm zmm zmm +// Construct and append a VSUBPS.RN_SAE instruction to the active function. +func (c *Context) VSUBPS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSUBPS_RN_SAE(ops...)) } -// VPUNPCKHDQ: Unpack and Interleave High-Order Doublewords into Quadwords. +// VSUBPS_RN_SAE: Subtract Packed Single-Precision Floating-Point Values (Round Towards Nearest). // // Forms: // -// VPUNPCKHDQ xmm xmm xmm -// VPUNPCKHDQ m128 xmm xmm -// VPUNPCKHDQ ymm ymm ymm -// VPUNPCKHDQ m256 ymm ymm -// Construct and append a VPUNPCKHDQ instruction to the active function. +// VSUBPS.RN_SAE zmm zmm k zmm +// VSUBPS.RN_SAE zmm zmm zmm +// Construct and append a VSUBPS.RN_SAE instruction to the active function. // Operates on the global context. -func VPUNPCKHDQ(mxy, xy, xy1 operand.Op) { ctx.VPUNPCKHDQ(mxy, xy, xy1) } +func VSUBPS_RN_SAE(ops ...operand.Op) { ctx.VSUBPS_RN_SAE(ops...) } -// VPUNPCKHQDQ: Unpack and Interleave High-Order Quadwords into Double Quadwords. +// VSUBPS_RN_SAE_Z: Subtract Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VPUNPCKHQDQ xmm xmm xmm -// VPUNPCKHQDQ m128 xmm xmm -// VPUNPCKHQDQ ymm ymm ymm -// VPUNPCKHQDQ m256 ymm ymm -// Construct and append a VPUNPCKHQDQ instruction to the active function. -func (c *Context) VPUNPCKHQDQ(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPUNPCKHQDQ(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBPS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VSUBPS.RN_SAE.Z instruction to the active function. +func (c *Context) VSUBPS_RN_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VSUBPS_RN_SAE_Z(z, z1, k, z2)) } -// VPUNPCKHQDQ: Unpack and Interleave High-Order Quadwords into Double Quadwords. +// VSUBPS_RN_SAE_Z: Subtract Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VPUNPCKHQDQ xmm xmm xmm -// VPUNPCKHQDQ m128 xmm xmm -// VPUNPCKHQDQ ymm ymm ymm -// VPUNPCKHQDQ m256 ymm ymm -// Construct and append a VPUNPCKHQDQ instruction to the active function. +// VSUBPS.RN_SAE.Z zmm zmm k zmm +// Construct and append a VSUBPS.RN_SAE.Z instruction to the active function. // Operates on the global context. -func VPUNPCKHQDQ(mxy, xy, xy1 operand.Op) { ctx.VPUNPCKHQDQ(mxy, xy, xy1) } +func VSUBPS_RN_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VSUBPS_RN_SAE_Z(z, z1, k, z2) } -// VPUNPCKHWD: Unpack and Interleave High-Order Words into Doublewords. +// VSUBPS_RU_SAE: Subtract Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). // // Forms: // -// VPUNPCKHWD xmm xmm xmm -// VPUNPCKHWD m128 xmm xmm -// VPUNPCKHWD ymm ymm ymm -// VPUNPCKHWD m256 ymm ymm -// Construct and append a VPUNPCKHWD instruction to the active function. -func (c *Context) VPUNPCKHWD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPUNPCKHWD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBPS.RU_SAE zmm zmm k zmm +// VSUBPS.RU_SAE zmm zmm zmm +// Construct and append a VSUBPS.RU_SAE instruction to the active function. +func (c *Context) VSUBPS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSUBPS_RU_SAE(ops...)) } -// VPUNPCKHWD: Unpack and Interleave High-Order Words into Doublewords. +// VSUBPS_RU_SAE: Subtract Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). // // Forms: // -// VPUNPCKHWD xmm xmm xmm -// VPUNPCKHWD m128 xmm xmm -// VPUNPCKHWD ymm ymm ymm -// VPUNPCKHWD m256 ymm ymm -// Construct and append a VPUNPCKHWD instruction to the active function. +// VSUBPS.RU_SAE zmm zmm k zmm +// VSUBPS.RU_SAE zmm zmm zmm +// Construct and append a VSUBPS.RU_SAE instruction to the active function. // Operates on the global context. -func VPUNPCKHWD(mxy, xy, xy1 operand.Op) { ctx.VPUNPCKHWD(mxy, xy, xy1) } +func VSUBPS_RU_SAE(ops ...operand.Op) { ctx.VSUBPS_RU_SAE(ops...) } -// VPUNPCKLBW: Unpack and Interleave Low-Order Bytes into Words. +// VSUBPS_RU_SAE_Z: Subtract Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VPUNPCKLBW xmm xmm xmm -// VPUNPCKLBW m128 xmm xmm -// VPUNPCKLBW ymm ymm ymm -// VPUNPCKLBW m256 ymm ymm -// Construct and append a VPUNPCKLBW instruction to the active function. -func (c *Context) VPUNPCKLBW(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPUNPCKLBW(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBPS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VSUBPS.RU_SAE.Z instruction to the active function. +func (c *Context) VSUBPS_RU_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VSUBPS_RU_SAE_Z(z, z1, k, z2)) } -// VPUNPCKLBW: Unpack and Interleave Low-Order Bytes into Words. +// VSUBPS_RU_SAE_Z: Subtract Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VPUNPCKLBW xmm xmm xmm -// VPUNPCKLBW m128 xmm xmm -// VPUNPCKLBW ymm ymm ymm -// VPUNPCKLBW m256 ymm ymm -// Construct and append a VPUNPCKLBW instruction to the active function. +// VSUBPS.RU_SAE.Z zmm zmm k zmm +// Construct and append a VSUBPS.RU_SAE.Z instruction to the active function. // Operates on the global context. -func VPUNPCKLBW(mxy, xy, xy1 operand.Op) { ctx.VPUNPCKLBW(mxy, xy, xy1) } +func VSUBPS_RU_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VSUBPS_RU_SAE_Z(z, z1, k, z2) } -// VPUNPCKLDQ: Unpack and Interleave Low-Order Doublewords into Quadwords. +// VSUBPS_RZ_SAE: Subtract Packed Single-Precision Floating-Point Values (Round Towards Zero). // // Forms: // -// VPUNPCKLDQ xmm xmm xmm -// VPUNPCKLDQ m128 xmm xmm -// VPUNPCKLDQ ymm ymm ymm -// VPUNPCKLDQ m256 ymm ymm -// Construct and append a VPUNPCKLDQ instruction to the active function. -func (c *Context) VPUNPCKLDQ(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPUNPCKLDQ(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBPS.RZ_SAE zmm zmm k zmm +// VSUBPS.RZ_SAE zmm zmm zmm +// Construct and append a VSUBPS.RZ_SAE instruction to the active function. +func (c *Context) VSUBPS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSUBPS_RZ_SAE(ops...)) } -// VPUNPCKLDQ: Unpack and Interleave Low-Order Doublewords into Quadwords. +// VSUBPS_RZ_SAE: Subtract Packed Single-Precision Floating-Point Values (Round Towards Zero). // // Forms: // -// VPUNPCKLDQ xmm xmm xmm -// VPUNPCKLDQ m128 xmm xmm -// VPUNPCKLDQ ymm ymm ymm -// VPUNPCKLDQ m256 ymm ymm -// Construct and append a VPUNPCKLDQ instruction to the active function. +// VSUBPS.RZ_SAE zmm zmm k zmm +// VSUBPS.RZ_SAE zmm zmm zmm +// Construct and append a VSUBPS.RZ_SAE instruction to the active function. // Operates on the global context. -func VPUNPCKLDQ(mxy, xy, xy1 operand.Op) { ctx.VPUNPCKLDQ(mxy, xy, xy1) } +func VSUBPS_RZ_SAE(ops ...operand.Op) { ctx.VSUBPS_RZ_SAE(ops...) } -// VPUNPCKLQDQ: Unpack and Interleave Low-Order Quadwords into Double Quadwords. +// VSUBPS_RZ_SAE_Z: Subtract Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). // // Forms: // -// VPUNPCKLQDQ xmm xmm xmm -// VPUNPCKLQDQ m128 xmm xmm -// VPUNPCKLQDQ ymm ymm ymm -// VPUNPCKLQDQ m256 ymm ymm -// Construct and append a VPUNPCKLQDQ instruction to the active function. -func (c *Context) VPUNPCKLQDQ(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPUNPCKLQDQ(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBPS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VSUBPS.RZ_SAE.Z instruction to the active function. +func (c *Context) VSUBPS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { + c.addinstruction(x86.VSUBPS_RZ_SAE_Z(z, z1, k, z2)) } -// VPUNPCKLQDQ: Unpack and Interleave Low-Order Quadwords into Double Quadwords. +// VSUBPS_RZ_SAE_Z: Subtract Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). // // Forms: // -// VPUNPCKLQDQ xmm xmm xmm -// VPUNPCKLQDQ m128 xmm xmm -// VPUNPCKLQDQ ymm ymm ymm -// VPUNPCKLQDQ m256 ymm ymm -// Construct and append a VPUNPCKLQDQ instruction to the active function. +// VSUBPS.RZ_SAE.Z zmm zmm k zmm +// Construct and append a VSUBPS.RZ_SAE.Z instruction to the active function. // Operates on the global context. -func VPUNPCKLQDQ(mxy, xy, xy1 operand.Op) { ctx.VPUNPCKLQDQ(mxy, xy, xy1) } +func VSUBPS_RZ_SAE_Z(z, z1, k, z2 operand.Op) { ctx.VSUBPS_RZ_SAE_Z(z, z1, k, z2) } -// VPUNPCKLWD: Unpack and Interleave Low-Order Words into Doublewords. +// VSUBPS_Z: Subtract Packed Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VPUNPCKLWD xmm xmm xmm -// VPUNPCKLWD m128 xmm xmm -// VPUNPCKLWD ymm ymm ymm -// VPUNPCKLWD m256 ymm ymm -// Construct and append a VPUNPCKLWD instruction to the active function. -func (c *Context) VPUNPCKLWD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPUNPCKLWD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBPS.Z m128 xmm k xmm +// VSUBPS.Z m256 ymm k ymm +// VSUBPS.Z xmm xmm k xmm +// VSUBPS.Z ymm ymm k ymm +// VSUBPS.Z m512 zmm k zmm +// VSUBPS.Z zmm zmm k zmm +// Construct and append a VSUBPS.Z instruction to the active function. +func (c *Context) VSUBPS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VSUBPS_Z(mxyz, xyz, k, xyz1)) } -// VPUNPCKLWD: Unpack and Interleave Low-Order Words into Doublewords. +// VSUBPS_Z: Subtract Packed Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VPUNPCKLWD xmm xmm xmm -// VPUNPCKLWD m128 xmm xmm -// VPUNPCKLWD ymm ymm ymm -// VPUNPCKLWD m256 ymm ymm -// Construct and append a VPUNPCKLWD instruction to the active function. +// VSUBPS.Z m128 xmm k xmm +// VSUBPS.Z m256 ymm k ymm +// VSUBPS.Z xmm xmm k xmm +// VSUBPS.Z ymm ymm k ymm +// VSUBPS.Z m512 zmm k zmm +// VSUBPS.Z zmm zmm k zmm +// Construct and append a VSUBPS.Z instruction to the active function. // Operates on the global context. -func VPUNPCKLWD(mxy, xy, xy1 operand.Op) { ctx.VPUNPCKLWD(mxy, xy, xy1) } +func VSUBPS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VSUBPS_Z(mxyz, xyz, k, xyz1) } -// VPXOR: Packed Bitwise Logical Exclusive OR. +// VSUBSD: Subtract Scalar Double-Precision Floating-Point Values. // // Forms: // -// VPXOR xmm xmm xmm -// VPXOR m128 xmm xmm -// VPXOR ymm ymm ymm -// VPXOR m256 ymm ymm -// Construct and append a VPXOR instruction to the active function. -func (c *Context) VPXOR(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VPXOR(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBSD m64 xmm xmm +// VSUBSD xmm xmm xmm +// VSUBSD m64 xmm k xmm +// VSUBSD xmm xmm k xmm +// Construct and append a VSUBSD instruction to the active function. +func (c *Context) VSUBSD(ops ...operand.Op) { + c.addinstruction(x86.VSUBSD(ops...)) } -// VPXOR: Packed Bitwise Logical Exclusive OR. +// VSUBSD: Subtract Scalar Double-Precision Floating-Point Values. // // Forms: // -// VPXOR xmm xmm xmm -// VPXOR m128 xmm xmm -// VPXOR ymm ymm ymm -// VPXOR m256 ymm ymm -// Construct and append a VPXOR instruction to the active function. +// VSUBSD m64 xmm xmm +// VSUBSD xmm xmm xmm +// VSUBSD m64 xmm k xmm +// VSUBSD xmm xmm k xmm +// Construct and append a VSUBSD instruction to the active function. // Operates on the global context. -func VPXOR(mxy, xy, xy1 operand.Op) { ctx.VPXOR(mxy, xy, xy1) } +func VSUBSD(ops ...operand.Op) { ctx.VSUBSD(ops...) } -// VRCPPS: Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values. +// VSUBSD_RD_SAE: Subtract Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). // // Forms: // -// VRCPPS xmm xmm -// VRCPPS m128 xmm -// VRCPPS ymm ymm -// VRCPPS m256 ymm -// Construct and append a VRCPPS instruction to the active function. -func (c *Context) VRCPPS(mxy, xy operand.Op) { - if inst, err := x86.VRCPPS(mxy, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBSD.RD_SAE xmm xmm k xmm +// VSUBSD.RD_SAE xmm xmm xmm +// Construct and append a VSUBSD.RD_SAE instruction to the active function. +func (c *Context) VSUBSD_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSUBSD_RD_SAE(ops...)) } -// VRCPPS: Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values. +// VSUBSD_RD_SAE: Subtract Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). // // Forms: // -// VRCPPS xmm xmm -// VRCPPS m128 xmm -// VRCPPS ymm ymm -// VRCPPS m256 ymm -// Construct and append a VRCPPS instruction to the active function. +// VSUBSD.RD_SAE xmm xmm k xmm +// VSUBSD.RD_SAE xmm xmm xmm +// Construct and append a VSUBSD.RD_SAE instruction to the active function. // Operates on the global context. -func VRCPPS(mxy, xy operand.Op) { ctx.VRCPPS(mxy, xy) } +func VSUBSD_RD_SAE(ops ...operand.Op) { ctx.VSUBSD_RD_SAE(ops...) } -// VRCPSS: Compute Approximate Reciprocal of Scalar Single-Precision Floating-Point Values. +// VSUBSD_RD_SAE_Z: Subtract Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VRCPSS xmm xmm xmm -// VRCPSS m32 xmm xmm -// Construct and append a VRCPSS instruction to the active function. -func (c *Context) VRCPSS(mx, x, x1 operand.Op) { - if inst, err := x86.VRCPSS(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBSD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VSUBSD.RD_SAE.Z instruction to the active function. +func (c *Context) VSUBSD_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VSUBSD_RD_SAE_Z(x, x1, k, x2)) } -// VRCPSS: Compute Approximate Reciprocal of Scalar Single-Precision Floating-Point Values. +// VSUBSD_RD_SAE_Z: Subtract Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VRCPSS xmm xmm xmm -// VRCPSS m32 xmm xmm -// Construct and append a VRCPSS instruction to the active function. +// VSUBSD.RD_SAE.Z xmm xmm k xmm +// Construct and append a VSUBSD.RD_SAE.Z instruction to the active function. // Operates on the global context. -func VRCPSS(mx, x, x1 operand.Op) { ctx.VRCPSS(mx, x, x1) } +func VSUBSD_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VSUBSD_RD_SAE_Z(x, x1, k, x2) } -// VROUNDPD: Round Packed Double Precision Floating-Point Values. +// VSUBSD_RN_SAE: Subtract Scalar Double-Precision Floating-Point Values (Round Towards Nearest). // // Forms: // -// VROUNDPD imm8 xmm xmm -// VROUNDPD imm8 m128 xmm -// VROUNDPD imm8 ymm ymm -// VROUNDPD imm8 m256 ymm -// Construct and append a VROUNDPD instruction to the active function. -func (c *Context) VROUNDPD(i, mxy, xy operand.Op) { - if inst, err := x86.VROUNDPD(i, mxy, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBSD.RN_SAE xmm xmm k xmm +// VSUBSD.RN_SAE xmm xmm xmm +// Construct and append a VSUBSD.RN_SAE instruction to the active function. +func (c *Context) VSUBSD_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSUBSD_RN_SAE(ops...)) } -// VROUNDPD: Round Packed Double Precision Floating-Point Values. +// VSUBSD_RN_SAE: Subtract Scalar Double-Precision Floating-Point Values (Round Towards Nearest). // // Forms: // -// VROUNDPD imm8 xmm xmm -// VROUNDPD imm8 m128 xmm -// VROUNDPD imm8 ymm ymm -// VROUNDPD imm8 m256 ymm -// Construct and append a VROUNDPD instruction to the active function. +// VSUBSD.RN_SAE xmm xmm k xmm +// VSUBSD.RN_SAE xmm xmm xmm +// Construct and append a VSUBSD.RN_SAE instruction to the active function. // Operates on the global context. -func VROUNDPD(i, mxy, xy operand.Op) { ctx.VROUNDPD(i, mxy, xy) } +func VSUBSD_RN_SAE(ops ...operand.Op) { ctx.VSUBSD_RN_SAE(ops...) } -// VROUNDPS: Round Packed Single Precision Floating-Point Values. +// VSUBSD_RN_SAE_Z: Subtract Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VROUNDPS imm8 xmm xmm -// VROUNDPS imm8 m128 xmm -// VROUNDPS imm8 ymm ymm -// VROUNDPS imm8 m256 ymm -// Construct and append a VROUNDPS instruction to the active function. -func (c *Context) VROUNDPS(i, mxy, xy operand.Op) { - if inst, err := x86.VROUNDPS(i, mxy, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBSD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VSUBSD.RN_SAE.Z instruction to the active function. +func (c *Context) VSUBSD_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VSUBSD_RN_SAE_Z(x, x1, k, x2)) } -// VROUNDPS: Round Packed Single Precision Floating-Point Values. +// VSUBSD_RN_SAE_Z: Subtract Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VROUNDPS imm8 xmm xmm -// VROUNDPS imm8 m128 xmm -// VROUNDPS imm8 ymm ymm -// VROUNDPS imm8 m256 ymm -// Construct and append a VROUNDPS instruction to the active function. +// VSUBSD.RN_SAE.Z xmm xmm k xmm +// Construct and append a VSUBSD.RN_SAE.Z instruction to the active function. // Operates on the global context. -func VROUNDPS(i, mxy, xy operand.Op) { ctx.VROUNDPS(i, mxy, xy) } +func VSUBSD_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VSUBSD_RN_SAE_Z(x, x1, k, x2) } -// VROUNDSD: Round Scalar Double Precision Floating-Point Values. +// VSUBSD_RU_SAE: Subtract Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). // // Forms: // -// VROUNDSD imm8 xmm xmm xmm -// VROUNDSD imm8 m64 xmm xmm -// Construct and append a VROUNDSD instruction to the active function. -func (c *Context) VROUNDSD(i, mx, x, x1 operand.Op) { - if inst, err := x86.VROUNDSD(i, mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBSD.RU_SAE xmm xmm k xmm +// VSUBSD.RU_SAE xmm xmm xmm +// Construct and append a VSUBSD.RU_SAE instruction to the active function. +func (c *Context) VSUBSD_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSUBSD_RU_SAE(ops...)) } -// VROUNDSD: Round Scalar Double Precision Floating-Point Values. +// VSUBSD_RU_SAE: Subtract Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). // // Forms: // -// VROUNDSD imm8 xmm xmm xmm -// VROUNDSD imm8 m64 xmm xmm -// Construct and append a VROUNDSD instruction to the active function. +// VSUBSD.RU_SAE xmm xmm k xmm +// VSUBSD.RU_SAE xmm xmm xmm +// Construct and append a VSUBSD.RU_SAE instruction to the active function. // Operates on the global context. -func VROUNDSD(i, mx, x, x1 operand.Op) { ctx.VROUNDSD(i, mx, x, x1) } +func VSUBSD_RU_SAE(ops ...operand.Op) { ctx.VSUBSD_RU_SAE(ops...) } -// VROUNDSS: Round Scalar Single Precision Floating-Point Values. +// VSUBSD_RU_SAE_Z: Subtract Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VROUNDSS imm8 xmm xmm xmm -// VROUNDSS imm8 m32 xmm xmm -// Construct and append a VROUNDSS instruction to the active function. -func (c *Context) VROUNDSS(i, mx, x, x1 operand.Op) { - if inst, err := x86.VROUNDSS(i, mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBSD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VSUBSD.RU_SAE.Z instruction to the active function. +func (c *Context) VSUBSD_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VSUBSD_RU_SAE_Z(x, x1, k, x2)) } -// VROUNDSS: Round Scalar Single Precision Floating-Point Values. +// VSUBSD_RU_SAE_Z: Subtract Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VROUNDSS imm8 xmm xmm xmm -// VROUNDSS imm8 m32 xmm xmm -// Construct and append a VROUNDSS instruction to the active function. +// VSUBSD.RU_SAE.Z xmm xmm k xmm +// Construct and append a VSUBSD.RU_SAE.Z instruction to the active function. // Operates on the global context. -func VROUNDSS(i, mx, x, x1 operand.Op) { ctx.VROUNDSS(i, mx, x, x1) } +func VSUBSD_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VSUBSD_RU_SAE_Z(x, x1, k, x2) } -// VRSQRTPS: Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values. +// VSUBSD_RZ_SAE: Subtract Scalar Double-Precision Floating-Point Values (Round Towards Zero). // // Forms: // -// VRSQRTPS xmm xmm -// VRSQRTPS m128 xmm -// VRSQRTPS ymm ymm -// VRSQRTPS m256 ymm -// Construct and append a VRSQRTPS instruction to the active function. -func (c *Context) VRSQRTPS(mxy, xy operand.Op) { - if inst, err := x86.VRSQRTPS(mxy, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBSD.RZ_SAE xmm xmm k xmm +// VSUBSD.RZ_SAE xmm xmm xmm +// Construct and append a VSUBSD.RZ_SAE instruction to the active function. +func (c *Context) VSUBSD_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSUBSD_RZ_SAE(ops...)) } -// VRSQRTPS: Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values. +// VSUBSD_RZ_SAE: Subtract Scalar Double-Precision Floating-Point Values (Round Towards Zero). // // Forms: // -// VRSQRTPS xmm xmm -// VRSQRTPS m128 xmm -// VRSQRTPS ymm ymm -// VRSQRTPS m256 ymm -// Construct and append a VRSQRTPS instruction to the active function. +// VSUBSD.RZ_SAE xmm xmm k xmm +// VSUBSD.RZ_SAE xmm xmm xmm +// Construct and append a VSUBSD.RZ_SAE instruction to the active function. // Operates on the global context. -func VRSQRTPS(mxy, xy operand.Op) { ctx.VRSQRTPS(mxy, xy) } +func VSUBSD_RZ_SAE(ops ...operand.Op) { ctx.VSUBSD_RZ_SAE(ops...) } -// VRSQRTSS: Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value. +// VSUBSD_RZ_SAE_Z: Subtract Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). // // Forms: // -// VRSQRTSS xmm xmm xmm -// VRSQRTSS m32 xmm xmm -// Construct and append a VRSQRTSS instruction to the active function. -func (c *Context) VRSQRTSS(mx, x, x1 operand.Op) { - if inst, err := x86.VRSQRTSS(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBSD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VSUBSD.RZ_SAE.Z instruction to the active function. +func (c *Context) VSUBSD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VSUBSD_RZ_SAE_Z(x, x1, k, x2)) } -// VRSQRTSS: Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value. +// VSUBSD_RZ_SAE_Z: Subtract Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). // // Forms: // -// VRSQRTSS xmm xmm xmm -// VRSQRTSS m32 xmm xmm -// Construct and append a VRSQRTSS instruction to the active function. +// VSUBSD.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VSUBSD.RZ_SAE.Z instruction to the active function. // Operates on the global context. -func VRSQRTSS(mx, x, x1 operand.Op) { ctx.VRSQRTSS(mx, x, x1) } +func VSUBSD_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VSUBSD_RZ_SAE_Z(x, x1, k, x2) } -// VSHUFPD: Shuffle Packed Double-Precision Floating-Point Values. +// VSUBSD_Z: Subtract Scalar Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VSHUFPD imm8 xmm xmm xmm -// VSHUFPD imm8 m128 xmm xmm -// VSHUFPD imm8 ymm ymm ymm -// VSHUFPD imm8 m256 ymm ymm -// Construct and append a VSHUFPD instruction to the active function. -func (c *Context) VSHUFPD(i, mxy, xy, xy1 operand.Op) { - if inst, err := x86.VSHUFPD(i, mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBSD.Z m64 xmm k xmm +// VSUBSD.Z xmm xmm k xmm +// Construct and append a VSUBSD.Z instruction to the active function. +func (c *Context) VSUBSD_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VSUBSD_Z(mx, x, k, x1)) } -// VSHUFPD: Shuffle Packed Double-Precision Floating-Point Values. +// VSUBSD_Z: Subtract Scalar Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VSHUFPD imm8 xmm xmm xmm -// VSHUFPD imm8 m128 xmm xmm -// VSHUFPD imm8 ymm ymm ymm -// VSHUFPD imm8 m256 ymm ymm -// Construct and append a VSHUFPD instruction to the active function. +// VSUBSD.Z m64 xmm k xmm +// VSUBSD.Z xmm xmm k xmm +// Construct and append a VSUBSD.Z instruction to the active function. // Operates on the global context. -func VSHUFPD(i, mxy, xy, xy1 operand.Op) { ctx.VSHUFPD(i, mxy, xy, xy1) } +func VSUBSD_Z(mx, x, k, x1 operand.Op) { ctx.VSUBSD_Z(mx, x, k, x1) } -// VSHUFPS: Shuffle Packed Single-Precision Floating-Point Values. +// VSUBSS: Subtract Scalar Single-Precision Floating-Point Values. // // Forms: // -// VSHUFPS imm8 xmm xmm xmm -// VSHUFPS imm8 m128 xmm xmm -// VSHUFPS imm8 ymm ymm ymm -// VSHUFPS imm8 m256 ymm ymm -// Construct and append a VSHUFPS instruction to the active function. -func (c *Context) VSHUFPS(i, mxy, xy, xy1 operand.Op) { - if inst, err := x86.VSHUFPS(i, mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBSS m32 xmm xmm +// VSUBSS xmm xmm xmm +// VSUBSS m32 xmm k xmm +// VSUBSS xmm xmm k xmm +// Construct and append a VSUBSS instruction to the active function. +func (c *Context) VSUBSS(ops ...operand.Op) { + c.addinstruction(x86.VSUBSS(ops...)) } -// VSHUFPS: Shuffle Packed Single-Precision Floating-Point Values. +// VSUBSS: Subtract Scalar Single-Precision Floating-Point Values. // // Forms: // -// VSHUFPS imm8 xmm xmm xmm -// VSHUFPS imm8 m128 xmm xmm -// VSHUFPS imm8 ymm ymm ymm -// VSHUFPS imm8 m256 ymm ymm -// Construct and append a VSHUFPS instruction to the active function. +// VSUBSS m32 xmm xmm +// VSUBSS xmm xmm xmm +// VSUBSS m32 xmm k xmm +// VSUBSS xmm xmm k xmm +// Construct and append a VSUBSS instruction to the active function. // Operates on the global context. -func VSHUFPS(i, mxy, xy, xy1 operand.Op) { ctx.VSHUFPS(i, mxy, xy, xy1) } +func VSUBSS(ops ...operand.Op) { ctx.VSUBSS(ops...) } -// VSQRTPD: Compute Square Roots of Packed Double-Precision Floating-Point Values. +// VSUBSS_RD_SAE: Subtract Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). // // Forms: // -// VSQRTPD xmm xmm -// VSQRTPD m128 xmm -// VSQRTPD ymm ymm -// VSQRTPD m256 ymm -// Construct and append a VSQRTPD instruction to the active function. -func (c *Context) VSQRTPD(mxy, xy operand.Op) { - if inst, err := x86.VSQRTPD(mxy, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBSS.RD_SAE xmm xmm k xmm +// VSUBSS.RD_SAE xmm xmm xmm +// Construct and append a VSUBSS.RD_SAE instruction to the active function. +func (c *Context) VSUBSS_RD_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSUBSS_RD_SAE(ops...)) } -// VSQRTPD: Compute Square Roots of Packed Double-Precision Floating-Point Values. +// VSUBSS_RD_SAE: Subtract Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). // // Forms: // -// VSQRTPD xmm xmm -// VSQRTPD m128 xmm -// VSQRTPD ymm ymm -// VSQRTPD m256 ymm -// Construct and append a VSQRTPD instruction to the active function. +// VSUBSS.RD_SAE xmm xmm k xmm +// VSUBSS.RD_SAE xmm xmm xmm +// Construct and append a VSUBSS.RD_SAE instruction to the active function. // Operates on the global context. -func VSQRTPD(mxy, xy operand.Op) { ctx.VSQRTPD(mxy, xy) } +func VSUBSS_RD_SAE(ops ...operand.Op) { ctx.VSUBSS_RD_SAE(ops...) } -// VSQRTPS: Compute Square Roots of Packed Single-Precision Floating-Point Values. +// VSUBSS_RD_SAE_Z: Subtract Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VSQRTPS xmm xmm -// VSQRTPS m128 xmm -// VSQRTPS ymm ymm -// VSQRTPS m256 ymm -// Construct and append a VSQRTPS instruction to the active function. -func (c *Context) VSQRTPS(mxy, xy operand.Op) { - if inst, err := x86.VSQRTPS(mxy, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBSS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VSUBSS.RD_SAE.Z instruction to the active function. +func (c *Context) VSUBSS_RD_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VSUBSS_RD_SAE_Z(x, x1, k, x2)) } -// VSQRTPS: Compute Square Roots of Packed Single-Precision Floating-Point Values. +// VSUBSS_RD_SAE_Z: Subtract Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VSQRTPS xmm xmm -// VSQRTPS m128 xmm -// VSQRTPS ymm ymm -// VSQRTPS m256 ymm -// Construct and append a VSQRTPS instruction to the active function. +// VSUBSS.RD_SAE.Z xmm xmm k xmm +// Construct and append a VSUBSS.RD_SAE.Z instruction to the active function. // Operates on the global context. -func VSQRTPS(mxy, xy operand.Op) { ctx.VSQRTPS(mxy, xy) } +func VSUBSS_RD_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VSUBSS_RD_SAE_Z(x, x1, k, x2) } -// VSQRTSD: Compute Square Root of Scalar Double-Precision Floating-Point Value. +// VSUBSS_RN_SAE: Subtract Scalar Single-Precision Floating-Point Values (Round Towards Nearest). // // Forms: // -// VSQRTSD xmm xmm xmm -// VSQRTSD m64 xmm xmm -// Construct and append a VSQRTSD instruction to the active function. -func (c *Context) VSQRTSD(mx, x, x1 operand.Op) { - if inst, err := x86.VSQRTSD(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBSS.RN_SAE xmm xmm k xmm +// VSUBSS.RN_SAE xmm xmm xmm +// Construct and append a VSUBSS.RN_SAE instruction to the active function. +func (c *Context) VSUBSS_RN_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSUBSS_RN_SAE(ops...)) } -// VSQRTSD: Compute Square Root of Scalar Double-Precision Floating-Point Value. +// VSUBSS_RN_SAE: Subtract Scalar Single-Precision Floating-Point Values (Round Towards Nearest). // // Forms: // -// VSQRTSD xmm xmm xmm -// VSQRTSD m64 xmm xmm -// Construct and append a VSQRTSD instruction to the active function. +// VSUBSS.RN_SAE xmm xmm k xmm +// VSUBSS.RN_SAE xmm xmm xmm +// Construct and append a VSUBSS.RN_SAE instruction to the active function. // Operates on the global context. -func VSQRTSD(mx, x, x1 operand.Op) { ctx.VSQRTSD(mx, x, x1) } +func VSUBSS_RN_SAE(ops ...operand.Op) { ctx.VSUBSS_RN_SAE(ops...) } -// VSQRTSS: Compute Square Root of Scalar Single-Precision Floating-Point Value. +// VSUBSS_RN_SAE_Z: Subtract Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VSQRTSS xmm xmm xmm -// VSQRTSS m32 xmm xmm -// Construct and append a VSQRTSS instruction to the active function. -func (c *Context) VSQRTSS(mx, x, x1 operand.Op) { - if inst, err := x86.VSQRTSS(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBSS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VSUBSS.RN_SAE.Z instruction to the active function. +func (c *Context) VSUBSS_RN_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VSUBSS_RN_SAE_Z(x, x1, k, x2)) } -// VSQRTSS: Compute Square Root of Scalar Single-Precision Floating-Point Value. +// VSUBSS_RN_SAE_Z: Subtract Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VSQRTSS xmm xmm xmm -// VSQRTSS m32 xmm xmm -// Construct and append a VSQRTSS instruction to the active function. +// VSUBSS.RN_SAE.Z xmm xmm k xmm +// Construct and append a VSUBSS.RN_SAE.Z instruction to the active function. // Operates on the global context. -func VSQRTSS(mx, x, x1 operand.Op) { ctx.VSQRTSS(mx, x, x1) } +func VSUBSS_RN_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VSUBSS_RN_SAE_Z(x, x1, k, x2) } -// VSTMXCSR: Store MXCSR Register State. +// VSUBSS_RU_SAE: Subtract Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). // // Forms: // -// VSTMXCSR m32 -// Construct and append a VSTMXCSR instruction to the active function. -func (c *Context) VSTMXCSR(m operand.Op) { - if inst, err := x86.VSTMXCSR(m); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBSS.RU_SAE xmm xmm k xmm +// VSUBSS.RU_SAE xmm xmm xmm +// Construct and append a VSUBSS.RU_SAE instruction to the active function. +func (c *Context) VSUBSS_RU_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSUBSS_RU_SAE(ops...)) } -// VSTMXCSR: Store MXCSR Register State. +// VSUBSS_RU_SAE: Subtract Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). // // Forms: // -// VSTMXCSR m32 -// Construct and append a VSTMXCSR instruction to the active function. +// VSUBSS.RU_SAE xmm xmm k xmm +// VSUBSS.RU_SAE xmm xmm xmm +// Construct and append a VSUBSS.RU_SAE instruction to the active function. // Operates on the global context. -func VSTMXCSR(m operand.Op) { ctx.VSTMXCSR(m) } +func VSUBSS_RU_SAE(ops ...operand.Op) { ctx.VSUBSS_RU_SAE(ops...) } -// VSUBPD: Subtract Packed Double-Precision Floating-Point Values. +// VSUBSS_RU_SAE_Z: Subtract Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). // // Forms: -// -// VSUBPD xmm xmm xmm -// VSUBPD m128 xmm xmm -// VSUBPD ymm ymm ymm -// VSUBPD m256 ymm ymm -// Construct and append a VSUBPD instruction to the active function. -func (c *Context) VSUBPD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VSUBPD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// +// VSUBSS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VSUBSS.RU_SAE.Z instruction to the active function. +func (c *Context) VSUBSS_RU_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VSUBSS_RU_SAE_Z(x, x1, k, x2)) } -// VSUBPD: Subtract Packed Double-Precision Floating-Point Values. +// VSUBSS_RU_SAE_Z: Subtract Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VSUBPD xmm xmm xmm -// VSUBPD m128 xmm xmm -// VSUBPD ymm ymm ymm -// VSUBPD m256 ymm ymm -// Construct and append a VSUBPD instruction to the active function. +// VSUBSS.RU_SAE.Z xmm xmm k xmm +// Construct and append a VSUBSS.RU_SAE.Z instruction to the active function. // Operates on the global context. -func VSUBPD(mxy, xy, xy1 operand.Op) { ctx.VSUBPD(mxy, xy, xy1) } +func VSUBSS_RU_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VSUBSS_RU_SAE_Z(x, x1, k, x2) } -// VSUBPS: Subtract Packed Single-Precision Floating-Point Values. +// VSUBSS_RZ_SAE: Subtract Scalar Single-Precision Floating-Point Values (Round Towards Zero). // // Forms: // -// VSUBPS xmm xmm xmm -// VSUBPS m128 xmm xmm -// VSUBPS ymm ymm ymm -// VSUBPS m256 ymm ymm -// Construct and append a VSUBPS instruction to the active function. -func (c *Context) VSUBPS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VSUBPS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBSS.RZ_SAE xmm xmm k xmm +// VSUBSS.RZ_SAE xmm xmm xmm +// Construct and append a VSUBSS.RZ_SAE instruction to the active function. +func (c *Context) VSUBSS_RZ_SAE(ops ...operand.Op) { + c.addinstruction(x86.VSUBSS_RZ_SAE(ops...)) } -// VSUBPS: Subtract Packed Single-Precision Floating-Point Values. +// VSUBSS_RZ_SAE: Subtract Scalar Single-Precision Floating-Point Values (Round Towards Zero). // // Forms: // -// VSUBPS xmm xmm xmm -// VSUBPS m128 xmm xmm -// VSUBPS ymm ymm ymm -// VSUBPS m256 ymm ymm -// Construct and append a VSUBPS instruction to the active function. +// VSUBSS.RZ_SAE xmm xmm k xmm +// VSUBSS.RZ_SAE xmm xmm xmm +// Construct and append a VSUBSS.RZ_SAE instruction to the active function. // Operates on the global context. -func VSUBPS(mxy, xy, xy1 operand.Op) { ctx.VSUBPS(mxy, xy, xy1) } +func VSUBSS_RZ_SAE(ops ...operand.Op) { ctx.VSUBSS_RZ_SAE(ops...) } -// VSUBSD: Subtract Scalar Double-Precision Floating-Point Values. +// VSUBSS_RZ_SAE_Z: Subtract Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). // // Forms: // -// VSUBSD xmm xmm xmm -// VSUBSD m64 xmm xmm -// Construct and append a VSUBSD instruction to the active function. -func (c *Context) VSUBSD(mx, x, x1 operand.Op) { - if inst, err := x86.VSUBSD(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBSS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VSUBSS.RZ_SAE.Z instruction to the active function. +func (c *Context) VSUBSS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { + c.addinstruction(x86.VSUBSS_RZ_SAE_Z(x, x1, k, x2)) } -// VSUBSD: Subtract Scalar Double-Precision Floating-Point Values. +// VSUBSS_RZ_SAE_Z: Subtract Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). // // Forms: // -// VSUBSD xmm xmm xmm -// VSUBSD m64 xmm xmm -// Construct and append a VSUBSD instruction to the active function. +// VSUBSS.RZ_SAE.Z xmm xmm k xmm +// Construct and append a VSUBSS.RZ_SAE.Z instruction to the active function. // Operates on the global context. -func VSUBSD(mx, x, x1 operand.Op) { ctx.VSUBSD(mx, x, x1) } +func VSUBSS_RZ_SAE_Z(x, x1, k, x2 operand.Op) { ctx.VSUBSS_RZ_SAE_Z(x, x1, k, x2) } -// VSUBSS: Subtract Scalar Single-Precision Floating-Point Values. +// VSUBSS_Z: Subtract Scalar Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VSUBSS xmm xmm xmm -// VSUBSS m32 xmm xmm -// Construct and append a VSUBSS instruction to the active function. -func (c *Context) VSUBSS(mx, x, x1 operand.Op) { - if inst, err := x86.VSUBSS(mx, x, x1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +// VSUBSS.Z m32 xmm k xmm +// VSUBSS.Z xmm xmm k xmm +// Construct and append a VSUBSS.Z instruction to the active function. +func (c *Context) VSUBSS_Z(mx, x, k, x1 operand.Op) { + c.addinstruction(x86.VSUBSS_Z(mx, x, k, x1)) } -// VSUBSS: Subtract Scalar Single-Precision Floating-Point Values. +// VSUBSS_Z: Subtract Scalar Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VSUBSS xmm xmm xmm -// VSUBSS m32 xmm xmm -// Construct and append a VSUBSS instruction to the active function. +// VSUBSS.Z m32 xmm k xmm +// VSUBSS.Z xmm xmm k xmm +// Construct and append a VSUBSS.Z instruction to the active function. // Operates on the global context. -func VSUBSS(mx, x, x1 operand.Op) { ctx.VSUBSS(mx, x, x1) } +func VSUBSS_Z(mx, x, k, x1 operand.Op) { ctx.VSUBSS_Z(mx, x, k, x1) } // VTESTPD: Packed Double-Precision Floating-Point Bit Test. // // Forms: // -// VTESTPD xmm xmm // VTESTPD m128 xmm -// VTESTPD ymm ymm // VTESTPD m256 ymm +// VTESTPD xmm xmm +// VTESTPD ymm ymm // Construct and append a VTESTPD instruction to the active function. func (c *Context) VTESTPD(mxy, xy operand.Op) { - if inst, err := x86.VTESTPD(mxy, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.VTESTPD(mxy, xy)) } // VTESTPD: Packed Double-Precision Floating-Point Bit Test. // // Forms: // -// VTESTPD xmm xmm // VTESTPD m128 xmm -// VTESTPD ymm ymm // VTESTPD m256 ymm +// VTESTPD xmm xmm +// VTESTPD ymm ymm // Construct and append a VTESTPD instruction to the active function. // Operates on the global context. func VTESTPD(mxy, xy operand.Op) { ctx.VTESTPD(mxy, xy) } @@ -25559,27 +76549,23 @@ func VTESTPD(mxy, xy operand.Op) { ctx.VTESTPD(mxy, xy) } // // Forms: // -// VTESTPS xmm xmm // VTESTPS m128 xmm -// VTESTPS ymm ymm // VTESTPS m256 ymm +// VTESTPS xmm xmm +// VTESTPS ymm ymm // Construct and append a VTESTPS instruction to the active function. func (c *Context) VTESTPS(mxy, xy operand.Op) { - if inst, err := x86.VTESTPS(mxy, xy); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.VTESTPS(mxy, xy)) } // VTESTPS: Packed Single-Precision Floating-Point Bit Test. // // Forms: // -// VTESTPS xmm xmm // VTESTPS m128 xmm -// VTESTPS ymm ymm // VTESTPS m256 ymm +// VTESTPS xmm xmm +// VTESTPS ymm ymm // Construct and append a VTESTPS instruction to the active function. // Operates on the global context. func VTESTPS(mxy, xy operand.Op) { ctx.VTESTPS(mxy, xy) } @@ -25588,225 +76574,813 @@ func VTESTPS(mxy, xy operand.Op) { ctx.VTESTPS(mxy, xy) } // // Forms: // -// VUCOMISD xmm xmm // VUCOMISD m64 xmm +// VUCOMISD xmm xmm // Construct and append a VUCOMISD instruction to the active function. func (c *Context) VUCOMISD(mx, x operand.Op) { - if inst, err := x86.VUCOMISD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.VUCOMISD(mx, x)) } // VUCOMISD: Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS. // // Forms: // -// VUCOMISD xmm xmm // VUCOMISD m64 xmm +// VUCOMISD xmm xmm // Construct and append a VUCOMISD instruction to the active function. // Operates on the global context. func VUCOMISD(mx, x operand.Op) { ctx.VUCOMISD(mx, x) } +// VUCOMISD_SAE: Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS (Suppress All Exceptions). +// +// Forms: +// +// VUCOMISD.SAE xmm xmm +// Construct and append a VUCOMISD.SAE instruction to the active function. +func (c *Context) VUCOMISD_SAE(x, x1 operand.Op) { + c.addinstruction(x86.VUCOMISD_SAE(x, x1)) +} + +// VUCOMISD_SAE: Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS (Suppress All Exceptions). +// +// Forms: +// +// VUCOMISD.SAE xmm xmm +// Construct and append a VUCOMISD.SAE instruction to the active function. +// Operates on the global context. +func VUCOMISD_SAE(x, x1 operand.Op) { ctx.VUCOMISD_SAE(x, x1) } + // VUCOMISS: Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS. // // Forms: // -// VUCOMISS xmm xmm // VUCOMISS m32 xmm +// VUCOMISS xmm xmm // Construct and append a VUCOMISS instruction to the active function. func (c *Context) VUCOMISS(mx, x operand.Op) { - if inst, err := x86.VUCOMISS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.VUCOMISS(mx, x)) } // VUCOMISS: Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS. // // Forms: // -// VUCOMISS xmm xmm // VUCOMISS m32 xmm +// VUCOMISS xmm xmm // Construct and append a VUCOMISS instruction to the active function. // Operates on the global context. func VUCOMISS(mx, x operand.Op) { ctx.VUCOMISS(mx, x) } +// VUCOMISS_SAE: Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS (Suppress All Exceptions). +// +// Forms: +// +// VUCOMISS.SAE xmm xmm +// Construct and append a VUCOMISS.SAE instruction to the active function. +func (c *Context) VUCOMISS_SAE(x, x1 operand.Op) { + c.addinstruction(x86.VUCOMISS_SAE(x, x1)) +} + +// VUCOMISS_SAE: Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS (Suppress All Exceptions). +// +// Forms: +// +// VUCOMISS.SAE xmm xmm +// Construct and append a VUCOMISS.SAE instruction to the active function. +// Operates on the global context. +func VUCOMISS_SAE(x, x1 operand.Op) { ctx.VUCOMISS_SAE(x, x1) } + // VUNPCKHPD: Unpack and Interleave High Packed Double-Precision Floating-Point Values. // // Forms: // -// VUNPCKHPD xmm xmm xmm // VUNPCKHPD m128 xmm xmm -// VUNPCKHPD ymm ymm ymm // VUNPCKHPD m256 ymm ymm +// VUNPCKHPD xmm xmm xmm +// VUNPCKHPD ymm ymm ymm +// VUNPCKHPD m128 xmm k xmm +// VUNPCKHPD m256 ymm k ymm +// VUNPCKHPD xmm xmm k xmm +// VUNPCKHPD ymm ymm k ymm +// VUNPCKHPD m512 zmm k zmm +// VUNPCKHPD m512 zmm zmm +// VUNPCKHPD zmm zmm k zmm +// VUNPCKHPD zmm zmm zmm // Construct and append a VUNPCKHPD instruction to the active function. -func (c *Context) VUNPCKHPD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VUNPCKHPD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +func (c *Context) VUNPCKHPD(ops ...operand.Op) { + c.addinstruction(x86.VUNPCKHPD(ops...)) } // VUNPCKHPD: Unpack and Interleave High Packed Double-Precision Floating-Point Values. // // Forms: // -// VUNPCKHPD xmm xmm xmm // VUNPCKHPD m128 xmm xmm -// VUNPCKHPD ymm ymm ymm // VUNPCKHPD m256 ymm ymm +// VUNPCKHPD xmm xmm xmm +// VUNPCKHPD ymm ymm ymm +// VUNPCKHPD m128 xmm k xmm +// VUNPCKHPD m256 ymm k ymm +// VUNPCKHPD xmm xmm k xmm +// VUNPCKHPD ymm ymm k ymm +// VUNPCKHPD m512 zmm k zmm +// VUNPCKHPD m512 zmm zmm +// VUNPCKHPD zmm zmm k zmm +// VUNPCKHPD zmm zmm zmm // Construct and append a VUNPCKHPD instruction to the active function. // Operates on the global context. -func VUNPCKHPD(mxy, xy, xy1 operand.Op) { ctx.VUNPCKHPD(mxy, xy, xy1) } +func VUNPCKHPD(ops ...operand.Op) { ctx.VUNPCKHPD(ops...) } + +// VUNPCKHPD_BCST: Unpack and Interleave High Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VUNPCKHPD.BCST m64 xmm k xmm +// VUNPCKHPD.BCST m64 xmm xmm +// VUNPCKHPD.BCST m64 ymm k ymm +// VUNPCKHPD.BCST m64 ymm ymm +// VUNPCKHPD.BCST m64 zmm k zmm +// VUNPCKHPD.BCST m64 zmm zmm +// Construct and append a VUNPCKHPD.BCST instruction to the active function. +func (c *Context) VUNPCKHPD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VUNPCKHPD_BCST(ops...)) +} + +// VUNPCKHPD_BCST: Unpack and Interleave High Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VUNPCKHPD.BCST m64 xmm k xmm +// VUNPCKHPD.BCST m64 xmm xmm +// VUNPCKHPD.BCST m64 ymm k ymm +// VUNPCKHPD.BCST m64 ymm ymm +// VUNPCKHPD.BCST m64 zmm k zmm +// VUNPCKHPD.BCST m64 zmm zmm +// Construct and append a VUNPCKHPD.BCST instruction to the active function. +// Operates on the global context. +func VUNPCKHPD_BCST(ops ...operand.Op) { ctx.VUNPCKHPD_BCST(ops...) } + +// VUNPCKHPD_BCST_Z: Unpack and Interleave High Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VUNPCKHPD.BCST.Z m64 xmm k xmm +// VUNPCKHPD.BCST.Z m64 ymm k ymm +// VUNPCKHPD.BCST.Z m64 zmm k zmm +// Construct and append a VUNPCKHPD.BCST.Z instruction to the active function. +func (c *Context) VUNPCKHPD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VUNPCKHPD_BCST_Z(m, xyz, k, xyz1)) +} + +// VUNPCKHPD_BCST_Z: Unpack and Interleave High Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VUNPCKHPD.BCST.Z m64 xmm k xmm +// VUNPCKHPD.BCST.Z m64 ymm k ymm +// VUNPCKHPD.BCST.Z m64 zmm k zmm +// Construct and append a VUNPCKHPD.BCST.Z instruction to the active function. +// Operates on the global context. +func VUNPCKHPD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VUNPCKHPD_BCST_Z(m, xyz, k, xyz1) } + +// VUNPCKHPD_Z: Unpack and Interleave High Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VUNPCKHPD.Z m128 xmm k xmm +// VUNPCKHPD.Z m256 ymm k ymm +// VUNPCKHPD.Z xmm xmm k xmm +// VUNPCKHPD.Z ymm ymm k ymm +// VUNPCKHPD.Z m512 zmm k zmm +// VUNPCKHPD.Z zmm zmm k zmm +// Construct and append a VUNPCKHPD.Z instruction to the active function. +func (c *Context) VUNPCKHPD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VUNPCKHPD_Z(mxyz, xyz, k, xyz1)) +} + +// VUNPCKHPD_Z: Unpack and Interleave High Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VUNPCKHPD.Z m128 xmm k xmm +// VUNPCKHPD.Z m256 ymm k ymm +// VUNPCKHPD.Z xmm xmm k xmm +// VUNPCKHPD.Z ymm ymm k ymm +// VUNPCKHPD.Z m512 zmm k zmm +// VUNPCKHPD.Z zmm zmm k zmm +// Construct and append a VUNPCKHPD.Z instruction to the active function. +// Operates on the global context. +func VUNPCKHPD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VUNPCKHPD_Z(mxyz, xyz, k, xyz1) } // VUNPCKHPS: Unpack and Interleave High Packed Single-Precision Floating-Point Values. // // Forms: // -// VUNPCKHPS xmm xmm xmm // VUNPCKHPS m128 xmm xmm -// VUNPCKHPS ymm ymm ymm // VUNPCKHPS m256 ymm ymm +// VUNPCKHPS xmm xmm xmm +// VUNPCKHPS ymm ymm ymm +// VUNPCKHPS m128 xmm k xmm +// VUNPCKHPS m256 ymm k ymm +// VUNPCKHPS xmm xmm k xmm +// VUNPCKHPS ymm ymm k ymm +// VUNPCKHPS m512 zmm k zmm +// VUNPCKHPS m512 zmm zmm +// VUNPCKHPS zmm zmm k zmm +// VUNPCKHPS zmm zmm zmm // Construct and append a VUNPCKHPS instruction to the active function. -func (c *Context) VUNPCKHPS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VUNPCKHPS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +func (c *Context) VUNPCKHPS(ops ...operand.Op) { + c.addinstruction(x86.VUNPCKHPS(ops...)) } // VUNPCKHPS: Unpack and Interleave High Packed Single-Precision Floating-Point Values. // // Forms: // -// VUNPCKHPS xmm xmm xmm // VUNPCKHPS m128 xmm xmm -// VUNPCKHPS ymm ymm ymm // VUNPCKHPS m256 ymm ymm +// VUNPCKHPS xmm xmm xmm +// VUNPCKHPS ymm ymm ymm +// VUNPCKHPS m128 xmm k xmm +// VUNPCKHPS m256 ymm k ymm +// VUNPCKHPS xmm xmm k xmm +// VUNPCKHPS ymm ymm k ymm +// VUNPCKHPS m512 zmm k zmm +// VUNPCKHPS m512 zmm zmm +// VUNPCKHPS zmm zmm k zmm +// VUNPCKHPS zmm zmm zmm // Construct and append a VUNPCKHPS instruction to the active function. // Operates on the global context. -func VUNPCKHPS(mxy, xy, xy1 operand.Op) { ctx.VUNPCKHPS(mxy, xy, xy1) } +func VUNPCKHPS(ops ...operand.Op) { ctx.VUNPCKHPS(ops...) } + +// VUNPCKHPS_BCST: Unpack and Interleave High Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VUNPCKHPS.BCST m32 xmm k xmm +// VUNPCKHPS.BCST m32 xmm xmm +// VUNPCKHPS.BCST m32 ymm k ymm +// VUNPCKHPS.BCST m32 ymm ymm +// VUNPCKHPS.BCST m32 zmm k zmm +// VUNPCKHPS.BCST m32 zmm zmm +// Construct and append a VUNPCKHPS.BCST instruction to the active function. +func (c *Context) VUNPCKHPS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VUNPCKHPS_BCST(ops...)) +} + +// VUNPCKHPS_BCST: Unpack and Interleave High Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VUNPCKHPS.BCST m32 xmm k xmm +// VUNPCKHPS.BCST m32 xmm xmm +// VUNPCKHPS.BCST m32 ymm k ymm +// VUNPCKHPS.BCST m32 ymm ymm +// VUNPCKHPS.BCST m32 zmm k zmm +// VUNPCKHPS.BCST m32 zmm zmm +// Construct and append a VUNPCKHPS.BCST instruction to the active function. +// Operates on the global context. +func VUNPCKHPS_BCST(ops ...operand.Op) { ctx.VUNPCKHPS_BCST(ops...) } + +// VUNPCKHPS_BCST_Z: Unpack and Interleave High Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VUNPCKHPS.BCST.Z m32 xmm k xmm +// VUNPCKHPS.BCST.Z m32 ymm k ymm +// VUNPCKHPS.BCST.Z m32 zmm k zmm +// Construct and append a VUNPCKHPS.BCST.Z instruction to the active function. +func (c *Context) VUNPCKHPS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VUNPCKHPS_BCST_Z(m, xyz, k, xyz1)) +} + +// VUNPCKHPS_BCST_Z: Unpack and Interleave High Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VUNPCKHPS.BCST.Z m32 xmm k xmm +// VUNPCKHPS.BCST.Z m32 ymm k ymm +// VUNPCKHPS.BCST.Z m32 zmm k zmm +// Construct and append a VUNPCKHPS.BCST.Z instruction to the active function. +// Operates on the global context. +func VUNPCKHPS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VUNPCKHPS_BCST_Z(m, xyz, k, xyz1) } + +// VUNPCKHPS_Z: Unpack and Interleave High Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VUNPCKHPS.Z m128 xmm k xmm +// VUNPCKHPS.Z m256 ymm k ymm +// VUNPCKHPS.Z xmm xmm k xmm +// VUNPCKHPS.Z ymm ymm k ymm +// VUNPCKHPS.Z m512 zmm k zmm +// VUNPCKHPS.Z zmm zmm k zmm +// Construct and append a VUNPCKHPS.Z instruction to the active function. +func (c *Context) VUNPCKHPS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VUNPCKHPS_Z(mxyz, xyz, k, xyz1)) +} + +// VUNPCKHPS_Z: Unpack and Interleave High Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VUNPCKHPS.Z m128 xmm k xmm +// VUNPCKHPS.Z m256 ymm k ymm +// VUNPCKHPS.Z xmm xmm k xmm +// VUNPCKHPS.Z ymm ymm k ymm +// VUNPCKHPS.Z m512 zmm k zmm +// VUNPCKHPS.Z zmm zmm k zmm +// Construct and append a VUNPCKHPS.Z instruction to the active function. +// Operates on the global context. +func VUNPCKHPS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VUNPCKHPS_Z(mxyz, xyz, k, xyz1) } // VUNPCKLPD: Unpack and Interleave Low Packed Double-Precision Floating-Point Values. // // Forms: // -// VUNPCKLPD xmm xmm xmm // VUNPCKLPD m128 xmm xmm -// VUNPCKLPD ymm ymm ymm // VUNPCKLPD m256 ymm ymm +// VUNPCKLPD xmm xmm xmm +// VUNPCKLPD ymm ymm ymm +// VUNPCKLPD m128 xmm k xmm +// VUNPCKLPD m256 ymm k ymm +// VUNPCKLPD xmm xmm k xmm +// VUNPCKLPD ymm ymm k ymm +// VUNPCKLPD m512 zmm k zmm +// VUNPCKLPD m512 zmm zmm +// VUNPCKLPD zmm zmm k zmm +// VUNPCKLPD zmm zmm zmm // Construct and append a VUNPCKLPD instruction to the active function. -func (c *Context) VUNPCKLPD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VUNPCKLPD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +func (c *Context) VUNPCKLPD(ops ...operand.Op) { + c.addinstruction(x86.VUNPCKLPD(ops...)) } // VUNPCKLPD: Unpack and Interleave Low Packed Double-Precision Floating-Point Values. // // Forms: // -// VUNPCKLPD xmm xmm xmm // VUNPCKLPD m128 xmm xmm -// VUNPCKLPD ymm ymm ymm // VUNPCKLPD m256 ymm ymm +// VUNPCKLPD xmm xmm xmm +// VUNPCKLPD ymm ymm ymm +// VUNPCKLPD m128 xmm k xmm +// VUNPCKLPD m256 ymm k ymm +// VUNPCKLPD xmm xmm k xmm +// VUNPCKLPD ymm ymm k ymm +// VUNPCKLPD m512 zmm k zmm +// VUNPCKLPD m512 zmm zmm +// VUNPCKLPD zmm zmm k zmm +// VUNPCKLPD zmm zmm zmm // Construct and append a VUNPCKLPD instruction to the active function. // Operates on the global context. -func VUNPCKLPD(mxy, xy, xy1 operand.Op) { ctx.VUNPCKLPD(mxy, xy, xy1) } +func VUNPCKLPD(ops ...operand.Op) { ctx.VUNPCKLPD(ops...) } + +// VUNPCKLPD_BCST: Unpack and Interleave Low Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VUNPCKLPD.BCST m64 xmm k xmm +// VUNPCKLPD.BCST m64 xmm xmm +// VUNPCKLPD.BCST m64 ymm k ymm +// VUNPCKLPD.BCST m64 ymm ymm +// VUNPCKLPD.BCST m64 zmm k zmm +// VUNPCKLPD.BCST m64 zmm zmm +// Construct and append a VUNPCKLPD.BCST instruction to the active function. +func (c *Context) VUNPCKLPD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VUNPCKLPD_BCST(ops...)) +} + +// VUNPCKLPD_BCST: Unpack and Interleave Low Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VUNPCKLPD.BCST m64 xmm k xmm +// VUNPCKLPD.BCST m64 xmm xmm +// VUNPCKLPD.BCST m64 ymm k ymm +// VUNPCKLPD.BCST m64 ymm ymm +// VUNPCKLPD.BCST m64 zmm k zmm +// VUNPCKLPD.BCST m64 zmm zmm +// Construct and append a VUNPCKLPD.BCST instruction to the active function. +// Operates on the global context. +func VUNPCKLPD_BCST(ops ...operand.Op) { ctx.VUNPCKLPD_BCST(ops...) } + +// VUNPCKLPD_BCST_Z: Unpack and Interleave Low Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VUNPCKLPD.BCST.Z m64 xmm k xmm +// VUNPCKLPD.BCST.Z m64 ymm k ymm +// VUNPCKLPD.BCST.Z m64 zmm k zmm +// Construct and append a VUNPCKLPD.BCST.Z instruction to the active function. +func (c *Context) VUNPCKLPD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VUNPCKLPD_BCST_Z(m, xyz, k, xyz1)) +} + +// VUNPCKLPD_BCST_Z: Unpack and Interleave Low Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VUNPCKLPD.BCST.Z m64 xmm k xmm +// VUNPCKLPD.BCST.Z m64 ymm k ymm +// VUNPCKLPD.BCST.Z m64 zmm k zmm +// Construct and append a VUNPCKLPD.BCST.Z instruction to the active function. +// Operates on the global context. +func VUNPCKLPD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VUNPCKLPD_BCST_Z(m, xyz, k, xyz1) } + +// VUNPCKLPD_Z: Unpack and Interleave Low Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VUNPCKLPD.Z m128 xmm k xmm +// VUNPCKLPD.Z m256 ymm k ymm +// VUNPCKLPD.Z xmm xmm k xmm +// VUNPCKLPD.Z ymm ymm k ymm +// VUNPCKLPD.Z m512 zmm k zmm +// VUNPCKLPD.Z zmm zmm k zmm +// Construct and append a VUNPCKLPD.Z instruction to the active function. +func (c *Context) VUNPCKLPD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VUNPCKLPD_Z(mxyz, xyz, k, xyz1)) +} + +// VUNPCKLPD_Z: Unpack and Interleave Low Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VUNPCKLPD.Z m128 xmm k xmm +// VUNPCKLPD.Z m256 ymm k ymm +// VUNPCKLPD.Z xmm xmm k xmm +// VUNPCKLPD.Z ymm ymm k ymm +// VUNPCKLPD.Z m512 zmm k zmm +// VUNPCKLPD.Z zmm zmm k zmm +// Construct and append a VUNPCKLPD.Z instruction to the active function. +// Operates on the global context. +func VUNPCKLPD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VUNPCKLPD_Z(mxyz, xyz, k, xyz1) } // VUNPCKLPS: Unpack and Interleave Low Packed Single-Precision Floating-Point Values. // // Forms: // -// VUNPCKLPS xmm xmm xmm // VUNPCKLPS m128 xmm xmm -// VUNPCKLPS ymm ymm ymm // VUNPCKLPS m256 ymm ymm +// VUNPCKLPS xmm xmm xmm +// VUNPCKLPS ymm ymm ymm +// VUNPCKLPS m128 xmm k xmm +// VUNPCKLPS m256 ymm k ymm +// VUNPCKLPS xmm xmm k xmm +// VUNPCKLPS ymm ymm k ymm +// VUNPCKLPS m512 zmm k zmm +// VUNPCKLPS m512 zmm zmm +// VUNPCKLPS zmm zmm k zmm +// VUNPCKLPS zmm zmm zmm // Construct and append a VUNPCKLPS instruction to the active function. -func (c *Context) VUNPCKLPS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VUNPCKLPS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +func (c *Context) VUNPCKLPS(ops ...operand.Op) { + c.addinstruction(x86.VUNPCKLPS(ops...)) } // VUNPCKLPS: Unpack and Interleave Low Packed Single-Precision Floating-Point Values. // // Forms: // -// VUNPCKLPS xmm xmm xmm // VUNPCKLPS m128 xmm xmm -// VUNPCKLPS ymm ymm ymm // VUNPCKLPS m256 ymm ymm +// VUNPCKLPS xmm xmm xmm +// VUNPCKLPS ymm ymm ymm +// VUNPCKLPS m128 xmm k xmm +// VUNPCKLPS m256 ymm k ymm +// VUNPCKLPS xmm xmm k xmm +// VUNPCKLPS ymm ymm k ymm +// VUNPCKLPS m512 zmm k zmm +// VUNPCKLPS m512 zmm zmm +// VUNPCKLPS zmm zmm k zmm +// VUNPCKLPS zmm zmm zmm // Construct and append a VUNPCKLPS instruction to the active function. // Operates on the global context. -func VUNPCKLPS(mxy, xy, xy1 operand.Op) { ctx.VUNPCKLPS(mxy, xy, xy1) } +func VUNPCKLPS(ops ...operand.Op) { ctx.VUNPCKLPS(ops...) } + +// VUNPCKLPS_BCST: Unpack and Interleave Low Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VUNPCKLPS.BCST m32 xmm k xmm +// VUNPCKLPS.BCST m32 xmm xmm +// VUNPCKLPS.BCST m32 ymm k ymm +// VUNPCKLPS.BCST m32 ymm ymm +// VUNPCKLPS.BCST m32 zmm k zmm +// VUNPCKLPS.BCST m32 zmm zmm +// Construct and append a VUNPCKLPS.BCST instruction to the active function. +func (c *Context) VUNPCKLPS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VUNPCKLPS_BCST(ops...)) +} + +// VUNPCKLPS_BCST: Unpack and Interleave Low Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VUNPCKLPS.BCST m32 xmm k xmm +// VUNPCKLPS.BCST m32 xmm xmm +// VUNPCKLPS.BCST m32 ymm k ymm +// VUNPCKLPS.BCST m32 ymm ymm +// VUNPCKLPS.BCST m32 zmm k zmm +// VUNPCKLPS.BCST m32 zmm zmm +// Construct and append a VUNPCKLPS.BCST instruction to the active function. +// Operates on the global context. +func VUNPCKLPS_BCST(ops ...operand.Op) { ctx.VUNPCKLPS_BCST(ops...) } + +// VUNPCKLPS_BCST_Z: Unpack and Interleave Low Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VUNPCKLPS.BCST.Z m32 xmm k xmm +// VUNPCKLPS.BCST.Z m32 ymm k ymm +// VUNPCKLPS.BCST.Z m32 zmm k zmm +// Construct and append a VUNPCKLPS.BCST.Z instruction to the active function. +func (c *Context) VUNPCKLPS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VUNPCKLPS_BCST_Z(m, xyz, k, xyz1)) +} + +// VUNPCKLPS_BCST_Z: Unpack and Interleave Low Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VUNPCKLPS.BCST.Z m32 xmm k xmm +// VUNPCKLPS.BCST.Z m32 ymm k ymm +// VUNPCKLPS.BCST.Z m32 zmm k zmm +// Construct and append a VUNPCKLPS.BCST.Z instruction to the active function. +// Operates on the global context. +func VUNPCKLPS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VUNPCKLPS_BCST_Z(m, xyz, k, xyz1) } + +// VUNPCKLPS_Z: Unpack and Interleave Low Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VUNPCKLPS.Z m128 xmm k xmm +// VUNPCKLPS.Z m256 ymm k ymm +// VUNPCKLPS.Z xmm xmm k xmm +// VUNPCKLPS.Z ymm ymm k ymm +// VUNPCKLPS.Z m512 zmm k zmm +// VUNPCKLPS.Z zmm zmm k zmm +// Construct and append a VUNPCKLPS.Z instruction to the active function. +func (c *Context) VUNPCKLPS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VUNPCKLPS_Z(mxyz, xyz, k, xyz1)) +} + +// VUNPCKLPS_Z: Unpack and Interleave Low Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VUNPCKLPS.Z m128 xmm k xmm +// VUNPCKLPS.Z m256 ymm k ymm +// VUNPCKLPS.Z xmm xmm k xmm +// VUNPCKLPS.Z ymm ymm k ymm +// VUNPCKLPS.Z m512 zmm k zmm +// VUNPCKLPS.Z zmm zmm k zmm +// Construct and append a VUNPCKLPS.Z instruction to the active function. +// Operates on the global context. +func VUNPCKLPS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VUNPCKLPS_Z(mxyz, xyz, k, xyz1) } // VXORPD: Bitwise Logical XOR for Double-Precision Floating-Point Values. // // Forms: // -// VXORPD xmm xmm xmm // VXORPD m128 xmm xmm -// VXORPD ymm ymm ymm // VXORPD m256 ymm ymm +// VXORPD xmm xmm xmm +// VXORPD ymm ymm ymm +// VXORPD m128 xmm k xmm +// VXORPD m256 ymm k ymm +// VXORPD xmm xmm k xmm +// VXORPD ymm ymm k ymm +// VXORPD m512 zmm k zmm +// VXORPD m512 zmm zmm +// VXORPD zmm zmm k zmm +// VXORPD zmm zmm zmm // Construct and append a VXORPD instruction to the active function. -func (c *Context) VXORPD(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VXORPD(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +func (c *Context) VXORPD(ops ...operand.Op) { + c.addinstruction(x86.VXORPD(ops...)) } // VXORPD: Bitwise Logical XOR for Double-Precision Floating-Point Values. // // Forms: // -// VXORPD xmm xmm xmm // VXORPD m128 xmm xmm -// VXORPD ymm ymm ymm // VXORPD m256 ymm ymm +// VXORPD xmm xmm xmm +// VXORPD ymm ymm ymm +// VXORPD m128 xmm k xmm +// VXORPD m256 ymm k ymm +// VXORPD xmm xmm k xmm +// VXORPD ymm ymm k ymm +// VXORPD m512 zmm k zmm +// VXORPD m512 zmm zmm +// VXORPD zmm zmm k zmm +// VXORPD zmm zmm zmm // Construct and append a VXORPD instruction to the active function. // Operates on the global context. -func VXORPD(mxy, xy, xy1 operand.Op) { ctx.VXORPD(mxy, xy, xy1) } +func VXORPD(ops ...operand.Op) { ctx.VXORPD(ops...) } + +// VXORPD_BCST: Bitwise Logical XOR for Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VXORPD.BCST m64 xmm k xmm +// VXORPD.BCST m64 xmm xmm +// VXORPD.BCST m64 ymm k ymm +// VXORPD.BCST m64 ymm ymm +// VXORPD.BCST m64 zmm k zmm +// VXORPD.BCST m64 zmm zmm +// Construct and append a VXORPD.BCST instruction to the active function. +func (c *Context) VXORPD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VXORPD_BCST(ops...)) +} + +// VXORPD_BCST: Bitwise Logical XOR for Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VXORPD.BCST m64 xmm k xmm +// VXORPD.BCST m64 xmm xmm +// VXORPD.BCST m64 ymm k ymm +// VXORPD.BCST m64 ymm ymm +// VXORPD.BCST m64 zmm k zmm +// VXORPD.BCST m64 zmm zmm +// Construct and append a VXORPD.BCST instruction to the active function. +// Operates on the global context. +func VXORPD_BCST(ops ...operand.Op) { ctx.VXORPD_BCST(ops...) } + +// VXORPD_BCST_Z: Bitwise Logical XOR for Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VXORPD.BCST.Z m64 xmm k xmm +// VXORPD.BCST.Z m64 ymm k ymm +// VXORPD.BCST.Z m64 zmm k zmm +// Construct and append a VXORPD.BCST.Z instruction to the active function. +func (c *Context) VXORPD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VXORPD_BCST_Z(m, xyz, k, xyz1)) +} + +// VXORPD_BCST_Z: Bitwise Logical XOR for Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VXORPD.BCST.Z m64 xmm k xmm +// VXORPD.BCST.Z m64 ymm k ymm +// VXORPD.BCST.Z m64 zmm k zmm +// Construct and append a VXORPD.BCST.Z instruction to the active function. +// Operates on the global context. +func VXORPD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VXORPD_BCST_Z(m, xyz, k, xyz1) } + +// VXORPD_Z: Bitwise Logical XOR for Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VXORPD.Z m128 xmm k xmm +// VXORPD.Z m256 ymm k ymm +// VXORPD.Z xmm xmm k xmm +// VXORPD.Z ymm ymm k ymm +// VXORPD.Z m512 zmm k zmm +// VXORPD.Z zmm zmm k zmm +// Construct and append a VXORPD.Z instruction to the active function. +func (c *Context) VXORPD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VXORPD_Z(mxyz, xyz, k, xyz1)) +} + +// VXORPD_Z: Bitwise Logical XOR for Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VXORPD.Z m128 xmm k xmm +// VXORPD.Z m256 ymm k ymm +// VXORPD.Z xmm xmm k xmm +// VXORPD.Z ymm ymm k ymm +// VXORPD.Z m512 zmm k zmm +// VXORPD.Z zmm zmm k zmm +// Construct and append a VXORPD.Z instruction to the active function. +// Operates on the global context. +func VXORPD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VXORPD_Z(mxyz, xyz, k, xyz1) } // VXORPS: Bitwise Logical XOR for Single-Precision Floating-Point Values. // // Forms: // -// VXORPS xmm xmm xmm // VXORPS m128 xmm xmm -// VXORPS ymm ymm ymm // VXORPS m256 ymm ymm +// VXORPS xmm xmm xmm +// VXORPS ymm ymm ymm +// VXORPS m128 xmm k xmm +// VXORPS m256 ymm k ymm +// VXORPS xmm xmm k xmm +// VXORPS ymm ymm k ymm +// VXORPS m512 zmm k zmm +// VXORPS m512 zmm zmm +// VXORPS zmm zmm k zmm +// VXORPS zmm zmm zmm // Construct and append a VXORPS instruction to the active function. -func (c *Context) VXORPS(mxy, xy, xy1 operand.Op) { - if inst, err := x86.VXORPS(mxy, xy, xy1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } +func (c *Context) VXORPS(ops ...operand.Op) { + c.addinstruction(x86.VXORPS(ops...)) } // VXORPS: Bitwise Logical XOR for Single-Precision Floating-Point Values. // // Forms: // -// VXORPS xmm xmm xmm // VXORPS m128 xmm xmm -// VXORPS ymm ymm ymm // VXORPS m256 ymm ymm +// VXORPS xmm xmm xmm +// VXORPS ymm ymm ymm +// VXORPS m128 xmm k xmm +// VXORPS m256 ymm k ymm +// VXORPS xmm xmm k xmm +// VXORPS ymm ymm k ymm +// VXORPS m512 zmm k zmm +// VXORPS m512 zmm zmm +// VXORPS zmm zmm k zmm +// VXORPS zmm zmm zmm // Construct and append a VXORPS instruction to the active function. // Operates on the global context. -func VXORPS(mxy, xy, xy1 operand.Op) { ctx.VXORPS(mxy, xy, xy1) } +func VXORPS(ops ...operand.Op) { ctx.VXORPS(ops...) } + +// VXORPS_BCST: Bitwise Logical XOR for Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VXORPS.BCST m32 xmm k xmm +// VXORPS.BCST m32 xmm xmm +// VXORPS.BCST m32 ymm k ymm +// VXORPS.BCST m32 ymm ymm +// VXORPS.BCST m32 zmm k zmm +// VXORPS.BCST m32 zmm zmm +// Construct and append a VXORPS.BCST instruction to the active function. +func (c *Context) VXORPS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VXORPS_BCST(ops...)) +} + +// VXORPS_BCST: Bitwise Logical XOR for Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VXORPS.BCST m32 xmm k xmm +// VXORPS.BCST m32 xmm xmm +// VXORPS.BCST m32 ymm k ymm +// VXORPS.BCST m32 ymm ymm +// VXORPS.BCST m32 zmm k zmm +// VXORPS.BCST m32 zmm zmm +// Construct and append a VXORPS.BCST instruction to the active function. +// Operates on the global context. +func VXORPS_BCST(ops ...operand.Op) { ctx.VXORPS_BCST(ops...) } + +// VXORPS_BCST_Z: Bitwise Logical XOR for Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VXORPS.BCST.Z m32 xmm k xmm +// VXORPS.BCST.Z m32 ymm k ymm +// VXORPS.BCST.Z m32 zmm k zmm +// Construct and append a VXORPS.BCST.Z instruction to the active function. +func (c *Context) VXORPS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VXORPS_BCST_Z(m, xyz, k, xyz1)) +} + +// VXORPS_BCST_Z: Bitwise Logical XOR for Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VXORPS.BCST.Z m32 xmm k xmm +// VXORPS.BCST.Z m32 ymm k ymm +// VXORPS.BCST.Z m32 zmm k zmm +// Construct and append a VXORPS.BCST.Z instruction to the active function. +// Operates on the global context. +func VXORPS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VXORPS_BCST_Z(m, xyz, k, xyz1) } + +// VXORPS_Z: Bitwise Logical XOR for Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VXORPS.Z m128 xmm k xmm +// VXORPS.Z m256 ymm k ymm +// VXORPS.Z xmm xmm k xmm +// VXORPS.Z ymm ymm k ymm +// VXORPS.Z m512 zmm k zmm +// VXORPS.Z zmm zmm k zmm +// Construct and append a VXORPS.Z instruction to the active function. +func (c *Context) VXORPS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VXORPS_Z(mxyz, xyz, k, xyz1)) +} + +// VXORPS_Z: Bitwise Logical XOR for Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VXORPS.Z m128 xmm k xmm +// VXORPS.Z m256 ymm k ymm +// VXORPS.Z xmm xmm k xmm +// VXORPS.Z ymm ymm k ymm +// VXORPS.Z m512 zmm k zmm +// VXORPS.Z zmm zmm k zmm +// Construct and append a VXORPS.Z instruction to the active function. +// Operates on the global context. +func VXORPS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VXORPS_Z(mxyz, xyz, k, xyz1) } // VZEROALL: Zero All YMM Registers. // @@ -25815,11 +77389,7 @@ func VXORPS(mxy, xy, xy1 operand.Op) { ctx.VXORPS(mxy, xy, xy1) } // VZEROALL // Construct and append a VZEROALL instruction to the active function. func (c *Context) VZEROALL() { - if inst, err := x86.VZEROALL(); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.VZEROALL()) } // VZEROALL: Zero All YMM Registers. @@ -25838,11 +77408,7 @@ func VZEROALL() { ctx.VZEROALL() } // VZEROUPPER // Construct and append a VZEROUPPER instruction to the active function. func (c *Context) VZEROUPPER() { - if inst, err := x86.VZEROUPPER(); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.VZEROUPPER()) } // VZEROUPPER: Zero Upper Bits of YMM Registers. @@ -25858,23 +77424,19 @@ func VZEROUPPER() { ctx.VZEROUPPER() } // // Forms: // -// XADDB r8 r8 // XADDB r8 m8 +// XADDB r8 r8 // Construct and append a XADDB instruction to the active function. func (c *Context) XADDB(r, mr operand.Op) { - if inst, err := x86.XADDB(r, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.XADDB(r, mr)) } // XADDB: Exchange and Add. // // Forms: // -// XADDB r8 r8 // XADDB r8 m8 +// XADDB r8 r8 // Construct and append a XADDB instruction to the active function. // Operates on the global context. func XADDB(r, mr operand.Op) { ctx.XADDB(r, mr) } @@ -25883,23 +77445,19 @@ func XADDB(r, mr operand.Op) { ctx.XADDB(r, mr) } // // Forms: // -// XADDL r32 r32 // XADDL r32 m32 +// XADDL r32 r32 // Construct and append a XADDL instruction to the active function. func (c *Context) XADDL(r, mr operand.Op) { - if inst, err := x86.XADDL(r, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.XADDL(r, mr)) } // XADDL: Exchange and Add. // // Forms: // -// XADDL r32 r32 // XADDL r32 m32 +// XADDL r32 r32 // Construct and append a XADDL instruction to the active function. // Operates on the global context. func XADDL(r, mr operand.Op) { ctx.XADDL(r, mr) } @@ -25908,23 +77466,19 @@ func XADDL(r, mr operand.Op) { ctx.XADDL(r, mr) } // // Forms: // -// XADDQ r64 r64 // XADDQ r64 m64 +// XADDQ r64 r64 // Construct and append a XADDQ instruction to the active function. func (c *Context) XADDQ(r, mr operand.Op) { - if inst, err := x86.XADDQ(r, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.XADDQ(r, mr)) } // XADDQ: Exchange and Add. // // Forms: // -// XADDQ r64 r64 // XADDQ r64 m64 +// XADDQ r64 r64 // Construct and append a XADDQ instruction to the active function. // Operates on the global context. func XADDQ(r, mr operand.Op) { ctx.XADDQ(r, mr) } @@ -25933,23 +77487,19 @@ func XADDQ(r, mr operand.Op) { ctx.XADDQ(r, mr) } // // Forms: // -// XADDW r16 r16 // XADDW r16 m16 +// XADDW r16 r16 // Construct and append a XADDW instruction to the active function. func (c *Context) XADDW(r, mr operand.Op) { - if inst, err := x86.XADDW(r, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.XADDW(r, mr)) } // XADDW: Exchange and Add. // // Forms: // -// XADDW r16 r16 // XADDW r16 m16 +// XADDW r16 r16 // Construct and append a XADDW instruction to the active function. // Operates on the global context. func XADDW(r, mr operand.Op) { ctx.XADDW(r, mr) } @@ -25958,25 +77508,21 @@ func XADDW(r, mr operand.Op) { ctx.XADDW(r, mr) } // // Forms: // -// XCHGB r8 r8 // XCHGB m8 r8 // XCHGB r8 m8 +// XCHGB r8 r8 // Construct and append a XCHGB instruction to the active function. func (c *Context) XCHGB(mr, mr1 operand.Op) { - if inst, err := x86.XCHGB(mr, mr1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.XCHGB(mr, mr1)) } // XCHGB: Exchange Register/Memory with Register. // // Forms: // -// XCHGB r8 r8 // XCHGB m8 r8 // XCHGB r8 m8 +// XCHGB r8 r8 // Construct and append a XCHGB instruction to the active function. // Operates on the global context. func XCHGB(mr, mr1 operand.Op) { ctx.XCHGB(mr, mr1) } @@ -25985,29 +77531,25 @@ func XCHGB(mr, mr1 operand.Op) { ctx.XCHGB(mr, mr1) } // // Forms: // -// XCHGL r32 eax // XCHGL eax r32 -// XCHGL r32 r32 // XCHGL m32 r32 +// XCHGL r32 eax // XCHGL r32 m32 +// XCHGL r32 r32 // Construct and append a XCHGL instruction to the active function. func (c *Context) XCHGL(emr, emr1 operand.Op) { - if inst, err := x86.XCHGL(emr, emr1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.XCHGL(emr, emr1)) } // XCHGL: Exchange Register/Memory with Register. // // Forms: // -// XCHGL r32 eax // XCHGL eax r32 -// XCHGL r32 r32 // XCHGL m32 r32 +// XCHGL r32 eax // XCHGL r32 m32 +// XCHGL r32 r32 // Construct and append a XCHGL instruction to the active function. // Operates on the global context. func XCHGL(emr, emr1 operand.Op) { ctx.XCHGL(emr, emr1) } @@ -26016,29 +77558,25 @@ func XCHGL(emr, emr1 operand.Op) { ctx.XCHGL(emr, emr1) } // // Forms: // -// XCHGQ r64 rax -// XCHGQ rax r64 -// XCHGQ r64 r64 // XCHGQ m64 r64 // XCHGQ r64 m64 +// XCHGQ r64 r64 +// XCHGQ r64 rax +// XCHGQ rax r64 // Construct and append a XCHGQ instruction to the active function. func (c *Context) XCHGQ(mr, mr1 operand.Op) { - if inst, err := x86.XCHGQ(mr, mr1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.XCHGQ(mr, mr1)) } // XCHGQ: Exchange Register/Memory with Register. // // Forms: // -// XCHGQ r64 rax -// XCHGQ rax r64 -// XCHGQ r64 r64 // XCHGQ m64 r64 // XCHGQ r64 m64 +// XCHGQ r64 r64 +// XCHGQ r64 rax +// XCHGQ rax r64 // Construct and append a XCHGQ instruction to the active function. // Operates on the global context. func XCHGQ(mr, mr1 operand.Op) { ctx.XCHGQ(mr, mr1) } @@ -26047,29 +77585,25 @@ func XCHGQ(mr, mr1 operand.Op) { ctx.XCHGQ(mr, mr1) } // // Forms: // -// XCHGW r16 ax // XCHGW ax r16 -// XCHGW r16 r16 // XCHGW m16 r16 +// XCHGW r16 ax // XCHGW r16 m16 +// XCHGW r16 r16 // Construct and append a XCHGW instruction to the active function. func (c *Context) XCHGW(amr, amr1 operand.Op) { - if inst, err := x86.XCHGW(amr, amr1); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.XCHGW(amr, amr1)) } // XCHGW: Exchange Register/Memory with Register. // // Forms: // -// XCHGW r16 ax // XCHGW ax r16 -// XCHGW r16 r16 // XCHGW m16 r16 +// XCHGW r16 ax // XCHGW r16 m16 +// XCHGW r16 r16 // Construct and append a XCHGW instruction to the active function. // Operates on the global context. func XCHGW(amr, amr1 operand.Op) { ctx.XCHGW(amr, amr1) } @@ -26081,11 +77615,7 @@ func XCHGW(amr, amr1 operand.Op) { ctx.XCHGW(amr, amr1) } // XGETBV // Construct and append a XGETBV instruction to the active function. func (c *Context) XGETBV() { - if inst, err := x86.XGETBV(); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.XGETBV()) } // XGETBV: Get Value of Extended Control Register. @@ -26104,11 +77634,7 @@ func XGETBV() { ctx.XGETBV() } // XLAT // Construct and append a XLAT instruction to the active function. func (c *Context) XLAT() { - if inst, err := x86.XLAT(); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.XLAT()) } // XLAT: Table Look-up Translation. @@ -26125,18 +77651,14 @@ func XLAT() { ctx.XLAT() } // Forms: // // XORB imm8 al +// XORB imm8 m8 // XORB imm8 r8 -// XORB r8 r8 // XORB m8 r8 -// XORB imm8 m8 // XORB r8 m8 +// XORB r8 r8 // Construct and append a XORB instruction to the active function. func (c *Context) XORB(imr, amr operand.Op) { - if inst, err := x86.XORB(imr, amr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.XORB(imr, amr)) } // XORB: Logical Exclusive OR. @@ -26144,11 +77666,11 @@ func (c *Context) XORB(imr, amr operand.Op) { // Forms: // // XORB imm8 al +// XORB imm8 m8 // XORB imm8 r8 -// XORB r8 r8 // XORB m8 r8 -// XORB imm8 m8 // XORB r8 m8 +// XORB r8 r8 // Construct and append a XORB instruction to the active function. // Operates on the global context. func XORB(imr, amr operand.Op) { ctx.XORB(imr, amr) } @@ -26158,20 +77680,16 @@ func XORB(imr, amr operand.Op) { ctx.XORB(imr, amr) } // Forms: // // XORL imm32 eax -// XORL imm8 r32 +// XORL imm32 m32 // XORL imm32 r32 -// XORL r32 r32 -// XORL m32 r32 // XORL imm8 m32 -// XORL imm32 m32 +// XORL imm8 r32 +// XORL m32 r32 // XORL r32 m32 +// XORL r32 r32 // Construct and append a XORL instruction to the active function. func (c *Context) XORL(imr, emr operand.Op) { - if inst, err := x86.XORL(imr, emr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.XORL(imr, emr)) } // XORL: Logical Exclusive OR. @@ -26179,13 +77697,13 @@ func (c *Context) XORL(imr, emr operand.Op) { // Forms: // // XORL imm32 eax -// XORL imm8 r32 +// XORL imm32 m32 // XORL imm32 r32 -// XORL r32 r32 -// XORL m32 r32 // XORL imm8 m32 -// XORL imm32 m32 +// XORL imm8 r32 +// XORL m32 r32 // XORL r32 m32 +// XORL r32 r32 // Construct and append a XORL instruction to the active function. // Operates on the global context. func XORL(imr, emr operand.Op) { ctx.XORL(imr, emr) } @@ -26194,23 +77712,19 @@ func XORL(imr, emr operand.Op) { ctx.XORL(imr, emr) } // // Forms: // -// XORPD xmm xmm // XORPD m128 xmm +// XORPD xmm xmm // Construct and append a XORPD instruction to the active function. func (c *Context) XORPD(mx, x operand.Op) { - if inst, err := x86.XORPD(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.XORPD(mx, x)) } // XORPD: Bitwise Logical XOR for Double-Precision Floating-Point Values. // // Forms: // -// XORPD xmm xmm // XORPD m128 xmm +// XORPD xmm xmm // Construct and append a XORPD instruction to the active function. // Operates on the global context. func XORPD(mx, x operand.Op) { ctx.XORPD(mx, x) } @@ -26219,23 +77733,19 @@ func XORPD(mx, x operand.Op) { ctx.XORPD(mx, x) } // // Forms: // -// XORPS xmm xmm // XORPS m128 xmm +// XORPS xmm xmm // Construct and append a XORPS instruction to the active function. func (c *Context) XORPS(mx, x operand.Op) { - if inst, err := x86.XORPS(mx, x); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.XORPS(mx, x)) } // XORPS: Bitwise Logical XOR for Single-Precision Floating-Point Values. // // Forms: // -// XORPS xmm xmm // XORPS m128 xmm +// XORPS xmm xmm // Construct and append a XORPS instruction to the active function. // Operates on the global context. func XORPS(mx, x operand.Op) { ctx.XORPS(mx, x) } @@ -26244,35 +77754,31 @@ func XORPS(mx, x operand.Op) { ctx.XORPS(mx, x) } // // Forms: // +// XORQ imm32 m64 +// XORQ imm32 r64 // XORQ imm32 rax +// XORQ imm8 m64 // XORQ imm8 r64 -// XORQ imm32 r64 -// XORQ r64 r64 // XORQ m64 r64 -// XORQ imm8 m64 -// XORQ imm32 m64 // XORQ r64 m64 +// XORQ r64 r64 // Construct and append a XORQ instruction to the active function. func (c *Context) XORQ(imr, mr operand.Op) { - if inst, err := x86.XORQ(imr, mr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.XORQ(imr, mr)) } // XORQ: Logical Exclusive OR. // // Forms: // +// XORQ imm32 m64 +// XORQ imm32 r64 // XORQ imm32 rax +// XORQ imm8 m64 // XORQ imm8 r64 -// XORQ imm32 r64 -// XORQ r64 r64 // XORQ m64 r64 -// XORQ imm8 m64 -// XORQ imm32 m64 // XORQ r64 m64 +// XORQ r64 r64 // Construct and append a XORQ instruction to the active function. // Operates on the global context. func XORQ(imr, mr operand.Op) { ctx.XORQ(imr, mr) } @@ -26282,20 +77788,16 @@ func XORQ(imr, mr operand.Op) { ctx.XORQ(imr, mr) } // Forms: // // XORW imm16 ax -// XORW imm8 r16 +// XORW imm16 m16 // XORW imm16 r16 -// XORW r16 r16 -// XORW m16 r16 // XORW imm8 m16 -// XORW imm16 m16 +// XORW imm8 r16 +// XORW m16 r16 // XORW r16 m16 +// XORW r16 r16 // Construct and append a XORW instruction to the active function. func (c *Context) XORW(imr, amr operand.Op) { - if inst, err := x86.XORW(imr, amr); err == nil { - c.Instruction(inst) - } else { - c.adderror(err) - } + c.addinstruction(x86.XORW(imr, amr)) } // XORW: Logical Exclusive OR. @@ -26303,13 +77805,13 @@ func (c *Context) XORW(imr, amr operand.Op) { // Forms: // // XORW imm16 ax -// XORW imm8 r16 +// XORW imm16 m16 // XORW imm16 r16 -// XORW r16 r16 -// XORW m16 r16 // XORW imm8 m16 -// XORW imm16 m16 +// XORW imm8 r16 +// XORW m16 r16 // XORW r16 m16 +// XORW r16 r16 // Construct and append a XORW instruction to the active function. // Operates on the global context. func XORW(imr, amr operand.Op) { ctx.XORW(imr, amr) } diff --git a/build/zinstructions_test.go b/build/zinstructions_test.go new file mode 100644 index 00000000..f937cb1e --- /dev/null +++ b/build/zinstructions_test.go @@ -0,0 +1,3188 @@ +// Code generated by command: avogen -output zinstructions_test.go buildtest. DO NOT EDIT. + +//go:build !integration +// +build !integration + +package build + +import ( + "math" + "testing" + + "github.com/mmcloughlin/avo/operand" + "github.com/mmcloughlin/avo/reg" +) + +var ( + op1 operand.Op = operand.Imm(1) + op3 operand.Op = operand.Imm(3) + opimm2u operand.Op = operand.Imm(3) + opimm8 operand.Op = operand.Imm(math.MaxInt8) + opimm16 operand.Op = operand.Imm(math.MaxInt16) + opimm32 operand.Op = operand.Imm(math.MaxInt32) + opimm64 operand.Op = operand.Imm(math.MaxInt64) + opal operand.Op = reg.AL + opcl operand.Op = reg.CL + opax operand.Op = reg.AX + opeax operand.Op = reg.EAX + oprax operand.Op = reg.RAX + opr8 operand.Op = reg.CH + opr16 operand.Op = reg.R9W + opr32 operand.Op = reg.R10L + opr64 operand.Op = reg.R11 + opxmm0 operand.Op = reg.X0 + opxmm operand.Op = reg.X7 + opymm operand.Op = reg.Y15 + opzmm operand.Op = reg.Z31 + opk operand.Op = reg.K7 + opm operand.Op = operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2} + opm8 operand.Op = operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1} + opm16 operand.Op = operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2} + opm32 operand.Op = operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4} + opm64 operand.Op = operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8} + opm128 operand.Op = operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8} + opm256 operand.Op = operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8} + opm512 operand.Op = operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8} + opvm32x operand.Op = operand.Mem{Base: reg.R13, Index: reg.X4, Scale: 1} + opvm64x operand.Op = operand.Mem{Base: reg.R13, Index: reg.X8, Scale: 1} + opvm32y operand.Op = operand.Mem{Base: reg.R13, Index: reg.Y4, Scale: 1} + opvm64y operand.Op = operand.Mem{Base: reg.R13, Index: reg.Y8, Scale: 1} + opvm32z operand.Op = operand.Mem{Base: reg.R13, Index: reg.Z4, Scale: 1} + opvm64z operand.Op = operand.Mem{Base: reg.R13, Index: reg.Z8, Scale: 1} + oprel8 operand.Op = operand.Rel(math.MaxInt8) + oprel32 operand.Op = operand.LabelRef("lbl") +) + +func TestContextInstructions(t *testing.T) { + ctx := NewContext() + ctx.Function("Instructions") + ctx.ADCB(opimm8, opal) + ctx.ADCL(opimm32, opeax) + ctx.ADCQ(opimm32, opm64) + ctx.ADCW(opimm16, opax) + ctx.ADCXL(opm32, opr32) + ctx.ADCXQ(opm64, opr64) + ctx.ADDB(opimm8, opal) + ctx.ADDL(opimm32, opeax) + ctx.ADDPD(opm128, opxmm) + ctx.ADDPS(opm128, opxmm) + ctx.ADDQ(opimm32, opm64) + ctx.ADDSD(opm64, opxmm) + ctx.ADDSS(opm32, opxmm) + ctx.ADDSUBPD(opm128, opxmm) + ctx.ADDSUBPS(opm128, opxmm) + ctx.ADDW(opimm16, opax) + ctx.ADOXL(opm32, opr32) + ctx.ADOXQ(opm64, opr64) + ctx.AESDEC(opm128, opxmm) + ctx.AESDECLAST(opm128, opxmm) + ctx.AESENC(opm128, opxmm) + ctx.AESENCLAST(opm128, opxmm) + ctx.AESIMC(opm128, opxmm) + ctx.AESKEYGENASSIST(opimm8, opm128, opxmm) + ctx.ANDB(opimm8, opal) + ctx.ANDL(opimm32, opeax) + ctx.ANDNL(opm32, opr32, opr32) + ctx.ANDNPD(opm128, opxmm) + ctx.ANDNPS(opm128, opxmm) + ctx.ANDNQ(opm64, opr64, opr64) + ctx.ANDPD(opm128, opxmm) + ctx.ANDPS(opm128, opxmm) + ctx.ANDQ(opimm32, opm64) + ctx.ANDW(opimm16, opax) + ctx.BEXTRL(opr32, opm32, opr32) + ctx.BEXTRQ(opr64, opm64, opr64) + ctx.BLENDPD(opimm8, opm128, opxmm) + ctx.BLENDPS(opimm8, opm128, opxmm) + ctx.BLENDVPD(opxmm0, opm128, opxmm) + ctx.BLENDVPS(opxmm0, opm128, opxmm) + ctx.BLSIL(opm32, opr32) + ctx.BLSIQ(opm64, opr64) + ctx.BLSMSKL(opm32, opr32) + ctx.BLSMSKQ(opm64, opr64) + ctx.BLSRL(opm32, opr32) + ctx.BLSRQ(opm64, opr64) + ctx.BSFL(opm32, opr32) + ctx.BSFQ(opm64, opr64) + ctx.BSFW(opm16, opr16) + ctx.BSRL(opm32, opr32) + ctx.BSRQ(opm64, opr64) + ctx.BSRW(opm16, opr16) + ctx.BSWAPL(opr32) + ctx.BSWAPQ(opr64) + ctx.BTCL(opimm8, opm32) + ctx.BTCQ(opimm8, opm64) + ctx.BTCW(opimm8, opm16) + ctx.BTL(opimm8, opm32) + ctx.BTQ(opimm8, opm64) + ctx.BTRL(opimm8, opm32) + ctx.BTRQ(opimm8, opm64) + ctx.BTRW(opimm8, opm16) + ctx.BTSL(opimm8, opm32) + ctx.BTSQ(opimm8, opm64) + ctx.BTSW(opimm8, opm16) + ctx.BTW(opimm8, opm16) + ctx.BZHIL(opr32, opm32, opr32) + ctx.BZHIQ(opr64, opm64, opr64) + ctx.CALL(oprel32) + ctx.CBW() + ctx.CDQ() + ctx.CDQE() + ctx.CLC() + ctx.CLD() + ctx.CLFLUSH(opm8) + ctx.CLFLUSHOPT(opm8) + ctx.CMC() + ctx.CMOVLCC(opm32, opr32) + ctx.CMOVLCS(opm32, opr32) + ctx.CMOVLEQ(opm32, opr32) + ctx.CMOVLGE(opm32, opr32) + ctx.CMOVLGT(opm32, opr32) + ctx.CMOVLHI(opm32, opr32) + ctx.CMOVLLE(opm32, opr32) + ctx.CMOVLLS(opm32, opr32) + ctx.CMOVLLT(opm32, opr32) + ctx.CMOVLMI(opm32, opr32) + ctx.CMOVLNE(opm32, opr32) + ctx.CMOVLOC(opm32, opr32) + ctx.CMOVLOS(opm32, opr32) + ctx.CMOVLPC(opm32, opr32) + ctx.CMOVLPL(opm32, opr32) + ctx.CMOVLPS(opm32, opr32) + ctx.CMOVQCC(opm64, opr64) + ctx.CMOVQCS(opm64, opr64) + ctx.CMOVQEQ(opm64, opr64) + ctx.CMOVQGE(opm64, opr64) + ctx.CMOVQGT(opm64, opr64) + ctx.CMOVQHI(opm64, opr64) + ctx.CMOVQLE(opm64, opr64) + ctx.CMOVQLS(opm64, opr64) + ctx.CMOVQLT(opm64, opr64) + ctx.CMOVQMI(opm64, opr64) + ctx.CMOVQNE(opm64, opr64) + ctx.CMOVQOC(opm64, opr64) + ctx.CMOVQOS(opm64, opr64) + ctx.CMOVQPC(opm64, opr64) + ctx.CMOVQPL(opm64, opr64) + ctx.CMOVQPS(opm64, opr64) + ctx.CMOVWCC(opm16, opr16) + ctx.CMOVWCS(opm16, opr16) + ctx.CMOVWEQ(opm16, opr16) + ctx.CMOVWGE(opm16, opr16) + ctx.CMOVWGT(opm16, opr16) + ctx.CMOVWHI(opm16, opr16) + ctx.CMOVWLE(opm16, opr16) + ctx.CMOVWLS(opm16, opr16) + ctx.CMOVWLT(opm16, opr16) + ctx.CMOVWMI(opm16, opr16) + ctx.CMOVWNE(opm16, opr16) + ctx.CMOVWOC(opm16, opr16) + ctx.CMOVWOS(opm16, opr16) + ctx.CMOVWPC(opm16, opr16) + ctx.CMOVWPL(opm16, opr16) + ctx.CMOVWPS(opm16, opr16) + ctx.CMPB(opal, opimm8) + ctx.CMPL(opeax, opimm32) + ctx.CMPPD(opm128, opxmm, opimm8) + ctx.CMPPS(opm128, opxmm, opimm8) + ctx.CMPQ(opm64, opimm32) + ctx.CMPSD(opm64, opxmm, opimm8) + ctx.CMPSS(opm32, opxmm, opimm8) + ctx.CMPW(opax, opimm16) + ctx.CMPXCHG16B(opm128) + ctx.CMPXCHG8B(opm64) + ctx.CMPXCHGB(opr8, opm8) + ctx.CMPXCHGL(opr32, opm32) + ctx.CMPXCHGQ(opr64, opm64) + ctx.CMPXCHGW(opr16, opm16) + ctx.COMISD(opm64, opxmm) + ctx.COMISS(opm32, opxmm) + ctx.CPUID() + ctx.CQO() + ctx.CRC32B(opm8, opr32) + ctx.CRC32L(opm32, opr32) + ctx.CRC32Q(opm64, opr64) + ctx.CRC32W(opm16, opr32) + ctx.CVTPD2PL(opm128, opxmm) + ctx.CVTPD2PS(opm128, opxmm) + ctx.CVTPL2PD(opm64, opxmm) + ctx.CVTPL2PS(opm128, opxmm) + ctx.CVTPS2PD(opm64, opxmm) + ctx.CVTPS2PL(opm128, opxmm) + ctx.CVTSD2SL(opm64, opr32) + ctx.CVTSD2SS(opm64, opxmm) + ctx.CVTSL2SD(opm32, opxmm) + ctx.CVTSL2SS(opm32, opxmm) + ctx.CVTSQ2SD(opm64, opxmm) + ctx.CVTSQ2SS(opm64, opxmm) + ctx.CVTSS2SD(opm32, opxmm) + ctx.CVTSS2SL(opm32, opr32) + ctx.CVTTPD2PL(opm128, opxmm) + ctx.CVTTPS2PL(opm128, opxmm) + ctx.CVTTSD2SL(opm64, opr32) + ctx.CVTTSD2SQ(opm64, opr64) + ctx.CVTTSS2SL(opm32, opr32) + ctx.CWD() + ctx.CWDE() + ctx.DECB(opm8) + ctx.DECL(opm32) + ctx.DECQ(opm64) + ctx.DECW(opm16) + ctx.DIVB(opm8) + ctx.DIVL(opm32) + ctx.DIVPD(opm128, opxmm) + ctx.DIVPS(opm128, opxmm) + ctx.DIVQ(opm64) + ctx.DIVSD(opm64, opxmm) + ctx.DIVSS(opm32, opxmm) + ctx.DIVW(opm16) + ctx.DPPD(opimm8, opm128, opxmm) + ctx.DPPS(opimm8, opm128, opxmm) + ctx.EXTRACTPS(opimm2u, opxmm, opm32) + ctx.HADDPD(opm128, opxmm) + ctx.HADDPS(opm128, opxmm) + ctx.HSUBPD(opm128, opxmm) + ctx.HSUBPS(opm128, opxmm) + ctx.IDIVB(opm8) + ctx.IDIVL(opm32) + ctx.IDIVQ(opm64) + ctx.IDIVW(opm16) + ctx.IMUL3L(opimm32, opm32, opr32) + ctx.IMUL3Q(opimm32, opm64, opr64) + ctx.IMUL3W(opimm16, opm16, opr16) + ctx.IMULB(opm8) + ctx.IMULL(opm32, opr32) + ctx.IMULQ(opm64, opr64) + ctx.IMULW(opm16, opr16) + ctx.INCB(opm8) + ctx.INCL(opm32) + ctx.INCQ(opm64) + ctx.INCW(opm16) + ctx.INSERTPS(opimm8, opm32, opxmm) + ctx.INT(op3) + ctx.JA(oprel32) + ctx.JAE(oprel32) + ctx.JB(oprel32) + ctx.JBE(oprel32) + ctx.JC(oprel32) + ctx.JCC(oprel32) + ctx.JCS(oprel32) + ctx.JCXZL(oprel8) + ctx.JCXZQ(oprel8) + ctx.JE(oprel32) + ctx.JEQ(oprel32) + ctx.JG(oprel32) + ctx.JGE(oprel32) + ctx.JGT(oprel32) + ctx.JHI(oprel32) + ctx.JHS(oprel32) + ctx.JL(oprel32) + ctx.JLE(oprel32) + ctx.JLO(oprel32) + ctx.JLS(oprel32) + ctx.JLT(oprel32) + ctx.JMI(oprel32) + ctx.JMP(oprel32) + ctx.JNA(oprel32) + ctx.JNAE(oprel32) + ctx.JNB(oprel32) + ctx.JNBE(oprel32) + ctx.JNC(oprel32) + ctx.JNE(oprel32) + ctx.JNG(oprel32) + ctx.JNGE(oprel32) + ctx.JNL(oprel32) + ctx.JNLE(oprel32) + ctx.JNO(oprel32) + ctx.JNP(oprel32) + ctx.JNS(oprel32) + ctx.JNZ(oprel32) + ctx.JO(oprel32) + ctx.JOC(oprel32) + ctx.JOS(oprel32) + ctx.JP(oprel32) + ctx.JPC(oprel32) + ctx.JPE(oprel32) + ctx.JPL(oprel32) + ctx.JPO(oprel32) + ctx.JPS(oprel32) + ctx.JS(oprel32) + ctx.JZ(oprel32) + ctx.KADDB(opk, opk, opk) + ctx.KADDD(opk, opk, opk) + ctx.KADDQ(opk, opk, opk) + ctx.KADDW(opk, opk, opk) + ctx.KANDB(opk, opk, opk) + ctx.KANDD(opk, opk, opk) + ctx.KANDNB(opk, opk, opk) + ctx.KANDND(opk, opk, opk) + ctx.KANDNQ(opk, opk, opk) + ctx.KANDNW(opk, opk, opk) + ctx.KANDQ(opk, opk, opk) + ctx.KANDW(opk, opk, opk) + ctx.KMOVB(opk, opk) + ctx.KMOVD(opk, opk) + ctx.KMOVQ(opk, opk) + ctx.KMOVW(opk, opk) + ctx.KNOTB(opk, opk) + ctx.KNOTD(opk, opk) + ctx.KNOTQ(opk, opk) + ctx.KNOTW(opk, opk) + ctx.KORB(opk, opk, opk) + ctx.KORD(opk, opk, opk) + ctx.KORQ(opk, opk, opk) + ctx.KORTESTB(opk, opk) + ctx.KORTESTD(opk, opk) + ctx.KORTESTQ(opk, opk) + ctx.KORTESTW(opk, opk) + ctx.KORW(opk, opk, opk) + ctx.KSHIFTLB(opimm8, opk, opk) + ctx.KSHIFTLD(opimm8, opk, opk) + ctx.KSHIFTLQ(opimm8, opk, opk) + ctx.KSHIFTLW(opimm8, opk, opk) + ctx.KSHIFTRB(opimm8, opk, opk) + ctx.KSHIFTRD(opimm8, opk, opk) + ctx.KSHIFTRQ(opimm8, opk, opk) + ctx.KSHIFTRW(opimm8, opk, opk) + ctx.KTESTB(opk, opk) + ctx.KTESTD(opk, opk) + ctx.KTESTQ(opk, opk) + ctx.KTESTW(opk, opk) + ctx.KUNPCKBW(opk, opk, opk) + ctx.KUNPCKDQ(opk, opk, opk) + ctx.KUNPCKWD(opk, opk, opk) + ctx.KXNORB(opk, opk, opk) + ctx.KXNORD(opk, opk, opk) + ctx.KXNORQ(opk, opk, opk) + ctx.KXNORW(opk, opk, opk) + ctx.KXORB(opk, opk, opk) + ctx.KXORD(opk, opk, opk) + ctx.KXORQ(opk, opk, opk) + ctx.KXORW(opk, opk, opk) + ctx.LDDQU(opm128, opxmm) + ctx.LDMXCSR(opm32) + ctx.LEAL(opm, opr32) + ctx.LEAQ(opm, opr64) + ctx.LEAW(opm, opr16) + ctx.LFENCE() + ctx.LZCNTL(opm32, opr32) + ctx.LZCNTQ(opm64, opr64) + ctx.LZCNTW(opm16, opr16) + ctx.MASKMOVDQU(opxmm, opxmm) + ctx.MASKMOVOU(opxmm, opxmm) + ctx.MAXPD(opm128, opxmm) + ctx.MAXPS(opm128, opxmm) + ctx.MAXSD(opm64, opxmm) + ctx.MAXSS(opm32, opxmm) + ctx.MFENCE() + ctx.MINPD(opm128, opxmm) + ctx.MINPS(opm128, opxmm) + ctx.MINSD(opm64, opxmm) + ctx.MINSS(opm32, opxmm) + ctx.MONITOR() + ctx.MOVAPD(opm128, opxmm) + ctx.MOVAPS(opm128, opxmm) + ctx.MOVB(opimm8, opm8) + ctx.MOVBELL(opm32, opr32) + ctx.MOVBEQQ(opm64, opr64) + ctx.MOVBEWW(opm16, opr16) + ctx.MOVBLSX(opm8, opr32) + ctx.MOVBLZX(opm8, opr32) + ctx.MOVBQSX(opm8, opr64) + ctx.MOVBQZX(opm8, opr64) + ctx.MOVBWSX(opm8, opr16) + ctx.MOVBWZX(opm8, opr16) + ctx.MOVD(opm32, opxmm) + ctx.MOVDDUP(opm64, opxmm) + ctx.MOVDQ2Q(opm32, opxmm) + ctx.MOVHLPS(opxmm, opxmm) + ctx.MOVHPD(opm64, opxmm) + ctx.MOVHPS(opm64, opxmm) + ctx.MOVL(opimm32, opm32) + ctx.MOVLHPS(opxmm, opxmm) + ctx.MOVLPD(opm64, opxmm) + ctx.MOVLPS(opm64, opxmm) + ctx.MOVLQSX(opm32, opr64) + ctx.MOVLQZX(opm32, opr64) + ctx.MOVMSKPD(opxmm, opr32) + ctx.MOVMSKPS(opxmm, opr32) + ctx.MOVNTDQ(opxmm, opm128) + ctx.MOVNTDQA(opm128, opxmm) + ctx.MOVNTIL(opr32, opm32) + ctx.MOVNTIQ(opr64, opm64) + ctx.MOVNTO(opxmm, opm128) + ctx.MOVNTPD(opxmm, opm128) + ctx.MOVNTPS(opxmm, opm128) + ctx.MOVO(opm128, opxmm) + ctx.MOVOA(opm128, opxmm) + ctx.MOVOU(opm128, opxmm) + ctx.MOVQ(opm32, opxmm) + ctx.MOVSD(opm64, opxmm) + ctx.MOVSHDUP(opm128, opxmm) + ctx.MOVSLDUP(opm128, opxmm) + ctx.MOVSS(opm32, opxmm) + ctx.MOVUPD(opm128, opxmm) + ctx.MOVUPS(opm128, opxmm) + ctx.MOVW(opimm16, opm16) + ctx.MOVWLSX(opm16, opr32) + ctx.MOVWLZX(opm16, opr32) + ctx.MOVWQSX(opm16, opr64) + ctx.MOVWQZX(opm16, opr64) + ctx.MPSADBW(opimm8, opm128, opxmm) + ctx.MULB(opm8) + ctx.MULL(opm32) + ctx.MULPD(opm128, opxmm) + ctx.MULPS(opm128, opxmm) + ctx.MULQ(opm64) + ctx.MULSD(opm64, opxmm) + ctx.MULSS(opm32, opxmm) + ctx.MULW(opm16) + ctx.MULXL(opm32, opr32, opr32) + ctx.MULXQ(opm64, opr64, opr64) + ctx.MWAIT() + ctx.NEGB(opm8) + ctx.NEGL(opm32) + ctx.NEGQ(opm64) + ctx.NEGW(opm16) + ctx.NOP() + ctx.NOTB(opm8) + ctx.NOTL(opm32) + ctx.NOTQ(opm64) + ctx.NOTW(opm16) + ctx.ORB(opimm8, opal) + ctx.ORL(opimm32, opeax) + ctx.ORPD(opm128, opxmm) + ctx.ORPS(opm128, opxmm) + ctx.ORQ(opimm32, opm64) + ctx.ORW(opimm16, opax) + ctx.PABSB(opm128, opxmm) + ctx.PABSD(opm128, opxmm) + ctx.PABSW(opm128, opxmm) + ctx.PACKSSLW(opm128, opxmm) + ctx.PACKSSWB(opm128, opxmm) + ctx.PACKUSDW(opm128, opxmm) + ctx.PACKUSWB(opm128, opxmm) + ctx.PADDB(opm128, opxmm) + ctx.PADDD(opm128, opxmm) + ctx.PADDL(opm128, opxmm) + ctx.PADDQ(opm128, opxmm) + ctx.PADDSB(opm128, opxmm) + ctx.PADDSW(opm128, opxmm) + ctx.PADDUSB(opm128, opxmm) + ctx.PADDUSW(opm128, opxmm) + ctx.PADDW(opm128, opxmm) + ctx.PALIGNR(opimm8, opm128, opxmm) + ctx.PAND(opm128, opxmm) + ctx.PANDN(opm128, opxmm) + ctx.PAUSE() + ctx.PAVGB(opm128, opxmm) + ctx.PAVGW(opm128, opxmm) + ctx.PBLENDVB(opxmm0, opm128, opxmm) + ctx.PBLENDW(opimm8, opm128, opxmm) + ctx.PCLMULQDQ(opimm8, opm128, opxmm) + ctx.PCMPEQB(opm128, opxmm) + ctx.PCMPEQL(opm128, opxmm) + ctx.PCMPEQQ(opm128, opxmm) + ctx.PCMPEQW(opm128, opxmm) + ctx.PCMPESTRI(opimm8, opm128, opxmm) + ctx.PCMPESTRM(opimm8, opm128, opxmm) + ctx.PCMPGTB(opm128, opxmm) + ctx.PCMPGTL(opm128, opxmm) + ctx.PCMPGTQ(opm128, opxmm) + ctx.PCMPGTW(opm128, opxmm) + ctx.PCMPISTRI(opimm8, opm128, opxmm) + ctx.PCMPISTRM(opimm8, opm128, opxmm) + ctx.PDEPL(opm32, opr32, opr32) + ctx.PDEPQ(opm64, opr64, opr64) + ctx.PEXTL(opm32, opr32, opr32) + ctx.PEXTQ(opm64, opr64, opr64) + ctx.PEXTRB(opimm8, opxmm, opm8) + ctx.PEXTRD(opimm8, opxmm, opm32) + ctx.PEXTRQ(opimm8, opxmm, opm64) + ctx.PEXTRW(opimm8, opxmm, opm16) + ctx.PHADDD(opm128, opxmm) + ctx.PHADDSW(opm128, opxmm) + ctx.PHADDW(opm128, opxmm) + ctx.PHMINPOSUW(opm128, opxmm) + ctx.PHSUBD(opm128, opxmm) + ctx.PHSUBSW(opm128, opxmm) + ctx.PHSUBW(opm128, opxmm) + ctx.PINSRB(opimm8, opm8, opxmm) + ctx.PINSRD(opimm8, opm32, opxmm) + ctx.PINSRQ(opimm8, opm64, opxmm) + ctx.PINSRW(opimm8, opm16, opxmm) + ctx.PMADDUBSW(opm128, opxmm) + ctx.PMADDWL(opm128, opxmm) + ctx.PMAXSB(opm128, opxmm) + ctx.PMAXSD(opm128, opxmm) + ctx.PMAXSW(opm128, opxmm) + ctx.PMAXUB(opm128, opxmm) + ctx.PMAXUD(opm128, opxmm) + ctx.PMAXUW(opm128, opxmm) + ctx.PMINSB(opm128, opxmm) + ctx.PMINSD(opm128, opxmm) + ctx.PMINSW(opm128, opxmm) + ctx.PMINUB(opm128, opxmm) + ctx.PMINUD(opm128, opxmm) + ctx.PMINUW(opm128, opxmm) + ctx.PMOVMSKB(opxmm, opr32) + ctx.PMOVSXBD(opm32, opxmm) + ctx.PMOVSXBQ(opm16, opxmm) + ctx.PMOVSXBW(opm64, opxmm) + ctx.PMOVSXDQ(opm64, opxmm) + ctx.PMOVSXWD(opm64, opxmm) + ctx.PMOVSXWQ(opm32, opxmm) + ctx.PMOVZXBD(opm32, opxmm) + ctx.PMOVZXBQ(opm16, opxmm) + ctx.PMOVZXBW(opm64, opxmm) + ctx.PMOVZXDQ(opm64, opxmm) + ctx.PMOVZXWD(opm64, opxmm) + ctx.PMOVZXWQ(opm32, opxmm) + ctx.PMULDQ(opm128, opxmm) + ctx.PMULHRSW(opm128, opxmm) + ctx.PMULHUW(opm128, opxmm) + ctx.PMULHW(opm128, opxmm) + ctx.PMULLD(opm128, opxmm) + ctx.PMULLW(opm128, opxmm) + ctx.PMULULQ(opm128, opxmm) + ctx.POPCNTL(opm32, opr32) + ctx.POPCNTQ(opm64, opr64) + ctx.POPCNTW(opm16, opr16) + ctx.POPQ(opm64) + ctx.POPW(opm16) + ctx.POR(opm128, opxmm) + ctx.PREFETCHNTA(opm8) + ctx.PREFETCHT0(opm8) + ctx.PREFETCHT1(opm8) + ctx.PREFETCHT2(opm8) + ctx.PSADBW(opm128, opxmm) + ctx.PSHUFB(opm128, opxmm) + ctx.PSHUFD(opimm8, opm128, opxmm) + ctx.PSHUFHW(opimm8, opm128, opxmm) + ctx.PSHUFL(opimm8, opm128, opxmm) + ctx.PSHUFLW(opimm8, opm128, opxmm) + ctx.PSIGNB(opm128, opxmm) + ctx.PSIGND(opm128, opxmm) + ctx.PSIGNW(opm128, opxmm) + ctx.PSLLDQ(opimm8, opxmm) + ctx.PSLLL(opimm8, opxmm) + ctx.PSLLO(opimm8, opxmm) + ctx.PSLLQ(opimm8, opxmm) + ctx.PSLLW(opimm8, opxmm) + ctx.PSRAL(opimm8, opxmm) + ctx.PSRAW(opimm8, opxmm) + ctx.PSRLDQ(opimm8, opxmm) + ctx.PSRLL(opimm8, opxmm) + ctx.PSRLO(opimm8, opxmm) + ctx.PSRLQ(opimm8, opxmm) + ctx.PSRLW(opimm8, opxmm) + ctx.PSUBB(opm128, opxmm) + ctx.PSUBL(opm128, opxmm) + ctx.PSUBQ(opm128, opxmm) + ctx.PSUBSB(opm128, opxmm) + ctx.PSUBSW(opm128, opxmm) + ctx.PSUBUSB(opm128, opxmm) + ctx.PSUBUSW(opm128, opxmm) + ctx.PSUBW(opm128, opxmm) + ctx.PTEST(opm128, opxmm) + ctx.PUNPCKHBW(opm128, opxmm) + ctx.PUNPCKHLQ(opm128, opxmm) + ctx.PUNPCKHQDQ(opm128, opxmm) + ctx.PUNPCKHWL(opm128, opxmm) + ctx.PUNPCKLBW(opm128, opxmm) + ctx.PUNPCKLLQ(opm128, opxmm) + ctx.PUNPCKLQDQ(opm128, opxmm) + ctx.PUNPCKLWL(opm128, opxmm) + ctx.PUSHQ(opimm32) + ctx.PUSHW(opm16) + ctx.PXOR(opm128, opxmm) + ctx.RCLB(op1, opm8) + ctx.RCLL(op1, opm32) + ctx.RCLQ(op1, opm64) + ctx.RCLW(op1, opm16) + ctx.RCPPS(opm128, opxmm) + ctx.RCPSS(opm32, opxmm) + ctx.RCRB(op1, opm8) + ctx.RCRL(op1, opm32) + ctx.RCRQ(op1, opm64) + ctx.RCRW(op1, opm16) + ctx.RDRANDL(opr16) + ctx.RDSEEDL(opr16) + ctx.RDTSC() + ctx.RDTSCP() + ctx.RET() + ctx.RETFL(opimm16) + ctx.RETFQ(opimm16) + ctx.RETFW(opimm16) + ctx.ROLB(op1, opm8) + ctx.ROLL(op1, opm32) + ctx.ROLQ(op1, opm64) + ctx.ROLW(op1, opm16) + ctx.RORB(op1, opm8) + ctx.RORL(op1, opm32) + ctx.RORQ(op1, opm64) + ctx.RORW(op1, opm16) + ctx.RORXL(opimm8, opm32, opr32) + ctx.RORXQ(opimm8, opm64, opr64) + ctx.ROUNDPD(opimm8, opm128, opxmm) + ctx.ROUNDPS(opimm8, opm128, opxmm) + ctx.ROUNDSD(opimm8, opm64, opxmm) + ctx.ROUNDSS(opimm8, opm32, opxmm) + ctx.RSQRTPS(opm128, opxmm) + ctx.RSQRTSS(opm32, opxmm) + ctx.SALB(op1, opm8) + ctx.SALL(op1, opm32) + ctx.SALQ(op1, opm64) + ctx.SALW(op1, opm16) + ctx.SARB(op1, opm8) + ctx.SARL(op1, opm32) + ctx.SARQ(op1, opm64) + ctx.SARW(op1, opm16) + ctx.SARXL(opr32, opm32, opr32) + ctx.SARXQ(opr64, opm64, opr64) + ctx.SBBB(opimm8, opal) + ctx.SBBL(opimm32, opeax) + ctx.SBBQ(opimm32, opm64) + ctx.SBBW(opimm16, opax) + ctx.SETCC(opm8) + ctx.SETCS(opm8) + ctx.SETEQ(opm8) + ctx.SETGE(opm8) + ctx.SETGT(opm8) + ctx.SETHI(opm8) + ctx.SETLE(opm8) + ctx.SETLS(opm8) + ctx.SETLT(opm8) + ctx.SETMI(opm8) + ctx.SETNE(opm8) + ctx.SETOC(opm8) + ctx.SETOS(opm8) + ctx.SETPC(opm8) + ctx.SETPL(opm8) + ctx.SETPS(opm8) + ctx.SFENCE() + ctx.SHA1MSG1(opm128, opxmm) + ctx.SHA1MSG2(opm128, opxmm) + ctx.SHA1NEXTE(opm128, opxmm) + ctx.SHA1RNDS4(opimm2u, opm128, opxmm) + ctx.SHA256MSG1(opm128, opxmm) + ctx.SHA256MSG2(opm128, opxmm) + ctx.SHA256RNDS2(opxmm0, opm128, opxmm) + ctx.SHLB(op1, opm8) + ctx.SHLL(op1, opm32) + ctx.SHLQ(op1, opm64) + ctx.SHLW(op1, opm16) + ctx.SHLXL(opr32, opm32, opr32) + ctx.SHLXQ(opr64, opm64, opr64) + ctx.SHRB(op1, opm8) + ctx.SHRL(op1, opm32) + ctx.SHRQ(op1, opm64) + ctx.SHRW(op1, opm16) + ctx.SHRXL(opr32, opm32, opr32) + ctx.SHRXQ(opr64, opm64, opr64) + ctx.SHUFPD(opimm8, opm128, opxmm) + ctx.SHUFPS(opimm8, opm128, opxmm) + ctx.SQRTPD(opm128, opxmm) + ctx.SQRTPS(opm128, opxmm) + ctx.SQRTSD(opm64, opxmm) + ctx.SQRTSS(opm32, opxmm) + ctx.STC() + ctx.STD() + ctx.STMXCSR(opm32) + ctx.SUBB(opimm8, opal) + ctx.SUBL(opimm32, opeax) + ctx.SUBPD(opm128, opxmm) + ctx.SUBPS(opm128, opxmm) + ctx.SUBQ(opimm32, opm64) + ctx.SUBSD(opm64, opxmm) + ctx.SUBSS(opm32, opxmm) + ctx.SUBW(opimm16, opax) + ctx.SYSCALL() + ctx.TESTB(opimm8, opal) + ctx.TESTL(opimm32, opeax) + ctx.TESTQ(opimm32, opm64) + ctx.TESTW(opimm16, opax) + ctx.TZCNTL(opm32, opr32) + ctx.TZCNTQ(opm64, opr64) + ctx.TZCNTW(opm16, opr16) + ctx.UCOMISD(opm64, opxmm) + ctx.UCOMISS(opm32, opxmm) + ctx.UD2() + ctx.UNPCKHPD(opm128, opxmm) + ctx.UNPCKHPS(opm128, opxmm) + ctx.UNPCKLPD(opm128, opxmm) + ctx.UNPCKLPS(opm128, opxmm) + ctx.VADDPD(opm128, opxmm, opxmm) + ctx.VADDPD_BCST(opm64, opxmm, opk, opxmm) + ctx.VADDPD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VADDPD_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VADDPD_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VADDPD_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VADDPD_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VADDPD_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VADDPD_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VADDPD_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VADDPD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VADDPD_Z(opm128, opxmm, opk, opxmm) + ctx.VADDPS(opm128, opxmm, opxmm) + ctx.VADDPS_BCST(opm32, opxmm, opk, opxmm) + ctx.VADDPS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VADDPS_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VADDPS_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VADDPS_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VADDPS_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VADDPS_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VADDPS_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VADDPS_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VADDPS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VADDPS_Z(opm128, opxmm, opk, opxmm) + ctx.VADDSD(opm64, opxmm, opxmm) + ctx.VADDSD_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VADDSD_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VADDSD_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VADDSD_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VADDSD_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VADDSD_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VADDSD_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VADDSD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VADDSD_Z(opm64, opxmm, opk, opxmm) + ctx.VADDSS(opm32, opxmm, opxmm) + ctx.VADDSS_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VADDSS_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VADDSS_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VADDSS_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VADDSS_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VADDSS_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VADDSS_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VADDSS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VADDSS_Z(opm32, opxmm, opk, opxmm) + ctx.VADDSUBPD(opm128, opxmm, opxmm) + ctx.VADDSUBPS(opm128, opxmm, opxmm) + ctx.VAESDEC(opm128, opxmm, opxmm) + ctx.VAESDECLAST(opm128, opxmm, opxmm) + ctx.VAESENC(opm128, opxmm, opxmm) + ctx.VAESENCLAST(opm128, opxmm, opxmm) + ctx.VAESIMC(opm128, opxmm) + ctx.VAESKEYGENASSIST(opimm8, opm128, opxmm) + ctx.VALIGND(opimm8, opm128, opxmm, opk, opxmm) + ctx.VALIGND_BCST(opimm8, opm32, opxmm, opk, opxmm) + ctx.VALIGND_BCST_Z(opimm8, opm32, opxmm, opk, opxmm) + ctx.VALIGND_Z(opimm8, opm128, opxmm, opk, opxmm) + ctx.VALIGNQ(opimm8, opm128, opxmm, opk, opxmm) + ctx.VALIGNQ_BCST(opimm8, opm64, opxmm, opk, opxmm) + ctx.VALIGNQ_BCST_Z(opimm8, opm64, opxmm, opk, opxmm) + ctx.VALIGNQ_Z(opimm8, opm128, opxmm, opk, opxmm) + ctx.VANDNPD(opm128, opxmm, opxmm) + ctx.VANDNPD_BCST(opm64, opxmm, opk, opxmm) + ctx.VANDNPD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VANDNPD_Z(opm128, opxmm, opk, opxmm) + ctx.VANDNPS(opm128, opxmm, opxmm) + ctx.VANDNPS_BCST(opm32, opxmm, opk, opxmm) + ctx.VANDNPS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VANDNPS_Z(opm128, opxmm, opk, opxmm) + ctx.VANDPD(opm128, opxmm, opxmm) + ctx.VANDPD_BCST(opm64, opxmm, opk, opxmm) + ctx.VANDPD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VANDPD_Z(opm128, opxmm, opk, opxmm) + ctx.VANDPS(opm128, opxmm, opxmm) + ctx.VANDPS_BCST(opm32, opxmm, opk, opxmm) + ctx.VANDPS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VANDPS_Z(opm128, opxmm, opk, opxmm) + ctx.VBLENDMPD(opm128, opxmm, opk, opxmm) + ctx.VBLENDMPD_BCST(opm64, opxmm, opk, opxmm) + ctx.VBLENDMPD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VBLENDMPD_Z(opm128, opxmm, opk, opxmm) + ctx.VBLENDMPS(opm128, opxmm, opk, opxmm) + ctx.VBLENDMPS_BCST(opm32, opxmm, opk, opxmm) + ctx.VBLENDMPS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VBLENDMPS_Z(opm128, opxmm, opk, opxmm) + ctx.VBLENDPD(opimm8, opm128, opxmm, opxmm) + ctx.VBLENDPS(opimm8, opm128, opxmm, opxmm) + ctx.VBLENDVPD(opxmm, opm128, opxmm, opxmm) + ctx.VBLENDVPS(opxmm, opm128, opxmm, opxmm) + ctx.VBROADCASTF128(opm128, opymm) + ctx.VBROADCASTF32X2(opm64, opk, opymm) + ctx.VBROADCASTF32X2_Z(opm64, opk, opymm) + ctx.VBROADCASTF32X4(opm128, opk, opymm) + ctx.VBROADCASTF32X4_Z(opm128, opk, opymm) + ctx.VBROADCASTF32X8(opm256, opk, opzmm) + ctx.VBROADCASTF32X8_Z(opm256, opk, opzmm) + ctx.VBROADCASTF64X2(opm128, opk, opymm) + ctx.VBROADCASTF64X2_Z(opm128, opk, opymm) + ctx.VBROADCASTF64X4(opm256, opk, opzmm) + ctx.VBROADCASTF64X4_Z(opm256, opk, opzmm) + ctx.VBROADCASTI128(opm128, opymm) + ctx.VBROADCASTI32X2(opm64, opk, opxmm) + ctx.VBROADCASTI32X2_Z(opm64, opk, opxmm) + ctx.VBROADCASTI32X4(opm128, opk, opymm) + ctx.VBROADCASTI32X4_Z(opm128, opk, opymm) + ctx.VBROADCASTI32X8(opm256, opk, opzmm) + ctx.VBROADCASTI32X8_Z(opm256, opk, opzmm) + ctx.VBROADCASTI64X2(opm128, opk, opymm) + ctx.VBROADCASTI64X2_Z(opm128, opk, opymm) + ctx.VBROADCASTI64X4(opm256, opk, opzmm) + ctx.VBROADCASTI64X4_Z(opm256, opk, opzmm) + ctx.VBROADCASTSD(opxmm, opymm) + ctx.VBROADCASTSD_Z(opm64, opk, opymm) + ctx.VBROADCASTSS(opxmm, opxmm) + ctx.VBROADCASTSS_Z(opm32, opk, opymm) + ctx.VCMPPD(opimm8, opm128, opxmm, opxmm) + ctx.VCMPPD_BCST(opimm8, opm64, opxmm, opk, opk) + ctx.VCMPPD_SAE(opimm8, opzmm, opzmm, opk, opk) + ctx.VCMPPS(opimm8, opm128, opxmm, opxmm) + ctx.VCMPPS_BCST(opimm8, opm32, opxmm, opk, opk) + ctx.VCMPPS_SAE(opimm8, opzmm, opzmm, opk, opk) + ctx.VCMPSD(opimm8, opm64, opxmm, opxmm) + ctx.VCMPSD_SAE(opimm8, opxmm, opxmm, opk, opk) + ctx.VCMPSS(opimm8, opm32, opxmm, opxmm) + ctx.VCMPSS_SAE(opimm8, opxmm, opxmm, opk, opk) + ctx.VCOMISD(opm64, opxmm) + ctx.VCOMISD_SAE(opxmm, opxmm) + ctx.VCOMISS(opm32, opxmm) + ctx.VCOMISS_SAE(opxmm, opxmm) + ctx.VCOMPRESSPD(opxmm, opk, opm128) + ctx.VCOMPRESSPD_Z(opxmm, opk, opm128) + ctx.VCOMPRESSPS(opxmm, opk, opm128) + ctx.VCOMPRESSPS_Z(opxmm, opk, opm128) + ctx.VCVTDQ2PD(opm128, opymm) + ctx.VCVTDQ2PD_BCST(opm32, opk, opxmm) + ctx.VCVTDQ2PD_BCST_Z(opm32, opk, opxmm) + ctx.VCVTDQ2PD_Z(opm128, opk, opymm) + ctx.VCVTDQ2PS(opm128, opxmm) + ctx.VCVTDQ2PS_BCST(opm32, opk, opxmm) + ctx.VCVTDQ2PS_BCST_Z(opm32, opk, opxmm) + ctx.VCVTDQ2PS_RD_SAE(opzmm, opk, opzmm) + ctx.VCVTDQ2PS_RD_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTDQ2PS_RN_SAE(opzmm, opk, opzmm) + ctx.VCVTDQ2PS_RN_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTDQ2PS_RU_SAE(opzmm, opk, opzmm) + ctx.VCVTDQ2PS_RU_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTDQ2PS_RZ_SAE(opzmm, opk, opzmm) + ctx.VCVTDQ2PS_RZ_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTDQ2PS_Z(opm128, opk, opxmm) + ctx.VCVTPD2DQ(opm512, opk, opymm) + ctx.VCVTPD2DQX(opm128, opxmm) + ctx.VCVTPD2DQX_BCST(opm64, opk, opxmm) + ctx.VCVTPD2DQX_BCST_Z(opm64, opk, opxmm) + ctx.VCVTPD2DQX_Z(opm128, opk, opxmm) + ctx.VCVTPD2DQY(opm256, opxmm) + ctx.VCVTPD2DQY_BCST(opm64, opk, opxmm) + ctx.VCVTPD2DQY_BCST_Z(opm64, opk, opxmm) + ctx.VCVTPD2DQY_Z(opm256, opk, opxmm) + ctx.VCVTPD2DQ_BCST(opm64, opk, opymm) + ctx.VCVTPD2DQ_BCST_Z(opm64, opk, opymm) + ctx.VCVTPD2DQ_RD_SAE(opzmm, opk, opymm) + ctx.VCVTPD2DQ_RD_SAE_Z(opzmm, opk, opymm) + ctx.VCVTPD2DQ_RN_SAE(opzmm, opk, opymm) + ctx.VCVTPD2DQ_RN_SAE_Z(opzmm, opk, opymm) + ctx.VCVTPD2DQ_RU_SAE(opzmm, opk, opymm) + ctx.VCVTPD2DQ_RU_SAE_Z(opzmm, opk, opymm) + ctx.VCVTPD2DQ_RZ_SAE(opzmm, opk, opymm) + ctx.VCVTPD2DQ_RZ_SAE_Z(opzmm, opk, opymm) + ctx.VCVTPD2DQ_Z(opm512, opk, opymm) + ctx.VCVTPD2PS(opm512, opk, opymm) + ctx.VCVTPD2PSX(opm128, opxmm) + ctx.VCVTPD2PSX_BCST(opm64, opk, opxmm) + ctx.VCVTPD2PSX_BCST_Z(opm64, opk, opxmm) + ctx.VCVTPD2PSX_Z(opm128, opk, opxmm) + ctx.VCVTPD2PSY(opm256, opxmm) + ctx.VCVTPD2PSY_BCST(opm64, opk, opxmm) + ctx.VCVTPD2PSY_BCST_Z(opm64, opk, opxmm) + ctx.VCVTPD2PSY_Z(opm256, opk, opxmm) + ctx.VCVTPD2PS_BCST(opm64, opk, opymm) + ctx.VCVTPD2PS_BCST_Z(opm64, opk, opymm) + ctx.VCVTPD2PS_RD_SAE(opzmm, opk, opymm) + ctx.VCVTPD2PS_RD_SAE_Z(opzmm, opk, opymm) + ctx.VCVTPD2PS_RN_SAE(opzmm, opk, opymm) + ctx.VCVTPD2PS_RN_SAE_Z(opzmm, opk, opymm) + ctx.VCVTPD2PS_RU_SAE(opzmm, opk, opymm) + ctx.VCVTPD2PS_RU_SAE_Z(opzmm, opk, opymm) + ctx.VCVTPD2PS_RZ_SAE(opzmm, opk, opymm) + ctx.VCVTPD2PS_RZ_SAE_Z(opzmm, opk, opymm) + ctx.VCVTPD2PS_Z(opm512, opk, opymm) + ctx.VCVTPD2QQ(opm128, opk, opxmm) + ctx.VCVTPD2QQ_BCST(opm64, opk, opxmm) + ctx.VCVTPD2QQ_BCST_Z(opm64, opk, opxmm) + ctx.VCVTPD2QQ_RD_SAE(opzmm, opk, opzmm) + ctx.VCVTPD2QQ_RD_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTPD2QQ_RN_SAE(opzmm, opk, opzmm) + ctx.VCVTPD2QQ_RN_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTPD2QQ_RU_SAE(opzmm, opk, opzmm) + ctx.VCVTPD2QQ_RU_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTPD2QQ_RZ_SAE(opzmm, opk, opzmm) + ctx.VCVTPD2QQ_RZ_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTPD2QQ_Z(opm128, opk, opxmm) + ctx.VCVTPD2UDQ(opm512, opk, opymm) + ctx.VCVTPD2UDQX(opm128, opk, opxmm) + ctx.VCVTPD2UDQX_BCST(opm64, opk, opxmm) + ctx.VCVTPD2UDQX_BCST_Z(opm64, opk, opxmm) + ctx.VCVTPD2UDQX_Z(opm128, opk, opxmm) + ctx.VCVTPD2UDQY(opm256, opk, opxmm) + ctx.VCVTPD2UDQY_BCST(opm64, opk, opxmm) + ctx.VCVTPD2UDQY_BCST_Z(opm64, opk, opxmm) + ctx.VCVTPD2UDQY_Z(opm256, opk, opxmm) + ctx.VCVTPD2UDQ_BCST(opm64, opk, opymm) + ctx.VCVTPD2UDQ_BCST_Z(opm64, opk, opymm) + ctx.VCVTPD2UDQ_RD_SAE(opzmm, opk, opymm) + ctx.VCVTPD2UDQ_RD_SAE_Z(opzmm, opk, opymm) + ctx.VCVTPD2UDQ_RN_SAE(opzmm, opk, opymm) + ctx.VCVTPD2UDQ_RN_SAE_Z(opzmm, opk, opymm) + ctx.VCVTPD2UDQ_RU_SAE(opzmm, opk, opymm) + ctx.VCVTPD2UDQ_RU_SAE_Z(opzmm, opk, opymm) + ctx.VCVTPD2UDQ_RZ_SAE(opzmm, opk, opymm) + ctx.VCVTPD2UDQ_RZ_SAE_Z(opzmm, opk, opymm) + ctx.VCVTPD2UDQ_Z(opm512, opk, opymm) + ctx.VCVTPD2UQQ(opm128, opk, opxmm) + ctx.VCVTPD2UQQ_BCST(opm64, opk, opxmm) + ctx.VCVTPD2UQQ_BCST_Z(opm64, opk, opxmm) + ctx.VCVTPD2UQQ_RD_SAE(opzmm, opk, opzmm) + ctx.VCVTPD2UQQ_RD_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTPD2UQQ_RN_SAE(opzmm, opk, opzmm) + ctx.VCVTPD2UQQ_RN_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTPD2UQQ_RU_SAE(opzmm, opk, opzmm) + ctx.VCVTPD2UQQ_RU_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTPD2UQQ_RZ_SAE(opzmm, opk, opzmm) + ctx.VCVTPD2UQQ_RZ_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTPD2UQQ_Z(opm128, opk, opxmm) + ctx.VCVTPH2PS(opm128, opymm) + ctx.VCVTPH2PS_SAE(opymm, opk, opzmm) + ctx.VCVTPH2PS_SAE_Z(opymm, opk, opzmm) + ctx.VCVTPH2PS_Z(opm128, opk, opymm) + ctx.VCVTPS2DQ(opm128, opxmm) + ctx.VCVTPS2DQ_BCST(opm32, opk, opxmm) + ctx.VCVTPS2DQ_BCST_Z(opm32, opk, opxmm) + ctx.VCVTPS2DQ_RD_SAE(opzmm, opk, opzmm) + ctx.VCVTPS2DQ_RD_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTPS2DQ_RN_SAE(opzmm, opk, opzmm) + ctx.VCVTPS2DQ_RN_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTPS2DQ_RU_SAE(opzmm, opk, opzmm) + ctx.VCVTPS2DQ_RU_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTPS2DQ_RZ_SAE(opzmm, opk, opzmm) + ctx.VCVTPS2DQ_RZ_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTPS2DQ_Z(opm128, opk, opxmm) + ctx.VCVTPS2PD(opm128, opymm) + ctx.VCVTPS2PD_BCST(opm32, opk, opxmm) + ctx.VCVTPS2PD_BCST_Z(opm32, opk, opxmm) + ctx.VCVTPS2PD_SAE(opymm, opk, opzmm) + ctx.VCVTPS2PD_SAE_Z(opymm, opk, opzmm) + ctx.VCVTPS2PD_Z(opm64, opk, opxmm) + ctx.VCVTPS2PH(opimm8, opxmm, opm64) + ctx.VCVTPS2PH_SAE(opimm8, opzmm, opk, opymm) + ctx.VCVTPS2PH_SAE_Z(opimm8, opzmm, opk, opymm) + ctx.VCVTPS2PH_Z(opimm8, opxmm, opk, opm64) + ctx.VCVTPS2QQ(opm128, opk, opymm) + ctx.VCVTPS2QQ_BCST(opm32, opk, opxmm) + ctx.VCVTPS2QQ_BCST_Z(opm32, opk, opxmm) + ctx.VCVTPS2QQ_RD_SAE(opymm, opk, opzmm) + ctx.VCVTPS2QQ_RD_SAE_Z(opymm, opk, opzmm) + ctx.VCVTPS2QQ_RN_SAE(opymm, opk, opzmm) + ctx.VCVTPS2QQ_RN_SAE_Z(opymm, opk, opzmm) + ctx.VCVTPS2QQ_RU_SAE(opymm, opk, opzmm) + ctx.VCVTPS2QQ_RU_SAE_Z(opymm, opk, opzmm) + ctx.VCVTPS2QQ_RZ_SAE(opymm, opk, opzmm) + ctx.VCVTPS2QQ_RZ_SAE_Z(opymm, opk, opzmm) + ctx.VCVTPS2QQ_Z(opm128, opk, opymm) + ctx.VCVTPS2UDQ(opm128, opk, opxmm) + ctx.VCVTPS2UDQ_BCST(opm32, opk, opxmm) + ctx.VCVTPS2UDQ_BCST_Z(opm32, opk, opxmm) + ctx.VCVTPS2UDQ_RD_SAE(opzmm, opk, opzmm) + ctx.VCVTPS2UDQ_RD_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTPS2UDQ_RN_SAE(opzmm, opk, opzmm) + ctx.VCVTPS2UDQ_RN_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTPS2UDQ_RU_SAE(opzmm, opk, opzmm) + ctx.VCVTPS2UDQ_RU_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTPS2UDQ_RZ_SAE(opzmm, opk, opzmm) + ctx.VCVTPS2UDQ_RZ_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTPS2UDQ_Z(opm128, opk, opxmm) + ctx.VCVTPS2UQQ(opm128, opk, opymm) + ctx.VCVTPS2UQQ_BCST(opm32, opk, opxmm) + ctx.VCVTPS2UQQ_BCST_Z(opm32, opk, opxmm) + ctx.VCVTPS2UQQ_RD_SAE(opymm, opk, opzmm) + ctx.VCVTPS2UQQ_RD_SAE_Z(opymm, opk, opzmm) + ctx.VCVTPS2UQQ_RN_SAE(opymm, opk, opzmm) + ctx.VCVTPS2UQQ_RN_SAE_Z(opymm, opk, opzmm) + ctx.VCVTPS2UQQ_RU_SAE(opymm, opk, opzmm) + ctx.VCVTPS2UQQ_RU_SAE_Z(opymm, opk, opzmm) + ctx.VCVTPS2UQQ_RZ_SAE(opymm, opk, opzmm) + ctx.VCVTPS2UQQ_RZ_SAE_Z(opymm, opk, opzmm) + ctx.VCVTPS2UQQ_Z(opm128, opk, opymm) + ctx.VCVTQQ2PD(opm128, opk, opxmm) + ctx.VCVTQQ2PD_BCST(opm64, opk, opxmm) + ctx.VCVTQQ2PD_BCST_Z(opm64, opk, opxmm) + ctx.VCVTQQ2PD_RD_SAE(opzmm, opk, opzmm) + ctx.VCVTQQ2PD_RD_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTQQ2PD_RN_SAE(opzmm, opk, opzmm) + ctx.VCVTQQ2PD_RN_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTQQ2PD_RU_SAE(opzmm, opk, opzmm) + ctx.VCVTQQ2PD_RU_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTQQ2PD_RZ_SAE(opzmm, opk, opzmm) + ctx.VCVTQQ2PD_RZ_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTQQ2PD_Z(opm128, opk, opxmm) + ctx.VCVTQQ2PS(opm512, opk, opymm) + ctx.VCVTQQ2PSX(opm128, opk, opxmm) + ctx.VCVTQQ2PSX_BCST(opm64, opk, opxmm) + ctx.VCVTQQ2PSX_BCST_Z(opm64, opk, opxmm) + ctx.VCVTQQ2PSX_Z(opm128, opk, opxmm) + ctx.VCVTQQ2PSY(opm256, opk, opxmm) + ctx.VCVTQQ2PSY_BCST(opm64, opk, opxmm) + ctx.VCVTQQ2PSY_BCST_Z(opm64, opk, opxmm) + ctx.VCVTQQ2PSY_Z(opm256, opk, opxmm) + ctx.VCVTQQ2PS_BCST(opm64, opk, opymm) + ctx.VCVTQQ2PS_BCST_Z(opm64, opk, opymm) + ctx.VCVTQQ2PS_RD_SAE(opzmm, opk, opymm) + ctx.VCVTQQ2PS_RD_SAE_Z(opzmm, opk, opymm) + ctx.VCVTQQ2PS_RN_SAE(opzmm, opk, opymm) + ctx.VCVTQQ2PS_RN_SAE_Z(opzmm, opk, opymm) + ctx.VCVTQQ2PS_RU_SAE(opzmm, opk, opymm) + ctx.VCVTQQ2PS_RU_SAE_Z(opzmm, opk, opymm) + ctx.VCVTQQ2PS_RZ_SAE(opzmm, opk, opymm) + ctx.VCVTQQ2PS_RZ_SAE_Z(opzmm, opk, opymm) + ctx.VCVTQQ2PS_Z(opm512, opk, opymm) + ctx.VCVTSD2SI(opm64, opr32) + ctx.VCVTSD2SIQ(opm64, opr64) + ctx.VCVTSD2SIQ_RD_SAE(opxmm, opr64) + ctx.VCVTSD2SIQ_RN_SAE(opxmm, opr64) + ctx.VCVTSD2SIQ_RU_SAE(opxmm, opr64) + ctx.VCVTSD2SIQ_RZ_SAE(opxmm, opr64) + ctx.VCVTSD2SI_RD_SAE(opxmm, opr32) + ctx.VCVTSD2SI_RN_SAE(opxmm, opr32) + ctx.VCVTSD2SI_RU_SAE(opxmm, opr32) + ctx.VCVTSD2SI_RZ_SAE(opxmm, opr32) + ctx.VCVTSD2SS(opm64, opxmm, opxmm) + ctx.VCVTSD2SS_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VCVTSD2SS_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VCVTSD2SS_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VCVTSD2SS_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VCVTSD2SS_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VCVTSD2SS_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VCVTSD2SS_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VCVTSD2SS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VCVTSD2SS_Z(opm64, opxmm, opk, opxmm) + ctx.VCVTSD2USIL(opm64, opr32) + ctx.VCVTSD2USIL_RD_SAE(opxmm, opr32) + ctx.VCVTSD2USIL_RN_SAE(opxmm, opr32) + ctx.VCVTSD2USIL_RU_SAE(opxmm, opr32) + ctx.VCVTSD2USIL_RZ_SAE(opxmm, opr32) + ctx.VCVTSD2USIQ(opm64, opr64) + ctx.VCVTSD2USIQ_RD_SAE(opxmm, opr64) + ctx.VCVTSD2USIQ_RN_SAE(opxmm, opr64) + ctx.VCVTSD2USIQ_RU_SAE(opxmm, opr64) + ctx.VCVTSD2USIQ_RZ_SAE(opxmm, opr64) + ctx.VCVTSI2SDL(opm32, opxmm, opxmm) + ctx.VCVTSI2SDQ(opm64, opxmm, opxmm) + ctx.VCVTSI2SDQ_RD_SAE(opr64, opxmm, opxmm) + ctx.VCVTSI2SDQ_RN_SAE(opr64, opxmm, opxmm) + ctx.VCVTSI2SDQ_RU_SAE(opr64, opxmm, opxmm) + ctx.VCVTSI2SDQ_RZ_SAE(opr64, opxmm, opxmm) + ctx.VCVTSI2SSL(opm32, opxmm, opxmm) + ctx.VCVTSI2SSL_RD_SAE(opr32, opxmm, opxmm) + ctx.VCVTSI2SSL_RN_SAE(opr32, opxmm, opxmm) + ctx.VCVTSI2SSL_RU_SAE(opr32, opxmm, opxmm) + ctx.VCVTSI2SSL_RZ_SAE(opr32, opxmm, opxmm) + ctx.VCVTSI2SSQ(opm64, opxmm, opxmm) + ctx.VCVTSI2SSQ_RD_SAE(opr64, opxmm, opxmm) + ctx.VCVTSI2SSQ_RN_SAE(opr64, opxmm, opxmm) + ctx.VCVTSI2SSQ_RU_SAE(opr64, opxmm, opxmm) + ctx.VCVTSI2SSQ_RZ_SAE(opr64, opxmm, opxmm) + ctx.VCVTSS2SD(opm32, opxmm, opxmm) + ctx.VCVTSS2SD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VCVTSS2SD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VCVTSS2SD_Z(opm32, opxmm, opk, opxmm) + ctx.VCVTSS2SI(opm32, opr32) + ctx.VCVTSS2SIQ(opm32, opr64) + ctx.VCVTSS2SIQ_RD_SAE(opxmm, opr64) + ctx.VCVTSS2SIQ_RN_SAE(opxmm, opr64) + ctx.VCVTSS2SIQ_RU_SAE(opxmm, opr64) + ctx.VCVTSS2SIQ_RZ_SAE(opxmm, opr64) + ctx.VCVTSS2SI_RD_SAE(opxmm, opr32) + ctx.VCVTSS2SI_RN_SAE(opxmm, opr32) + ctx.VCVTSS2SI_RU_SAE(opxmm, opr32) + ctx.VCVTSS2SI_RZ_SAE(opxmm, opr32) + ctx.VCVTSS2USIL(opm32, opr32) + ctx.VCVTSS2USIL_RD_SAE(opxmm, opr32) + ctx.VCVTSS2USIL_RN_SAE(opxmm, opr32) + ctx.VCVTSS2USIL_RU_SAE(opxmm, opr32) + ctx.VCVTSS2USIL_RZ_SAE(opxmm, opr32) + ctx.VCVTSS2USIQ(opm32, opr64) + ctx.VCVTSS2USIQ_RD_SAE(opxmm, opr64) + ctx.VCVTSS2USIQ_RN_SAE(opxmm, opr64) + ctx.VCVTSS2USIQ_RU_SAE(opxmm, opr64) + ctx.VCVTSS2USIQ_RZ_SAE(opxmm, opr64) + ctx.VCVTTPD2DQ(opm512, opk, opymm) + ctx.VCVTTPD2DQX(opm128, opxmm) + ctx.VCVTTPD2DQX_BCST(opm64, opk, opxmm) + ctx.VCVTTPD2DQX_BCST_Z(opm64, opk, opxmm) + ctx.VCVTTPD2DQX_Z(opm128, opk, opxmm) + ctx.VCVTTPD2DQY(opm256, opxmm) + ctx.VCVTTPD2DQY_BCST(opm64, opk, opxmm) + ctx.VCVTTPD2DQY_BCST_Z(opm64, opk, opxmm) + ctx.VCVTTPD2DQY_Z(opm256, opk, opxmm) + ctx.VCVTTPD2DQ_BCST(opm64, opk, opymm) + ctx.VCVTTPD2DQ_BCST_Z(opm64, opk, opymm) + ctx.VCVTTPD2DQ_SAE(opzmm, opk, opymm) + ctx.VCVTTPD2DQ_SAE_Z(opzmm, opk, opymm) + ctx.VCVTTPD2DQ_Z(opm512, opk, opymm) + ctx.VCVTTPD2QQ(opm128, opk, opxmm) + ctx.VCVTTPD2QQ_BCST(opm64, opk, opxmm) + ctx.VCVTTPD2QQ_BCST_Z(opm64, opk, opxmm) + ctx.VCVTTPD2QQ_SAE(opzmm, opk, opzmm) + ctx.VCVTTPD2QQ_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTTPD2QQ_Z(opm128, opk, opxmm) + ctx.VCVTTPD2UDQ(opm512, opk, opymm) + ctx.VCVTTPD2UDQX(opm128, opk, opxmm) + ctx.VCVTTPD2UDQX_BCST(opm64, opk, opxmm) + ctx.VCVTTPD2UDQX_BCST_Z(opm64, opk, opxmm) + ctx.VCVTTPD2UDQX_Z(opm128, opk, opxmm) + ctx.VCVTTPD2UDQY(opm256, opk, opxmm) + ctx.VCVTTPD2UDQY_BCST(opm64, opk, opxmm) + ctx.VCVTTPD2UDQY_BCST_Z(opm64, opk, opxmm) + ctx.VCVTTPD2UDQY_Z(opm256, opk, opxmm) + ctx.VCVTTPD2UDQ_BCST(opm64, opk, opymm) + ctx.VCVTTPD2UDQ_BCST_Z(opm64, opk, opymm) + ctx.VCVTTPD2UDQ_SAE(opzmm, opk, opymm) + ctx.VCVTTPD2UDQ_SAE_Z(opzmm, opk, opymm) + ctx.VCVTTPD2UDQ_Z(opm512, opk, opymm) + ctx.VCVTTPD2UQQ(opm128, opk, opxmm) + ctx.VCVTTPD2UQQ_BCST(opm64, opk, opxmm) + ctx.VCVTTPD2UQQ_BCST_Z(opm64, opk, opxmm) + ctx.VCVTTPD2UQQ_SAE(opzmm, opk, opzmm) + ctx.VCVTTPD2UQQ_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTTPD2UQQ_Z(opm128, opk, opxmm) + ctx.VCVTTPS2DQ(opm128, opxmm) + ctx.VCVTTPS2DQ_BCST(opm32, opk, opxmm) + ctx.VCVTTPS2DQ_BCST_Z(opm32, opk, opxmm) + ctx.VCVTTPS2DQ_SAE(opzmm, opk, opzmm) + ctx.VCVTTPS2DQ_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTTPS2DQ_Z(opm128, opk, opxmm) + ctx.VCVTTPS2QQ(opm128, opk, opymm) + ctx.VCVTTPS2QQ_BCST(opm32, opk, opxmm) + ctx.VCVTTPS2QQ_BCST_Z(opm32, opk, opxmm) + ctx.VCVTTPS2QQ_SAE(opymm, opk, opzmm) + ctx.VCVTTPS2QQ_SAE_Z(opymm, opk, opzmm) + ctx.VCVTTPS2QQ_Z(opm128, opk, opymm) + ctx.VCVTTPS2UDQ(opm128, opk, opxmm) + ctx.VCVTTPS2UDQ_BCST(opm32, opk, opxmm) + ctx.VCVTTPS2UDQ_BCST_Z(opm32, opk, opxmm) + ctx.VCVTTPS2UDQ_SAE(opzmm, opk, opzmm) + ctx.VCVTTPS2UDQ_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTTPS2UDQ_Z(opm128, opk, opxmm) + ctx.VCVTTPS2UQQ(opm128, opk, opymm) + ctx.VCVTTPS2UQQ_BCST(opm32, opk, opxmm) + ctx.VCVTTPS2UQQ_BCST_Z(opm32, opk, opxmm) + ctx.VCVTTPS2UQQ_SAE(opymm, opk, opzmm) + ctx.VCVTTPS2UQQ_SAE_Z(opymm, opk, opzmm) + ctx.VCVTTPS2UQQ_Z(opm128, opk, opymm) + ctx.VCVTTSD2SI(opm64, opr32) + ctx.VCVTTSD2SIQ(opm64, opr64) + ctx.VCVTTSD2SIQ_SAE(opxmm, opr64) + ctx.VCVTTSD2SI_SAE(opxmm, opr32) + ctx.VCVTTSD2USIL(opm64, opr32) + ctx.VCVTTSD2USIL_SAE(opxmm, opr32) + ctx.VCVTTSD2USIQ(opm64, opr64) + ctx.VCVTTSD2USIQ_SAE(opxmm, opr64) + ctx.VCVTTSS2SI(opm32, opr32) + ctx.VCVTTSS2SIQ(opm32, opr64) + ctx.VCVTTSS2SIQ_SAE(opxmm, opr64) + ctx.VCVTTSS2SI_SAE(opxmm, opr32) + ctx.VCVTTSS2USIL(opm32, opr32) + ctx.VCVTTSS2USIL_SAE(opxmm, opr32) + ctx.VCVTTSS2USIQ(opm32, opr64) + ctx.VCVTTSS2USIQ_SAE(opxmm, opr64) + ctx.VCVTUDQ2PD(opm128, opk, opymm) + ctx.VCVTUDQ2PD_BCST(opm32, opk, opxmm) + ctx.VCVTUDQ2PD_BCST_Z(opm32, opk, opxmm) + ctx.VCVTUDQ2PD_Z(opm128, opk, opymm) + ctx.VCVTUDQ2PS(opm128, opk, opxmm) + ctx.VCVTUDQ2PS_BCST(opm32, opk, opxmm) + ctx.VCVTUDQ2PS_BCST_Z(opm32, opk, opxmm) + ctx.VCVTUDQ2PS_RD_SAE(opzmm, opk, opzmm) + ctx.VCVTUDQ2PS_RD_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTUDQ2PS_RN_SAE(opzmm, opk, opzmm) + ctx.VCVTUDQ2PS_RN_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTUDQ2PS_RU_SAE(opzmm, opk, opzmm) + ctx.VCVTUDQ2PS_RU_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTUDQ2PS_RZ_SAE(opzmm, opk, opzmm) + ctx.VCVTUDQ2PS_RZ_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTUDQ2PS_Z(opm128, opk, opxmm) + ctx.VCVTUQQ2PD(opm128, opk, opxmm) + ctx.VCVTUQQ2PD_BCST(opm64, opk, opxmm) + ctx.VCVTUQQ2PD_BCST_Z(opm64, opk, opxmm) + ctx.VCVTUQQ2PD_RD_SAE(opzmm, opk, opzmm) + ctx.VCVTUQQ2PD_RD_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTUQQ2PD_RN_SAE(opzmm, opk, opzmm) + ctx.VCVTUQQ2PD_RN_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTUQQ2PD_RU_SAE(opzmm, opk, opzmm) + ctx.VCVTUQQ2PD_RU_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTUQQ2PD_RZ_SAE(opzmm, opk, opzmm) + ctx.VCVTUQQ2PD_RZ_SAE_Z(opzmm, opk, opzmm) + ctx.VCVTUQQ2PD_Z(opm128, opk, opxmm) + ctx.VCVTUQQ2PS(opm512, opk, opymm) + ctx.VCVTUQQ2PSX(opm128, opk, opxmm) + ctx.VCVTUQQ2PSX_BCST(opm64, opk, opxmm) + ctx.VCVTUQQ2PSX_BCST_Z(opm64, opk, opxmm) + ctx.VCVTUQQ2PSX_Z(opm128, opk, opxmm) + ctx.VCVTUQQ2PSY(opm256, opk, opxmm) + ctx.VCVTUQQ2PSY_BCST(opm64, opk, opxmm) + ctx.VCVTUQQ2PSY_BCST_Z(opm64, opk, opxmm) + ctx.VCVTUQQ2PSY_Z(opm256, opk, opxmm) + ctx.VCVTUQQ2PS_BCST(opm64, opk, opymm) + ctx.VCVTUQQ2PS_BCST_Z(opm64, opk, opymm) + ctx.VCVTUQQ2PS_RD_SAE(opzmm, opk, opymm) + ctx.VCVTUQQ2PS_RD_SAE_Z(opzmm, opk, opymm) + ctx.VCVTUQQ2PS_RN_SAE(opzmm, opk, opymm) + ctx.VCVTUQQ2PS_RN_SAE_Z(opzmm, opk, opymm) + ctx.VCVTUQQ2PS_RU_SAE(opzmm, opk, opymm) + ctx.VCVTUQQ2PS_RU_SAE_Z(opzmm, opk, opymm) + ctx.VCVTUQQ2PS_RZ_SAE(opzmm, opk, opymm) + ctx.VCVTUQQ2PS_RZ_SAE_Z(opzmm, opk, opymm) + ctx.VCVTUQQ2PS_Z(opm512, opk, opymm) + ctx.VCVTUSI2SDL(opm32, opxmm, opxmm) + ctx.VCVTUSI2SDQ(opm64, opxmm, opxmm) + ctx.VCVTUSI2SDQ_RD_SAE(opr64, opxmm, opxmm) + ctx.VCVTUSI2SDQ_RN_SAE(opr64, opxmm, opxmm) + ctx.VCVTUSI2SDQ_RU_SAE(opr64, opxmm, opxmm) + ctx.VCVTUSI2SDQ_RZ_SAE(opr64, opxmm, opxmm) + ctx.VCVTUSI2SSL(opm32, opxmm, opxmm) + ctx.VCVTUSI2SSL_RD_SAE(opr32, opxmm, opxmm) + ctx.VCVTUSI2SSL_RN_SAE(opr32, opxmm, opxmm) + ctx.VCVTUSI2SSL_RU_SAE(opr32, opxmm, opxmm) + ctx.VCVTUSI2SSL_RZ_SAE(opr32, opxmm, opxmm) + ctx.VCVTUSI2SSQ(opm64, opxmm, opxmm) + ctx.VCVTUSI2SSQ_RD_SAE(opr64, opxmm, opxmm) + ctx.VCVTUSI2SSQ_RN_SAE(opr64, opxmm, opxmm) + ctx.VCVTUSI2SSQ_RU_SAE(opr64, opxmm, opxmm) + ctx.VCVTUSI2SSQ_RZ_SAE(opr64, opxmm, opxmm) + ctx.VDBPSADBW(opimm8, opm128, opxmm, opk, opxmm) + ctx.VDBPSADBW_Z(opimm8, opm128, opxmm, opk, opxmm) + ctx.VDIVPD(opm128, opxmm, opxmm) + ctx.VDIVPD_BCST(opm64, opxmm, opk, opxmm) + ctx.VDIVPD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VDIVPD_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VDIVPD_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VDIVPD_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VDIVPD_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VDIVPD_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VDIVPD_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VDIVPD_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VDIVPD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VDIVPD_Z(opm128, opxmm, opk, opxmm) + ctx.VDIVPS(opm128, opxmm, opxmm) + ctx.VDIVPS_BCST(opm32, opxmm, opk, opxmm) + ctx.VDIVPS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VDIVPS_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VDIVPS_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VDIVPS_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VDIVPS_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VDIVPS_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VDIVPS_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VDIVPS_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VDIVPS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VDIVPS_Z(opm128, opxmm, opk, opxmm) + ctx.VDIVSD(opm64, opxmm, opxmm) + ctx.VDIVSD_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VDIVSD_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VDIVSD_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VDIVSD_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VDIVSD_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VDIVSD_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VDIVSD_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VDIVSD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VDIVSD_Z(opm64, opxmm, opk, opxmm) + ctx.VDIVSS(opm32, opxmm, opxmm) + ctx.VDIVSS_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VDIVSS_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VDIVSS_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VDIVSS_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VDIVSS_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VDIVSS_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VDIVSS_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VDIVSS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VDIVSS_Z(opm32, opxmm, opk, opxmm) + ctx.VDPPD(opimm8, opm128, opxmm, opxmm) + ctx.VDPPS(opimm8, opm128, opxmm, opxmm) + ctx.VEXP2PD(opm512, opk, opzmm) + ctx.VEXP2PD_BCST(opm64, opk, opzmm) + ctx.VEXP2PD_BCST_Z(opm64, opk, opzmm) + ctx.VEXP2PD_SAE(opzmm, opk, opzmm) + ctx.VEXP2PD_SAE_Z(opzmm, opk, opzmm) + ctx.VEXP2PD_Z(opm512, opk, opzmm) + ctx.VEXP2PS(opm512, opk, opzmm) + ctx.VEXP2PS_BCST(opm32, opk, opzmm) + ctx.VEXP2PS_BCST_Z(opm32, opk, opzmm) + ctx.VEXP2PS_SAE(opzmm, opk, opzmm) + ctx.VEXP2PS_SAE_Z(opzmm, opk, opzmm) + ctx.VEXP2PS_Z(opm512, opk, opzmm) + ctx.VEXPANDPD(opm256, opk, opymm) + ctx.VEXPANDPD_Z(opm256, opk, opymm) + ctx.VEXPANDPS(opm128, opk, opxmm) + ctx.VEXPANDPS_Z(opm128, opk, opxmm) + ctx.VEXTRACTF128(opimm8, opymm, opm128) + ctx.VEXTRACTF32X4(opimm8, opymm, opk, opm128) + ctx.VEXTRACTF32X4_Z(opimm8, opymm, opk, opm128) + ctx.VEXTRACTF32X8(opimm8, opzmm, opk, opm256) + ctx.VEXTRACTF32X8_Z(opimm8, opzmm, opk, opm256) + ctx.VEXTRACTF64X2(opimm8, opymm, opk, opm128) + ctx.VEXTRACTF64X2_Z(opimm8, opymm, opk, opm128) + ctx.VEXTRACTF64X4(opimm8, opzmm, opk, opm256) + ctx.VEXTRACTF64X4_Z(opimm8, opzmm, opk, opm256) + ctx.VEXTRACTI128(opimm8, opymm, opm128) + ctx.VEXTRACTI32X4(opimm8, opymm, opk, opm128) + ctx.VEXTRACTI32X4_Z(opimm8, opymm, opk, opm128) + ctx.VEXTRACTI32X8(opimm8, opzmm, opk, opm256) + ctx.VEXTRACTI32X8_Z(opimm8, opzmm, opk, opm256) + ctx.VEXTRACTI64X2(opimm8, opymm, opk, opm128) + ctx.VEXTRACTI64X2_Z(opimm8, opymm, opk, opm128) + ctx.VEXTRACTI64X4(opimm8, opzmm, opk, opm256) + ctx.VEXTRACTI64X4_Z(opimm8, opzmm, opk, opm256) + ctx.VEXTRACTPS(opimm8, opxmm, opm32) + ctx.VFIXUPIMMPD(opimm8, opm128, opxmm, opk, opxmm) + ctx.VFIXUPIMMPD_BCST(opimm8, opm64, opxmm, opk, opxmm) + ctx.VFIXUPIMMPD_BCST_Z(opimm8, opm64, opxmm, opk, opxmm) + ctx.VFIXUPIMMPD_SAE(opimm8, opzmm, opzmm, opk, opzmm) + ctx.VFIXUPIMMPD_SAE_Z(opimm8, opzmm, opzmm, opk, opzmm) + ctx.VFIXUPIMMPD_Z(opimm8, opm128, opxmm, opk, opxmm) + ctx.VFIXUPIMMPS(opimm8, opm256, opymm, opk, opymm) + ctx.VFIXUPIMMPS_BCST(opimm8, opm32, opymm, opk, opymm) + ctx.VFIXUPIMMPS_BCST_Z(opimm8, opm32, opymm, opk, opymm) + ctx.VFIXUPIMMPS_SAE(opimm8, opzmm, opzmm, opk, opzmm) + ctx.VFIXUPIMMPS_SAE_Z(opimm8, opzmm, opzmm, opk, opzmm) + ctx.VFIXUPIMMPS_Z(opimm8, opm256, opymm, opk, opymm) + ctx.VFIXUPIMMSD(opimm8, opm64, opxmm, opk, opxmm) + ctx.VFIXUPIMMSD_SAE(opimm8, opxmm, opxmm, opk, opxmm) + ctx.VFIXUPIMMSD_SAE_Z(opimm8, opxmm, opxmm, opk, opxmm) + ctx.VFIXUPIMMSD_Z(opimm8, opm64, opxmm, opk, opxmm) + ctx.VFIXUPIMMSS(opimm8, opm32, opxmm, opk, opxmm) + ctx.VFIXUPIMMSS_SAE(opimm8, opxmm, opxmm, opk, opxmm) + ctx.VFIXUPIMMSS_SAE_Z(opimm8, opxmm, opxmm, opk, opxmm) + ctx.VFIXUPIMMSS_Z(opimm8, opm32, opxmm, opk, opxmm) + ctx.VFMADD132PD(opm128, opxmm, opxmm) + ctx.VFMADD132PD_BCST(opm64, opxmm, opk, opxmm) + ctx.VFMADD132PD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VFMADD132PD_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADD132PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADD132PD_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADD132PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADD132PD_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADD132PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADD132PD_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADD132PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADD132PD_Z(opm128, opxmm, opk, opxmm) + ctx.VFMADD132PS(opm128, opxmm, opxmm) + ctx.VFMADD132PS_BCST(opm32, opxmm, opk, opxmm) + ctx.VFMADD132PS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VFMADD132PS_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADD132PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADD132PS_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADD132PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADD132PS_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADD132PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADD132PS_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADD132PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADD132PS_Z(opm128, opxmm, opk, opxmm) + ctx.VFMADD132SD(opm64, opxmm, opxmm) + ctx.VFMADD132SD_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMADD132SD_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMADD132SD_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMADD132SD_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMADD132SD_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMADD132SD_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMADD132SD_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMADD132SD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMADD132SD_Z(opm64, opxmm, opk, opxmm) + ctx.VFMADD132SS(opm32, opxmm, opxmm) + ctx.VFMADD132SS_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMADD132SS_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMADD132SS_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMADD132SS_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMADD132SS_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMADD132SS_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMADD132SS_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMADD132SS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMADD132SS_Z(opm32, opxmm, opk, opxmm) + ctx.VFMADD213PD(opm128, opxmm, opxmm) + ctx.VFMADD213PD_BCST(opm64, opxmm, opk, opxmm) + ctx.VFMADD213PD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VFMADD213PD_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADD213PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADD213PD_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADD213PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADD213PD_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADD213PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADD213PD_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADD213PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADD213PD_Z(opm128, opxmm, opk, opxmm) + ctx.VFMADD213PS(opm128, opxmm, opxmm) + ctx.VFMADD213PS_BCST(opm32, opxmm, opk, opxmm) + ctx.VFMADD213PS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VFMADD213PS_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADD213PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADD213PS_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADD213PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADD213PS_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADD213PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADD213PS_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADD213PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADD213PS_Z(opm128, opxmm, opk, opxmm) + ctx.VFMADD213SD(opm64, opxmm, opxmm) + ctx.VFMADD213SD_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMADD213SD_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMADD213SD_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMADD213SD_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMADD213SD_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMADD213SD_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMADD213SD_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMADD213SD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMADD213SD_Z(opm64, opxmm, opk, opxmm) + ctx.VFMADD213SS(opm32, opxmm, opxmm) + ctx.VFMADD213SS_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMADD213SS_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMADD213SS_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMADD213SS_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMADD213SS_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMADD213SS_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMADD213SS_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMADD213SS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMADD213SS_Z(opm32, opxmm, opk, opxmm) + ctx.VFMADD231PD(opm128, opxmm, opxmm) + ctx.VFMADD231PD_BCST(opm64, opxmm, opk, opxmm) + ctx.VFMADD231PD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VFMADD231PD_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADD231PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADD231PD_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADD231PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADD231PD_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADD231PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADD231PD_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADD231PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADD231PD_Z(opm128, opxmm, opk, opxmm) + ctx.VFMADD231PS(opm128, opxmm, opxmm) + ctx.VFMADD231PS_BCST(opm32, opxmm, opk, opxmm) + ctx.VFMADD231PS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VFMADD231PS_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADD231PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADD231PS_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADD231PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADD231PS_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADD231PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADD231PS_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADD231PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADD231PS_Z(opm128, opxmm, opk, opxmm) + ctx.VFMADD231SD(opm64, opxmm, opxmm) + ctx.VFMADD231SD_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMADD231SD_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMADD231SD_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMADD231SD_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMADD231SD_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMADD231SD_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMADD231SD_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMADD231SD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMADD231SD_Z(opm64, opxmm, opk, opxmm) + ctx.VFMADD231SS(opm32, opxmm, opxmm) + ctx.VFMADD231SS_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMADD231SS_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMADD231SS_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMADD231SS_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMADD231SS_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMADD231SS_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMADD231SS_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMADD231SS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMADD231SS_Z(opm32, opxmm, opk, opxmm) + ctx.VFMADDSUB132PD(opm128, opxmm, opxmm) + ctx.VFMADDSUB132PD_BCST(opm64, opxmm, opk, opxmm) + ctx.VFMADDSUB132PD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VFMADDSUB132PD_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB132PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB132PD_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB132PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB132PD_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB132PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB132PD_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB132PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB132PD_Z(opm128, opxmm, opk, opxmm) + ctx.VFMADDSUB132PS(opm128, opxmm, opxmm) + ctx.VFMADDSUB132PS_BCST(opm32, opxmm, opk, opxmm) + ctx.VFMADDSUB132PS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VFMADDSUB132PS_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB132PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB132PS_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB132PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB132PS_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB132PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB132PS_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB132PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB132PS_Z(opm128, opxmm, opk, opxmm) + ctx.VFMADDSUB213PD(opm128, opxmm, opxmm) + ctx.VFMADDSUB213PD_BCST(opm64, opxmm, opk, opxmm) + ctx.VFMADDSUB213PD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VFMADDSUB213PD_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB213PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB213PD_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB213PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB213PD_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB213PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB213PD_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB213PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB213PD_Z(opm128, opxmm, opk, opxmm) + ctx.VFMADDSUB213PS(opm128, opxmm, opxmm) + ctx.VFMADDSUB213PS_BCST(opm32, opxmm, opk, opxmm) + ctx.VFMADDSUB213PS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VFMADDSUB213PS_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB213PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB213PS_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB213PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB213PS_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB213PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB213PS_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB213PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB213PS_Z(opm128, opxmm, opk, opxmm) + ctx.VFMADDSUB231PD(opm128, opxmm, opxmm) + ctx.VFMADDSUB231PD_BCST(opm64, opxmm, opk, opxmm) + ctx.VFMADDSUB231PD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VFMADDSUB231PD_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB231PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB231PD_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB231PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB231PD_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB231PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB231PD_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB231PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB231PD_Z(opm128, opxmm, opk, opxmm) + ctx.VFMADDSUB231PS(opm128, opxmm, opxmm) + ctx.VFMADDSUB231PS_BCST(opm32, opxmm, opk, opxmm) + ctx.VFMADDSUB231PS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VFMADDSUB231PS_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB231PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB231PS_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB231PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB231PS_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB231PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB231PS_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB231PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMADDSUB231PS_Z(opm128, opxmm, opk, opxmm) + ctx.VFMSUB132PD(opm128, opxmm, opxmm) + ctx.VFMSUB132PD_BCST(opm64, opxmm, opk, opxmm) + ctx.VFMSUB132PD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VFMSUB132PD_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB132PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB132PD_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB132PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB132PD_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB132PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB132PD_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB132PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB132PD_Z(opm128, opxmm, opk, opxmm) + ctx.VFMSUB132PS(opm128, opxmm, opxmm) + ctx.VFMSUB132PS_BCST(opm32, opxmm, opk, opxmm) + ctx.VFMSUB132PS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VFMSUB132PS_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB132PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB132PS_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB132PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB132PS_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB132PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB132PS_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB132PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB132PS_Z(opm128, opxmm, opk, opxmm) + ctx.VFMSUB132SD(opm64, opxmm, opxmm) + ctx.VFMSUB132SD_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB132SD_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB132SD_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB132SD_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB132SD_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB132SD_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB132SD_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB132SD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB132SD_Z(opm64, opxmm, opk, opxmm) + ctx.VFMSUB132SS(opm32, opxmm, opxmm) + ctx.VFMSUB132SS_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB132SS_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB132SS_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB132SS_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB132SS_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB132SS_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB132SS_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB132SS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB132SS_Z(opm32, opxmm, opk, opxmm) + ctx.VFMSUB213PD(opm128, opxmm, opxmm) + ctx.VFMSUB213PD_BCST(opm64, opxmm, opk, opxmm) + ctx.VFMSUB213PD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VFMSUB213PD_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB213PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB213PD_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB213PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB213PD_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB213PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB213PD_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB213PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB213PD_Z(opm128, opxmm, opk, opxmm) + ctx.VFMSUB213PS(opm128, opxmm, opxmm) + ctx.VFMSUB213PS_BCST(opm32, opxmm, opk, opxmm) + ctx.VFMSUB213PS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VFMSUB213PS_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB213PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB213PS_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB213PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB213PS_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB213PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB213PS_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB213PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB213PS_Z(opm128, opxmm, opk, opxmm) + ctx.VFMSUB213SD(opm64, opxmm, opxmm) + ctx.VFMSUB213SD_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB213SD_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB213SD_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB213SD_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB213SD_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB213SD_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB213SD_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB213SD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB213SD_Z(opm64, opxmm, opk, opxmm) + ctx.VFMSUB213SS(opm32, opxmm, opxmm) + ctx.VFMSUB213SS_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB213SS_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB213SS_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB213SS_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB213SS_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB213SS_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB213SS_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB213SS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB213SS_Z(opm32, opxmm, opk, opxmm) + ctx.VFMSUB231PD(opm128, opxmm, opxmm) + ctx.VFMSUB231PD_BCST(opm64, opxmm, opk, opxmm) + ctx.VFMSUB231PD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VFMSUB231PD_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB231PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB231PD_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB231PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB231PD_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB231PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB231PD_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB231PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB231PD_Z(opm128, opxmm, opk, opxmm) + ctx.VFMSUB231PS(opm128, opxmm, opxmm) + ctx.VFMSUB231PS_BCST(opm32, opxmm, opk, opxmm) + ctx.VFMSUB231PS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VFMSUB231PS_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB231PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB231PS_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB231PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB231PS_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB231PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB231PS_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB231PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUB231PS_Z(opm128, opxmm, opk, opxmm) + ctx.VFMSUB231SD(opm64, opxmm, opxmm) + ctx.VFMSUB231SD_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB231SD_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB231SD_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB231SD_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB231SD_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB231SD_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB231SD_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB231SD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB231SD_Z(opm64, opxmm, opk, opxmm) + ctx.VFMSUB231SS(opm32, opxmm, opxmm) + ctx.VFMSUB231SS_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB231SS_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB231SS_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB231SS_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB231SS_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB231SS_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB231SS_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB231SS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFMSUB231SS_Z(opm32, opxmm, opk, opxmm) + ctx.VFMSUBADD132PD(opm128, opxmm, opxmm) + ctx.VFMSUBADD132PD_BCST(opm64, opxmm, opk, opxmm) + ctx.VFMSUBADD132PD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VFMSUBADD132PD_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD132PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD132PD_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD132PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD132PD_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD132PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD132PD_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD132PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD132PD_Z(opm128, opxmm, opk, opxmm) + ctx.VFMSUBADD132PS(opm128, opxmm, opxmm) + ctx.VFMSUBADD132PS_BCST(opm32, opxmm, opk, opxmm) + ctx.VFMSUBADD132PS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VFMSUBADD132PS_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD132PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD132PS_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD132PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD132PS_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD132PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD132PS_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD132PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD132PS_Z(opm128, opxmm, opk, opxmm) + ctx.VFMSUBADD213PD(opm128, opxmm, opxmm) + ctx.VFMSUBADD213PD_BCST(opm64, opxmm, opk, opxmm) + ctx.VFMSUBADD213PD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VFMSUBADD213PD_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD213PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD213PD_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD213PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD213PD_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD213PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD213PD_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD213PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD213PD_Z(opm128, opxmm, opk, opxmm) + ctx.VFMSUBADD213PS(opm128, opxmm, opxmm) + ctx.VFMSUBADD213PS_BCST(opm32, opxmm, opk, opxmm) + ctx.VFMSUBADD213PS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VFMSUBADD213PS_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD213PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD213PS_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD213PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD213PS_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD213PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD213PS_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD213PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD213PS_Z(opm128, opxmm, opk, opxmm) + ctx.VFMSUBADD231PD(opm128, opxmm, opxmm) + ctx.VFMSUBADD231PD_BCST(opm64, opxmm, opk, opxmm) + ctx.VFMSUBADD231PD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VFMSUBADD231PD_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD231PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD231PD_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD231PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD231PD_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD231PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD231PD_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD231PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD231PD_Z(opm128, opxmm, opk, opxmm) + ctx.VFMSUBADD231PS(opm128, opxmm, opxmm) + ctx.VFMSUBADD231PS_BCST(opm32, opxmm, opk, opxmm) + ctx.VFMSUBADD231PS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VFMSUBADD231PS_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD231PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD231PS_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD231PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD231PS_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD231PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD231PS_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD231PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFMSUBADD231PS_Z(opm128, opxmm, opk, opxmm) + ctx.VFNMADD132PD(opm128, opxmm, opxmm) + ctx.VFNMADD132PD_BCST(opm64, opxmm, opk, opxmm) + ctx.VFNMADD132PD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VFNMADD132PD_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD132PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD132PD_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD132PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD132PD_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD132PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD132PD_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD132PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD132PD_Z(opm128, opxmm, opk, opxmm) + ctx.VFNMADD132PS(opm128, opxmm, opxmm) + ctx.VFNMADD132PS_BCST(opm32, opxmm, opk, opxmm) + ctx.VFNMADD132PS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VFNMADD132PS_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD132PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD132PS_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD132PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD132PS_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD132PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD132PS_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD132PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD132PS_Z(opm128, opxmm, opk, opxmm) + ctx.VFNMADD132SD(opm64, opxmm, opxmm) + ctx.VFNMADD132SD_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD132SD_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD132SD_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD132SD_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD132SD_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD132SD_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD132SD_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD132SD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD132SD_Z(opm64, opxmm, opk, opxmm) + ctx.VFNMADD132SS(opm32, opxmm, opxmm) + ctx.VFNMADD132SS_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD132SS_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD132SS_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD132SS_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD132SS_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD132SS_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD132SS_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD132SS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD132SS_Z(opm32, opxmm, opk, opxmm) + ctx.VFNMADD213PD(opm128, opxmm, opxmm) + ctx.VFNMADD213PD_BCST(opm64, opxmm, opk, opxmm) + ctx.VFNMADD213PD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VFNMADD213PD_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD213PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD213PD_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD213PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD213PD_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD213PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD213PD_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD213PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD213PD_Z(opm128, opxmm, opk, opxmm) + ctx.VFNMADD213PS(opm128, opxmm, opxmm) + ctx.VFNMADD213PS_BCST(opm32, opxmm, opk, opxmm) + ctx.VFNMADD213PS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VFNMADD213PS_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD213PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD213PS_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD213PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD213PS_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD213PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD213PS_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD213PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD213PS_Z(opm128, opxmm, opk, opxmm) + ctx.VFNMADD213SD(opm64, opxmm, opxmm) + ctx.VFNMADD213SD_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD213SD_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD213SD_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD213SD_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD213SD_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD213SD_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD213SD_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD213SD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD213SD_Z(opm64, opxmm, opk, opxmm) + ctx.VFNMADD213SS(opm32, opxmm, opxmm) + ctx.VFNMADD213SS_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD213SS_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD213SS_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD213SS_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD213SS_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD213SS_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD213SS_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD213SS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD213SS_Z(opm32, opxmm, opk, opxmm) + ctx.VFNMADD231PD(opm128, opxmm, opxmm) + ctx.VFNMADD231PD_BCST(opm64, opxmm, opk, opxmm) + ctx.VFNMADD231PD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VFNMADD231PD_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD231PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD231PD_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD231PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD231PD_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD231PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD231PD_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD231PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD231PD_Z(opm128, opxmm, opk, opxmm) + ctx.VFNMADD231PS(opm128, opxmm, opxmm) + ctx.VFNMADD231PS_BCST(opm32, opxmm, opk, opxmm) + ctx.VFNMADD231PS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VFNMADD231PS_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD231PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD231PS_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD231PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD231PS_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD231PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD231PS_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD231PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMADD231PS_Z(opm128, opxmm, opk, opxmm) + ctx.VFNMADD231SD(opm64, opxmm, opxmm) + ctx.VFNMADD231SD_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD231SD_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD231SD_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD231SD_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD231SD_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD231SD_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD231SD_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD231SD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD231SD_Z(opm64, opxmm, opk, opxmm) + ctx.VFNMADD231SS(opm32, opxmm, opxmm) + ctx.VFNMADD231SS_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD231SS_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD231SS_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD231SS_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD231SS_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD231SS_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD231SS_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD231SS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMADD231SS_Z(opm32, opxmm, opk, opxmm) + ctx.VFNMSUB132PD(opm128, opxmm, opxmm) + ctx.VFNMSUB132PD_BCST(opm64, opxmm, opk, opxmm) + ctx.VFNMSUB132PD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VFNMSUB132PD_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB132PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB132PD_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB132PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB132PD_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB132PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB132PD_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB132PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB132PD_Z(opm128, opxmm, opk, opxmm) + ctx.VFNMSUB132PS(opm128, opxmm, opxmm) + ctx.VFNMSUB132PS_BCST(opm32, opxmm, opk, opxmm) + ctx.VFNMSUB132PS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VFNMSUB132PS_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB132PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB132PS_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB132PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB132PS_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB132PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB132PS_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB132PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB132PS_Z(opm128, opxmm, opk, opxmm) + ctx.VFNMSUB132SD(opm64, opxmm, opxmm) + ctx.VFNMSUB132SD_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB132SD_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB132SD_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB132SD_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB132SD_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB132SD_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB132SD_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB132SD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB132SD_Z(opm64, opxmm, opk, opxmm) + ctx.VFNMSUB132SS(opm32, opxmm, opxmm) + ctx.VFNMSUB132SS_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB132SS_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB132SS_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB132SS_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB132SS_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB132SS_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB132SS_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB132SS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB132SS_Z(opm32, opxmm, opk, opxmm) + ctx.VFNMSUB213PD(opm128, opxmm, opxmm) + ctx.VFNMSUB213PD_BCST(opm64, opxmm, opk, opxmm) + ctx.VFNMSUB213PD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VFNMSUB213PD_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB213PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB213PD_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB213PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB213PD_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB213PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB213PD_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB213PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB213PD_Z(opm128, opxmm, opk, opxmm) + ctx.VFNMSUB213PS(opm128, opxmm, opxmm) + ctx.VFNMSUB213PS_BCST(opm32, opxmm, opk, opxmm) + ctx.VFNMSUB213PS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VFNMSUB213PS_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB213PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB213PS_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB213PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB213PS_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB213PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB213PS_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB213PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB213PS_Z(opm128, opxmm, opk, opxmm) + ctx.VFNMSUB213SD(opm64, opxmm, opxmm) + ctx.VFNMSUB213SD_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB213SD_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB213SD_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB213SD_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB213SD_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB213SD_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB213SD_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB213SD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB213SD_Z(opm64, opxmm, opk, opxmm) + ctx.VFNMSUB213SS(opm32, opxmm, opxmm) + ctx.VFNMSUB213SS_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB213SS_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB213SS_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB213SS_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB213SS_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB213SS_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB213SS_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB213SS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB213SS_Z(opm32, opxmm, opk, opxmm) + ctx.VFNMSUB231PD(opm128, opxmm, opxmm) + ctx.VFNMSUB231PD_BCST(opm64, opxmm, opk, opxmm) + ctx.VFNMSUB231PD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VFNMSUB231PD_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB231PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB231PD_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB231PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB231PD_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB231PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB231PD_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB231PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB231PD_Z(opm128, opxmm, opk, opxmm) + ctx.VFNMSUB231PS(opm128, opxmm, opxmm) + ctx.VFNMSUB231PS_BCST(opm32, opxmm, opk, opxmm) + ctx.VFNMSUB231PS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VFNMSUB231PS_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB231PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB231PS_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB231PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB231PS_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB231PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB231PS_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB231PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VFNMSUB231PS_Z(opm128, opxmm, opk, opxmm) + ctx.VFNMSUB231SD(opm64, opxmm, opxmm) + ctx.VFNMSUB231SD_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB231SD_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB231SD_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB231SD_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB231SD_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB231SD_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB231SD_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB231SD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB231SD_Z(opm64, opxmm, opk, opxmm) + ctx.VFNMSUB231SS(opm32, opxmm, opxmm) + ctx.VFNMSUB231SS_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB231SS_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB231SS_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB231SS_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB231SS_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB231SS_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB231SS_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB231SS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VFNMSUB231SS_Z(opm32, opxmm, opk, opxmm) + ctx.VFPCLASSPDX(opimm8, opm128, opk, opk) + ctx.VFPCLASSPDX_BCST(opimm8, opm64, opk, opk) + ctx.VFPCLASSPDY(opimm8, opm256, opk, opk) + ctx.VFPCLASSPDY_BCST(opimm8, opm64, opk, opk) + ctx.VFPCLASSPDZ(opimm8, opm512, opk, opk) + ctx.VFPCLASSPDZ_BCST(opimm8, opm64, opk, opk) + ctx.VFPCLASSPSX(opimm8, opm128, opk, opk) + ctx.VFPCLASSPSX_BCST(opimm8, opm32, opk, opk) + ctx.VFPCLASSPSY(opimm8, opm256, opk, opk) + ctx.VFPCLASSPSY_BCST(opimm8, opm32, opk, opk) + ctx.VFPCLASSPSZ(opimm8, opm512, opk, opk) + ctx.VFPCLASSPSZ_BCST(opimm8, opm32, opk, opk) + ctx.VFPCLASSSD(opimm8, opm64, opk, opk) + ctx.VFPCLASSSS(opimm8, opm32, opk, opk) + ctx.VGATHERDPD(opxmm, opvm32x, opxmm) + ctx.VGATHERDPS(opxmm, opvm32x, opxmm) + ctx.VGATHERQPD(opxmm, opvm64x, opxmm) + ctx.VGATHERQPS(opxmm, opvm64x, opxmm) + ctx.VGETEXPPD(opm128, opk, opxmm) + ctx.VGETEXPPD_BCST(opm64, opk, opxmm) + ctx.VGETEXPPD_BCST_Z(opm64, opk, opxmm) + ctx.VGETEXPPD_SAE(opzmm, opk, opzmm) + ctx.VGETEXPPD_SAE_Z(opzmm, opk, opzmm) + ctx.VGETEXPPD_Z(opm128, opk, opxmm) + ctx.VGETEXPPS(opm128, opk, opxmm) + ctx.VGETEXPPS_BCST(opm32, opk, opxmm) + ctx.VGETEXPPS_BCST_Z(opm32, opk, opxmm) + ctx.VGETEXPPS_SAE(opzmm, opk, opzmm) + ctx.VGETEXPPS_SAE_Z(opzmm, opk, opzmm) + ctx.VGETEXPPS_Z(opm128, opk, opxmm) + ctx.VGETEXPSD(opm64, opxmm, opk, opxmm) + ctx.VGETEXPSD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VGETEXPSD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VGETEXPSD_Z(opm64, opxmm, opk, opxmm) + ctx.VGETEXPSS(opm32, opxmm, opk, opxmm) + ctx.VGETEXPSS_SAE(opxmm, opxmm, opk, opxmm) + ctx.VGETEXPSS_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VGETEXPSS_Z(opm32, opxmm, opk, opxmm) + ctx.VGETMANTPD(opimm8, opm128, opk, opxmm) + ctx.VGETMANTPD_BCST(opimm8, opm64, opk, opxmm) + ctx.VGETMANTPD_BCST_Z(opimm8, opm64, opk, opxmm) + ctx.VGETMANTPD_SAE(opimm8, opzmm, opk, opzmm) + ctx.VGETMANTPD_SAE_Z(opimm8, opzmm, opk, opzmm) + ctx.VGETMANTPD_Z(opimm8, opm128, opk, opxmm) + ctx.VGETMANTPS(opimm8, opm128, opk, opxmm) + ctx.VGETMANTPS_BCST(opimm8, opm32, opk, opxmm) + ctx.VGETMANTPS_BCST_Z(opimm8, opm32, opk, opxmm) + ctx.VGETMANTPS_SAE(opimm8, opzmm, opk, opzmm) + ctx.VGETMANTPS_SAE_Z(opimm8, opzmm, opk, opzmm) + ctx.VGETMANTPS_Z(opimm8, opm128, opk, opxmm) + ctx.VGETMANTSD(opimm8, opm64, opxmm, opk, opxmm) + ctx.VGETMANTSD_SAE(opimm8, opxmm, opxmm, opk, opxmm) + ctx.VGETMANTSD_SAE_Z(opimm8, opxmm, opxmm, opk, opxmm) + ctx.VGETMANTSD_Z(opimm8, opm64, opxmm, opk, opxmm) + ctx.VGETMANTSS(opimm8, opm32, opxmm, opk, opxmm) + ctx.VGETMANTSS_SAE(opimm8, opxmm, opxmm, opk, opxmm) + ctx.VGETMANTSS_SAE_Z(opimm8, opxmm, opxmm, opk, opxmm) + ctx.VGETMANTSS_Z(opimm8, opm32, opxmm, opk, opxmm) + ctx.VHADDPD(opm128, opxmm, opxmm) + ctx.VHADDPS(opm128, opxmm, opxmm) + ctx.VHSUBPD(opm128, opxmm, opxmm) + ctx.VHSUBPS(opm128, opxmm, opxmm) + ctx.VINSERTF128(opimm8, opm128, opymm, opymm) + ctx.VINSERTF32X4(opimm8, opm128, opymm, opk, opymm) + ctx.VINSERTF32X4_Z(opimm8, opm128, opymm, opk, opymm) + ctx.VINSERTF32X8(opimm8, opm256, opzmm, opk, opzmm) + ctx.VINSERTF32X8_Z(opimm8, opm256, opzmm, opk, opzmm) + ctx.VINSERTF64X2(opimm8, opm128, opymm, opk, opymm) + ctx.VINSERTF64X2_Z(opimm8, opm128, opymm, opk, opymm) + ctx.VINSERTF64X4(opimm8, opm256, opzmm, opk, opzmm) + ctx.VINSERTF64X4_Z(opimm8, opm256, opzmm, opk, opzmm) + ctx.VINSERTI128(opimm8, opm128, opymm, opymm) + ctx.VINSERTI32X4(opimm8, opm128, opymm, opk, opymm) + ctx.VINSERTI32X4_Z(opimm8, opm128, opymm, opk, opymm) + ctx.VINSERTI32X8(opimm8, opm256, opzmm, opk, opzmm) + ctx.VINSERTI32X8_Z(opimm8, opm256, opzmm, opk, opzmm) + ctx.VINSERTI64X2(opimm8, opm128, opymm, opk, opymm) + ctx.VINSERTI64X2_Z(opimm8, opm128, opymm, opk, opymm) + ctx.VINSERTI64X4(opimm8, opm256, opzmm, opk, opzmm) + ctx.VINSERTI64X4_Z(opimm8, opm256, opzmm, opk, opzmm) + ctx.VINSERTPS(opimm8, opm32, opxmm, opxmm) + ctx.VLDDQU(opm128, opxmm) + ctx.VLDMXCSR(opm32) + ctx.VMASKMOVDQU(opxmm, opxmm) + ctx.VMASKMOVPD(opm128, opxmm, opxmm) + ctx.VMASKMOVPS(opm128, opxmm, opxmm) + ctx.VMAXPD(opm128, opxmm, opxmm) + ctx.VMAXPD_BCST(opm64, opxmm, opk, opxmm) + ctx.VMAXPD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VMAXPD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VMAXPD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VMAXPD_Z(opm128, opxmm, opk, opxmm) + ctx.VMAXPS(opm128, opxmm, opxmm) + ctx.VMAXPS_BCST(opm32, opxmm, opk, opxmm) + ctx.VMAXPS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VMAXPS_SAE(opzmm, opzmm, opk, opzmm) + ctx.VMAXPS_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VMAXPS_Z(opm128, opxmm, opk, opxmm) + ctx.VMAXSD(opm64, opxmm, opxmm) + ctx.VMAXSD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VMAXSD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VMAXSD_Z(opm64, opxmm, opk, opxmm) + ctx.VMAXSS(opm32, opxmm, opxmm) + ctx.VMAXSS_SAE(opxmm, opxmm, opk, opxmm) + ctx.VMAXSS_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VMAXSS_Z(opm32, opxmm, opk, opxmm) + ctx.VMINPD(opm128, opxmm, opxmm) + ctx.VMINPD_BCST(opm64, opxmm, opk, opxmm) + ctx.VMINPD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VMINPD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VMINPD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VMINPD_Z(opm128, opxmm, opk, opxmm) + ctx.VMINPS(opm128, opxmm, opxmm) + ctx.VMINPS_BCST(opm32, opxmm, opk, opxmm) + ctx.VMINPS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VMINPS_SAE(opzmm, opzmm, opk, opzmm) + ctx.VMINPS_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VMINPS_Z(opm128, opxmm, opk, opxmm) + ctx.VMINSD(opm64, opxmm, opxmm) + ctx.VMINSD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VMINSD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VMINSD_Z(opm64, opxmm, opk, opxmm) + ctx.VMINSS(opm32, opxmm, opxmm) + ctx.VMINSS_SAE(opxmm, opxmm, opk, opxmm) + ctx.VMINSS_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VMINSS_Z(opm32, opxmm, opk, opxmm) + ctx.VMOVAPD(opm128, opxmm) + ctx.VMOVAPD_Z(opm128, opk, opxmm) + ctx.VMOVAPS(opm128, opxmm) + ctx.VMOVAPS_Z(opm128, opk, opxmm) + ctx.VMOVD(opm32, opxmm) + ctx.VMOVDDUP(opm256, opymm) + ctx.VMOVDDUP_Z(opm256, opk, opymm) + ctx.VMOVDQA(opm128, opxmm) + ctx.VMOVDQA32(opm128, opk, opxmm) + ctx.VMOVDQA32_Z(opm128, opk, opxmm) + ctx.VMOVDQA64(opm128, opk, opxmm) + ctx.VMOVDQA64_Z(opm128, opk, opxmm) + ctx.VMOVDQU(opm128, opxmm) + ctx.VMOVDQU16(opm128, opk, opxmm) + ctx.VMOVDQU16_Z(opm128, opk, opxmm) + ctx.VMOVDQU32(opm128, opk, opxmm) + ctx.VMOVDQU32_Z(opm128, opk, opxmm) + ctx.VMOVDQU64(opm128, opk, opxmm) + ctx.VMOVDQU64_Z(opm128, opk, opxmm) + ctx.VMOVDQU8(opm128, opk, opxmm) + ctx.VMOVDQU8_Z(opm128, opk, opxmm) + ctx.VMOVHLPS(opxmm, opxmm, opxmm) + ctx.VMOVHPD(opm64, opxmm, opxmm) + ctx.VMOVHPS(opm64, opxmm, opxmm) + ctx.VMOVLHPS(opxmm, opxmm, opxmm) + ctx.VMOVLPD(opm64, opxmm, opxmm) + ctx.VMOVLPS(opm64, opxmm, opxmm) + ctx.VMOVMSKPD(opxmm, opr32) + ctx.VMOVMSKPS(opxmm, opr32) + ctx.VMOVNTDQ(opxmm, opm128) + ctx.VMOVNTDQA(opm256, opymm) + ctx.VMOVNTPD(opxmm, opm128) + ctx.VMOVNTPS(opxmm, opm128) + ctx.VMOVQ(opm64, opxmm) + ctx.VMOVSD(opm64, opxmm) + ctx.VMOVSD_Z(opm64, opk, opxmm) + ctx.VMOVSHDUP(opm128, opxmm) + ctx.VMOVSHDUP_Z(opm128, opk, opxmm) + ctx.VMOVSLDUP(opm128, opxmm) + ctx.VMOVSLDUP_Z(opm128, opk, opxmm) + ctx.VMOVSS(opm32, opxmm) + ctx.VMOVSS_Z(opm32, opk, opxmm) + ctx.VMOVUPD(opm128, opxmm) + ctx.VMOVUPD_Z(opm128, opk, opxmm) + ctx.VMOVUPS(opm128, opxmm) + ctx.VMOVUPS_Z(opm128, opk, opxmm) + ctx.VMPSADBW(opimm8, opm256, opymm, opymm) + ctx.VMULPD(opm128, opxmm, opxmm) + ctx.VMULPD_BCST(opm64, opxmm, opk, opxmm) + ctx.VMULPD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VMULPD_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VMULPD_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VMULPD_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VMULPD_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VMULPD_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VMULPD_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VMULPD_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VMULPD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VMULPD_Z(opm128, opxmm, opk, opxmm) + ctx.VMULPS(opm128, opxmm, opxmm) + ctx.VMULPS_BCST(opm32, opxmm, opk, opxmm) + ctx.VMULPS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VMULPS_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VMULPS_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VMULPS_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VMULPS_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VMULPS_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VMULPS_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VMULPS_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VMULPS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VMULPS_Z(opm128, opxmm, opk, opxmm) + ctx.VMULSD(opm64, opxmm, opxmm) + ctx.VMULSD_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VMULSD_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VMULSD_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VMULSD_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VMULSD_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VMULSD_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VMULSD_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VMULSD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VMULSD_Z(opm64, opxmm, opk, opxmm) + ctx.VMULSS(opm32, opxmm, opxmm) + ctx.VMULSS_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VMULSS_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VMULSS_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VMULSS_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VMULSS_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VMULSS_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VMULSS_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VMULSS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VMULSS_Z(opm32, opxmm, opk, opxmm) + ctx.VORPD(opm128, opxmm, opxmm) + ctx.VORPD_BCST(opm64, opxmm, opk, opxmm) + ctx.VORPD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VORPD_Z(opm128, opxmm, opk, opxmm) + ctx.VORPS(opm128, opxmm, opxmm) + ctx.VORPS_BCST(opm32, opxmm, opk, opxmm) + ctx.VORPS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VORPS_Z(opm128, opxmm, opk, opxmm) + ctx.VPABSB(opm256, opymm) + ctx.VPABSB_Z(opm128, opk, opxmm) + ctx.VPABSD(opm256, opymm) + ctx.VPABSD_BCST(opm32, opk, opxmm) + ctx.VPABSD_BCST_Z(opm32, opk, opxmm) + ctx.VPABSD_Z(opm128, opk, opxmm) + ctx.VPABSQ(opm128, opk, opxmm) + ctx.VPABSQ_BCST(opm64, opk, opxmm) + ctx.VPABSQ_BCST_Z(opm64, opk, opxmm) + ctx.VPABSQ_Z(opm128, opk, opxmm) + ctx.VPABSW(opm256, opymm) + ctx.VPABSW_Z(opm128, opk, opxmm) + ctx.VPACKSSDW(opm256, opymm, opymm) + ctx.VPACKSSDW_BCST(opm32, opxmm, opk, opxmm) + ctx.VPACKSSDW_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VPACKSSDW_Z(opm128, opxmm, opk, opxmm) + ctx.VPACKSSWB(opm256, opymm, opymm) + ctx.VPACKSSWB_Z(opm128, opxmm, opk, opxmm) + ctx.VPACKUSDW(opm256, opymm, opymm) + ctx.VPACKUSDW_BCST(opm32, opxmm, opk, opxmm) + ctx.VPACKUSDW_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VPACKUSDW_Z(opm128, opxmm, opk, opxmm) + ctx.VPACKUSWB(opm256, opymm, opymm) + ctx.VPACKUSWB_Z(opm128, opxmm, opk, opxmm) + ctx.VPADDB(opm256, opymm, opymm) + ctx.VPADDB_Z(opm128, opxmm, opk, opxmm) + ctx.VPADDD(opm256, opymm, opymm) + ctx.VPADDD_BCST(opm32, opxmm, opk, opxmm) + ctx.VPADDD_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VPADDD_Z(opm128, opxmm, opk, opxmm) + ctx.VPADDQ(opm256, opymm, opymm) + ctx.VPADDQ_BCST(opm64, opxmm, opk, opxmm) + ctx.VPADDQ_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VPADDQ_Z(opm128, opxmm, opk, opxmm) + ctx.VPADDSB(opm256, opymm, opymm) + ctx.VPADDSB_Z(opm128, opxmm, opk, opxmm) + ctx.VPADDSW(opm256, opymm, opymm) + ctx.VPADDSW_Z(opm128, opxmm, opk, opxmm) + ctx.VPADDUSB(opm256, opymm, opymm) + ctx.VPADDUSB_Z(opm128, opxmm, opk, opxmm) + ctx.VPADDUSW(opm256, opymm, opymm) + ctx.VPADDUSW_Z(opm128, opxmm, opk, opxmm) + ctx.VPADDW(opm256, opymm, opymm) + ctx.VPADDW_Z(opm128, opxmm, opk, opxmm) + ctx.VPALIGNR(opimm8, opm256, opymm, opymm) + ctx.VPALIGNR_Z(opimm8, opm128, opxmm, opk, opxmm) + ctx.VPAND(opm256, opymm, opymm) + ctx.VPANDD(opm128, opxmm, opk, opxmm) + ctx.VPANDD_BCST(opm32, opxmm, opk, opxmm) + ctx.VPANDD_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VPANDD_Z(opm128, opxmm, opk, opxmm) + ctx.VPANDN(opm256, opymm, opymm) + ctx.VPANDND(opm128, opxmm, opk, opxmm) + ctx.VPANDND_BCST(opm32, opxmm, opk, opxmm) + ctx.VPANDND_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VPANDND_Z(opm128, opxmm, opk, opxmm) + ctx.VPANDNQ(opm128, opxmm, opk, opxmm) + ctx.VPANDNQ_BCST(opm64, opxmm, opk, opxmm) + ctx.VPANDNQ_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VPANDNQ_Z(opm128, opxmm, opk, opxmm) + ctx.VPANDQ(opm128, opxmm, opk, opxmm) + ctx.VPANDQ_BCST(opm64, opxmm, opk, opxmm) + ctx.VPANDQ_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VPANDQ_Z(opm128, opxmm, opk, opxmm) + ctx.VPAVGB(opm256, opymm, opymm) + ctx.VPAVGB_Z(opm128, opxmm, opk, opxmm) + ctx.VPAVGW(opm256, opymm, opymm) + ctx.VPAVGW_Z(opm128, opxmm, opk, opxmm) + ctx.VPBLENDD(opimm8, opm128, opxmm, opxmm) + ctx.VPBLENDMB(opm128, opxmm, opk, opxmm) + ctx.VPBLENDMB_Z(opm128, opxmm, opk, opxmm) + ctx.VPBLENDMD(opm128, opxmm, opk, opxmm) + ctx.VPBLENDMD_BCST(opm32, opxmm, opk, opxmm) + ctx.VPBLENDMD_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VPBLENDMD_Z(opm128, opxmm, opk, opxmm) + ctx.VPBLENDMQ(opm128, opxmm, opk, opxmm) + ctx.VPBLENDMQ_BCST(opm64, opxmm, opk, opxmm) + ctx.VPBLENDMQ_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VPBLENDMQ_Z(opm128, opxmm, opk, opxmm) + ctx.VPBLENDMW(opm128, opxmm, opk, opxmm) + ctx.VPBLENDMW_Z(opm128, opxmm, opk, opxmm) + ctx.VPBLENDVB(opymm, opm256, opymm, opymm) + ctx.VPBLENDW(opimm8, opm256, opymm, opymm) + ctx.VPBROADCASTB(opm8, opxmm) + ctx.VPBROADCASTB_Z(opm8, opk, opxmm) + ctx.VPBROADCASTD(opm32, opxmm) + ctx.VPBROADCASTD_Z(opm32, opk, opxmm) + ctx.VPBROADCASTMB2Q(opk, opxmm) + ctx.VPBROADCASTMW2D(opk, opxmm) + ctx.VPBROADCASTQ(opm64, opxmm) + ctx.VPBROADCASTQ_Z(opm64, opk, opxmm) + ctx.VPBROADCASTW(opm16, opxmm) + ctx.VPBROADCASTW_Z(opm16, opk, opxmm) + ctx.VPCLMULQDQ(opimm8, opm128, opxmm, opxmm) + ctx.VPCMPB(opimm8, opm128, opxmm, opk, opk) + ctx.VPCMPD(opimm8, opm128, opxmm, opk, opk) + ctx.VPCMPD_BCST(opimm8, opm32, opxmm, opk, opk) + ctx.VPCMPEQB(opm256, opymm, opymm) + ctx.VPCMPEQD(opm256, opymm, opymm) + ctx.VPCMPEQD_BCST(opm32, opxmm, opk, opk) + ctx.VPCMPEQQ(opm256, opymm, opymm) + ctx.VPCMPEQQ_BCST(opm64, opxmm, opk, opk) + ctx.VPCMPEQW(opm256, opymm, opymm) + ctx.VPCMPESTRI(opimm8, opm128, opxmm) + ctx.VPCMPESTRM(opimm8, opm128, opxmm) + ctx.VPCMPGTB(opm256, opymm, opymm) + ctx.VPCMPGTD(opm256, opymm, opymm) + ctx.VPCMPGTD_BCST(opm32, opxmm, opk, opk) + ctx.VPCMPGTQ(opm256, opymm, opymm) + ctx.VPCMPGTQ_BCST(opm64, opxmm, opk, opk) + ctx.VPCMPGTW(opm256, opymm, opymm) + ctx.VPCMPISTRI(opimm8, opm128, opxmm) + ctx.VPCMPISTRM(opimm8, opm128, opxmm) + ctx.VPCMPQ(opimm8, opm128, opxmm, opk, opk) + ctx.VPCMPQ_BCST(opimm8, opm64, opxmm, opk, opk) + ctx.VPCMPUB(opimm8, opm128, opxmm, opk, opk) + ctx.VPCMPUD(opimm8, opm128, opxmm, opk, opk) + ctx.VPCMPUD_BCST(opimm8, opm32, opxmm, opk, opk) + ctx.VPCMPUQ(opimm8, opm128, opxmm, opk, opk) + ctx.VPCMPUQ_BCST(opimm8, opm64, opxmm, opk, opk) + ctx.VPCMPUW(opimm8, opm128, opxmm, opk, opk) + ctx.VPCMPW(opimm8, opm128, opxmm, opk, opk) + ctx.VPCOMPRESSD(opxmm, opk, opm128) + ctx.VPCOMPRESSD_Z(opxmm, opk, opm128) + ctx.VPCOMPRESSQ(opxmm, opk, opm128) + ctx.VPCOMPRESSQ_Z(opxmm, opk, opm128) + ctx.VPCONFLICTD(opm128, opk, opxmm) + ctx.VPCONFLICTD_BCST(opm32, opk, opxmm) + ctx.VPCONFLICTD_BCST_Z(opm32, opk, opxmm) + ctx.VPCONFLICTD_Z(opm128, opk, opxmm) + ctx.VPCONFLICTQ(opm128, opk, opxmm) + ctx.VPCONFLICTQ_BCST(opm64, opk, opxmm) + ctx.VPCONFLICTQ_BCST_Z(opm64, opk, opxmm) + ctx.VPCONFLICTQ_Z(opm128, opk, opxmm) + ctx.VPERM2F128(opimm8, opm256, opymm, opymm) + ctx.VPERM2I128(opimm8, opm256, opymm, opymm) + ctx.VPERMB(opm128, opxmm, opk, opxmm) + ctx.VPERMB_Z(opm128, opxmm, opk, opxmm) + ctx.VPERMD(opm256, opymm, opymm) + ctx.VPERMD_BCST(opm32, opymm, opk, opymm) + ctx.VPERMD_BCST_Z(opm32, opymm, opk, opymm) + ctx.VPERMD_Z(opm256, opymm, opk, opymm) + ctx.VPERMI2B(opm128, opxmm, opk, opxmm) + ctx.VPERMI2B_Z(opm128, opxmm, opk, opxmm) + ctx.VPERMI2D(opm128, opxmm, opk, opxmm) + ctx.VPERMI2D_BCST(opm32, opxmm, opk, opxmm) + ctx.VPERMI2D_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VPERMI2D_Z(opm128, opxmm, opk, opxmm) + ctx.VPERMI2PD(opm128, opxmm, opk, opxmm) + ctx.VPERMI2PD_BCST(opm64, opxmm, opk, opxmm) + ctx.VPERMI2PD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VPERMI2PD_Z(opm128, opxmm, opk, opxmm) + ctx.VPERMI2PS(opm128, opxmm, opk, opxmm) + ctx.VPERMI2PS_BCST(opm32, opxmm, opk, opxmm) + ctx.VPERMI2PS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VPERMI2PS_Z(opm128, opxmm, opk, opxmm) + ctx.VPERMI2Q(opm128, opxmm, opk, opxmm) + ctx.VPERMI2Q_BCST(opm64, opxmm, opk, opxmm) + ctx.VPERMI2Q_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VPERMI2Q_Z(opm128, opxmm, opk, opxmm) + ctx.VPERMI2W(opm128, opxmm, opk, opxmm) + ctx.VPERMI2W_Z(opm128, opxmm, opk, opxmm) + ctx.VPERMILPD(opimm8, opm128, opxmm) + ctx.VPERMILPD_BCST(opimm8, opm64, opk, opxmm) + ctx.VPERMILPD_BCST_Z(opimm8, opm64, opk, opxmm) + ctx.VPERMILPD_Z(opimm8, opm128, opk, opxmm) + ctx.VPERMILPS(opimm8, opm128, opxmm) + ctx.VPERMILPS_BCST(opimm8, opm32, opk, opxmm) + ctx.VPERMILPS_BCST_Z(opimm8, opm32, opk, opxmm) + ctx.VPERMILPS_Z(opimm8, opm128, opk, opxmm) + ctx.VPERMPD(opimm8, opm256, opymm) + ctx.VPERMPD_BCST(opimm8, opm64, opk, opymm) + ctx.VPERMPD_BCST_Z(opimm8, opm64, opk, opymm) + ctx.VPERMPD_Z(opimm8, opm256, opk, opymm) + ctx.VPERMPS(opm256, opymm, opymm) + ctx.VPERMPS_BCST(opm32, opymm, opk, opymm) + ctx.VPERMPS_BCST_Z(opm32, opymm, opk, opymm) + ctx.VPERMPS_Z(opm256, opymm, opk, opymm) + ctx.VPERMQ(opimm8, opm256, opymm) + ctx.VPERMQ_BCST(opimm8, opm64, opk, opymm) + ctx.VPERMQ_BCST_Z(opimm8, opm64, opk, opymm) + ctx.VPERMQ_Z(opimm8, opm256, opk, opymm) + ctx.VPERMT2B(opm128, opxmm, opk, opxmm) + ctx.VPERMT2B_Z(opm128, opxmm, opk, opxmm) + ctx.VPERMT2D(opm128, opxmm, opk, opxmm) + ctx.VPERMT2D_BCST(opm32, opxmm, opk, opxmm) + ctx.VPERMT2D_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VPERMT2D_Z(opm128, opxmm, opk, opxmm) + ctx.VPERMT2PD(opm128, opxmm, opk, opxmm) + ctx.VPERMT2PD_BCST(opm64, opxmm, opk, opxmm) + ctx.VPERMT2PD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VPERMT2PD_Z(opm128, opxmm, opk, opxmm) + ctx.VPERMT2PS(opm128, opxmm, opk, opxmm) + ctx.VPERMT2PS_BCST(opm32, opxmm, opk, opxmm) + ctx.VPERMT2PS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VPERMT2PS_Z(opm128, opxmm, opk, opxmm) + ctx.VPERMT2Q(opm128, opxmm, opk, opxmm) + ctx.VPERMT2Q_BCST(opm64, opxmm, opk, opxmm) + ctx.VPERMT2Q_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VPERMT2Q_Z(opm128, opxmm, opk, opxmm) + ctx.VPERMT2W(opm128, opxmm, opk, opxmm) + ctx.VPERMT2W_Z(opm128, opxmm, opk, opxmm) + ctx.VPERMW(opm128, opxmm, opk, opxmm) + ctx.VPERMW_Z(opm128, opxmm, opk, opxmm) + ctx.VPEXPANDD(opm128, opk, opxmm) + ctx.VPEXPANDD_Z(opm128, opk, opxmm) + ctx.VPEXPANDQ(opm128, opk, opxmm) + ctx.VPEXPANDQ_Z(opm128, opk, opxmm) + ctx.VPEXTRB(opimm8, opxmm, opm8) + ctx.VPEXTRD(opimm8, opxmm, opm32) + ctx.VPEXTRQ(opimm8, opxmm, opm64) + ctx.VPEXTRW(opimm8, opxmm, opm16) + ctx.VPGATHERDD(opxmm, opvm32x, opxmm) + ctx.VPGATHERDQ(opxmm, opvm32x, opxmm) + ctx.VPGATHERQD(opxmm, opvm64x, opxmm) + ctx.VPGATHERQQ(opxmm, opvm64x, opxmm) + ctx.VPHADDD(opm256, opymm, opymm) + ctx.VPHADDSW(opm256, opymm, opymm) + ctx.VPHADDW(opm256, opymm, opymm) + ctx.VPHMINPOSUW(opm128, opxmm) + ctx.VPHSUBD(opm256, opymm, opymm) + ctx.VPHSUBSW(opm256, opymm, opymm) + ctx.VPHSUBW(opm256, opymm, opymm) + ctx.VPINSRB(opimm8, opm8, opxmm, opxmm) + ctx.VPINSRD(opimm8, opm32, opxmm, opxmm) + ctx.VPINSRQ(opimm8, opm64, opxmm, opxmm) + ctx.VPINSRW(opimm8, opm16, opxmm, opxmm) + ctx.VPLZCNTD(opm128, opk, opxmm) + ctx.VPLZCNTD_BCST(opm32, opk, opxmm) + ctx.VPLZCNTD_BCST_Z(opm32, opk, opxmm) + ctx.VPLZCNTD_Z(opm128, opk, opxmm) + ctx.VPLZCNTQ(opm128, opk, opxmm) + ctx.VPLZCNTQ_BCST(opm64, opk, opxmm) + ctx.VPLZCNTQ_BCST_Z(opm64, opk, opxmm) + ctx.VPLZCNTQ_Z(opm128, opk, opxmm) + ctx.VPMADD52HUQ(opm128, opxmm, opk, opxmm) + ctx.VPMADD52HUQ_BCST(opm64, opxmm, opk, opxmm) + ctx.VPMADD52HUQ_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VPMADD52HUQ_Z(opm128, opxmm, opk, opxmm) + ctx.VPMADD52LUQ(opm128, opxmm, opk, opxmm) + ctx.VPMADD52LUQ_BCST(opm64, opxmm, opk, opxmm) + ctx.VPMADD52LUQ_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VPMADD52LUQ_Z(opm128, opxmm, opk, opxmm) + ctx.VPMADDUBSW(opm256, opymm, opymm) + ctx.VPMADDUBSW_Z(opm128, opxmm, opk, opxmm) + ctx.VPMADDWD(opm256, opymm, opymm) + ctx.VPMADDWD_Z(opm128, opxmm, opk, opxmm) + ctx.VPMASKMOVD(opm128, opxmm, opxmm) + ctx.VPMASKMOVQ(opm128, opxmm, opxmm) + ctx.VPMAXSB(opm256, opymm, opymm) + ctx.VPMAXSB_Z(opm128, opxmm, opk, opxmm) + ctx.VPMAXSD(opm256, opymm, opymm) + ctx.VPMAXSD_BCST(opm32, opxmm, opk, opxmm) + ctx.VPMAXSD_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VPMAXSD_Z(opm128, opxmm, opk, opxmm) + ctx.VPMAXSQ(opm128, opxmm, opk, opxmm) + ctx.VPMAXSQ_BCST(opm64, opxmm, opk, opxmm) + ctx.VPMAXSQ_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VPMAXSQ_Z(opm128, opxmm, opk, opxmm) + ctx.VPMAXSW(opm256, opymm, opymm) + ctx.VPMAXSW_Z(opm128, opxmm, opk, opxmm) + ctx.VPMAXUB(opm256, opymm, opymm) + ctx.VPMAXUB_Z(opm128, opxmm, opk, opxmm) + ctx.VPMAXUD(opm256, opymm, opymm) + ctx.VPMAXUD_BCST(opm32, opxmm, opk, opxmm) + ctx.VPMAXUD_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VPMAXUD_Z(opm128, opxmm, opk, opxmm) + ctx.VPMAXUQ(opm128, opxmm, opk, opxmm) + ctx.VPMAXUQ_BCST(opm64, opxmm, opk, opxmm) + ctx.VPMAXUQ_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VPMAXUQ_Z(opm128, opxmm, opk, opxmm) + ctx.VPMAXUW(opm256, opymm, opymm) + ctx.VPMAXUW_Z(opm128, opxmm, opk, opxmm) + ctx.VPMINSB(opm256, opymm, opymm) + ctx.VPMINSB_Z(opm128, opxmm, opk, opxmm) + ctx.VPMINSD(opm256, opymm, opymm) + ctx.VPMINSD_BCST(opm32, opxmm, opk, opxmm) + ctx.VPMINSD_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VPMINSD_Z(opm128, opxmm, opk, opxmm) + ctx.VPMINSQ(opm128, opxmm, opk, opxmm) + ctx.VPMINSQ_BCST(opm64, opxmm, opk, opxmm) + ctx.VPMINSQ_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VPMINSQ_Z(opm128, opxmm, opk, opxmm) + ctx.VPMINSW(opm256, opymm, opymm) + ctx.VPMINSW_Z(opm128, opxmm, opk, opxmm) + ctx.VPMINUB(opm256, opymm, opymm) + ctx.VPMINUB_Z(opm128, opxmm, opk, opxmm) + ctx.VPMINUD(opm256, opymm, opymm) + ctx.VPMINUD_BCST(opm32, opxmm, opk, opxmm) + ctx.VPMINUD_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VPMINUD_Z(opm128, opxmm, opk, opxmm) + ctx.VPMINUQ(opm128, opxmm, opk, opxmm) + ctx.VPMINUQ_BCST(opm64, opxmm, opk, opxmm) + ctx.VPMINUQ_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VPMINUQ_Z(opm128, opxmm, opk, opxmm) + ctx.VPMINUW(opm256, opymm, opymm) + ctx.VPMINUW_Z(opm128, opxmm, opk, opxmm) + ctx.VPMOVB2M(opxmm, opk) + ctx.VPMOVD2M(opxmm, opk) + ctx.VPMOVDB(opxmm, opk, opm32) + ctx.VPMOVDB_Z(opxmm, opk, opm32) + ctx.VPMOVDW(opxmm, opk, opm64) + ctx.VPMOVDW_Z(opxmm, opk, opm64) + ctx.VPMOVM2B(opk, opxmm) + ctx.VPMOVM2D(opk, opxmm) + ctx.VPMOVM2Q(opk, opxmm) + ctx.VPMOVM2W(opk, opxmm) + ctx.VPMOVMSKB(opymm, opr32) + ctx.VPMOVQ2M(opxmm, opk) + ctx.VPMOVQB(opxmm, opk, opm16) + ctx.VPMOVQB_Z(opxmm, opk, opm16) + ctx.VPMOVQD(opxmm, opk, opm64) + ctx.VPMOVQD_Z(opxmm, opk, opm64) + ctx.VPMOVQW(opxmm, opk, opm32) + ctx.VPMOVQW_Z(opxmm, opk, opm32) + ctx.VPMOVSDB(opxmm, opk, opm32) + ctx.VPMOVSDB_Z(opxmm, opk, opm32) + ctx.VPMOVSDW(opxmm, opk, opm64) + ctx.VPMOVSDW_Z(opxmm, opk, opm64) + ctx.VPMOVSQB(opxmm, opk, opm16) + ctx.VPMOVSQB_Z(opxmm, opk, opm16) + ctx.VPMOVSQD(opxmm, opk, opm64) + ctx.VPMOVSQD_Z(opxmm, opk, opm64) + ctx.VPMOVSQW(opxmm, opk, opm32) + ctx.VPMOVSQW_Z(opxmm, opk, opm32) + ctx.VPMOVSWB(opxmm, opk, opm64) + ctx.VPMOVSWB_Z(opxmm, opk, opm64) + ctx.VPMOVSXBD(opm64, opymm) + ctx.VPMOVSXBD_Z(opm32, opk, opxmm) + ctx.VPMOVSXBQ(opm32, opymm) + ctx.VPMOVSXBQ_Z(opm16, opk, opxmm) + ctx.VPMOVSXBW(opm128, opymm) + ctx.VPMOVSXBW_Z(opm128, opk, opymm) + ctx.VPMOVSXDQ(opm128, opymm) + ctx.VPMOVSXDQ_Z(opm128, opk, opymm) + ctx.VPMOVSXWD(opm128, opymm) + ctx.VPMOVSXWD_Z(opm128, opk, opymm) + ctx.VPMOVSXWQ(opm64, opymm) + ctx.VPMOVSXWQ_Z(opm32, opk, opxmm) + ctx.VPMOVUSDB(opxmm, opk, opm32) + ctx.VPMOVUSDB_Z(opxmm, opk, opm32) + ctx.VPMOVUSDW(opxmm, opk, opm64) + ctx.VPMOVUSDW_Z(opxmm, opk, opm64) + ctx.VPMOVUSQB(opxmm, opk, opm16) + ctx.VPMOVUSQB_Z(opxmm, opk, opm16) + ctx.VPMOVUSQD(opxmm, opk, opm64) + ctx.VPMOVUSQD_Z(opxmm, opk, opm64) + ctx.VPMOVUSQW(opxmm, opk, opm32) + ctx.VPMOVUSQW_Z(opxmm, opk, opm32) + ctx.VPMOVUSWB(opxmm, opk, opm64) + ctx.VPMOVUSWB_Z(opxmm, opk, opm64) + ctx.VPMOVW2M(opxmm, opk) + ctx.VPMOVWB(opxmm, opk, opm64) + ctx.VPMOVWB_Z(opxmm, opk, opm64) + ctx.VPMOVZXBD(opm64, opymm) + ctx.VPMOVZXBD_Z(opm32, opk, opxmm) + ctx.VPMOVZXBQ(opm32, opymm) + ctx.VPMOVZXBQ_Z(opm16, opk, opxmm) + ctx.VPMOVZXBW(opm128, opymm) + ctx.VPMOVZXBW_Z(opm128, opk, opymm) + ctx.VPMOVZXDQ(opm128, opymm) + ctx.VPMOVZXDQ_Z(opm128, opk, opymm) + ctx.VPMOVZXWD(opm128, opymm) + ctx.VPMOVZXWD_Z(opm128, opk, opymm) + ctx.VPMOVZXWQ(opm64, opymm) + ctx.VPMOVZXWQ_Z(opm32, opk, opxmm) + ctx.VPMULDQ(opm256, opymm, opymm) + ctx.VPMULDQ_BCST(opm64, opxmm, opk, opxmm) + ctx.VPMULDQ_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VPMULDQ_Z(opm128, opxmm, opk, opxmm) + ctx.VPMULHRSW(opm256, opymm, opymm) + ctx.VPMULHRSW_Z(opm128, opxmm, opk, opxmm) + ctx.VPMULHUW(opm256, opymm, opymm) + ctx.VPMULHUW_Z(opm128, opxmm, opk, opxmm) + ctx.VPMULHW(opm256, opymm, opymm) + ctx.VPMULHW_Z(opm128, opxmm, opk, opxmm) + ctx.VPMULLD(opm256, opymm, opymm) + ctx.VPMULLD_BCST(opm32, opxmm, opk, opxmm) + ctx.VPMULLD_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VPMULLD_Z(opm128, opxmm, opk, opxmm) + ctx.VPMULLQ(opm128, opxmm, opk, opxmm) + ctx.VPMULLQ_BCST(opm64, opxmm, opk, opxmm) + ctx.VPMULLQ_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VPMULLQ_Z(opm128, opxmm, opk, opxmm) + ctx.VPMULLW(opm256, opymm, opymm) + ctx.VPMULLW_Z(opm128, opxmm, opk, opxmm) + ctx.VPMULTISHIFTQB(opm128, opxmm, opk, opxmm) + ctx.VPMULTISHIFTQB_BCST(opm64, opxmm, opk, opxmm) + ctx.VPMULTISHIFTQB_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VPMULTISHIFTQB_Z(opm128, opxmm, opk, opxmm) + ctx.VPMULUDQ(opm256, opymm, opymm) + ctx.VPMULUDQ_BCST(opm64, opxmm, opk, opxmm) + ctx.VPMULUDQ_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VPMULUDQ_Z(opm128, opxmm, opk, opxmm) + ctx.VPOPCNTD(opm512, opk, opzmm) + ctx.VPOPCNTD_BCST(opm32, opk, opzmm) + ctx.VPOPCNTD_BCST_Z(opm32, opk, opzmm) + ctx.VPOPCNTD_Z(opm512, opk, opzmm) + ctx.VPOPCNTQ(opm512, opk, opzmm) + ctx.VPOPCNTQ_BCST(opm64, opk, opzmm) + ctx.VPOPCNTQ_BCST_Z(opm64, opk, opzmm) + ctx.VPOPCNTQ_Z(opm512, opk, opzmm) + ctx.VPOR(opm256, opymm, opymm) + ctx.VPORD(opm128, opxmm, opk, opxmm) + ctx.VPORD_BCST(opm32, opxmm, opk, opxmm) + ctx.VPORD_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VPORD_Z(opm128, opxmm, opk, opxmm) + ctx.VPORQ(opm128, opxmm, opk, opxmm) + ctx.VPORQ_BCST(opm64, opxmm, opk, opxmm) + ctx.VPORQ_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VPORQ_Z(opm128, opxmm, opk, opxmm) + ctx.VPROLD(opimm8, opm128, opk, opxmm) + ctx.VPROLD_BCST(opimm8, opm32, opk, opxmm) + ctx.VPROLD_BCST_Z(opimm8, opm32, opk, opxmm) + ctx.VPROLD_Z(opimm8, opm128, opk, opxmm) + ctx.VPROLQ(opimm8, opm128, opk, opxmm) + ctx.VPROLQ_BCST(opimm8, opm64, opk, opxmm) + ctx.VPROLQ_BCST_Z(opimm8, opm64, opk, opxmm) + ctx.VPROLQ_Z(opimm8, opm128, opk, opxmm) + ctx.VPROLVD(opm128, opxmm, opk, opxmm) + ctx.VPROLVD_BCST(opm32, opxmm, opk, opxmm) + ctx.VPROLVD_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VPROLVD_Z(opm128, opxmm, opk, opxmm) + ctx.VPROLVQ(opm128, opxmm, opk, opxmm) + ctx.VPROLVQ_BCST(opm64, opxmm, opk, opxmm) + ctx.VPROLVQ_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VPROLVQ_Z(opm128, opxmm, opk, opxmm) + ctx.VPRORD(opimm8, opm128, opk, opxmm) + ctx.VPRORD_BCST(opimm8, opm32, opk, opxmm) + ctx.VPRORD_BCST_Z(opimm8, opm32, opk, opxmm) + ctx.VPRORD_Z(opimm8, opm128, opk, opxmm) + ctx.VPRORQ(opimm8, opm128, opk, opxmm) + ctx.VPRORQ_BCST(opimm8, opm64, opk, opxmm) + ctx.VPRORQ_BCST_Z(opimm8, opm64, opk, opxmm) + ctx.VPRORQ_Z(opimm8, opm128, opk, opxmm) + ctx.VPRORVD(opm128, opxmm, opk, opxmm) + ctx.VPRORVD_BCST(opm32, opxmm, opk, opxmm) + ctx.VPRORVD_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VPRORVD_Z(opm128, opxmm, opk, opxmm) + ctx.VPRORVQ(opm128, opxmm, opk, opxmm) + ctx.VPRORVQ_BCST(opm64, opxmm, opk, opxmm) + ctx.VPRORVQ_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VPRORVQ_Z(opm128, opxmm, opk, opxmm) + ctx.VPSADBW(opm256, opymm, opymm) + ctx.VPSCATTERDD(opxmm, opk, opvm32x) + ctx.VPSCATTERDQ(opxmm, opk, opvm32x) + ctx.VPSCATTERQD(opxmm, opk, opvm64x) + ctx.VPSCATTERQQ(opxmm, opk, opvm64x) + ctx.VPSHUFB(opm256, opymm, opymm) + ctx.VPSHUFB_Z(opm128, opxmm, opk, opxmm) + ctx.VPSHUFD(opimm8, opm256, opymm) + ctx.VPSHUFD_BCST(opimm8, opm32, opk, opxmm) + ctx.VPSHUFD_BCST_Z(opimm8, opm32, opk, opxmm) + ctx.VPSHUFD_Z(opimm8, opm128, opk, opxmm) + ctx.VPSHUFHW(opimm8, opm256, opymm) + ctx.VPSHUFHW_Z(opimm8, opm128, opk, opxmm) + ctx.VPSHUFLW(opimm8, opm256, opymm) + ctx.VPSHUFLW_Z(opimm8, opm128, opk, opxmm) + ctx.VPSIGNB(opm256, opymm, opymm) + ctx.VPSIGND(opm256, opymm, opymm) + ctx.VPSIGNW(opm256, opymm, opymm) + ctx.VPSLLD(opimm8, opymm, opymm) + ctx.VPSLLDQ(opimm8, opymm, opymm) + ctx.VPSLLD_BCST(opimm8, opm32, opk, opxmm) + ctx.VPSLLD_BCST_Z(opimm8, opm32, opk, opxmm) + ctx.VPSLLD_Z(opimm8, opm128, opk, opxmm) + ctx.VPSLLQ(opimm8, opymm, opymm) + ctx.VPSLLQ_BCST(opimm8, opm64, opk, opxmm) + ctx.VPSLLQ_BCST_Z(opimm8, opm64, opk, opxmm) + ctx.VPSLLQ_Z(opimm8, opm128, opk, opxmm) + ctx.VPSLLVD(opm128, opxmm, opxmm) + ctx.VPSLLVD_BCST(opm32, opxmm, opk, opxmm) + ctx.VPSLLVD_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VPSLLVD_Z(opm128, opxmm, opk, opxmm) + ctx.VPSLLVQ(opm128, opxmm, opxmm) + ctx.VPSLLVQ_BCST(opm64, opxmm, opk, opxmm) + ctx.VPSLLVQ_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VPSLLVQ_Z(opm128, opxmm, opk, opxmm) + ctx.VPSLLVW(opm128, opxmm, opk, opxmm) + ctx.VPSLLVW_Z(opm128, opxmm, opk, opxmm) + ctx.VPSLLW(opimm8, opymm, opymm) + ctx.VPSLLW_Z(opimm8, opm128, opk, opxmm) + ctx.VPSRAD(opimm8, opymm, opymm) + ctx.VPSRAD_BCST(opimm8, opm32, opk, opxmm) + ctx.VPSRAD_BCST_Z(opimm8, opm32, opk, opxmm) + ctx.VPSRAD_Z(opimm8, opm128, opk, opxmm) + ctx.VPSRAQ(opimm8, opm128, opk, opxmm) + ctx.VPSRAQ_BCST(opimm8, opm64, opk, opxmm) + ctx.VPSRAQ_BCST_Z(opimm8, opm64, opk, opxmm) + ctx.VPSRAQ_Z(opimm8, opm128, opk, opxmm) + ctx.VPSRAVD(opm128, opxmm, opxmm) + ctx.VPSRAVD_BCST(opm32, opxmm, opk, opxmm) + ctx.VPSRAVD_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VPSRAVD_Z(opm128, opxmm, opk, opxmm) + ctx.VPSRAVQ(opm128, opxmm, opk, opxmm) + ctx.VPSRAVQ_BCST(opm64, opxmm, opk, opxmm) + ctx.VPSRAVQ_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VPSRAVQ_Z(opm128, opxmm, opk, opxmm) + ctx.VPSRAVW(opm128, opxmm, opk, opxmm) + ctx.VPSRAVW_Z(opm128, opxmm, opk, opxmm) + ctx.VPSRAW(opimm8, opymm, opymm) + ctx.VPSRAW_Z(opimm8, opm128, opk, opxmm) + ctx.VPSRLD(opimm8, opymm, opymm) + ctx.VPSRLDQ(opimm8, opymm, opymm) + ctx.VPSRLD_BCST(opimm8, opm32, opk, opxmm) + ctx.VPSRLD_BCST_Z(opimm8, opm32, opk, opxmm) + ctx.VPSRLD_Z(opimm8, opm128, opk, opxmm) + ctx.VPSRLQ(opimm8, opymm, opymm) + ctx.VPSRLQ_BCST(opimm8, opm64, opk, opxmm) + ctx.VPSRLQ_BCST_Z(opimm8, opm64, opk, opxmm) + ctx.VPSRLQ_Z(opimm8, opm128, opk, opxmm) + ctx.VPSRLVD(opm128, opxmm, opxmm) + ctx.VPSRLVD_BCST(opm32, opxmm, opk, opxmm) + ctx.VPSRLVD_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VPSRLVD_Z(opm128, opxmm, opk, opxmm) + ctx.VPSRLVQ(opm128, opxmm, opxmm) + ctx.VPSRLVQ_BCST(opm64, opxmm, opk, opxmm) + ctx.VPSRLVQ_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VPSRLVQ_Z(opm128, opxmm, opk, opxmm) + ctx.VPSRLVW(opm128, opxmm, opk, opxmm) + ctx.VPSRLVW_Z(opm128, opxmm, opk, opxmm) + ctx.VPSRLW(opimm8, opymm, opymm) + ctx.VPSRLW_Z(opimm8, opm128, opk, opxmm) + ctx.VPSUBB(opm256, opymm, opymm) + ctx.VPSUBB_Z(opm128, opxmm, opk, opxmm) + ctx.VPSUBD(opm256, opymm, opymm) + ctx.VPSUBD_BCST(opm32, opxmm, opk, opxmm) + ctx.VPSUBD_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VPSUBD_Z(opm128, opxmm, opk, opxmm) + ctx.VPSUBQ(opm256, opymm, opymm) + ctx.VPSUBQ_BCST(opm64, opxmm, opk, opxmm) + ctx.VPSUBQ_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VPSUBQ_Z(opm128, opxmm, opk, opxmm) + ctx.VPSUBSB(opm256, opymm, opymm) + ctx.VPSUBSB_Z(opm128, opxmm, opk, opxmm) + ctx.VPSUBSW(opm256, opymm, opymm) + ctx.VPSUBSW_Z(opm128, opxmm, opk, opxmm) + ctx.VPSUBUSB(opm256, opymm, opymm) + ctx.VPSUBUSB_Z(opm128, opxmm, opk, opxmm) + ctx.VPSUBUSW(opm256, opymm, opymm) + ctx.VPSUBUSW_Z(opm128, opxmm, opk, opxmm) + ctx.VPSUBW(opm256, opymm, opymm) + ctx.VPSUBW_Z(opm128, opxmm, opk, opxmm) + ctx.VPTERNLOGD(opimm8, opm128, opxmm, opk, opxmm) + ctx.VPTERNLOGD_BCST(opimm8, opm32, opxmm, opk, opxmm) + ctx.VPTERNLOGD_BCST_Z(opimm8, opm32, opxmm, opk, opxmm) + ctx.VPTERNLOGD_Z(opimm8, opm128, opxmm, opk, opxmm) + ctx.VPTERNLOGQ(opimm8, opm128, opxmm, opk, opxmm) + ctx.VPTERNLOGQ_BCST(opimm8, opm64, opxmm, opk, opxmm) + ctx.VPTERNLOGQ_BCST_Z(opimm8, opm64, opxmm, opk, opxmm) + ctx.VPTERNLOGQ_Z(opimm8, opm128, opxmm, opk, opxmm) + ctx.VPTEST(opm128, opxmm) + ctx.VPTESTMB(opm128, opxmm, opk, opk) + ctx.VPTESTMD(opm128, opxmm, opk, opk) + ctx.VPTESTMD_BCST(opm32, opxmm, opk, opk) + ctx.VPTESTMQ(opm128, opxmm, opk, opk) + ctx.VPTESTMQ_BCST(opm64, opxmm, opk, opk) + ctx.VPTESTMW(opm128, opxmm, opk, opk) + ctx.VPTESTNMB(opm512, opzmm, opk, opk) + ctx.VPTESTNMD(opm128, opxmm, opk, opk) + ctx.VPTESTNMD_BCST(opm32, opxmm, opk, opk) + ctx.VPTESTNMQ(opm128, opxmm, opk, opk) + ctx.VPTESTNMQ_BCST(opm64, opxmm, opk, opk) + ctx.VPTESTNMW(opm512, opzmm, opk, opk) + ctx.VPUNPCKHBW(opm256, opymm, opymm) + ctx.VPUNPCKHBW_Z(opm128, opxmm, opk, opxmm) + ctx.VPUNPCKHDQ(opm256, opymm, opymm) + ctx.VPUNPCKHDQ_BCST(opm32, opxmm, opk, opxmm) + ctx.VPUNPCKHDQ_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VPUNPCKHDQ_Z(opm128, opxmm, opk, opxmm) + ctx.VPUNPCKHQDQ(opm256, opymm, opymm) + ctx.VPUNPCKHQDQ_BCST(opm64, opxmm, opk, opxmm) + ctx.VPUNPCKHQDQ_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VPUNPCKHQDQ_Z(opm128, opxmm, opk, opxmm) + ctx.VPUNPCKHWD(opm256, opymm, opymm) + ctx.VPUNPCKHWD_Z(opm128, opxmm, opk, opxmm) + ctx.VPUNPCKLBW(opm256, opymm, opymm) + ctx.VPUNPCKLBW_Z(opm128, opxmm, opk, opxmm) + ctx.VPUNPCKLDQ(opm256, opymm, opymm) + ctx.VPUNPCKLDQ_BCST(opm32, opxmm, opk, opxmm) + ctx.VPUNPCKLDQ_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VPUNPCKLDQ_Z(opm128, opxmm, opk, opxmm) + ctx.VPUNPCKLQDQ(opm256, opymm, opymm) + ctx.VPUNPCKLQDQ_BCST(opm64, opxmm, opk, opxmm) + ctx.VPUNPCKLQDQ_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VPUNPCKLQDQ_Z(opm128, opxmm, opk, opxmm) + ctx.VPUNPCKLWD(opm256, opymm, opymm) + ctx.VPUNPCKLWD_Z(opm128, opxmm, opk, opxmm) + ctx.VPXOR(opm256, opymm, opymm) + ctx.VPXORD(opm128, opxmm, opk, opxmm) + ctx.VPXORD_BCST(opm32, opxmm, opk, opxmm) + ctx.VPXORD_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VPXORD_Z(opm128, opxmm, opk, opxmm) + ctx.VPXORQ(opm128, opxmm, opk, opxmm) + ctx.VPXORQ_BCST(opm64, opxmm, opk, opxmm) + ctx.VPXORQ_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VPXORQ_Z(opm128, opxmm, opk, opxmm) + ctx.VRANGEPD(opimm8, opm128, opxmm, opk, opxmm) + ctx.VRANGEPD_BCST(opimm8, opm64, opxmm, opk, opxmm) + ctx.VRANGEPD_BCST_Z(opimm8, opm64, opxmm, opk, opxmm) + ctx.VRANGEPD_SAE(opimm8, opzmm, opzmm, opk, opzmm) + ctx.VRANGEPD_SAE_Z(opimm8, opzmm, opzmm, opk, opzmm) + ctx.VRANGEPD_Z(opimm8, opm128, opxmm, opk, opxmm) + ctx.VRANGEPS(opimm8, opm128, opxmm, opk, opxmm) + ctx.VRANGEPS_BCST(opimm8, opm32, opxmm, opk, opxmm) + ctx.VRANGEPS_BCST_Z(opimm8, opm32, opxmm, opk, opxmm) + ctx.VRANGEPS_SAE(opimm8, opzmm, opzmm, opk, opzmm) + ctx.VRANGEPS_SAE_Z(opimm8, opzmm, opzmm, opk, opzmm) + ctx.VRANGEPS_Z(opimm8, opm128, opxmm, opk, opxmm) + ctx.VRANGESD(opimm8, opm64, opxmm, opk, opxmm) + ctx.VRANGESD_SAE(opimm8, opxmm, opxmm, opk, opxmm) + ctx.VRANGESD_SAE_Z(opimm8, opxmm, opxmm, opk, opxmm) + ctx.VRANGESD_Z(opimm8, opm64, opxmm, opk, opxmm) + ctx.VRANGESS(opimm8, opm32, opxmm, opk, opxmm) + ctx.VRANGESS_SAE(opimm8, opxmm, opxmm, opk, opxmm) + ctx.VRANGESS_SAE_Z(opimm8, opxmm, opxmm, opk, opxmm) + ctx.VRANGESS_Z(opimm8, opm32, opxmm, opk, opxmm) + ctx.VRCP14PD(opm128, opk, opxmm) + ctx.VRCP14PD_BCST(opm64, opk, opxmm) + ctx.VRCP14PD_BCST_Z(opm64, opk, opxmm) + ctx.VRCP14PD_Z(opm128, opk, opxmm) + ctx.VRCP14PS(opm128, opk, opxmm) + ctx.VRCP14PS_BCST(opm32, opk, opxmm) + ctx.VRCP14PS_BCST_Z(opm32, opk, opxmm) + ctx.VRCP14PS_Z(opm128, opk, opxmm) + ctx.VRCP14SD(opm64, opxmm, opk, opxmm) + ctx.VRCP14SD_Z(opm64, opxmm, opk, opxmm) + ctx.VRCP14SS(opm32, opxmm, opk, opxmm) + ctx.VRCP14SS_Z(opm32, opxmm, opk, opxmm) + ctx.VRCP28PD(opm512, opk, opzmm) + ctx.VRCP28PD_BCST(opm64, opk, opzmm) + ctx.VRCP28PD_BCST_Z(opm64, opk, opzmm) + ctx.VRCP28PD_SAE(opzmm, opk, opzmm) + ctx.VRCP28PD_SAE_Z(opzmm, opk, opzmm) + ctx.VRCP28PD_Z(opm512, opk, opzmm) + ctx.VRCP28PS(opm512, opk, opzmm) + ctx.VRCP28PS_BCST(opm32, opk, opzmm) + ctx.VRCP28PS_BCST_Z(opm32, opk, opzmm) + ctx.VRCP28PS_SAE(opzmm, opk, opzmm) + ctx.VRCP28PS_SAE_Z(opzmm, opk, opzmm) + ctx.VRCP28PS_Z(opm512, opk, opzmm) + ctx.VRCP28SD(opm64, opxmm, opk, opxmm) + ctx.VRCP28SD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VRCP28SD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VRCP28SD_Z(opm64, opxmm, opk, opxmm) + ctx.VRCP28SS(opm32, opxmm, opk, opxmm) + ctx.VRCP28SS_SAE(opxmm, opxmm, opk, opxmm) + ctx.VRCP28SS_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VRCP28SS_Z(opm32, opxmm, opk, opxmm) + ctx.VRCPPS(opm128, opxmm) + ctx.VRCPSS(opm32, opxmm, opxmm) + ctx.VREDUCEPD(opimm8, opm128, opk, opxmm) + ctx.VREDUCEPD_BCST(opimm8, opm64, opk, opxmm) + ctx.VREDUCEPD_BCST_Z(opimm8, opm64, opk, opxmm) + ctx.VREDUCEPD_Z(opimm8, opm128, opk, opxmm) + ctx.VREDUCEPS(opimm8, opm128, opk, opxmm) + ctx.VREDUCEPS_BCST(opimm8, opm32, opk, opxmm) + ctx.VREDUCEPS_BCST_Z(opimm8, opm32, opk, opxmm) + ctx.VREDUCEPS_Z(opimm8, opm128, opk, opxmm) + ctx.VREDUCESD(opimm8, opm64, opxmm, opk, opxmm) + ctx.VREDUCESD_Z(opimm8, opm64, opxmm, opk, opxmm) + ctx.VREDUCESS(opimm8, opm32, opxmm, opk, opxmm) + ctx.VREDUCESS_Z(opimm8, opm32, opxmm, opk, opxmm) + ctx.VRNDSCALEPD(opimm8, opm128, opk, opxmm) + ctx.VRNDSCALEPD_BCST(opimm8, opm64, opk, opxmm) + ctx.VRNDSCALEPD_BCST_Z(opimm8, opm64, opk, opxmm) + ctx.VRNDSCALEPD_SAE(opimm8, opzmm, opk, opzmm) + ctx.VRNDSCALEPD_SAE_Z(opimm8, opzmm, opk, opzmm) + ctx.VRNDSCALEPD_Z(opimm8, opm128, opk, opxmm) + ctx.VRNDSCALEPS(opimm8, opm128, opk, opxmm) + ctx.VRNDSCALEPS_BCST(opimm8, opm32, opk, opxmm) + ctx.VRNDSCALEPS_BCST_Z(opimm8, opm32, opk, opxmm) + ctx.VRNDSCALEPS_SAE(opimm8, opzmm, opk, opzmm) + ctx.VRNDSCALEPS_SAE_Z(opimm8, opzmm, opk, opzmm) + ctx.VRNDSCALEPS_Z(opimm8, opm128, opk, opxmm) + ctx.VRNDSCALESD(opimm8, opm64, opxmm, opk, opxmm) + ctx.VRNDSCALESD_SAE(opimm8, opxmm, opxmm, opk, opxmm) + ctx.VRNDSCALESD_SAE_Z(opimm8, opxmm, opxmm, opk, opxmm) + ctx.VRNDSCALESD_Z(opimm8, opm64, opxmm, opk, opxmm) + ctx.VRNDSCALESS(opimm8, opm32, opxmm, opk, opxmm) + ctx.VRNDSCALESS_SAE(opimm8, opxmm, opxmm, opk, opxmm) + ctx.VRNDSCALESS_SAE_Z(opimm8, opxmm, opxmm, opk, opxmm) + ctx.VRNDSCALESS_Z(opimm8, opm32, opxmm, opk, opxmm) + ctx.VROUNDPD(opimm8, opm128, opxmm) + ctx.VROUNDPS(opimm8, opm128, opxmm) + ctx.VROUNDSD(opimm8, opm64, opxmm, opxmm) + ctx.VROUNDSS(opimm8, opm32, opxmm, opxmm) + ctx.VRSQRT14PD(opm128, opk, opxmm) + ctx.VRSQRT14PD_BCST(opm64, opk, opxmm) + ctx.VRSQRT14PD_BCST_Z(opm64, opk, opxmm) + ctx.VRSQRT14PD_Z(opm128, opk, opxmm) + ctx.VRSQRT14PS(opm128, opk, opxmm) + ctx.VRSQRT14PS_BCST(opm32, opk, opxmm) + ctx.VRSQRT14PS_BCST_Z(opm32, opk, opxmm) + ctx.VRSQRT14PS_Z(opm128, opk, opxmm) + ctx.VRSQRT14SD(opm64, opxmm, opk, opxmm) + ctx.VRSQRT14SD_Z(opm64, opxmm, opk, opxmm) + ctx.VRSQRT14SS(opm32, opxmm, opk, opxmm) + ctx.VRSQRT14SS_Z(opm32, opxmm, opk, opxmm) + ctx.VRSQRT28PD(opm512, opk, opzmm) + ctx.VRSQRT28PD_BCST(opm64, opk, opzmm) + ctx.VRSQRT28PD_BCST_Z(opm64, opk, opzmm) + ctx.VRSQRT28PD_SAE(opzmm, opk, opzmm) + ctx.VRSQRT28PD_SAE_Z(opzmm, opk, opzmm) + ctx.VRSQRT28PD_Z(opm512, opk, opzmm) + ctx.VRSQRT28PS(opm512, opk, opzmm) + ctx.VRSQRT28PS_BCST(opm32, opk, opzmm) + ctx.VRSQRT28PS_BCST_Z(opm32, opk, opzmm) + ctx.VRSQRT28PS_SAE(opzmm, opk, opzmm) + ctx.VRSQRT28PS_SAE_Z(opzmm, opk, opzmm) + ctx.VRSQRT28PS_Z(opm512, opk, opzmm) + ctx.VRSQRT28SD(opm64, opxmm, opk, opxmm) + ctx.VRSQRT28SD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VRSQRT28SD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VRSQRT28SD_Z(opm64, opxmm, opk, opxmm) + ctx.VRSQRT28SS(opm32, opxmm, opk, opxmm) + ctx.VRSQRT28SS_SAE(opxmm, opxmm, opk, opxmm) + ctx.VRSQRT28SS_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VRSQRT28SS_Z(opm32, opxmm, opk, opxmm) + ctx.VRSQRTPS(opm128, opxmm) + ctx.VRSQRTSS(opm32, opxmm, opxmm) + ctx.VSCALEFPD(opm128, opxmm, opk, opxmm) + ctx.VSCALEFPD_BCST(opm64, opxmm, opk, opxmm) + ctx.VSCALEFPD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VSCALEFPD_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VSCALEFPD_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VSCALEFPD_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VSCALEFPD_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VSCALEFPD_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VSCALEFPD_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VSCALEFPD_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VSCALEFPD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VSCALEFPD_Z(opm128, opxmm, opk, opxmm) + ctx.VSCALEFPS(opm128, opxmm, opk, opxmm) + ctx.VSCALEFPS_BCST(opm32, opxmm, opk, opxmm) + ctx.VSCALEFPS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VSCALEFPS_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VSCALEFPS_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VSCALEFPS_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VSCALEFPS_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VSCALEFPS_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VSCALEFPS_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VSCALEFPS_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VSCALEFPS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VSCALEFPS_Z(opm128, opxmm, opk, opxmm) + ctx.VSCALEFSD(opm64, opxmm, opk, opxmm) + ctx.VSCALEFSD_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VSCALEFSD_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VSCALEFSD_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VSCALEFSD_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VSCALEFSD_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VSCALEFSD_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VSCALEFSD_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VSCALEFSD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VSCALEFSD_Z(opm64, opxmm, opk, opxmm) + ctx.VSCALEFSS(opm32, opxmm, opk, opxmm) + ctx.VSCALEFSS_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VSCALEFSS_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VSCALEFSS_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VSCALEFSS_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VSCALEFSS_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VSCALEFSS_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VSCALEFSS_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VSCALEFSS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VSCALEFSS_Z(opm32, opxmm, opk, opxmm) + ctx.VSCATTERDPD(opxmm, opk, opvm32x) + ctx.VSCATTERDPS(opxmm, opk, opvm32x) + ctx.VSCATTERQPD(opxmm, opk, opvm64x) + ctx.VSCATTERQPS(opxmm, opk, opvm64x) + ctx.VSHUFF32X4(opimm8, opm256, opymm, opk, opymm) + ctx.VSHUFF32X4_BCST(opimm8, opm32, opymm, opk, opymm) + ctx.VSHUFF32X4_BCST_Z(opimm8, opm32, opymm, opk, opymm) + ctx.VSHUFF32X4_Z(opimm8, opm256, opymm, opk, opymm) + ctx.VSHUFF64X2(opimm8, opm256, opymm, opk, opymm) + ctx.VSHUFF64X2_BCST(opimm8, opm64, opymm, opk, opymm) + ctx.VSHUFF64X2_BCST_Z(opimm8, opm64, opymm, opk, opymm) + ctx.VSHUFF64X2_Z(opimm8, opm256, opymm, opk, opymm) + ctx.VSHUFI32X4(opimm8, opm256, opymm, opk, opymm) + ctx.VSHUFI32X4_BCST(opimm8, opm32, opymm, opk, opymm) + ctx.VSHUFI32X4_BCST_Z(opimm8, opm32, opymm, opk, opymm) + ctx.VSHUFI32X4_Z(opimm8, opm256, opymm, opk, opymm) + ctx.VSHUFI64X2(opimm8, opm256, opymm, opk, opymm) + ctx.VSHUFI64X2_BCST(opimm8, opm64, opymm, opk, opymm) + ctx.VSHUFI64X2_BCST_Z(opimm8, opm64, opymm, opk, opymm) + ctx.VSHUFI64X2_Z(opimm8, opm256, opymm, opk, opymm) + ctx.VSHUFPD(opimm8, opm128, opxmm, opxmm) + ctx.VSHUFPD_BCST(opimm8, opm64, opxmm, opk, opxmm) + ctx.VSHUFPD_BCST_Z(opimm8, opm64, opxmm, opk, opxmm) + ctx.VSHUFPD_Z(opimm8, opm128, opxmm, opk, opxmm) + ctx.VSHUFPS(opimm8, opm128, opxmm, opxmm) + ctx.VSHUFPS_BCST(opimm8, opm32, opxmm, opk, opxmm) + ctx.VSHUFPS_BCST_Z(opimm8, opm32, opxmm, opk, opxmm) + ctx.VSHUFPS_Z(opimm8, opm128, opxmm, opk, opxmm) + ctx.VSQRTPD(opm128, opxmm) + ctx.VSQRTPD_BCST(opm32, opk, opxmm) + ctx.VSQRTPD_BCST_Z(opm32, opk, opxmm) + ctx.VSQRTPD_RD_SAE(opzmm, opk, opzmm) + ctx.VSQRTPD_RD_SAE_Z(opzmm, opk, opzmm) + ctx.VSQRTPD_RN_SAE(opzmm, opk, opzmm) + ctx.VSQRTPD_RN_SAE_Z(opzmm, opk, opzmm) + ctx.VSQRTPD_RU_SAE(opzmm, opk, opzmm) + ctx.VSQRTPD_RU_SAE_Z(opzmm, opk, opzmm) + ctx.VSQRTPD_RZ_SAE(opzmm, opk, opzmm) + ctx.VSQRTPD_RZ_SAE_Z(opzmm, opk, opzmm) + ctx.VSQRTPD_Z(opm128, opk, opxmm) + ctx.VSQRTPS(opm128, opxmm) + ctx.VSQRTPS_BCST(opm32, opk, opxmm) + ctx.VSQRTPS_BCST_Z(opm32, opk, opxmm) + ctx.VSQRTPS_RD_SAE(opzmm, opk, opzmm) + ctx.VSQRTPS_RD_SAE_Z(opzmm, opk, opzmm) + ctx.VSQRTPS_RN_SAE(opzmm, opk, opzmm) + ctx.VSQRTPS_RN_SAE_Z(opzmm, opk, opzmm) + ctx.VSQRTPS_RU_SAE(opzmm, opk, opzmm) + ctx.VSQRTPS_RU_SAE_Z(opzmm, opk, opzmm) + ctx.VSQRTPS_RZ_SAE(opzmm, opk, opzmm) + ctx.VSQRTPS_RZ_SAE_Z(opzmm, opk, opzmm) + ctx.VSQRTPS_Z(opm128, opk, opxmm) + ctx.VSQRTSD(opm64, opxmm, opxmm) + ctx.VSQRTSD_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VSQRTSD_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VSQRTSD_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VSQRTSD_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VSQRTSD_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VSQRTSD_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VSQRTSD_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VSQRTSD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VSQRTSD_Z(opm64, opxmm, opk, opxmm) + ctx.VSQRTSS(opm32, opxmm, opxmm) + ctx.VSQRTSS_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VSQRTSS_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VSQRTSS_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VSQRTSS_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VSQRTSS_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VSQRTSS_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VSQRTSS_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VSQRTSS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VSQRTSS_Z(opm32, opxmm, opk, opxmm) + ctx.VSTMXCSR(opm32) + ctx.VSUBPD(opm128, opxmm, opxmm) + ctx.VSUBPD_BCST(opm64, opxmm, opk, opxmm) + ctx.VSUBPD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VSUBPD_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VSUBPD_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VSUBPD_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VSUBPD_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VSUBPD_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VSUBPD_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VSUBPD_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VSUBPD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VSUBPD_Z(opm128, opxmm, opk, opxmm) + ctx.VSUBPS(opm128, opxmm, opxmm) + ctx.VSUBPS_BCST(opm32, opxmm, opk, opxmm) + ctx.VSUBPS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VSUBPS_RD_SAE(opzmm, opzmm, opk, opzmm) + ctx.VSUBPS_RD_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VSUBPS_RN_SAE(opzmm, opzmm, opk, opzmm) + ctx.VSUBPS_RN_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VSUBPS_RU_SAE(opzmm, opzmm, opk, opzmm) + ctx.VSUBPS_RU_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VSUBPS_RZ_SAE(opzmm, opzmm, opk, opzmm) + ctx.VSUBPS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm) + ctx.VSUBPS_Z(opm128, opxmm, opk, opxmm) + ctx.VSUBSD(opm64, opxmm, opxmm) + ctx.VSUBSD_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VSUBSD_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VSUBSD_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VSUBSD_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VSUBSD_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VSUBSD_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VSUBSD_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VSUBSD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VSUBSD_Z(opm64, opxmm, opk, opxmm) + ctx.VSUBSS(opm32, opxmm, opxmm) + ctx.VSUBSS_RD_SAE(opxmm, opxmm, opk, opxmm) + ctx.VSUBSS_RD_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VSUBSS_RN_SAE(opxmm, opxmm, opk, opxmm) + ctx.VSUBSS_RN_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VSUBSS_RU_SAE(opxmm, opxmm, opk, opxmm) + ctx.VSUBSS_RU_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VSUBSS_RZ_SAE(opxmm, opxmm, opk, opxmm) + ctx.VSUBSS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm) + ctx.VSUBSS_Z(opm32, opxmm, opk, opxmm) + ctx.VTESTPD(opm128, opxmm) + ctx.VTESTPS(opm128, opxmm) + ctx.VUCOMISD(opm64, opxmm) + ctx.VUCOMISD_SAE(opxmm, opxmm) + ctx.VUCOMISS(opm32, opxmm) + ctx.VUCOMISS_SAE(opxmm, opxmm) + ctx.VUNPCKHPD(opm128, opxmm, opxmm) + ctx.VUNPCKHPD_BCST(opm64, opxmm, opk, opxmm) + ctx.VUNPCKHPD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VUNPCKHPD_Z(opm128, opxmm, opk, opxmm) + ctx.VUNPCKHPS(opm128, opxmm, opxmm) + ctx.VUNPCKHPS_BCST(opm32, opxmm, opk, opxmm) + ctx.VUNPCKHPS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VUNPCKHPS_Z(opm128, opxmm, opk, opxmm) + ctx.VUNPCKLPD(opm128, opxmm, opxmm) + ctx.VUNPCKLPD_BCST(opm64, opxmm, opk, opxmm) + ctx.VUNPCKLPD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VUNPCKLPD_Z(opm128, opxmm, opk, opxmm) + ctx.VUNPCKLPS(opm128, opxmm, opxmm) + ctx.VUNPCKLPS_BCST(opm32, opxmm, opk, opxmm) + ctx.VUNPCKLPS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VUNPCKLPS_Z(opm128, opxmm, opk, opxmm) + ctx.VXORPD(opm128, opxmm, opxmm) + ctx.VXORPD_BCST(opm64, opxmm, opk, opxmm) + ctx.VXORPD_BCST_Z(opm64, opxmm, opk, opxmm) + ctx.VXORPD_Z(opm128, opxmm, opk, opxmm) + ctx.VXORPS(opm128, opxmm, opxmm) + ctx.VXORPS_BCST(opm32, opxmm, opk, opxmm) + ctx.VXORPS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VXORPS_Z(opm128, opxmm, opk, opxmm) + ctx.VZEROALL() + ctx.VZEROUPPER() + ctx.XADDB(opr8, opm8) + ctx.XADDL(opr32, opm32) + ctx.XADDQ(opr64, opm64) + ctx.XADDW(opr16, opm16) + ctx.XCHGB(opm8, opr8) + ctx.XCHGL(opeax, opr32) + ctx.XCHGQ(opm64, opr64) + ctx.XCHGW(opax, opr16) + ctx.XGETBV() + ctx.XLAT() + ctx.XORB(opimm8, opal) + ctx.XORL(opimm32, opeax) + ctx.XORPD(opm128, opxmm) + ctx.XORPS(opm128, opxmm) + ctx.XORQ(opimm32, opm64) + ctx.XORW(opimm16, opax) + if _, err := ctx.Result(); err != nil { + t.Fatal(err) + } +} diff --git a/build/zmov.go b/build/zmov.go index ca9bb554..2bb9d4cb 100644 --- a/build/zmov.go +++ b/build/zmov.go @@ -10,62 +10,262 @@ import ( func (c *Context) mov(a, b operand.Op, an, bn int, t *types.Basic) { switch { - case (t.Info()&types.IsInteger) != 0 && an == 1 && bn == 1: + case (t.Info()&types.IsInteger) != 0 && an == 8 && bn == 8 && operand.IsK(a) && operand.IsK(b): + c.KMOVB(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 8 && bn == 1 && operand.IsK(a) && operand.IsM8(b): + c.KMOVB(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 8 && bn == 4 && operand.IsK(a) && operand.IsR32(b): + c.KMOVB(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 1 && bn == 8 && operand.IsK(b) && operand.IsM8(a): + c.KMOVB(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 4 && bn == 8 && operand.IsK(b) && operand.IsR32(a): + c.KMOVB(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 8 && bn == 8 && operand.IsK(a) && operand.IsK(b): + c.KMOVD(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 8 && bn == 4 && operand.IsK(a) && operand.IsM32(b): + c.KMOVD(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 8 && bn == 4 && operand.IsK(a) && operand.IsR32(b): + c.KMOVD(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 4 && bn == 8 && operand.IsK(b) && operand.IsM32(a): + c.KMOVD(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 4 && bn == 8 && operand.IsK(b) && operand.IsR32(a): + c.KMOVD(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 8 && bn == 8 && operand.IsK(a) && operand.IsK(b): + c.KMOVQ(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 8 && bn == 8 && operand.IsK(a) && operand.IsM64(b): + c.KMOVQ(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 8 && bn == 8 && operand.IsK(a) && operand.IsR64(b): + c.KMOVQ(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 8 && bn == 8 && operand.IsK(b) && operand.IsM64(a): + c.KMOVQ(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 8 && bn == 8 && operand.IsK(b) && operand.IsR64(a): + c.KMOVQ(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 8 && bn == 8 && operand.IsK(a) && operand.IsK(b): + c.KMOVW(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 8 && bn == 2 && operand.IsK(a) && operand.IsM16(b): + c.KMOVW(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 8 && bn == 4 && operand.IsK(a) && operand.IsR32(b): + c.KMOVW(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 2 && bn == 8 && operand.IsK(b) && operand.IsM16(a): + c.KMOVW(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 4 && bn == 8 && operand.IsK(b) && operand.IsR32(a): + c.KMOVW(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 1 && bn == 1 && operand.IsM8(a) && operand.IsR8(b): c.MOVB(a, b) - case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) == 0 && an == 1 && bn == 4: + case (t.Info()&types.IsInteger) != 0 && an == 1 && bn == 1 && operand.IsM8(b) && operand.IsR8(a): + c.MOVB(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 1 && bn == 1 && operand.IsR8(a) && operand.IsR8(b): + c.MOVB(a, b) + case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) == 0 && an == 1 && bn == 4 && operand.IsM8(a) && operand.IsR32(b): c.MOVBLSX(a, b) - case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) != 0 && an == 1 && bn == 4: + case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) == 0 && an == 1 && bn == 4 && operand.IsR32(b) && operand.IsR8(a): + c.MOVBLSX(a, b) + case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) != 0 && an == 1 && bn == 4 && operand.IsM8(a) && operand.IsR32(b): + c.MOVBLZX(a, b) + case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) != 0 && an == 1 && bn == 4 && operand.IsR32(b) && operand.IsR8(a): c.MOVBLZX(a, b) - case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) == 0 && an == 1 && bn == 8: + case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) == 0 && an == 1 && bn == 8 && operand.IsM8(a) && operand.IsR64(b): c.MOVBQSX(a, b) - case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) != 0 && an == 1 && bn == 8: + case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) == 0 && an == 1 && bn == 8 && operand.IsR64(b) && operand.IsR8(a): + c.MOVBQSX(a, b) + case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) != 0 && an == 1 && bn == 8 && operand.IsM8(a) && operand.IsR64(b): + c.MOVBQZX(a, b) + case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) != 0 && an == 1 && bn == 8 && operand.IsR64(b) && operand.IsR8(a): c.MOVBQZX(a, b) - case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) == 0 && an == 1 && bn == 2: + case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) == 0 && an == 1 && bn == 2 && operand.IsM8(a) && operand.IsR16(b): + c.MOVBWSX(a, b) + case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) == 0 && an == 1 && bn == 2 && operand.IsR16(b) && operand.IsR8(a): c.MOVBWSX(a, b) - case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) != 0 && an == 1 && bn == 2: + case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) != 0 && an == 1 && bn == 2 && operand.IsM8(a) && operand.IsR16(b): c.MOVBWZX(a, b) - case (t.Info()&types.IsInteger) != 0 && an == 4 && bn == 4: + case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) != 0 && an == 1 && bn == 2 && operand.IsR16(b) && operand.IsR8(a): + c.MOVBWZX(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 4 && bn == 4 && operand.IsM32(a) && operand.IsR32(b): + c.MOVL(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 4 && bn == 4 && operand.IsM32(b) && operand.IsR32(a): + c.MOVL(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 4 && bn == 4 && operand.IsR32(a) && operand.IsR32(b): c.MOVL(a, b) - case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) == 0 && an == 4 && bn == 8: + case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) == 0 && an == 4 && bn == 8 && operand.IsM32(a) && operand.IsR64(b): c.MOVLQSX(a, b) - case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) != 0 && an == 4 && bn == 8: + case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) == 0 && an == 4 && bn == 8 && operand.IsR32(a) && operand.IsR64(b): + c.MOVLQSX(a, b) + case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) != 0 && an == 4 && bn == 8 && operand.IsM32(a) && operand.IsR64(b): c.MOVLQZX(a, b) - case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 16: + case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 16 && operand.IsM128(a) && operand.IsXMM(b): + c.MOVOU(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 16 && operand.IsM128(b) && operand.IsXMM(a): + c.MOVOU(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 16 && operand.IsXMM(a) && operand.IsXMM(b): c.MOVOU(a, b) - case (t.Info()&types.IsInteger) != 0 && an == 4 && bn == 16: + case (t.Info()&types.IsInteger) != 0 && an == 4 && bn == 16 && operand.IsM32(a) && operand.IsXMM(b): c.MOVQ(a, b) - case (t.Info()&types.IsInteger) != 0 && an == 8 && bn == 8: + case (t.Info()&types.IsInteger) != 0 && an == 8 && bn == 16 && operand.IsM64(a) && operand.IsXMM(b): c.MOVQ(a, b) - case (t.Info()&types.IsInteger) != 0 && an == 8 && bn == 16: + case (t.Info()&types.IsInteger) != 0 && an == 4 && bn == 16 && operand.IsR32(a) && operand.IsXMM(b): c.MOVQ(a, b) - case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 4: + case (t.Info()&types.IsInteger) != 0 && an == 8 && bn == 16 && operand.IsR64(a) && operand.IsXMM(b): c.MOVQ(a, b) - case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 8: + case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 4 && operand.IsM32(b) && operand.IsXMM(a): c.MOVQ(a, b) - case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 16: + case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 8 && operand.IsM64(b) && operand.IsXMM(a): c.MOVQ(a, b) - case (t.Info()&types.IsFloat) != 0 && an == 8 && bn == 16: + case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 4 && operand.IsR32(b) && operand.IsXMM(a): + c.MOVQ(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 8 && operand.IsR64(b) && operand.IsXMM(a): + c.MOVQ(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 16 && operand.IsXMM(a) && operand.IsXMM(b): + c.MOVQ(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 8 && bn == 8 && operand.IsM64(a) && operand.IsR64(b): + c.MOVQ(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 8 && bn == 8 && operand.IsM64(b) && operand.IsR64(a): + c.MOVQ(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 8 && bn == 8 && operand.IsR64(a) && operand.IsR64(b): + c.MOVQ(a, b) + case (t.Info()&types.IsFloat) != 0 && an == 8 && bn == 16 && operand.IsM64(a) && operand.IsXMM(b): c.MOVSD(a, b) - case (t.Info()&types.IsFloat) != 0 && an == 16 && bn == 8: + case (t.Info()&types.IsFloat) != 0 && an == 16 && bn == 8 && operand.IsM64(b) && operand.IsXMM(a): c.MOVSD(a, b) - case (t.Info()&types.IsFloat) != 0 && an == 16 && bn == 16: + case (t.Info()&types.IsFloat) != 0 && an == 16 && bn == 16 && operand.IsXMM(a) && operand.IsXMM(b): c.MOVSD(a, b) - case (t.Info()&types.IsFloat) != 0 && an == 4 && bn == 16: + case (t.Info()&types.IsFloat) != 0 && an == 4 && bn == 16 && operand.IsM32(a) && operand.IsXMM(b): c.MOVSS(a, b) - case (t.Info()&types.IsFloat) != 0 && an == 16 && bn == 4: + case (t.Info()&types.IsFloat) != 0 && an == 16 && bn == 4 && operand.IsM32(b) && operand.IsXMM(a): c.MOVSS(a, b) - case (t.Info()&types.IsFloat) != 0 && an == 16 && bn == 16: + case (t.Info()&types.IsFloat) != 0 && an == 16 && bn == 16 && operand.IsXMM(a) && operand.IsXMM(b): c.MOVSS(a, b) - case (t.Info()&types.IsInteger) != 0 && an == 2 && bn == 2: + case (t.Info()&types.IsInteger) != 0 && an == 2 && bn == 2 && operand.IsM16(a) && operand.IsR16(b): c.MOVW(a, b) - case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) == 0 && an == 2 && bn == 4: + case (t.Info()&types.IsInteger) != 0 && an == 2 && bn == 2 && operand.IsM16(b) && operand.IsR16(a): + c.MOVW(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 2 && bn == 2 && operand.IsR16(a) && operand.IsR16(b): + c.MOVW(a, b) + case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) == 0 && an == 2 && bn == 4 && operand.IsM16(a) && operand.IsR32(b): + c.MOVWLSX(a, b) + case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) == 0 && an == 2 && bn == 4 && operand.IsR16(a) && operand.IsR32(b): c.MOVWLSX(a, b) - case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) != 0 && an == 2 && bn == 4: + case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) != 0 && an == 2 && bn == 4 && operand.IsM16(a) && operand.IsR32(b): c.MOVWLZX(a, b) - case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) == 0 && an == 2 && bn == 8: + case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) != 0 && an == 2 && bn == 4 && operand.IsR16(a) && operand.IsR32(b): + c.MOVWLZX(a, b) + case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) == 0 && an == 2 && bn == 8 && operand.IsM16(a) && operand.IsR64(b): + c.MOVWQSX(a, b) + case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) == 0 && an == 2 && bn == 8 && operand.IsR16(a) && operand.IsR64(b): c.MOVWQSX(a, b) - case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) != 0 && an == 2 && bn == 8: + case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) != 0 && an == 2 && bn == 8 && operand.IsM16(a) && operand.IsR64(b): + c.MOVWQZX(a, b) + case (t.Info()&types.IsInteger) != 0 && (t.Info()&types.IsUnsigned) != 0 && an == 2 && bn == 8 && operand.IsR16(a) && operand.IsR64(b): c.MOVWQZX(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 4 && bn == 16 && operand.IsM32(a) && operand.IsXMM(b): + c.VMOVD(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 4 && bn == 16 && operand.IsR32(a) && operand.IsXMM(b): + c.VMOVD(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 4 && operand.IsM32(b) && operand.IsXMM(a): + c.VMOVD(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 4 && operand.IsR32(b) && operand.IsXMM(a): + c.VMOVD(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 16 && operand.IsM128(a) && operand.IsXMM(b): + c.VMOVDQU(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 32 && bn == 32 && operand.IsM256(a) && operand.IsYMM(b): + c.VMOVDQU(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 16 && operand.IsM128(b) && operand.IsXMM(a): + c.VMOVDQU(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 16 && operand.IsXMM(a) && operand.IsXMM(b): + c.VMOVDQU(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 32 && bn == 32 && operand.IsM256(b) && operand.IsYMM(a): + c.VMOVDQU(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 32 && bn == 32 && operand.IsYMM(a) && operand.IsYMM(b): + c.VMOVDQU(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 16 && operand.IsM128(a) && operand.IsXMM(b): + c.VMOVDQU16(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 32 && bn == 32 && operand.IsM256(a) && operand.IsYMM(b): + c.VMOVDQU16(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 16 && operand.IsM128(b) && operand.IsXMM(a): + c.VMOVDQU16(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 16 && operand.IsXMM(a) && operand.IsXMM(b): + c.VMOVDQU16(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 32 && bn == 32 && operand.IsM256(b) && operand.IsYMM(a): + c.VMOVDQU16(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 32 && bn == 32 && operand.IsYMM(a) && operand.IsYMM(b): + c.VMOVDQU16(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 64 && bn == 64 && operand.IsM512(a) && operand.IsZMM(b): + c.VMOVDQU16(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 64 && bn == 64 && operand.IsM512(b) && operand.IsZMM(a): + c.VMOVDQU16(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 64 && bn == 64 && operand.IsZMM(a) && operand.IsZMM(b): + c.VMOVDQU16(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 16 && operand.IsM128(a) && operand.IsXMM(b): + c.VMOVDQU32(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 32 && bn == 32 && operand.IsM256(a) && operand.IsYMM(b): + c.VMOVDQU32(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 16 && operand.IsM128(b) && operand.IsXMM(a): + c.VMOVDQU32(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 16 && operand.IsXMM(a) && operand.IsXMM(b): + c.VMOVDQU32(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 32 && bn == 32 && operand.IsM256(b) && operand.IsYMM(a): + c.VMOVDQU32(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 32 && bn == 32 && operand.IsYMM(a) && operand.IsYMM(b): + c.VMOVDQU32(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 64 && bn == 64 && operand.IsM512(a) && operand.IsZMM(b): + c.VMOVDQU32(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 64 && bn == 64 && operand.IsM512(b) && operand.IsZMM(a): + c.VMOVDQU32(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 64 && bn == 64 && operand.IsZMM(a) && operand.IsZMM(b): + c.VMOVDQU32(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 16 && operand.IsM128(a) && operand.IsXMM(b): + c.VMOVDQU64(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 32 && bn == 32 && operand.IsM256(a) && operand.IsYMM(b): + c.VMOVDQU64(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 16 && operand.IsM128(b) && operand.IsXMM(a): + c.VMOVDQU64(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 16 && operand.IsXMM(a) && operand.IsXMM(b): + c.VMOVDQU64(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 32 && bn == 32 && operand.IsM256(b) && operand.IsYMM(a): + c.VMOVDQU64(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 32 && bn == 32 && operand.IsYMM(a) && operand.IsYMM(b): + c.VMOVDQU64(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 64 && bn == 64 && operand.IsM512(a) && operand.IsZMM(b): + c.VMOVDQU64(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 64 && bn == 64 && operand.IsM512(b) && operand.IsZMM(a): + c.VMOVDQU64(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 64 && bn == 64 && operand.IsZMM(a) && operand.IsZMM(b): + c.VMOVDQU64(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 16 && operand.IsM128(a) && operand.IsXMM(b): + c.VMOVDQU8(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 32 && bn == 32 && operand.IsM256(a) && operand.IsYMM(b): + c.VMOVDQU8(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 16 && operand.IsM128(b) && operand.IsXMM(a): + c.VMOVDQU8(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 16 && operand.IsXMM(a) && operand.IsXMM(b): + c.VMOVDQU8(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 32 && bn == 32 && operand.IsM256(b) && operand.IsYMM(a): + c.VMOVDQU8(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 32 && bn == 32 && operand.IsYMM(a) && operand.IsYMM(b): + c.VMOVDQU8(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 64 && bn == 64 && operand.IsM512(a) && operand.IsZMM(b): + c.VMOVDQU8(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 64 && bn == 64 && operand.IsM512(b) && operand.IsZMM(a): + c.VMOVDQU8(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 64 && bn == 64 && operand.IsZMM(a) && operand.IsZMM(b): + c.VMOVDQU8(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 8 && bn == 16 && operand.IsM64(a) && operand.IsXMM(b): + c.VMOVQ(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 8 && bn == 16 && operand.IsR64(a) && operand.IsXMM(b): + c.VMOVQ(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 8 && operand.IsM64(b) && operand.IsXMM(a): + c.VMOVQ(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 8 && operand.IsR64(b) && operand.IsXMM(a): + c.VMOVQ(a, b) + case (t.Info()&types.IsInteger) != 0 && an == 16 && bn == 16 && operand.IsXMM(a) && operand.IsXMM(b): + c.VMOVQ(a, b) + case (t.Info()&types.IsFloat) != 0 && an == 8 && bn == 16 && operand.IsM64(a) && operand.IsXMM(b): + c.VMOVSD(a, b) + case (t.Info()&types.IsFloat) != 0 && an == 16 && bn == 8 && operand.IsM64(b) && operand.IsXMM(a): + c.VMOVSD(a, b) + case (t.Info()&types.IsFloat) != 0 && an == 4 && bn == 16 && operand.IsM32(a) && operand.IsXMM(b): + c.VMOVSS(a, b) + case (t.Info()&types.IsFloat) != 0 && an == 16 && bn == 4 && operand.IsM32(b) && operand.IsXMM(a): + c.VMOVSS(a, b) default: c.adderrormessage("could not deduce mov instruction") } diff --git a/examples/README.md b/examples/README.md index 167abd2a..03b66c17 100644 --- a/examples/README.md +++ b/examples/README.md @@ -19,5 +19,6 @@ Features: * **[fnv1a](fnv1a):** [FNV-1a](https://en.wikipedia.org/wiki/Fowler%E2%80%93Noll%E2%80%93Vo_hash_function#FNV-1a_hash) hash function. * **[dot](dot):** Vector dot product. * **[geohash](geohash):** Integer [geohash](https://en.wikipedia.org/wiki/Geohash) encoding. +* **[md5x16](md5x16):** AVX-512 accelerated [MD5](https://en.wikipedia.org/wiki/MD5). * **[sha1](sha1):** [SHA-1](https://en.wikipedia.org/wiki/SHA-1) cryptographic hash. * **[stadtx](stadtx):** [`StadtX` hash](https://github.com/demerphq/BeagleHash) port from [dgryski/go-stadtx](https://github.com/dgryski/go-stadtx). diff --git a/examples/md5x16/README.md b/examples/md5x16/README.md new file mode 100644 index 00000000..975ab125 --- /dev/null +++ b/examples/md5x16/README.md @@ -0,0 +1,135 @@ +# md5x16 + +AVX-512 accelerated 16-lane [MD5](https://en.wikipedia.org/wiki/MD5) in `avo`. + +Inspired by [`minio/md5-simd`](https://github.com/minio/md5-simd) and +[`igneous-systems/md5vec`](https://github.com/igneous-systems/md5vec). + +Note that the focus of this example is the core assembly `block` function. The +`Sum` function can only handle parallel hashes of exactly the same length. In +practice you'd likely need hash server functionality provided by +[`md5-simd`](https://github.com/minio/md5-simd) to multiplex independent hashes +of different lengths into the 16 SIMD lanes. + +[embedmd]:# (asm.go /func main/ /^}/) +```go +func main() { + // Define round constants data section. + // + // These may be computed as the integer part of abs(sin(i+1))*2^32. + T := GLOBL("consts", RODATA|NOPTR) + for i := 0; i < 64; i++ { + k := uint32(math.Floor(math.Ldexp(math.Abs(math.Sin(float64(i+1))), 32))) + DATA(4*i, U32(k)) + } + + // MD5 16-lane block function. + TEXT("block", 0, "func(h *[4][16]uint32, base uintptr, offsets *[16]uint32, mask uint16)") + Doc( + "block MD5 hashes 16 messages into the running hash states h. Messages are", + "at the given offsets from the base pointer. The 16-bit mask specifies", + "which lanes are active: when bit i is not set loads will be disabled and", + "the value of the resulting hash is undefined.", + ) + h := Mem{Base: Load(Param("h"), GP64())} + base := Mem{Base: Load(Param("base"), GP64())} + offsetsptr := Mem{Base: Load(Param("offsets"), GP64())} + mask := Load(Param("mask"), K()) + + Comment("Load offsets.") + offsets := ZMM() + VMOVUPD(offsetsptr, offsets) + + Comment("Load initial hash.") + hash := [4]Register{ZMM(), ZMM(), ZMM(), ZMM()} + for i, r := range hash { + VMOVUPD(h.Offset(64*i), r) + } + + Comment("Initialize registers.") + a, b, c, d := ZMM(), ZMM(), ZMM(), ZMM() + for i, r := range []Register{a, b, c, d} { + VMOVUPD(hash[i], r) + } + + // Allocate message registers. + m := make([]Register, 16) + for i := range m { + m[i] = ZMM() + } + + // Generate round updates. + // + // Each 16-round block is parameterized based on the btiwise function, + // message indexes and shift amounts. Constants B, C, D are helpers in + // computing the logic table required by VPTERNLOGD. + const ( + B = uint8(0b10101010) + C = uint8(0b11001100) + D = uint8(0b11110000) + ) + quarter := []struct { + F uint8 // ternary logic table + i func(int) int // message index at round r + s []int // shift amounts + }{ + { + F: (B & C) | (^B & D), + i: func(r int) int { return r % 16 }, + s: []int{7, 12, 17, 22}, + }, + { + F: (D & B) | (^D & C), + i: func(r int) int { return (5*r + 1) % 16 }, + s: []int{5, 9, 14, 20}, + }, + { + F: B ^ C ^ D, + i: func(r int) int { return (3*r + 5) % 16 }, + s: []int{4, 11, 16, 23}, + }, + { + F: C ^ (B | ^D), + i: func(r int) int { return (7 * r) % 16 }, + s: []int{6, 10, 15, 21}, + }, + } + + for r := 0; r < 64; r++ { + Commentf("Round %d.", r) + q := quarter[r/16] + + // Load message words. + if r < 16 { + k := K() + KMOVW(mask, k) + VPGATHERDD(base.Offset(4*r).Idx(offsets, 1), k, m[r]) + } + + VPADDD(m[q.i(r)], a, a) + VPADDD_BCST(T.Offset(4*r), a, a) + f := ZMM() + VMOVUPD(d, f) + VPTERNLOGD(U8(q.F), b, c, f) + VPADDD(f, a, a) + VPROLD(U8(q.s[r%4]), a, a) + VPADDD(b, a, a) + a, b, c, d = d, a, b, c + } + + Comment("Final add.") + for i, r := range []Register{a, b, c, d} { + VPADDD(r, hash[i], hash[i]) + } + + Comment("Store results back.") + for i, r := range hash { + VMOVUPD(r, h.Offset(64*i)) + } + + VZEROUPPER() + RET() + + Generate() +} +``` diff --git a/examples/md5x16/asm.go b/examples/md5x16/asm.go new file mode 100644 index 00000000..3d5e7937 --- /dev/null +++ b/examples/md5x16/asm.go @@ -0,0 +1,132 @@ +//go:build ignore +// +build ignore + +package main + +import ( + "math" + + . "github.com/mmcloughlin/avo/build" + . "github.com/mmcloughlin/avo/operand" + . "github.com/mmcloughlin/avo/reg" +) + +func main() { + // Define round constants data section. + // + // These may be computed as the integer part of abs(sin(i+1))*2^32. + T := GLOBL("consts", RODATA|NOPTR) + for i := 0; i < 64; i++ { + k := uint32(math.Floor(math.Ldexp(math.Abs(math.Sin(float64(i+1))), 32))) + DATA(4*i, U32(k)) + } + + // MD5 16-lane block function. + TEXT("block", 0, "func(h *[4][16]uint32, base uintptr, offsets *[16]uint32, mask uint16)") + Doc( + "block MD5 hashes 16 messages into the running hash states h. Messages are", + "at the given offsets from the base pointer. The 16-bit mask specifies", + "which lanes are active: when bit i is not set loads will be disabled and", + "the value of the resulting hash is undefined.", + ) + h := Mem{Base: Load(Param("h"), GP64())} + base := Mem{Base: Load(Param("base"), GP64())} + offsetsptr := Mem{Base: Load(Param("offsets"), GP64())} + mask := Load(Param("mask"), K()) + + Comment("Load offsets.") + offsets := ZMM() + VMOVUPD(offsetsptr, offsets) + + Comment("Load initial hash.") + hash := [4]Register{ZMM(), ZMM(), ZMM(), ZMM()} + for i, r := range hash { + VMOVUPD(h.Offset(64*i), r) + } + + Comment("Initialize registers.") + a, b, c, d := ZMM(), ZMM(), ZMM(), ZMM() + for i, r := range []Register{a, b, c, d} { + VMOVUPD(hash[i], r) + } + + // Allocate message registers. + m := make([]Register, 16) + for i := range m { + m[i] = ZMM() + } + + // Generate round updates. + // + // Each 16-round block is parameterized based on the btiwise function, + // message indexes and shift amounts. Constants B, C, D are helpers in + // computing the logic table required by VPTERNLOGD. + const ( + B = uint8(0b10101010) + C = uint8(0b11001100) + D = uint8(0b11110000) + ) + quarter := []struct { + F uint8 // ternary logic table + i func(int) int // message index at round r + s []int // shift amounts + }{ + { + F: (B & C) | (^B & D), + i: func(r int) int { return r % 16 }, + s: []int{7, 12, 17, 22}, + }, + { + F: (D & B) | (^D & C), + i: func(r int) int { return (5*r + 1) % 16 }, + s: []int{5, 9, 14, 20}, + }, + { + F: B ^ C ^ D, + i: func(r int) int { return (3*r + 5) % 16 }, + s: []int{4, 11, 16, 23}, + }, + { + F: C ^ (B | ^D), + i: func(r int) int { return (7 * r) % 16 }, + s: []int{6, 10, 15, 21}, + }, + } + + for r := 0; r < 64; r++ { + Commentf("Round %d.", r) + q := quarter[r/16] + + // Load message words. + if r < 16 { + k := K() + KMOVW(mask, k) + VPGATHERDD(base.Offset(4*r).Idx(offsets, 1), k, m[r]) + } + + VPADDD(m[q.i(r)], a, a) + VPADDD_BCST(T.Offset(4*r), a, a) + f := ZMM() + VMOVUPD(d, f) + VPTERNLOGD(U8(q.F), b, c, f) + VPADDD(f, a, a) + VPROLD(U8(q.s[r%4]), a, a) + VPADDD(b, a, a) + a, b, c, d = d, a, b, c + } + + Comment("Final add.") + for i, r := range []Register{a, b, c, d} { + VPADDD(r, hash[i], hash[i]) + } + + Comment("Store results back.") + for i, r := range hash { + VMOVUPD(r, h.Offset(64*i)) + } + + VZEROUPPER() + RET() + + Generate() +} diff --git a/examples/md5x16/md5x16.go b/examples/md5x16/md5x16.go new file mode 100644 index 00000000..db6b4a0c --- /dev/null +++ b/examples/md5x16/md5x16.go @@ -0,0 +1,151 @@ +// Package md5x16 implements 16-lane parallel MD5 with AVX-512 instructions. +package md5x16 + +import ( + "encoding/binary" + "errors" + "math" + "reflect" + "unsafe" +) + +//go:generate go run asm.go -out md5x16.s -stubs stub.go + +// Size of a MD5 checksum in bytes. +const Size = 16 + +// BlockSize is the block size of MD5 in bytes. +const BlockSize = 64 + +// Lanes is the maximum number of parallel MD5 computations. +const Lanes = 16 + +// Validate checks whether the preconditions required by Sum() are met. +func Validate(data [Lanes][]byte) error { + _, err := config(data) + return err +} + +// Sum returns the MD5 checksum of up to Lanes data of the same length. +// +// Non-nil inputs must all have the same length, and occupy a memory span not +// exceeding 32 bits. +func Sum(data [Lanes][]byte) [Lanes][Size]byte { + // Determine lane configuration. + cfg, err := config(data) + if err != nil { + panic(err) + } + + // Initialize hash. + var h [4][Lanes]uint32 + for _, l := range cfg.active { + h[0][l] = 0x67452301 + h[1][l] = 0xefcdab89 + h[2][l] = 0x98badcfe + h[3][l] = 0x10325476 + } + + // Consume full blocks. + base, n := cfg.base, cfg.n + for ; n >= BlockSize; n -= BlockSize { + block(&h, base, &cfg.offsets, cfg.mask) + base += BlockSize + } + + // Final block. + var last [Lanes][]byte + var buffer [Lanes * BlockSize]byte + base = dataptr(buffer[:]) + var offsets [Lanes]uint32 + for _, l := range cfg.active { + last[l] = buffer[l*BlockSize : (l+1)*BlockSize] + offsets[l] = uint32(l * BlockSize) + copy(last[l], data[l][cfg.n-n:]) + last[l][n] = 0x80 + } + + if n >= 56 { + block(&h, base, &offsets, cfg.mask) + for i := range buffer { + buffer[i] = 0 + } + } + + for _, l := range cfg.active { + binary.LittleEndian.PutUint64(last[l][56:], uint64(8*cfg.n)) + } + block(&h, base, &offsets, cfg.mask) + + // Write into byte array. + var digest [Lanes][Size]byte + for _, l := range cfg.active { + for i := 0; i < 4; i++ { + binary.LittleEndian.PutUint32(digest[l][4*i:], h[i][l]) + } + } + + return digest +} + +// lanes represents the configuration of the 16 data lanes of an MD5 +// computation. +type lanes struct { + n int // length of all active (non-nil) lanes + active []int // indexes of active lanes + mask uint16 // mask of active lanes + base uintptr // base pointer + offsets [Lanes]uint32 // offset of data lanes relative to base +} + +// config determines the lane configuration for the provided data. Returns an +// error if there are no active lanes, there's a length mismatch among active +// lanes, or the data spans a memory region larger than 32-bits. +func config(data [Lanes][]byte) (*lanes, error) { + cfg := &lanes{} + + // Populate active lanes, and ensure they're all the same length. + for l, d := range data { + if d != nil { + cfg.active = append(cfg.active, l) + } + } + + if len(cfg.active) == 0 { + return nil, errors.New("no active lanes") + } + + cfg.n = len(data[cfg.active[0]]) + for _, l := range cfg.active { + cfg.mask |= 1 << l + if len(data[l]) != cfg.n { + return nil, errors.New("length mismatch") + } + } + + // Compute base pointer and lane offsets. + cfg.base = ^uintptr(0) + for _, l := range cfg.active { + ptr := dataptr(data[l]) + if ptr < cfg.base { + cfg.base = ptr + } + } + + for _, l := range cfg.active { + ptr := dataptr(data[l]) + offset := ptr - cfg.base + if offset > math.MaxUint32 { + return nil, errors.New("input data exceed 32-bit memory region") + } + cfg.offsets[l] = uint32(offset) + } + + return cfg, nil +} + +// dataptr extracts the data pointer from the given slice. +func dataptr(data []byte) uintptr { + hdr := (*reflect.SliceHeader)(unsafe.Pointer(&data)) + return hdr.Data +} diff --git a/examples/md5x16/md5x16.s b/examples/md5x16/md5x16.s new file mode 100644 index 00000000..a94cc896 --- /dev/null +++ b/examples/md5x16/md5x16.s @@ -0,0 +1,714 @@ +// Code generated by command: go run asm.go -out md5x16.s -stubs stub.go. DO NOT EDIT. + +#include "textflag.h" + +DATA consts<>+0(SB)/4, $0xd76aa478 +DATA consts<>+4(SB)/4, $0xe8c7b756 +DATA consts<>+8(SB)/4, $0x242070db +DATA consts<>+12(SB)/4, $0xc1bdceee +DATA consts<>+16(SB)/4, $0xf57c0faf +DATA consts<>+20(SB)/4, $0x4787c62a +DATA consts<>+24(SB)/4, $0xa8304613 +DATA consts<>+28(SB)/4, $0xfd469501 +DATA consts<>+32(SB)/4, $0x698098d8 +DATA consts<>+36(SB)/4, $0x8b44f7af +DATA consts<>+40(SB)/4, $0xffff5bb1 +DATA consts<>+44(SB)/4, $0x895cd7be +DATA consts<>+48(SB)/4, $0x6b901122 +DATA consts<>+52(SB)/4, $0xfd987193 +DATA consts<>+56(SB)/4, $0xa679438e +DATA consts<>+60(SB)/4, $0x49b40821 +DATA consts<>+64(SB)/4, $0xf61e2562 +DATA consts<>+68(SB)/4, $0xc040b340 +DATA consts<>+72(SB)/4, $0x265e5a51 +DATA consts<>+76(SB)/4, $0xe9b6c7aa +DATA consts<>+80(SB)/4, $0xd62f105d +DATA consts<>+84(SB)/4, $0x02441453 +DATA consts<>+88(SB)/4, $0xd8a1e681 +DATA consts<>+92(SB)/4, $0xe7d3fbc8 +DATA consts<>+96(SB)/4, $0x21e1cde6 +DATA consts<>+100(SB)/4, $0xc33707d6 +DATA consts<>+104(SB)/4, $0xf4d50d87 +DATA consts<>+108(SB)/4, $0x455a14ed +DATA consts<>+112(SB)/4, $0xa9e3e905 +DATA consts<>+116(SB)/4, $0xfcefa3f8 +DATA consts<>+120(SB)/4, $0x676f02d9 +DATA consts<>+124(SB)/4, $0x8d2a4c8a +DATA consts<>+128(SB)/4, $0xfffa3942 +DATA consts<>+132(SB)/4, $0x8771f681 +DATA consts<>+136(SB)/4, $0x6d9d6122 +DATA consts<>+140(SB)/4, $0xfde5380c +DATA consts<>+144(SB)/4, $0xa4beea44 +DATA consts<>+148(SB)/4, $0x4bdecfa9 +DATA consts<>+152(SB)/4, $0xf6bb4b60 +DATA consts<>+156(SB)/4, $0xbebfbc70 +DATA consts<>+160(SB)/4, $0x289b7ec6 +DATA consts<>+164(SB)/4, $0xeaa127fa +DATA consts<>+168(SB)/4, $0xd4ef3085 +DATA consts<>+172(SB)/4, $0x04881d05 +DATA consts<>+176(SB)/4, $0xd9d4d039 +DATA consts<>+180(SB)/4, $0xe6db99e5 +DATA consts<>+184(SB)/4, $0x1fa27cf8 +DATA consts<>+188(SB)/4, $0xc4ac5665 +DATA consts<>+192(SB)/4, $0xf4292244 +DATA consts<>+196(SB)/4, $0x432aff97 +DATA consts<>+200(SB)/4, $0xab9423a7 +DATA consts<>+204(SB)/4, $0xfc93a039 +DATA consts<>+208(SB)/4, $0x655b59c3 +DATA consts<>+212(SB)/4, $0x8f0ccc92 +DATA consts<>+216(SB)/4, $0xffeff47d +DATA consts<>+220(SB)/4, $0x85845dd1 +DATA consts<>+224(SB)/4, $0x6fa87e4f +DATA consts<>+228(SB)/4, $0xfe2ce6e0 +DATA consts<>+232(SB)/4, $0xa3014314 +DATA consts<>+236(SB)/4, $0x4e0811a1 +DATA consts<>+240(SB)/4, $0xf7537e82 +DATA consts<>+244(SB)/4, $0xbd3af235 +DATA consts<>+248(SB)/4, $0x2ad7d2bb +DATA consts<>+252(SB)/4, $0xeb86d391 +GLOBL consts<>(SB), RODATA|NOPTR, $256 + +// func block(h *[4][16]uint32, base uintptr, offsets *[16]uint32, mask uint16) +// Requires: AVX, AVX512F +TEXT ·block(SB), $0-26 + MOVQ h+0(FP), AX + MOVQ base+8(FP), CX + MOVQ offsets+16(FP), DX + KMOVW mask+24(FP), K1 + + // Load offsets. + VMOVUPD (DX), Z0 + + // Load initial hash. + VMOVUPD (AX), Z1 + VMOVUPD 64(AX), Z2 + VMOVUPD 128(AX), Z3 + VMOVUPD 192(AX), Z4 + + // Initialize registers. + VMOVUPD Z1, Z5 + VMOVUPD Z2, Z6 + VMOVUPD Z3, Z7 + VMOVUPD Z4, Z8 + + // Round 0. + KMOVW K1, K2 + VPGATHERDD (CX)(Z0*1), K2, Z9 + VPADDD Z9, Z5, Z5 + VPADDD.BCST consts<>+0(SB), Z5, Z5 + VMOVUPD Z8, Z25 + VPTERNLOGD $0xd8, Z6, Z7, Z25 + VPADDD Z25, Z5, Z5 + VPROLD $0x07, Z5, Z5 + VPADDD Z6, Z5, Z5 + + // Round 1. + KMOVW K1, K2 + VPGATHERDD 4(CX)(Z0*1), K2, Z10 + VPADDD Z10, Z8, Z8 + VPADDD.BCST consts<>+4(SB), Z8, Z8 + VMOVUPD Z7, Z25 + VPTERNLOGD $0xd8, Z5, Z6, Z25 + VPADDD Z25, Z8, Z8 + VPROLD $0x0c, Z8, Z8 + VPADDD Z5, Z8, Z8 + + // Round 2. + KMOVW K1, K2 + VPGATHERDD 8(CX)(Z0*1), K2, Z11 + VPADDD Z11, Z7, Z7 + VPADDD.BCST consts<>+8(SB), Z7, Z7 + VMOVUPD Z6, Z25 + VPTERNLOGD $0xd8, Z8, Z5, Z25 + VPADDD Z25, Z7, Z7 + VPROLD $0x11, Z7, Z7 + VPADDD Z8, Z7, Z7 + + // Round 3. + KMOVW K1, K2 + VPGATHERDD 12(CX)(Z0*1), K2, Z12 + VPADDD Z12, Z6, Z6 + VPADDD.BCST consts<>+12(SB), Z6, Z6 + VMOVUPD Z5, Z25 + VPTERNLOGD $0xd8, Z7, Z8, Z25 + VPADDD Z25, Z6, Z6 + VPROLD $0x16, Z6, Z6 + VPADDD Z7, Z6, Z6 + + // Round 4. + KMOVW K1, K2 + VPGATHERDD 16(CX)(Z0*1), K2, Z13 + VPADDD Z13, Z5, Z5 + VPADDD.BCST consts<>+16(SB), Z5, Z5 + VMOVUPD Z8, Z25 + VPTERNLOGD $0xd8, Z6, Z7, Z25 + VPADDD Z25, Z5, Z5 + VPROLD $0x07, Z5, Z5 + VPADDD Z6, Z5, Z5 + + // Round 5. + KMOVW K1, K2 + VPGATHERDD 20(CX)(Z0*1), K2, Z14 + VPADDD Z14, Z8, Z8 + VPADDD.BCST consts<>+20(SB), Z8, Z8 + VMOVUPD Z7, Z25 + VPTERNLOGD $0xd8, Z5, Z6, Z25 + VPADDD Z25, Z8, Z8 + VPROLD $0x0c, Z8, Z8 + VPADDD Z5, Z8, Z8 + + // Round 6. + KMOVW K1, K2 + VPGATHERDD 24(CX)(Z0*1), K2, Z15 + VPADDD Z15, Z7, Z7 + VPADDD.BCST consts<>+24(SB), Z7, Z7 + VMOVUPD Z6, Z25 + VPTERNLOGD $0xd8, Z8, Z5, Z25 + VPADDD Z25, Z7, Z7 + VPROLD $0x11, Z7, Z7 + VPADDD Z8, Z7, Z7 + + // Round 7. + KMOVW K1, K2 + VPGATHERDD 28(CX)(Z0*1), K2, Z16 + VPADDD Z16, Z6, Z6 + VPADDD.BCST consts<>+28(SB), Z6, Z6 + VMOVUPD Z5, Z25 + VPTERNLOGD $0xd8, Z7, Z8, Z25 + VPADDD Z25, Z6, Z6 + VPROLD $0x16, Z6, Z6 + VPADDD Z7, Z6, Z6 + + // Round 8. + KMOVW K1, K2 + VPGATHERDD 32(CX)(Z0*1), K2, Z17 + VPADDD Z17, Z5, Z5 + VPADDD.BCST consts<>+32(SB), Z5, Z5 + VMOVUPD Z8, Z25 + VPTERNLOGD $0xd8, Z6, Z7, Z25 + VPADDD Z25, Z5, Z5 + VPROLD $0x07, Z5, Z5 + VPADDD Z6, Z5, Z5 + + // Round 9. + KMOVW K1, K2 + VPGATHERDD 36(CX)(Z0*1), K2, Z18 + VPADDD Z18, Z8, Z8 + VPADDD.BCST consts<>+36(SB), Z8, Z8 + VMOVUPD Z7, Z25 + VPTERNLOGD $0xd8, Z5, Z6, Z25 + VPADDD Z25, Z8, Z8 + VPROLD $0x0c, Z8, Z8 + VPADDD Z5, Z8, Z8 + + // Round 10. + KMOVW K1, K2 + VPGATHERDD 40(CX)(Z0*1), K2, Z19 + VPADDD Z19, Z7, Z7 + VPADDD.BCST consts<>+40(SB), Z7, Z7 + VMOVUPD Z6, Z25 + VPTERNLOGD $0xd8, Z8, Z5, Z25 + VPADDD Z25, Z7, Z7 + VPROLD $0x11, Z7, Z7 + VPADDD Z8, Z7, Z7 + + // Round 11. + KMOVW K1, K2 + VPGATHERDD 44(CX)(Z0*1), K2, Z20 + VPADDD Z20, Z6, Z6 + VPADDD.BCST consts<>+44(SB), Z6, Z6 + VMOVUPD Z5, Z25 + VPTERNLOGD $0xd8, Z7, Z8, Z25 + VPADDD Z25, Z6, Z6 + VPROLD $0x16, Z6, Z6 + VPADDD Z7, Z6, Z6 + + // Round 12. + KMOVW K1, K2 + VPGATHERDD 48(CX)(Z0*1), K2, Z21 + VPADDD Z21, Z5, Z5 + VPADDD.BCST consts<>+48(SB), Z5, Z5 + VMOVUPD Z8, Z25 + VPTERNLOGD $0xd8, Z6, Z7, Z25 + VPADDD Z25, Z5, Z5 + VPROLD $0x07, Z5, Z5 + VPADDD Z6, Z5, Z5 + + // Round 13. + KMOVW K1, K2 + VPGATHERDD 52(CX)(Z0*1), K2, Z22 + VPADDD Z22, Z8, Z8 + VPADDD.BCST consts<>+52(SB), Z8, Z8 + VMOVUPD Z7, Z25 + VPTERNLOGD $0xd8, Z5, Z6, Z25 + VPADDD Z25, Z8, Z8 + VPROLD $0x0c, Z8, Z8 + VPADDD Z5, Z8, Z8 + + // Round 14. + KMOVW K1, K2 + VPGATHERDD 56(CX)(Z0*1), K2, Z23 + VPADDD Z23, Z7, Z7 + VPADDD.BCST consts<>+56(SB), Z7, Z7 + VMOVUPD Z6, Z25 + VPTERNLOGD $0xd8, Z8, Z5, Z25 + VPADDD Z25, Z7, Z7 + VPROLD $0x11, Z7, Z7 + VPADDD Z8, Z7, Z7 + + // Round 15. + KMOVW K1, K1 + VPGATHERDD 60(CX)(Z0*1), K1, Z24 + VPADDD Z24, Z6, Z6 + VPADDD.BCST consts<>+60(SB), Z6, Z6 + VMOVUPD Z5, Z0 + VPTERNLOGD $0xd8, Z7, Z8, Z0 + VPADDD Z0, Z6, Z6 + VPROLD $0x16, Z6, Z6 + VPADDD Z7, Z6, Z6 + + // Round 16. + VPADDD Z10, Z5, Z5 + VPADDD.BCST consts<>+64(SB), Z5, Z5 + VMOVUPD Z8, Z0 + VPTERNLOGD $0xac, Z6, Z7, Z0 + VPADDD Z0, Z5, Z5 + VPROLD $0x05, Z5, Z5 + VPADDD Z6, Z5, Z5 + + // Round 17. + VPADDD Z15, Z8, Z8 + VPADDD.BCST consts<>+68(SB), Z8, Z8 + VMOVUPD Z7, Z0 + VPTERNLOGD $0xac, Z5, Z6, Z0 + VPADDD Z0, Z8, Z8 + VPROLD $0x09, Z8, Z8 + VPADDD Z5, Z8, Z8 + + // Round 18. + VPADDD Z20, Z7, Z7 + VPADDD.BCST consts<>+72(SB), Z7, Z7 + VMOVUPD Z6, Z0 + VPTERNLOGD $0xac, Z8, Z5, Z0 + VPADDD Z0, Z7, Z7 + VPROLD $0x0e, Z7, Z7 + VPADDD Z8, Z7, Z7 + + // Round 19. + VPADDD Z9, Z6, Z6 + VPADDD.BCST consts<>+76(SB), Z6, Z6 + VMOVUPD Z5, Z0 + VPTERNLOGD $0xac, Z7, Z8, Z0 + VPADDD Z0, Z6, Z6 + VPROLD $0x14, Z6, Z6 + VPADDD Z7, Z6, Z6 + + // Round 20. + VPADDD Z14, Z5, Z5 + VPADDD.BCST consts<>+80(SB), Z5, Z5 + VMOVUPD Z8, Z0 + VPTERNLOGD $0xac, Z6, Z7, Z0 + VPADDD Z0, Z5, Z5 + VPROLD $0x05, Z5, Z5 + VPADDD Z6, Z5, Z5 + + // Round 21. + VPADDD Z19, Z8, Z8 + VPADDD.BCST consts<>+84(SB), Z8, Z8 + VMOVUPD Z7, Z0 + VPTERNLOGD $0xac, Z5, Z6, Z0 + VPADDD Z0, Z8, Z8 + VPROLD $0x09, Z8, Z8 + VPADDD Z5, Z8, Z8 + + // Round 22. + VPADDD Z24, Z7, Z7 + VPADDD.BCST consts<>+88(SB), Z7, Z7 + VMOVUPD Z6, Z0 + VPTERNLOGD $0xac, Z8, Z5, Z0 + VPADDD Z0, Z7, Z7 + VPROLD $0x0e, Z7, Z7 + VPADDD Z8, Z7, Z7 + + // Round 23. + VPADDD Z13, Z6, Z6 + VPADDD.BCST consts<>+92(SB), Z6, Z6 + VMOVUPD Z5, Z0 + VPTERNLOGD $0xac, Z7, Z8, Z0 + VPADDD Z0, Z6, Z6 + VPROLD $0x14, Z6, Z6 + VPADDD Z7, Z6, Z6 + + // Round 24. + VPADDD Z18, Z5, Z5 + VPADDD.BCST consts<>+96(SB), Z5, Z5 + VMOVUPD Z8, Z0 + VPTERNLOGD $0xac, Z6, Z7, Z0 + VPADDD Z0, Z5, Z5 + VPROLD $0x05, Z5, Z5 + VPADDD Z6, Z5, Z5 + + // Round 25. + VPADDD Z23, Z8, Z8 + VPADDD.BCST consts<>+100(SB), Z8, Z8 + VMOVUPD Z7, Z0 + VPTERNLOGD $0xac, Z5, Z6, Z0 + VPADDD Z0, Z8, Z8 + VPROLD $0x09, Z8, Z8 + VPADDD Z5, Z8, Z8 + + // Round 26. + VPADDD Z12, Z7, Z7 + VPADDD.BCST consts<>+104(SB), Z7, Z7 + VMOVUPD Z6, Z0 + VPTERNLOGD $0xac, Z8, Z5, Z0 + VPADDD Z0, Z7, Z7 + VPROLD $0x0e, Z7, Z7 + VPADDD Z8, Z7, Z7 + + // Round 27. + VPADDD Z17, Z6, Z6 + VPADDD.BCST consts<>+108(SB), Z6, Z6 + VMOVUPD Z5, Z0 + VPTERNLOGD $0xac, Z7, Z8, Z0 + VPADDD Z0, Z6, Z6 + VPROLD $0x14, Z6, Z6 + VPADDD Z7, Z6, Z6 + + // Round 28. + VPADDD Z22, Z5, Z5 + VPADDD.BCST consts<>+112(SB), Z5, Z5 + VMOVUPD Z8, Z0 + VPTERNLOGD $0xac, Z6, Z7, Z0 + VPADDD Z0, Z5, Z5 + VPROLD $0x05, Z5, Z5 + VPADDD Z6, Z5, Z5 + + // Round 29. + VPADDD Z11, Z8, Z8 + VPADDD.BCST consts<>+116(SB), Z8, Z8 + VMOVUPD Z7, Z0 + VPTERNLOGD $0xac, Z5, Z6, Z0 + VPADDD Z0, Z8, Z8 + VPROLD $0x09, Z8, Z8 + VPADDD Z5, Z8, Z8 + + // Round 30. + VPADDD Z16, Z7, Z7 + VPADDD.BCST consts<>+120(SB), Z7, Z7 + VMOVUPD Z6, Z0 + VPTERNLOGD $0xac, Z8, Z5, Z0 + VPADDD Z0, Z7, Z7 + VPROLD $0x0e, Z7, Z7 + VPADDD Z8, Z7, Z7 + + // Round 31. + VPADDD Z21, Z6, Z6 + VPADDD.BCST consts<>+124(SB), Z6, Z6 + VMOVUPD Z5, Z0 + VPTERNLOGD $0xac, Z7, Z8, Z0 + VPADDD Z0, Z6, Z6 + VPROLD $0x14, Z6, Z6 + VPADDD Z7, Z6, Z6 + + // Round 32. + VPADDD Z14, Z5, Z5 + VPADDD.BCST consts<>+128(SB), Z5, Z5 + VMOVUPD Z8, Z0 + VPTERNLOGD $0x96, Z6, Z7, Z0 + VPADDD Z0, Z5, Z5 + VPROLD $0x04, Z5, Z5 + VPADDD Z6, Z5, Z5 + + // Round 33. + VPADDD Z17, Z8, Z8 + VPADDD.BCST consts<>+132(SB), Z8, Z8 + VMOVUPD Z7, Z0 + VPTERNLOGD $0x96, Z5, Z6, Z0 + VPADDD Z0, Z8, Z8 + VPROLD $0x0b, Z8, Z8 + VPADDD Z5, Z8, Z8 + + // Round 34. + VPADDD Z20, Z7, Z7 + VPADDD.BCST consts<>+136(SB), Z7, Z7 + VMOVUPD Z6, Z0 + VPTERNLOGD $0x96, Z8, Z5, Z0 + VPADDD Z0, Z7, Z7 + VPROLD $0x10, Z7, Z7 + VPADDD Z8, Z7, Z7 + + // Round 35. + VPADDD Z23, Z6, Z6 + VPADDD.BCST consts<>+140(SB), Z6, Z6 + VMOVUPD Z5, Z0 + VPTERNLOGD $0x96, Z7, Z8, Z0 + VPADDD Z0, Z6, Z6 + VPROLD $0x17, Z6, Z6 + VPADDD Z7, Z6, Z6 + + // Round 36. + VPADDD Z10, Z5, Z5 + VPADDD.BCST consts<>+144(SB), Z5, Z5 + VMOVUPD Z8, Z0 + VPTERNLOGD $0x96, Z6, Z7, Z0 + VPADDD Z0, Z5, Z5 + VPROLD $0x04, Z5, Z5 + VPADDD Z6, Z5, Z5 + + // Round 37. + VPADDD Z13, Z8, Z8 + VPADDD.BCST consts<>+148(SB), Z8, Z8 + VMOVUPD Z7, Z0 + VPTERNLOGD $0x96, Z5, Z6, Z0 + VPADDD Z0, Z8, Z8 + VPROLD $0x0b, Z8, Z8 + VPADDD Z5, Z8, Z8 + + // Round 38. + VPADDD Z16, Z7, Z7 + VPADDD.BCST consts<>+152(SB), Z7, Z7 + VMOVUPD Z6, Z0 + VPTERNLOGD $0x96, Z8, Z5, Z0 + VPADDD Z0, Z7, Z7 + VPROLD $0x10, Z7, Z7 + VPADDD Z8, Z7, Z7 + + // Round 39. + VPADDD Z19, Z6, Z6 + VPADDD.BCST consts<>+156(SB), Z6, Z6 + VMOVUPD Z5, Z0 + VPTERNLOGD $0x96, Z7, Z8, Z0 + VPADDD Z0, Z6, Z6 + VPROLD $0x17, Z6, Z6 + VPADDD Z7, Z6, Z6 + + // Round 40. + VPADDD Z22, Z5, Z5 + VPADDD.BCST consts<>+160(SB), Z5, Z5 + VMOVUPD Z8, Z0 + VPTERNLOGD $0x96, Z6, Z7, Z0 + VPADDD Z0, Z5, Z5 + VPROLD $0x04, Z5, Z5 + VPADDD Z6, Z5, Z5 + + // Round 41. + VPADDD Z9, Z8, Z8 + VPADDD.BCST consts<>+164(SB), Z8, Z8 + VMOVUPD Z7, Z0 + VPTERNLOGD $0x96, Z5, Z6, Z0 + VPADDD Z0, Z8, Z8 + VPROLD $0x0b, Z8, Z8 + VPADDD Z5, Z8, Z8 + + // Round 42. + VPADDD Z12, Z7, Z7 + VPADDD.BCST consts<>+168(SB), Z7, Z7 + VMOVUPD Z6, Z0 + VPTERNLOGD $0x96, Z8, Z5, Z0 + VPADDD Z0, Z7, Z7 + VPROLD $0x10, Z7, Z7 + VPADDD Z8, Z7, Z7 + + // Round 43. + VPADDD Z15, Z6, Z6 + VPADDD.BCST consts<>+172(SB), Z6, Z6 + VMOVUPD Z5, Z0 + VPTERNLOGD $0x96, Z7, Z8, Z0 + VPADDD Z0, Z6, Z6 + VPROLD $0x17, Z6, Z6 + VPADDD Z7, Z6, Z6 + + // Round 44. + VPADDD Z18, Z5, Z5 + VPADDD.BCST consts<>+176(SB), Z5, Z5 + VMOVUPD Z8, Z0 + VPTERNLOGD $0x96, Z6, Z7, Z0 + VPADDD Z0, Z5, Z5 + VPROLD $0x04, Z5, Z5 + VPADDD Z6, Z5, Z5 + + // Round 45. + VPADDD Z21, Z8, Z8 + VPADDD.BCST consts<>+180(SB), Z8, Z8 + VMOVUPD Z7, Z0 + VPTERNLOGD $0x96, Z5, Z6, Z0 + VPADDD Z0, Z8, Z8 + VPROLD $0x0b, Z8, Z8 + VPADDD Z5, Z8, Z8 + + // Round 46. + VPADDD Z24, Z7, Z7 + VPADDD.BCST consts<>+184(SB), Z7, Z7 + VMOVUPD Z6, Z0 + VPTERNLOGD $0x96, Z8, Z5, Z0 + VPADDD Z0, Z7, Z7 + VPROLD $0x10, Z7, Z7 + VPADDD Z8, Z7, Z7 + + // Round 47. + VPADDD Z11, Z6, Z6 + VPADDD.BCST consts<>+188(SB), Z6, Z6 + VMOVUPD Z5, Z0 + VPTERNLOGD $0x96, Z7, Z8, Z0 + VPADDD Z0, Z6, Z6 + VPROLD $0x17, Z6, Z6 + VPADDD Z7, Z6, Z6 + + // Round 48. + VPADDD Z9, Z5, Z5 + VPADDD.BCST consts<>+192(SB), Z5, Z5 + VMOVUPD Z8, Z0 + VPTERNLOGD $0x63, Z6, Z7, Z0 + VPADDD Z0, Z5, Z5 + VPROLD $0x06, Z5, Z5 + VPADDD Z6, Z5, Z5 + + // Round 49. + VPADDD Z16, Z8, Z8 + VPADDD.BCST consts<>+196(SB), Z8, Z8 + VMOVUPD Z7, Z0 + VPTERNLOGD $0x63, Z5, Z6, Z0 + VPADDD Z0, Z8, Z8 + VPROLD $0x0a, Z8, Z8 + VPADDD Z5, Z8, Z8 + + // Round 50. + VPADDD Z23, Z7, Z7 + VPADDD.BCST consts<>+200(SB), Z7, Z7 + VMOVUPD Z6, Z0 + VPTERNLOGD $0x63, Z8, Z5, Z0 + VPADDD Z0, Z7, Z7 + VPROLD $0x0f, Z7, Z7 + VPADDD Z8, Z7, Z7 + + // Round 51. + VPADDD Z14, Z6, Z6 + VPADDD.BCST consts<>+204(SB), Z6, Z6 + VMOVUPD Z5, Z0 + VPTERNLOGD $0x63, Z7, Z8, Z0 + VPADDD Z0, Z6, Z6 + VPROLD $0x15, Z6, Z6 + VPADDD Z7, Z6, Z6 + + // Round 52. + VPADDD Z21, Z5, Z5 + VPADDD.BCST consts<>+208(SB), Z5, Z5 + VMOVUPD Z8, Z0 + VPTERNLOGD $0x63, Z6, Z7, Z0 + VPADDD Z0, Z5, Z5 + VPROLD $0x06, Z5, Z5 + VPADDD Z6, Z5, Z5 + + // Round 53. + VPADDD Z12, Z8, Z8 + VPADDD.BCST consts<>+212(SB), Z8, Z8 + VMOVUPD Z7, Z0 + VPTERNLOGD $0x63, Z5, Z6, Z0 + VPADDD Z0, Z8, Z8 + VPROLD $0x0a, Z8, Z8 + VPADDD Z5, Z8, Z8 + + // Round 54. + VPADDD Z19, Z7, Z7 + VPADDD.BCST consts<>+216(SB), Z7, Z7 + VMOVUPD Z6, Z0 + VPTERNLOGD $0x63, Z8, Z5, Z0 + VPADDD Z0, Z7, Z7 + VPROLD $0x0f, Z7, Z7 + VPADDD Z8, Z7, Z7 + + // Round 55. + VPADDD Z10, Z6, Z6 + VPADDD.BCST consts<>+220(SB), Z6, Z6 + VMOVUPD Z5, Z0 + VPTERNLOGD $0x63, Z7, Z8, Z0 + VPADDD Z0, Z6, Z6 + VPROLD $0x15, Z6, Z6 + VPADDD Z7, Z6, Z6 + + // Round 56. + VPADDD Z17, Z5, Z5 + VPADDD.BCST consts<>+224(SB), Z5, Z5 + VMOVUPD Z8, Z0 + VPTERNLOGD $0x63, Z6, Z7, Z0 + VPADDD Z0, Z5, Z5 + VPROLD $0x06, Z5, Z5 + VPADDD Z6, Z5, Z5 + + // Round 57. + VPADDD Z24, Z8, Z8 + VPADDD.BCST consts<>+228(SB), Z8, Z8 + VMOVUPD Z7, Z0 + VPTERNLOGD $0x63, Z5, Z6, Z0 + VPADDD Z0, Z8, Z8 + VPROLD $0x0a, Z8, Z8 + VPADDD Z5, Z8, Z8 + + // Round 58. + VPADDD Z15, Z7, Z7 + VPADDD.BCST consts<>+232(SB), Z7, Z7 + VMOVUPD Z6, Z0 + VPTERNLOGD $0x63, Z8, Z5, Z0 + VPADDD Z0, Z7, Z7 + VPROLD $0x0f, Z7, Z7 + VPADDD Z8, Z7, Z7 + + // Round 59. + VPADDD Z22, Z6, Z6 + VPADDD.BCST consts<>+236(SB), Z6, Z6 + VMOVUPD Z5, Z0 + VPTERNLOGD $0x63, Z7, Z8, Z0 + VPADDD Z0, Z6, Z6 + VPROLD $0x15, Z6, Z6 + VPADDD Z7, Z6, Z6 + + // Round 60. + VPADDD Z13, Z5, Z5 + VPADDD.BCST consts<>+240(SB), Z5, Z5 + VMOVUPD Z8, Z0 + VPTERNLOGD $0x63, Z6, Z7, Z0 + VPADDD Z0, Z5, Z5 + VPROLD $0x06, Z5, Z5 + VPADDD Z6, Z5, Z5 + + // Round 61. + VPADDD Z20, Z8, Z8 + VPADDD.BCST consts<>+244(SB), Z8, Z8 + VMOVUPD Z7, Z0 + VPTERNLOGD $0x63, Z5, Z6, Z0 + VPADDD Z0, Z8, Z8 + VPROLD $0x0a, Z8, Z8 + VPADDD Z5, Z8, Z8 + + // Round 62. + VPADDD Z11, Z7, Z7 + VPADDD.BCST consts<>+248(SB), Z7, Z7 + VMOVUPD Z6, Z0 + VPTERNLOGD $0x63, Z8, Z5, Z0 + VPADDD Z0, Z7, Z7 + VPROLD $0x0f, Z7, Z7 + VPADDD Z8, Z7, Z7 + + // Round 63. + VPADDD Z18, Z6, Z6 + VPADDD.BCST consts<>+252(SB), Z6, Z6 + VMOVUPD Z5, Z0 + VPTERNLOGD $0x63, Z7, Z8, Z0 + VPADDD Z0, Z6, Z6 + VPROLD $0x15, Z6, Z6 + VPADDD Z7, Z6, Z6 + + // Final add. + VPADDD Z5, Z1, Z1 + VPADDD Z6, Z2, Z2 + VPADDD Z7, Z3, Z3 + VPADDD Z8, Z4, Z4 + + // Store results back. + VMOVUPD Z1, (AX) + VMOVUPD Z2, 64(AX) + VMOVUPD Z3, 128(AX) + VMOVUPD Z4, 192(AX) + VZEROUPPER + RET diff --git a/examples/md5x16/md5x16_test.go b/examples/md5x16/md5x16_test.go new file mode 100644 index 00000000..c21a9221 --- /dev/null +++ b/examples/md5x16/md5x16_test.go @@ -0,0 +1,136 @@ +package md5x16 + +import ( + "crypto/md5" + "encoding/hex" + "math/rand" + "testing" + "testing/quick" + + "golang.org/x/sys/cpu" +) + +func RequireISA(t *testing.T) { + t.Helper() + if !cpu.X86.HasAVX512F { + t.Skip("requires AVX512F instruction set") + } +} + +func TestVectors(t *testing.T) { + RequireISA(t) + + cases := []struct { + Data string + HexDigest string + }{ + {"", "d41d8cd98f00b204e9800998ecf8427e"}, + {"The quick brown fox jumps over the lazy dog", "9e107d9d372bb6826bd81d3542a419d6"}, + {"The quick brown fox jumps over the lazy dog.", "e4d909c290d0fb1ca068ffaddf22cbd0"}, + } + for _, c := range cases { + digest := Single(t, []byte(c.Data)) + got := hex.EncodeToString(digest[:]) + if got != c.HexDigest { + t.Errorf("Sum(%#v) = %s; expect %s", c.Data, got, c.HexDigest) + } + } +} + +func TestCmp(t *testing.T) { + RequireISA(t) + + sum := func(data []byte) [Size]byte { return Single(t, data) } + if err := quick.CheckEqual(sum, md5.Sum, nil); err != nil { + t.Fatal(err) + } +} + +func TestLengths(t *testing.T) { + RequireISA(t) + + const max = BlockSize << 6 + data := make([]byte, max) + rand.Read(data) + + for n := 0; n <= max; n++ { + got := Single(t, data[:n]) + expect := md5.Sum(data[:n]) + if got != expect { + t.Fatalf("failed on length %d", n) + } + } +} + +// Single hashes a single data buffer in all 16 lanes and returns the result, +// after asserting that all lanes are the same. +func Single(t *testing.T, d []byte) [Size]byte { + // Place the same data in every lane. + var data [Lanes][]byte + for l := range data { + data[l] = d + } + + if err := Validate(data); err != nil { + t.Fatal(err) + } + + // Hash and check the lanes are the same. + digest := Sum(data) + for l := range data { + if digest[0] != digest[l] { + t.Logf("lane %02d: %x", 0, digest[0]) + t.Logf("lane %02d: %x", l, digest[l]) + t.Fatal("lane mismatch") + } + } + + return digest[0] +} + +func TestActiveLanes(t *testing.T) { + RequireISA(t) + + const trials = 1 << 10 + const maxlen = BlockSize << 6 + for trial := 0; trial < trials; trial++ { + // Pick active lanes. + lanes := 1 + rand.Intn(Lanes-1) + active := rand.Perm(Lanes)[:lanes] + + // Fill active lanes with random data. + n := rand.Intn(maxlen) + buffer := make([]byte, lanes*n) + rand.Read(buffer) + + var data [Lanes][]byte + for i, l := range active { + data[l] = buffer[i*n : (i+1)*n] + } + + // Hash. + digest := Sum(data) + + // Verify correct result in active lanes. + for _, l := range active { + expect := md5.Sum(data[l]) + if digest[l] != expect { + t.Fatalf("lane %02d: mismatch", l) + } + } + + // Verify other lanes are zero. + isactive := map[int]bool{} + for _, l := range active { + isactive[l] = true + } + for l := 0; l < Lanes; l++ { + if !isactive[l] { + var zero [Size]byte + if digest[l] != zero { + t.Fatalf("inactive lane %d is non-zero", l) + } + } + } + } +} diff --git a/examples/md5x16/stub.go b/examples/md5x16/stub.go new file mode 100644 index 00000000..ff46fe29 --- /dev/null +++ b/examples/md5x16/stub.go @@ -0,0 +1,9 @@ +// Code generated by command: go run asm.go -out md5x16.s -stubs stub.go. DO NOT EDIT. + +package md5x16 + +// block MD5 hashes 16 messages into the running hash states h. Messages are +// at the given offsets from the base pointer. The 16-bit mask specifies +// which lanes are active: when bit i is not set loads will be disabled and +// the value of the resulting hash is undefined. +func block(h *[4][16]uint32, base uintptr, offsets *[16]uint32, mask uint16) diff --git a/go.mod b/go.mod index 67d1f0b2..6592a40c 100644 --- a/go.mod +++ b/go.mod @@ -1,6 +1,6 @@ module github.com/mmcloughlin/avo -go 1.11 +go 1.13 require ( golang.org/x/arch v0.0.0-20210923205945-b76863e36670 diff --git a/internal/api/doc.go b/internal/api/doc.go new file mode 100644 index 00000000..82ad3b3f --- /dev/null +++ b/internal/api/doc.go @@ -0,0 +1,2 @@ +// Package api determines the API of avo instruction constructors. +package api diff --git a/internal/api/function.go b/internal/api/function.go new file mode 100644 index 00000000..1ae795cc --- /dev/null +++ b/internal/api/function.go @@ -0,0 +1,177 @@ +package api + +import ( + "bytes" + "fmt" + "sort" + "strconv" + "strings" + "text/tabwriter" + + "github.com/mmcloughlin/avo/internal/inst" +) + +// Function represents a function that constructs some collection of +// instruction forms. +type Function struct { + Instruction inst.Instruction + Suffixes inst.Suffixes + inst.Forms +} + +// Name returns the function name. +func (f *Function) Name() string { + return f.opcodesuffix("_") +} + +// Opcode returns the full Go opcode of the instruction built by this function. Includes any suffixes. +func (f *Function) Opcode() string { + return f.opcodesuffix(".") +} + +func (f *Function) opcodesuffix(sep string) string { + n := f.Instruction.Opcode + for _, suffix := range f.Suffixes { + n += sep + n += suffix.String() + } + return n +} + +// HasSuffix reports whether the function has the provided suffix. +func (f *Function) HasSuffix(suffix inst.Suffix) bool { + for _, s := range f.Suffixes { + if s == suffix { + return true + } + } + return false +} + +// Summary returns a summary of the instruction this function constructs. +func (f *Function) Summary() string { + summary := f.Instruction.Summary + if len(f.Suffixes) > 0 { + summary += " (" + strings.Join(f.Suffixes.Summaries(), ", ") + ")" + } + return summary +} + +// Doc returns the function document comment as a list of lines. +func (f *Function) Doc() []string { + lines := []string{ + fmt.Sprintf("%s: %s.", f.Name(), f.Summary()), + "", + "Forms:", + "", + } + + // Write a table of instruction forms. + buf := bytes.NewBuffer(nil) + w := tabwriter.NewWriter(buf, 0, 0, 1, ' ', 0) + for _, form := range f.Forms { + row := f.Opcode() + "\t" + strings.Join(form.Signature(), "\t") + "\n" + fmt.Fprint(w, row) + } + w.Flush() + + tbl := strings.TrimSpace(buf.String()) + for _, line := range strings.Split(tbl, "\n") { + lines = append(lines, "\t"+line) + } + + return lines +} + +// Signature of the function. Derived from the instruction forms generated by this function. +func (f *Function) Signature() Signature { + // Handle the case of forms with multiple arities. + switch { + case f.IsVariadic(): + return variadic{name: "ops"} + case f.IsNiladic(): + return niladic{} + } + + // Generate nice-looking variable names. + n := f.Arity() + ops := make([]string, n) + count := map[string]int{} + for j := 0; j < n; j++ { + // Collect unique lowercase bytes from first characters of operand types. + s := map[byte]bool{} + for _, form := range f.Forms { + c := form.Operands[j].Type[0] + if 'a' <= c && c <= 'z' { + s[c] = true + } + } + + // Operand name is the sorted bytes. + var b []byte + for c := range s { + b = append(b, c) + } + sort.Slice(b, func(i, j int) bool { return b[i] < b[j] }) + name := string(b) + + // Append a counter if we've seen it already. + m := count[name] + count[name]++ + if m > 0 { + name += strconv.Itoa(m) + } + ops[j] = name + } + + return argslist(ops) +} + +// InstructionFunctions builds the list of all functions for a given +// instruction. +func InstructionFunctions(i inst.Instruction) []*Function { + // One function for each possible suffix combination. + bysuffix := map[string]*Function{} + for _, f := range i.Forms { + for _, suffixes := range f.SupportedSuffixes() { + k := suffixes.String() + if _, ok := bysuffix[k]; !ok { + bysuffix[k] = &Function{ + Instruction: i, + Suffixes: suffixes, + } + } + bysuffix[k].Forms = append(bysuffix[k].Forms, f) + } + } + + // Convert to a sorted slice. + var fns []*Function + for _, fn := range bysuffix { + fns = append(fns, fn) + } + + SortFunctions(fns) + + return fns +} + +// InstructionsFunctions builds all functions for a list of instructions. +func InstructionsFunctions(is []inst.Instruction) []*Function { + var all []*Function + for _, i := range is { + fns := InstructionFunctions(i) + all = append(all, fns...) + } + + SortFunctions(all) + + return all +} + +// SortFunctions sorts a list of functions by name. +func SortFunctions(fns []*Function) { + sort.Slice(fns, func(i, j int) bool { + return fns[i].Name() < fns[j].Name() + }) +} diff --git a/internal/api/function_test.go b/internal/api/function_test.go new file mode 100644 index 00000000..0c348b62 --- /dev/null +++ b/internal/api/function_test.go @@ -0,0 +1,50 @@ +package api + +import ( + "strings" + "testing" + + "github.com/mmcloughlin/avo/internal/inst" +) + +func TestFunctionsDuplicateFormSignatures(t *testing.T) { + // Test for duplicate form signatures within a given function. This could + // manifest as duplicate case statements in generated code. + fns := InstructionsFunctions(inst.Instructions) + for _, fn := range fns { + fn := fn // scopelint + t.Run(fn.Name(), func(t *testing.T) { + seen := map[string]bool{} + for _, f := range fn.Forms { + sig := strings.Join(f.Signature(), "_") + t.Log(sig) + if seen[sig] { + t.Fatalf("duplicate: %s", sig) + } + seen[sig] = true + } + }) + } +} + +func TestFunctionsUniqueArgNames(t *testing.T) { + fns := InstructionsFunctions(inst.Instructions) + for _, fn := range fns { + s := fn.Signature() + for _, n := range fn.Arities() { + if n == 0 { + continue + } + names := map[string]bool{} + for j := 0; j < n; j++ { + names[s.ParameterName(j)] = true + } + if len(names) != n { + t.Errorf("repeated argument for instruction %s", fn.Name()) + } + if _, found := names[""]; found { + t.Errorf("empty argument name for instruction %s", fn.Name()) + } + } + } +} diff --git a/internal/api/signature.go b/internal/api/signature.go new file mode 100644 index 00000000..9b24b885 --- /dev/null +++ b/internal/api/signature.go @@ -0,0 +1,59 @@ +package api + +import ( + "fmt" + "strconv" + "strings" +) + +// Signature provides access to details about the signature of an instruction function. +type Signature interface { + ParameterList() string + Arguments() string + ParameterName(int) string + ParameterSlice() string + Length() string +} + +// ArgsList builds a signature for a function with the named parameters. +func ArgsList(args []string) Signature { + return argslist(args) +} + +type argslist []string + +func (a argslist) ParameterList() string { return strings.Join(a, ", ") + " " + OperandType } +func (a argslist) Arguments() string { return strings.Join(a, ", ") } +func (a argslist) ParameterName(i int) string { return a[i] } +func (a argslist) ParameterSlice() string { + return fmt.Sprintf("[]%s{%s}", OperandType, strings.Join(a, ", ")) +} +func (a argslist) Length() string { return strconv.Itoa(len(a)) } + +// Variadic is the signature for a variadic function with the named argument slice. +func Variadic(name string) Signature { + return variadic{name: name} +} + +type variadic struct { + name string +} + +func (v variadic) ParameterList() string { return v.name + " ..." + OperandType } +func (v variadic) Arguments() string { return v.name + "..." } +func (v variadic) ParameterName(i int) string { return fmt.Sprintf("%s[%d]", v.name, i) } +func (v variadic) ParameterSlice() string { return v.name } +func (v variadic) Length() string { return fmt.Sprintf("len(%s)", v.name) } + +// Niladic is the signature for a function with no arguments. +func Niladic() Signature { + return niladic{} +} + +type niladic struct{} + +func (n niladic) ParameterList() string { return "" } +func (n niladic) Arguments() string { return "" } +func (n niladic) ParameterName(i int) string { panic("niladic function has no parameters") } +func (n niladic) ParameterSlice() string { return fmt.Sprintf("[]%s{}", OperandType) } +func (n niladic) Length() string { return "0" } diff --git a/internal/api/types.go b/internal/api/types.go new file mode 100644 index 00000000..38404e79 --- /dev/null +++ b/internal/api/types.go @@ -0,0 +1,75 @@ +package api + +import ( + "path" + "sort" + "strings" +) + +const ( + // Package is the avo package import path. + Package = "github.com/mmcloughlin/avo" + + // IRPackage is the package that defines intermediate representation types. + IRPackage = "ir" + + // OperandPackage is the package for operand types. + OperandPackage = "operand" + + // OperandType is the type used for operands. + OperandType = OperandPackage + ".Op" + + // RegisterPackage is the name of the package containing register types. + RegisterPackage = "reg" + + // RegisterType is the type used for registers. + RegisterType = RegisterPackage + ".Register" +) + +// ImportPath returns the full import path for an avo subpackage. +func ImportPath(pkg string) string { + return path.Join(Package, pkg) +} + +// ImplicitRegisterIdentifier maps an implicit register name to a string +// suitable for a related Go identifier. +func ImplicitRegisterIdentifier(r string) string { + r = strings.Replace(r, "mm", "", 1) // handles the "xmm0" type + return strings.ToUpper(r) +} + +// ImplicitRegister returns avo syntax for the given implicit register type (from Opcodes XML). +func ImplicitRegister(r string) string { + return RegisterPackage + "." + ImplicitRegisterIdentifier(r) +} + +// OperandTypeIdentifier maps an operand type to a string suitable for a related +// Go identifier. +func OperandTypeIdentifier(t string) string { + return strings.ToUpper(strings.ReplaceAll(t, "/", "")) +} + +// CheckerName returns the name of the function that checks an operand of type t. +func CheckerName(t string) string { + return "operand.Is" + OperandTypeIdentifier(t) +} + +// ISAsIdentifier returns a string representation of an ISA list that suitable +// for use in a Go identifier. +func ISAsIdentifier(isas []string) string { + if len(isas) == 0 { + return "Base" + } + sorted := append([]string(nil), isas...) + sort.Strings(sorted) + ident := strings.Join(sorted, "_") + ident = strings.ReplaceAll(ident, ".", "") // SSE4.1 + ident = strings.ReplaceAll(ident, "+", "") // MMX+ + return ident +} + +// SuffixesClassIdentifier returns a string representation of a suffix class +// that's suitable for use in a Go identifier. +func SuffixesClassIdentifier(c string) string { + return strings.ToUpper(c) +} diff --git a/internal/api/types_test.go b/internal/api/types_test.go new file mode 100644 index 00000000..c99d218a --- /dev/null +++ b/internal/api/types_test.go @@ -0,0 +1,26 @@ +package api + +import ( + "go/token" + "testing" + + "github.com/mmcloughlin/avo/internal/inst" +) + +func TestISAsIdentifier(t *testing.T) { + for _, isas := range inst.ISACombinations(inst.Instructions) { + ident := ISAsIdentifier(isas) + if !token.IsIdentifier(ident) { + t.Errorf("expected %q to be an identifier", ident) + } + } +} + +func TestSuffixesClassIdentifier(t *testing.T) { + for key := range inst.SuffixesClasses(inst.Instructions) { + ident := SuffixesClassIdentifier(key) + if !token.IsIdentifier(ident) { + t.Errorf("expected %q to be an identifier", ident) + } + } +} diff --git a/internal/cmd/avogen/main.go b/internal/cmd/avogen/main.go index 8440f359..862f5bdc 100644 --- a/internal/cmd/avogen/main.go +++ b/internal/cmd/avogen/main.go @@ -15,13 +15,17 @@ import ( ) var generators = map[string]gen.Builder{ - "asmtest": gen.NewAsmTest, - "godata": gen.NewGoData, - "godatatest": gen.NewGoDataTest, - "ctors": gen.NewCtors, - "ctorstest": gen.NewCtorsTest, - "build": gen.NewBuild, - "mov": gen.NewMOV, + "asmtest": gen.NewAsmTest, + "godata": gen.NewGoData, + "godatatest": gen.NewGoDataTest, + "optab": gen.NewOptab, + "ctors": gen.NewCtors, + "ctorstest": gen.NewCtorsTest, + "ctorsstress": gen.NewCtorsStress, + "ctorsbench": gen.NewCtorsBench, + "build": gen.NewBuild, + "buildtest": gen.NewBuildTest, + "mov": gen.NewMOV, } // Command-line flags. diff --git a/internal/gen/api.go b/internal/gen/api.go new file mode 100644 index 00000000..a7e5f75d --- /dev/null +++ b/internal/gen/api.go @@ -0,0 +1,257 @@ +package gen + +import ( + "fmt" + "sort" + "strings" + + "github.com/mmcloughlin/avo/internal/api" + "github.com/mmcloughlin/avo/internal/inst" +) + +// Enum is a generated enumeration type. This assists with mapping between the +// conceptual values of the enum, and it's materialization as Go code. +type Enum struct { + name string + doc []string + values []string +} + +// NewEnum initializes an empty enum type with the given name. +func NewEnum(name string) *Enum { + return &Enum{name: name} +} + +// Name returns the type name. +func (e *Enum) Name() string { return e.name } + +// Receiver returns the receiver variable name. +func (e *Enum) Receiver() string { + return strings.ToLower(e.name[:1]) +} + +// SetDoc sets type documentation, as a list of lines. +func (e *Enum) SetDoc(doc ...string) { + e.doc = doc +} + +// Doc returns the type documentation. +func (e *Enum) Doc() []string { return e.doc } + +// AddValue adds a named enumerator. +func (e *Enum) AddValue(value string) { + e.values = append(e.values, value) +} + +// Values returns all enumerators. +func (e *Enum) Values() []string { return e.values } + +// None returns the name of the "unset" constant of this enumeration. +func (e *Enum) None() string { + return e.ConstName("None") +} + +// ConstName returns the constant name that refers to the given enumerator +// value. +func (e *Enum) ConstName(value string) string { + return e.name + value +} + +// ConstNames returns the constant names for all enumerator values. +func (e *Enum) ConstNames() []string { + var consts []string + for _, v := range e.values { + consts = append(consts, e.ConstName(v)) + } + return consts +} + +// MaxName returns the name of the constant that represents the maximum +// enumerator. This value is placed at the very end of the enum, so all values +// will be between the None and Max enumerators. +func (e *Enum) MaxName() string { + return strings.ToLower(e.ConstName("max")) +} + +// Max returns the value of the maximum enumerator. +func (e *Enum) Max() int { + return len(e.values) +} + +// UnderlyingType returns the underlying unsigned integer type used for the +// enumeration. This will be the smallest type that can represent all the +// values. +func (e *Enum) UnderlyingType() string { + b := uint(8) + for ; b < 64 && e.Max() > ((1< 0 { + opcode += "." + suffixes.String() + } + a.Printf("\t%s\t%s\n", opcode, strings.Join(as, ", ")) } - a.Printf("\t%s\t%s\n", i.Opcode, strings.Join(as, ", ")) - counts["total"]++ } a.Printf("\n") } a.Printf("\tRET\n") - for m, c := range counts { - a.Printf("// %s: %d\n", m, c) - } - return a.Result() } @@ -88,21 +84,21 @@ func (a asmtest) skip(opcode string) (bool, string) { return false, "" } -func (a asmtest) args(opcode string, ops []inst.Operand) []string { +func (a asmtest) args(opcode string, ops []inst.Operand) ([]string, error) { // Special case for CALL, since it needs a different type of rel32 argument than others. if opcode == "CALL" { - return []string{a.sym} + return []string{a.sym}, nil } as := make([]string, len(ops)) for i, op := range ops { a := a.arg(op.Type, i) if a == "" { - return nil + return nil, fmt.Errorf("unsupported operand type %q", op.Type) } as[i] = a } - return as + return as, nil } // arg generates an argument for an operand of the given type. @@ -134,10 +130,10 @@ func (a asmtest) arg(t string, i int) string { "ymm": "Y" + strconv.Itoa(3+i), // // // - // + "zmm": "Z" + strconv.Itoa(16+i), // // // - // + "k": "K" + strconv.Itoa(1+i), // // // // @@ -155,15 +151,8 @@ func (a asmtest) arg(t string, i int) string { // "m256": "256(AX)(CX*2)", // // - // + "m512": "512(AX)(CX*2)", // // - // - // - // - // - // - // - // "vm32x": "32(X14*8)", // // "vm64x": "64(X14*8)", // @@ -172,9 +161,9 @@ func (a asmtest) arg(t string, i int) string { // "vm64y": "64(Y13*8)", // // - // + "vm32z": "32(Z13*8)", // // - // + "vm64z": "64(Z13*8)", // // "rel8": a.rel8, // "rel32": a.rel32, // diff --git a/internal/gen/avotypes.go b/internal/gen/avotypes.go deleted file mode 100644 index 4c3218f3..00000000 --- a/internal/gen/avotypes.go +++ /dev/null @@ -1,22 +0,0 @@ -package gen - -import ( - "fmt" - "strings" -) - -const ( - pkg = "github.com/mmcloughlin/avo" - operandType = "operand.Op" -) - -// implicitRegister returns avo syntax for the given implicit register type (from Opcodes XML). -func implicitRegister(t string) string { - r := strings.Replace(t, "mm", "", 1) // handles the "xmm0" type - return fmt.Sprintf("reg.%s", strings.ToUpper(r)) -} - -// checkername returns the name of the function that checks an operand of type t. -func checkername(t string) string { - return "operand.Is" + strings.ToUpper(t) -} diff --git a/internal/gen/build.go b/internal/gen/build.go index d79159d1..4905b810 100644 --- a/internal/gen/build.go +++ b/internal/gen/build.go @@ -3,6 +3,7 @@ package gen import ( "fmt" + "github.com/mmcloughlin/avo/internal/api" "github.com/mmcloughlin/avo/internal/inst" "github.com/mmcloughlin/avo/internal/prnt" "github.com/mmcloughlin/avo/printer" @@ -26,34 +27,41 @@ func (b *build) Generate(is []inst.Instruction) ([]byte, error) { b.Printf("package build\n\n") b.Printf("import (\n") - b.Printf("\t\"%s/operand\"\n", pkg) - b.Printf("\t\"%s/x86\"\n", pkg) + b.Printf("\t%q\n", api.ImportPath(api.IRPackage)) + b.Printf("\t%q\n", api.ImportPath(api.OperandPackage)) + b.Printf("\t%q\n", api.ImportPath("x86")) b.Printf(")\n\n") - for _, i := range is { - b.instruction(i) + // Helper to reduce source code size a little. + b.Printf("func (c *Context) addinstruction(i *ir.Instruction, err error) {\n") + b.Printf("if err == nil { c.Instruction(i) }") + b.Printf(" else { c.adderror(err) }\n") + b.Printf("}\n\n") + + // Generate build functions. + fns := api.InstructionsFunctions(is) + for _, fn := range fns { + b.function(fn) } return b.Result() } -func (b *build) instruction(i inst.Instruction) { - s := params(i) - d := doc(i) +func (b *build) function(fn *api.Function) { + s := fn.Signature() + d := fn.Doc() // Context method. methoddoc := append([]string{}, d...) - methoddoc = append(methoddoc, fmt.Sprintf("Construct and append a %s instruction to the active function.", i.Opcode)) + methoddoc = append(methoddoc, fmt.Sprintf("Construct and append a %s instruction to the active function.", fn.Opcode())) b.Comment(methoddoc...) - b.Printf("func (c *Context) %s(%s) {\n", i.Opcode, s.ParameterList()) - b.Printf("if inst, err := x86.%s(%s); err == nil", i.Opcode, s.Arguments()) - b.Printf(" { c.Instruction(inst) }") - b.Printf(" else { c.adderror(err) }\n") + b.Printf("func (c *Context) %s(%s) {\n", fn.Name(), s.ParameterList()) + b.Printf("c.addinstruction(x86.%s(%s))", fn.Name(), s.Arguments()) b.Printf("}\n\n") // Global version. globaldoc := append([]string{}, methoddoc...) globaldoc = append(globaldoc, "Operates on the global context.") b.Comment(globaldoc...) - b.Printf("func %s(%s) { ctx.%s(%s) }\n\n", i.Opcode, s.ParameterList(), i.Opcode, s.Arguments()) + b.Printf("func %s(%s) { ctx.%s(%s) }\n\n", fn.Name(), s.ParameterList(), fn.Name(), s.Arguments()) } diff --git a/internal/gen/buildtest.go b/internal/gen/buildtest.go new file mode 100644 index 00000000..582b58e1 --- /dev/null +++ b/internal/gen/buildtest.go @@ -0,0 +1,51 @@ +package gen + +import ( + "github.com/mmcloughlin/avo/internal/api" + "github.com/mmcloughlin/avo/internal/inst" + "github.com/mmcloughlin/avo/internal/prnt" + "github.com/mmcloughlin/avo/printer" +) + +type buildtest struct { + cfg printer.Config + prnt.Generator +} + +// NewBuildTest autogenerates tests for instruction methods on the build +// context. +func NewBuildTest(cfg printer.Config) Interface { + return GoFmt(&buildtest{cfg: cfg}) +} + +func (b *buildtest) Generate(is []inst.Instruction) ([]byte, error) { + b.Printf("// %s\n\n", b.cfg.GeneratedWarning()) + b.BuildTag("!integration") + b.NL() + b.Printf("package build\n\n") + b.Printf("import (\n") + b.Printf("\t\"math\"\n") + b.Printf("\t\"testing\"\n") + b.NL() + b.Printf("\t%q\n", api.ImportPath(api.OperandPackage)) + b.Printf("\t%q\n", api.ImportPath(api.RegisterPackage)) + b.Printf(")\n\n") + + DeclareTestArguments(&b.Generator) + + b.Printf("func TestContextInstructions(t *testing.T) {") + b.Printf("ctx := NewContext()\n") + b.Printf("ctx.Function(\"Instructions\")\n") + + fns := api.InstructionsFunctions(is) + for _, fn := range fns { + f := fn.Forms[0] + s := TestSignature(f) + b.Printf("ctx.%s(%s)\n", fn.Name(), s.Arguments()) + } + + b.Printf("if _, err := ctx.Result(); err != nil { t.Fatal(err) }\n") + b.Printf("}\n\n") + + return b.Result() +} diff --git a/internal/gen/ctors.go b/internal/gen/ctors.go index e48a5dc3..b4955107 100644 --- a/internal/gen/ctors.go +++ b/internal/gen/ctors.go @@ -1,10 +1,7 @@ package gen import ( - "bytes" - "fmt" - "strings" - + "github.com/mmcloughlin/avo/internal/api" "github.com/mmcloughlin/avo/internal/inst" "github.com/mmcloughlin/avo/internal/prnt" "github.com/mmcloughlin/avo/printer" @@ -15,9 +12,9 @@ type ctors struct { prnt.Generator } -// NewCtors will build instruction constructors. Each constructor will check -// that the provided operands match one of the allowed instruction forms. If so -// it will return an Instruction object that can be added to an avo Function. +// NewCtors will build instruction constructors. Each constructor delegates to +// the optab-based instruction builder, providing it with a candidate list of +// forms to match against. func NewCtors(cfg printer.Config) Interface { return GoFmt(&ctors{cfg: cfg}) } @@ -26,107 +23,30 @@ func (c *ctors) Generate(is []inst.Instruction) ([]byte, error) { c.Printf("// %s\n\n", c.cfg.GeneratedWarning()) c.Printf("package x86\n\n") c.Printf("import (\n") - c.Printf("\t\"errors\"\n") - c.NL() - c.Printf("\tintrep \"%s/ir\"\n", pkg) - c.Printf("\t\"%s/reg\"\n", pkg) - c.Printf("\t\"%s/operand\"\n", pkg) + c.Printf("\tintrep %q\n", api.ImportPath(api.IRPackage)) + c.Printf("\t%q\n", api.ImportPath(api.OperandPackage)) c.Printf(")\n\n") - for _, i := range is { - c.instruction(i) + fns := api.InstructionsFunctions(is) + table := NewTable(is) + for _, fn := range fns { + c.function(fn, table) } return c.Result() } -func (c *ctors) instruction(i inst.Instruction) { - c.Comment(doc(i)...) +func (c *ctors) function(fn *api.Function, table *Table) { + c.Comment(fn.Doc()...) - s := params(i) + s := fn.Signature() - c.Printf("func %s(%s) (*intrep.Instruction, error) {\n", i.Opcode, s.ParameterList()) - c.forms(i, s) + c.Printf("func %s(%s) (*intrep.Instruction, error) {\n", fn.Name(), s.ParameterList()) + c.Printf( + "return build(%s.Forms(), %s, %s)\n", + table.OpcodeConst(fn.Instruction.Opcode), + table.SuffixesConst(fn.Suffixes), + s.ParameterSlice(), + ) c.Printf("}\n\n") } - -func (c *ctors) forms(i inst.Instruction, s signature) { - if i.IsNiladic() { - if len(i.Forms) != 1 { - c.AddError(fmt.Errorf("%s breaks assumption that niladic instructions have one form", i.Opcode)) - } - c.Printf("return &%s, nil\n", construct(i, i.Forms[0], s)) - return - } - - c.Printf("switch {\n") - - for _, f := range i.Forms { - var conds []string - - if i.IsVariadic() { - checklen := fmt.Sprintf("%s == %d", s.Length(), len(f.Operands)) - conds = append(conds, checklen) - } - - for j, op := range f.Operands { - checktype := fmt.Sprintf("%s(%s)", checkername(op.Type), s.ParameterName(j)) - conds = append(conds, checktype) - } - - c.Printf("case %s:\n", strings.Join(conds, " && ")) - c.Printf("return &%s, nil\n", construct(i, f, s)) - } - - c.Printf("}\n") - c.Printf("return nil, errors.New(\"%s: bad operands\")\n", i.Opcode) -} - -func construct(i inst.Instruction, f inst.Form, s signature) string { - buf := bytes.NewBuffer(nil) - fmt.Fprintf(buf, "intrep.Instruction{\n") - fmt.Fprintf(buf, "\tOpcode: %#v,\n", i.Opcode) - fmt.Fprintf(buf, "\tOperands: %s,\n", s.ParameterSlice()) - - // Input output. - fmt.Fprintf(buf, "\tInputs: %s,\n", operandsWithAction(f, inst.R, s)) - fmt.Fprintf(buf, "\tOutputs: %s,\n", operandsWithAction(f, inst.W, s)) - - // ISAs. - if len(f.ISA) > 0 { - fmt.Fprintf(buf, "\tISA: %#v,\n", f.ISA) - } - - // Branch variables. - if i.IsTerminal() { - fmt.Fprintf(buf, "\tIsTerminal: true,\n") - } - - if i.IsBranch() { - fmt.Fprintf(buf, "\tIsBranch: true,\n") - fmt.Fprintf(buf, "\tIsConditional: %#v,\n", i.IsConditionalBranch()) - } - - // Cancelling inputs. - if f.CancellingInputs { - fmt.Fprintf(buf, "\tCancellingInputs: true,\n") - } - - fmt.Fprintf(buf, "}") - return buf.String() -} - -func operandsWithAction(f inst.Form, a inst.Action, s signature) string { - opexprs := []string{} - for i, op := range f.Operands { - if op.Action.Contains(a) { - opexprs = append(opexprs, s.ParameterName(i)) - } - } - for _, op := range f.ImplicitOperands { - if op.Action.Contains(a) { - opexprs = append(opexprs, implicitRegister(op.Register)) - } - } - return fmt.Sprintf("[]%s{%s}", operandType, strings.Join(opexprs, ", ")) -} diff --git a/internal/gen/ctors_test.go b/internal/gen/ctors_test.go deleted file mode 100644 index d8b4b692..00000000 --- a/internal/gen/ctors_test.go +++ /dev/null @@ -1,28 +0,0 @@ -package gen - -import ( - "testing" - - "github.com/mmcloughlin/avo/internal/inst" -) - -func TestParamsUniqueArgNames(t *testing.T) { - for _, i := range inst.Instructions { - s := params(i) - for _, n := range i.Arities() { - if n == 0 { - continue - } - names := map[string]bool{} - for j := 0; j < n; j++ { - names[s.ParameterName(j)] = true - } - if len(names) != n { - t.Errorf("repeated argument for instruction %s", i.Opcode) - } - if _, found := names[""]; found { - t.Errorf("empty argument name for instruction %s", i.Opcode) - } - } - } -} diff --git a/internal/gen/ctorstest.go b/internal/gen/ctorstest.go index 297e9fe3..85860b6b 100644 --- a/internal/gen/ctorstest.go +++ b/internal/gen/ctorstest.go @@ -1,8 +1,11 @@ package gen import ( + "bytes" + "fmt" "strings" + "github.com/mmcloughlin/avo/internal/api" "github.com/mmcloughlin/avo/internal/prnt" "github.com/mmcloughlin/avo/printer" @@ -21,93 +24,173 @@ func NewCtorsTest(cfg printer.Config) Interface { func (c *ctorstest) Generate(is []inst.Instruction) ([]byte, error) { c.Printf("// %s\n\n", c.cfg.GeneratedWarning()) + c.BuildTag("!integration") + c.NL() c.Printf("package x86\n\n") c.Printf("import (\n") - c.Printf("\t\"testing\"\n") c.Printf("\t\"math\"\n") + c.Printf("\t\"testing\"\n") c.NL() - c.Printf("\t\"%s/reg\"\n", pkg) - c.Printf("\t\"%s/operand\"\n", pkg) + c.Printf("\t%q\n", api.ImportPath(api.OperandPackage)) + c.Printf("\t%q\n", api.ImportPath(api.RegisterPackage)) c.Printf(")\n\n") - for _, i := range is { - c.instruction(i) + DeclareTestArguments(&c.Generator) + + fns := api.InstructionsFunctions(is) + for _, fn := range fns { + c.function(fn) } return c.Result() } -func (c *ctorstest) instruction(i inst.Instruction) { - c.Printf("func Test%sValidForms(t *testing.T) {", i.Opcode) +func (c *ctorstest) function(fn *api.Function) { + c.Printf("func Test%sValidFormsNoError(t *testing.T) {", fn.Name()) + for _, f := range fn.Forms { + s := TestSignature(f) + c.Printf("if _, err := %s(%s); err != nil { t.Fatal(err) }\n", fn.Name(), s.Arguments()) + } + c.Printf("}\n\n") +} + +type ctorsstress struct { + cfg printer.Config + prnt.Generator +} + +// NewCtorsStress autogenerates stress tests for instruction constructors. +func NewCtorsStress(cfg printer.Config) Interface { + return GoFmt(&ctorsstress{cfg: cfg}) +} + +func (c *ctorsstress) Generate(is []inst.Instruction) ([]byte, error) { + c.Printf("// %s\n\n", c.cfg.GeneratedWarning()) + c.BuildTag("stress") + c.NL() + c.Printf("package x86\n\n") + c.Printf("import (\n") + c.Printf("\t\"reflect\"\n") + c.Printf("\t\"testing\"\n") + c.NL() + c.Printf("\t%q\n", api.ImportPath(api.IRPackage)) + c.Printf("\t%q\n", api.ImportPath(api.OperandPackage)) + c.Printf("\t%q\n", api.ImportPath(api.RegisterPackage)) + c.Printf(")\n\n") + + fns := api.InstructionsFunctions(is) + for _, fn := range fns { + c.function(fn) + } + + return c.Result() +} - for _, f := range i.Forms { +func (c *ctorsstress) function(fn *api.Function) { + c.Printf("func Test%sValidFormsCorrectInstruction(t *testing.T) {", fn.Name()) + for _, f := range fn.Forms { name := strings.Join(f.Signature(), "_") c.Printf("t.Run(\"form=%s\", func(t *testing.T) {\n", name) + s := TestSignature(f) + c.Printf("expect := &%s\n", construct(fn, f, s)) + c.Printf("got, err := %s(%s);\n", fn.Name(), s.Arguments()) + c.Printf("if err != nil { t.Fatal(err) }\n") + c.Printf("if !reflect.DeepEqual(got, expect) { t.Fatal(\"mismatch\") }\n") + c.Printf("})\n") + } + c.Printf("}\n\n") +} + +type ctorsbench struct { + cfg printer.Config + prnt.Generator +} + +// NewCtorsBench autogenerates a benchmark for the instruction constructors. +func NewCtorsBench(cfg printer.Config) Interface { + return GoFmt(&ctorsbench{cfg: cfg}) +} + +func (c *ctorsbench) Generate(is []inst.Instruction) ([]byte, error) { + c.Printf("// %s\n\n", c.cfg.GeneratedWarning()) + c.BuildTag("stress") + c.NL() + c.Printf("package x86\n\n") + c.Printf("import (\n") + c.Printf("\t\"time\"\n") + c.Printf("\t\"testing\"\n") + c.Printf(")\n\n") - for _, args := range validFormArgs(f) { - c.Printf("if _, err := %s(%s)", i.Opcode, strings.Join(args, ", ")) - c.Printf("; err != nil { t.Fatal(err) }\n") + c.Printf("func BenchmarkConstructors(b *testing.B) {\n") + c.Printf("start := time.Now()\n") + c.Printf("for i := 0; i < b.N; i++ {\n") + n := 0 + for _, fn := range api.InstructionsFunctions(is) { + for _, f := range fn.Forms { + n++ + c.Printf("%s(%s)\n", fn.Name(), TestSignature(f).Arguments()) } + } + c.Printf("}\n") + c.Printf("elapsed := time.Since(start)\n") + c.Printf("\tb.ReportMetric(%d * float64(b.N) / elapsed.Seconds(), \"inst/s\")\n", n) + c.Printf("}\n\n") + return c.Result() +} - c.Printf("})\n") +func construct(fn *api.Function, f inst.Form, s api.Signature) string { + buf := bytes.NewBuffer(nil) + fmt.Fprintf(buf, "ir.Instruction{\n") + fmt.Fprintf(buf, "\tOpcode: %#v,\n", fn.Instruction.Opcode) + if len(fn.Suffixes) > 0 { + fmt.Fprintf(buf, "\tSuffixes: %#v,\n", fn.Suffixes.Strings()) } + fmt.Fprintf(buf, "\tOperands: %s,\n", s.ParameterSlice()) - c.Printf("}\n\n") + // Inputs. + fmt.Fprintf(buf, "\tInputs: %s,\n", operandsWithAction(f, inst.R, s)) + + // Outputs. + fmt.Fprintf(buf, "\tOutputs: %s,\n", operandsWithAction(f, inst.W, s)) + + // ISAs. + if len(f.ISA) > 0 { + fmt.Fprintf(buf, "\tISA: %#v,\n", f.ISA) + } + + // Branch variables. + if fn.Instruction.IsTerminal() { + fmt.Fprintf(buf, "\tIsTerminal: true,\n") + } + + if fn.Instruction.IsBranch() { + fmt.Fprintf(buf, "\tIsBranch: true,\n") + fmt.Fprintf(buf, "\tIsConditional: %#v,\n", fn.Instruction.IsConditionalBranch()) + } + + // Cancelling inputs. + if f.CancellingInputs { + fmt.Fprintf(buf, "\tCancellingInputs: true,\n") + } + + fmt.Fprintf(buf, "}") + return buf.String() } -func validFormArgs(f inst.Form) [][]string { - n := len(f.Operands) - args := make([][]string, n) +func operandsWithAction(f inst.Form, a inst.Action, s api.Signature) string { + var opexprs []string for i, op := range f.Operands { - valid, ok := validArgs[op.Type] - if !ok { - panic("missing operands for type " + op.Type) + if op.Action.ContainsAny(a) { + opexprs = append(opexprs, s.ParameterName(i)) } - args[i] = valid } - return cross(args) -} - -var validArgs = map[string][]string{ - // Immediates - "1": {"operand.Imm(1)"}, - "3": {"operand.Imm(3)"}, - "imm2u": {"operand.Imm(1)", "operand.Imm(3)"}, - "imm8": {"operand.Imm(math.MaxInt8)"}, - "imm16": {"operand.Imm(math.MaxInt16)"}, - "imm32": {"operand.Imm(math.MaxInt32)"}, - "imm64": {"operand.Imm(math.MaxInt64)"}, - - // Registers - "al": {"reg.AL"}, - "cl": {"reg.CL"}, - "ax": {"reg.AX"}, - "eax": {"reg.EAX"}, - "rax": {"reg.RAX"}, - "r8": {"reg.CH", "reg.BL", "reg.R13B"}, - "r16": {"reg.CX", "reg.R9W"}, - "r32": {"reg.R10L"}, - "r64": {"reg.R11"}, - "xmm0": {"reg.X0"}, - "xmm": {"reg.X7"}, - "ymm": {"reg.Y15"}, - - // Memory - "m": {"operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}"}, - "m8": {"operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}"}, - "m16": {"operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}"}, - "m32": {"operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}"}, - "m64": {"operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}"}, - "m128": {"operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}"}, - "m256": {"operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}"}, - - // Vector memory - "vm32x": {"operand.Mem{Base: reg.R13, Index: reg.X4, Scale: 1}"}, - "vm64x": {"operand.Mem{Base: reg.R13, Index: reg.X8, Scale: 1}"}, - "vm32y": {"operand.Mem{Base: reg.R13, Index: reg.Y4, Scale: 1}"}, - "vm64y": {"operand.Mem{Base: reg.R13, Index: reg.Y8, Scale: 1}"}, - - // Relative - "rel8": {"operand.Rel(math.MaxInt8)"}, - "rel32": {"operand.Rel(math.MaxInt32)", "operand.LabelRef(\"lbl\")"}, + for _, op := range f.ImplicitOperands { + if op.Action.ContainsAny(a) { + opexprs = append(opexprs, api.ImplicitRegister(op.Register)) + } + } + if len(opexprs) == 0 { + return "nil" + } + return fmt.Sprintf("[]%s{%s}", api.OperandType, strings.Join(opexprs, ", ")) } diff --git a/internal/gen/godata.go b/internal/gen/godata.go index 37c0a442..443d53c2 100644 --- a/internal/gen/godata.go +++ b/internal/gen/godata.go @@ -1,6 +1,7 @@ package gen import ( + "github.com/mmcloughlin/avo/internal/api" "github.com/mmcloughlin/avo/internal/inst" "github.com/mmcloughlin/avo/internal/prnt" "github.com/mmcloughlin/avo/printer" @@ -57,8 +58,21 @@ func (g *godata) Generate(is []inst.Instruction) ([]byte, error) { g.Printf("},\n") } - if f.CancellingInputs { - g.Printf("CancellingInputs: true,\n") + g.Printf("EncodingType: %#v,\n", f.EncodingType) + + for _, flag := range []struct { + Field string + Enabled bool + }{ + {"CancellingInputs", f.CancellingInputs}, + {"Zeroing", f.Zeroing}, + {"EmbeddedRounding", f.EmbeddedRounding}, + {"SuppressAllExceptions", f.SuppressAllExceptions}, + {"Broadcast", f.Broadcast}, + } { + if flag.Enabled { + g.Printf("%s: true,\n", flag.Field) + } } g.Printf("},\n") @@ -90,6 +104,7 @@ func NewGoDataTest(cfg printer.Config) Interface { func (g *godatatest) Generate(is []inst.Instruction) ([]byte, error) { g.Printf("// %s\n\n", g.cfg.GeneratedWarning()) + g.NL() g.Printf("package inst_test\n\n") g.Printf(`import ( @@ -98,7 +113,7 @@ func (g *godatatest) Generate(is []inst.Instruction) ([]byte, error) { "%s/internal/inst" ) - `, pkg) + `, api.Package) g.Printf("var raw = %#v\n\n", is) diff --git a/internal/gen/mov.go b/internal/gen/mov.go index cf8c2325..a281addc 100644 --- a/internal/gen/mov.go +++ b/internal/gen/mov.go @@ -6,6 +6,7 @@ import ( "sort" "strings" + "github.com/mmcloughlin/avo/internal/api" "github.com/mmcloughlin/avo/internal/inst" "github.com/mmcloughlin/avo/internal/prnt" "github.com/mmcloughlin/avo/printer" @@ -29,7 +30,7 @@ func (m *mov) Generate(is []inst.Instruction) ([]byte, error) { m.Printf("import (\n") m.Printf("\t\"go/types\"\n") m.NL() - m.Printf("\t\"%s/operand\"\n", pkg) + m.Printf("\t%q\n", api.ImportPath(api.OperandPackage)) m.Printf(")\n\n") m.Printf("func (c *Context) mov(a, b operand.Op, an, bn int, t *types.Basic) {\n") @@ -48,15 +49,17 @@ func (m *mov) Generate(is []inst.Instruction) ([]byte, error) { func (m *mov) instruction(i inst.Instruction) { f := flags(i) - sizes, err := formsizes(i) + mfs, err := movforms(i) if err != nil { m.AddError(err) return } - for _, size := range sizes { + for _, mf := range mfs { conds := []string{ - fmt.Sprintf("an == %d", size.A), - fmt.Sprintf("bn == %d", size.B), + fmt.Sprintf("an == %d", opsize[mf.A]), + fmt.Sprintf("%s(a)", api.CheckerName(mf.A)), + fmt.Sprintf("bn == %d", opsize[mf.B]), + fmt.Sprintf("%s(b)", api.CheckerName(mf.B)), } for c, on := range f { cmp := map[bool]string{true: "!=", false: "=="} @@ -71,15 +74,29 @@ func (m *mov) instruction(i inst.Instruction) { // ismov decides whether the given instruction is a plain move instruction. func ismov(i inst.Instruction) bool { - if i.AliasOf != "" || !strings.HasPrefix(i.Opcode, "MOV") { + // Ignore aliases. + if i.AliasOf != "" { return false } + + // Accept specific move instruction prefixes. + prefixes := []string{"MOV", "KMOV", "VMOV"} + accept := false + for _, prefix := range prefixes { + accept = strings.HasPrefix(i.Opcode, prefix) || accept + } + if !accept { + return false + } + + // Exclude some cases based on instruction descriptions. exclude := []string{"Packed", "Duplicate", "Aligned", "Hint", "Swapping"} for _, substring := range exclude { if strings.Contains(i.Summary, substring) { return false } } + return true } @@ -100,34 +117,27 @@ func flags(i inst.Instruction) map[string]bool { return f } -type movsize struct{ A, B int8 } +type movform struct{ A, B string } -func (s movsize) sortkey() uint16 { return (uint16(s.A) << 8) | uint16(s.B) } - -func formsizes(i inst.Instruction) ([]movsize, error) { - set := map[movsize]bool{} +func movforms(i inst.Instruction) ([]movform, error) { + var mfs []movform for _, f := range i.Forms { if f.Arity() != 2 { continue } - s := movsize{ - A: opsize[f.Operands[0].Type], - B: opsize[f.Operands[1].Type], + mf := movform{ + A: f.Operands[0].Type, + B: f.Operands[1].Type, } - if s.A < 0 || s.B < 0 { + if opsize[mf.A] < 0 || opsize[mf.B] < 0 { continue } - if s.A == 0 || s.B == 0 { + if opsize[mf.A] == 0 || opsize[mf.B] == 0 { return nil, errors.New("unknown operand type") } - set[s] = true - } - var ss []movsize - for s := range set { - ss = append(ss, s) + mfs = append(mfs, mf) } - sort.Slice(ss, func(i, j int) bool { return ss[i].sortkey() < ss[j].sortkey() }) - return ss, nil + return mfs, nil } var opsize = map[string]int8{ @@ -140,9 +150,14 @@ var opsize = map[string]int8{ "r32": 4, "r64": 8, "xmm": 16, + "ymm": 32, + "zmm": 64, "m8": 1, "m16": 2, "m32": 4, "m64": 8, "m128": 16, + "m256": 32, + "m512": 64, + "k": 8, } diff --git a/internal/gen/optab.go b/internal/gen/optab.go new file mode 100644 index 00000000..cda73de2 --- /dev/null +++ b/internal/gen/optab.go @@ -0,0 +1,288 @@ +package gen + +import ( + "fmt" + "sort" + "strconv" + "strings" + + "github.com/mmcloughlin/avo/internal/api" + "github.com/mmcloughlin/avo/internal/inst" + "github.com/mmcloughlin/avo/internal/prnt" + "github.com/mmcloughlin/avo/printer" +) + +type optab struct { + prnt.Generator + + cfg printer.Config + + table *Table +} + +// NewOptab builds the operator table. This contains a more compact +// representation of the instruction database, containing the data needed for +// instruction builders to match against provided operands, and build the +// selected instruction. +func NewOptab(cfg printer.Config) Interface { + return GoFmt(&optab{cfg: cfg}) +} + +func (t *optab) Generate(is []inst.Instruction) ([]byte, error) { + t.Printf("// %s\n\n", t.cfg.GeneratedWarning()) + t.Printf("package x86\n\n") + t.Printf("import (\n") + t.Printf("\t%q\n", api.ImportPath(api.OperandPackage)) + t.Printf("\t%q\n", api.ImportPath(api.RegisterPackage)) + t.Printf(")\n\n") + + // Generate instruction data table. + t.table = NewTable(is) + + // Size constants. + t.maxOperands(is) + + // Types. + t.operandTypeEnum(is) + t.implicitRegisterEnum(is) + t.enum(t.table.Suffix()) + t.suffixesType(is) + t.suffixesClassEnum(is) + t.isasEnum(is) + t.opcodeEnum(is) + + // Forms table. + t.forms(is) + + return t.Result() +} + +func (t *optab) maxOperands(is []inst.Instruction) { + max := 0 + for _, i := range inst.Instructions { + for _, f := range i.Forms { + a := len(f.Operands) + len(f.ImplicitOperands) + if a > max { + max = a + } + } + } + + t.Comment("maxoperands is the maximum number of operands in an instruction form, including implicit operands.") + t.Printf("const maxoperands = %d\n\n", max) +} + +func (t *optab) operandTypeEnum(is []inst.Instruction) { + // Operand type enum. + e := t.table.OperandType() + t.enum(e) + + // Operand match function. + types := inst.OperandTypes(is) + t.Printf("func (%s %s) Match(op %s) bool {\n", e.Receiver(), e.Name(), api.OperandType) + t.Printf("\tswitch %s {\n", e.Receiver()) + t.Printf("\t\tdefault: return false\n") + for _, typ := range types { + t.Printf("\t\tcase %s: return %s(op)\n", t.table.OperandTypeConst(typ), api.CheckerName(typ)) + } + t.Printf("\t}\n") + t.Printf("}\n\n") +} + +func (t *optab) implicitRegisterEnum(is []inst.Instruction) { + // Implicit register enum. + e := t.table.ImplicitRegister() + t.enum(e) + + // Register conversion function. + registers := inst.ImplicitRegisters(is) + t.Printf("func (%s %s) Register() %s {\n", e.Receiver(), e.Name(), api.RegisterType) + t.Printf("\tswitch %s {\n", e.Receiver()) + t.Printf("\t\tdefault: panic(\"unexpected implicit register type\")\n") + for _, r := range registers { + t.Printf("\t\tcase %s: return %s\n", t.table.ImplicitRegisterConst(r), api.ImplicitRegister(r)) + } + t.Printf("\t}\n") + t.Printf("}\n\n") +} + +func (t *optab) suffixesType(is []inst.Instruction) { + // Declare the type as an array. This requires us to know the maximum number + // of suffixes an instruction can have. + max := 0 + for _, class := range inst.SuffixesClasses(is) { + for _, suffixes := range class { + if len(suffixes) > max { + max = len(suffixes) + } + } + } + + t.Comment("maxsuffixes is the maximum number of suffixes an instruction can have.") + t.Printf("const maxsuffixes = %d\n\n", max) + + name := t.table.SuffixesTypeName() + t.Printf("type %s [maxsuffixes]%s\n", name, t.table.Suffix().Name()) + + // Conversion function to list of strings. + mapname := name + "stringsmap" + + t.Printf("func (s %s) Strings() []string {\n", name) + t.Printf("return %s[s]", mapname) + t.Printf("}\n") + + var entries []string + for _, class := range inst.SuffixesClasses(is) { + for _, suffixes := range class { + entry := fmt.Sprintf("%s: %#v", t.table.SuffixesConst(suffixes), suffixes.Strings()) + entries = append(entries, entry) + } + } + + t.Printf("var %s = map[%s][]string{\n", mapname, name) + sort.Strings(entries) + for _, entry := range entries { + t.Printf("%s,\n", entry) + } + t.Printf("}\n") +} + +func (t *optab) suffixesClassEnum(is []inst.Instruction) { + // Suffixes class enum. + e := t.table.SuffixesClass() + t.enum(e) + + // Mapping method to the set of accepted suffixes. + sets := map[string]string{} + for key, class := range inst.SuffixesClasses(is) { + var entries []string + for _, suffixes := range class { + entry := fmt.Sprintf("%s: true", t.table.SuffixesConst(suffixes)) + entries = append(entries, entry) + } + + sort.Strings(entries) + sets[api.SuffixesClassIdentifier(key)] = "{" + strings.Join(entries, ", ") + "}" + } + + settype := fmt.Sprintf("map[%s]bool", t.table.SuffixesTypeName()) + t.mapping(e, "SuffixesSet", settype, "nil", sets) +} + +func (t *optab) isasEnum(is []inst.Instruction) { + // ISAs enum. + e := t.table.ISAs() + t.enum(e) + + // Mapping method to produce the list of ISAs. + lists := map[string]string{} + for _, isas := range inst.ISACombinations(is) { + lists[api.ISAsIdentifier(isas)] = fmt.Sprintf("%#v", isas) + } + t.mapping(e, "List", "[]string", "nil", lists) +} + +func (t *optab) opcodeEnum(is []inst.Instruction) { + e := t.table.Opcode() + t.enum(e) + t.stringmethod(e) +} + +func (t *optab) forms(is []inst.Instruction) { + // We require all instructions for a given opcode to be in a contiguous + // block. This is likely true already but we'll make a sorted copy to ensure + // the optab is robust to changes elsewhere. + is = append([]inst.Instruction(nil), is...) + sort.Slice(is, func(i, j int) bool { + return is[i].Opcode < is[j].Opcode + }) + + // Output instruction forms table. + table := "forms" + t.Printf("var %s = []form{\n", table) + for _, i := range is { + for _, f := range i.Forms { + t.Printf("{") + + // Basic properties. + t.Printf("%s, ", t.table.OpcodeConst(i.Opcode)) + t.Printf("%s, ", t.table.SuffixesClassConst(f.SuffixesClass())) + t.Printf("%s, ", Features(i, f)) + t.Printf("%s, ", t.table.ISAsConst(f.ISA)) + + // Operands. + t.Printf("%d, ", len(f.Operands)) + t.Printf("oprnds{") + for _, op := range f.Operands { + t.Printf( + "{uint8(%s),false,%s},", + t.table.OperandTypeConst(op.Type), + Action(op.Action), + ) + } + for _, op := range f.ImplicitOperands { + t.Printf( + "{uint8(%s),true,%s},", + t.table.ImplicitRegisterConst(op.Register), + Action(op.Action), + ) + } + t.Printf("}") + + t.Printf("},\n") + } + } + t.Printf("}\n\n") + + // Build mapping from opcode to corresponding forms. + forms := map[string]string{} + n := 0 + for _, i := range is { + e := n + len(i.Forms) + forms[i.Opcode] = fmt.Sprintf("%s[%d:%d]", table, n, e) + n = e + } + + t.mapping(t.table.Opcode(), "Forms", "[]form", "nil", forms) +} + +func (t *optab) enum(e *Enum) { + // Type declaration. + t.Comment(e.Doc()...) + t.Printf("type %s %s\n\n", e.Name(), e.UnderlyingType()) + + // Supported values. + t.Printf("const (\n") + t.Printf("\t%s %s = iota\n", e.None(), e.name) + for _, name := range e.ConstNames() { + t.Printf("\t%s\n", name) + } + t.Printf("\t%s\n", e.MaxName()) + t.Printf(")\n\n") +} + +func (t *optab) mapping(e *Enum, name, ret, zero string, to map[string]string) { + table := strings.ToLower(e.Name() + name + "table") + + r := e.Receiver() + t.Printf("func (%s %s) %s() %s {\n", r, e.Name(), name, ret) + t.Printf("if %s < %s && %s < %s {\n", e.None(), r, r, e.MaxName()) + t.Printf("return %s[%s-1]\n", table, r) + t.Printf("}\n") + t.Printf("return %s\n", zero) + t.Printf("}\n\n") + + t.Printf("var %s = []%s{\n", table, ret) + for _, value := range e.Values() { + t.Printf("\t%s,\n", to[value]) + } + t.Printf("}\n\n") +} + +func (t *optab) stringmethod(e *Enum) { + s := map[string]string{} + for _, value := range e.Values() { + s[value] = strconv.Quote(value) + } + t.mapping(e, "String", "string", `""`, s) +} diff --git a/internal/gen/signature.go b/internal/gen/signature.go deleted file mode 100644 index ea7cdcac..00000000 --- a/internal/gen/signature.go +++ /dev/null @@ -1,122 +0,0 @@ -package gen - -import ( - "bytes" - "fmt" - "sort" - "strconv" - "strings" - "text/tabwriter" - - "github.com/mmcloughlin/avo/internal/inst" -) - -// signature provides access to details about the signature of an instruction function. -type signature interface { - ParameterList() string - Arguments() string - ParameterName(int) string - ParameterSlice() string - Length() string -} - -// argslist is the signature for a function with the given named parameters. -type argslist []string - -func (a argslist) ParameterList() string { return strings.Join(a, ", ") + " " + operandType } -func (a argslist) Arguments() string { return strings.Join(a, ", ") } -func (a argslist) ParameterName(i int) string { return a[i] } -func (a argslist) ParameterSlice() string { - return fmt.Sprintf("[]%s{%s}", operandType, strings.Join(a, ", ")) -} -func (a argslist) Length() string { return strconv.Itoa(len(a)) } - -// variadic is the signature for a variadic function. -type variadic struct { - name string -} - -func (v variadic) ParameterList() string { return v.name + " ..." + operandType } -func (v variadic) Arguments() string { return v.name + "..." } -func (v variadic) ParameterName(i int) string { return fmt.Sprintf("%s[%d]", v.name, i) } -func (v variadic) ParameterSlice() string { return v.name } -func (v variadic) Length() string { return fmt.Sprintf("len(%s)", v.name) } - -// niladic is the signature for a function with no arguments. -type niladic struct{} - -func (n niladic) ParameterList() string { return "" } -func (n niladic) Arguments() string { return "" } -func (n niladic) ParameterName(i int) string { panic("niladic function has no parameters") } -func (n niladic) ParameterSlice() string { return "nil" } -func (n niladic) Length() string { return "0" } - -// params generates the function parameters and a function. -func params(i inst.Instruction) signature { - // Handle the case of forms with multiple arities. - switch { - case i.IsVariadic(): - return variadic{name: "ops"} - case i.IsNiladic(): - return niladic{} - } - - // Generate nice-looking variable names. - n := i.Arity() - ops := make([]string, n) - count := map[string]int{} - for j := 0; j < n; j++ { - // Collect unique lowercase bytes from first characters of operand types. - s := map[byte]bool{} - for _, f := range i.Forms { - c := f.Operands[j].Type[0] - if 'a' <= c && c <= 'z' { - s[c] = true - } - } - - // Operand name is the sorted bytes. - var b []byte - for c := range s { - b = append(b, c) - } - sort.Slice(b, func(i, j int) bool { return b[i] < b[j] }) - name := string(b) - - // Append a counter if we've seen it already. - m := count[name] - count[name]++ - if m > 0 { - name += strconv.Itoa(m) - } - ops[j] = name - } - - return argslist(ops) -} - -// doc generates the lines of the function comment. -func doc(i inst.Instruction) []string { - lines := []string{ - fmt.Sprintf("%s: %s.", i.Opcode, i.Summary), - "", - "Forms:", - "", - } - - // Write a table of instruction forms. - buf := bytes.NewBuffer(nil) - w := tabwriter.NewWriter(buf, 0, 0, 1, ' ', 0) - for _, f := range i.Forms { - row := i.Opcode + "\t" + strings.Join(f.Signature(), "\t") + "\n" - fmt.Fprint(w, row) - } - w.Flush() - - tbl := strings.TrimSpace(buf.String()) - for _, line := range strings.Split(tbl, "\n") { - lines = append(lines, "\t"+line) - } - - return lines -} diff --git a/internal/gen/testing.go b/internal/gen/testing.go new file mode 100644 index 00000000..ee2ecd64 --- /dev/null +++ b/internal/gen/testing.go @@ -0,0 +1,85 @@ +package gen + +import ( + "github.com/mmcloughlin/avo/internal/api" + "github.com/mmcloughlin/avo/internal/inst" + "github.com/mmcloughlin/avo/internal/prnt" +) + +// DeclareTestArguments prints a block of variables declaring a valid operand of +// each operand type. +func DeclareTestArguments(g *prnt.Generator) { + g.Printf("var (\n") + for _, arg := range validArgs { + g.Printf("\t%s operand.Op = %s\n", TestArgumentName(arg.Type), arg.Code) + } + g.Printf(")\n") +} + +// TestSignature returns a function signature with arguments matching the given +// instruction form. Requires variables declared by DeclareTestArguments(). +func TestSignature(f inst.Form) api.Signature { + var names []string + for _, op := range f.Operands { + names = append(names, TestArgumentName(op.Type)) + } + return api.ArgsList(names) +} + +// TestArgumentName returns the name of the variable of operand type t declared +// by DeclareTestArguments(). +func TestArgumentName(t string) string { + return "op" + t +} + +var validArgs = []struct { + Type string + Code string +}{ + // Immediates + {"1", "operand.Imm(1)"}, + {"3", "operand.Imm(3)"}, + {"imm2u", "operand.Imm(3)"}, + {"imm8", "operand.Imm(math.MaxInt8)"}, + {"imm16", "operand.Imm(math.MaxInt16)"}, + {"imm32", "operand.Imm(math.MaxInt32)"}, + {"imm64", "operand.Imm(math.MaxInt64)"}, + + // Registers + {"al", "reg.AL"}, + {"cl", "reg.CL"}, + {"ax", "reg.AX"}, + {"eax", "reg.EAX"}, + {"rax", "reg.RAX"}, + {"r8", "reg.CH"}, + {"r16", "reg.R9W"}, + {"r32", "reg.R10L"}, + {"r64", "reg.R11"}, + {"xmm0", "reg.X0"}, + {"xmm", "reg.X7"}, + {"ymm", "reg.Y15"}, + {"zmm", "reg.Z31"}, + {"k", "reg.K7"}, + + // Memory + {"m", "operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}"}, + {"m8", "operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}"}, + {"m16", "operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}"}, + {"m32", "operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}"}, + {"m64", "operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}"}, + {"m128", "operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}"}, + {"m256", "operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}"}, + {"m512", "operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}"}, + + // Vector memory + {"vm32x", "operand.Mem{Base: reg.R13, Index: reg.X4, Scale: 1}"}, + {"vm64x", "operand.Mem{Base: reg.R13, Index: reg.X8, Scale: 1}"}, + {"vm32y", "operand.Mem{Base: reg.R13, Index: reg.Y4, Scale: 1}"}, + {"vm64y", "operand.Mem{Base: reg.R13, Index: reg.Y8, Scale: 1}"}, + {"vm32z", "operand.Mem{Base: reg.R13, Index: reg.Z4, Scale: 1}"}, + {"vm64z", "operand.Mem{Base: reg.R13, Index: reg.Z8, Scale: 1}"}, + + // Relative + {"rel8", "operand.Rel(math.MaxInt8)"}, + {"rel32", "operand.LabelRef(\"lbl\")"}, +} diff --git a/internal/gen/util.go b/internal/gen/util.go deleted file mode 100644 index 445180c2..00000000 --- a/internal/gen/util.go +++ /dev/null @@ -1,19 +0,0 @@ -package gen - -// cross returns the cross product of the lists in x. -func cross(x [][]string) [][]string { - r := [][]string{nil} - for _, s := range x { - var nxt [][]string - for _, pre := range r { - for _, a := range s { - concat := make([]string, len(pre), len(pre)+1) - copy(concat, pre) - concat = append(concat, a) - nxt = append(nxt, concat) - } - } - r = nxt - } - return r -} diff --git a/internal/gen/util_test.go b/internal/gen/util_test.go deleted file mode 100644 index 9f51c363..00000000 --- a/internal/gen/util_test.go +++ /dev/null @@ -1,46 +0,0 @@ -package gen - -import ( - "reflect" - "testing" -) - -func TestCross(t *testing.T) { - x := [][]string{ - {"a", "b", "c"}, - {"1", "2"}, - {"!", "?"}, - } - expect := [][]string{ - {"a", "1", "!"}, - {"a", "1", "?"}, - {"a", "2", "!"}, - {"a", "2", "?"}, - {"b", "1", "!"}, - {"b", "1", "?"}, - {"b", "2", "!"}, - {"b", "2", "?"}, - {"c", "1", "!"}, - {"c", "1", "?"}, - {"c", "2", "!"}, - {"c", "2", "?"}, - } - got := cross(x) - if !reflect.DeepEqual(got, expect) { - t.Errorf("bad cross product") - } -} - -func TestCrossSimple(t *testing.T) { - x := [][]string{ - {"a", "b"}, - } - expect := [][]string{ - {"a"}, - {"b"}, - } - got := cross(x) - if !reflect.DeepEqual(got, expect) { - t.Errorf("bad cross product") - } -} diff --git a/internal/inst/stress_test.go b/internal/inst/stress_test.go new file mode 100644 index 00000000..193bc276 --- /dev/null +++ b/internal/inst/stress_test.go @@ -0,0 +1,9 @@ +// The godata test relies on a huge generated file, so we limit it to a +// stress-test only build. + +//go:build stress +// +build stress + +package inst + +//go:generate avogen -bootstrap -data ../data -output ztable_test.go godatatest diff --git a/internal/inst/table.go b/internal/inst/table.go index 378b7437..0ec44abf 100644 --- a/internal/inst/table.go +++ b/internal/inst/table.go @@ -1,7 +1,11 @@ package inst +import ( + "sort" + "strings" +) + //go:generate avogen -bootstrap -data ../data -output ztable.go godata -//go:generate avogen -bootstrap -data ../data -output ztable_test.go godatatest // Lookup returns the instruction with the given opcode. Boolean return value // indicates whether the instruction was found. @@ -13,3 +17,119 @@ func Lookup(opcode string) (Instruction, bool) { } return Instruction{}, false } + +// OperandTypes returns all the operand types that appear in the provided +// instructions. +func OperandTypes(is []Instruction) []string { + set := map[string]bool{} + for _, i := range is { + for _, f := range i.Forms { + for _, op := range f.Operands { + set[op.Type] = true + } + } + } + return sortedslice(set) +} + +// ImplicitRegisters returns all the registers that appear as implicit operands +// in the provided instructions. +func ImplicitRegisters(is []Instruction) []string { + set := map[string]bool{} + for _, i := range is { + for _, f := range i.Forms { + for _, op := range f.ImplicitOperands { + set[op.Register] = true + } + } + } + return sortedslice(set) +} + +// UniqueSuffixes returns all the non-empty suffixes that appear in the provided +// instructions. +func UniqueSuffixes(is []Instruction) []Suffix { + // Collect set. + set := map[Suffix]bool{} + for _, i := range is { + for _, f := range i.Forms { + for _, suffixes := range f.SupportedSuffixes() { + for _, suffix := range suffixes { + set[suffix] = true + } + } + } + } + + // Convert to sorted slice. + suffixes := make([]Suffix, 0, len(set)) + for suffix := range set { + suffixes = append(suffixes, suffix) + } + + sort.Slice(suffixes, func(i, j int) bool { + return suffixes[i] < suffixes[j] + }) + + return suffixes +} + +// SuffixesClasses returns all possible classes of suffix combinations. +func SuffixesClasses(is []Instruction) map[string][]Suffixes { + classes := map[string][]Suffixes{} + for _, i := range is { + for _, f := range i.Forms { + class := f.SuffixesClass() + if _, ok := classes[class]; ok { + continue + } + classes[class] = f.SupportedSuffixes() + } + } + return classes +} + +// ISAs returns all the unique ISAs seen in the given instructions. +func ISAs(is []Instruction) []string { + set := map[string]bool{} + for _, i := range is { + for _, f := range i.Forms { + for _, isa := range f.ISA { + set[isa] = true + } + } + } + return sortedslice(set) +} + +// ISACombinations returns all the unique combinations of ISAs seen in the given +// instructions. +func ISACombinations(is []Instruction) [][]string { + var combinations [][]string + seen := map[string]bool{} + for _, i := range is { + for _, f := range i.Forms { + isas := append([]string(nil), f.ISA...) + sort.Strings(isas) + key := strings.Join(isas, ",") + + if !seen[key] { + combinations = append(combinations, isas) + seen[key] = true + } + } + } + return combinations +} + +// sortedslice builds a sorted slice of strings from a set. +func sortedslice(set map[string]bool) []string { + ss := make([]string, 0, len(set)) + for s := range set { + ss = append(ss, s) + } + + sort.Strings(ss) + + return ss +} diff --git a/internal/inst/table_test.go b/internal/inst/table_test.go index 5621459a..e8e647fb 100644 --- a/internal/inst/table_test.go +++ b/internal/inst/table_test.go @@ -3,6 +3,7 @@ package inst_test import ( "io/ioutil" "reflect" + "sort" "strings" "testing" @@ -70,6 +71,84 @@ func TestInstructionProperties(t *testing.T) { } } +func TestHaveSuffixes(t *testing.T) { + for _, i := range inst.Instructions { + for _, f := range i.Forms { + if len(f.SupportedSuffixes()) == 0 { + t.Errorf("%s: no supported suffixes", i.Opcode) + } + } + } +} + +func TestAcceptsSuffixes(t *testing.T) { + // Verify consistency between the AcceptsSuffixes and SupportedSuffixes methods. + for _, i := range inst.Instructions { + for _, f := range i.Forms { + expect := false + for _, suffixes := range f.SupportedSuffixes() { + if len(suffixes) > 0 { + expect = true + } + } + + if got := f.AcceptsSuffixes(); got != expect { + t.Errorf("%s: AcceptsSuffixes() = %v; expect %v", i.Opcode, got, expect) + } + } + } +} + +func TestSuffixesClasses(t *testing.T) { + // Verify that all instructions in a suffix class support the same suffixes. + reps := map[string][]inst.Suffixes{} + for _, i := range inst.Instructions { + for _, f := range i.Forms { + class := f.SuffixesClass() + expect, ok := reps[class] + if !ok { + t.Logf("new class %q: representative from instruction %s", class, i.Opcode) + reps[class] = f.SupportedSuffixes() + continue + } + + got := f.SupportedSuffixes() + if !reflect.DeepEqual(expect, got) { + t.Fatalf("suffixes mismatch for class %q", class) + } + } + } +} + +func TestSuffixesHaveSummaries(t *testing.T) { + set := map[inst.Suffix]bool{} + for _, i := range inst.Instructions { + for _, f := range i.Forms { + for _, suffixes := range f.SupportedSuffixes() { + for _, suffix := range suffixes { + set[suffix] = true + } + } + } + } + + for suffix := range set { + if suffix.Summary() == "" { + t.Errorf("suffix %q missing summary", suffix) + } + } +} + +func TestISASorted(t *testing.T) { + for _, i := range inst.Instructions { + for _, f := range i.Forms { + if !sort.StringsAreSorted(f.ISA) { + t.Fatalf("%s: isa not sorted", i.Opcode) + } + } + } +} + func TestAssembles(t *testing.T) { g := gen.NewAsmTest(printer.NewArgvConfig()) b, err := g.Generate(inst.Instructions) @@ -143,17 +222,86 @@ func TestCancellingInputs(t *testing.T) { n := 0 for _, op := range f.Operands { if op.Action.Read() { - n++ switch op.Type { - case "r8", "r16", "r32", "r64", "xmm", "ymm": - // pass + case "r8", "r16", "r32", "r64", "xmm", "ymm", "zmm": + n++ + case "k": + // skip mask registers default: t.Errorf("%s: unexpected operand type %q for self-cancelling input", i.Opcode, op.Type) } } } - if n != 2 { - t.Errorf("%s: expected two inputs for self-cancelling form", i.Opcode) + if n < 2 { + t.Log(f) + t.Errorf("%s: expected at least two inputs for self-cancelling form", i.Opcode) + } + } + } +} + +func TestFlagOperandTypes(t *testing.T) { + for _, i := range inst.Instructions { + for _, f := range i.Forms { + // Check for memory operands. + mem := false + for _, op := range f.Operands { + if strings.HasPrefix(op.Type, "m") { + mem = true + } + } + + // Broadcast applies to memory instructions only. + if f.Broadcast && !mem { + t.Errorf("%s: expect broadcast form to have memory operand", i.Opcode) + } + + // Embedded rounding must be register-only. + if f.EmbeddedRounding && mem { + t.Errorf("%s: embedded-rounding only supported for register-only forms", i.Opcode) + } + + // Suppress all exceptions is register only. + if f.SuppressAllExceptions && mem { + t.Errorf("%s: embedded-rounding only supported for register-only forms", i.Opcode) + } + } + } +} + +func TestFlagCombinations(t *testing.T) { + for _, i := range inst.Instructions { + for _, f := range i.Forms { + if f.EmbeddedRounding && f.SuppressAllExceptions { + t.Errorf("%s: embedded-rounding cannot be combined with suppress-all-exceptions", i.Opcode) + } + if f.Broadcast && f.EmbeddedRounding { + t.Errorf("%s: broadcast cannot be combined with embedded-rounding", i.Opcode) + } + if f.Broadcast && f.SuppressAllExceptions { + t.Errorf("%s: broadcast cannot be combined with suppress-all-exceptions", i.Opcode) + } + } + } +} + +func TestZeroingHasMask(t *testing.T) { + for _, i := range inst.Instructions { + for _, f := range i.Forms { + if !f.Zeroing { + continue + } + + // Expect mask operand. + mask := false + for _, op := range f.Operands { + if op.Type == "k" { + mask = true + } + } + + if !mask { + t.Errorf("%s: expect mask operand if zeroing is enabled", i.Opcode) } } } diff --git a/internal/inst/types.go b/internal/inst/types.go index 2732da35..0d65b96c 100644 --- a/internal/inst/types.go +++ b/internal/inst/types.go @@ -10,7 +10,7 @@ type Instruction struct { Opcode string // Golang assembly mnemonic AliasOf string // Opcode of instruction that this is an alias for Summary string // Description of the instruction - Forms []Form // Accepted operand forms + Forms // Accepted operand forms } // IsTerminal reports whether the instruction exits a function. @@ -40,10 +40,13 @@ func (i Instruction) IsConditionalBranch() bool { return i.IsBranch() && i.Opcode != "JMP" } +// Forms is a collection of instruction forms. +type Forms []Form + // Arities returns the unique arities among the instruction forms. -func (i Instruction) Arities() []int { +func (fs Forms) Arities() []int { s := map[int]bool{} - for _, f := range i.Forms { + for _, f := range fs { s[f.Arity()] = true } a := make([]int, 0, len(s)) @@ -56,22 +59,22 @@ func (i Instruction) Arities() []int { // Arity is a convenience for returning the unique instruction arity when you // know it is not variadic. Panics for a variadic instruction. -func (i Instruction) Arity() int { - if i.IsVariadic() { +func (fs Forms) Arity() int { + if fs.IsVariadic() { panic("variadic") } - a := i.Arities() + a := fs.Arities() return a[0] } // IsVariadic reports whether the instruction has more than one arity. -func (i Instruction) IsVariadic() bool { - return len(i.Arities()) > 1 +func (fs Forms) IsVariadic() bool { + return len(fs.Arities()) > 1 } // IsNiladic reports whether the instruction takes no operands. -func (i Instruction) IsNiladic() bool { - a := i.Arities() +func (fs Forms) IsNiladic() bool { + a := fs.Arities() return len(a) == 1 && a[0] == 0 } @@ -86,12 +89,35 @@ type Form struct { // Registers read or written but not explicitly passed to the instruction. ImplicitOperands []ImplicitOperand + // Encoding type required for this instruction form. + EncodingType EncodingType + // CancellingInputs indicates this instruction form has no dependency on the // input operands when they refer to the same register. The classic example of // this is "XORQ RAX, RAX", in which case the output has no dependence on the // value of RAX. Instruction forms with cancelling inputs have only two input // operands, which have the same register type. CancellingInputs bool + + // Zeroing indicates whether the instruction form uses AVX-512 zeroing. This + // is the .Z suffix in Go, usually indicated with {z} operand suffix in + // Intel manuals. + Zeroing bool + + // EmbeddedRounding indicates whether the instruction form uses AVX-512 + // embedded rounding. This is the RN_SAE, RZ_SAE, RD_SAE and RU_SAE suffixes + // in Go, usually indicated with {er} in Intel manuals. + EmbeddedRounding bool + + // SuppressAllExceptions indicates whether the instruction form uses AVX-512 + // "suppress all exceptions". This is the SAE suffix in Go, usually + // indicated with {sae} in Intel manuals. + SuppressAllExceptions bool + + // Broadcast indicates whether the instruction form uses AVX-512 + // broadcast. This is the BCST suffix in Go, usually indicated by operand + // types like "m64bcst" in Intel manuals. + Broadcast bool } // Arity returns the number of operands this form expects. @@ -108,6 +134,143 @@ func (f Form) Signature() []string { return s } +// Clone the instruction form. +func (f Form) Clone() Form { + c := f + c.ISA = append([]string(nil), f.ISA...) + c.Operands = append([]Operand(nil), f.Operands...) + c.ImplicitOperands = append([]ImplicitOperand(nil), f.ImplicitOperands...) + return c +} + +// AcceptsSuffixes reports whether this form takes any opcode suffixes. +func (f Form) AcceptsSuffixes() bool { + return f.Broadcast || f.EmbeddedRounding || f.SuppressAllExceptions || f.Zeroing +} + +// SuffixesClass returns a key representing the class of instruction suffixes it +// accepts. All instructions sharing a suffix class accept the same suffixes. +func (f Form) SuffixesClass() string { + if !f.AcceptsSuffixes() { + return "nil" + } + var parts []string + for _, flag := range []struct { + Name string + Enabled bool + }{ + {"er", f.EmbeddedRounding}, + {"sae", f.SuppressAllExceptions}, + {"bcst", f.Broadcast}, + {"z", f.Zeroing}, + } { + if flag.Enabled { + parts = append(parts, flag.Name) + } + } + return strings.Join(parts, "_") +} + +// SupportedSuffixes returns the list of all possible suffix combinations +// supported by this instruction form. +func (f Form) SupportedSuffixes() []Suffixes { + suffixes := []Suffixes{ + {}, + } + + add := func(ss ...Suffix) { + var exts []Suffixes + for _, s := range ss { + for _, suffix := range suffixes { + ext := append(Suffixes(nil), suffix...) + ext = append(ext, s) + exts = append(exts, ext) + } + } + suffixes = exts + } + + if f.Broadcast { + add(BCST) + } + + if f.EmbeddedRounding { + add(RN_SAE, RZ_SAE, RD_SAE, RU_SAE) + } + + if f.SuppressAllExceptions { + add(SAE) + } + + if f.Zeroing { + add(Z) + } + + return suffixes +} + +// Suffix is an opcode suffix. +type Suffix string + +// Supported opcode suffixes in x86 assembly. +const ( + BCST Suffix = "BCST" + RN_SAE Suffix = "RN_SAE" + RZ_SAE Suffix = "RZ_SAE" + RD_SAE Suffix = "RD_SAE" + RU_SAE Suffix = "RU_SAE" + SAE Suffix = "SAE" + Z Suffix = "Z" +) + +func (s Suffix) String() string { + return string(s) +} + +// Summary of the opcode suffix, for documentation purposes. +func (s Suffix) Summary() string { + return suffixsummary[s] +} + +var suffixsummary = map[Suffix]string{ + BCST: "Broadcast", + RN_SAE: "Round Towards Nearest", + RZ_SAE: "Round Towards Zero", + RD_SAE: "Round Towards Negative Infinity", + RU_SAE: "Round Towards Positive Infinity", + SAE: "Suppress All Exceptions", + Z: "Zeroing Masking", +} + +// Suffixes is a list of opcode suffixes. +type Suffixes []Suffix + +// String returns the dot-separated suffixes. +func (s Suffixes) String() string { return s.Join(".") } + +// Join suffixes with the given separator. +func (s Suffixes) Join(sep string) string { + return strings.Join(s.Strings(), sep) +} + +// Strings returns the suffixes as strings. +func (s Suffixes) Strings() []string { + var ss []string + for _, suffix := range s { + ss = append(ss, suffix.String()) + } + return ss +} + +// Summaries returns all the suffix summaries. +func (s Suffixes) Summaries() []string { + var summaries []string + for _, suffix := range s { + summaries = append(summaries, suffix.Summary()) + } + return summaries +} + // Operand is an operand to an instruction, describing the expected type and read/write action. type Operand struct { Type string @@ -125,9 +288,10 @@ type Action uint8 // Possible Action types. const ( - R Action = 0x1 - W Action = 0x2 - RW Action = R | W + R Action = 1 << iota // Read + W // Write + + RW Action = R | W // Read-Write ) // ActionFromReadWrite builds an Action from boolean flags. @@ -142,19 +306,24 @@ func ActionFromReadWrite(r, w bool) Action { return a } -// Contains reports whether a supports all actions in s. -func (a Action) Contains(s Action) bool { +// ContainsAll reports whether a supports all actions in s. +func (a Action) ContainsAll(s Action) bool { return (a & s) == s } +// ContainsAny reports whether a supports any actions in s. +func (a Action) ContainsAny(s Action) bool { + return (a & s) != 0 +} + // Read reports whether a supports read. func (a Action) Read() bool { - return a.Contains(R) + return a.ContainsAll(R) } // Write reports whether a supports write. func (a Action) Write() bool { - return a.Contains(W) + return a.ContainsAll(W) } // String represents a as a human-readable string. @@ -168,3 +337,14 @@ func (a Action) String() string { } return s } + +// EncodingType specifies a category of encoding types. +type EncodingType uint8 + +// Supported encoding types. +const ( + EncodingTypeLegacy EncodingType = 1 + iota + EncodingTypeREX + EncodingTypeVEX + EncodingTypeEVEX +) diff --git a/internal/inst/types_test.go b/internal/inst/types_test.go new file mode 100644 index 00000000..a0e149c3 --- /dev/null +++ b/internal/inst/types_test.go @@ -0,0 +1,82 @@ +package inst + +import ( + "reflect" + "testing" +) + +func TestFormSupportedSuffixes(t *testing.T) { + cases := []struct { + Form Form + Expect []Suffixes + }{ + { + Form: Form{}, + Expect: []Suffixes{ + {}, + }, + }, + { + Form: Form{ + Broadcast: true, + }, + Expect: []Suffixes{ + {BCST}, + }, + }, + { + Form: Form{ + EmbeddedRounding: true, + }, + Expect: []Suffixes{ + {RN_SAE}, + {RZ_SAE}, + {RD_SAE}, + {RU_SAE}, + }, + }, + { + Form: Form{ + SuppressAllExceptions: true, + }, + Expect: []Suffixes{ + {SAE}, + }, + }, + { + Form: Form{ + Zeroing: true, + }, + Expect: []Suffixes{ + {Z}, + }, + }, + { + Form: Form{ + EmbeddedRounding: true, + Zeroing: true, + }, + Expect: []Suffixes{ + {RN_SAE, Z}, + {RZ_SAE, Z}, + {RD_SAE, Z}, + {RU_SAE, Z}, + }, + }, + { + Form: Form{ + Broadcast: true, + Zeroing: true, + }, + Expect: []Suffixes{ + {BCST, Z}, + }, + }, + } + for _, c := range cases { + got := c.Form.SupportedSuffixes() + if !reflect.DeepEqual(c.Expect, got) { + t.Errorf("%v.SupportedSuffixes() = %v; expect %v", c.Form, got, c.Expect) + } + } +} diff --git a/internal/inst/ztable.go b/internal/inst/ztable.go index b9ea9167..dd1b04f5 100644 --- a/internal/inst/ztable.go +++ b/internal/inst/ztable.go @@ -12,36 +12,42 @@ var Instructions = []Instruction{ {Type: "imm8", Action: 0x0}, {Type: "al", Action: 0x3}, }, + EncodingType: 0x1, }, { Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r8", Action: 0x3}, + {Type: "m8", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r8", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "r8", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "m8", Action: 0x1}, {Type: "r8", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "r8", Action: 0x1}, {Type: "m8", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r8", Action: 0x1}, - {Type: "m8", Action: 0x3}, + {Type: "r8", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -54,48 +60,56 @@ var Instructions = []Instruction{ {Type: "imm32", Action: 0x0}, {Type: "eax", Action: 0x3}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r32", Action: 0x3}, + {Type: "imm32", Action: 0x0}, + {Type: "m32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "imm32", Action: 0x0}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m32", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm32", Action: 0x0}, + {Type: "r32", Action: 0x1}, {Type: "m32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r32", Action: 0x1}, - {Type: "m32", Action: 0x3}, + {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -106,50 +120,58 @@ var Instructions = []Instruction{ { Operands: []Operand{ {Type: "imm32", Action: 0x0}, - {Type: "rax", Action: 0x3}, + {Type: "m64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "imm32", Action: 0x0}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "imm32", Action: 0x0}, - {Type: "r64", Action: 0x3}, + {Type: "rax", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m64", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm32", Action: 0x0}, + {Type: "r64", Action: 0x1}, {Type: "m64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r64", Action: 0x1}, - {Type: "m64", Action: 0x3}, + {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -162,48 +184,56 @@ var Instructions = []Instruction{ {Type: "imm16", Action: 0x0}, {Type: "ax", Action: 0x3}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r16", Action: 0x3}, + {Type: "imm16", Action: 0x0}, + {Type: "m16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "imm16", Action: 0x0}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r16", Action: 0x1}, - {Type: "r16", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m16", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m16", Action: 0x3}, + {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm16", Action: 0x0}, + {Type: "r16", Action: 0x1}, {Type: "m16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r16", Action: 0x1}, - {Type: "m16", Action: 0x3}, + {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -214,16 +244,18 @@ var Instructions = []Instruction{ { ISA: []string{"ADX"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"ADX"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -234,16 +266,18 @@ var Instructions = []Instruction{ { ISA: []string{"ADX"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"ADX"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -256,36 +290,42 @@ var Instructions = []Instruction{ {Type: "imm8", Action: 0x0}, {Type: "al", Action: 0x3}, }, + EncodingType: 0x1, }, { Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r8", Action: 0x3}, + {Type: "m8", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r8", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "r8", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "m8", Action: 0x1}, {Type: "r8", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "r8", Action: 0x1}, {Type: "m8", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r8", Action: 0x1}, - {Type: "m8", Action: 0x3}, + {Type: "r8", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -298,48 +338,56 @@ var Instructions = []Instruction{ {Type: "imm32", Action: 0x0}, {Type: "eax", Action: 0x3}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r32", Action: 0x3}, + {Type: "imm32", Action: 0x0}, + {Type: "m32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "imm32", Action: 0x0}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m32", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm32", Action: 0x0}, + {Type: "r32", Action: 0x1}, {Type: "m32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r32", Action: 0x1}, - {Type: "m32", Action: 0x3}, + {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -350,16 +398,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -370,16 +420,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -390,50 +442,58 @@ var Instructions = []Instruction{ { Operands: []Operand{ {Type: "imm32", Action: 0x0}, - {Type: "rax", Action: 0x3}, + {Type: "m64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "imm32", Action: 0x0}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "imm32", Action: 0x0}, - {Type: "r64", Action: 0x3}, + {Type: "rax", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m64", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm32", Action: 0x0}, + {Type: "r64", Action: 0x1}, {Type: "m64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r64", Action: 0x1}, - {Type: "m64", Action: 0x3}, + {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -444,16 +504,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -464,16 +526,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -484,16 +548,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE3"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE3"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -504,16 +570,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE3"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE3"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -526,48 +594,56 @@ var Instructions = []Instruction{ {Type: "imm16", Action: 0x0}, {Type: "ax", Action: 0x3}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r16", Action: 0x3}, + {Type: "imm16", Action: 0x0}, + {Type: "m16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "imm16", Action: 0x0}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r16", Action: 0x1}, - {Type: "r16", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m16", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m16", Action: 0x3}, + {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm16", Action: 0x0}, + {Type: "r16", Action: 0x1}, {Type: "m16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r16", Action: 0x1}, - {Type: "m16", Action: 0x3}, + {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -578,16 +654,18 @@ var Instructions = []Instruction{ { ISA: []string{"ADX"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"ADX"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -598,16 +676,18 @@ var Instructions = []Instruction{ { ISA: []string{"ADX"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"ADX"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -618,16 +698,18 @@ var Instructions = []Instruction{ { ISA: []string{"AES"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"AES"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, @@ -638,16 +720,18 @@ var Instructions = []Instruction{ { ISA: []string{"AES"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"AES"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, @@ -658,16 +742,18 @@ var Instructions = []Instruction{ { ISA: []string{"AES"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"AES"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -678,16 +764,18 @@ var Instructions = []Instruction{ { ISA: []string{"AES"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"AES"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -698,16 +786,18 @@ var Instructions = []Instruction{ { ISA: []string{"AES"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"AES"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, @@ -719,17 +809,19 @@ var Instructions = []Instruction{ ISA: []string{"AES"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"AES"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, @@ -742,36 +834,42 @@ var Instructions = []Instruction{ {Type: "imm8", Action: 0x0}, {Type: "al", Action: 0x3}, }, + EncodingType: 0x1, }, { Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r8", Action: 0x3}, + {Type: "m8", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r8", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "r8", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "m8", Action: 0x1}, {Type: "r8", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "r8", Action: 0x1}, {Type: "m8", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r8", Action: 0x1}, - {Type: "m8", Action: 0x3}, + {Type: "r8", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -784,48 +882,56 @@ var Instructions = []Instruction{ {Type: "imm32", Action: 0x0}, {Type: "eax", Action: 0x3}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r32", Action: 0x3}, + {Type: "imm32", Action: 0x0}, + {Type: "m32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "imm32", Action: 0x0}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m32", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm32", Action: 0x0}, + {Type: "r32", Action: 0x1}, {Type: "m32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r32", Action: 0x1}, - {Type: "m32", Action: 0x3}, + {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -836,19 +942,21 @@ var Instructions = []Instruction{ { ISA: []string{"BMI"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x3, }, { ISA: []string{"BMI"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x2}, }, + EncodingType: 0x3, + CancellingInputs: true, }, }, }, @@ -859,17 +967,19 @@ var Instructions = []Instruction{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, + CancellingInputs: true, }, }, }, @@ -880,17 +990,19 @@ var Instructions = []Instruction{ { ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x2, }, { ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, + CancellingInputs: true, }, }, }, @@ -901,19 +1013,21 @@ var Instructions = []Instruction{ { ISA: []string{"BMI"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x3, }, { ISA: []string{"BMI"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x2}, }, + EncodingType: 0x3, + CancellingInputs: true, }, }, }, @@ -924,16 +1038,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -944,16 +1060,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -964,50 +1082,58 @@ var Instructions = []Instruction{ { Operands: []Operand{ {Type: "imm32", Action: 0x0}, - {Type: "rax", Action: 0x3}, + {Type: "m64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "imm32", Action: 0x0}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "imm32", Action: 0x0}, - {Type: "r64", Action: 0x3}, + {Type: "rax", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m64", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm32", Action: 0x0}, + {Type: "r64", Action: 0x1}, {Type: "m64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r64", Action: 0x1}, - {Type: "m64", Action: 0x3}, + {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -1020,48 +1146,56 @@ var Instructions = []Instruction{ {Type: "imm16", Action: 0x0}, {Type: "ax", Action: 0x3}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r16", Action: 0x3}, + {Type: "imm16", Action: 0x0}, + {Type: "m16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "imm16", Action: 0x0}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r16", Action: 0x1}, - {Type: "r16", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m16", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m16", Action: 0x3}, + {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm16", Action: 0x0}, + {Type: "r16", Action: 0x1}, {Type: "m16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r16", Action: 0x1}, - {Type: "m16", Action: 0x3}, + {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -1073,17 +1207,19 @@ var Instructions = []Instruction{ ISA: []string{"BMI"}, Operands: []Operand{ {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"BMI"}, Operands: []Operand{ {Type: "r32", Action: 0x1}, - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, @@ -1095,17 +1231,19 @@ var Instructions = []Instruction{ ISA: []string{"BMI"}, Operands: []Operand{ {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"BMI"}, Operands: []Operand{ {Type: "r64", Action: 0x1}, - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, @@ -1117,17 +1255,19 @@ var Instructions = []Instruction{ ISA: []string{"SSE4.1"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE4.1"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -1139,17 +1279,19 @@ var Instructions = []Instruction{ ISA: []string{"SSE4.1"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE4.1"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -1161,17 +1303,19 @@ var Instructions = []Instruction{ ISA: []string{"SSE4.1"}, Operands: []Operand{ {Type: "xmm0", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE4.1"}, Operands: []Operand{ {Type: "xmm0", Action: 0x1}, - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -1183,17 +1327,19 @@ var Instructions = []Instruction{ ISA: []string{"SSE4.1"}, Operands: []Operand{ {Type: "xmm0", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE4.1"}, Operands: []Operand{ {Type: "xmm0", Action: 0x1}, - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -1204,16 +1350,18 @@ var Instructions = []Instruction{ { ISA: []string{"BMI"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"BMI"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, @@ -1224,16 +1372,18 @@ var Instructions = []Instruction{ { ISA: []string{"BMI"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"BMI"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, @@ -1244,16 +1394,18 @@ var Instructions = []Instruction{ { ISA: []string{"BMI"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"BMI"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, @@ -1264,16 +1416,18 @@ var Instructions = []Instruction{ { ISA: []string{"BMI"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"BMI"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, @@ -1284,16 +1438,18 @@ var Instructions = []Instruction{ { ISA: []string{"BMI"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"BMI"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, @@ -1304,16 +1460,18 @@ var Instructions = []Instruction{ { ISA: []string{"BMI"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"BMI"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, @@ -1323,15 +1481,17 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -1341,15 +1501,17 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -1359,15 +1521,17 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -1377,15 +1541,17 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -1395,15 +1561,17 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -1413,15 +1581,17 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -1433,6 +1603,7 @@ var Instructions = []Instruction{ Operands: []Operand{ {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -1444,6 +1615,7 @@ var Instructions = []Instruction{ Operands: []Operand{ {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -1454,26 +1626,30 @@ var Instructions = []Instruction{ { Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r32", Action: 0x3}, + {Type: "m32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "r32", Action: 0x1}, {Type: "m32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r32", Action: 0x1}, - {Type: "m32", Action: 0x3}, + {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -1484,26 +1660,30 @@ var Instructions = []Instruction{ { Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r64", Action: 0x3}, + {Type: "m64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "r64", Action: 0x1}, {Type: "m64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r64", Action: 0x1}, - {Type: "m64", Action: 0x3}, + {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -1514,26 +1694,30 @@ var Instructions = []Instruction{ { Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r16", Action: 0x3}, + {Type: "m16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r16", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "r16", Action: 0x1}, {Type: "m16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r16", Action: 0x1}, - {Type: "m16", Action: 0x3}, + {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -1544,26 +1728,30 @@ var Instructions = []Instruction{ { Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "r32", Action: 0x1}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "r32", Action: 0x1}, {Type: "m32", Action: 0x1}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r32", Action: 0x1}, - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, }, + EncodingType: 0x2, }, }, }, @@ -1574,26 +1762,30 @@ var Instructions = []Instruction{ { Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "r64", Action: 0x1}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "r64", Action: 0x1}, {Type: "m64", Action: 0x1}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r64", Action: 0x1}, - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, }, + EncodingType: 0x2, }, }, }, @@ -1604,26 +1796,30 @@ var Instructions = []Instruction{ { Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r32", Action: 0x3}, + {Type: "m32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "r32", Action: 0x1}, {Type: "m32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r32", Action: 0x1}, - {Type: "m32", Action: 0x3}, + {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -1634,26 +1830,30 @@ var Instructions = []Instruction{ { Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r64", Action: 0x3}, + {Type: "m64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "r64", Action: 0x1}, {Type: "m64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r64", Action: 0x1}, - {Type: "m64", Action: 0x3}, + {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -1664,26 +1864,30 @@ var Instructions = []Instruction{ { Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r16", Action: 0x3}, + {Type: "m16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r16", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "r16", Action: 0x1}, {Type: "m16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r16", Action: 0x1}, - {Type: "m16", Action: 0x3}, + {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -1694,26 +1898,30 @@ var Instructions = []Instruction{ { Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r32", Action: 0x3}, + {Type: "m32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "r32", Action: 0x1}, {Type: "m32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r32", Action: 0x1}, - {Type: "m32", Action: 0x3}, + {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -1724,26 +1932,30 @@ var Instructions = []Instruction{ { Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r64", Action: 0x3}, + {Type: "m64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "r64", Action: 0x1}, {Type: "m64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r64", Action: 0x1}, - {Type: "m64", Action: 0x3}, + {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -1754,26 +1966,30 @@ var Instructions = []Instruction{ { Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r16", Action: 0x3}, + {Type: "m16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r16", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "r16", Action: 0x1}, {Type: "m16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r16", Action: 0x1}, - {Type: "m16", Action: 0x3}, + {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -1784,26 +2000,30 @@ var Instructions = []Instruction{ { Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x1}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r16", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "r16", Action: 0x1}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "r16", Action: 0x1}, {Type: "m16", Action: 0x1}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r16", Action: 0x1}, - {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x1}, }, + EncodingType: 0x2, }, }, }, @@ -1815,17 +2035,19 @@ var Instructions = []Instruction{ ISA: []string{"BMI2"}, Operands: []Operand{ {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"BMI2"}, Operands: []Operand{ {Type: "r32", Action: 0x1}, - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, @@ -1837,17 +2059,19 @@ var Instructions = []Instruction{ ISA: []string{"BMI2"}, Operands: []Operand{ {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"BMI2"}, Operands: []Operand{ {Type: "r64", Action: 0x1}, - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, @@ -1859,6 +2083,7 @@ var Instructions = []Instruction{ Operands: []Operand{ {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -1872,6 +2097,7 @@ var Instructions = []Instruction{ {Register: "ax", Action: 0x2}, {Register: "al", Action: 0x1}, }, + EncodingType: 0x1, }, }, }, @@ -1885,6 +2111,7 @@ var Instructions = []Instruction{ {Register: "eax", Action: 0x1}, {Register: "edx", Action: 0x2}, }, + EncodingType: 0x1, }, }, }, @@ -1898,6 +2125,7 @@ var Instructions = []Instruction{ {Register: "eax", Action: 0x1}, {Register: "rax", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, @@ -1906,7 +2134,8 @@ var Instructions = []Instruction{ Summary: "Clear Carry Flag", Forms: []Form{ { - Operands: []Operand{}, + Operands: []Operand{}, + EncodingType: 0x1, }, }, }, @@ -1915,7 +2144,8 @@ var Instructions = []Instruction{ Summary: "Clear Direction Flag", Forms: []Form{ { - Operands: []Operand{}, + Operands: []Operand{}, + EncodingType: 0x1, }, }, }, @@ -1928,6 +2158,7 @@ var Instructions = []Instruction{ Operands: []Operand{ {Type: "m8", Action: 0x1}, }, + EncodingType: 0x2, }, }, }, @@ -1940,6 +2171,7 @@ var Instructions = []Instruction{ Operands: []Operand{ {Type: "m8", Action: 0x1}, }, + EncodingType: 0x2, }, }, }, @@ -1948,7 +2180,8 @@ var Instructions = []Instruction{ Summary: "Complement Carry Flag", Forms: []Form{ { - Operands: []Operand{}, + Operands: []Operand{}, + EncodingType: 0x1, }, }, }, @@ -1959,16 +2192,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -1979,16 +2214,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -1999,16 +2236,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2019,16 +2258,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2039,16 +2280,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2059,16 +2302,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2079,16 +2324,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2099,16 +2346,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2119,16 +2368,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2139,16 +2390,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2159,16 +2412,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2179,16 +2434,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2199,16 +2456,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2219,16 +2478,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2239,16 +2500,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2259,16 +2522,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2279,16 +2544,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2299,16 +2566,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2319,16 +2588,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2339,16 +2610,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2359,16 +2632,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2379,16 +2654,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2399,16 +2676,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2419,16 +2698,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2439,16 +2720,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2459,16 +2742,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2479,16 +2764,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2499,16 +2786,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2519,16 +2808,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2539,16 +2830,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2559,16 +2852,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2579,16 +2874,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2599,16 +2896,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2619,16 +2918,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2639,16 +2940,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2659,16 +2962,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2679,16 +2984,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2699,16 +3006,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2719,16 +3028,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2739,16 +3050,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2759,16 +3072,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2779,16 +3094,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2799,16 +3116,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2819,16 +3138,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2839,16 +3160,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2859,16 +3182,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2879,16 +3204,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2899,16 +3226,18 @@ var Instructions = []Instruction{ { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"CMOV"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -2921,37 +3250,43 @@ var Instructions = []Instruction{ {Type: "al", Action: 0x1}, {Type: "imm8", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "r8", Action: 0x1}, + {Type: "m8", Action: 0x1}, {Type: "imm8", Action: 0x0}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r8", Action: 0x1}, + {Type: "m8", Action: 0x1}, {Type: "r8", Action: 0x1}, }, - CancellingInputs: true, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r8", Action: 0x1}, - {Type: "m8", Action: 0x1}, + {Type: "imm8", Action: 0x0}, }, + EncodingType: 0x2, }, { Operands: []Operand{ + {Type: "r8", Action: 0x1}, {Type: "m8", Action: 0x1}, - {Type: "imm8", Action: 0x0}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m8", Action: 0x1}, + {Type: "r8", Action: 0x1}, {Type: "r8", Action: 0x1}, }, + EncodingType: 0x2, + CancellingInputs: true, }, }, }, @@ -2964,49 +3299,57 @@ var Instructions = []Instruction{ {Type: "eax", Action: 0x1}, {Type: "imm32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "imm32", Action: 0x0}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "imm32", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "imm8", Action: 0x0}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x1}, }, - CancellingInputs: true, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r32", Action: 0x1}, - {Type: "m32", Action: 0x1}, + {Type: "imm32", Action: 0x0}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "imm8", Action: 0x0}, }, + EncodingType: 0x2, }, { Operands: []Operand{ + {Type: "r32", Action: 0x1}, {Type: "m32", Action: 0x1}, - {Type: "imm32", Action: 0x0}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x1}, }, + EncodingType: 0x2, + CancellingInputs: true, }, }, }, @@ -3017,18 +3360,20 @@ var Instructions = []Instruction{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, {Type: "imm8", Action: 0x0}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, {Type: "imm8", Action: 0x0}, }, + EncodingType: 0x2, }, }, }, @@ -3039,18 +3384,20 @@ var Instructions = []Instruction{ { ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, {Type: "imm8", Action: 0x0}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, {Type: "imm8", Action: 0x0}, }, + EncodingType: 0x2, }, }, }, @@ -3060,52 +3407,60 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rax", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "imm32", Action: 0x0}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "imm8", Action: 0x0}, }, + EncodingType: 0x2, }, { Operands: []Operand{ + {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x1}, - {Type: "imm32", Action: 0x0}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x1}, + {Type: "imm32", Action: 0x0}, }, - CancellingInputs: true, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r64", Action: 0x1}, - {Type: "m64", Action: 0x1}, + {Type: "imm8", Action: 0x0}, }, + EncodingType: 0x2, }, { Operands: []Operand{ + {Type: "r64", Action: 0x1}, {Type: "m64", Action: 0x1}, - {Type: "imm8", Action: 0x0}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "imm32", Action: 0x0}, + {Type: "r64", Action: 0x1}, + {Type: "r64", Action: 0x1}, }, + EncodingType: 0x2, + CancellingInputs: true, }, { Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "r64", Action: 0x1}, + {Type: "rax", Action: 0x1}, + {Type: "imm32", Action: 0x0}, }, + EncodingType: 0x2, }, }, }, @@ -3116,18 +3471,20 @@ var Instructions = []Instruction{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x3}, {Type: "imm8", Action: 0x0}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, {Type: "imm8", Action: 0x0}, }, + EncodingType: 0x2, }, }, }, @@ -3138,18 +3495,20 @@ var Instructions = []Instruction{ { ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x3}, {Type: "imm8", Action: 0x0}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, {Type: "imm8", Action: 0x0}, }, + EncodingType: 0x2, }, }, }, @@ -3162,49 +3521,57 @@ var Instructions = []Instruction{ {Type: "ax", Action: 0x1}, {Type: "imm16", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "r16", Action: 0x1}, - {Type: "imm8", Action: 0x0}, + {Type: "m16", Action: 0x1}, + {Type: "imm16", Action: 0x0}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r16", Action: 0x1}, - {Type: "imm16", Action: 0x0}, + {Type: "m16", Action: 0x1}, + {Type: "imm8", Action: 0x0}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x1}, {Type: "r16", Action: 0x1}, }, - CancellingInputs: true, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r16", Action: 0x1}, - {Type: "m16", Action: 0x1}, + {Type: "imm16", Action: 0x0}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x1}, {Type: "imm8", Action: 0x0}, }, + EncodingType: 0x2, }, { Operands: []Operand{ + {Type: "r16", Action: 0x1}, {Type: "m16", Action: 0x1}, - {Type: "imm16", Action: 0x0}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x1}, {Type: "r16", Action: 0x1}, }, + EncodingType: 0x2, + CancellingInputs: true, }, }, }, @@ -3222,6 +3589,7 @@ var Instructions = []Instruction{ {Register: "rcx", Action: 0x1}, {Register: "rdx", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -3239,6 +3607,7 @@ var Instructions = []Instruction{ {Register: "ecx", Action: 0x1}, {Register: "edx", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -3249,14 +3618,16 @@ var Instructions = []Instruction{ { Operands: []Operand{ {Type: "r8", Action: 0x1}, - {Type: "r8", Action: 0x3}, + {Type: "m8", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r8", Action: 0x1}, - {Type: "m8", Action: 0x3}, + {Type: "r8", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -3267,14 +3638,16 @@ var Instructions = []Instruction{ { Operands: []Operand{ {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x3}, + {Type: "m32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r32", Action: 0x1}, - {Type: "m32", Action: 0x3}, + {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -3285,14 +3658,16 @@ var Instructions = []Instruction{ { Operands: []Operand{ {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x3}, + {Type: "m64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r64", Action: 0x1}, - {Type: "m64", Action: 0x3}, + {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -3303,14 +3678,16 @@ var Instructions = []Instruction{ { Operands: []Operand{ {Type: "r16", Action: 0x1}, - {Type: "r16", Action: 0x3}, + {Type: "m16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r16", Action: 0x1}, - {Type: "m16", Action: 0x3}, + {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -3321,16 +3698,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, }, + EncodingType: 0x2, }, }, }, @@ -3341,16 +3720,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, }, + EncodingType: 0x2, }, }, }, @@ -3367,6 +3748,7 @@ var Instructions = []Instruction{ {Register: "ecx", Action: 0x3}, {Register: "edx", Action: 0x2}, }, + EncodingType: 0x1, }, }, }, @@ -3380,6 +3762,7 @@ var Instructions = []Instruction{ {Register: "rax", Action: 0x1}, {Register: "rdx", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, @@ -3390,30 +3773,34 @@ var Instructions = []Instruction{ { ISA: []string{"SSE4.2"}, Operands: []Operand{ - {Type: "r8", Action: 0x1}, + {Type: "m8", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE4.2"}, Operands: []Operand{ {Type: "m8", Action: 0x1}, - {Type: "r32", Action: 0x3}, + {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE4.2"}, Operands: []Operand{ {Type: "r8", Action: 0x1}, - {Type: "r64", Action: 0x3}, + {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE4.2"}, Operands: []Operand{ - {Type: "m8", Action: 0x1}, + {Type: "r8", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -3424,16 +3811,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE4.2"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE4.2"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -3444,16 +3833,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE4.2"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE4.2"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -3464,16 +3855,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE4.2"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE4.2"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -3484,16 +3877,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, @@ -3504,16 +3899,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, @@ -3524,16 +3921,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, @@ -3544,16 +3943,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, @@ -3564,16 +3965,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, @@ -3584,16 +3987,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, @@ -3604,30 +4009,34 @@ var Instructions = []Instruction{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ {Type: "m64", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, @@ -3638,16 +4047,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -3658,16 +4069,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -3678,16 +4091,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -3698,16 +4113,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -3718,16 +4135,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -3738,16 +4157,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -3758,30 +4179,34 @@ var Instructions = []Instruction{ { ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE"}, Operands: []Operand{ {Type: "m32", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, @@ -3792,16 +4217,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, @@ -3812,16 +4239,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, @@ -3832,16 +4261,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, @@ -3852,16 +4283,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, @@ -3872,30 +4305,34 @@ var Instructions = []Instruction{ { ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE"}, Operands: []Operand{ {Type: "m32", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, @@ -3909,6 +4346,7 @@ var Instructions = []Instruction{ {Register: "ax", Action: 0x1}, {Register: "dx", Action: 0x2}, }, + EncodingType: 0x1, }, }, }, @@ -3922,6 +4360,7 @@ var Instructions = []Instruction{ {Register: "ax", Action: 0x1}, {Register: "eax", Action: 0x2}, }, + EncodingType: 0x1, }, }, }, @@ -3931,13 +4370,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "r8", Action: 0x3}, + {Type: "m8", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m8", Action: 0x3}, + {Type: "r8", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -3947,13 +4388,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "r32", Action: 0x3}, + {Type: "m32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m32", Action: 0x3}, + {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -3963,13 +4406,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "r64", Action: 0x3}, + {Type: "m64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m64", Action: 0x3}, + {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -3979,13 +4424,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "r16", Action: 0x3}, + {Type: "m16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m16", Action: 0x3}, + {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -3995,19 +4442,21 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "r8", Action: 0x1}, + {Type: "m8", Action: 0x1}, }, ImplicitOperands: []ImplicitOperand{ {Register: "ax", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m8", Action: 0x1}, + {Type: "r8", Action: 0x1}, }, ImplicitOperands: []ImplicitOperand{ {Register: "ax", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -4017,21 +4466,23 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, }, ImplicitOperands: []ImplicitOperand{ {Register: "eax", Action: 0x3}, {Register: "edx", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, }, ImplicitOperands: []ImplicitOperand{ {Register: "eax", Action: 0x3}, {Register: "edx", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -4042,16 +4493,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -4062,16 +4515,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -4081,21 +4536,23 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, }, ImplicitOperands: []ImplicitOperand{ {Register: "rax", Action: 0x3}, {Register: "rdx", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, }, ImplicitOperands: []ImplicitOperand{ {Register: "rax", Action: 0x3}, {Register: "rdx", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -4106,16 +4563,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -4126,16 +4585,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -4145,21 +4606,23 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x1}, }, ImplicitOperands: []ImplicitOperand{ {Register: "ax", Action: 0x3}, {Register: "dx", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x1}, }, ImplicitOperands: []ImplicitOperand{ {Register: "ax", Action: 0x3}, {Register: "dx", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -4171,17 +4634,19 @@ var Instructions = []Instruction{ ISA: []string{"SSE4.1"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE4.1"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -4193,17 +4658,19 @@ var Instructions = []Instruction{ ISA: []string{"SSE4.1"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE4.1"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -4216,16 +4683,18 @@ var Instructions = []Instruction{ Operands: []Operand{ {Type: "imm2u", Action: 0x0}, {Type: "xmm", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "m32", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE4.1"}, Operands: []Operand{ {Type: "imm2u", Action: 0x0}, {Type: "xmm", Action: 0x1}, - {Type: "m32", Action: 0x2}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, @@ -4236,16 +4705,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE3"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE3"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -4256,16 +4727,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE3"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE3"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -4276,16 +4749,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE3"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE3"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -4296,16 +4771,18 @@ var Instructions = []Instruction{ { ISA: []string{"SSE3"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE3"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -4315,19 +4792,21 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "r8", Action: 0x1}, + {Type: "m8", Action: 0x1}, }, ImplicitOperands: []ImplicitOperand{ {Register: "ax", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m8", Action: 0x1}, + {Type: "r8", Action: 0x1}, }, ImplicitOperands: []ImplicitOperand{ {Register: "ax", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -4337,21 +4816,23 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, }, ImplicitOperands: []ImplicitOperand{ {Register: "eax", Action: 0x3}, {Register: "edx", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, }, ImplicitOperands: []ImplicitOperand{ {Register: "eax", Action: 0x3}, {Register: "edx", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -4361,21 +4842,23 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, }, ImplicitOperands: []ImplicitOperand{ {Register: "rax", Action: 0x3}, {Register: "rdx", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, }, ImplicitOperands: []ImplicitOperand{ {Register: "rax", Action: 0x3}, {Register: "rdx", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -4385,21 +4868,23 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x1}, }, ImplicitOperands: []ImplicitOperand{ {Register: "ax", Action: 0x3}, {Register: "dx", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x1}, }, ImplicitOperands: []ImplicitOperand{ {Register: "ax", Action: 0x3}, {Register: "dx", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -4409,10 +4894,11 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r32", Action: 0x1}, + {Type: "imm32", Action: 0x0}, + {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ @@ -4420,6 +4906,7 @@ var Instructions = []Instruction{ {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ @@ -4427,13 +4914,15 @@ var Instructions = []Instruction{ {Type: "m32", Action: 0x1}, {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "m32", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, @@ -4443,10 +4932,11 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r64", Action: 0x1}, + {Type: "imm32", Action: 0x0}, + {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ @@ -4454,6 +4944,7 @@ var Instructions = []Instruction{ {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ @@ -4461,13 +4952,15 @@ var Instructions = []Instruction{ {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "m64", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, @@ -4477,10 +4970,11 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r16", Action: 0x1}, + {Type: "imm16", Action: 0x0}, + {Type: "m16", Action: 0x1}, {Type: "r16", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ @@ -4488,6 +4982,7 @@ var Instructions = []Instruction{ {Type: "r16", Action: 0x1}, {Type: "r16", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ @@ -4495,13 +4990,15 @@ var Instructions = []Instruction{ {Type: "m16", Action: 0x1}, {Type: "r16", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm16", Action: 0x0}, - {Type: "m16", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "r16", Action: 0x1}, {Type: "r16", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, @@ -4511,21 +5008,23 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "r8", Action: 0x1}, + {Type: "m8", Action: 0x1}, }, ImplicitOperands: []ImplicitOperand{ {Register: "ax", Action: 0x2}, {Register: "al", Action: 0x1}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m8", Action: 0x1}, + {Type: "r8", Action: 0x1}, }, ImplicitOperands: []ImplicitOperand{ {Register: "ax", Action: 0x2}, {Register: "al", Action: 0x1}, }, + EncodingType: 0x2, }, }, }, @@ -4535,12 +5034,10 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "r32", Action: 0x1}, - }, - ImplicitOperands: []ImplicitOperand{ - {Register: "eax", Action: 0x3}, - {Register: "edx", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ @@ -4550,18 +5047,24 @@ var Instructions = []Instruction{ {Register: "eax", Action: 0x3}, {Register: "edx", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "r32", Action: 0x3}, + {Type: "r32", Action: 0x1}, + }, + ImplicitOperands: []ImplicitOperand{ + {Register: "eax", Action: 0x3}, + {Register: "edx", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, @@ -4571,12 +5074,10 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "r64", Action: 0x1}, - }, - ImplicitOperands: []ImplicitOperand{ - {Register: "rax", Action: 0x3}, - {Register: "rdx", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ @@ -4586,18 +5087,24 @@ var Instructions = []Instruction{ {Register: "rax", Action: 0x3}, {Register: "rdx", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "r64", Action: 0x3}, + {Type: "r64", Action: 0x1}, + }, + ImplicitOperands: []ImplicitOperand{ + {Register: "rax", Action: 0x3}, + {Register: "rdx", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, @@ -4607,12 +5114,10 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "r16", Action: 0x1}, - }, - ImplicitOperands: []ImplicitOperand{ - {Register: "ax", Action: 0x3}, - {Register: "dx", Action: 0x2}, + {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ @@ -4622,18 +5127,24 @@ var Instructions = []Instruction{ {Register: "ax", Action: 0x3}, {Register: "dx", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r16", Action: 0x1}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m16", Action: 0x1}, - {Type: "r16", Action: 0x3}, + {Type: "r16", Action: 0x1}, }, + ImplicitOperands: []ImplicitOperand{ + {Register: "ax", Action: 0x3}, + {Register: "dx", Action: 0x2}, + }, + EncodingType: 0x2, }, }, }, @@ -4643,13 +5154,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "r8", Action: 0x3}, + {Type: "m8", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m8", Action: 0x3}, + {Type: "r8", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -4659,13 +5172,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "r32", Action: 0x3}, + {Type: "m32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m32", Action: 0x3}, + {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -4675,13 +5190,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "r64", Action: 0x3}, + {Type: "m64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m64", Action: 0x3}, + {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -4691,13 +5208,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "r16", Action: 0x3}, + {Type: "m16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m16", Action: 0x3}, + {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -4709,17 +5228,19 @@ var Instructions = []Instruction{ ISA: []string{"SSE4.1"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE4.1"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -4731,11 +5252,13 @@ var Instructions = []Instruction{ Operands: []Operand{ {Type: "3", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ {Type: "imm8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -4746,13 +5269,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -4763,13 +5288,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -4780,13 +5307,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -4797,13 +5326,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -4814,13 +5345,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -4830,13 +5363,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -4846,13 +5381,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -4867,6 +5404,7 @@ var Instructions = []Instruction{ ImplicitOperands: []ImplicitOperand{ {Register: "ecx", Action: 0x1}, }, + EncodingType: 0x1, }, }, }, @@ -4881,6 +5419,7 @@ var Instructions = []Instruction{ ImplicitOperands: []ImplicitOperand{ {Register: "rcx", Action: 0x1}, }, + EncodingType: 0x1, }, }, }, @@ -4891,13 +5430,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -4907,13 +5448,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -4924,13 +5467,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -4940,13 +5485,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -4956,13 +5503,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -4972,13 +5521,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -4989,13 +5540,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -5006,13 +5559,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -5022,13 +5577,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -5039,13 +5596,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -5055,13 +5614,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -5071,13 +5632,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -5087,13 +5650,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -5103,23 +5668,27 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, }, + EncodingType: 0x2, }, }, }, @@ -5130,13 +5699,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -5147,13 +5718,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -5164,13 +5737,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -5181,13 +5756,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -5198,13 +5775,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -5214,13 +5793,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -5231,13 +5812,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -5248,13 +5831,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -5265,13 +5850,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -5282,13 +5869,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -5299,13 +5888,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -5316,13 +5907,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -5333,13 +5926,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -5350,13 +5945,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -5367,13 +5964,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -5383,13 +5982,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -5399,13 +6000,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -5416,13 +6019,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -5432,13 +6037,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -5449,13 +6056,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -5465,13 +6074,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -5482,13 +6093,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -5498,13 +6111,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -5515,13 +6130,15 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, @@ -5532,1273 +6149,1591 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "rel8", Action: 0x0}, + {Type: "rel32", Action: 0x0}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "rel32", Action: 0x0}, + {Type: "rel8", Action: 0x0}, }, + EncodingType: 0x1, }, }, }, { - Opcode: "LDDQU", - Summary: "Load Unaligned Integer 128 Bits", + Opcode: "KADDB", + Summary: "ADD Two 8-bit Masks", Forms: []Form{ { - ISA: []string{"SSE3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "LDMXCSR", - Summary: "Load MXCSR Register", + Opcode: "KADDD", + Summary: "ADD Two 32-bit Masks", Forms: []Form{ { - ISA: []string{"SSE"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "LEAL", - Summary: "Load Effective Address", + Opcode: "KADDQ", + Summary: "ADD Two 64-bit Masks", Forms: []Form{ { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "m", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "LEAQ", - Summary: "Load Effective Address", + Opcode: "KADDW", + Summary: "ADD Two 16-bit Masks", Forms: []Form{ { + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "LEAW", - Summary: "Load Effective Address", + Opcode: "KANDB", + Summary: "Bitwise Logical AND 8-bit Masks", Forms: []Form{ { + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m", Action: 0x1}, - {Type: "r16", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "LFENCE", - Summary: "Load Fence", + Opcode: "KANDD", + Summary: "Bitwise Logical AND 32-bit Masks", Forms: []Form{ { - ISA: []string{"SSE2"}, - Operands: []Operand{}, + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x3, }, }, }, { - Opcode: "LZCNTL", - Summary: "Count the Number of Leading Zero Bits", + Opcode: "KANDNB", + Summary: "Bitwise Logical AND NOT 8-bit Masks", Forms: []Form{ { - ISA: []string{"LZCNT"}, - Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x2}, - }, - }, - { - ISA: []string{"LZCNT"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "LZCNTQ", - Summary: "Count the Number of Leading Zero Bits", + Opcode: "KANDND", + Summary: "Bitwise Logical AND NOT 32-bit Masks", Forms: []Form{ { - ISA: []string{"LZCNT"}, - Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x2}, - }, - }, - { - ISA: []string{"LZCNT"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "LZCNTW", - Summary: "Count the Number of Leading Zero Bits", + Opcode: "KANDNQ", + Summary: "Bitwise Logical AND NOT 64-bit Masks", Forms: []Form{ { - ISA: []string{"LZCNT"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, - {Type: "r16", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, + }, + }, + { + Opcode: "KANDNW", + Summary: "Bitwise Logical AND NOT 16-bit Masks", + Forms: []Form{ { - ISA: []string{"LZCNT"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, - {Type: "r16", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "MASKMOVDQU", - AliasOf: "MASKMOVOU", - Summary: "Store Selected Bytes of Double Quadword", + Opcode: "KANDQ", + Summary: "Bitwise Logical AND 64-bit Masks", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - }, - ImplicitOperands: []ImplicitOperand{ - {Register: "rdi", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "MASKMOVOU", - Summary: "Store Selected Bytes of Double Quadword", + Opcode: "KANDW", + Summary: "Bitwise Logical AND 16-bit Masks", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - }, - ImplicitOperands: []ImplicitOperand{ - {Register: "rdi", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "MAXPD", - Summary: "Return Maximum Packed Double-Precision Floating-Point Values", + Opcode: "KMOVB", + Summary: "Move 8-bit Mask", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "m8", Action: 0x2}, }, + EncodingType: 0x3, }, - }, - }, - { - Opcode: "MAXPS", - Summary: "Return Maximum Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"SSE"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"SSE"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m8", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "MAXSD", - Summary: "Return Maximum Scalar Double-Precision Floating-Point Value", + Opcode: "KMOVD", + Summary: "Move 32-bit Mask", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "m32", Action: 0x2}, }, + EncodingType: 0x3, }, - }, - }, - { - Opcode: "MAXSS", - Summary: "Return Maximum Scalar Single-Precision Floating-Point Value", - Forms: []Form{ { - ISA: []string{"SSE"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"SSE"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, - }, - }, - { - Opcode: "MFENCE", - Summary: "Memory Fence", - Forms: []Form{ { - ISA: []string{"SSE2"}, - Operands: []Operand{}, + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x3, }, }, }, { - Opcode: "MINPD", - Summary: "Return Minimum Packed Double-Precision Floating-Point Values", + Opcode: "KMOVQ", + Summary: "Move 64-bit Mask", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x2}, }, + EncodingType: 0x3, }, - }, - }, - { - Opcode: "MINPS", - Summary: "Return Minimum Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"SSE"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"SSE"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "MINSD", - Summary: "Return Minimum Scalar Double-Precision Floating-Point Value", + Opcode: "KMOVW", + Summary: "Move 16-bit Mask", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "m16", Action: 0x2}, }, + EncodingType: 0x3, }, - }, - }, - { - Opcode: "MINSS", - Summary: "Return Minimum Scalar Single-Precision Floating-Point Value", - Forms: []Form{ { - ISA: []string{"SSE"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"SSE"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m16", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "MONITOR", - Summary: "Monitor a Linear Address Range", + Opcode: "KNOTB", + Summary: "NOT 8-bit Mask Register", Forms: []Form{ { - ISA: []string{"MONITOR"}, - Operands: []Operand{}, - ImplicitOperands: []ImplicitOperand{ - {Register: "rax", Action: 0x1}, - {Register: "ecx", Action: 0x1}, - {Register: "edx", Action: 0x1}, + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "MOVAPD", - Summary: "Move Aligned Packed Double-Precision Floating-Point Values", + Opcode: "KNOTD", + Summary: "NOT 32-bit Mask Register", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, + }, + }, + { + Opcode: "KNOTQ", + Summary: "NOT 64-bit Mask Register", + Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, + }, + }, + { + Opcode: "KNOTW", + Summary: "NOT 16-bit Mask Register", + Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "m128", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "MOVAPS", - Summary: "Move Aligned Packed Single-Precision Floating-Point Values", + Opcode: "KORB", + Summary: "Bitwise Logical OR 8-bit Masks", Forms: []Form{ { - ISA: []string{"SSE"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, + }, + }, + { + Opcode: "KORD", + Summary: "Bitwise Logical OR 32-bit Masks", + Forms: []Form{ { - ISA: []string{"SSE"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, + }, + }, + { + Opcode: "KORQ", + Summary: "Bitwise Logical OR 64-bit Masks", + Forms: []Form{ { - ISA: []string{"SSE"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "m128", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "MOVB", - Summary: "Move", + Opcode: "KORTESTB", + Summary: "OR 8-bit Masks and Set Flags", Forms: []Form{ { + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r8", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, }, + EncodingType: 0x3, }, + }, + }, + { + Opcode: "KORTESTD", + Summary: "OR 32-bit Masks and Set Flags", + Forms: []Form{ { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "r8", Action: 0x1}, - {Type: "r8", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, }, + EncodingType: 0x3, }, + }, + }, + { + Opcode: "KORTESTQ", + Summary: "OR 64-bit Masks and Set Flags", + Forms: []Form{ { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "m8", Action: 0x1}, - {Type: "r8", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, }, + EncodingType: 0x3, }, + }, + }, + { + Opcode: "KORTESTW", + Summary: "OR 16-bit Masks and Set Flags", + Forms: []Form{ { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m8", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, }, + EncodingType: 0x3, }, + }, + }, + { + Opcode: "KORW", + Summary: "Bitwise Logical OR 16-bit Masks", + Forms: []Form{ { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "r8", Action: 0x1}, - {Type: "m8", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "MOVBELL", - Summary: "Move Data After Swapping Bytes", + Opcode: "KSHIFTLB", + Summary: "Shift Left 8-bit Masks", Forms: []Form{ { - ISA: []string{"MOVBE"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, + }, + }, + { + Opcode: "KSHIFTLD", + Summary: "Shift Left 32-bit Masks", + Forms: []Form{ { - ISA: []string{"MOVBE"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "m32", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "MOVBEQQ", - Summary: "Move Data After Swapping Bytes", + Opcode: "KSHIFTLQ", + Summary: "Shift Left 64-bit Masks", Forms: []Form{ { - ISA: []string{"MOVBE"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, + }, + }, + { + Opcode: "KSHIFTLW", + Summary: "Shift Left 16-bit Masks", + Forms: []Form{ { - ISA: []string{"MOVBE"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "m64", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "MOVBEWW", - Summary: "Move Data After Swapping Bytes", + Opcode: "KSHIFTRB", + Summary: "Shift Right 8-bit Masks", Forms: []Form{ { - ISA: []string{"MOVBE"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, - {Type: "r16", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, + }, + }, + { + Opcode: "KSHIFTRD", + Summary: "Shift Right 32-bit Masks", + Forms: []Form{ { - ISA: []string{"MOVBE"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, - {Type: "m16", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "MOVBLSX", - Summary: "Move with Sign-Extension", + Opcode: "KSHIFTRQ", + Summary: "Shift Right 64-bit Masks", Forms: []Form{ { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "r8", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, + }, + }, + { + Opcode: "KSHIFTRW", + Summary: "Shift Right 16-bit Masks", + Forms: []Form{ { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m8", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "MOVBLZX", - Summary: "Move with Zero-Extend", + Opcode: "KTESTB", + Summary: "Bit Test 8-bit Masks and Set Flags", Forms: []Form{ { + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "r8", Action: 0x1}, - {Type: "r32", Action: 0x2}, - }, - }, - { - Operands: []Operand{ - {Type: "m8", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "MOVBQSX", - Summary: "Move with Sign-Extension", + Opcode: "KTESTD", + Summary: "Bit Test 32-bit Masks and Set Flags", Forms: []Form{ { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "r8", Action: 0x1}, - {Type: "r64", Action: 0x2}, - }, - }, - { - Operands: []Operand{ - {Type: "m8", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "MOVBQZX", - Summary: "Move with Zero-Extend", + Opcode: "KTESTQ", + Summary: "Bit Test 64-bit Masks and Set Flags", Forms: []Form{ { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "r8", Action: 0x1}, - {Type: "r64", Action: 0x2}, - }, - }, - { - Operands: []Operand{ - {Type: "m8", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "MOVBWSX", - Summary: "Move with Sign-Extension", + Opcode: "KTESTW", + Summary: "Bit Test 16-bit Masks and Set Flags", Forms: []Form{ { + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "r8", Action: 0x1}, - {Type: "r16", Action: 0x2}, - }, - }, - { - Operands: []Operand{ - {Type: "m8", Action: 0x1}, - {Type: "r16", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "MOVBWZX", - Summary: "Move with Zero-Extend", + Opcode: "KUNPCKBW", + Summary: "Unpack and Interleave 8-bit Masks", Forms: []Form{ { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "r8", Action: 0x1}, - {Type: "r16", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, + }, + }, + { + Opcode: "KUNPCKDQ", + Summary: "Unpack and Interleave 32-bit Masks", + Forms: []Form{ { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "m8", Action: 0x1}, - {Type: "r16", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "MOVD", - AliasOf: "MOVQ", - Summary: "Move", + Opcode: "KUNPCKWD", + Summary: "Unpack and Interleave 16-bit Masks", Forms: []Form{ { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "r64", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, + }, + }, + { + Opcode: "KXNORB", + Summary: "Bitwise Logical XNOR 8-bit Masks", + Forms: []Form{ { + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "imm64", Action: 0x0}, - {Type: "r64", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, + }, + }, + { + Opcode: "KXNORD", + Summary: "Bitwise Logical XNOR 32-bit Masks", + Forms: []Form{ { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, + }, + }, + { + Opcode: "KXNORQ", + Summary: "Bitwise Logical XNOR 64-bit Masks", + Forms: []Form{ { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, + }, + }, + { + Opcode: "KXNORW", + Summary: "Bitwise Logical XNOR 16-bit Masks", + Forms: []Form{ { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "m64", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, + }, + }, + { + Opcode: "KXORB", + Summary: "Bitwise Logical XOR 8-bit Masks", + Forms: []Form{ { + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "m64", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, + }, + }, + { + Opcode: "KXORD", + Summary: "Bitwise Logical XOR 32-bit Masks", + Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, + }, + }, + { + Opcode: "KXORQ", + Summary: "Bitwise Logical XOR 64-bit Masks", + Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, + }, + }, + { + Opcode: "KXORW", + Summary: "Bitwise Logical XOR 16-bit Masks", + Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x3, }, + }, + }, + { + Opcode: "LDDQU", + Summary: "Load Unaligned Integer 128 Bits", + Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"SSE3"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "LDMXCSR", + Summary: "Load MXCSR Register", + Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "m64", Action: 0x2}, + {Type: "m32", Action: 0x1}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "LEAL", + Summary: "Load Effective Address", + Forms: []Form{ { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m", Action: 0x1}, {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "LEAQ", + Summary: "Load Effective Address", + Forms: []Form{ { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m", Action: 0x1}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "LEAW", + Summary: "Load Effective Address", + Forms: []Form{ { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m", Action: 0x1}, + {Type: "r16", Action: 0x2}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "LFENCE", + Summary: "Load Fence", + Forms: []Form{ { - ISA: []string{"SSE2"}, - Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "m32", Action: 0x2}, - }, + ISA: []string{"SSE2"}, + Operands: []Operand{}, + EncodingType: 0x1, }, }, }, { - Opcode: "MOVDDUP", - Summary: "Move One Double-FP and Duplicate", + Opcode: "LZCNTL", + Summary: "Count the Number of Leading Zero Bits", Forms: []Form{ { - ISA: []string{"SSE3"}, + ISA: []string{"LZCNT"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE3"}, + ISA: []string{"LZCNT"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "r32", Action: 0x1}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "MOVDQ2Q", - AliasOf: "MOVQ", - Summary: "Move", + Opcode: "LZCNTQ", + Summary: "Count the Number of Leading Zero Bits", Forms: []Form{ { + ISA: []string{"LZCNT"}, Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "r64", Action: 0x2}, - }, - }, - { - Operands: []Operand{ - {Type: "imm64", Action: 0x0}, + {Type: "m64", Action: 0x1}, {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, { + ISA: []string{"LZCNT"}, Operands: []Operand{ {Type: "r64", Action: 0x1}, {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "LZCNTW", + Summary: "Count the Number of Leading Zero Bits", + Forms: []Form{ { + ISA: []string{"LZCNT"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x2}, }, + EncodingType: 0x2, }, { + ISA: []string{"LZCNT"}, Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "m64", Action: 0x2}, + {Type: "r16", Action: 0x1}, + {Type: "r16", Action: 0x2}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "MASKMOVDQU", + AliasOf: "MASKMOVOU", + Summary: "Store Selected Bytes of Double Quadword", + Forms: []Form{ { + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "m64", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + }, + ImplicitOperands: []ImplicitOperand{ + {Register: "rdi", Action: 0x1}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "MASKMOVOU", + Summary: "Store Selected Bytes of Double Quadword", + Forms: []Form{ { ISA: []string{"SSE2"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + }, + ImplicitOperands: []ImplicitOperand{ + {Register: "rdi", Action: 0x1}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "MAXPD", + Summary: "Return Maximum Packed Double-Precision Floating-Point Values", + Forms: []Form{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "MAXPS", + Summary: "Return Maximum Packed Single-Precision Floating-Point Values", + Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, + ISA: []string{"SSE"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "m64", Action: 0x2}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "MAXSD", + Summary: "Return Maximum Scalar Double-Precision Floating-Point Value", + Forms: []Form{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "MAXSS", + Summary: "Return Maximum Scalar Single-Precision Floating-Point Value", + Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"SSE"}, Operands: []Operand{ {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, + ISA: []string{"SSE"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "m32", Action: 0x2}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "MOVHLPS", - Summary: "Move Packed Single-Precision Floating-Point Values High to Low", + Opcode: "MFENCE", + Summary: "Memory Fence", Forms: []Form{ { - ISA: []string{"SSE"}, - Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, - }, + ISA: []string{"SSE2"}, + Operands: []Operand{}, + EncodingType: 0x1, }, }, }, { - Opcode: "MOVHPD", - Summary: "Move High Packed Double-Precision Floating-Point Value", + Opcode: "MINPD", + Summary: "Return Minimum Packed Double-Precision Floating-Point Values", Forms: []Form{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "m64", Action: 0x2}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "MOVHPS", - Summary: "Move High Packed Single-Precision Floating-Point Values", + Opcode: "MINPS", + Summary: "Return Minimum Packed Single-Precision Floating-Point Values", Forms: []Form{ { ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "m64", Action: 0x2}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "MOVL", - Summary: "Move", + Opcode: "MINSD", + Summary: "Return Minimum Scalar Double-Precision Floating-Point Value", Forms: []Form{ { + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "r32", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "MINSS", + Summary: "Return Minimum Scalar Single-Precision Floating-Point Value", + Forms: []Form{ { + ISA: []string{"SSE"}, Operands: []Operand{ {Type: "m32", Action: 0x1}, - {Type: "r32", Action: 0x2}, - }, - }, - { - Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "m32", Action: 0x2}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { + ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "m32", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "MOVLHPS", - Summary: "Move Packed Single-Precision Floating-Point Values Low to High", + Opcode: "MONITOR", + Summary: "Monitor a Linear Address Range", Forms: []Form{ { - ISA: []string{"SSE"}, - Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + ISA: []string{"MONITOR"}, + Operands: []Operand{}, + ImplicitOperands: []ImplicitOperand{ + {Register: "rax", Action: 0x1}, + {Register: "ecx", Action: 0x1}, + {Register: "edx", Action: 0x1}, }, + EncodingType: 0x1, }, }, }, { - Opcode: "MOVLPD", - Summary: "Move Low Packed Double-Precision Floating-Point Value", + Opcode: "MOVAPD", + Summary: "Move Aligned Packed Double-Precision Floating-Point Values", Forms: []Form{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "m64", Action: 0x2}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "MOVLPS", - Summary: "Move Low Packed Single-Precision Floating-Point Values", + Opcode: "MOVAPS", + Summary: "Move Aligned Packed Single-Precision Floating-Point Values", Forms: []Form{ { ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "m64", Action: 0x2}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "MOVLQSX", - Summary: "Move Doubleword to Quadword with Sign-Extension", + Opcode: "MOVB", + Summary: "Move", Forms: []Form{ { Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m8", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "r8", Action: 0x2}, }, + EncodingType: 0x2, }, - }, - }, - { - Opcode: "MOVLQZX", - Summary: "Move with Zero-Extend", - Forms: []Form{ { Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "m8", Action: 0x1}, + {Type: "r8", Action: 0x2}, }, + EncodingType: 0x2, }, - }, - }, - { - Opcode: "MOVMSKPD", - Summary: "Extract Packed Double-Precision Floating-Point Sign Mask", - Forms: []Form{ { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "r8", Action: 0x1}, + {Type: "m8", Action: 0x2}, }, + EncodingType: 0x2, }, - }, - }, - { - Opcode: "MOVMSKPS", - Summary: "Extract Packed Single-Precision Floating-Point Sign Mask", - Forms: []Form{ { - ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "r8", Action: 0x1}, + {Type: "r8", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "MOVNTDQ", - AliasOf: "MOVNTO", - Summary: "Store Double Quadword Using Non-Temporal Hint", + Opcode: "MOVBELL", + Summary: "Move Data After Swapping Bytes", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"MOVBE"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "m128", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, - }, - }, - { - Opcode: "MOVNTDQA", - Summary: "Load Double Quadword Non-Temporal Aligned Hint", - Forms: []Form{ { - ISA: []string{"SSE4.1"}, + ISA: []string{"MOVBE"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "MOVNTIL", - Summary: "Store Doubleword Using Non-Temporal Hint", + Opcode: "MOVBEQQ", + Summary: "Move Data After Swapping Bytes", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"MOVBE"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "m32", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, - }, - }, - { - Opcode: "MOVNTIQ", - Summary: "Store Doubleword Using Non-Temporal Hint", - Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"MOVBE"}, Operands: []Operand{ {Type: "r64", Action: 0x1}, {Type: "m64", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "MOVNTO", - Summary: "Store Double Quadword Using Non-Temporal Hint", + Opcode: "MOVBEWW", + Summary: "Move Data After Swapping Bytes", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"MOVBE"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "m128", Action: 0x2}, + {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x2}, }, + EncodingType: 0x2, }, - }, - }, - { - Opcode: "MOVNTPD", - Summary: "Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint", - Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"MOVBE"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "m128", Action: 0x2}, + {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "MOVNTPS", - Summary: "Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint", + Opcode: "MOVBLSX", + Summary: "Move with Sign-Extension", Forms: []Form{ { - ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "m128", Action: 0x2}, + {Type: "m8", Action: 0x1}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, - }, - }, - { - Opcode: "MOVO", - Summary: "Move Aligned Double Quadword", - Forms: []Form{ { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "r8", Action: 0x1}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "MOVBLZX", + Summary: "Move with Zero-Extend", + Forms: []Form{ { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m8", Action: 0x1}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "m128", Action: 0x2}, + {Type: "r8", Action: 0x1}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "MOVOA", - AliasOf: "MOVO", - Summary: "Move Aligned Double Quadword", + Opcode: "MOVBQSX", + Summary: "Move with Sign-Extension", Forms: []Form{ { - ISA: []string{"SSE2"}, - Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, - }, - }, - { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m8", Action: 0x1}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "m128", Action: 0x2}, + {Type: "r8", Action: 0x1}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "MOVOU", - Summary: "Move Unaligned Double Quadword", + Opcode: "MOVBQZX", + Summary: "Move with Zero-Extend", Forms: []Form{ { - ISA: []string{"SSE2"}, - Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, - }, - }, - { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m8", Action: 0x1}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "m128", Action: 0x2}, + {Type: "r8", Action: 0x1}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "MOVQ", - Summary: "Move", + Opcode: "MOVBWSX", + Summary: "Move with Sign-Extension", Forms: []Form{ { Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "r64", Action: 0x2}, + {Type: "m8", Action: 0x1}, + {Type: "r16", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm64", Action: 0x0}, - {Type: "r64", Action: 0x2}, + {Type: "r8", Action: 0x1}, + {Type: "r16", Action: 0x2}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "MOVBWZX", + Summary: "Move with Zero-Extend", + Forms: []Form{ { Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "m8", Action: 0x1}, + {Type: "r16", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "r8", Action: 0x1}, + {Type: "r16", Action: 0x2}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "MOVD", + AliasOf: "MOVQ", + Summary: "Move", + Forms: []Form{ { + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "m64", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "m64", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "r32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, @@ -6806,3366 +7741,3739 @@ var Instructions = []Instruction{ {Type: "r64", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "m64", Action: 0x2}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm32", Action: 0x0}, + {Type: "m64", Action: 0x2}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "m32", Action: 0x2}, + {Type: "imm32", Action: 0x0}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, - }, - }, - { - Opcode: "MOVSD", - Summary: "Move Scalar Double-Precision Floating-Point Value", - Forms: []Form{ { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "imm64", Action: 0x0}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, Operands: []Operand{ {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "r64", Action: 0x1}, {Type: "m64", Action: 0x2}, }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x2, }, }, }, { - Opcode: "MOVSHDUP", - Summary: "Move Packed Single-FP High and Duplicate", + Opcode: "MOVDDUP", + Summary: "Move One Double-FP and Duplicate", Forms: []Form{ { ISA: []string{"SSE3"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE3"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "MOVSLDUP", - Summary: "Move Packed Single-FP Low and Duplicate", + Opcode: "MOVDQ2Q", + AliasOf: "MOVQ", + Summary: "Move", Forms: []Form{ { - ISA: []string{"SSE3"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE3"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, - }, - }, - { - Opcode: "MOVSS", - Summary: "Move Scalar Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"SSE"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "r32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "r64", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE"}, + ISA: []string{"SSE2"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "m32", Action: 0x2}, }, + EncodingType: 0x2, }, - }, - }, - { - Opcode: "MOVUPD", - Summary: "Move Unaligned Packed Double-Precision Floating-Point Values", - Forms: []Form{ { ISA: []string{"SSE2"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m64", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "m128", Action: 0x2}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, - }, - }, - { - Opcode: "MOVUPS", - Summary: "Move Unaligned Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"SSE"}, + ISA: []string{"SSE2"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm32", Action: 0x0}, + {Type: "m64", Action: 0x2}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "m128", Action: 0x2}, + {Type: "imm32", Action: 0x0}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, - }, - }, - { - Opcode: "MOVW", - Summary: "Move", - Forms: []Form{ { Operands: []Operand{ - {Type: "imm16", Action: 0x0}, - {Type: "r16", Action: 0x2}, + {Type: "imm64", Action: 0x0}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r16", Action: 0x1}, - {Type: "r16", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m16", Action: 0x1}, - {Type: "r16", Action: 0x2}, + {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm16", Action: 0x0}, - {Type: "m16", Action: 0x2}, + {Type: "r64", Action: 0x1}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "MOVHLPS", + Summary: "Move Packed Single-Precision Floating-Point Values High to Low", + Forms: []Form{ { + ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, - {Type: "m16", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "MOVWLSX", - Summary: "Move with Sign-Extension", + Opcode: "MOVHPD", + Summary: "Move High Packed Double-Precision Floating-Point Value", Forms: []Form{ { + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "MOVWLZX", - Summary: "Move with Zero-Extend", + Opcode: "MOVHPS", + Summary: "Move High Packed Single-Precision Floating-Point Values", Forms: []Form{ { + ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { + ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "MOVWQSX", - Summary: "Move with Sign-Extension", + Opcode: "MOVL", + Summary: "Move", Forms: []Form{ { Operands: []Operand{ - {Type: "r16", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "imm32", Action: 0x0}, + {Type: "m32", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m16", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "imm32", Action: 0x0}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, - }, - }, - { - Opcode: "MOVWQZX", - Summary: "Move with Zero-Extend", - Forms: []Form{ { Operands: []Operand{ - {Type: "r16", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m16", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x2}, }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x2, }, }, }, { - Opcode: "MPSADBW", - Summary: "Compute Multiple Packed Sums of Absolute Difference", + Opcode: "MOVLHPS", + Summary: "Move Packed Single-Precision Floating-Point Values Low to High", Forms: []Form{ { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "MOVLPD", + Summary: "Move Low Packed Double-Precision Floating-Point Value", + Forms: []Form{ { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x2, }, }, }, { - Opcode: "MULB", - Summary: "Unsigned Multiply", + Opcode: "MOVLPS", + Summary: "Move Low Packed Single-Precision Floating-Point Values", Forms: []Form{ { + ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "r8", Action: 0x1}, - }, - ImplicitOperands: []ImplicitOperand{ - {Register: "ax", Action: 0x2}, - {Register: "al", Action: 0x1}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { + ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "m8", Action: 0x1}, - }, - ImplicitOperands: []ImplicitOperand{ - {Register: "ax", Action: 0x2}, - {Register: "al", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "MULL", - Summary: "Unsigned Multiply", + Opcode: "MOVLQSX", + Summary: "Move Doubleword to Quadword with Sign-Extension", Forms: []Form{ { Operands: []Operand{ - {Type: "r32", Action: 0x1}, - }, - ImplicitOperands: []ImplicitOperand{ - {Register: "eax", Action: 0x3}, - {Register: "edx", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m32", Action: 0x1}, - }, - ImplicitOperands: []ImplicitOperand{ - {Register: "eax", Action: 0x3}, - {Register: "edx", Action: 0x2}, + {Type: "r32", Action: 0x1}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "MULPD", - Summary: "Multiply Packed Double-Precision Floating-Point Values", + Opcode: "MOVLQZX", + Summary: "Move with Zero-Extend", Forms: []Form{ { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x0, }, + }, + }, + { + Opcode: "MOVMSKPD", + Summary: "Extract Packed Double-Precision Floating-Point Sign Mask", + Forms: []Form{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "MULPS", - Summary: "Multiply Packed Single-Precision Floating-Point Values", + Opcode: "MOVMSKPS", + Summary: "Extract Packed Single-Precision Floating-Point Sign Mask", Forms: []Form{ { ISA: []string{"SSE"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "MOVNTDQ", + AliasOf: "MOVNTO", + Summary: "Store Double Quadword Using Non-Temporal Hint", + Forms: []Form{ { - ISA: []string{"SSE"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "MULQ", - Summary: "Unsigned Multiply", + Opcode: "MOVNTDQA", + Summary: "Load Double Quadword Non-Temporal Aligned Hint", Forms: []Form{ { + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, - }, - ImplicitOperands: []ImplicitOperand{ - {Register: "rax", Action: 0x3}, - {Register: "rdx", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "MOVNTIL", + Summary: "Store Doubleword Using Non-Temporal Hint", + Forms: []Form{ { + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - }, - ImplicitOperands: []ImplicitOperand{ - {Register: "rax", Action: 0x3}, - {Register: "rdx", Action: 0x2}, + {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "MULSD", - Summary: "Multiply Scalar Double-Precision Floating-Point Values", + Opcode: "MOVNTIQ", + Summary: "Store Doubleword Using Non-Temporal Hint", Forms: []Form{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x2}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "MOVNTO", + Summary: "Store Double Quadword Using Non-Temporal Hint", + Forms: []Form{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "MULSS", - Summary: "Multiply Scalar Single-Precision Floating-Point Values", + Opcode: "MOVNTPD", + Summary: "Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint", Forms: []Form{ { - ISA: []string{"SSE"}, + ISA: []string{"SSE2"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m128", Action: 0x2}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "MOVNTPS", + Summary: "Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint", + Forms: []Form{ { ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "MULW", - Summary: "Unsigned Multiply", + Opcode: "MOVO", + Summary: "Move Aligned Double Quadword", Forms: []Form{ { + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, - }, - ImplicitOperands: []ImplicitOperand{ - {Register: "ax", Action: 0x3}, - {Register: "dx", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, - }, - ImplicitOperands: []ImplicitOperand{ - {Register: "ax", Action: 0x3}, - {Register: "dx", Action: 0x2}, - }, - }, - }, - }, - { - Opcode: "MULXL", - Summary: "Unsigned Multiply Without Affecting Flags", - Forms: []Form{ - { - ISA: []string{"BMI2"}, - Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x2}, - {Type: "r32", Action: 0x2}, - }, - ImplicitOperands: []ImplicitOperand{ - {Register: "edx", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, }, + EncodingType: 0x2, }, { - ISA: []string{"BMI2"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "r32", Action: 0x2}, - {Type: "r32", Action: 0x2}, - }, - ImplicitOperands: []ImplicitOperand{ - {Register: "edx", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "MULXQ", - Summary: "Unsigned Multiply Without Affecting Flags", + Opcode: "MOVOA", + AliasOf: "MOVO", + Summary: "Move Aligned Double Quadword", Forms: []Form{ { - ISA: []string{"BMI2"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x2}, - {Type: "r64", Action: 0x2}, - }, - ImplicitOperands: []ImplicitOperand{ - {Register: "rdx", Action: 0x1}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { - ISA: []string{"BMI2"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "r64", Action: 0x2}, - {Type: "r64", Action: 0x2}, - }, - ImplicitOperands: []ImplicitOperand{ - {Register: "rdx", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, }, + EncodingType: 0x2, }, - }, - }, - { - Opcode: "MWAIT", - Summary: "Monitor Wait", - Forms: []Form{ { - ISA: []string{"MONITOR"}, - Operands: []Operand{}, - ImplicitOperands: []ImplicitOperand{ - {Register: "eax", Action: 0x1}, - {Register: "ecx", Action: 0x1}, + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "NEGB", - Summary: "Two's Complement Negation", + Opcode: "MOVOU", + Summary: "Move Unaligned Double Quadword", Forms: []Form{ { + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "r8", Action: 0x3}, - }, - }, - { - Operands: []Operand{ - {Type: "m8", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, - }, - }, - { - Opcode: "NEGL", - Summary: "Two's Complement Negation", - Forms: []Form{ { + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "r32", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, }, + EncodingType: 0x2, }, { + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m32", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "NEGQ", - Summary: "Two's Complement Negation", + Opcode: "MOVQ", + Summary: "Move", Forms: []Form{ { + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "r64", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m64", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, - }, - }, - { - Opcode: "NEGW", - Summary: "Two's Complement Negation", - Forms: []Form{ { + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "r16", Action: 0x3}, + {Type: "r32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m16", Action: 0x3}, + {Type: "r64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, - }, - }, - { - Opcode: "NOP", - Summary: "No Operation", - Forms: []Form{ - { - Operands: []Operand{}, - }, - }, - }, - { - Opcode: "NOTB", - Summary: "One's Complement Negation", - Forms: []Form{ { + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "r8", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x2}, }, + EncodingType: 0x2, }, { + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m8", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x2}, }, + EncodingType: 0x2, }, - }, - }, - { - Opcode: "NOTL", - Summary: "One's Complement Negation", - Forms: []Form{ { + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "r32", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, { + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m32", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, - }, - }, - { - Opcode: "NOTQ", - Summary: "One's Complement Negation", - Forms: []Form{ { + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "r64", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m64", Action: 0x3}, + {Type: "imm32", Action: 0x0}, + {Type: "m64", Action: 0x2}, }, + EncodingType: 0x2, }, - }, - }, - { - Opcode: "NOTW", - Summary: "One's Complement Negation", - Forms: []Form{ { Operands: []Operand{ - {Type: "r16", Action: 0x3}, + {Type: "imm32", Action: 0x0}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m16", Action: 0x3}, + {Type: "imm64", Action: 0x0}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, - }, - }, - { - Opcode: "ORB", - Summary: "Logical Inclusive OR", - Forms: []Form{ { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "al", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r8", Action: 0x3}, + {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r8", Action: 0x1}, - {Type: "r8", Action: 0x3}, + {Type: "r64", Action: 0x1}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "MOVSD", + Summary: "Move Scalar Double-Precision Floating-Point Value", + Forms: []Form{ { + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m8", Action: 0x1}, - {Type: "r8", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m8", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x2}, }, + EncodingType: 0x2, }, { + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "r8", Action: 0x1}, - {Type: "m8", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "ORL", - Summary: "Logical Inclusive OR", + Opcode: "MOVSHDUP", + Summary: "Move Packed Single-FP High and Duplicate", Forms: []Form{ { + ISA: []string{"SSE3"}, Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "eax", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { + ISA: []string{"SSE3"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r32", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "MOVSLDUP", + Summary: "Move Packed Single-FP Low and Duplicate", + Forms: []Form{ { + ISA: []string{"SSE3"}, Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "r32", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { + ISA: []string{"SSE3"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "MOVSS", + Summary: "Move Scalar Single-Precision Floating-Point Values", + Forms: []Form{ { + ISA: []string{"SSE"}, Operands: []Operand{ {Type: "m32", Action: 0x1}, - {Type: "r32", Action: 0x3}, - }, - }, - { - Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m32", Action: 0x3}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { + ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "m32", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x2}, }, + EncodingType: 0x2, }, { + ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "m32", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "ORPD", - Summary: "Bitwise Logical OR of Double-Precision Floating-Point Values", + Opcode: "MOVUPD", + Summary: "Move Unaligned Packed Double-Precision Floating-Point Values", Forms: []Form{ - { - ISA: []string{"SSE2"}, - Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, - }, - }, { ISA: []string{"SSE2"}, Operands: []Operand{ {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, - }, - }, - { - Opcode: "ORPS", - Summary: "Bitwise Logical OR of Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"SSE"}, + ISA: []string{"SSE2"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m128", Action: 0x2}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "ORQ", - Summary: "Logical Inclusive OR", + Opcode: "MOVUPS", + Summary: "Move Unaligned Packed Single-Precision Floating-Point Values", Forms: []Form{ { + ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "rax", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { + ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r64", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, }, + EncodingType: 0x2, }, { + ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "r64", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "MOVW", + Summary: "Move", + Forms: []Form{ { Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x3}, + {Type: "imm16", Action: 0x0}, + {Type: "m16", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "r64", Action: 0x3}, + {Type: "imm16", Action: 0x0}, + {Type: "r16", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m64", Action: 0x3}, + {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "m64", Action: 0x3}, + {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "m64", Action: 0x3}, + {Type: "r16", Action: 0x1}, + {Type: "r16", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "ORW", - Summary: "Logical Inclusive OR", + Opcode: "MOVWLSX", + Summary: "Move with Sign-Extension", Forms: []Form{ { Operands: []Operand{ - {Type: "imm16", Action: 0x0}, - {Type: "ax", Action: 0x3}, + {Type: "m16", Action: 0x1}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r16", Action: 0x3}, + {Type: "r16", Action: 0x1}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "MOVWLZX", + Summary: "Move with Zero-Extend", + Forms: []Form{ { Operands: []Operand{ - {Type: "imm16", Action: 0x0}, - {Type: "r16", Action: 0x3}, + {Type: "m16", Action: 0x1}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r16", Action: 0x1}, - {Type: "r16", Action: 0x3}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "MOVWQSX", + Summary: "Move with Sign-Extension", + Forms: []Form{ { Operands: []Operand{ {Type: "m16", Action: 0x1}, - {Type: "r16", Action: 0x3}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m16", Action: 0x3}, + {Type: "r16", Action: 0x1}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "MOVWQZX", + Summary: "Move with Zero-Extend", + Forms: []Form{ { Operands: []Operand{ - {Type: "imm16", Action: 0x0}, - {Type: "m16", Action: 0x3}, + {Type: "m16", Action: 0x1}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r16", Action: 0x1}, - {Type: "m16", Action: 0x3}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PABSB", - Summary: "Packed Absolute Value of Byte Integers", + Opcode: "MPSADBW", + Summary: "Compute Multiple Packed Sums of Absolute Difference", Forms: []Form{ { - ISA: []string{"SSSE3"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSSE3"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PABSD", - Summary: "Packed Absolute Value of Doubleword Integers", + Opcode: "MULB", + Summary: "Unsigned Multiply", Forms: []Form{ { - ISA: []string{"SSSE3"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m8", Action: 0x1}, + }, + ImplicitOperands: []ImplicitOperand{ + {Register: "ax", Action: 0x2}, + {Register: "al", Action: 0x1}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSSE3"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "r8", Action: 0x1}, + }, + ImplicitOperands: []ImplicitOperand{ + {Register: "ax", Action: 0x2}, + {Register: "al", Action: 0x1}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PABSW", - Summary: "Packed Absolute Value of Word Integers", + Opcode: "MULL", + Summary: "Unsigned Multiply", Forms: []Form{ { - ISA: []string{"SSSE3"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + }, + ImplicitOperands: []ImplicitOperand{ + {Register: "eax", Action: 0x3}, + {Register: "edx", Action: 0x2}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSSE3"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "r32", Action: 0x1}, + }, + ImplicitOperands: []ImplicitOperand{ + {Register: "eax", Action: 0x3}, + {Register: "edx", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PACKSSLW", - Summary: "Pack Doublewords into Words with Signed Saturation", + Opcode: "MULPD", + Summary: "Multiply Packed Double-Precision Floating-Point Values", Forms: []Form{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PACKSSWB", - Summary: "Pack Words into Bytes with Signed Saturation", + Opcode: "MULPS", + Summary: "Multiply Packed Single-Precision Floating-Point Values", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, + ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PACKUSDW", - Summary: "Pack Doublewords into Words with Unsigned Saturation", + Opcode: "MULQ", + Summary: "Unsigned Multiply", Forms: []Form{ { - ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m64", Action: 0x1}, + }, + ImplicitOperands: []ImplicitOperand{ + {Register: "rax", Action: 0x3}, + {Register: "rdx", Action: 0x2}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "r64", Action: 0x1}, + }, + ImplicitOperands: []ImplicitOperand{ + {Register: "rax", Action: 0x3}, + {Register: "rdx", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PACKUSWB", - Summary: "Pack Words into Bytes with Unsigned Saturation", + Opcode: "MULSD", + Summary: "Multiply Scalar Double-Precision Floating-Point Values", Forms: []Form{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PADDB", - Summary: "Add Packed Byte Integers", - Forms: []Form{ + Opcode: "MULSS", + Summary: "Multiply Scalar Single-Precision Floating-Point Values", + Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, + ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PADDD", - AliasOf: "PADDL", - Summary: "Add Packed Doubleword Integers", + Opcode: "MULW", + Summary: "Unsigned Multiply", Forms: []Form{ { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m16", Action: 0x1}, + }, + ImplicitOperands: []ImplicitOperand{ + {Register: "ax", Action: 0x3}, + {Register: "dx", Action: 0x2}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "r16", Action: 0x1}, + }, + ImplicitOperands: []ImplicitOperand{ + {Register: "ax", Action: 0x3}, + {Register: "dx", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PADDL", - Summary: "Add Packed Doubleword Integers", + Opcode: "MULXL", + Summary: "Unsigned Multiply Without Affecting Flags", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"BMI2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x2}, + {Type: "r32", Action: 0x2}, + }, + ImplicitOperands: []ImplicitOperand{ + {Register: "edx", Action: 0x1}, }, + EncodingType: 0x3, }, { - ISA: []string{"SSE2"}, + ISA: []string{"BMI2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "r32", Action: 0x1}, + {Type: "r32", Action: 0x2}, + {Type: "r32", Action: 0x2}, + }, + ImplicitOperands: []ImplicitOperand{ + {Register: "edx", Action: 0x1}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "PADDQ", - Summary: "Add Packed Quadword Integers", + Opcode: "MULXQ", + Summary: "Unsigned Multiply Without Affecting Flags", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"BMI2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x2}, + {Type: "r64", Action: 0x2}, + }, + ImplicitOperands: []ImplicitOperand{ + {Register: "rdx", Action: 0x1}, }, + EncodingType: 0x3, }, { - ISA: []string{"SSE2"}, + ISA: []string{"BMI2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "r64", Action: 0x1}, + {Type: "r64", Action: 0x2}, + {Type: "r64", Action: 0x2}, + }, + ImplicitOperands: []ImplicitOperand{ + {Register: "rdx", Action: 0x1}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "PADDSB", - Summary: "Add Packed Signed Byte Integers with Signed Saturation", + Opcode: "MWAIT", + Summary: "Monitor Wait", + Forms: []Form{ + { + ISA: []string{"MONITOR"}, + Operands: []Operand{}, + ImplicitOperands: []ImplicitOperand{ + {Register: "eax", Action: 0x1}, + {Register: "ecx", Action: 0x1}, + }, + EncodingType: 0x1, + }, + }, + }, + { + Opcode: "NEGB", + Summary: "Two's Complement Negation", Forms: []Form{ { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m8", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "r8", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PADDSW", - Summary: "Add Packed Signed Word Integers with Signed Saturation", + Opcode: "NEGL", + Summary: "Two's Complement Negation", Forms: []Form{ { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m32", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PADDUSB", - Summary: "Add Packed Unsigned Byte Integers with Unsigned Saturation", + Opcode: "NEGQ", + Summary: "Two's Complement Negation", Forms: []Form{ { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m64", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PADDUSW", - Summary: "Add Packed Unsigned Word Integers with Unsigned Saturation", + Opcode: "NEGW", + Summary: "Two's Complement Negation", Forms: []Form{ { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m16", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PADDW", - Summary: "Add Packed Word Integers", + Opcode: "NOP", + Summary: "No Operation", + Forms: []Form{ + { + Operands: []Operand{}, + EncodingType: 0x1, + }, + }, + }, + { + Opcode: "NOTB", + Summary: "One's Complement Negation", Forms: []Form{ { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m8", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "r8", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PALIGNR", - Summary: "Packed Align Right", + Opcode: "NOTL", + Summary: "One's Complement Negation", Forms: []Form{ { - ISA: []string{"SSSE3"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m32", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSSE3"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PAND", - Summary: "Packed Bitwise Logical AND", + Opcode: "NOTQ", + Summary: "One's Complement Negation", Forms: []Form{ { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m64", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PANDN", - Summary: "Packed Bitwise Logical AND NOT", + Opcode: "NOTW", + Summary: "One's Complement Negation", Forms: []Form{ { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m16", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PAUSE", - Summary: "Spin Loop Hint", + Opcode: "ORB", + Summary: "Logical Inclusive OR", Forms: []Form{ { - Operands: []Operand{}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "al", Action: 0x3}, + }, + EncodingType: 0x1, }, - }, - }, - { - Opcode: "PAVGB", - Summary: "Average Packed Byte Integers", - Forms: []Form{ { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m8", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "r8", Action: 0x3}, }, + EncodingType: 0x2, }, - }, - }, - { - Opcode: "PAVGW", - Summary: "Average Packed Word Integers", - Forms: []Form{ { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m8", Action: 0x1}, + {Type: "r8", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "r8", Action: 0x1}, + {Type: "m8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r8", Action: 0x1}, + {Type: "r8", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PBLENDVB", - Summary: "Variable Blend Packed Bytes", + Opcode: "ORL", + Summary: "Logical Inclusive OR", Forms: []Form{ { - ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "xmm0", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "imm32", Action: 0x0}, + {Type: "eax", Action: 0x3}, }, + EncodingType: 0x1, }, { - ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "xmm0", Action: 0x1}, - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "imm32", Action: 0x0}, + {Type: "m32", Action: 0x3}, }, + EncodingType: 0x2, }, - }, - }, - { - Opcode: "PBLENDW", - Summary: "Blend Packed Words", - Forms: []Form{ { - ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "imm32", Action: 0x0}, + {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE4.1"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m32", Action: 0x3}, }, + EncodingType: 0x2, }, - }, - }, - { - Opcode: "PCLMULQDQ", - Summary: "Carry-Less Quadword Multiplication", - Forms: []Form{ { - ISA: []string{"PCLMULQDQ"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"PCLMULQDQ"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, - }, - }, - { - Opcode: "PCMPEQB", - Summary: "Compare Packed Byte Data for Equality", - Forms: []Form{ { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "r32", Action: 0x1}, + {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PCMPEQL", - Summary: "Compare Packed Doubleword Data for Equality", + Opcode: "ORPD", + Summary: "Bitwise Logical OR of Double-Precision Floating-Point Values", Forms: []Form{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PCMPEQQ", - Summary: "Compare Packed Quadword Data for Equality", + Opcode: "ORPS", + Summary: "Bitwise Logical OR of Single-Precision Floating-Point Values", Forms: []Form{ { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x2, }, { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PCMPEQW", - Summary: "Compare Packed Word Data for Equality", + Opcode: "ORQ", + Summary: "Logical Inclusive OR", Forms: []Form{ { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "imm32", Action: 0x0}, + {Type: "m64", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "imm32", Action: 0x0}, + {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, - }, - }, - { - Opcode: "PCMPESTRI", - Summary: "Packed Compare Explicit Length Strings, Return Index", - Forms: []Form{ { - ISA: []string{"SSE4.2"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "imm32", Action: 0x0}, + {Type: "rax", Action: 0x3}, }, - ImplicitOperands: []ImplicitOperand{ - {Register: "eax", Action: 0x1}, - {Register: "ecx", Action: 0x2}, - {Register: "edx", Action: 0x1}, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE4.2"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "r64", Action: 0x3}, }, - ImplicitOperands: []ImplicitOperand{ - {Register: "eax", Action: 0x1}, - {Register: "ecx", Action: 0x2}, - {Register: "edx", Action: 0x1}, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, }, }, }, { - Opcode: "PCMPESTRM", - Summary: "Packed Compare Explicit Length Strings, Return Mask", + Opcode: "ORW", + Summary: "Logical Inclusive OR", Forms: []Form{ { - ISA: []string{"SSE4.2"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "imm16", Action: 0x0}, + {Type: "ax", Action: 0x3}, }, - ImplicitOperands: []ImplicitOperand{ - {Register: "eax", Action: 0x1}, - {Register: "edx", Action: 0x1}, - {Register: "xmm0", Action: 0x2}, + EncodingType: 0x1, + }, + { + Operands: []Operand{ + {Type: "imm16", Action: 0x0}, + {Type: "m16", Action: 0x3}, }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm16", Action: 0x0}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, }, { - ISA: []string{"SSE4.2"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "m16", Action: 0x3}, }, - ImplicitOperands: []ImplicitOperand{ - {Register: "eax", Action: 0x1}, - {Register: "edx", Action: 0x1}, - {Register: "xmm0", Action: 0x2}, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r16", Action: 0x1}, + {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PCMPGTB", - Summary: "Compare Packed Signed Byte Integers for Greater Than", + Opcode: "PABSB", + Summary: "Packed Absolute Value of Byte Integers", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"SSSE3"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, + ISA: []string{"SSSE3"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PCMPGTL", - Summary: "Compare Packed Signed Doubleword Integers for Greater Than", + Opcode: "PABSD", + Summary: "Packed Absolute Value of Doubleword Integers", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"SSSE3"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, + ISA: []string{"SSSE3"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PCMPGTQ", - Summary: "Compare Packed Data for Greater Than", + Opcode: "PABSW", + Summary: "Packed Absolute Value of Word Integers", Forms: []Form{ { - ISA: []string{"SSE4.2"}, + ISA: []string{"SSSE3"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x2, }, { - ISA: []string{"SSE4.2"}, + ISA: []string{"SSSE3"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PCMPGTW", - Summary: "Compare Packed Signed Word Integers for Greater Than", + Opcode: "PACKSSLW", + Summary: "Pack Doublewords into Words with Signed Saturation", Forms: []Form{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PCMPISTRI", - Summary: "Packed Compare Implicit Length Strings, Return Index", + Opcode: "PACKSSWB", + Summary: "Pack Words into Bytes with Signed Saturation", Forms: []Form{ { - ISA: []string{"SSE4.2"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - }, - ImplicitOperands: []ImplicitOperand{ - {Register: "ecx", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE4.2"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, - ImplicitOperands: []ImplicitOperand{ - {Register: "ecx", Action: 0x2}, - }, + EncodingType: 0x2, }, }, }, { - Opcode: "PCMPISTRM", - Summary: "Packed Compare Implicit Length Strings, Return Mask", + Opcode: "PACKUSDW", + Summary: "Pack Doublewords into Words with Unsigned Saturation", Forms: []Form{ { - ISA: []string{"SSE4.2"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - }, - ImplicitOperands: []ImplicitOperand{ - {Register: "xmm0", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE4.2"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, - ImplicitOperands: []ImplicitOperand{ - {Register: "xmm0", Action: 0x2}, - }, + EncodingType: 0x2, }, }, }, { - Opcode: "PDEPL", - Summary: "Parallel Bits Deposit", + Opcode: "PACKUSWB", + Summary: "Pack Words into Bytes with Unsigned Saturation", Forms: []Form{ { - ISA: []string{"BMI2"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"BMI2"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PDEPQ", - Summary: "Parallel Bits Deposit", + Opcode: "PADDB", + Summary: "Add Packed Byte Integers", Forms: []Form{ { - ISA: []string{"BMI2"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"BMI2"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PEXTL", - Summary: "Parallel Bits Extract", + Opcode: "PADDD", + AliasOf: "PADDL", + Summary: "Add Packed Doubleword Integers", Forms: []Form{ { - ISA: []string{"BMI2"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"BMI2"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PEXTQ", - Summary: "Parallel Bits Extract", + Opcode: "PADDL", + Summary: "Add Packed Doubleword Integers", Forms: []Form{ { - ISA: []string{"BMI2"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"BMI2"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PEXTRB", - Summary: "Extract Byte", + Opcode: "PADDQ", + Summary: "Add Packed Quadword Integers", Forms: []Form{ { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, - {Type: "m8", Action: 0x2}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PEXTRD", - Summary: "Extract Doubleword", + Opcode: "PADDSB", + Summary: "Add Packed Signed Byte Integers with Signed Saturation", Forms: []Form{ { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, - {Type: "m32", Action: 0x2}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PEXTRQ", - Summary: "Extract Quadword", + Opcode: "PADDSW", + Summary: "Add Packed Signed Word Integers with Signed Saturation", Forms: []Form{ { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, - {Type: "m64", Action: 0x2}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PEXTRW", - Summary: "Extract Word", + Opcode: "PADDUSB", + Summary: "Add Packed Unsigned Byte Integers with Unsigned Saturation", Forms: []Form{ { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, - {Type: "m16", Action: 0x2}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PHADDD", - Summary: "Packed Horizontal Add Doubleword Integer", + Opcode: "PADDUSW", + Summary: "Add Packed Unsigned Word Integers with Unsigned Saturation", Forms: []Form{ { - ISA: []string{"SSSE3"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSSE3"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PHADDSW", - Summary: "Packed Horizontal Add Signed Word Integers with Signed Saturation", + Opcode: "PADDW", + Summary: "Add Packed Word Integers", Forms: []Form{ { - ISA: []string{"SSSE3"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSSE3"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PHADDW", - Summary: "Packed Horizontal Add Word Integers", + Opcode: "PALIGNR", + Summary: "Packed Align Right", Forms: []Form{ { ISA: []string{"SSSE3"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSSE3"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PHMINPOSUW", - Summary: "Packed Horizontal Minimum of Unsigned Word Integers", + Opcode: "PAND", + Summary: "Packed Bitwise Logical AND", Forms: []Form{ { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PHSUBD", - Summary: "Packed Horizontal Subtract Doubleword Integers", + Opcode: "PANDN", + Summary: "Packed Bitwise Logical AND NOT", Forms: []Form{ { - ISA: []string{"SSSE3"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x2, }, { - ISA: []string{"SSSE3"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, + CancellingInputs: true, }, }, }, { - Opcode: "PHSUBSW", - Summary: "Packed Horizontal Subtract Signed Word Integers with Signed Saturation", + Opcode: "PAUSE", + Summary: "Spin Loop Hint", Forms: []Form{ { - ISA: []string{"SSSE3"}, - Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, - }, - CancellingInputs: true, - }, - { - ISA: []string{"SSSE3"}, - Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, - }, + Operands: []Operand{}, + EncodingType: 0x1, }, }, }, { - Opcode: "PHSUBW", - Summary: "Packed Horizontal Subtract Word Integers", + Opcode: "PAVGB", + Summary: "Average Packed Byte Integers", Forms: []Form{ { - ISA: []string{"SSSE3"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x2, }, { - ISA: []string{"SSSE3"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PINSRB", - Summary: "Insert Byte", + Opcode: "PAVGW", + Summary: "Average Packed Word Integers", Forms: []Form{ { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r32", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m8", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PINSRD", - Summary: "Insert Doubleword", + Opcode: "PBLENDVB", + Summary: "Variable Blend Packed Bytes", Forms: []Form{ { ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r32", Action: 0x1}, + {Type: "xmm0", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m32", Action: 0x1}, + {Type: "xmm0", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PINSRQ", - Summary: "Insert Quadword", + Opcode: "PBLENDW", + Summary: "Blend Packed Words", Forms: []Form{ { ISA: []string{"SSE4.1"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r64", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE4.1"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PINSRW", - Summary: "Insert Word", + Opcode: "PCLMULQDQ", + Summary: "Carry-Less Quadword Multiplication", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"PCLMULQDQ"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r32", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, + ISA: []string{"PCLMULQDQ"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "m16", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PMADDUBSW", - Summary: "Multiply and Add Packed Signed and Unsigned Byte Integers", + Opcode: "PCMPEQB", + Summary: "Compare Packed Byte Data for Equality", Forms: []Form{ { - ISA: []string{"SSSE3"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSSE3"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, + CancellingInputs: true, }, }, }, { - Opcode: "PMADDWL", - Summary: "Multiply and Add Packed Signed Word Integers", + Opcode: "PCMPEQL", + Summary: "Compare Packed Doubleword Data for Equality", Forms: []Form{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, + CancellingInputs: true, }, }, }, { - Opcode: "PMAXSB", - Summary: "Maximum of Packed Signed Byte Integers", + Opcode: "PCMPEQQ", + Summary: "Compare Packed Quadword Data for Equality", Forms: []Form{ - { - ISA: []string{"SSE4.1"}, - Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, - }, - }, { ISA: []string{"SSE4.1"}, Operands: []Operand{ {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, - }, - }, - { - Opcode: "PMAXSD", - Summary: "Maximum of Packed Signed Doubleword Integers", - Forms: []Form{ { ISA: []string{"SSE4.1"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, - }, - { - ISA: []string{"SSE4.1"}, - Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, - }, + EncodingType: 0x2, + CancellingInputs: true, }, }, }, { - Opcode: "PMAXSW", - Summary: "Maximum of Packed Signed Word Integers", + Opcode: "PCMPEQW", + Summary: "Compare Packed Word Data for Equality", Forms: []Form{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, + CancellingInputs: true, }, }, }, { - Opcode: "PMAXUB", - Summary: "Maximum of Packed Unsigned Byte Integers", + Opcode: "PCMPESTRI", + Summary: "Packed Compare Explicit Length Strings, Return Index", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"SSE4.2"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, }, + ImplicitOperands: []ImplicitOperand{ + {Register: "eax", Action: 0x1}, + {Register: "ecx", Action: 0x2}, + {Register: "edx", Action: 0x1}, + }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, + ISA: []string{"SSE4.2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + }, + ImplicitOperands: []ImplicitOperand{ + {Register: "eax", Action: 0x1}, + {Register: "ecx", Action: 0x2}, + {Register: "edx", Action: 0x1}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PMAXUD", - Summary: "Maximum of Packed Unsigned Doubleword Integers", + Opcode: "PCMPESTRM", + Summary: "Packed Compare Explicit Length Strings, Return Mask", Forms: []Form{ { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSE4.2"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, }, + ImplicitOperands: []ImplicitOperand{ + {Register: "eax", Action: 0x1}, + {Register: "edx", Action: 0x1}, + {Register: "xmm0", Action: 0x2}, + }, + EncodingType: 0x2, }, { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSE4.2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, }, + ImplicitOperands: []ImplicitOperand{ + {Register: "eax", Action: 0x1}, + {Register: "edx", Action: 0x1}, + {Register: "xmm0", Action: 0x2}, + }, + EncodingType: 0x2, }, }, }, { - Opcode: "PMAXUW", - Summary: "Maximum of Packed Unsigned Word Integers", + Opcode: "PCMPGTB", + Summary: "Compare Packed Signed Byte Integers for Greater Than", Forms: []Form{ { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, + CancellingInputs: true, }, }, }, { - Opcode: "PMINSB", - Summary: "Minimum of Packed Signed Byte Integers", + Opcode: "PCMPGTL", + Summary: "Compare Packed Signed Doubleword Integers for Greater Than", Forms: []Form{ { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, + CancellingInputs: true, }, }, }, { - Opcode: "PMINSD", - Summary: "Minimum of Packed Signed Doubleword Integers", + Opcode: "PCMPGTQ", + Summary: "Compare Packed Data for Greater Than", Forms: []Form{ { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSE4.2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSE4.2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, + CancellingInputs: true, }, }, }, { - Opcode: "PMINSW", - Summary: "Minimum of Packed Signed Word Integers", + Opcode: "PCMPGTW", + Summary: "Compare Packed Signed Word Integers for Greater Than", Forms: []Form{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, + CancellingInputs: true, }, }, }, { - Opcode: "PMINUB", - Summary: "Minimum of Packed Unsigned Byte Integers", + Opcode: "PCMPISTRI", + Summary: "Packed Compare Implicit Length Strings, Return Index", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"SSE4.2"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, }, + ImplicitOperands: []ImplicitOperand{ + {Register: "ecx", Action: 0x2}, + }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, + ISA: []string{"SSE4.2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, }, + ImplicitOperands: []ImplicitOperand{ + {Register: "ecx", Action: 0x2}, + }, + EncodingType: 0x2, }, }, }, { - Opcode: "PMINUD", - Summary: "Minimum of Packed Unsigned Doubleword Integers", + Opcode: "PCMPISTRM", + Summary: "Packed Compare Implicit Length Strings, Return Mask", Forms: []Form{ { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSE4.2"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, }, + ImplicitOperands: []ImplicitOperand{ + {Register: "xmm0", Action: 0x2}, + }, + EncodingType: 0x2, }, { - ISA: []string{"SSE4.1"}, - Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, - }, - }, - }, - }, - { - Opcode: "PMINUW", - Summary: "Minimum of Packed Unsigned Word Integers", - Forms: []Form{ - { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSE4.2"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, }, - }, - { - ISA: []string{"SSE4.1"}, - Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + ImplicitOperands: []ImplicitOperand{ + {Register: "xmm0", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PMOVMSKB", - Summary: "Move Byte Mask", + Opcode: "PDEPL", + Summary: "Parallel Bits Deposit", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"BMI2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, {Type: "r32", Action: 0x2}, }, - }, - }, - }, - { - Opcode: "PMOVSXBD", - Summary: "Move Packed Byte Integers to Doubleword Integers with Sign Extension", - Forms: []Form{ - { - ISA: []string{"SSE4.1"}, - Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, - }, + EncodingType: 0x3, }, { - ISA: []string{"SSE4.1"}, + ISA: []string{"BMI2"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "r32", Action: 0x1}, + {Type: "r32", Action: 0x1}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "PMOVSXBQ", - Summary: "Move Packed Byte Integers to Quadword Integers with Sign Extension", + Opcode: "PDEPQ", + Summary: "Parallel Bits Deposit", Forms: []Form{ { - ISA: []string{"SSE4.1"}, + ISA: []string{"BMI2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"SSE4.1"}, + ISA: []string{"BMI2"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "r64", Action: 0x1}, + {Type: "r64", Action: 0x1}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "PMOVSXBW", - Summary: "Move Packed Byte Integers to Word Integers with Sign Extension", + Opcode: "PEXTL", + Summary: "Parallel Bits Extract", Forms: []Form{ { - ISA: []string{"SSE4.1"}, + ISA: []string{"BMI2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x1}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"SSE4.1"}, + ISA: []string{"BMI2"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "r32", Action: 0x1}, + {Type: "r32", Action: 0x1}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "PMOVSXDQ", - Summary: "Move Packed Doubleword Integers to Quadword Integers with Sign Extension", + Opcode: "PEXTQ", + Summary: "Parallel Bits Extract", Forms: []Form{ { - ISA: []string{"SSE4.1"}, + ISA: []string{"BMI2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x1}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"SSE4.1"}, + ISA: []string{"BMI2"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "r64", Action: 0x1}, + {Type: "r64", Action: 0x1}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "PMOVSXWD", - Summary: "Move Packed Word Integers to Doubleword Integers with Sign Extension", + Opcode: "PEXTRB", + Summary: "Extract Byte", Forms: []Form{ { ISA: []string{"SSE4.1"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m8", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PMOVSXWQ", - Summary: "Move Packed Word Integers to Quadword Integers with Sign Extension", + Opcode: "PEXTRD", + Summary: "Extract Doubleword", Forms: []Form{ { ISA: []string{"SSE4.1"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PMOVZXBD", - Summary: "Move Packed Byte Integers to Doubleword Integers with Zero Extension", + Opcode: "PEXTRQ", + Summary: "Extract Quadword", Forms: []Form{ { ISA: []string{"SSE4.1"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m64", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PMOVZXBQ", - Summary: "Move Packed Byte Integers to Quadword Integers with Zero Extension", + Opcode: "PEXTRW", + Summary: "Extract Word", Forms: []Form{ { ISA: []string{"SSE4.1"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m16", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PMOVZXBW", - Summary: "Move Packed Byte Integers to Word Integers with Zero Extension", + Opcode: "PHADDD", + Summary: "Packed Horizontal Add Doubleword Integer", Forms: []Form{ { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSSE3"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSSE3"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PMOVZXDQ", - Summary: "Move Packed Doubleword Integers to Quadword Integers with Zero Extension", + Opcode: "PHADDSW", + Summary: "Packed Horizontal Add Signed Word Integers with Signed Saturation", Forms: []Form{ { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSSE3"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSSE3"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PMOVZXWD", - Summary: "Move Packed Word Integers to Doubleword Integers with Zero Extension", + Opcode: "PHADDW", + Summary: "Packed Horizontal Add Word Integers", Forms: []Form{ { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSSE3"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSSE3"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PMOVZXWQ", - Summary: "Move Packed Word Integers to Quadword Integers with Zero Extension", + Opcode: "PHMINPOSUW", + Summary: "Packed Horizontal Minimum of Unsigned Word Integers", Forms: []Form{ { ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PMULDQ", - Summary: "Multiply Packed Signed Doubleword Integers and Store Quadword Result", + Opcode: "PHSUBD", + Summary: "Packed Horizontal Subtract Doubleword Integers", Forms: []Form{ { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSSE3"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSSE3"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, + CancellingInputs: true, }, }, }, { - Opcode: "PMULHRSW", - Summary: "Packed Multiply Signed Word Integers and Store High Result with Round and Scale", + Opcode: "PHSUBSW", + Summary: "Packed Horizontal Subtract Signed Word Integers with Signed Saturation", Forms: []Form{ { ISA: []string{"SSSE3"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSSE3"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, + CancellingInputs: true, }, }, }, { - Opcode: "PMULHUW", - Summary: "Multiply Packed Unsigned Word Integers and Store High Result", + Opcode: "PHSUBW", + Summary: "Packed Horizontal Subtract Word Integers", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"SSSE3"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, + ISA: []string{"SSSE3"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, + CancellingInputs: true, }, }, }, { - Opcode: "PMULHW", - Summary: "Multiply Packed Signed Word Integers and Store High Result", + Opcode: "PINSRB", + Summary: "Insert Byte", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m8", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "r32", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PMULLD", - Summary: "Multiply Packed Signed Doubleword Integers and Store Low Result", + Opcode: "PINSRD", + Summary: "Insert Doubleword", Forms: []Form{ { ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "r32", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PMULLW", - Summary: "Multiply Packed Signed Word Integers and Store Low Result", + Opcode: "PINSRQ", + Summary: "Insert Quadword", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "r64", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PMULULQ", - Summary: "Multiply Packed Unsigned Doubleword Integers", + Opcode: "PINSRW", + Summary: "Insert Word", Forms: []Form{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m16", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "r32", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "POPCNTL", - Summary: "Count of Number of Bits Set to 1", + Opcode: "PMADDUBSW", + Summary: "Multiply and Add Packed Signed and Unsigned Byte Integers", Forms: []Form{ { - ISA: []string{"POPCNT"}, + ISA: []string{"SSSE3"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"POPCNT"}, + ISA: []string{"SSSE3"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "POPCNTQ", - Summary: "Count of Number of Bits Set to 1", + Opcode: "PMADDWL", + Summary: "Multiply and Add Packed Signed Word Integers", Forms: []Form{ { - ISA: []string{"POPCNT"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"POPCNT"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "POPCNTW", - Summary: "Count of Number of Bits Set to 1", + Opcode: "PMAXSB", + Summary: "Maximum of Packed Signed Byte Integers", Forms: []Form{ { - ISA: []string{"POPCNT"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, - {Type: "r16", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"POPCNT"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, - {Type: "r16", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "POPQ", - Summary: "Pop a Value from the Stack", + Opcode: "PMAXSD", + Summary: "Maximum of Packed Signed Doubleword Integers", Forms: []Form{ { + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "r64", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "m64", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "POPW", - Summary: "Pop a Value from the Stack", + Opcode: "PMAXSW", + Summary: "Maximum of Packed Signed Word Integers", Forms: []Form{ { + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "r16", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m16", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "POR", - Summary: "Packed Bitwise Logical OR", + Opcode: "PMAXUB", + Summary: "Maximum of Packed Unsigned Byte Integers", Forms: []Form{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PREFETCHNTA", - Summary: "Prefetch Data Into Caches using NTA Hint", + Opcode: "PMAXUD", + Summary: "Maximum of Packed Unsigned Doubleword Integers", Forms: []Form{ { - ISA: []string{"MMX+"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "m8", Action: 0x1}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, - }, - }, - { - Opcode: "PREFETCHT0", - Summary: "Prefetch Data Into Caches using T0 Hint", - Forms: []Form{ { - ISA: []string{"MMX+"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "m8", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PREFETCHT1", - Summary: "Prefetch Data Into Caches using T1 Hint", + Opcode: "PMAXUW", + Summary: "Maximum of Packed Unsigned Word Integers", Forms: []Form{ { - ISA: []string{"MMX+"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "m8", Action: 0x1}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, - }, - }, - { - Opcode: "PREFETCHT2", - Summary: "Prefetch Data Into Caches using T2 Hint", - Forms: []Form{ { - ISA: []string{"MMX+"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "m8", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PSADBW", - Summary: "Compute Sum of Absolute Differences", + Opcode: "PMINSB", + Summary: "Minimum of Packed Signed Byte Integers", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PSHUFB", - Summary: "Packed Shuffle Bytes", + Opcode: "PMINSD", + Summary: "Minimum of Packed Signed Doubleword Integers", Forms: []Form{ { - ISA: []string{"SSSE3"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSSE3"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PSHUFD", - AliasOf: "PSHUFL", - Summary: "Shuffle Packed Doublewords", + Opcode: "PMINSW", + Summary: "Minimum of Packed Signed Word Integers", Forms: []Form{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PSHUFHW", - Summary: "Shuffle Packed High Words", + Opcode: "PMINUB", + Summary: "Minimum of Packed Unsigned Byte Integers", Forms: []Form{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PSHUFL", - Summary: "Shuffle Packed Doublewords", + Opcode: "PMINUD", + Summary: "Minimum of Packed Unsigned Doubleword Integers", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PSHUFLW", - Summary: "Shuffle Packed Low Words", + Opcode: "PMINUW", + Summary: "Minimum of Packed Unsigned Word Integers", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PSIGNB", - Summary: "Packed Sign of Byte Integers", + Opcode: "PMOVMSKB", + Summary: "Move Byte Mask", Forms: []Form{ { - ISA: []string{"SSSE3"}, + ISA: []string{"SSE2"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, - }, - }, - { - ISA: []string{"SSSE3"}, - Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PSIGND", - Summary: "Packed Sign of Doubleword Integers", + Opcode: "PMOVSXBD", + Summary: "Move Packed Byte Integers to Doubleword Integers with Sign Extension", Forms: []Form{ { - ISA: []string{"SSSE3"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSSE3"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PSIGNW", - Summary: "Packed Sign of Word Integers", + Opcode: "PMOVSXBQ", + Summary: "Move Packed Byte Integers to Quadword Integers with Sign Extension", Forms: []Form{ { - ISA: []string{"SSSE3"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m16", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSSE3"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PSLLDQ", - AliasOf: "PSLLO", - Summary: "Shift Packed Double Quadword Left Logical", + Opcode: "PMOVSXBW", + Summary: "Move Packed Byte Integers to Word Integers with Sign Extension", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE4.1"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PSLLL", - Summary: "Shift Packed Doubleword Data Left Logical", + Opcode: "PMOVSXDQ", + Summary: "Move Packed Doubleword Integers to Quadword Integers with Sign Extension", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "PMOVSXWD", + Summary: "Move Packed Word Integers to Doubleword Integers with Sign Extension", + Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE4.1"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PSLLO", - Summary: "Shift Packed Double Quadword Left Logical", + Opcode: "PMOVSXWQ", + Summary: "Move Packed Word Integers to Quadword Integers with Sign Extension", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE4.1"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PSLLQ", - Summary: "Shift Packed Quadword Data Left Logical", + Opcode: "PMOVZXBD", + Summary: "Move Packed Byte Integers to Doubleword Integers with Zero Extension", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "PMOVZXBQ", + Summary: "Move Packed Byte Integers to Quadword Integers with Zero Extension", + Forms: []Form{ + { + ISA: []string{"SSE4.1"}, + Operands: []Operand{ + {Type: "m16", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PSLLW", - Summary: "Shift Packed Word Data Left Logical", + Opcode: "PMOVZXBW", + Summary: "Move Packed Byte Integers to Word Integers with Zero Extension", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "PMOVZXDQ", + Summary: "Move Packed Doubleword Integers to Quadword Integers with Zero Extension", + Forms: []Form{ + { + ISA: []string{"SSE4.1"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PSRAL", - Summary: "Shift Packed Doubleword Data Right Arithmetic", + Opcode: "PMOVZXWD", + Summary: "Move Packed Word Integers to Doubleword Integers with Zero Extension", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "PMOVZXWQ", + Summary: "Move Packed Word Integers to Quadword Integers with Zero Extension", + Forms: []Form{ + { + ISA: []string{"SSE4.1"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PSRAW", - Summary: "Shift Packed Word Data Right Arithmetic", + Opcode: "PMULDQ", + Summary: "Multiply Packed Signed Doubleword Integers and Store Quadword Result", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "PMULHRSW", + Summary: "Packed Multiply Signed Word Integers and Store High Result with Round and Scale", + Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"SSSE3"}, Operands: []Operand{ {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSSE3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, }, }, }, { - Opcode: "PSRLDQ", - AliasOf: "PSRLO", - Summary: "Shift Packed Double Quadword Right Logical", + Opcode: "PMULHUW", + Summary: "Multiply Packed Unsigned Word Integers and Store High Result", Forms: []Form{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PSRLL", - Summary: "Shift Packed Doubleword Data Right Logical", + Opcode: "PMULHW", + Summary: "Multiply Packed Signed Word Integers and Store High Result", Forms: []Form{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, @@ -10173,39 +11481,65 @@ var Instructions = []Instruction{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "PMULLD", + Summary: "Multiply Packed Signed Doubleword Integers and Store Low Result", + Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"SSE4.1"}, Operands: []Operand{ {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE4.1"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, }, }, }, { - Opcode: "PSRLO", - Summary: "Shift Packed Double Quadword Right Logical", + Opcode: "PMULLW", + Summary: "Multiply Packed Signed Word Integers and Store Low Result", Forms: []Form{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PSRLQ", - Summary: "Shift Packed Quadword Data Right Logical", + Opcode: "PMULULQ", + Summary: "Multiply Packed Unsigned Doubleword Integers", Forms: []Form{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, @@ -10213,13438 +11547,102931 @@ var Instructions = []Instruction{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "POPCNTL", + Summary: "Count of Number of Bits Set to 1", + Forms: []Form{ + { + ISA: []string{"POPCNT"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, + ISA: []string{"POPCNT"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "r32", Action: 0x1}, + {Type: "r32", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PSRLW", - Summary: "Shift Packed Word Data Right Logical", + Opcode: "POPCNTQ", + Summary: "Count of Number of Bits Set to 1", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"POPCNT"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, + ISA: []string{"POPCNT"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "r64", Action: 0x1}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "POPCNTW", + Summary: "Count of Number of Bits Set to 1", + Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"POPCNT"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"POPCNT"}, + Operands: []Operand{ + {Type: "r16", Action: 0x1}, + {Type: "r16", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PSUBB", - Summary: "Subtract Packed Byte Integers", + Opcode: "POPQ", + Summary: "Pop a Value from the Stack", Forms: []Form{ { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m64", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "r64", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PSUBL", - Summary: "Subtract Packed Doubleword Integers", + Opcode: "POPW", + Summary: "Pop a Value from the Stack", Forms: []Form{ { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m16", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "r16", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PSUBQ", - Summary: "Subtract Packed Quadword Integers", + Opcode: "POR", + Summary: "Packed Bitwise Logical OR", Forms: []Form{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PSUBSB", - Summary: "Subtract Packed Signed Byte Integers with Signed Saturation", + Opcode: "PREFETCHNTA", + Summary: "Prefetch Data Into Caches using NTA Hint", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"MMX+"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m8", Action: 0x1}, }, - CancellingInputs: true, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "PREFETCHT0", + Summary: "Prefetch Data Into Caches using T0 Hint", + Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"MMX+"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m8", Action: 0x1}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PSUBSW", - Summary: "Subtract Packed Signed Word Integers with Signed Saturation", + Opcode: "PREFETCHT1", + Summary: "Prefetch Data Into Caches using T1 Hint", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"MMX+"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m8", Action: 0x1}, }, - CancellingInputs: true, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "PREFETCHT2", + Summary: "Prefetch Data Into Caches using T2 Hint", + Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"MMX+"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m8", Action: 0x1}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PSUBUSB", - Summary: "Subtract Packed Unsigned Byte Integers with Unsigned Saturation", + Opcode: "PSADBW", + Summary: "Compute Sum of Absolute Differences", Forms: []Form{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, + CancellingInputs: true, }, }, }, { - Opcode: "PSUBUSW", - Summary: "Subtract Packed Unsigned Word Integers with Unsigned Saturation", + Opcode: "PSHUFB", + Summary: "Packed Shuffle Bytes", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"SSSE3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSSE3"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x2, }, + }, + }, + { + Opcode: "PSHUFD", + AliasOf: "PSHUFL", + Summary: "Shuffle Packed Doublewords", + Forms: []Form{ { ISA: []string{"SSE2"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PSUBW", - Summary: "Subtract Packed Word Integers", + Opcode: "PSHUFHW", + Summary: "Shuffle Packed High Words", Forms: []Form{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PTEST", - Summary: "Packed Logical Compare", + Opcode: "PSHUFL", + Summary: "Shuffle Packed Doublewords", Forms: []Form{ { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE4.1"}, + ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PUNPCKHBW", - Summary: "Unpack and Interleave High-Order Bytes into Words", + Opcode: "PSHUFLW", + Summary: "Shuffle Packed Low Words", Forms: []Form{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PUNPCKHLQ", - Summary: "Unpack and Interleave High-Order Doublewords into Quadwords", + Opcode: "PSIGNB", + Summary: "Packed Sign of Byte Integers", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"SSSE3"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, { - ISA: []string{"SSE2"}, + ISA: []string{"SSSE3"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x2, }, }, }, { - Opcode: "PUNPCKHQDQ", - Summary: "Unpack and Interleave High-Order Quadwords into Double Quadwords", + Opcode: "PSIGND", + Summary: "Packed Sign of Doubleword Integers", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"SSSE3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSSE3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "PSIGNW", + Summary: "Packed Sign of Word Integers", + Forms: []Form{ + { + ISA: []string{"SSSE3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSSE3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "PSLLDQ", + AliasOf: "PSLLO", + Summary: "Shift Packed Double Quadword Left Logical", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "PSLLL", + Summary: "Shift Packed Doubleword Data Left Logical", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "PSLLO", + Summary: "Shift Packed Double Quadword Left Logical", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "PSLLQ", + Summary: "Shift Packed Quadword Data Left Logical", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "PSLLW", + Summary: "Shift Packed Word Data Left Logical", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "PSRAL", + Summary: "Shift Packed Doubleword Data Right Arithmetic", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "PSRAW", + Summary: "Shift Packed Word Data Right Arithmetic", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "PSRLDQ", + AliasOf: "PSRLO", + Summary: "Shift Packed Double Quadword Right Logical", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "PSRLL", + Summary: "Shift Packed Doubleword Data Right Logical", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "PSRLO", + Summary: "Shift Packed Double Quadword Right Logical", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "PSRLQ", + Summary: "Shift Packed Quadword Data Right Logical", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "PSRLW", + Summary: "Shift Packed Word Data Right Logical", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "PSUBB", + Summary: "Subtract Packed Byte Integers", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "PSUBL", + Summary: "Subtract Packed Doubleword Integers", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "PSUBQ", + Summary: "Subtract Packed Quadword Integers", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "PSUBSB", + Summary: "Subtract Packed Signed Byte Integers with Signed Saturation", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "PSUBSW", + Summary: "Subtract Packed Signed Word Integers with Signed Saturation", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "PSUBUSB", + Summary: "Subtract Packed Unsigned Byte Integers with Unsigned Saturation", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "PSUBUSW", + Summary: "Subtract Packed Unsigned Word Integers with Unsigned Saturation", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "PSUBW", + Summary: "Subtract Packed Word Integers", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "PTEST", + Summary: "Packed Logical Compare", + Forms: []Form{ + { + ISA: []string{"SSE4.1"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE4.1"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "PUNPCKHBW", + Summary: "Unpack and Interleave High-Order Bytes into Words", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "PUNPCKHLQ", + Summary: "Unpack and Interleave High-Order Doublewords into Quadwords", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "PUNPCKHQDQ", + Summary: "Unpack and Interleave High-Order Quadwords into Double Quadwords", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "PUNPCKHWL", + Summary: "Unpack and Interleave High-Order Words into Doublewords", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "PUNPCKLBW", + Summary: "Unpack and Interleave Low-Order Bytes into Words", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "PUNPCKLLQ", + Summary: "Unpack and Interleave Low-Order Doublewords into Quadwords", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "PUNPCKLQDQ", + Summary: "Unpack and Interleave Low-Order Quadwords into Double Quadwords", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "PUNPCKLWL", + Summary: "Unpack and Interleave Low-Order Words into Doublewords", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "PUSHQ", + Summary: "Push Value Onto the Stack", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "imm32", Action: 0x0}, + }, + EncodingType: 0x1, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + }, + EncodingType: 0x1, + }, + { + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "PUSHW", + Summary: "Push Value Onto the Stack", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "m16", Action: 0x1}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r16", Action: 0x1}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "PXOR", + Summary: "Packed Bitwise Logical Exclusive OR", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "RCLB", + Summary: "Rotate Left through Carry Flag", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "RCLL", + Summary: "Rotate Left through Carry Flag", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "RCLQ", + Summary: "Rotate Left through Carry Flag", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "RCLW", + Summary: "Rotate Left through Carry Flag", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "RCPPS", + Summary: "Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"SSE"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "RCPSS", + Summary: "Compute Approximate Reciprocal of Scalar Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"SSE"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "RCRB", + Summary: "Rotate Right through Carry Flag", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "RCRL", + Summary: "Rotate Right through Carry Flag", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "RCRQ", + Summary: "Rotate Right through Carry Flag", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "RCRW", + Summary: "Rotate Right through Carry Flag", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "RDRANDL", + Summary: "Read Random Number", + Forms: []Form{ + { + ISA: []string{"RDRAND"}, + Operands: []Operand{ + {Type: "r16", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"RDRAND"}, + Operands: []Operand{ + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"RDRAND"}, + Operands: []Operand{ + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "RDSEEDL", + Summary: "Read Random SEED", + Forms: []Form{ + { + ISA: []string{"RDSEED"}, + Operands: []Operand{ + {Type: "r16", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"RDSEED"}, + Operands: []Operand{ + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"RDSEED"}, + Operands: []Operand{ + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "RDTSC", + Summary: "Read Time-Stamp Counter", + Forms: []Form{ + { + ISA: []string{"RDTSC"}, + Operands: []Operand{}, + ImplicitOperands: []ImplicitOperand{ + {Register: "eax", Action: 0x2}, + {Register: "edx", Action: 0x2}, + }, + EncodingType: 0x1, + }, + }, + }, + { + Opcode: "RDTSCP", + Summary: "Read Time-Stamp Counter and Processor ID", + Forms: []Form{ + { + ISA: []string{"RDTSCP"}, + Operands: []Operand{}, + ImplicitOperands: []ImplicitOperand{ + {Register: "eax", Action: 0x2}, + {Register: "ecx", Action: 0x2}, + {Register: "edx", Action: 0x2}, + }, + EncodingType: 0x1, + }, + }, + }, + { + Opcode: "RET", + Summary: "Return from Procedure", + Forms: []Form{ + { + Operands: []Operand{}, + EncodingType: 0x1, + }, + }, + }, + { + Opcode: "RETFL", + Summary: "Return from Procedure", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "imm16", Action: 0x0}, + }, + EncodingType: 0x1, + }, + }, + }, + { + Opcode: "RETFQ", + Summary: "Return from Procedure", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "imm16", Action: 0x0}, + }, + EncodingType: 0x1, + }, + }, + }, + { + Opcode: "RETFW", + Summary: "Return from Procedure", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "imm16", Action: 0x0}, + }, + EncodingType: 0x1, + }, + }, + }, + { + Opcode: "ROLB", + Summary: "Rotate Left", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "ROLL", + Summary: "Rotate Left", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "ROLQ", + Summary: "Rotate Left", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "ROLW", + Summary: "Rotate Left", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "RORB", + Summary: "Rotate Right", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "RORL", + Summary: "Rotate Right", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "RORQ", + Summary: "Rotate Right", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "RORW", + Summary: "Rotate Right", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "RORXL", + Summary: "Rotate Right Logical Without Affecting Flags", + Forms: []Form{ + { + ISA: []string{"BMI2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"BMI2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r32", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "RORXQ", + Summary: "Rotate Right Logical Without Affecting Flags", + Forms: []Form{ + { + ISA: []string{"BMI2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"BMI2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r64", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "ROUNDPD", + Summary: "Round Packed Double Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"SSE4.1"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE4.1"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "ROUNDPS", + Summary: "Round Packed Single Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"SSE4.1"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE4.1"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "ROUNDSD", + Summary: "Round Scalar Double Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"SSE4.1"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE4.1"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "ROUNDSS", + Summary: "Round Scalar Single Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"SSE4.1"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE4.1"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "RSQRTPS", + Summary: "Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"SSE"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "RSQRTSS", + Summary: "Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value", + Forms: []Form{ + { + ISA: []string{"SSE"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SALB", + Summary: "Arithmetic Shift Left", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SALL", + Summary: "Arithmetic Shift Left", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SALQ", + Summary: "Arithmetic Shift Left", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SALW", + Summary: "Arithmetic Shift Left", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SARB", + Summary: "Arithmetic Shift Right", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SARL", + Summary: "Arithmetic Shift Right", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SARQ", + Summary: "Arithmetic Shift Right", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SARW", + Summary: "Arithmetic Shift Right", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SARXL", + Summary: "Arithmetic Shift Right Without Affecting Flags", + Forms: []Form{ + { + ISA: []string{"BMI2"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"BMI2"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "r32", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "SARXQ", + Summary: "Arithmetic Shift Right Without Affecting Flags", + Forms: []Form{ + { + ISA: []string{"BMI2"}, + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"BMI2"}, + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "r64", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "SBBB", + Summary: "Subtract with Borrow", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "al", Action: 0x3}, + }, + EncodingType: 0x1, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "m8", Action: 0x1}, + {Type: "r8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r8", Action: 0x1}, + {Type: "m8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r8", Action: 0x1}, + {Type: "r8", Action: 0x3}, + }, + EncodingType: 0x2, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "SBBL", + Summary: "Subtract with Borrow", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "imm32", Action: 0x0}, + {Type: "eax", Action: 0x3}, + }, + EncodingType: 0x1, + }, + { + Operands: []Operand{ + {Type: "imm32", Action: 0x0}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm32", Action: 0x0}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "SBBQ", + Summary: "Subtract with Borrow", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "imm32", Action: 0x0}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm32", Action: 0x0}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm32", Action: 0x0}, + {Type: "rax", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "SBBW", + Summary: "Subtract with Borrow", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "imm16", Action: 0x0}, + {Type: "ax", Action: 0x3}, + }, + EncodingType: 0x1, + }, + { + Operands: []Operand{ + {Type: "imm16", Action: 0x0}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm16", Action: 0x0}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r16", Action: 0x1}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "SETCC", + Summary: "Set byte if above or equal (CF == 0)", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "m8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SETCS", + Summary: "Set byte if below (CF == 1)", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "m8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SETEQ", + Summary: "Set byte if equal (ZF == 1)", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "m8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SETGE", + Summary: "Set byte if greater or equal (SF == OF)", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "m8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SETGT", + Summary: "Set byte if greater (ZF == 0 and SF == OF)", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "m8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SETHI", + Summary: "Set byte if above (CF == 0 and ZF == 0)", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "m8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SETLE", + Summary: "Set byte if less or equal (ZF == 1 or SF != OF)", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "m8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SETLS", + Summary: "Set byte if below or equal (CF == 1 or ZF == 1)", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "m8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SETLT", + Summary: "Set byte if less (SF != OF)", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "m8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SETMI", + Summary: "Set byte if sign (SF == 1)", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "m8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SETNE", + Summary: "Set byte if not equal (ZF == 0)", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "m8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SETOC", + Summary: "Set byte if not overflow (OF == 0)", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "m8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SETOS", + Summary: "Set byte if overflow (OF == 1)", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "m8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SETPC", + Summary: "Set byte if not parity (PF == 0)", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "m8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SETPL", + Summary: "Set byte if not sign (SF == 0)", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "m8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SETPS", + Summary: "Set byte if parity (PF == 1)", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "m8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r8", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SFENCE", + Summary: "Store Fence", + Forms: []Form{ + { + ISA: []string{"MMX+"}, + Operands: []Operand{}, + EncodingType: 0x1, + }, + }, + }, + { + Opcode: "SHA1MSG1", + Summary: "Perform an Intermediate Calculation for the Next Four SHA1 Message Doublewords", + Forms: []Form{ + { + ISA: []string{"SHA"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SHA"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SHA1MSG2", + Summary: "Perform a Final Calculation for the Next Four SHA1 Message Doublewords", + Forms: []Form{ + { + ISA: []string{"SHA"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SHA"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SHA1NEXTE", + Summary: "Calculate SHA1 State Variable E after Four Rounds", + Forms: []Form{ + { + ISA: []string{"SHA"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SHA"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SHA1RNDS4", + Summary: "Perform Four Rounds of SHA1 Operation", + Forms: []Form{ + { + ISA: []string{"SHA"}, + Operands: []Operand{ + {Type: "imm2u", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SHA"}, + Operands: []Operand{ + {Type: "imm2u", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SHA256MSG1", + Summary: "Perform an Intermediate Calculation for the Next Four SHA256 Message Doublewords", + Forms: []Form{ + { + ISA: []string{"SHA"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SHA"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SHA256MSG2", + Summary: "Perform a Final Calculation for the Next Four SHA256 Message Doublewords", + Forms: []Form{ + { + ISA: []string{"SHA"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SHA"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SHA256RNDS2", + Summary: "Perform Two Rounds of SHA256 Operation", + Forms: []Form{ + { + ISA: []string{"SHA"}, + Operands: []Operand{ + {Type: "xmm0", Action: 0x1}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SHA"}, + Operands: []Operand{ + {Type: "xmm0", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SHLB", + Summary: "Logical Shift Left", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SHLL", + Summary: "Logical Shift Left", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r32", Action: 0x1}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r32", Action: 0x1}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SHLQ", + Summary: "Logical Shift Left", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r64", Action: 0x1}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r64", Action: 0x1}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SHLW", + Summary: "Logical Shift Left", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r16", Action: 0x1}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r16", Action: 0x1}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SHLXL", + Summary: "Logical Shift Left Without Affecting Flags", + Forms: []Form{ + { + ISA: []string{"BMI2"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"BMI2"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "r32", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "SHLXQ", + Summary: "Logical Shift Left Without Affecting Flags", + Forms: []Form{ + { + ISA: []string{"BMI2"}, + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"BMI2"}, + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "r64", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "SHRB", + Summary: "Logical Shift Right", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SHRL", + Summary: "Logical Shift Right", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r32", Action: 0x1}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r32", Action: 0x1}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SHRQ", + Summary: "Logical Shift Right", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r64", Action: 0x1}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r64", Action: 0x1}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SHRW", + Summary: "Logical Shift Right", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "1", Action: 0x0}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "cl", Action: 0x1}, + {Type: "r16", Action: 0x1}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r16", Action: 0x1}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SHRXL", + Summary: "Logical Shift Right Without Affecting Flags", + Forms: []Form{ + { + ISA: []string{"BMI2"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"BMI2"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "r32", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "SHRXQ", + Summary: "Logical Shift Right Without Affecting Flags", + Forms: []Form{ + { + ISA: []string{"BMI2"}, + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"BMI2"}, + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "r64", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "SHUFPD", + Summary: "Shuffle Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SHUFPS", + Summary: "Shuffle Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"SSE"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SQRTPD", + Summary: "Compute Square Roots of Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SQRTPS", + Summary: "Compute Square Roots of Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"SSE"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SQRTSD", + Summary: "Compute Square Root of Scalar Double-Precision Floating-Point Value", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SQRTSS", + Summary: "Compute Square Root of Scalar Single-Precision Floating-Point Value", + Forms: []Form{ + { + ISA: []string{"SSE"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "STC", + Summary: "Set Carry Flag", + Forms: []Form{ + { + Operands: []Operand{}, + EncodingType: 0x1, + }, + }, + }, + { + Opcode: "STD", + Summary: "Set Direction Flag", + Forms: []Form{ + { + Operands: []Operand{}, + EncodingType: 0x1, + }, + }, + }, + { + Opcode: "STMXCSR", + Summary: "Store MXCSR Register State", + Forms: []Form{ + { + ISA: []string{"SSE"}, + Operands: []Operand{ + {Type: "m32", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SUBB", + Summary: "Subtract", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "al", Action: 0x3}, + }, + EncodingType: 0x1, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "m8", Action: 0x1}, + {Type: "r8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r8", Action: 0x1}, + {Type: "m8", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r8", Action: 0x1}, + {Type: "r8", Action: 0x3}, + }, + EncodingType: 0x2, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "SUBL", + Summary: "Subtract", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "imm32", Action: 0x0}, + {Type: "eax", Action: 0x3}, + }, + EncodingType: 0x1, + }, + { + Operands: []Operand{ + {Type: "imm32", Action: 0x0}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm32", Action: 0x0}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "r32", Action: 0x3}, + }, + EncodingType: 0x2, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "SUBPD", + Summary: "Subtract Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SUBPS", + Summary: "Subtract Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"SSE"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SUBQ", + Summary: "Subtract", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "imm32", Action: 0x0}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm32", Action: 0x0}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm32", Action: 0x0}, + {Type: "rax", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "r64", Action: 0x3}, + }, + EncodingType: 0x2, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "SUBSD", + Summary: "Subtract Scalar Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SUBSS", + Summary: "Subtract Scalar Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"SSE"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "SUBW", + Summary: "Subtract", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "imm16", Action: 0x0}, + {Type: "ax", Action: 0x3}, + }, + EncodingType: 0x1, + }, + { + Operands: []Operand{ + {Type: "imm16", Action: 0x0}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm16", Action: 0x0}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r16", Action: 0x1}, + {Type: "r16", Action: 0x3}, + }, + EncodingType: 0x2, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "SYSCALL", + Summary: "Fast System Call", + Forms: []Form{ + { + Operands: []Operand{}, + ImplicitOperands: []ImplicitOperand{ + {Register: "r11", Action: 0x2}, + {Register: "rcx", Action: 0x2}, + }, + EncodingType: 0x1, + }, + }, + }, + { + Opcode: "TESTB", + Summary: "Logical Compare", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "al", Action: 0x1}, + }, + EncodingType: 0x1, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m8", Action: 0x1}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r8", Action: 0x1}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r8", Action: 0x1}, + {Type: "m8", Action: 0x1}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r8", Action: 0x1}, + {Type: "r8", Action: 0x1}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "TESTL", + Summary: "Logical Compare", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "imm32", Action: 0x0}, + {Type: "eax", Action: 0x1}, + }, + EncodingType: 0x1, + }, + { + Operands: []Operand{ + {Type: "imm32", Action: 0x0}, + {Type: "m32", Action: 0x1}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm32", Action: 0x0}, + {Type: "r32", Action: 0x1}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "r32", Action: 0x1}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "TESTQ", + Summary: "Logical Compare", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "imm32", Action: 0x0}, + {Type: "m64", Action: 0x1}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm32", Action: 0x0}, + {Type: "r64", Action: 0x1}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm32", Action: 0x0}, + {Type: "rax", Action: 0x1}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "m64", Action: 0x1}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "r64", Action: 0x1}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "TESTW", + Summary: "Logical Compare", + Forms: []Form{ + { + Operands: []Operand{ + {Type: "imm16", Action: 0x0}, + {Type: "ax", Action: 0x1}, + }, + EncodingType: 0x1, + }, + { + Operands: []Operand{ + {Type: "imm16", Action: 0x0}, + {Type: "m16", Action: 0x1}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "imm16", Action: 0x0}, + {Type: "r16", Action: 0x1}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r16", Action: 0x1}, + {Type: "m16", Action: 0x1}, + }, + EncodingType: 0x2, + }, + { + Operands: []Operand{ + {Type: "r16", Action: 0x1}, + {Type: "r16", Action: 0x1}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "TZCNTL", + Summary: "Count the Number of Trailing Zero Bits", + Forms: []Form{ + { + ISA: []string{"BMI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"BMI"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "TZCNTQ", + Summary: "Count the Number of Trailing Zero Bits", + Forms: []Form{ + { + ISA: []string{"BMI"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"BMI"}, + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "TZCNTW", + Summary: "Count the Number of Trailing Zero Bits", + Forms: []Form{ + { + ISA: []string{"BMI"}, + Operands: []Operand{ + {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x2}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"BMI"}, + Operands: []Operand{ + {Type: "r16", Action: 0x1}, + {Type: "r16", Action: 0x2}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "UCOMISD", + Summary: "Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "UCOMISS", + Summary: "Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS", + Forms: []Form{ + { + ISA: []string{"SSE"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "UD2", + Summary: "Undefined Instruction", + Forms: []Form{ + { + Operands: []Operand{}, + EncodingType: 0x1, + }, + }, + }, + { + Opcode: "UNPCKHPD", + Summary: "Unpack and Interleave High Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "UNPCKHPS", + Summary: "Unpack and Interleave High Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"SSE"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "UNPCKLPD", + Summary: "Unpack and Interleave Low Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "UNPCKLPS", + Summary: "Unpack and Interleave Low Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"SSE"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + { + ISA: []string{"SSE"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x2, + }, + }, + }, + { + Opcode: "VADDPD", + Summary: "Add Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VADDPS", + Summary: "Add Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VADDSD", + Summary: "Add Scalar Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VADDSS", + Summary: "Add Scalar Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VADDSUBPD", + Summary: "Packed Double-FP Add/Subtract", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VADDSUBPS", + Summary: "Packed Single-FP Add/Subtract", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VAESDEC", + Summary: "Perform One Round of an AES Decryption Flow", + Forms: []Form{ + { + ISA: []string{"AES", "AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AES", "AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VAESDECLAST", + Summary: "Perform Last Round of an AES Decryption Flow", + Forms: []Form{ + { + ISA: []string{"AES", "AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AES", "AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VAESENC", + Summary: "Perform One Round of an AES Encryption Flow", + Forms: []Form{ + { + ISA: []string{"AES", "AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AES", "AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VAESENCLAST", + Summary: "Perform Last Round of an AES Encryption Flow", + Forms: []Form{ + { + ISA: []string{"AES", "AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AES", "AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VAESIMC", + Summary: "Perform the AES InvMixColumn Transformation", + Forms: []Form{ + { + ISA: []string{"AES", "AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AES", "AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VAESKEYGENASSIST", + Summary: "AES Round Key Generation Assist", + Forms: []Form{ + { + ISA: []string{"AES", "AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AES", "AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VALIGND", + Summary: "Align Doubleword Vectors", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VALIGNQ", + Summary: "Align Quadword Vectors", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VANDNPD", + Summary: "Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "VANDNPS", + Summary: "Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "VANDPD", + Summary: "Bitwise Logical AND of Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VANDPS", + Summary: "Bitwise Logical AND of Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VBLENDMPD", + Summary: "Blend Packed Double-Precision Floating-Point Vectors Using an OpMask Control", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VBLENDMPS", + Summary: "Blend Packed Single-Precision Floating-Point Vectors Using an OpMask Control", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VBLENDPD", + Summary: "Blend Packed Double Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VBLENDPS", + Summary: " Blend Packed Single Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VBLENDVPD", + Summary: " Variable Blend Packed Double Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VBLENDVPS", + Summary: " Variable Blend Packed Single Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VBROADCASTF128", + Summary: "Broadcast 128 Bit of Floating-Point Data", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VBROADCASTF32X2", + Summary: "Broadcast Two Single-Precision Floating-Point Elements", + Forms: []Form{ + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VBROADCASTF32X4", + Summary: "Broadcast Four Single-Precision Floating-Point Elements", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VBROADCASTF32X8", + Summary: "Broadcast Eight Single-Precision Floating-Point Elements", + Forms: []Form{ + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VBROADCASTF64X2", + Summary: "Broadcast Two Double-Precision Floating-Point Elements", + Forms: []Form{ + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VBROADCASTF64X4", + Summary: "Broadcast Four Double-Precision Floating-Point Elements", + Forms: []Form{ + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VBROADCASTI128", + Summary: "Broadcast 128 Bits of Integer Data", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VBROADCASTI32X2", + Summary: "Broadcast Two Doubleword Elements", + Forms: []Form{ + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VBROADCASTI32X4", + Summary: "Broadcast Four Doubleword Elements", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VBROADCASTI32X8", + Summary: "Broadcast Eight Doubleword Elements", + Forms: []Form{ + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VBROADCASTI64X2", + Summary: "Broadcast Two Quadword Elements", + Forms: []Form{ + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VBROADCASTI64X4", + Summary: "Broadcast Four Quadword Elements", + Forms: []Form{ + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VBROADCASTSD", + Summary: "Broadcast Double-Precision Floating-Point Element", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VBROADCASTSS", + Summary: "Broadcast Single-Precision Floating-Point Element", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VCMPPD", + Summary: "Compare Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VCMPPS", + Summary: "Compare Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VCMPSD", + Summary: "Compare Scalar Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VCMPSS", + Summary: "Compare Scalar Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VCOMISD", + Summary: "Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VCOMISS", + Summary: "Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VCOMPRESSPD", + Summary: "Store Sparse Packed Double-Precision Floating-Point Values into Dense Memory/Register", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m512", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m512", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m512", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VCOMPRESSPS", + Summary: "Store Sparse Packed Single-Precision Floating-Point Values into Dense Memory/Register", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m512", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m512", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m512", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VCVTDQ2PD", + Summary: "Convert Packed Dword Integers to Packed Double-Precision FP Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VCVTDQ2PS", + Summary: "Convert Packed Dword Integers to Packed Single-Precision FP Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VCVTPD2DQ", + Summary: "Convert Packed Double-Precision FP Values to Packed Dword Integers", + Forms: []Form{ + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VCVTPD2DQX", + Summary: "Convert Packed Double-Precision FP Values to Packed Dword Integers", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + }, + }, + { + Opcode: "VCVTPD2DQY", + Summary: "Convert Packed Double-Precision FP Values to Packed Dword Integers", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + }, + }, + { + Opcode: "VCVTPD2PS", + Summary: "Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values", + Forms: []Form{ + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VCVTPD2PSX", + Summary: "Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + }, + }, + { + Opcode: "VCVTPD2PSY", + Summary: "Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + }, + }, + { + Opcode: "VCVTPD2QQ", + Summary: "Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers", + Forms: []Form{ + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VCVTPD2UDQ", + Summary: "Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers", + Forms: []Form{ + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VCVTPD2UDQX", + Summary: "Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VCVTPD2UDQY", + Summary: "Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VCVTPD2UQQ", + Summary: "Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers", + Forms: []Form{ + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VCVTPH2PS", + Summary: "Convert Half-Precision FP Values to Single-Precision FP Values", + Forms: []Form{ + { + ISA: []string{"F16C"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"F16C"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"F16C"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"F16C"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VCVTPS2DQ", + Summary: "Convert Packed Single-Precision FP Values to Packed Dword Integers", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VCVTPS2PD", + Summary: "Convert Packed Single-Precision FP Values to Packed Double-Precision FP Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + }, + }, + { + Opcode: "VCVTPS2PH", + Summary: "Convert Single-Precision FP value to Half-Precision FP value", + Forms: []Form{ + { + ISA: []string{"F16C"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"F16C"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"F16C"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"F16C"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VCVTPS2QQ", + Summary: "Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values", + Forms: []Form{ + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VCVTPS2UDQ", + Summary: "Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VCVTPS2UQQ", + Summary: "Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values", + Forms: []Form{ + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VCVTQQ2PD", + Summary: "Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VCVTQQ2PS", + Summary: "Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VCVTQQ2PSX", + Summary: "Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VCVTQQ2PSY", + Summary: "Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VCVTSD2SI", + Summary: "Convert Scalar Double-Precision FP Value to Integer", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VCVTSD2SIQ", + Summary: "Convert Scalar Double-Precision FP Value to Integer", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VCVTSD2SS", + Summary: "Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VCVTSD2USIL", + Summary: "Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer", + Forms: []Form{ + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VCVTSD2USIQ", + Summary: "Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer", + Forms: []Form{ + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VCVTSI2SDL", + Summary: "Convert Dword Integer to Scalar Double-Precision FP Value", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VCVTSI2SDQ", + Summary: "Convert Dword Integer to Scalar Double-Precision FP Value", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VCVTSI2SSL", + Summary: "Convert Dword Integer to Scalar Single-Precision FP Value", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VCVTSI2SSQ", + Summary: "Convert Dword Integer to Scalar Single-Precision FP Value", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VCVTSS2SD", + Summary: "Convert Scalar Single-Precision FP Value to Scalar Double-Precision FP Value", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VCVTSS2SI", + Summary: "Convert Scalar Single-Precision FP Value to Dword Integer", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VCVTSS2SIQ", + Summary: "Convert Scalar Single-Precision FP Value to Dword Integer", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VCVTSS2USIL", + Summary: "Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer", + Forms: []Form{ + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VCVTSS2USIQ", + Summary: "Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer", + Forms: []Form{ + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VCVTTPD2DQ", + Summary: "Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers", + Forms: []Form{ + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VCVTTPD2DQX", + Summary: "Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + }, + }, + { + Opcode: "VCVTTPD2DQY", + Summary: "Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + }, + }, + { + Opcode: "VCVTTPD2QQ", + Summary: "Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers", + Forms: []Form{ + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VCVTTPD2UDQ", + Summary: "Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers", + Forms: []Form{ + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VCVTTPD2UDQX", + Summary: "Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VCVTTPD2UDQY", + Summary: "Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VCVTTPD2UQQ", + Summary: "Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers", + Forms: []Form{ + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VCVTTPS2DQ", + Summary: "Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VCVTTPS2QQ", + Summary: "Convert with Truncation Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values", + Forms: []Form{ + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VCVTTPS2UDQ", + Summary: "Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VCVTTPS2UQQ", + Summary: "Convert with Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values", + Forms: []Form{ + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VCVTTSD2SI", + Summary: "Convert with Truncation Scalar Double-Precision FP Value to Signed Integer", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VCVTTSD2SIQ", + Summary: "Convert with Truncation Scalar Double-Precision FP Value to Signed Integer", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VCVTTSD2USIL", + Summary: "Convert with Truncation Scalar Double-Precision Floating-Point Value to Unsigned Integer", + Forms: []Form{ + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VCVTTSD2USIQ", + Summary: "Convert with Truncation Scalar Double-Precision Floating-Point Value to Unsigned Integer", + Forms: []Form{ + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VCVTTSS2SI", + Summary: "Convert with Truncation Scalar Single-Precision FP Value to Dword Integer", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VCVTTSS2SIQ", + Summary: "Convert with Truncation Scalar Single-Precision FP Value to Dword Integer", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VCVTTSS2USIL", + Summary: "Convert with Truncation Scalar Single-Precision Floating-Point Value to Unsigned Integer", + Forms: []Form{ + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VCVTTSS2USIQ", + Summary: "Convert with Truncation Scalar Single-Precision Floating-Point Value to Unsigned Integer", + Forms: []Form{ + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VCVTUDQ2PD", + Summary: "Convert Packed Unsigned Doubleword Integers to Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VCVTUDQ2PS", + Summary: "Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VCVTUQQ2PD", + Summary: "Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VCVTUQQ2PS", + Summary: "Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VCVTUQQ2PSX", + Summary: "Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VCVTUQQ2PSY", + Summary: "Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VCVTUSI2SDL", + Summary: "Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value", + Forms: []Form{ + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VCVTUSI2SDQ", + Summary: "Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value", + Forms: []Form{ + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VCVTUSI2SSL", + Summary: "Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value", + Forms: []Form{ + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VCVTUSI2SSQ", + Summary: "Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value", + Forms: []Form{ + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VDBPSADBW", + Summary: "Double Block Packed Sum-Absolute-Differences on Unsigned Bytes", + Forms: []Form{ + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VDIVPD", + Summary: "Divide Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VDIVPS", + Summary: "Divide Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VDIVSD", + Summary: "Divide Scalar Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VDIVSS", + Summary: "Divide Scalar Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VDPPD", + Summary: "Dot Product of Packed Double Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VDPPS", + Summary: "Dot Product of Packed Single Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VEXP2PD", + Summary: "Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point Values with Less Than 2^-23 Relative Error", + Forms: []Form{ + { + ISA: []string{"AVX512ER"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512ER"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512ER"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512ER"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512ER"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512ER"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512ER"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512ER"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512ER"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512ER"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512ER"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512ER"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VEXP2PS", + Summary: "Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point Values with Less Than 2^-23 Relative Error", + Forms: []Form{ + { + ISA: []string{"AVX512ER"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512ER"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512ER"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512ER"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512ER"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512ER"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512ER"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512ER"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512ER"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512ER"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512ER"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512ER"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VEXPANDPD", + Summary: "Load Sparse Packed Double-Precision Floating-Point Values from Dense Memory", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VEXPANDPS", + Summary: "Load Sparse Packed Single-Precision Floating-Point Values from Dense Memory", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VEXTRACTF128", + Summary: "Extract Packed Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VEXTRACTF32X4", + Summary: "Extract 128 Bits of Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VEXTRACTF32X8", + Summary: "Extract 256 Bits of Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VEXTRACTF64X2", + Summary: "Extract 128 Bits of Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VEXTRACTF64X4", + Summary: "Extract 256 Bits of Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VEXTRACTI128", + Summary: "Extract Packed Integer Values", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VEXTRACTI32X4", + Summary: "Extract 128 Bits of Packed Doubleword Integer Values", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VEXTRACTI32X8", + Summary: "Extract 256 Bits of Packed Doubleword Integer Values", + Forms: []Form{ + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VEXTRACTI64X2", + Summary: "Extract 128 Bits of Packed Quadword Integer Values", + Forms: []Form{ + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VEXTRACTI64X4", + Summary: "Extract 256 Bits of Packed Quadword Integer Values", + Forms: []Form{ + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VEXTRACTPS", + Summary: "Extract Packed Single Precision Floating-Point Value", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VFIXUPIMMPD", + Summary: "Fix Up Special Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VFIXUPIMMPS", + Summary: "Fix Up Special Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VFIXUPIMMSD", + Summary: "Fix Up Special Scalar Double-Precision Floating-Point Value", + Forms: []Form{ + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VFIXUPIMMSS", + Summary: "Fix Up Special Scalar Single-Precision Floating-Point Value", + Forms: []Form{ + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VFMADD132PD", + Summary: "Fused Multiply-Add of Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMADD132PS", + Summary: "Fused Multiply-Add of Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMADD132SD", + Summary: "Fused Multiply-Add of Scalar Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMADD132SS", + Summary: "Fused Multiply-Add of Scalar Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMADD213PD", + Summary: "Fused Multiply-Add of Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMADD213PS", + Summary: "Fused Multiply-Add of Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMADD213SD", + Summary: "Fused Multiply-Add of Scalar Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMADD213SS", + Summary: "Fused Multiply-Add of Scalar Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMADD231PD", + Summary: "Fused Multiply-Add of Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMADD231PS", + Summary: "Fused Multiply-Add of Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMADD231SD", + Summary: "Fused Multiply-Add of Scalar Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMADD231SS", + Summary: "Fused Multiply-Add of Scalar Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMADDSUB132PD", + Summary: "Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMADDSUB132PS", + Summary: "Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMADDSUB213PD", + Summary: "Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMADDSUB213PS", + Summary: "Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMADDSUB231PD", + Summary: "Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMADDSUB231PS", + Summary: "Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMSUB132PD", + Summary: "Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMSUB132PS", + Summary: "Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMSUB132SD", + Summary: "Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMSUB132SS", + Summary: "Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMSUB213PD", + Summary: "Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMSUB213PS", + Summary: "Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMSUB213SD", + Summary: "Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMSUB213SS", + Summary: "Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMSUB231PD", + Summary: "Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMSUB231PS", + Summary: "Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMSUB231SD", + Summary: "Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMSUB231SS", + Summary: "Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMSUBADD132PD", + Summary: "Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMSUBADD132PS", + Summary: "Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMSUBADD213PD", + Summary: "Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMSUBADD213PS", + Summary: "Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMSUBADD231PD", + Summary: "Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFMSUBADD231PS", + Summary: "Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFNMADD132PD", + Summary: "Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFNMADD132PS", + Summary: "Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFNMADD132SD", + Summary: "Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFNMADD132SS", + Summary: "Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFNMADD213PD", + Summary: "Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFNMADD213PS", + Summary: "Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFNMADD213SD", + Summary: "Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFNMADD213SS", + Summary: "Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFNMADD231PD", + Summary: "Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFNMADD231PS", + Summary: "Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFNMADD231SD", + Summary: "Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFNMADD231SS", + Summary: "Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFNMSUB132PD", + Summary: "Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFNMSUB132PS", + Summary: "Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFNMSUB132SD", + Summary: "Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFNMSUB132SS", + Summary: "Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFNMSUB213PD", + Summary: "Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFNMSUB213PS", + Summary: "Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFNMSUB213SD", + Summary: "Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFNMSUB213SS", + Summary: "Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFNMSUB231PD", + Summary: "Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFNMSUB231PS", + Summary: "Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFNMSUB231SD", + Summary: "Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFNMSUB231SS", + Summary: "Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"FMA3"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VFPCLASSPDX", + Summary: "Test Class of Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VFPCLASSPDY", + Summary: "Test Class of Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VFPCLASSPDZ", + Summary: "Test Class of Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VFPCLASSPSX", + Summary: "Test Class of Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VFPCLASSPSY", + Summary: "Test Class of Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VFPCLASSPSZ", + Summary: "Test Class of Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VFPCLASSSD", + Summary: "Test Class of Scalar Double-Precision Floating-Point Value", + Forms: []Form{ + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VFPCLASSSS", + Summary: "Test Class of Scalar Single-Precision Floating-Point Value", + Forms: []Form{ + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VGATHERDPD", + Summary: "Gather Packed Double-Precision Floating-Point Values Using Signed Doubleword Indices", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x3}, + {Type: "vm32x", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x3}, + {Type: "vm32x", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "vm32x", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "vm32x", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "vm32y", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VGATHERDPS", + Summary: "Gather Packed Single-Precision Floating-Point Values Using Signed Doubleword Indices", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x3}, + {Type: "vm32x", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x3}, + {Type: "vm32y", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "vm32x", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "vm32y", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "vm32z", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VGATHERQPD", + Summary: "Gather Packed Double-Precision Floating-Point Values Using Signed Quadword Indices", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x3}, + {Type: "vm64x", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x3}, + {Type: "vm64y", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "vm64x", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "vm64y", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "vm64z", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VGATHERQPS", + Summary: "Gather Packed Single-Precision Floating-Point Values Using Signed Quadword Indices", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x3}, + {Type: "vm64x", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x3}, + {Type: "vm64y", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "vm64x", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "vm64y", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "vm64z", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VGETEXPPD", + Summary: "Extract Exponents of Packed Double-Precision Floating-Point Values as Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VGETEXPPS", + Summary: "Extract Exponents of Packed Single-Precision Floating-Point Values as Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VGETEXPSD", + Summary: "Extract Exponent of Scalar Double-Precision Floating-Point Value as Double-Precision Floating-Point Value", + Forms: []Form{ + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VGETEXPSS", + Summary: "Extract Exponent of Scalar Single-Precision Floating-Point Value as Single-Precision Floating-Point Value", + Forms: []Form{ + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VGETMANTPD", + Summary: "Extract Normalized Mantissas from Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VGETMANTPS", + Summary: "Extract Normalized Mantissas from Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VGETMANTSD", + Summary: "Extract Normalized Mantissa from Scalar Double-Precision Floating-Point Value", + Forms: []Form{ + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VGETMANTSS", + Summary: "Extract Normalized Mantissa from Scalar Single-Precision Floating-Point Value", + Forms: []Form{ + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VHADDPD", + Summary: "Packed Double-FP Horizontal Add", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VHADDPS", + Summary: "Packed Single-FP Horizontal Add", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VHSUBPD", + Summary: "Packed Double-FP Horizontal Subtract", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VHSUBPS", + Summary: "Packed Single-FP Horizontal Subtract", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VINSERTF128", + Summary: "Insert Packed Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VINSERTF32X4", + Summary: "Insert 128 Bits of Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VINSERTF32X8", + Summary: "Insert 256 Bits of Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VINSERTF64X2", + Summary: "Insert 128 Bits of Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VINSERTF64X4", + Summary: "Insert 256 Bits of Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VINSERTI128", + Summary: "Insert Packed Integer Values", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VINSERTI32X4", + Summary: "Insert 128 Bits of Packed Doubleword Integer Values", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VINSERTI32X8", + Summary: "Insert 256 Bits of Packed Doubleword Integer Values", + Forms: []Form{ + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VINSERTI64X2", + Summary: "Insert 128 Bits of Packed Quadword Integer Values", + Forms: []Form{ + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VINSERTI64X4", + Summary: "Insert 256 Bits of Packed Quadword Integer Values", + Forms: []Form{ + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VINSERTPS", + Summary: "Insert Packed Single Precision Floating-Point Value", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VLDDQU", + Summary: "Load Unaligned Integer 128 Bits", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VLDMXCSR", + Summary: "Load MXCSR Register", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VMASKMOVDQU", + Summary: "Store Selected Bytes of Double Quadword", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + }, + ImplicitOperands: []ImplicitOperand{ + {Register: "rdi", Action: 0x1}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VMASKMOVPD", + Summary: "Conditional Move Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VMASKMOVPS", + Summary: "Conditional Move Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VMAXPD", + Summary: "Return Maximum Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VMAXPS", + Summary: "Return Maximum Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VMAXSD", + Summary: "Return Maximum Scalar Double-Precision Floating-Point Value", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VMAXSS", + Summary: "Return Maximum Scalar Single-Precision Floating-Point Value", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VMINPD", + Summary: "Return Minimum Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VMINPS", + Summary: "Return Minimum Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VMINSD", + Summary: "Return Minimum Scalar Double-Precision Floating-Point Value", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VMINSS", + Summary: "Return Minimum Scalar Single-Precision Floating-Point Value", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + }, + }, + { + Opcode: "VMOVAPD", + Summary: "Move Aligned Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m512", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m512", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m512", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VMOVAPS", + Summary: "Move Aligned Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m512", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m512", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m512", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VMOVD", + Summary: "Move Doubleword", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VMOVDDUP", + Summary: "Move One Double-FP and Duplicate", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VMOVDQA", + Summary: "Move Aligned Double Quadword", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VMOVDQA32", + Summary: "Move Aligned Doubleword Values", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m512", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m512", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m512", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VMOVDQA64", + Summary: "Move Aligned Quadword Values", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m512", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m512", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m512", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VMOVDQU", + Summary: "Move Unaligned Double Quadword", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VMOVDQU16", + Summary: "Move Unaligned Word Values", + Forms: []Form{ + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m512", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m512", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m512", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VMOVDQU32", + Summary: "Move Unaligned Doubleword Values", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m512", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m512", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m512", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VMOVDQU64", + Summary: "Move Unaligned Quadword Values", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m512", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m512", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m512", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VMOVDQU8", + Summary: "Move Unaligned Byte Values", + Forms: []Form{ + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m512", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m512", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m512", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VMOVHLPS", + Summary: "Move Packed Single-Precision Floating-Point Values High to Low", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VMOVHPD", + Summary: "Move High Packed Double-Precision Floating-Point Value", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VMOVHPS", + Summary: "Move High Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VMOVLHPS", + Summary: "Move Packed Single-Precision Floating-Point Values Low to High", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VMOVLPD", + Summary: "Move Low Packed Double-Precision Floating-Point Value", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VMOVLPS", + Summary: "Move Low Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VMOVMSKPD", + Summary: "Extract Packed Double-Precision Floating-Point Sign Mask", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VMOVMSKPS", + Summary: "Extract Packed Single-Precision Floating-Point Sign Mask", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VMOVNTDQ", + Summary: "Store Double Quadword Using Non-Temporal Hint", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m512", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VMOVNTDQA", + Summary: "Load Double Quadword Non-Temporal Aligned Hint", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VMOVNTPD", + Summary: "Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m512", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VMOVNTPS", + Summary: "Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m512", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VMOVQ", + Summary: "Move Quadword", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VMOVSD", + Summary: "Move Scalar Double-Precision Floating-Point Value", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + }, + }, + { + Opcode: "VMOVSHDUP", + Summary: "Move Packed Single-FP High and Duplicate", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VMOVSLDUP", + Summary: "Move Packed Single-FP Low and Duplicate", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VMOVSS", + Summary: "Move Scalar Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m32", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + }, + }, + { + Opcode: "VMOVUPD", + Summary: "Move Unaligned Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m512", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m512", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m512", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VMOVUPS", + Summary: "Move Unaligned Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m512", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m512", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m512", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VMPSADBW", + Summary: "Compute Multiple Packed Sums of Absolute Difference", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VMULPD", + Summary: "Multiply Packed Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VMULPS", + Summary: "Multiply Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VMULSD", + Summary: "Multiply Scalar Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VMULSS", + Summary: "Multiply Scalar Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + }, + }, + { + Opcode: "VORPD", + Summary: "Bitwise Logical OR of Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VORPS", + Summary: "Bitwise Logical OR of Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPABSB", + Summary: "Packed Absolute Value of Byte Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPABSD", + Summary: "Packed Absolute Value of Doubleword Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPABSQ", + Summary: "Packed Absolute Value of Quadword Integers", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPABSW", + Summary: "Packed Absolute Value of Word Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPACKSSDW", + Summary: "Pack Doublewords into Words with Signed Saturation", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPACKSSWB", + Summary: "Pack Words into Bytes with Signed Saturation", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPACKUSDW", + Summary: "Pack Doublewords into Words with Unsigned Saturation", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPACKUSWB", + Summary: "Pack Words into Bytes with Unsigned Saturation", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPADDB", + Summary: "Add Packed Byte Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPADDD", + Summary: "Add Packed Doubleword Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPADDQ", + Summary: "Add Packed Quadword Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPADDSB", + Summary: "Add Packed Signed Byte Integers with Signed Saturation", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPADDSW", + Summary: "Add Packed Signed Word Integers with Signed Saturation", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPADDUSB", + Summary: "Add Packed Unsigned Byte Integers with Unsigned Saturation", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPADDUSW", + Summary: "Add Packed Unsigned Word Integers with Unsigned Saturation", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPADDW", + Summary: "Add Packed Word Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPALIGNR", + Summary: "Packed Align Right", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPAND", + Summary: "Packed Bitwise Logical AND", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VPANDD", + Summary: "Bitwise Logical AND of Packed Doubleword Integers", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPANDN", + Summary: "Packed Bitwise Logical AND NOT", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "VPANDND", + Summary: "Bitwise Logical AND NOT of Packed Doubleword Integers", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPANDNQ", + Summary: "Bitwise Logical AND NOT of Packed Quadword Integers", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPANDQ", + Summary: "Bitwise Logical AND of Packed Quadword Integers", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPAVGB", + Summary: "Average Packed Byte Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPAVGW", + Summary: "Average Packed Word Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPBLENDD", + Summary: "Blend Packed Doublewords", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VPBLENDMB", + Summary: "Blend Byte Vectors Using an OpMask Control", + Forms: []Form{ + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPBLENDMD", + Summary: "Blend Doubleword Vectors Using an OpMask Control", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPBLENDMQ", + Summary: "Blend Quadword Vectors Using an OpMask Control", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPBLENDMW", + Summary: "Blend Word Vectors Using an OpMask Control", + Forms: []Form{ + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPBLENDVB", + Summary: "Variable Blend Packed Bytes", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VPBLENDW", + Summary: "Blend Packed Words", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VPBROADCASTB", + Summary: "Broadcast Byte Integer", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m8", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m8", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m8", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m8", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m8", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m8", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m8", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m8", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m8", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPBROADCASTD", + Summary: "Broadcast Doubleword Integer", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPBROADCASTMB2Q", + Summary: "Broadcast Low Byte of Mask Register to Packed Quadword Values", + Forms: []Form{ + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPBROADCASTMW2D", + Summary: "Broadcast Low Word of Mask Register to Packed Doubleword Values", + Forms: []Form{ + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPBROADCASTQ", + Summary: "Broadcast Quadword Integer", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "r64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPBROADCASTW", + Summary: "Broadcast Word Integer", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m16", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m16", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m16", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m16", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m16", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m16", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m16", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m16", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m16", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "r32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPCLMULQDQ", + Summary: "Carry-Less Quadword Multiplication", + Forms: []Form{ + { + ISA: []string{"AVX", "PCLMULQDQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX", "PCLMULQDQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VPCMPB", + Summary: "Compare Packed Signed Byte Values", + Forms: []Form{ + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPCMPD", + Summary: "Compare Packed Signed Doubleword Values", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPCMPEQB", + Summary: "Compare Packed Byte Data for Equality", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "VPCMPEQD", + Summary: "Compare Packed Doubleword Data for Equality", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "VPCMPEQQ", + Summary: "Compare Packed Quadword Data for Equality", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "VPCMPEQW", + Summary: "Compare Packed Word Data for Equality", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "VPCMPESTRI", + Summary: "Packed Compare Explicit Length Strings, Return Index", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + }, + ImplicitOperands: []ImplicitOperand{ + {Register: "eax", Action: 0x1}, + {Register: "ecx", Action: 0x2}, + {Register: "edx", Action: 0x1}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + }, + ImplicitOperands: []ImplicitOperand{ + {Register: "eax", Action: 0x1}, + {Register: "ecx", Action: 0x2}, + {Register: "edx", Action: 0x1}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VPCMPESTRM", + Summary: "Packed Compare Explicit Length Strings, Return Mask", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + }, + ImplicitOperands: []ImplicitOperand{ + {Register: "eax", Action: 0x1}, + {Register: "edx", Action: 0x1}, + {Register: "xmm0", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + }, + ImplicitOperands: []ImplicitOperand{ + {Register: "eax", Action: 0x1}, + {Register: "edx", Action: 0x1}, + {Register: "xmm0", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VPCMPGTB", + Summary: "Compare Packed Signed Byte Integers for Greater Than", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "VPCMPGTD", + Summary: "Compare Packed Signed Doubleword Integers for Greater Than", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "VPCMPGTQ", + Summary: "Compare Packed Data for Greater Than", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "VPCMPGTW", + Summary: "Compare Packed Signed Word Integers for Greater Than", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "VPCMPISTRI", + Summary: "Packed Compare Implicit Length Strings, Return Index", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + }, + ImplicitOperands: []ImplicitOperand{ + {Register: "ecx", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + }, + ImplicitOperands: []ImplicitOperand{ + {Register: "ecx", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VPCMPISTRM", + Summary: "Packed Compare Implicit Length Strings, Return Mask", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + }, + ImplicitOperands: []ImplicitOperand{ + {Register: "xmm0", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + }, + ImplicitOperands: []ImplicitOperand{ + {Register: "xmm0", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VPCMPQ", + Summary: "Compare Packed Signed Quadword Values", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPCMPUB", + Summary: "Compare Packed Unsigned Byte Values", + Forms: []Form{ + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPCMPUD", + Summary: "Compare Packed Unsigned Doubleword Values", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPCMPUQ", + Summary: "Compare Packed Unsigned Quadword Values", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPCMPUW", + Summary: "Compare Packed Unsigned Word Values", + Forms: []Form{ + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPCMPW", + Summary: "Compare Packed Signed Word Values", + Forms: []Form{ + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPCOMPRESSD", + Summary: "Store Sparse Packed Doubleword Integer Values into Dense Memory/Register", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m512", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m512", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m512", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPCOMPRESSQ", + Summary: "Store Sparse Packed Quadword Integer Values into Dense Memory/Register", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m512", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m512", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m512", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPCONFLICTD", + Summary: "Detect Conflicts Within a Vector of Packed Doubleword Values into Dense Memory/Register", + Forms: []Form{ + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPCONFLICTQ", + Summary: "Detect Conflicts Within a Vector of Packed Quadword Values into Dense Memory/Register", + Forms: []Form{ + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPERM2F128", + Summary: "Permute Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VPERM2I128", + Summary: "Permute 128-Bit Integer Values", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VPERMB", + Summary: "Permute Byte Integers", + Forms: []Form{ + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VBMI"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VBMI"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPERMD", + Summary: "Permute Doubleword Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPERMI2B", + Summary: "Full Permute of Bytes From Two Tables Overwriting the Index", + Forms: []Form{ + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VBMI"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VBMI"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPERMI2D", + Summary: "Full Permute of Doublewords From Two Tables Overwriting the Index", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPERMI2PD", + Summary: "Full Permute of Double-Precision Floating-Point Values From Two Tables Overwriting the Index", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPERMI2PS", + Summary: "Full Permute of Single-Precision Floating-Point Values From Two Tables Overwriting the Index", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPERMI2Q", + Summary: "Full Permute of Quadwords From Two Tables Overwriting the Index", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPERMI2W", + Summary: "Full Permute of Words From Two Tables Overwriting the Index", + Forms: []Form{ + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPERMILPD", + Summary: "Permute Double-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPERMILPS", + Summary: "Permute Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPERMPD", + Summary: "Permute Double-Precision Floating-Point Elements", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPERMPS", + Summary: "Permute Single-Precision Floating-Point Elements", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPERMQ", + Summary: "Permute Quadword Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPERMT2B", + Summary: "Full Permute of Bytes From Two Tables Overwriting a Table", + Forms: []Form{ + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VBMI"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VBMI"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPERMT2D", + Summary: "Full Permute of Doublewords From Two Tables Overwriting a Table", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPERMT2PD", + Summary: "Full Permute of Double-Precision Floating-Point Values From Two Tables Overwriting a Table", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPERMT2PS", + Summary: "Full Permute of Single-Precision Floating-Point Values From Two Tables Overwriting a Table", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPERMT2Q", + Summary: "Full Permute of Quadwords From Two Tables Overwriting a Table", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPERMT2W", + Summary: "Full Permute of Words From Two Tables Overwriting a Table", + Forms: []Form{ + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPERMW", + Summary: "Permute Word Integers", + Forms: []Form{ + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPEXPANDD", + Summary: "Load Sparse Packed Doubleword Integer Values from Dense Memory/Register", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPEXPANDQ", + Summary: "Load Sparse Packed Quadword Integer Values from Dense Memory/Register", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPEXTRB", + Summary: "Extract Byte", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "m8", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VPEXTRD", + Summary: "Extract Doubleword", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VPEXTRQ", + Summary: "Extract Quadword", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "r64", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VPEXTRW", + Summary: "Extract Word", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "m16", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VPGATHERDD", + Summary: "Gather Packed Doubleword Values Using Signed Doubleword Indices", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x3}, + {Type: "vm32x", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x3}, + {Type: "vm32y", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "vm32x", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "vm32y", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "vm32z", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPGATHERDQ", + Summary: "Gather Packed Quadword Values Using Signed Doubleword Indices", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x3}, + {Type: "vm32x", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x3}, + {Type: "vm32x", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "vm32x", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "vm32x", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "vm32y", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPGATHERQD", + Summary: "Gather Packed Doubleword Values Using Signed Quadword Indices", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x3}, + {Type: "vm64x", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x3}, + {Type: "vm64y", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "vm64x", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "vm64y", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "vm64z", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPGATHERQQ", + Summary: "Gather Packed Quadword Values Using Signed Quadword Indices", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x3}, + {Type: "vm64x", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x3}, + {Type: "vm64y", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "vm64x", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "vm64y", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "vm64z", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPHADDD", + Summary: "Packed Horizontal Add Doubleword Integer", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VPHADDSW", + Summary: "Packed Horizontal Add Signed Word Integers with Signed Saturation", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VPHADDW", + Summary: "Packed Horizontal Add Word Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VPHMINPOSUW", + Summary: "Packed Horizontal Minimum of Unsigned Word Integers", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VPHSUBD", + Summary: "Packed Horizontal Subtract Doubleword Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "VPHSUBSW", + Summary: "Packed Horizontal Subtract Signed Word Integers with Signed Saturation", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "VPHSUBW", + Summary: "Packed Horizontal Subtract Word Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "VPINSRB", + Summary: "Insert Byte", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m8", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VPINSRD", + Summary: "Insert Doubleword", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VPINSRQ", + Summary: "Insert Quadword", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VPINSRW", + Summary: "Insert Word", + Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m16", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "r32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VPLZCNTD", + Summary: "Count the Number of Leading Zero Bits for Packed Doubleword Values", + Forms: []Form{ + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPLZCNTQ", + Summary: "Count the Number of Leading Zero Bits for Packed Quadword Values", + Forms: []Form{ + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512CD", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512CD"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMADD52HUQ", + Summary: "Packed Multiply of Unsigned 52-bit Unsigned Integers and Add High 52-bit Products to Quadword Accumulators", + Forms: []Form{ + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512IFMA"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512IFMA"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512IFMA"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512IFMA"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512IFMA"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512IFMA"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512IFMA"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512IFMA"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512IFMA"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMADD52LUQ", + Summary: "Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit Products to Quadword Accumulators", + Forms: []Form{ + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512IFMA", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512IFMA"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512IFMA"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512IFMA"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512IFMA"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512IFMA"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512IFMA"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512IFMA"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512IFMA"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512IFMA"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMADDUBSW", + Summary: "Multiply and Add Packed Signed and Unsigned Byte Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMADDWD", + Summary: "Multiply and Add Packed Signed Word Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMASKMOVD", + Summary: "Conditional Move Packed Doubleword Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VPMASKMOVQ", + Summary: "Conditional Move Packed Quadword Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VPMAXSB", + Summary: "Maximum of Packed Signed Byte Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMAXSD", + Summary: "Maximum of Packed Signed Doubleword Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMAXSQ", + Summary: "Maximum of Packed Signed Quadword Integers", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMAXSW", + Summary: "Maximum of Packed Signed Word Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMAXUB", + Summary: "Maximum of Packed Unsigned Byte Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMAXUD", + Summary: "Maximum of Packed Unsigned Doubleword Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMAXUQ", + Summary: "Maximum of Packed Unsigned Quadword Integers", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMAXUW", + Summary: "Maximum of Packed Unsigned Word Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMINSB", + Summary: "Minimum of Packed Signed Byte Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMINSD", + Summary: "Minimum of Packed Signed Doubleword Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMINSQ", + Summary: "Minimum of Packed Signed Quadword Integers", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMINSW", + Summary: "Minimum of Packed Signed Word Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMINUB", + Summary: "Minimum of Packed Unsigned Byte Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMINUD", + Summary: "Minimum of Packed Unsigned Doubleword Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMINUQ", + Summary: "Minimum of Packed Unsigned Quadword Integers", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMINUW", + Summary: "Minimum of Packed Unsigned Word Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVB2M", + Summary: "Move Signs of Packed Byte Integers to Mask Register", + Forms: []Form{ + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVD2M", + Summary: "Move Signs of Packed Doubleword Integers to Mask Register", + Forms: []Form{ + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVDB", + Summary: "Down Convert Packed Doubleword Values to Byte Values with Truncation", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m32", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVDW", + Summary: "Down Convert Packed Doubleword Values to Word Values with Truncation", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVM2B", + Summary: "Expand Bits of Mask Register to Packed Byte Integers", + Forms: []Form{ + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVM2D", + Summary: "Expand Bits of Mask Register to Packed Doubleword Integers", + Forms: []Form{ + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVM2Q", + Summary: "Expand Bits of Mask Register to Packed Quadword Integers", + Forms: []Form{ + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVM2W", + Summary: "Expand Bits of Mask Register to Packed Word Integers", + Forms: []Form{ + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVMSKB", + Summary: "Move Byte Mask", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "r32", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VPMOVQ2M", + Summary: "Move Signs of Packed Quadword Integers to Mask Register", + Forms: []Form{ + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVQB", + Summary: "Down Convert Packed Quadword Values to Byte Values with Truncation", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m16", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m16", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m32", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m32", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVQD", + Summary: "Down Convert Packed Quadword Values to Doubleword Values with Truncation", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVQW", + Summary: "Down Convert Packed Quadword Values to Word Values with Truncation", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m32", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVSDB", + Summary: "Down Convert Packed Doubleword Values to Byte Values with Signed Saturation", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m32", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVSDW", + Summary: "Down Convert Packed Doubleword Values to Word Values with Signed Saturation", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVSQB", + Summary: "Down Convert Packed Quadword Values to Byte Values with Signed Saturation", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m16", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m16", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m32", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m32", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVSQD", + Summary: "Down Convert Packed Quadword Values to Doubleword Values with Signed Saturation", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVSQW", + Summary: "Down Convert Packed Quadword Values to Word Values with Signed Saturation", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m32", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVSWB", + Summary: "Down Convert Packed Word Values to Byte Values with Signed Saturation", + Forms: []Form{ + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVSXBD", + Summary: "Move Packed Byte Integers to Doubleword Integers with Sign Extension", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVSXBQ", + Summary: "Move Packed Byte Integers to Quadword Integers with Sign Extension", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m16", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m16", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m16", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVSXBW", + Summary: "Move Packed Byte Integers to Word Integers with Sign Extension", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVSXDQ", + Summary: "Move Packed Doubleword Integers to Quadword Integers with Sign Extension", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVSXWD", + Summary: "Move Packed Word Integers to Doubleword Integers with Sign Extension", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVSXWQ", + Summary: "Move Packed Word Integers to Quadword Integers with Sign Extension", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVUSDB", + Summary: "Down Convert Packed Doubleword Values to Byte Values with Unsigned Saturation", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m32", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVUSDW", + Summary: "Down Convert Packed Doubleword Values to Word Values with Unsigned Saturation", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVUSQB", + Summary: "Down Convert Packed Quadword Values to Byte Values with Unsigned Saturation", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m16", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m16", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m16", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m32", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m32", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVUSQD", + Summary: "Down Convert Packed Quadword Values to Doubleword Values with Unsigned Saturation", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVUSQW", + Summary: "Down Convert Packed Quadword Values to Word Values with Unsigned Saturation", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m32", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m32", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVUSWB", + Summary: "Down Convert Packed Word Values to Byte Values with Unsigned Saturation", + Forms: []Form{ + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVW2M", + Summary: "Move Signs of Packed Word Integers to Mask Register", + Forms: []Form{ + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVWB", + Summary: "Down Convert Packed Word Values to Byte Values with Truncation", + Forms: []Form{ + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "m128", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "m256", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVZXBD", + Summary: "Move Packed Byte Integers to Doubleword Integers with Zero Extension", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVZXBQ", + Summary: "Move Packed Byte Integers to Quadword Integers with Zero Extension", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m16", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m16", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m16", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVZXBW", + Summary: "Move Packed Byte Integers to Word Integers with Zero Extension", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVZXDQ", + Summary: "Move Packed Doubleword Integers to Quadword Integers with Zero Extension", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVZXWD", + Summary: "Move Packed Word Integers to Doubleword Integers with Zero Extension", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMOVZXWQ", + Summary: "Move Packed Word Integers to Quadword Integers with Zero Extension", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMULDQ", + Summary: "Multiply Packed Signed Doubleword Integers and Store Quadword Result", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMULHRSW", + Summary: "Packed Multiply Signed Word Integers and Store High Result with Round and Scale", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMULHUW", + Summary: "Multiply Packed Unsigned Word Integers and Store High Result", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMULHW", + Summary: "Multiply Packed Signed Word Integers and Store High Result", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMULLD", + Summary: "Multiply Packed Signed Doubleword Integers and Store Low Result", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMULLQ", + Summary: "Multiply Packed Signed Quadword Integers and Store Low Result", + Forms: []Form{ + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMULLW", + Summary: "Multiply Packed Signed Word Integers and Store Low Result", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMULTISHIFTQB", + Summary: "Select Packed Unaligned Bytes from Quadword Sources", + Forms: []Form{ + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VBMI", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VBMI"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VBMI"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512VBMI"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VBMI"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VBMI"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VBMI"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPMULUDQ", + Summary: "Multiply Packed Unsigned Doubleword Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPOPCNTD", + Summary: "Packed Population Count for Doubleword Integers", + Forms: []Form{ + { + ISA: []string{"AVX512VPOPCNTDQ"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VPOPCNTDQ"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512VPOPCNTDQ"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VPOPCNTDQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VPOPCNTDQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VPOPCNTDQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VPOPCNTDQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VPOPCNTDQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VPOPCNTDQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPOPCNTQ", + Summary: "Packed Population Count for Quadword Integers", + Forms: []Form{ + { + ISA: []string{"AVX512VPOPCNTDQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VPOPCNTDQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VPOPCNTDQ"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VPOPCNTDQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VPOPCNTDQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512VPOPCNTDQ"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VPOPCNTDQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VPOPCNTDQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VPOPCNTDQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPOR", + Summary: "Packed Bitwise Logical OR", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VPORD", + Summary: "Bitwise Logical OR of Packed Doubleword Integers", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPORQ", + Summary: "Bitwise Logical OR of Packed Quadword Integers", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPROLD", + Summary: "Rotate Packed Doubleword Left", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPROLQ", + Summary: "Rotate Packed Quadword Left", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPROLVD", + Summary: "Variable Rotate Packed Doubleword Left", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPROLVQ", + Summary: "Variable Rotate Packed Quadword Left", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPRORD", + Summary: "Rotate Packed Doubleword Right", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPRORQ", + Summary: "Rotate Packed Quadword Right", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPRORVD", + Summary: "Variable Rotate Packed Doubleword Right", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPRORVQ", + Summary: "Variable Rotate Packed Quadword Right", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPSADBW", + Summary: "Compute Sum of Absolute Differences", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, + }, + }, + }, + { + Opcode: "VPSCATTERDD", + Summary: "Scatter Packed Doubleword Values with Signed Doubleword Indices", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "vm32x", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "vm32y", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "vm32z", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPSCATTERDQ", + Summary: "Scatter Packed Quadword Values with Signed Doubleword Indices", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "vm32x", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "vm32x", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "vm32y", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPSCATTERQD", + Summary: "Scatter Packed Doubleword Values with Signed Quadword Indices", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "vm64x", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "vm64y", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "vm64z", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPSCATTERQQ", + Summary: "Scatter Packed Quadword Values with Signed Quadword Indices", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "vm64x", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "vm64y", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "vm64z", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPSHUFB", + Summary: "Packed Shuffle Bytes", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPSHUFD", + Summary: "Shuffle Packed Doublewords", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPSHUFHW", + Summary: "Shuffle Packed High Words", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPSHUFLW", + Summary: "Shuffle Packed Low Words", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPSIGNB", + Summary: "Packed Sign of Byte Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VPSIGND", + Summary: "Packed Sign of Doubleword Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VPSIGNW", + Summary: "Packed Sign of Word Integers", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + }, + }, + { + Opcode: "VPSLLD", + Summary: "Shift Packed Doubleword Data Left Logical", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPSLLDQ", + Summary: "Shift Packed Double Quadword Left Logical", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPSLLQ", + Summary: "Shift Packed Quadword Data Left Logical", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPSLLVD", + Summary: "Variable Shift Packed Doubleword Data Left Logical", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPSLLVQ", + Summary: "Variable Shift Packed Quadword Data Left Logical", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPSLLVW", + Summary: "Variable Shift Packed Word Data Left Logical", + Forms: []Form{ + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPSLLW", + Summary: "Shift Packed Word Data Left Logical", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPSRAD", + Summary: "Shift Packed Doubleword Data Right Arithmetic", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPSRAQ", + Summary: "Shift Packed Quadword Data Right Arithmetic", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPSRAVD", + Summary: "Variable Shift Packed Doubleword Data Right Arithmetic", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPSRAVQ", + Summary: "Variable Shift Packed Quadword Data Right Arithmetic", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPSRAVW", + Summary: "Variable Shift Packed Word Data Right Arithmetic", + Forms: []Form{ + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPSRAW", + Summary: "Shift Packed Word Data Right Arithmetic", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPSRLD", + Summary: "Shift Packed Doubleword Data Right Logical", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPSRLDQ", + Summary: "Shift Packed Double Quadword Right Logical", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPSRLQ", + Summary: "Shift Packed Quadword Data Right Logical", + Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "PUNPCKHWL", - Summary: "Unpack and Interleave High-Order Words into Doublewords", - Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "PUNPCKLBW", - Summary: "Unpack and Interleave Low-Order Bytes into Words", - Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "PUNPCKLLQ", - Summary: "Unpack and Interleave Low-Order Doublewords into Quadwords", + Opcode: "VPSRLVD", + Summary: "Variable Shift Packed Doubleword Data Right Logical", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"AVX2"}, Operands: []Operand{ + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"SSE2"}, + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, - }, - }, - { - Opcode: "PUNPCKLQDQ", - Summary: "Unpack and Interleave Low-Order Quadwords into Double Quadwords", - Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"AVX2"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"SSE2"}, + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, - }, - }, - { - Opcode: "PUNPCKLWL", - Summary: "Unpack and Interleave Low-Order Words into Doublewords", - Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "PUSHQ", - Summary: "Push Value Onto the Stack", - Forms: []Form{ { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm32", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, - }, - }, - { - Opcode: "PUSHW", - Summary: "Push Value Onto the Stack", - Forms: []Form{ { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "PXOR", - Summary: "Packed Bitwise Logical Exclusive OR", - Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "RCLB", - Summary: "Rotate Left through Carry Flag", - Forms: []Form{ { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r8", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r8", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r8", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m8", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m8", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m8", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "RCLL", - Summary: "Rotate Left through Carry Flag", - Forms: []Form{ { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r32", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r32", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r32", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m32", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m32", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m32", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "RCLQ", - Summary: "Rotate Left through Carry Flag", + Opcode: "VPSRLVQ", + Summary: "Variable Shift Packed Quadword Data Right Logical", Forms: []Form{ { + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r64", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r64", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r64", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m64", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m64", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m64", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "RCLW", - Summary: "Rotate Left through Carry Flag", - Forms: []Form{ { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r16", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r16", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r16", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m16", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m16", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m16", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "RCPPS", - Summary: "Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"SSE"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"SSE"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "RCPSS", - Summary: "Compute Approximate Reciprocal of Scalar Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"SSE"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"SSE"}, - Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x3}, - }, - }, - }, - }, - { - Opcode: "RCRB", - Summary: "Rotate Right through Carry Flag", - Forms: []Form{ - { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r8", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r8", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r8", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m8", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m8", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m8", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "RCRL", - Summary: "Rotate Right through Carry Flag", - Forms: []Form{ { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r32", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r32", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r32", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m32", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m32", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m32", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "RCRQ", - Summary: "Rotate Right through Carry Flag", + Opcode: "VPSRLVW", + Summary: "Variable Shift Packed Word Data Right Logical", Forms: []Form{ { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r64", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r64", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r64", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m64", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m64", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m64", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "RCRW", - Summary: "Rotate Right through Carry Flag", - Forms: []Form{ { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r16", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r16", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r16", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m16", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m16", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m16", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "RDRANDL", - Summary: "Read Random Number", - Forms: []Form{ { - ISA: []string{"RDRAND"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "r32", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "RDRANDQ", - Summary: "Read Random Number", - Forms: []Form{ { - ISA: []string{"RDRAND"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "r64", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "RDRANDW", - Summary: "Read Random Number", - Forms: []Form{ { - ISA: []string{"RDRAND"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "r16", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "RDSEEDL", - Summary: "Read Random SEED", - Forms: []Form{ { - ISA: []string{"RDSEED"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "r32", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "RDSEEDQ", - Summary: "Read Random SEED", - Forms: []Form{ { - ISA: []string{"RDSEED"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "r64", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "RDSEEDW", - Summary: "Read Random SEED", - Forms: []Form{ { - ISA: []string{"RDSEED"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "r16", Action: 0x2}, - }, - }, - }, - }, - { - Opcode: "RDTSC", - Summary: "Read Time-Stamp Counter", - Forms: []Form{ - { - ISA: []string{"RDTSC"}, - Operands: []Operand{}, - ImplicitOperands: []ImplicitOperand{ - {Register: "eax", Action: 0x2}, - {Register: "edx", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "RDTSCP", - Summary: "Read Time-Stamp Counter and Processor ID", + Opcode: "VPSRLW", + Summary: "Shift Packed Word Data Right Logical", Forms: []Form{ { - ISA: []string{"RDTSCP"}, - Operands: []Operand{}, - ImplicitOperands: []ImplicitOperand{ - {Register: "eax", Action: 0x2}, - {Register: "ecx", Action: 0x2}, - {Register: "edx", Action: 0x2}, + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, - }, - }, - { - Opcode: "RET", - Summary: "Return from Procedure", - Forms: []Form{ - { - Operands: []Operand{}, - }, - }, - }, - { - Opcode: "RETFL", - Summary: "Return from Procedure", - Forms: []Form{ { + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "imm16", Action: 0x0}, - }, - }, - }, - }, - { - Opcode: "RETFQ", - Summary: "Return from Procedure", - Forms: []Form{ + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, { + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "imm16", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, - }, - }, - { - Opcode: "RETFW", - Summary: "Return from Procedure", - Forms: []Form{ { + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "imm16", Action: 0x0}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, - }, - }, - { - Opcode: "ROLB", - Summary: "Rotate Left", - Forms: []Form{ { + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r8", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r8", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r8", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m8", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "m8", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m8", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "ROLL", - Summary: "Rotate Left", - Forms: []Form{ { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r32", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r32", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r32", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m32", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "m32", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m32", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "ROLQ", - Summary: "Rotate Left", - Forms: []Form{ { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r64", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r64", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r64", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m64", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m64", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m64", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "ROLW", - Summary: "Rotate Left", - Forms: []Form{ { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r16", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r16", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r16", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m16", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "m16", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m16", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "RORB", - Summary: "Rotate Right", - Forms: []Form{ { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r8", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r8", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r8", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m8", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m8", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m8", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "RORL", - Summary: "Rotate Right", - Forms: []Form{ { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r32", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r32", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, + }, + }, + { + Opcode: "VPSUBB", + Summary: "Subtract Packed Byte Integers", + Forms: []Form{ { + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r32", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m32", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, + CancellingInputs: true, }, { + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m32", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m32", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, + CancellingInputs: true, }, - }, - }, - { - Opcode: "RORQ", - Summary: "Rotate Right", - Forms: []Form{ { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r64", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r64", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r64", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m64", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m64", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + CancellingInputs: true, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m64", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, }, - }, - }, - { - Opcode: "RORW", - Summary: "Rotate Right", - Forms: []Form{ { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r16", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + CancellingInputs: true, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r16", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r16", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m16", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m16", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m16", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + CancellingInputs: true, }, - }, - }, - { - Opcode: "RORXL", - Summary: "Rotate Right Logical Without Affecting Flags", - Forms: []Form{ { - ISA: []string{"BMI2"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, }, { - ISA: []string{"BMI2"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m32", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, }, }, }, { - Opcode: "RORXQ", - Summary: "Rotate Right Logical Without Affecting Flags", + Opcode: "VPSUBD", + Summary: "Subtract Packed Doubleword Integers", Forms: []Form{ { - ISA: []string{"BMI2"}, + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"BMI2"}, + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m64", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, + CancellingInputs: true, }, - }, - }, - { - Opcode: "ROUNDPD", - Summary: "Round Packed Double Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"SSE4.1"}, + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"SSE4.1"}, + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, + CancellingInputs: true, }, - }, - }, - { - Opcode: "ROUNDPS", - Summary: "Round Packed Single Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"SSE4.1"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"SSE4.1"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "ROUNDSD", - Summary: "Round Scalar Double Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"SSE4.1"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"SSE4.1"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "ROUNDSS", - Summary: "Round Scalar Single Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"SSE4.1"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"SSE4.1"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, - }, - }, - { - Opcode: "RSQRTPS", - Summary: "Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"SSE"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"SSE"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "RSQRTSS", - Summary: "Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value", - Forms: []Form{ { - ISA: []string{"SSE"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"SSE"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + CancellingInputs: true, }, - }, - }, - { - Opcode: "SALB", - Summary: "Arithmetic Shift Left", - Forms: []Form{ { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r8", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r8", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + CancellingInputs: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r8", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m8", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m8", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m8", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "SALL", - Summary: "Arithmetic Shift Left", - Forms: []Form{ { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r32", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r32", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r32", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m32", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + CancellingInputs: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m32", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m32", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, }, }, }, { - Opcode: "SALQ", - Summary: "Arithmetic Shift Left", + Opcode: "VPSUBQ", + Summary: "Subtract Packed Quadword Integers", Forms: []Form{ { + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r64", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r64", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r64", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m64", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m64", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m64", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "SALW", - Summary: "Arithmetic Shift Left", - Forms: []Form{ { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r16", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r16", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r16", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m16", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m16", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m16", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + CancellingInputs: true, }, - }, - }, - { - Opcode: "SARB", - Summary: "Arithmetic Shift Right", - Forms: []Form{ { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r8", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r8", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + CancellingInputs: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r8", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m8", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m8", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m8", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "SARL", - Summary: "Arithmetic Shift Right", - Forms: []Form{ { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r32", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r32", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r32", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m32", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + CancellingInputs: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m32", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m32", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, }, }, }, { - Opcode: "SARQ", - Summary: "Arithmetic Shift Right", + Opcode: "VPSUBSB", + Summary: "Subtract Packed Signed Byte Integers with Signed Saturation", Forms: []Form{ { + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r64", Action: 0x3}, - }, - }, - { - Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r64", Action: 0x3}, - }, - }, - { - Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r64", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m64", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, + CancellingInputs: true, }, { + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m64", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m64", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, + CancellingInputs: true, }, - }, - }, - { - Opcode: "SARW", - Summary: "Arithmetic Shift Right", - Forms: []Form{ { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r16", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r16", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r16", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m16", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m16", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + CancellingInputs: true, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m16", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, }, - }, - }, - { - Opcode: "SARXL", - Summary: "Arithmetic Shift Right Without Affecting Flags", - Forms: []Form{ { - ISA: []string{"BMI2"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + CancellingInputs: true, }, { - ISA: []string{"BMI2"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "m32", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, }, - }, - }, - { - Opcode: "SARXQ", - Summary: "Arithmetic Shift Right Without Affecting Flags", - Forms: []Form{ { - ISA: []string{"BMI2"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"BMI2"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "m64", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "SBBB", - Summary: "Subtract with Borrow", - Forms: []Form{ { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "al", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r8", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + CancellingInputs: true, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "r8", Action: 0x1}, - {Type: "r8", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, CancellingInputs: true, + Zeroing: true, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "m8", Action: 0x1}, - {Type: "r8", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, }, + }, + }, + { + Opcode: "VPSUBSW", + Summary: "Subtract Packed Signed Word Integers with Signed Saturation", + Forms: []Form{ { + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m8", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "r8", Action: 0x1}, - {Type: "m8", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, + CancellingInputs: true, }, - }, - }, - { - Opcode: "SBBL", - Summary: "Subtract with Borrow", - Forms: []Form{ { + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "eax", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r32", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, + CancellingInputs: true, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "r32", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "r32", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m32", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "m32", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + CancellingInputs: true, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "m32", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, }, - }, - }, - { - Opcode: "SBBQ", - Summary: "Subtract with Borrow", - Forms: []Form{ { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "rax", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + CancellingInputs: true, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r64", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "r64", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "r64", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m64", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + CancellingInputs: true, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "m64", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "m64", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, }, }, }, { - Opcode: "SBBW", - Summary: "Subtract with Borrow", + Opcode: "VPSUBUSB", + Summary: "Subtract Packed Unsigned Byte Integers with Unsigned Saturation", Forms: []Form{ { + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "imm16", Action: 0x0}, - {Type: "ax", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r16", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, + CancellingInputs: true, }, { + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "imm16", Action: 0x0}, - {Type: "r16", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, - {Type: "r16", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, CancellingInputs: true, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, - {Type: "r16", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m16", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm16", Action: 0x0}, - {Type: "m16", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, - {Type: "m16", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "SETCC", - Summary: "Set byte if above or equal (CF == 0)", - Forms: []Form{ { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "r8", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + CancellingInputs: true, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "m8", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, }, - }, - }, - { - Opcode: "SETCS", - Summary: "Set byte if below (CF == 1)", - Forms: []Form{ { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "r8", Action: 0x2}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + CancellingInputs: true, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "m8", Action: 0x2}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, }, - }, - }, - { - Opcode: "SETEQ", - Summary: "Set byte if equal (ZF == 1)", - Forms: []Form{ { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "r8", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "m8", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "SETGE", - Summary: "Set byte if greater or equal (SF == OF)", - Forms: []Form{ { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "r8", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "m8", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + CancellingInputs: true, }, - }, - }, - { - Opcode: "SETGT", - Summary: "Set byte if greater (ZF == 0 and SF == OF)", - Forms: []Form{ { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "r8", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "m8", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, }, }, }, { - Opcode: "SETHI", - Summary: "Set byte if above (CF == 0 and ZF == 0)", + Opcode: "VPSUBUSW", + Summary: "Subtract Packed Unsigned Word Integers with Unsigned Saturation", Forms: []Form{ { + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "r8", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "m8", Action: 0x2}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, + CancellingInputs: true, }, - }, - }, - { - Opcode: "SETLE", - Summary: "Set byte if less or equal (ZF == 1 or SF != OF)", - Forms: []Form{ { + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "r8", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m8", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, + CancellingInputs: true, }, - }, - }, - { - Opcode: "SETLS", - Summary: "Set byte if below or equal (CF == 1 or ZF == 1)", - Forms: []Form{ { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "r8", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "m8", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "SETLT", - Summary: "Set byte if less (SF != OF)", - Forms: []Form{ { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "r8", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "m8", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "SETMI", - Summary: "Set byte if sign (SF == 1)", - Forms: []Form{ { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "r8", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + CancellingInputs: true, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "m8", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, }, - }, - }, - { - Opcode: "SETNE", - Summary: "Set byte if not equal (ZF == 0)", - Forms: []Form{ { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "r8", Action: 0x2}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + CancellingInputs: true, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "m8", Action: 0x2}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, }, - }, - }, - { - Opcode: "SETOC", - Summary: "Set byte if not overflow (OF == 0)", - Forms: []Form{ { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "r8", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "m8", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "SETOS", - Summary: "Set byte if overflow (OF == 1)", - Forms: []Form{ { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "r8", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "m8", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + CancellingInputs: true, }, - }, - }, - { - Opcode: "SETPC", - Summary: "Set byte if not parity (PF == 0)", - Forms: []Form{ { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "r8", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "m8", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, }, }, }, { - Opcode: "SETPL", - Summary: "Set byte if not sign (SF == 0)", + Opcode: "VPSUBW", + Summary: "Subtract Packed Word Integers", Forms: []Form{ { + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "r8", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "m8", Action: 0x2}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, + CancellingInputs: true, }, - }, - }, - { - Opcode: "SETPS", - Summary: "Set byte if parity (PF == 1)", - Forms: []Form{ { + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "r8", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m8", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, + CancellingInputs: true, }, - }, - }, - { - Opcode: "SFENCE", - Summary: "Store Fence", - Forms: []Form{ - { - ISA: []string{"MMX+"}, - Operands: []Operand{}, - }, - }, - }, - { - Opcode: "SHA1MSG1", - Summary: "Perform an Intermediate Calculation for the Next Four SHA1 Message Doublewords", - Forms: []Form{ { - ISA: []string{"SHA"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"SHA"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "SHA1MSG2", - Summary: "Perform a Final Calculation for the Next Four SHA1 Message Doublewords", - Forms: []Form{ { - ISA: []string{"SHA"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"SHA"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "SHA1NEXTE", - Summary: "Calculate SHA1 State Variable E after Four Rounds", - Forms: []Form{ { - ISA: []string{"SHA"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + CancellingInputs: true, }, { - ISA: []string{"SHA"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, }, - }, - }, - { - Opcode: "SHA1RNDS4", - Summary: "Perform Four Rounds of SHA1 Operation", - Forms: []Form{ { - ISA: []string{"SHA"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm2u", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + CancellingInputs: true, }, { - ISA: []string{"SHA"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm2u", Action: 0x0}, - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, }, - }, - }, - { - Opcode: "SHA256MSG1", - Summary: "Perform an Intermediate Calculation for the Next Four SHA256 Message Doublewords", - Forms: []Form{ { - ISA: []string{"SHA"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"SHA"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "SHA256MSG2", - Summary: "Perform a Final Calculation for the Next Four SHA256 Message Doublewords", - Forms: []Form{ { - ISA: []string{"SHA"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"SHA"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + CancellingInputs: true, }, - }, - }, - { - Opcode: "SHA256RNDS2", - Summary: "Perform Two Rounds of SHA256 Operation", - Forms: []Form{ { - ISA: []string{"SHA"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "xmm0", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, }, { - ISA: []string{"SHA"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "xmm0", Action: 0x1}, - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, }, }, }, { - Opcode: "SHLB", - Summary: "Logical Shift Left", + Opcode: "VPTERNLOGD", + Summary: "Bitwise Ternary Logical Operation on Doubleword Values", Forms: []Form{ { - Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r8", Action: 0x3}, - }, - }, - { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r8", Action: 0x3}, - }, - }, - { - Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r8", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m8", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "m8", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m8", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "SHLL", - Summary: "Logical Shift Left", - Forms: []Form{ { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r32", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r32", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r32", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m32", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "m32", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m32", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r32", Action: 0x1}, - {Type: "m32", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r32", Action: 0x1}, - {Type: "m32", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "SHLQ", - Summary: "Logical Shift Left", - Forms: []Form{ { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r64", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r64", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r64", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m64", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "m64", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m64", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r64", Action: 0x1}, - {Type: "m64", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r64", Action: 0x1}, - {Type: "m64", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "SHLW", - Summary: "Logical Shift Left", - Forms: []Form{ { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r16", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r16", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r16", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, + }, + }, + { + Opcode: "VPTERNLOGQ", + Summary: "Bitwise Ternary Logical Operation on Quadword Values", + Forms: []Form{ { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m16", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "m16", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m16", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r16", Action: 0x1}, - {Type: "r16", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r16", Action: 0x1}, - {Type: "r16", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r16", Action: 0x1}, - {Type: "m16", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r16", Action: 0x1}, - {Type: "m16", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "SHLXL", - Summary: "Logical Shift Left Without Affecting Flags", - Forms: []Form{ { - ISA: []string{"BMI2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"BMI2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "m32", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "SHLXQ", - Summary: "Logical Shift Left Without Affecting Flags", - Forms: []Form{ { - ISA: []string{"BMI2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"BMI2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "m64", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, - }, - }, - { - Opcode: "SHRB", - Summary: "Logical Shift Right", - Forms: []Form{ { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r8", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r8", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r8", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m8", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "m8", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m8", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "SHRL", - Summary: "Logical Shift Right", - Forms: []Form{ { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r32", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r32", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r32", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m32", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "m32", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m32", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r32", Action: 0x1}, - {Type: "m32", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Zeroing: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r32", Action: 0x1}, - {Type: "m32", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "SHRQ", - Summary: "Logical Shift Right", + Opcode: "VPTEST", + Summary: "Packed Logical Compare", Forms: []Form{ { + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r64", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, }, + EncodingType: 0x3, }, { + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r64", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, }, + EncodingType: 0x3, }, { + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r64", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, }, + EncodingType: 0x3, }, { + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m64", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, }, + EncodingType: 0x3, }, + }, + }, + { + Opcode: "VPTESTMB", + Summary: "Logical AND of Packed Byte Integer Values and Set Mask", + Forms: []Form{ { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m64", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m64", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r64", Action: 0x1}, - {Type: "m64", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r64", Action: 0x1}, - {Type: "m64", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "SHRW", - Summary: "Logical Shift Right", - Forms: []Form{ { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "r16", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r16", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r16", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "1", Action: 0x0}, - {Type: "m16", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m16", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "m16", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, + }, + }, + { + Opcode: "VPTESTMD", + Summary: "Logical AND of Packed Doubleword Integer Values and Set Mask", + Forms: []Form{ { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r16", Action: 0x1}, - {Type: "r16", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r16", Action: 0x1}, - {Type: "r16", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r16", Action: 0x1}, - {Type: "m16", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "cl", Action: 0x1}, - {Type: "r16", Action: 0x1}, - {Type: "m16", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "SHRXL", - Summary: "Logical Shift Right Without Affecting Flags", - Forms: []Form{ { - ISA: []string{"BMI2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"BMI2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, {Type: "m32", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "SHRXQ", - Summary: "Logical Shift Right Without Affecting Flags", - Forms: []Form{ { - ISA: []string{"BMI2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"BMI2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "m64", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "SHUFPD", - Summary: "Shuffle Packed Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "SHUFPS", - Summary: "Shuffle Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"SSE"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"SSE"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "SQRTPD", - Summary: "Compute Square Roots of Packed Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "SQRTPS", - Summary: "Compute Square Roots of Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"SSE"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"SSE"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "SQRTSD", - Summary: "Compute Square Root of Scalar Double-Precision Floating-Point Value", - Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "SQRTSS", - Summary: "Compute Square Root of Scalar Single-Precision Floating-Point Value", + Opcode: "VPTESTMQ", + Summary: "Logical AND of Packed Quadword Integer Values and Set Mask", Forms: []Form{ { - ISA: []string{"SSE"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"SSE"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "STC", - Summary: "Set Carry Flag", - Forms: []Form{ - { - Operands: []Operand{}, - }, - }, - }, - { - Opcode: "STD", - Summary: "Set Direction Flag", - Forms: []Form{ { - Operands: []Operand{}, + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "STMXCSR", - Summary: "Store MXCSR Register State", - Forms: []Form{ { - ISA: []string{"SSE"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m32", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "SUBB", - Summary: "Subtract", - Forms: []Form{ { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "al", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r8", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "r8", Action: 0x1}, - {Type: "r8", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m8", Action: 0x1}, - {Type: "r8", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m8", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "r8", Action: 0x1}, - {Type: "m8", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "SUBL", - Summary: "Subtract", - Forms: []Form{ { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "eax", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r32", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "r32", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "r32", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m32", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "m32", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "m32", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "SUBPD", - Summary: "Subtract Packed Double-Precision Floating-Point Values", + Opcode: "VPTESTMW", + Summary: "Logical AND of Packed Word Integer Values and Set Mask", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "SUBPS", - Summary: "Subtract Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"SSE"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"SSE"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "SUBQ", - Summary: "Subtract", - Forms: []Form{ { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "rax", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r64", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "r64", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "r64", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m64", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "m64", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "m64", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "SUBSD", - Summary: "Subtract Scalar Double-Precision Floating-Point Values", + Opcode: "VPTESTNMB", + Summary: "Logical NAND of Packed Byte Integer Values and Set Mask", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512BW", "AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512BW", "AVX512F"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "SUBSS", - Summary: "Subtract Scalar Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"SSE"}, + ISA: []string{"AVX512BW", "AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"SSE"}, + ISA: []string{"AVX512BW", "AVX512F"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "SUBW", - Summary: "Subtract", - Forms: []Form{ { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm16", Action: 0x0}, - {Type: "ax", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r16", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm16", Action: 0x0}, - {Type: "r16", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, - {Type: "r16", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, - {Type: "r16", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m16", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm16", Action: 0x0}, - {Type: "m16", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, - {Type: "m16", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "SYSCALL", - Summary: "Fast System Call", + Opcode: "VPTESTNMD", + Summary: "Logical NAND of Packed Doubleword Integer Values and Set Mask", Forms: []Form{ { - Operands: []Operand{}, - ImplicitOperands: []ImplicitOperand{ - {Register: "r11", Action: 0x2}, - {Register: "rcx", Action: 0x2}, + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "TESTB", - Summary: "Logical Compare", - Forms: []Form{ { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "al", Action: 0x1}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r8", Action: 0x1}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "r8", Action: 0x1}, - {Type: "r8", Action: 0x1}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m8", Action: 0x1}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "r8", Action: 0x1}, - {Type: "m8", Action: 0x1}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "TESTL", - Summary: "Logical Compare", - Forms: []Form{ { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "eax", Action: 0x1}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "r32", Action: 0x1}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "TESTQ", - Summary: "Logical Compare", - Forms: []Form{ { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "rax", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "r64", Action: 0x1}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x1}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm32", Action: 0x0}, - {Type: "m64", Action: 0x1}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "m64", Action: 0x1}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "TESTW", - Summary: "Logical Compare", - Forms: []Form{ { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm16", Action: 0x0}, - {Type: "ax", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm16", Action: 0x0}, - {Type: "r16", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, + }, + }, + { + Opcode: "VPTESTNMQ", + Summary: "Logical NAND of Packed Quadword Integer Values and Set Mask", + Forms: []Form{ { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, - {Type: "r16", Action: 0x1}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm16", Action: 0x0}, - {Type: "m16", Action: 0x1}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, - {Type: "m16", Action: 0x1}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "TZCNTL", - Summary: "Count the Number of Trailing Zero Bits", - Forms: []Form{ { - ISA: []string{"BMI"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"BMI"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "TZCNTQ", - Summary: "Count the Number of Trailing Zero Bits", - Forms: []Form{ { - ISA: []string{"BMI"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"BMI"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m64", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "TZCNTW", - Summary: "Count the Number of Trailing Zero Bits", - Forms: []Form{ { - ISA: []string{"BMI"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "r16", Action: 0x1}, - {Type: "r16", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"BMI"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, - {Type: "r16", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "UCOMISD", - Summary: "Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS", - Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "UCOMISS", - Summary: "Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS", - Forms: []Form{ { - ISA: []string{"SSE"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"SSE"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "UD2", - Summary: "Undefined Instruction", - Forms: []Form{ { - Operands: []Operand{}, + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "UNPCKHPD", - Summary: "Unpack and Interleave High Packed Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "UNPCKHPS", - Summary: "Unpack and Interleave High Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"SSE"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"SSE"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "UNPCKLPD", - Summary: "Unpack and Interleave Low Packed Double-Precision Floating-Point Values", + Opcode: "VPTESTNMW", + Summary: "Logical NAND of Packed Word Integer Values and Set Mask", Forms: []Form{ { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512BW", "AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"SSE2"}, + ISA: []string{"AVX512BW", "AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "UNPCKLPS", - Summary: "Unpack and Interleave Low Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"SSE"}, + ISA: []string{"AVX512BW", "AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"SSE"}, + ISA: []string{"AVX512BW", "AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VADDPD", - Summary: "Add Packed Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ + {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VADDPS", - Summary: "Add Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "VADDSD", - Summary: "Add Scalar Double-Precision Floating-Point Values", + Opcode: "VPUNPCKHBW", + Summary: "Unpack and Interleave High-Order Bytes into Words", Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, - }, - }, - { - Opcode: "VADDSS", - Summary: "Add Scalar Single-Precision Floating-Point Values", - Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, - }, - }, - { - Opcode: "VADDSUBPD", - Summary: "Packed Double-FP Add/Subtract", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ + {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VADDSUBPS", - Summary: "Packed Single-FP Add/Subtract", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VAESDEC", - Summary: "Perform One Round of an AES Decryption Flow", - Forms: []Form{ { - ISA: []string{"AVX", "AES"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX", "AES"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VAESDECLAST", - Summary: "Perform Last Round of an AES Decryption Flow", - Forms: []Form{ { - ISA: []string{"AVX", "AES"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX", "AES"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "VAESENC", - Summary: "Perform One Round of an AES Encryption Flow", + Opcode: "VPUNPCKHDQ", + Summary: "Unpack and Interleave High-Order Doublewords into Quadwords", Forms: []Form{ { - ISA: []string{"AVX", "AES"}, + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX", "AES"}, + ISA: []string{"AVX"}, Operands: []Operand{ {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, - }, - }, - { - Opcode: "VAESENCLAST", - Summary: "Perform Last Round of an AES Encryption Flow", - Forms: []Form{ { - ISA: []string{"AVX", "AES"}, + ISA: []string{"AVX"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX", "AES"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VAESIMC", - Summary: "Perform the AES InvMixColumn Transformation", - Forms: []Form{ { - ISA: []string{"AVX", "AES"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX", "AES"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VAESKEYGENASSIST", - Summary: "AES Round Key Generation Assist", - Forms: []Form{ { - ISA: []string{"AVX", "AES"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX", "AES"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VANDNPD", - Summary: "Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m32", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VANDNPS", - Summary: "Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VANDPD", - Summary: "Bitwise Logical AND of Packed Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VANDPS", - Summary: "Bitwise Logical AND of Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, }, }, }, { - Opcode: "VBLENDPD", - Summary: "Blend Packed Double Precision Floating-Point Values", + Opcode: "VPUNPCKHQDQ", + Summary: "Unpack and Interleave High-Order Quadwords into Double Quadwords", Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "ymm", Action: 0x1}, + {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VBLENDPS", - Summary: " Blend Packed Single Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m256", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VBLENDVPD", - Summary: " Variable Blend Packed Double Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "ymm", Action: 0x1}, - {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VBLENDVPS", - Summary: " Variable Blend Packed Single Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VBROADCASTF128", - Summary: "Broadcast 128 Bit of Floating-Point Data", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, - }, - }, - { - Opcode: "VBROADCASTI128", - Summary: "Broadcast 128 Bits of Integer Data", - Forms: []Form{ { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VBROADCASTSD", - Summary: "Broadcast Double-Precision Floating-Point Element", - Forms: []Form{ { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "VBROADCASTSS", - Summary: "Broadcast Single-Precision Floating-Point Element", + Opcode: "VPUNPCKHWD", + Summary: "Unpack and Interleave High-Order Words into Doublewords", Forms: []Form{ { ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, - }, - }, - { - ISA: []string{"AVX"}, - Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, - }, - }, - { - Opcode: "VCMPPD", - Summary: "Compare Packed Double-Precision Floating-Point Values", - Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "ymm", Action: 0x1}, + {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VCMPPS", - Summary: "Compare Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VCMPSD", - Summary: "Compare Scalar Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VCMPSS", - Summary: "Compare Scalar Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "VCOMISD", - Summary: "Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS", + Opcode: "VPUNPCKLBW", + Summary: "Unpack and Interleave Low-Order Bytes into Words", Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, - }, - }, - { - Opcode: "VCOMISS", - Summary: "Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS", - Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VCVTDQ2PD", - Summary: "Convert Packed Dword Integers to Packed Double-Precision FP Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VCVTDQ2PS", - Summary: "Convert Packed Dword Integers to Packed Single-Precision FP Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VCVTPD2DQX", - Summary: "Convert Packed Double-Precision FP Values to Packed Dword Integers", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VCVTPD2DQY", - Summary: "Convert Packed Double-Precision FP Values to Packed Dword Integers", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "VCVTPD2PSX", - Summary: "Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values", + Opcode: "VPUNPCKLDQ", + Summary: "Unpack and Interleave Low-Order Doublewords into Quadwords", Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, - }, - }, - { - Opcode: "VCVTPD2PSY", - Summary: "Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values", - Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VCVTPH2PS", - Summary: "Convert Half-Precision FP Values to Single-Precision FP Values", - Forms: []Form{ { - ISA: []string{"F16C"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"F16C"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"F16C"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"F16C"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VCVTPS2DQ", - Summary: "Convert Packed Single-Precision FP Values to Packed Dword Integers", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m32", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, - }, - }, - { - Opcode: "VCVTPS2PD", - Summary: "Convert Packed Single-Precision FP Values to Packed Double-Precision FP Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VCVTPS2PH", - Summary: "Convert Single-Precision FP value to Half-Precision FP value", - Forms: []Form{ { - ISA: []string{"F16C"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"F16C"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "ymm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"F16C"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "m64", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"F16C"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "ymm", Action: 0x1}, - {Type: "m128", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VCVTSD2SI", - Summary: "Convert Scalar Double-Precision FP Value to Integer", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VCVTSD2SIQ", - Summary: "Convert Scalar Double-Precision FP Value to Integer", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VCVTSD2SS", - Summary: "Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "VCVTSI2SDL", - Summary: "Convert Dword Integer to Scalar Double-Precision FP Value", + Opcode: "VPUNPCKLQDQ", + Summary: "Unpack and Interleave Low-Order Quadwords into Double Quadwords", Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, - }, - }, - { - Opcode: "VCVTSI2SDQ", - Summary: "Convert Dword Integer to Scalar Double-Precision FP Value", - Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, - }, - }, - { - Opcode: "VCVTSI2SSL", - Summary: "Convert Dword Integer to Scalar Single-Precision FP Value", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VCVTSI2SSQ", - Summary: "Convert Dword Integer to Scalar Single-Precision FP Value", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VCVTSS2SD", - Summary: "Convert Scalar Single-Precision FP Value to Scalar Double-Precision FP Value", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VCVTSS2SI", - Summary: "Convert Scalar Single-Precision FP Value to Dword Integer", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, - }, - }, - { - Opcode: "VCVTSS2SIQ", - Summary: "Convert Scalar Single-Precision FP Value to Dword Integer", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VCVTTPD2DQX", - Summary: "Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VCVTTPD2DQY", - Summary: "Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "ymm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VCVTTPS2DQ", - Summary: "Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, - }, - }, - { - Opcode: "VCVTTSD2SI", - Summary: "Convert with Truncation Scalar Double-Precision FP Value to Signed Integer", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VCVTTSD2SIQ", - Summary: "Convert with Truncation Scalar Double-Precision FP Value to Signed Integer", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "VCVTTSS2SI", - Summary: "Convert with Truncation Scalar Single-Precision FP Value to Dword Integer", + Opcode: "VPUNPCKLWD", + Summary: "Unpack and Interleave Low-Order Words into Doublewords", Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX2"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, - }, - }, - { - Opcode: "VCVTTSS2SIQ", - Summary: "Convert with Truncation Scalar Single-Precision FP Value to Dword Integer", - Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, - }, - }, - { - Opcode: "VDIVPD", - Summary: "Divide Packed Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ + {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VDIVPS", - Summary: "Divide Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VDIVSD", - Summary: "Divide Scalar Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VDIVSS", - Summary: "Divide Scalar Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512BW"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BW"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "VDPPD", - Summary: "Dot Product of Packed Double Precision Floating-Point Values", + Opcode: "VPXOR", + Summary: "Packed Bitwise Logical Exclusive OR", Forms: []Form{ + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX2"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x3, + CancellingInputs: true, + }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, + CancellingInputs: true, }, }, }, { - Opcode: "VDPPS", - Summary: "Dot Product of Packed Single Precision Floating-Point Values", + Opcode: "VPXORD", + Summary: "Bitwise Logical Exclusive OR of Packed Doubleword Integers", Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VEXTRACTF128", - Summary: "Extract Packed Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "ymm", Action: 0x1}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "ymm", Action: 0x1}, - {Type: "m128", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VEXTRACTI128", - Summary: "Extract Packed Integer Values", - Forms: []Form{ { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "m128", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, - }, - }, - { - Opcode: "VEXTRACTPS", - Summary: "Extract Packed Single Precision Floating-Point Value", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, - {Type: "m32", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VFMADD132PD", - Summary: "Fused Multiply-Add of Packed Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VFMADD132PS", - Summary: "Fused Multiply-Add of Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VFMADD132SD", - Summary: "Fused Multiply-Add of Scalar Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VFMADD132SS", - Summary: "Fused Multiply-Add of Scalar Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, }, }, }, { - Opcode: "VFMADD213PD", - Summary: "Fused Multiply-Add of Packed Double-Precision Floating-Point Values", + Opcode: "VPXORQ", + Summary: "Bitwise Logical Exclusive OR of Packed Quadword Integers", Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VFMADD213PS", - Summary: "Fused Multiply-Add of Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VFMADD213SD", - Summary: "Fused Multiply-Add of Scalar Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VFMADD213SS", - Summary: "Fused Multiply-Add of Scalar Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VFMADD231PD", - Summary: "Fused Multiply-Add of Packed Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VFMADD231PS", - Summary: "Fused Multiply-Add of Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VFMADD231SD", - Summary: "Fused Multiply-Add of Scalar Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VFMADD231SS", - Summary: "Fused Multiply-Add of Scalar Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "VFMADDSUB132PD", - Summary: "Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values", + Opcode: "VRANGEPD", + Summary: "Range Restriction Calculation For Packed Pairs of Double-Precision Floating-Point Values", Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VFMADDSUB132PS", - Summary: "Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, - }, - }, - { - Opcode: "VFMADDSUB213PD", - Summary: "Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VFMADDSUB213PS", - Summary: "Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VFMADDSUB231PD", - Summary: "Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VFMADDSUB231PS", - Summary: "Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VFMSUB132PD", - Summary: "Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, }, }, { - Opcode: "VFMSUB132PS", - Summary: "Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values", + Opcode: "VRANGEPS", + Summary: "Range Restriction Calculation For Packed Pairs of Single-Precision Floating-Point Values", Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VFMSUB132SD", - Summary: "Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VFMSUB132SS", - Summary: "Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, - }, - }, - { - Opcode: "VFMSUB213PD", - Summary: "Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VFMSUB213PS", - Summary: "Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VFMSUB213SD", - Summary: "Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VFMSUB213SS", - Summary: "Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VFMSUB231PD", - Summary: "Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VFMSUB231PS", - Summary: "Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, }, }, { - Opcode: "VFMSUB231SD", - Summary: "Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values", + Opcode: "VRANGESD", + Summary: "Range Restriction Calculation For a pair of Scalar Double-Precision Floating-Point Values", Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VFMSUB231SS", - Summary: "Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, - }, - }, - { - Opcode: "VFMSUBADD132PD", - Summary: "Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, }, }, { - Opcode: "VFMSUBADD132PS", - Summary: "Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values", + Opcode: "VRANGESS", + Summary: "Range Restriction Calculation For a pair of Scalar Single-Precision Floating-Point Values", Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VFMSUBADD213PD", - Summary: "Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, }, }, { - Opcode: "VFMSUBADD213PS", - Summary: "Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values", + Opcode: "VRCP14PD", + Summary: "Compute Approximate Reciprocals of Packed Double-Precision Floating-Point Values", Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VFMSUBADD231PD", - Summary: "Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, - }, - }, - { - Opcode: "VFMSUBADD231PS", - Summary: "Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VFNMADD132PD", - Summary: "Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x3}, }, - }, - }, - }, - { - Opcode: "VFNMADD132PS", - Summary: "Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values", - Forms: []Form{ - { - ISA: []string{"FMA3"}, - Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, - }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VFNMADD132SD", - Summary: "Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VFNMADD132SS", - Summary: "Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, - }, - }, - { - Opcode: "VFNMADD213PD", - Summary: "Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "VFNMADD213PS", - Summary: "Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values", + Opcode: "VRCP14PS", + Summary: "Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values", Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VFNMADD213SD", - Summary: "Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VFNMADD213SS", - Summary: "Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, - }, - }, - { - Opcode: "VFNMADD231PD", - Summary: "Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VFNMADD231PS", - Summary: "Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VFNMADD231SD", - Summary: "Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VFNMADD231SS", - Summary: "Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VFNMSUB132PD", - Summary: "Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "VFNMSUB132PS", - Summary: "Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values", + Opcode: "VRCP14SD", + Summary: "Compute Approximate Reciprocal of a Scalar Double-Precision Floating-Point Value", Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VFNMSUB132SD", - Summary: "Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "VFNMSUB132SS", - Summary: "Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values", + Opcode: "VRCP14SS", + Summary: "Compute Approximate Reciprocal of a Scalar Single-Precision Floating-Point Value", Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VFNMSUB213PD", - Summary: "Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "VFNMSUB213PS", - Summary: "Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values", + Opcode: "VRCP28PD", + Summary: "Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error", Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VFNMSUB213SD", - Summary: "Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VFNMSUB213SS", - Summary: "Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, - }, - }, - { - Opcode: "VFNMSUB231PD", - Summary: "Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, }, }, { - Opcode: "VFNMSUB231PS", - Summary: "Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values", + Opcode: "VRCP28PS", + Summary: "Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error", Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VFNMSUB231SD", - Summary: "Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VFNMSUB231SS", - Summary: "Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"FMA3"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, - }, - }, - { - Opcode: "VGATHERDPD", - Summary: "Gather Packed Double-Precision Floating-Point Values Using Signed Doubleword Indices", - Forms: []Form{ { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "xmm", Action: 0x3}, - {Type: "vm32x", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "ymm", Action: 0x3}, - {Type: "vm32x", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, }, - }, - }, - { - Opcode: "VGATHERDPS", - Summary: "Gather Packed Single-Precision Floating-Point Values Using Signed Doubleword Indices", - Forms: []Form{ { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "xmm", Action: 0x3}, - {Type: "vm32x", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "ymm", Action: 0x3}, - {Type: "vm32y", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, }, }, { - Opcode: "VGATHERQPD", - Summary: "Gather Packed Double-Precision Floating-Point Values Using Signed Quadword Indices", + Opcode: "VRCP28SD", + Summary: "Approximation to the Reciprocal of a Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error", Forms: []Form{ { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "xmm", Action: 0x3}, - {Type: "vm64x", Action: 0x1}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "ymm", Action: 0x3}, - {Type: "vm64y", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VGATHERQPS", - Summary: "Gather Packed Single-Precision Floating-Point Values Using Signed Quadword Indices", - Forms: []Form{ { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "xmm", Action: 0x3}, - {Type: "vm64x", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, - {Type: "vm64y", Action: 0x1}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512ER"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, - }, - }, - { - Opcode: "VHADDPD", - Summary: "Packed Double-FP Horizontal Add", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, }, }, { - Opcode: "VHADDPS", - Summary: "Packed Single-FP Horizontal Add", + Opcode: "VRCP28SS", + Summary: "Approximation to the Reciprocal of a Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error", Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512ER"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, - }, - }, - { - Opcode: "VHSUBPD", - Summary: "Packed Double-FP Horizontal Subtract", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, }, }, { - Opcode: "VHSUBPS", - Summary: "Packed Single-FP Horizontal Subtract", + Opcode: "VRCPPS", + Summary: "Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values", Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "VINSERTF128", - Summary: "Insert Packed Floating-Point Values", + Opcode: "VRCPSS", + Summary: "Compute Approximate Reciprocal of Scalar Single-Precision Floating-Point Values", Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "VINSERTI128", - Summary: "Insert Packed Integer Values", + Opcode: "VREDUCEPD", + Summary: "Perform Reduction Transformation on Packed Double-Precision Floating-Point Values", Forms: []Form{ { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, {Type: "m128", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VINSERTPS", - Summary: "Insert Packed Single Precision Floating-Point Value", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VLDDQU", - Summary: "Load Unaligned Integer 128 Bits", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VLDMXCSR", - Summary: "Load MXCSR Register", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VMASKMOVDQU", - Summary: "Store Selected Bytes of Double Quadword", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - }, - ImplicitOperands: []ImplicitOperand{ - {Register: "rdi", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, - }, - }, - { - Opcode: "VMASKMOVPD", - Summary: "Conditional Move Packed Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "m128", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "m256", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VMASKMOVPS", - Summary: "Conditional Move Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "m128", Action: 0x2}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "ymm", Action: 0x1}, - {Type: "m256", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VMAXPD", - Summary: "Return Maximum Packed Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VMAXPS", - Summary: "Return Maximum Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VMAXSD", - Summary: "Return Maximum Scalar Double-Precision Floating-Point Value", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "VMAXSS", - Summary: "Return Maximum Scalar Single-Precision Floating-Point Value", + Opcode: "VREDUCEPS", + Summary: "Perform Reduction Transformation on Packed Single-Precision Floating-Point Values", Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VMINPD", - Summary: "Return Minimum Packed Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VMINPS", - Summary: "Return Minimum Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, - }, - }, - { - Opcode: "VMINSD", - Summary: "Return Minimum Scalar Double-Precision Floating-Point Value", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VMINSS", - Summary: "Return Minimum Scalar Single-Precision Floating-Point Value", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VMOVAPD", - Summary: "Move Aligned Packed Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "m128", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "m256", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, - }, - }, - { - Opcode: "VMOVAPS", - Summary: "Move Aligned Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "m128", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "m256", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "VMOVD", - Summary: "Move Doubleword", + Opcode: "VREDUCESD", + Summary: "Perform Reduction Transformation on a Scalar Double-Precision Floating-Point Value", Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "r32", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, - {Type: "m32", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VMOVDDUP", - Summary: "Move One Double-FP and Duplicate", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, - }, - { - ISA: []string{"AVX"}, - Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, - }, - }, - { - ISA: []string{"AVX"}, - Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x2}, - }, + EncodingType: 0x4, }, }, }, { - Opcode: "VMOVDQA", - Summary: "Move Aligned Double Quadword", + Opcode: "VREDUCESS", + Summary: "Perform Reduction Transformation on a Scalar Single-Precision Floating-Point Value", Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, - {Type: "m128", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "m256", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "VMOVDQU", - Summary: "Move Unaligned Double Quadword", + Opcode: "VRNDSCALEPD", + Summary: "Round Packed Double-Precision Floating-Point Values To Include A Given Number Of Fraction Bits", Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x2}, - }, - }, - { - ISA: []string{"AVX"}, - Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "m128", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "m256", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VMOVHLPS", - Summary: "Move Packed Single-Precision Floating-Point Values High to Low", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VMOVHPD", - Summary: "Move High Packed Double-Precision Floating-Point Value", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "m64", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, - }, - }, - { - Opcode: "VMOVHPS", - Summary: "Move High Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "m64", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, - }, - }, - { - Opcode: "VMOVLHPS", - Summary: "Move Packed Single-Precision Floating-Point Values Low to High", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, - }, - }, - }, - { - Opcode: "VMOVLPD", - Summary: "Move Low Packed Double-Precision Floating-Point Value", - Forms: []Form{ - { - ISA: []string{"AVX"}, - Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "m64", Action: 0x2}, - }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VMOVLPS", - Summary: "Move Low Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, - {Type: "m64", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VMOVMSKPD", - Summary: "Extract Packed Double-Precision Floating-Point Sign Mask", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "ymm", Action: 0x1}, - {Type: "r32", Action: 0x2}, - }, - }, - }, - }, - { - Opcode: "VMOVMSKPS", - Summary: "Extract Packed Single-Precision Floating-Point Sign Mask", - Forms: []Form{ - { - ISA: []string{"AVX"}, - Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "ymm", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VMOVNTDQ", - Summary: "Store Double Quadword Using Non-Temporal Hint", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "m128", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "m256", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VMOVNTDQA", - Summary: "Load Double Quadword Non-Temporal Aligned Hint", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VMOVNTPD", - Summary: "Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "m128", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "m256", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, - }, - }, - { - Opcode: "VMOVNTPS", - Summary: "Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "m128", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "m256", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VMOVQ", - Summary: "Move Quadword", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "m64", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, }, }, { - Opcode: "VMOVSD", - Summary: "Move Scalar Double-Precision Floating-Point Value", + Opcode: "VRNDSCALEPS", + Summary: "Round Packed Single-Precision Floating-Point Values To Include A Given Number Of Fraction Bits", Forms: []Form{ { - ISA: []string{"AVX"}, - Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x2}, - }, - }, - { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "m64", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VMOVSHDUP", - Summary: "Move Packed Single-FP High and Duplicate", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VMOVSLDUP", - Summary: "Move Packed Single-FP Low and Duplicate", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, - }, - }, - { - Opcode: "VMOVSS", - Summary: "Move Scalar Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "m32", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VMOVUPD", - Summary: "Move Unaligned Packed Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "m128", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "m256", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, - }, - }, - { - Opcode: "VMOVUPS", - Summary: "Move Unaligned Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "m128", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "m256", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, - }, - }, - { - Opcode: "VMPSADBW", - Summary: "Compute Multiple Packed Sums of Absolute Difference", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, }, }, { - Opcode: "VMULPD", - Summary: "Multiply Packed Double-Precision Floating-Point Values", + Opcode: "VRNDSCALESD", + Summary: "Round Scalar Double-Precision Floating-Point Value To Include A Given Number Of Fraction Bits", Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VMULPS", - Summary: "Multiply Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, - Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, - }, - }, - { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, }, - }, - }, - { - Opcode: "VMULSD", - Summary: "Multiply Scalar Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, }, }, { - Opcode: "VMULSS", - Summary: "Multiply Scalar Single-Precision Floating-Point Values", + Opcode: "VRNDSCALESS", + Summary: "Round Scalar Single-Precision Floating-Point Value To Include A Given Number Of Fraction Bits", Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VORPD", - Summary: "Bitwise Logical OR of Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, - }, - }, - { - ISA: []string{"AVX"}, - Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, - }, - }, - { - Opcode: "VORPS", - Summary: "Bitwise Logical OR of Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, }, }, { - Opcode: "VPABSB", - Summary: "Packed Absolute Value of Byte Integers", + Opcode: "VROUNDPD", + Summary: "Round Packed Double Precision Floating-Point Values", Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, - }, - }, - { - ISA: []string{"AVX"}, - Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, - Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, - }, - }, - { - ISA: []string{"AVX2"}, + ISA: []string{"AVX"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, - }, - }, - { - Opcode: "VPABSD", - Summary: "Packed Absolute Value of Doubleword Integers", - Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, - }, - }, - { - ISA: []string{"AVX2"}, - Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, - }, - { - ISA: []string{"AVX2"}, - Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x2}, - }, + EncodingType: 0x3, }, }, }, { - Opcode: "VPABSW", - Summary: "Packed Absolute Value of Word Integers", + Opcode: "VROUNDPS", + Summary: "Round Packed Single Precision Floating-Point Values", Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "VPACKSSDW", - Summary: "Pack Doublewords into Words with Signed Saturation", + Opcode: "VROUNDSD", + Summary: "Round Scalar Double Precision Floating-Point Values", Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, - }, - { - ISA: []string{"AVX2"}, - Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, - }, - }, - { - ISA: []string{"AVX2"}, - Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, - }, + EncodingType: 0x3, }, }, }, { - Opcode: "VPACKSSWB", - Summary: "Pack Words into Bytes with Signed Saturation", + Opcode: "VROUNDSS", + Summary: "Round Scalar Single Precision Floating-Point Values", Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, - }, - { - ISA: []string{"AVX2"}, - Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, - }, - }, - { - ISA: []string{"AVX2"}, - Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, - }, + EncodingType: 0x3, }, }, }, { - Opcode: "VPACKUSDW", - Summary: "Pack Doublewords into Words with Unsigned Saturation", + Opcode: "VRSQRT14PD", + Summary: "Compute Approximate Reciprocals of Square Roots of Packed Double-Precision Floating-Point Values", Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VPACKUSWB", - Summary: "Pack Words into Bytes with Unsigned Saturation", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, - }, - }, - }, - { - Opcode: "VPADDB", - Summary: "Add Packed Byte Integers", - Forms: []Form{ + EncodingType: 0x4, + Broadcast: true, + }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VPADDD", - Summary: "Add Packed Doubleword Integers", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VPADDQ", - Summary: "Add Packed Quadword Integers", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VPADDSB", - Summary: "Add Packed Signed Byte Integers with Signed Saturation", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "VPADDSW", - Summary: "Add Packed Signed Word Integers with Signed Saturation", + Opcode: "VRSQRT14PS", + Summary: "Compute Approximate Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values", Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VPADDUSB", - Summary: "Add Packed Unsigned Byte Integers with Unsigned Saturation", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VPADDUSW", - Summary: "Add Packed Unsigned Word Integers with Unsigned Saturation", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VPADDW", - Summary: "Add Packed Word Integers", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VPALIGNR", - Summary: "Packed Align Right", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VPAND", - Summary: "Packed Bitwise Logical AND", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "VPANDN", - Summary: "Packed Bitwise Logical AND NOT", + Opcode: "VRSQRT14SD", + Summary: "Compute Approximate Reciprocal of a Square Root of a Scalar Double-Precision Floating-Point Value", Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VPAVGB", - Summary: "Average Packed Byte Integers", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, + }, + }, + { + Opcode: "VRSQRT14SS", + Summary: "Compute Approximate Reciprocal of a Square Root of a Scalar Single-Precision Floating-Point Value", + Forms: []Form{ { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VPAVGW", - Summary: "Average Packed Word Integers", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "VPBLENDD", - Summary: "Blend Packed Doublewords", + Opcode: "VRSQRT28PD", + Summary: "Approximation to the Reciprocal Square Root of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error", Forms: []Form{ { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VPBLENDVB", - Summary: "Variable Blend Packed Bytes", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, - }, - }, - { - Opcode: "VPBLENDW", - Summary: "Blend Packed Words", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, }, }, { - Opcode: "VPBROADCASTB", - Summary: "Broadcast Byte Integer", + Opcode: "VRSQRT28PS", + Summary: "Approximation to the Reciprocal Square Root of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error", Forms: []Form{ { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "m8", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "m8", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VPBROADCASTD", - Summary: "Broadcast Doubleword Integer", - Forms: []Form{ { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, - }, - }, - { - Opcode: "VPBROADCASTQ", - Summary: "Broadcast Quadword Integer", - Forms: []Form{ { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, }, }, { - Opcode: "VPBROADCASTW", - Summary: "Broadcast Word Integer", + Opcode: "VRSQRT28SD", + Summary: "Approximation to the Reciprocal Square Root of a Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error", Forms: []Form{ { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VPCLMULQDQ", - Summary: "Carry-Less Quadword Multiplication", - Forms: []Form{ { - ISA: []string{"AVX", "PCLMULQDQ"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, { - ISA: []string{"AVX", "PCLMULQDQ"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VPCMPEQB", - Summary: "Compare Packed Byte Data for Equality", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, - Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, - }, - CancellingInputs: true, - }, - { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, }, }, { - Opcode: "VPCMPEQD", - Summary: "Compare Packed Doubleword Data for Equality", + Opcode: "VRSQRT28SS", + Summary: "Approximation to the Reciprocal Square Root of a Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error", Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512ER"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, - }, - }, - { - Opcode: "VPCMPEQQ", - Summary: "Compare Packed Quadword Data for Equality", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + SuppressAllExceptions: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512ER"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, }, }, { - Opcode: "VPCMPEQW", - Summary: "Compare Packed Word Data for Equality", + Opcode: "VRSQRTPS", + Summary: "Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values", Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "VPCMPESTRI", - Summary: "Packed Compare Explicit Length Strings, Return Index", + Opcode: "VRSQRTSS", + Summary: "Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value", Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, - ImplicitOperands: []ImplicitOperand{ - {Register: "eax", Action: 0x1}, - {Register: "ecx", Action: 0x2}, - {Register: "edx", Action: 0x1}, - }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, - ImplicitOperands: []ImplicitOperand{ - {Register: "eax", Action: 0x1}, - {Register: "ecx", Action: 0x2}, - {Register: "edx", Action: 0x1}, - }, + EncodingType: 0x3, }, }, }, { - Opcode: "VPCMPESTRM", - Summary: "Packed Compare Explicit Length Strings, Return Mask", + Opcode: "VSCALEFPD", + Summary: "Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values", Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, - ImplicitOperands: []ImplicitOperand{ - {Register: "eax", Action: 0x1}, - {Register: "edx", Action: 0x1}, - {Register: "xmm0", Action: 0x2}, - }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, - ImplicitOperands: []ImplicitOperand{ - {Register: "eax", Action: 0x1}, - {Register: "edx", Action: 0x1}, - {Register: "xmm0", Action: 0x2}, - }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VPCMPGTB", - Summary: "Compare Packed Signed Byte Integers for Greater Than", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VPCMPGTD", - Summary: "Compare Packed Signed Doubleword Integers for Greater Than", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m64", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VPCMPGTQ", - Summary: "Compare Packed Data for Greater Than", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, - Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, - }, - CancellingInputs: true, - }, - { - ISA: []string{"AVX2"}, - Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, - }, - }, - }, - }, - { - Opcode: "VPCMPGTW", - Summary: "Compare Packed Signed Word Integers for Greater Than", - Forms: []Form{ - { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VPCMPISTRI", - Summary: "Packed Compare Implicit Length Strings, Return Index", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - }, - ImplicitOperands: []ImplicitOperand{ - {Register: "ecx", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - }, - ImplicitOperands: []ImplicitOperand{ - {Register: "ecx", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VPCMPISTRM", - Summary: "Packed Compare Implicit Length Strings, Return Mask", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - }, - ImplicitOperands: []ImplicitOperand{ - {Register: "xmm0", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - }, - ImplicitOperands: []ImplicitOperand{ - {Register: "xmm0", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VPERM2F128", - Summary: "Permute Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VPERM2I128", - Summary: "Permute 128-Bit Integer Values", - Forms: []Form{ { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + EmbeddedRounding: true, }, - }, - }, - { - Opcode: "VPERMD", - Summary: "Permute Doubleword Integers", - Forms: []Form{ { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, }, - }, - }, - { - Opcode: "VPERMILPD", - Summary: "Permute Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + EmbeddedRounding: true, }, + }, + }, + { + Opcode: "VSCALEFPS", + Summary: "Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values", + Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VPERMILPS", - Summary: "Permute Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, - Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, - }, - }, - { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m32", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VPERMPD", - Summary: "Permute Double-Precision Floating-Point Elements", - Forms: []Form{ { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VPERMPS", - Summary: "Permute Single-Precision Floating-Point Elements", - Forms: []Form{ { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, - }, - }, - }, - }, - { - Opcode: "VPERMQ", - Summary: "Permute Quadword Integers", - Forms: []Form{ - { - ISA: []string{"AVX2"}, - Operands: []Operand{ - {Type: "imm8", Action: 0x0}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VPEXTRB", - Summary: "Extract Byte", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "m8", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, - }, - }, - { - Opcode: "VPEXTRD", - Summary: "Extract Doubleword", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "m32", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VPEXTRQ", - Summary: "Extract Quadword", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "r64", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "m64", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VPEXTRW", - Summary: "Extract Word", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "m16", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + EmbeddedRounding: true, }, - }, - }, - { - Opcode: "VPGATHERDD", - Summary: "Gather Packed Doubleword Values Using Signed Doubleword Indices", - Forms: []Form{ { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x3}, - {Type: "vm32x", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x3}, - {Type: "vm32y", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, }, - }, - }, - { - Opcode: "VPGATHERDQ", - Summary: "Gather Packed Quadword Values Using Signed Doubleword Indices", - Forms: []Form{ { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x3}, - {Type: "vm32x", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x3}, - {Type: "vm32x", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + EmbeddedRounding: true, }, }, }, { - Opcode: "VPGATHERQD", - Summary: "Gather Packed Doubleword Values Using Signed Quadword Indices", + Opcode: "VSCALEFSD", + Summary: "Scale Scalar Double-Precision Floating-Point Value With a Double-Precision Floating-Point Value", Forms: []Form{ { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x3}, - {Type: "vm64x", Action: 0x1}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x3}, - {Type: "vm64y", Action: 0x1}, - {Type: "xmm", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VPGATHERQQ", - Summary: "Gather Packed Quadword Values Using Signed Quadword Indices", - Forms: []Form{ { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x3}, - {Type: "vm64x", Action: 0x1}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x3}, - {Type: "vm64y", Action: 0x1}, - {Type: "ymm", Action: 0x3}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + EmbeddedRounding: true, }, - }, - }, - { - Opcode: "VPHADDD", - Summary: "Packed Horizontal Add Doubleword Integer", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + EmbeddedRounding: true, }, }, }, { - Opcode: "VPHADDSW", - Summary: "Packed Horizontal Add Signed Word Integers with Signed Saturation", + Opcode: "VSCALEFSS", + Summary: "Scale Scalar Single-Precision Floating-Point Value With a Single-Precision Floating-Point Value", Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + EmbeddedRounding: true, }, - }, - }, - { - Opcode: "VPHADDW", - Summary: "Packed Horizontal Add Word Integers", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + EmbeddedRounding: true, }, }, }, { - Opcode: "VPHMINPOSUW", - Summary: "Packed Horizontal Minimum of Unsigned Word Integers", + Opcode: "VSCATTERDPD", + Summary: "Scatter Packed Double-Precision Floating-Point Values with Signed Doubleword Indices", Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "vm32x", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "vm32x", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "vm32y", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "VPHSUBD", - Summary: "Packed Horizontal Subtract Doubleword Integers", + Opcode: "VSCATTERDPS", + Summary: "Scatter Packed Single-Precision Floating-Point Values with Signed Doubleword Indices", Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "vm32x", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "vm32y", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "vm32z", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VSCATTERQPD", + Summary: "Scatter Packed Double-Precision Floating-Point Values with Signed Quadword Indices", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "vm64x", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "vm64y", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "vm64z", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "VPHSUBSW", - Summary: "Packed Horizontal Subtract Signed Word Integers with Signed Saturation", + Opcode: "VSCATTERQPS", + Summary: "Scatter Packed Single-Precision Floating-Point Values with Signed Quadword Indices", Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "vm64x", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "vm64y", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "vm64z", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VSHUFF32X4", + Summary: "Shuffle 128-Bit Packed Single-Precision Floating-Point Values", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VPHSUBW", - Summary: "Packed Horizontal Subtract Word Integers", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VPINSRB", - Summary: "Insert Byte", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r32", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "m8", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VPINSRD", - Summary: "Insert Doubleword", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r32", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VPINSRQ", - Summary: "Insert Quadword", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r64", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VPINSRW", - Summary: "Insert Word", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r32", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "m16", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VPMADDUBSW", - Summary: "Multiply and Add Packed Signed and Unsigned Byte Integers", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "VPMADDWD", - Summary: "Multiply and Add Packed Signed Word Integers", + Opcode: "VSHUFF64X2", + Summary: "Shuffle 128-Bit Packed Double-Precision Floating-Point Values", Forms: []Form{ { - ISA: []string{"AVX"}, - Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, - }, - }, - { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VPMASKMOVD", - Summary: "Conditional Move Packed Doubleword Integers", - Forms: []Form{ { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "m128", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "m256", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VPMASKMOVQ", - Summary: "Conditional Move Packed Quadword Integers", - Forms: []Form{ { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "m128", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "m256", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VPMAXSB", - Summary: "Maximum of Packed Signed Byte Integers", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VPMAXSD", - Summary: "Maximum of Packed Signed Doubleword Integers", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VSHUFI32X4", + Summary: "Shuffle 128-Bit Packed Doubleword Integer Values", + Forms: []Form{ + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VPMAXSW", - Summary: "Maximum of Packed Signed Word Integers", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VPMAXUB", - Summary: "Maximum of Packed Unsigned Byte Integers", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VPMAXUD", - Summary: "Maximum of Packed Unsigned Doubleword Integers", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VPMAXUW", - Summary: "Maximum of Packed Unsigned Word Integers", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "VPMINSB", - Summary: "Minimum of Packed Signed Byte Integers", + Opcode: "VSHUFI64X2", + Summary: "Shuffle 128-Bit Packed Quadword Integer Values", Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, - }, - }, - { - Opcode: "VPMINSD", - Summary: "Minimum of Packed Signed Doubleword Integers", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VPMINSW", - Summary: "Minimum of Packed Signed Word Integers", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VPMINUB", - Summary: "Minimum of Packed Unsigned Byte Integers", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "VPMINUD", - Summary: "Minimum of Packed Unsigned Doubleword Integers", + Opcode: "VSHUFPD", + Summary: "Shuffle Packed Double-Precision Floating-Point Values", Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, - }, - }, - { - Opcode: "VPMINUW", - Summary: "Minimum of Packed Unsigned Word Integers", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VPMOVMSKB", - Summary: "Move Byte Mask", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "r32", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, - }, - }, - { - Opcode: "VPMOVSXBD", - Summary: "Move Packed Byte Integers to Doubleword Integers with Sign Extension", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VPMOVSXBQ", - Summary: "Move Packed Byte Integers to Quadword Integers with Sign Extension", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VPMOVSXBW", - Summary: "Move Packed Byte Integers to Word Integers with Sign Extension", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VPMOVSXDQ", - Summary: "Move Packed Doubleword Integers to Quadword Integers with Sign Extension", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "VPMOVSXWD", - Summary: "Move Packed Word Integers to Doubleword Integers with Sign Extension", + Opcode: "VSHUFPS", + Summary: "Shuffle Packed Single-Precision Floating-Point Values", Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "m128", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VPMOVSXWQ", - Summary: "Move Packed Word Integers to Quadword Integers with Sign Extension", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VPMOVZXBD", - Summary: "Move Packed Byte Integers to Doubleword Integers with Zero Extension", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VPMOVZXBQ", - Summary: "Move Packed Byte Integers to Quadword Integers with Zero Extension", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m16", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VPMOVZXBW", - Summary: "Move Packed Byte Integers to Word Integers with Zero Extension", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VPMOVZXDQ", - Summary: "Move Packed Doubleword Integers to Quadword Integers with Zero Extension", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "imm8", Action: 0x0}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "VPMOVZXWD", - Summary: "Move Packed Word Integers to Doubleword Integers with Zero Extension", + Opcode: "VSQRTPD", + Summary: "Compute Square Roots of Packed Double-Precision Floating-Point Values", Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m128", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VPMOVZXWQ", - Summary: "Move Packed Word Integers to Quadword Integers with Zero Extension", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VPMULDQ", - Summary: "Multiply Packed Signed Doubleword Integers and Store Quadword Result", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VPMULHRSW", - Summary: "Packed Multiply Signed Word Integers and Store High Result with Round and Scale", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VPMULHUW", - Summary: "Multiply Packed Unsigned Word Integers and Store High Result", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VPMULHW", - Summary: "Multiply Packed Signed Word Integers and Store High Result", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + EmbeddedRounding: true, }, - }, - }, - { - Opcode: "VPMULLD", - Summary: "Multiply Packed Signed Doubleword Integers and Store Low Result", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + EmbeddedRounding: true, }, }, }, { - Opcode: "VPMULLW", - Summary: "Multiply Packed Signed Word Integers and Store Low Result", + Opcode: "VSQRTPS", + Summary: "Compute Square Roots of Packed Single-Precision Floating-Point Values", Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, - }, - }, - { - Opcode: "VPMULUDQ", - Summary: "Multiply Packed Unsigned Doubleword Integers", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VPOR", - Summary: "Packed Bitwise Logical OR", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VPSADBW", - Summary: "Compute Sum of Absolute Differences", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VPSHUFB", - Summary: "Packed Shuffle Bytes", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VPSHUFD", - Summary: "Shuffle Packed Doublewords", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + EmbeddedRounding: true, }, - }, - }, - { - Opcode: "VPSHUFHW", - Summary: "Shuffle Packed High Words", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + EmbeddedRounding: true, }, }, }, { - Opcode: "VPSHUFLW", - Summary: "Shuffle Packed Low Words", + Opcode: "VSQRTSD", + Summary: "Compute Square Root of Scalar Double-Precision Floating-Point Value", Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VPSIGNB", - Summary: "Packed Sign of Byte Integers", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + EmbeddedRounding: true, }, }, }, { - Opcode: "VPSIGND", - Summary: "Packed Sign of Doubleword Integers", + Opcode: "VSQRTSS", + Summary: "Compute Square Root of Scalar Single-Precision Floating-Point Value", Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VPSIGNW", - Summary: "Packed Sign of Word Integers", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + EmbeddedRounding: true, }, + }, + }, + { + Opcode: "VSTMXCSR", + Summary: "Store MXCSR Register State", + Forms: []Form{ { - ISA: []string{"AVX2"}, + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m32", Action: 0x2}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "VPSLLD", - Summary: "Shift Packed Doubleword Data Left Logical", + Opcode: "VSUBPD", + Summary: "Subtract Packed Double-Precision Floating-Point Values", Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m128", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VPSLLDQ", - Summary: "Shift Packed Double Quadword Left Logical", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VPSLLQ", - Summary: "Shift Packed Quadword Data Left Logical", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VPSLLVD", - Summary: "Variable Shift Packed Doubleword Data Left Logical", - Forms: []Form{ { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VPSLLVQ", - Summary: "Variable Shift Packed Quadword Data Left Logical", - Forms: []Form{ { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VPSLLW", - Summary: "Shift Packed Word Data Left Logical", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + EmbeddedRounding: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, }, - }, - }, - { - Opcode: "VPSRAD", - Summary: "Shift Packed Doubleword Data Right Arithmetic", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + EmbeddedRounding: true, }, + }, + }, + { + Opcode: "VSUBPS", + Summary: "Subtract Packed Single-Precision Floating-Point Values", + Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ @@ -23652,342 +114479,424 @@ var Instructions = []Instruction{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, - }, - }, - { - Opcode: "VPSRAVD", - Summary: "Variable Shift Packed Doubleword Data Right Arithmetic", - Forms: []Form{ { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VPSRAW", - Summary: "Shift Packed Word Data Right Arithmetic", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VPSRLD", - Summary: "Shift Packed Doubleword Data Right Logical", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, - }, - }, - { - Opcode: "VPSRLDQ", - Summary: "Shift Packed Double Quadword Right Logical", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VPSRLQ", - Summary: "Shift Packed Quadword Data Right Logical", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + EmbeddedRounding: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + EmbeddedRounding: true, }, }, }, { - Opcode: "VPSRLVD", - Summary: "Variable Shift Packed Doubleword Data Right Logical", + Opcode: "VSUBSD", + Summary: "Subtract Scalar Double-Precision Floating-Point Values", Forms: []Form{ { - ISA: []string{"AVX2"}, + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VPSRLVQ", - Summary: "Variable Shift Packed Quadword Data Right Logical", - Forms: []Form{ { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + EmbeddedRounding: true, + }, + { + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + EmbeddedRounding: true, }, }, }, { - Opcode: "VPSRLW", - Summary: "Shift Packed Word Data Right Logical", + Opcode: "VSUBSS", + Summary: "Subtract Scalar Single-Precision Floating-Point Values", Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, @@ -23996,214 +114905,227 @@ var Instructions = []Instruction{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + EmbeddedRounding: true, }, - }, - }, - { - Opcode: "VPSUBB", - Summary: "Subtract Packed Byte Integers", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + EmbeddedRounding: true, }, { - ISA: []string{"AVX2"}, - Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, - }, - CancellingInputs: true, - }, - { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + EmbeddedRounding: true, }, }, }, { - Opcode: "VPSUBD", - Summary: "Subtract Packed Doubleword Integers", + Opcode: "VTESTPD", + Summary: "Packed Double-Precision Floating-Point Bit Test", Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, }, - CancellingInputs: true, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "ymm", Action: 0x1}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "VPSUBQ", - Summary: "Subtract Packed Quadword Integers", + Opcode: "VTESTPS", + Summary: "Packed Single-Precision Floating-Point Bit Test", Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, }, - CancellingInputs: true, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "ymm", Action: 0x1}, }, + EncodingType: 0x3, }, }, }, { - Opcode: "VPSUBSB", - Summary: "Subtract Packed Signed Byte Integers with Signed Saturation", + Opcode: "VUCOMISD", + Summary: "Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS", Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, - }, - }, - { - ISA: []string{"AVX2"}, - Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, }, - CancellingInputs: true, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, }, }, { - Opcode: "VPSUBSW", - Summary: "Subtract Packed Signed Word Integers with Signed Saturation", + Opcode: "VUCOMISS", + Summary: "Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS", Forms: []Form{ + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + }, + EncodingType: 0x3, + }, { ISA: []string{"AVX"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + }, + EncodingType: 0x4, + SuppressAllExceptions: true, }, + }, + }, + { + Opcode: "VUNPCKHPD", + Summary: "Unpack and Interleave High Packed Double-Precision Floating-Point Values", + Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ @@ -24211,742 +115133,872 @@ var Instructions = []Instruction{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, + {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x3, + }, + { + ISA: []string{"AVX"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, - }, - }, - { - Opcode: "VPSUBUSB", - Summary: "Subtract Packed Unsigned Byte Integers with Unsigned Saturation", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VPSUBUSW", - Summary: "Subtract Packed Unsigned Word Integers with Unsigned Saturation", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m64", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VPSUBW", - Summary: "Subtract Packed Word Integers", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VPTEST", - Summary: "Packed Logical Compare", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VPUNPCKHBW", - Summary: "Unpack and Interleave High-Order Bytes into Words", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "VPUNPCKHDQ", - Summary: "Unpack and Interleave High-Order Doublewords into Quadwords", + Opcode: "VUNPCKHPS", + Summary: "Unpack and Interleave High Packed Single-Precision Floating-Point Values", Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, - }, - }, - { - Opcode: "VPUNPCKHQDQ", - Summary: "Unpack and Interleave High-Order Quadwords into Double Quadwords", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VPUNPCKHWD", - Summary: "Unpack and Interleave High-Order Words into Doublewords", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m32", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VPUNPCKLBW", - Summary: "Unpack and Interleave Low-Order Bytes into Words", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VPUNPCKLDQ", - Summary: "Unpack and Interleave Low-Order Doublewords into Quadwords", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VPUNPCKLQDQ", - Summary: "Unpack and Interleave Low-Order Quadwords into Double Quadwords", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512F"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "VPUNPCKLWD", - Summary: "Unpack and Interleave Low-Order Words into Doublewords", + Opcode: "VUNPCKLPD", + Summary: "Unpack and Interleave Low Packed Double-Precision Floating-Point Values", Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, - }, - }, - { - Opcode: "VPXOR", - Summary: "Packed Bitwise Logical Exclusive OR", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x4, }, { - ISA: []string{"AVX2"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VRCPPS", - Summary: "Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "m64", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ + {Type: "m64", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, - }, - }, - { - Opcode: "VRCPSS", - Summary: "Compute Approximate Reciprocal of Scalar Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VROUNDPD", - Summary: "Round Packed Double Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VROUNDPS", - Summary: "Round Packed Single Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, - }, - }, - { - Opcode: "VROUNDSD", - Summary: "Round Scalar Double Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VROUNDSS", - Summary: "Round Scalar Single Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "VRSQRTPS", - Summary: "Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values", + Opcode: "VUNPCKLPS", + Summary: "Unpack and Interleave Low Packed Single-Precision Floating-Point Values", Forms: []Form{ - { - ISA: []string{"AVX"}, - Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, - }, - }, { ISA: []string{"AVX"}, Operands: []Operand{ {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, - }, - { - ISA: []string{"AVX"}, - Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, - }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, - }, - }, - { - Opcode: "VRSQRTSS", - Summary: "Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value", - Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ @@ -24954,682 +116006,847 @@ var Instructions = []Instruction{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, - }, - }, - { - Opcode: "VSHUFPD", - Summary: "Shuffle Packed Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "ymm", Action: 0x1}, + {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VSHUFPS", - Summary: "Shuffle Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m128", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "ymm", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m256", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512F", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VSQRTPD", - Summary: "Compute Square Roots of Packed Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VSQRTPS", - Summary: "Compute Square Roots of Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VSQRTSD", - Summary: "Compute Square Root of Scalar Double-Precision Floating-Point Value", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, - }, - }, - { - Opcode: "VSQRTSS", - Summary: "Compute Square Root of Scalar Single-Precision Floating-Point Value", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VSTMXCSR", - Summary: "Store MXCSR Register State", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512F"}, Operands: []Operand{ - {Type: "m32", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, }, }, { - Opcode: "VSUBPD", - Summary: "Subtract Packed Double-Precision Floating-Point Values", + Opcode: "VXORPD", + Summary: "Bitwise Logical XOR for Double-Precision Floating-Point Values", Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, + CancellingInputs: true, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, + CancellingInputs: true, }, - }, - }, - { - Opcode: "VSUBPS", - Summary: "Subtract Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ + {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VSUBSD", - Summary: "Subtract Scalar Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, - }, - }, - { - Opcode: "VSUBSS", - Summary: "Subtract Scalar Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VTESTPD", - Summary: "Packed Double-Precision Floating-Point Bit Test", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m64", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + CancellingInputs: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + CancellingInputs: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, }, - }, - }, - { - Opcode: "VTESTPS", - Summary: "Packed Single-Precision Floating-Point Bit Test", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VUCOMISD", - Summary: "Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "m64", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ {Type: "m64", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VUCOMISS", - Summary: "Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + CancellingInputs: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m32", Action: 0x1}, - {Type: "xmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + CancellingInputs: true, }, }, }, { - Opcode: "VUNPCKHPD", - Summary: "Unpack and Interleave High Packed Double-Precision Floating-Point Values", + Opcode: "VXORPS", + Summary: "Bitwise Logical XOR for Single-Precision Floating-Point Values", Forms: []Form{ { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x3, + CancellingInputs: true, }, { ISA: []string{"AVX"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x3, + CancellingInputs: true, }, - }, - }, - { - Opcode: "VUNPCKHPS", - Summary: "Unpack and Interleave High Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ + {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VUNPCKLPD", - Summary: "Unpack and Interleave Low Packed Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ + {Type: "m32", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512DQ", "AVX512VL"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, + {Type: "m32", Action: 0x1}, {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VUNPCKLPS", - Summary: "Unpack and Interleave Low Packed Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x4, + CancellingInputs: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "xmm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ {Type: "ymm", Action: 0x1}, {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, }, + EncodingType: 0x4, + CancellingInputs: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ", "AVX512VL"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, {Type: "ymm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, + Zeroing: true, + }, + { + ISA: []string{"AVX512DQ"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, }, - }, - }, - { - Opcode: "VXORPD", - Summary: "Bitwise Logical XOR for Double-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Broadcast: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + Zeroing: true, }, - }, - }, - { - Opcode: "VXORPS", - Summary: "Bitwise Logical XOR for Single-Precision Floating-Point Values", - Forms: []Form{ { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, - CancellingInputs: true, + EncodingType: 0x4, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, - {Type: "xmm", Action: 0x1}, - {Type: "xmm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, }, + EncodingType: 0x4, + CancellingInputs: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, CancellingInputs: true, + Zeroing: true, }, { - ISA: []string{"AVX"}, + ISA: []string{"AVX512DQ"}, Operands: []Operand{ - {Type: "m256", Action: 0x1}, - {Type: "ymm", Action: 0x1}, - {Type: "ymm", Action: 0x2}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, }, + EncodingType: 0x4, + CancellingInputs: true, }, }, }, @@ -25638,8 +116855,9 @@ var Instructions = []Instruction{ Summary: "Zero All YMM Registers", Forms: []Form{ { - ISA: []string{"AVX"}, - Operands: []Operand{}, + ISA: []string{"AVX"}, + Operands: []Operand{}, + EncodingType: 0x3, }, }, }, @@ -25648,8 +116866,9 @@ var Instructions = []Instruction{ Summary: "Zero Upper Bits of YMM Registers", Forms: []Form{ { - ISA: []string{"AVX"}, - Operands: []Operand{}, + ISA: []string{"AVX"}, + Operands: []Operand{}, + EncodingType: 0x3, }, }, }, @@ -25660,14 +116879,16 @@ var Instructions = []Instruction{ { Operands: []Operand{ {Type: "r8", Action: 0x3}, - {Type: "r8", Action: 0x3}, + {Type: "m8", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r8", Action: 0x3}, - {Type: "m8", Action: 0x3}, + {Type: "r8", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -25678,14 +116899,16 @@ var Instructions = []Instruction{ { Operands: []Operand{ {Type: "r32", Action: 0x3}, - {Type: "r32", Action: 0x3}, + {Type: "m32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r32", Action: 0x3}, - {Type: "m32", Action: 0x3}, + {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -25696,14 +116919,16 @@ var Instructions = []Instruction{ { Operands: []Operand{ {Type: "r64", Action: 0x3}, - {Type: "r64", Action: 0x3}, + {Type: "m64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r64", Action: 0x3}, - {Type: "m64", Action: 0x3}, + {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -25714,14 +116939,16 @@ var Instructions = []Instruction{ { Operands: []Operand{ {Type: "r16", Action: 0x3}, - {Type: "r16", Action: 0x3}, + {Type: "m16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r16", Action: 0x3}, - {Type: "m16", Action: 0x3}, + {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -25731,21 +116958,24 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "r8", Action: 0x3}, + {Type: "m8", Action: 0x3}, {Type: "r8", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m8", Action: 0x3}, {Type: "r8", Action: 0x3}, + {Type: "m8", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r8", Action: 0x3}, - {Type: "m8", Action: 0x3}, + {Type: "r8", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -25755,33 +116985,38 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "r32", Action: 0x3}, {Type: "eax", Action: 0x3}, + {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "eax", Action: 0x3}, + {Type: "m32", Action: 0x3}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r32", Action: 0x3}, - {Type: "r32", Action: 0x3}, + {Type: "eax", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m32", Action: 0x3}, {Type: "r32", Action: 0x3}, + {Type: "m32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r32", Action: 0x3}, - {Type: "m32", Action: 0x3}, + {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -25791,33 +117026,38 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ + {Type: "m64", Action: 0x3}, {Type: "r64", Action: 0x3}, - {Type: "rax", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "rax", Action: 0x3}, {Type: "r64", Action: 0x3}, + {Type: "m64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r64", Action: 0x3}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m64", Action: 0x3}, {Type: "r64", Action: 0x3}, + {Type: "rax", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ + {Type: "rax", Action: 0x3}, {Type: "r64", Action: 0x3}, - {Type: "m64", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -25827,33 +117067,38 @@ var Instructions = []Instruction{ Forms: []Form{ { Operands: []Operand{ - {Type: "r16", Action: 0x3}, {Type: "ax", Action: 0x3}, + {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "ax", Action: 0x3}, + {Type: "m16", Action: 0x3}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r16", Action: 0x3}, - {Type: "r16", Action: 0x3}, + {Type: "ax", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m16", Action: 0x3}, {Type: "r16", Action: 0x3}, + {Type: "m16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r16", Action: 0x3}, - {Type: "m16", Action: 0x3}, + {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, }, }, @@ -25868,6 +117113,7 @@ var Instructions = []Instruction{ {Register: "ecx", Action: 0x1}, {Register: "edx", Action: 0x2}, }, + EncodingType: 0x1, }, }, }, @@ -25881,6 +117127,7 @@ var Instructions = []Instruction{ {Register: "al", Action: 0x3}, {Register: "ebx", Action: 0x1}, }, + EncodingType: 0x1, }, }, }, @@ -25893,37 +117140,43 @@ var Instructions = []Instruction{ {Type: "imm8", Action: 0x0}, {Type: "al", Action: 0x3}, }, + EncodingType: 0x1, }, { Operands: []Operand{ {Type: "imm8", Action: 0x0}, - {Type: "r8", Action: 0x3}, + {Type: "m8", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r8", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "r8", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "m8", Action: 0x1}, {Type: "r8", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "r8", Action: 0x1}, {Type: "m8", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r8", Action: 0x1}, - {Type: "m8", Action: 0x3}, + {Type: "r8", Action: 0x3}, }, + EncodingType: 0x2, + CancellingInputs: true, }, }, }, @@ -25936,49 +117189,57 @@ var Instructions = []Instruction{ {Type: "imm32", Action: 0x0}, {Type: "eax", Action: 0x3}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r32", Action: 0x3}, + {Type: "imm32", Action: 0x0}, + {Type: "m32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "imm32", Action: 0x0}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r32", Action: 0x1}, - {Type: "r32", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m32", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m32", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m32", Action: 0x3}, + {Type: "m32", Action: 0x1}, + {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm32", Action: 0x0}, + {Type: "r32", Action: 0x1}, {Type: "m32", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r32", Action: 0x1}, - {Type: "m32", Action: 0x3}, + {Type: "r32", Action: 0x3}, }, + EncodingType: 0x2, + CancellingInputs: true, }, }, }, @@ -25989,17 +117250,19 @@ var Instructions = []Instruction{ { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x2, }, { ISA: []string{"SSE2"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, + CancellingInputs: true, }, }, }, @@ -26010,17 +117273,19 @@ var Instructions = []Instruction{ { ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "xmm", Action: 0x1}, + {Type: "m128", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x2, }, { ISA: []string{"SSE"}, Operands: []Operand{ - {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, {Type: "xmm", Action: 0x3}, }, + EncodingType: 0x2, + CancellingInputs: true, }, }, }, @@ -26031,51 +117296,59 @@ var Instructions = []Instruction{ { Operands: []Operand{ {Type: "imm32", Action: 0x0}, - {Type: "rax", Action: 0x3}, + {Type: "m64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, + {Type: "imm32", Action: 0x0}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "imm32", Action: 0x0}, - {Type: "r64", Action: 0x3}, + {Type: "rax", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r64", Action: 0x1}, - {Type: "r64", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m64", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m64", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m64", Action: 0x3}, + {Type: "m64", Action: 0x1}, + {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm32", Action: 0x0}, + {Type: "r64", Action: 0x1}, {Type: "m64", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r64", Action: 0x1}, - {Type: "m64", Action: 0x3}, + {Type: "r64", Action: 0x3}, }, + EncodingType: 0x2, + CancellingInputs: true, }, }, }, @@ -26088,49 +117361,57 @@ var Instructions = []Instruction{ {Type: "imm16", Action: 0x0}, {Type: "ax", Action: 0x3}, }, + EncodingType: 0x1, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "r16", Action: 0x3}, + {Type: "imm16", Action: 0x0}, + {Type: "m16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "imm16", Action: 0x0}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "r16", Action: 0x1}, - {Type: "r16", Action: 0x3}, + {Type: "imm8", Action: 0x0}, + {Type: "m16", Action: 0x3}, }, - CancellingInputs: true, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "m16", Action: 0x1}, + {Type: "imm8", Action: 0x0}, {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm8", Action: 0x0}, - {Type: "m16", Action: 0x3}, + {Type: "m16", Action: 0x1}, + {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ - {Type: "imm16", Action: 0x0}, + {Type: "r16", Action: 0x1}, {Type: "m16", Action: 0x3}, }, + EncodingType: 0x2, }, { Operands: []Operand{ {Type: "r16", Action: 0x1}, - {Type: "m16", Action: 0x3}, + {Type: "r16", Action: 0x3}, }, + EncodingType: 0x2, + CancellingInputs: true, }, }, }, diff --git a/internal/inst/ztable_test.go b/internal/inst/ztable_test.go deleted file mode 100644 index 31974cc9..00000000 --- a/internal/inst/ztable_test.go +++ /dev/null @@ -1,18 +0,0 @@ -// Code generated by command: avogen -bootstrap -data ../data -output ztable_test.go godatatest. DO NOT EDIT. - -package inst_test - -import ( - "reflect" - "testing" - - "github.com/mmcloughlin/avo/internal/inst" -) - -var raw = []inst.Instruction{inst.Instruction{Opcode: "ADCB", AliasOf: "", Summary: "Add with Carry", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "al", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x1}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ADCL", AliasOf: "", Summary: "Add with Carry", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "eax", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ADCQ", AliasOf: "", Summary: "Add with Carry", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "rax", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ADCW", AliasOf: "", Summary: "Add with Carry", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm16", Action: 0x0}, inst.Operand{Type: "ax", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm16", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm16", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ADCXL", AliasOf: "", Summary: "Unsigned Integer Addition of Two Operands with Carry Flag", Forms: []inst.Form{inst.Form{ISA: []string{"ADX"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"ADX"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ADCXQ", AliasOf: "", Summary: "Unsigned Integer Addition of Two Operands with Carry Flag", Forms: []inst.Form{inst.Form{ISA: []string{"ADX"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"ADX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ADDB", AliasOf: "", Summary: "Add", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "al", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x1}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ADDL", AliasOf: "", Summary: "Add", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "eax", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ADDPD", AliasOf: "", Summary: "Add Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ADDPS", AliasOf: "", Summary: "Add Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ADDQ", AliasOf: "", Summary: "Add", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "rax", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ADDSD", AliasOf: "", Summary: "Add Scalar Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ADDSS", AliasOf: "", Summary: "Add Scalar Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ADDSUBPD", AliasOf: "", Summary: "Packed Double-FP Add/Subtract", Forms: []inst.Form{inst.Form{ISA: []string{"SSE3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ADDSUBPS", AliasOf: "", Summary: "Packed Single-FP Add/Subtract", Forms: []inst.Form{inst.Form{ISA: []string{"SSE3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ADDW", AliasOf: "", Summary: "Add", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm16", Action: 0x0}, inst.Operand{Type: "ax", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm16", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm16", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ADOXL", AliasOf: "", Summary: "Unsigned Integer Addition of Two Operands with Overflow Flag", Forms: []inst.Form{inst.Form{ISA: []string{"ADX"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"ADX"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ADOXQ", AliasOf: "", Summary: "Unsigned Integer Addition of Two Operands with Overflow Flag", Forms: []inst.Form{inst.Form{ISA: []string{"ADX"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"ADX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "AESDEC", AliasOf: "", Summary: "Perform One Round of an AES Decryption Flow", Forms: []inst.Form{inst.Form{ISA: []string{"AES"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AES"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "AESDECLAST", AliasOf: "", Summary: "Perform Last Round of an AES Decryption Flow", Forms: []inst.Form{inst.Form{ISA: []string{"AES"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AES"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "AESENC", AliasOf: "", Summary: "Perform One Round of an AES Encryption Flow", Forms: []inst.Form{inst.Form{ISA: []string{"AES"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AES"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "AESENCLAST", AliasOf: "", Summary: "Perform Last Round of an AES Encryption Flow", Forms: []inst.Form{inst.Form{ISA: []string{"AES"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AES"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "AESIMC", AliasOf: "", Summary: "Perform the AES InvMixColumn Transformation", Forms: []inst.Form{inst.Form{ISA: []string{"AES"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AES"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "AESKEYGENASSIST", AliasOf: "", Summary: "AES Round Key Generation Assist", Forms: []inst.Form{inst.Form{ISA: []string{"AES"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AES"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ANDB", AliasOf: "", Summary: "Logical AND", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "al", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x1}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ANDL", AliasOf: "", Summary: "Logical AND", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "eax", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ANDNL", AliasOf: "", Summary: "Logical AND NOT", Forms: []inst.Form{inst.Form{ISA: []string{"BMI"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"BMI"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ANDNPD", AliasOf: "", Summary: "Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ANDNPS", AliasOf: "", Summary: "Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ANDNQ", AliasOf: "", Summary: "Logical AND NOT", Forms: []inst.Form{inst.Form{ISA: []string{"BMI"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"BMI"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ANDPD", AliasOf: "", Summary: "Bitwise Logical AND of Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ANDPS", AliasOf: "", Summary: "Bitwise Logical AND of Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ANDQ", AliasOf: "", Summary: "Logical AND", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "rax", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ANDW", AliasOf: "", Summary: "Logical AND", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm16", Action: 0x0}, inst.Operand{Type: "ax", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm16", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm16", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BEXTRL", AliasOf: "", Summary: "Bit Field Extract", Forms: []inst.Form{inst.Form{ISA: []string{"BMI"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"BMI"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BEXTRQ", AliasOf: "", Summary: "Bit Field Extract", Forms: []inst.Form{inst.Form{ISA: []string{"BMI"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"BMI"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BLENDPD", AliasOf: "", Summary: "Blend Packed Double Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BLENDPS", AliasOf: "", Summary: " Blend Packed Single Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BLENDVPD", AliasOf: "", Summary: " Variable Blend Packed Double Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm0", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm0", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BLENDVPS", AliasOf: "", Summary: " Variable Blend Packed Single Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm0", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm0", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BLSIL", AliasOf: "", Summary: "Isolate Lowest Set Bit", Forms: []inst.Form{inst.Form{ISA: []string{"BMI"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"BMI"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BLSIQ", AliasOf: "", Summary: "Isolate Lowest Set Bit", Forms: []inst.Form{inst.Form{ISA: []string{"BMI"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"BMI"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BLSMSKL", AliasOf: "", Summary: "Mask From Lowest Set Bit", Forms: []inst.Form{inst.Form{ISA: []string{"BMI"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"BMI"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BLSMSKQ", AliasOf: "", Summary: "Mask From Lowest Set Bit", Forms: []inst.Form{inst.Form{ISA: []string{"BMI"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"BMI"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BLSRL", AliasOf: "", Summary: "Reset Lowest Set Bit", Forms: []inst.Form{inst.Form{ISA: []string{"BMI"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"BMI"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BLSRQ", AliasOf: "", Summary: "Reset Lowest Set Bit", Forms: []inst.Form{inst.Form{ISA: []string{"BMI"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"BMI"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BSFL", AliasOf: "", Summary: "Bit Scan Forward", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BSFQ", AliasOf: "", Summary: "Bit Scan Forward", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BSFW", AliasOf: "", Summary: "Bit Scan Forward", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BSRL", AliasOf: "", Summary: "Bit Scan Reverse", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BSRQ", AliasOf: "", Summary: "Bit Scan Reverse", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BSRW", AliasOf: "", Summary: "Bit Scan Reverse", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BSWAPL", AliasOf: "", Summary: "Byte Swap", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BSWAPQ", AliasOf: "", Summary: "Byte Swap", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BTCL", AliasOf: "", Summary: "Bit Test and Complement", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BTCQ", AliasOf: "", Summary: "Bit Test and Complement", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BTCW", AliasOf: "", Summary: "Bit Test and Complement", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BTL", AliasOf: "", Summary: "Bit Test", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BTQ", AliasOf: "", Summary: "Bit Test", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BTRL", AliasOf: "", Summary: "Bit Test and Reset", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BTRQ", AliasOf: "", Summary: "Bit Test and Reset", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BTRW", AliasOf: "", Summary: "Bit Test and Reset", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BTSL", AliasOf: "", Summary: "Bit Test and Set", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BTSQ", AliasOf: "", Summary: "Bit Test and Set", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BTSW", AliasOf: "", Summary: "Bit Test and Set", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BTW", AliasOf: "", Summary: "Bit Test", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "m16", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BZHIL", AliasOf: "", Summary: "Zero High Bits Starting with Specified Bit Position", Forms: []inst.Form{inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "BZHIQ", AliasOf: "", Summary: "Zero High Bits Starting with Specified Bit Position", Forms: []inst.Form{inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CALL", AliasOf: "", Summary: "Call Procedure", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CBW", AliasOf: "", Summary: "Convert Byte to Word", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "ax", Action: 0x2}, inst.ImplicitOperand{Register: "al", Action: 0x1}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "CDQ", AliasOf: "", Summary: "Convert Doubleword to Quadword", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "eax", Action: 0x1}, inst.ImplicitOperand{Register: "edx", Action: 0x2}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "CDQE", AliasOf: "", Summary: "Convert Doubleword to Quadword", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "eax", Action: 0x1}, inst.ImplicitOperand{Register: "rax", Action: 0x2}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "CLC", AliasOf: "", Summary: "Clear Carry Flag", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CLD", AliasOf: "", Summary: "Clear Direction Flag", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CLFLUSH", AliasOf: "", Summary: "Flush Cache Line", Forms: []inst.Form{inst.Form{ISA: []string{"CLFLUSH"}, Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CLFLUSHOPT", AliasOf: "", Summary: "Flush Cache Line Optimized", Forms: []inst.Form{inst.Form{ISA: []string{"CLFLUSHOPT"}, Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMC", AliasOf: "", Summary: "Complement Carry Flag", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVLCC", AliasOf: "", Summary: "Move if above or equal (CF == 0)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVLCS", AliasOf: "", Summary: "Move if below (CF == 1)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVLEQ", AliasOf: "", Summary: "Move if equal (ZF == 1)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVLGE", AliasOf: "", Summary: "Move if greater or equal (SF == OF)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVLGT", AliasOf: "", Summary: "Move if greater (ZF == 0 and SF == OF)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVLHI", AliasOf: "", Summary: "Move if above (CF == 0 and ZF == 0)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVLLE", AliasOf: "", Summary: "Move if less or equal (ZF == 1 or SF != OF)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVLLS", AliasOf: "", Summary: "Move if below or equal (CF == 1 or ZF == 1)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVLLT", AliasOf: "", Summary: "Move if less (SF != OF)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVLMI", AliasOf: "", Summary: "Move if sign (SF == 1)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVLNE", AliasOf: "", Summary: "Move if not equal (ZF == 0)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVLOC", AliasOf: "", Summary: "Move if not overflow (OF == 0)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVLOS", AliasOf: "", Summary: "Move if overflow (OF == 1)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVLPC", AliasOf: "", Summary: "Move if not parity (PF == 0)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVLPL", AliasOf: "", Summary: "Move if not sign (SF == 0)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVLPS", AliasOf: "", Summary: "Move if parity (PF == 1)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVQCC", AliasOf: "", Summary: "Move if above or equal (CF == 0)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVQCS", AliasOf: "", Summary: "Move if below (CF == 1)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVQEQ", AliasOf: "", Summary: "Move if equal (ZF == 1)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVQGE", AliasOf: "", Summary: "Move if greater or equal (SF == OF)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVQGT", AliasOf: "", Summary: "Move if greater (ZF == 0 and SF == OF)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVQHI", AliasOf: "", Summary: "Move if above (CF == 0 and ZF == 0)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVQLE", AliasOf: "", Summary: "Move if less or equal (ZF == 1 or SF != OF)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVQLS", AliasOf: "", Summary: "Move if below or equal (CF == 1 or ZF == 1)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVQLT", AliasOf: "", Summary: "Move if less (SF != OF)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVQMI", AliasOf: "", Summary: "Move if sign (SF == 1)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVQNE", AliasOf: "", Summary: "Move if not equal (ZF == 0)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVQOC", AliasOf: "", Summary: "Move if not overflow (OF == 0)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVQOS", AliasOf: "", Summary: "Move if overflow (OF == 1)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVQPC", AliasOf: "", Summary: "Move if not parity (PF == 0)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVQPL", AliasOf: "", Summary: "Move if not sign (SF == 0)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVQPS", AliasOf: "", Summary: "Move if parity (PF == 1)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVWCC", AliasOf: "", Summary: "Move if above or equal (CF == 0)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVWCS", AliasOf: "", Summary: "Move if below (CF == 1)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVWEQ", AliasOf: "", Summary: "Move if equal (ZF == 1)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVWGE", AliasOf: "", Summary: "Move if greater or equal (SF == OF)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVWGT", AliasOf: "", Summary: "Move if greater (ZF == 0 and SF == OF)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVWHI", AliasOf: "", Summary: "Move if above (CF == 0 and ZF == 0)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVWLE", AliasOf: "", Summary: "Move if less or equal (ZF == 1 or SF != OF)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVWLS", AliasOf: "", Summary: "Move if below or equal (CF == 1 or ZF == 1)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVWLT", AliasOf: "", Summary: "Move if less (SF != OF)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVWMI", AliasOf: "", Summary: "Move if sign (SF == 1)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVWNE", AliasOf: "", Summary: "Move if not equal (ZF == 0)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVWOC", AliasOf: "", Summary: "Move if not overflow (OF == 0)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVWOS", AliasOf: "", Summary: "Move if overflow (OF == 1)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVWPC", AliasOf: "", Summary: "Move if not parity (PF == 0)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVWPL", AliasOf: "", Summary: "Move if not sign (SF == 0)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMOVWPS", AliasOf: "", Summary: "Move if parity (PF == 1)", Forms: []inst.Form{inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"CMOV"}, Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMPB", AliasOf: "", Summary: "Compare Two Operands", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "al", Action: 0x1}, inst.Operand{Type: "imm8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}, inst.Operand{Type: "imm8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}, inst.Operand{Type: "r8", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}, inst.Operand{Type: "m8", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x1}, inst.Operand{Type: "imm8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x1}, inst.Operand{Type: "r8", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMPL", AliasOf: "", Summary: "Compare Two Operands", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "eax", Action: 0x1}, inst.Operand{Type: "imm32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "imm8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "imm32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "imm8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "imm32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMPPD", AliasOf: "", Summary: "Compare Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}, inst.Operand{Type: "imm8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}, inst.Operand{Type: "imm8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMPPS", AliasOf: "", Summary: "Compare Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}, inst.Operand{Type: "imm8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}, inst.Operand{Type: "imm8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMPQ", AliasOf: "", Summary: "Compare Two Operands", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rax", Action: 0x1}, inst.Operand{Type: "imm32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "imm8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "imm32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "imm8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "imm32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMPSD", AliasOf: "", Summary: "Compare Scalar Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}, inst.Operand{Type: "imm8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}, inst.Operand{Type: "imm8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMPSS", AliasOf: "", Summary: "Compare Scalar Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}, inst.Operand{Type: "imm8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}, inst.Operand{Type: "imm8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMPW", AliasOf: "", Summary: "Compare Two Operands", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "ax", Action: 0x1}, inst.Operand{Type: "imm16", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "imm8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "imm16", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "m16", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "imm8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "imm16", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMPXCHG16B", AliasOf: "", Summary: "Compare and Exchange 16 Bytes", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "rax", Action: 0x3}, inst.ImplicitOperand{Register: "rbx", Action: 0x1}, inst.ImplicitOperand{Register: "rcx", Action: 0x1}, inst.ImplicitOperand{Register: "rdx", Action: 0x3}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "CMPXCHG8B", AliasOf: "", Summary: "Compare and Exchange 8 Bytes", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "eax", Action: 0x3}, inst.ImplicitOperand{Register: "ebx", Action: 0x1}, inst.ImplicitOperand{Register: "ecx", Action: 0x1}, inst.ImplicitOperand{Register: "edx", Action: 0x3}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "CMPXCHGB", AliasOf: "", Summary: "Compare and Exchange", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMPXCHGL", AliasOf: "", Summary: "Compare and Exchange", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMPXCHGQ", AliasOf: "", Summary: "Compare and Exchange", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CMPXCHGW", AliasOf: "", Summary: "Compare and Exchange", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "COMISD", AliasOf: "", Summary: "Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "COMISS", AliasOf: "", Summary: "Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CPUID", AliasOf: "", Summary: "CPU Identification", Forms: []inst.Form{inst.Form{ISA: []string{"CPUID"}, Operands: []inst.Operand{}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "eax", Action: 0x3}, inst.ImplicitOperand{Register: "ebx", Action: 0x2}, inst.ImplicitOperand{Register: "ecx", Action: 0x3}, inst.ImplicitOperand{Register: "edx", Action: 0x2}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "CQO", AliasOf: "", Summary: "Convert Quadword to Octaword", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "rax", Action: 0x1}, inst.ImplicitOperand{Register: "rdx", Action: 0x2}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "CRC32B", AliasOf: "", Summary: "Accumulate CRC32 Value", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.2"}, Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.2"}, Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.2"}, Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.2"}, Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CRC32L", AliasOf: "", Summary: "Accumulate CRC32 Value", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.2"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.2"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CRC32Q", AliasOf: "", Summary: "Accumulate CRC32 Value", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.2"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CRC32W", AliasOf: "", Summary: "Accumulate CRC32 Value", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.2"}, Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.2"}, Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CVTPD2PL", AliasOf: "", Summary: "Convert Packed Double-Precision FP Values to Packed Dword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CVTPD2PS", AliasOf: "", Summary: "Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CVTPL2PD", AliasOf: "", Summary: "Convert Packed Dword Integers to Packed Double-Precision FP Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CVTPL2PS", AliasOf: "", Summary: "Convert Packed Dword Integers to Packed Single-Precision FP Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CVTPS2PD", AliasOf: "", Summary: "Convert Packed Single-Precision FP Values to Packed Double-Precision FP Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CVTPS2PL", AliasOf: "", Summary: "Convert Packed Single-Precision FP Values to Packed Dword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CVTSD2SL", AliasOf: "", Summary: "Convert Scalar Double-Precision FP Value to Integer", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CVTSD2SS", AliasOf: "", Summary: "Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CVTSL2SD", AliasOf: "", Summary: "Convert Dword Integer to Scalar Double-Precision FP Value", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CVTSL2SS", AliasOf: "", Summary: "Convert Dword Integer to Scalar Single-Precision FP Value", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CVTSQ2SD", AliasOf: "", Summary: "Convert Dword Integer to Scalar Double-Precision FP Value", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CVTSQ2SS", AliasOf: "", Summary: "Convert Dword Integer to Scalar Single-Precision FP Value", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CVTSS2SD", AliasOf: "", Summary: "Convert Scalar Single-Precision FP Value to Scalar Double-Precision FP Value", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CVTSS2SL", AliasOf: "", Summary: "Convert Scalar Single-Precision FP Value to Dword Integer", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CVTTPD2PL", AliasOf: "", Summary: "Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CVTTPS2PL", AliasOf: "", Summary: "Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CVTTSD2SL", AliasOf: "", Summary: "Convert with Truncation Scalar Double-Precision FP Value to Signed Integer", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CVTTSD2SQ", AliasOf: "", Summary: "Convert with Truncation Scalar Double-Precision FP Value to Signed Integer", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CVTTSS2SL", AliasOf: "", Summary: "Convert with Truncation Scalar Single-Precision FP Value to Dword Integer", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "CWD", AliasOf: "", Summary: "Convert Word to Doubleword", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "ax", Action: 0x1}, inst.ImplicitOperand{Register: "dx", Action: 0x2}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "CWDE", AliasOf: "", Summary: "Convert Word to Doubleword", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "ax", Action: 0x1}, inst.ImplicitOperand{Register: "eax", Action: 0x2}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "DECB", AliasOf: "", Summary: "Decrement by 1", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "DECL", AliasOf: "", Summary: "Decrement by 1", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "DECQ", AliasOf: "", Summary: "Decrement by 1", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "DECW", AliasOf: "", Summary: "Decrement by 1", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "DIVB", AliasOf: "", Summary: "Unsigned Divide", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "ax", Action: 0x3}}, CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "ax", Action: 0x3}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "DIVL", AliasOf: "", Summary: "Unsigned Divide", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "eax", Action: 0x3}, inst.ImplicitOperand{Register: "edx", Action: 0x3}}, CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "eax", Action: 0x3}, inst.ImplicitOperand{Register: "edx", Action: 0x3}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "DIVPD", AliasOf: "", Summary: "Divide Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "DIVPS", AliasOf: "", Summary: "Divide Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "DIVQ", AliasOf: "", Summary: "Unsigned Divide", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "rax", Action: 0x3}, inst.ImplicitOperand{Register: "rdx", Action: 0x3}}, CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "rax", Action: 0x3}, inst.ImplicitOperand{Register: "rdx", Action: 0x3}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "DIVSD", AliasOf: "", Summary: "Divide Scalar Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "DIVSS", AliasOf: "", Summary: "Divide Scalar Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "DIVW", AliasOf: "", Summary: "Unsigned Divide", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "ax", Action: 0x3}, inst.ImplicitOperand{Register: "dx", Action: 0x3}}, CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "ax", Action: 0x3}, inst.ImplicitOperand{Register: "dx", Action: 0x3}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "DPPD", AliasOf: "", Summary: "Dot Product of Packed Double Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "DPPS", AliasOf: "", Summary: "Dot Product of Packed Single Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "EXTRACTPS", AliasOf: "", Summary: "Extract Packed Single Precision Floating-Point Value", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm2u", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm2u", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "HADDPD", AliasOf: "", Summary: "Packed Double-FP Horizontal Add", Forms: []inst.Form{inst.Form{ISA: []string{"SSE3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "HADDPS", AliasOf: "", Summary: "Packed Single-FP Horizontal Add", Forms: []inst.Form{inst.Form{ISA: []string{"SSE3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "HSUBPD", AliasOf: "", Summary: "Packed Double-FP Horizontal Subtract", Forms: []inst.Form{inst.Form{ISA: []string{"SSE3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "HSUBPS", AliasOf: "", Summary: "Packed Single-FP Horizontal Subtract", Forms: []inst.Form{inst.Form{ISA: []string{"SSE3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "IDIVB", AliasOf: "", Summary: "Signed Divide", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "ax", Action: 0x3}}, CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "ax", Action: 0x3}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "IDIVL", AliasOf: "", Summary: "Signed Divide", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "eax", Action: 0x3}, inst.ImplicitOperand{Register: "edx", Action: 0x3}}, CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "eax", Action: 0x3}, inst.ImplicitOperand{Register: "edx", Action: 0x3}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "IDIVQ", AliasOf: "", Summary: "Signed Divide", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "rax", Action: 0x3}, inst.ImplicitOperand{Register: "rdx", Action: 0x3}}, CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "rax", Action: 0x3}, inst.ImplicitOperand{Register: "rdx", Action: 0x3}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "IDIVW", AliasOf: "", Summary: "Signed Divide", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "ax", Action: 0x3}, inst.ImplicitOperand{Register: "dx", Action: 0x3}}, CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "ax", Action: 0x3}, inst.ImplicitOperand{Register: "dx", Action: 0x3}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "IMUL3L", AliasOf: "", Summary: "Signed Multiply", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "IMUL3Q", AliasOf: "", Summary: "Signed Multiply", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "IMUL3W", AliasOf: "", Summary: "Signed Multiply", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm16", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm16", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "IMULB", AliasOf: "", Summary: "Signed Multiply", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "ax", Action: 0x2}, inst.ImplicitOperand{Register: "al", Action: 0x1}}, CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "ax", Action: 0x2}, inst.ImplicitOperand{Register: "al", Action: 0x1}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "IMULL", AliasOf: "", Summary: "Signed Multiply", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "eax", Action: 0x3}, inst.ImplicitOperand{Register: "edx", Action: 0x2}}, CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "eax", Action: 0x3}, inst.ImplicitOperand{Register: "edx", Action: 0x2}}, CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "IMULQ", AliasOf: "", Summary: "Signed Multiply", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "rax", Action: 0x3}, inst.ImplicitOperand{Register: "rdx", Action: 0x2}}, CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "rax", Action: 0x3}, inst.ImplicitOperand{Register: "rdx", Action: 0x2}}, CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "IMULW", AliasOf: "", Summary: "Signed Multiply", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "ax", Action: 0x3}, inst.ImplicitOperand{Register: "dx", Action: 0x2}}, CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "ax", Action: 0x3}, inst.ImplicitOperand{Register: "dx", Action: 0x2}}, CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "INCB", AliasOf: "", Summary: "Increment by 1", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "INCL", AliasOf: "", Summary: "Increment by 1", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "INCQ", AliasOf: "", Summary: "Increment by 1", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "INCW", AliasOf: "", Summary: "Increment by 1", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "INSERTPS", AliasOf: "", Summary: "Insert Packed Single Precision Floating-Point Value", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "INT", AliasOf: "", Summary: "Call to Interrupt Procedure", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "3", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JA", AliasOf: "JHI", Summary: "Jump if above (CF == 0 and ZF == 0)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JAE", AliasOf: "JCC", Summary: "Jump if above or equal (CF == 0)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JB", AliasOf: "JCS", Summary: "Jump if below (CF == 1)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JBE", AliasOf: "JLS", Summary: "Jump if below or equal (CF == 1 or ZF == 1)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JC", AliasOf: "JCS", Summary: "Jump if below (CF == 1)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JCC", AliasOf: "", Summary: "Jump if above or equal (CF == 0)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JCS", AliasOf: "", Summary: "Jump if below (CF == 1)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JCXZL", AliasOf: "", Summary: "Jump if ECX register is 0", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "ecx", Action: 0x1}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "JCXZQ", AliasOf: "", Summary: "Jump if RCX register is 0", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "rcx", Action: 0x1}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "JE", AliasOf: "JEQ", Summary: "Jump if equal (ZF == 1)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JEQ", AliasOf: "", Summary: "Jump if equal (ZF == 1)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JG", AliasOf: "JGT", Summary: "Jump if greater (ZF == 0 and SF == OF)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JGE", AliasOf: "", Summary: "Jump if greater or equal (SF == OF)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JGT", AliasOf: "", Summary: "Jump if greater (ZF == 0 and SF == OF)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JHI", AliasOf: "", Summary: "Jump if above (CF == 0 and ZF == 0)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JHS", AliasOf: "JCC", Summary: "Jump if above or equal (CF == 0)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JL", AliasOf: "JLT", Summary: "Jump if less (SF != OF)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JLE", AliasOf: "", Summary: "Jump if less or equal (ZF == 1 or SF != OF)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JLO", AliasOf: "JCS", Summary: "Jump if below (CF == 1)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JLS", AliasOf: "", Summary: "Jump if below or equal (CF == 1 or ZF == 1)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JLT", AliasOf: "", Summary: "Jump if less (SF != OF)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JMI", AliasOf: "", Summary: "Jump if sign (SF == 1)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JMP", AliasOf: "", Summary: "Jump Unconditionally", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JNA", AliasOf: "JLS", Summary: "Jump if below or equal (CF == 1 or ZF == 1)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JNAE", AliasOf: "JCS", Summary: "Jump if below (CF == 1)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JNB", AliasOf: "JCC", Summary: "Jump if above or equal (CF == 0)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JNBE", AliasOf: "JHI", Summary: "Jump if above (CF == 0 and ZF == 0)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JNC", AliasOf: "JCC", Summary: "Jump if above or equal (CF == 0)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JNE", AliasOf: "", Summary: "Jump if not equal (ZF == 0)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JNG", AliasOf: "JLE", Summary: "Jump if less or equal (ZF == 1 or SF != OF)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JNGE", AliasOf: "JLT", Summary: "Jump if less (SF != OF)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JNL", AliasOf: "JGE", Summary: "Jump if greater or equal (SF == OF)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JNLE", AliasOf: "JGT", Summary: "Jump if greater (ZF == 0 and SF == OF)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JNO", AliasOf: "JOC", Summary: "Jump if not overflow (OF == 0)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JNP", AliasOf: "JPC", Summary: "Jump if not parity (PF == 0)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JNS", AliasOf: "JPL", Summary: "Jump if not sign (SF == 0)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JNZ", AliasOf: "JNE", Summary: "Jump if not equal (ZF == 0)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JO", AliasOf: "JOS", Summary: "Jump if overflow (OF == 1)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JOC", AliasOf: "", Summary: "Jump if not overflow (OF == 0)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JOS", AliasOf: "", Summary: "Jump if overflow (OF == 1)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JP", AliasOf: "JPS", Summary: "Jump if parity (PF == 1)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JPC", AliasOf: "", Summary: "Jump if not parity (PF == 0)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JPE", AliasOf: "JPS", Summary: "Jump if parity (PF == 1)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JPL", AliasOf: "", Summary: "Jump if not sign (SF == 0)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JPO", AliasOf: "JPC", Summary: "Jump if not parity (PF == 0)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JPS", AliasOf: "", Summary: "Jump if parity (PF == 1)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JS", AliasOf: "JMI", Summary: "Jump if sign (SF == 1)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "JZ", AliasOf: "JEQ", Summary: "Jump if equal (ZF == 1)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rel32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "LDDQU", AliasOf: "", Summary: "Load Unaligned Integer 128 Bits", Forms: []inst.Form{inst.Form{ISA: []string{"SSE3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "LDMXCSR", AliasOf: "", Summary: "Load MXCSR Register", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "LEAL", AliasOf: "", Summary: "Load Effective Address", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "LEAQ", AliasOf: "", Summary: "Load Effective Address", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "LEAW", AliasOf: "", Summary: "Load Effective Address", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "LFENCE", AliasOf: "", Summary: "Load Fence", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "LZCNTL", AliasOf: "", Summary: "Count the Number of Leading Zero Bits", Forms: []inst.Form{inst.Form{ISA: []string{"LZCNT"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"LZCNT"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "LZCNTQ", AliasOf: "", Summary: "Count the Number of Leading Zero Bits", Forms: []inst.Form{inst.Form{ISA: []string{"LZCNT"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"LZCNT"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "LZCNTW", AliasOf: "", Summary: "Count the Number of Leading Zero Bits", Forms: []inst.Form{inst.Form{ISA: []string{"LZCNT"}, Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"LZCNT"}, Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MASKMOVDQU", AliasOf: "MASKMOVOU", Summary: "Store Selected Bytes of Double Quadword", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "rdi", Action: 0x1}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "MASKMOVOU", AliasOf: "", Summary: "Store Selected Bytes of Double Quadword", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "rdi", Action: 0x1}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "MAXPD", AliasOf: "", Summary: "Return Maximum Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MAXPS", AliasOf: "", Summary: "Return Maximum Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MAXSD", AliasOf: "", Summary: "Return Maximum Scalar Double-Precision Floating-Point Value", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MAXSS", AliasOf: "", Summary: "Return Maximum Scalar Single-Precision Floating-Point Value", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MFENCE", AliasOf: "", Summary: "Memory Fence", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MINPD", AliasOf: "", Summary: "Return Minimum Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MINPS", AliasOf: "", Summary: "Return Minimum Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MINSD", AliasOf: "", Summary: "Return Minimum Scalar Double-Precision Floating-Point Value", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MINSS", AliasOf: "", Summary: "Return Minimum Scalar Single-Precision Floating-Point Value", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MONITOR", AliasOf: "", Summary: "Monitor a Linear Address Range", Forms: []inst.Form{inst.Form{ISA: []string{"MONITOR"}, Operands: []inst.Operand{}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "rax", Action: 0x1}, inst.ImplicitOperand{Register: "ecx", Action: 0x1}, inst.ImplicitOperand{Register: "edx", Action: 0x1}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVAPD", AliasOf: "", Summary: "Move Aligned Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVAPS", AliasOf: "", Summary: "Move Aligned Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVB", AliasOf: "", Summary: "Move", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}, inst.Operand{Type: "r8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x1}, inst.Operand{Type: "r8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}, inst.Operand{Type: "m8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVBELL", AliasOf: "", Summary: "Move Data After Swapping Bytes", Forms: []inst.Form{inst.Form{ISA: []string{"MOVBE"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"MOVBE"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVBEQQ", AliasOf: "", Summary: "Move Data After Swapping Bytes", Forms: []inst.Form{inst.Form{ISA: []string{"MOVBE"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"MOVBE"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVBEWW", AliasOf: "", Summary: "Move Data After Swapping Bytes", Forms: []inst.Form{inst.Form{ISA: []string{"MOVBE"}, Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"MOVBE"}, Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "m16", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVBLSX", AliasOf: "", Summary: "Move with Sign-Extension", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVBLZX", AliasOf: "", Summary: "Move with Zero-Extend", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVBQSX", AliasOf: "", Summary: "Move with Sign-Extension", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVBQZX", AliasOf: "", Summary: "Move with Zero-Extend", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVBWSX", AliasOf: "", Summary: "Move with Sign-Extension", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVBWZX", AliasOf: "", Summary: "Move with Zero-Extend", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVD", AliasOf: "MOVQ", Summary: "Move", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm64", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVDDUP", AliasOf: "", Summary: "Move One Double-FP and Duplicate", Forms: []inst.Form{inst.Form{ISA: []string{"SSE3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE3"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVDQ2Q", AliasOf: "MOVQ", Summary: "Move", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm64", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVHLPS", AliasOf: "", Summary: "Move Packed Single-Precision Floating-Point Values High to Low", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVHPD", AliasOf: "", Summary: "Move High Packed Double-Precision Floating-Point Value", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVHPS", AliasOf: "", Summary: "Move High Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVL", AliasOf: "", Summary: "Move", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVLHPS", AliasOf: "", Summary: "Move Packed Single-Precision Floating-Point Values Low to High", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVLPD", AliasOf: "", Summary: "Move Low Packed Double-Precision Floating-Point Value", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVLPS", AliasOf: "", Summary: "Move Low Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVLQSX", AliasOf: "", Summary: "Move Doubleword to Quadword with Sign-Extension", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVLQZX", AliasOf: "", Summary: "Move with Zero-Extend", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVMSKPD", AliasOf: "", Summary: "Extract Packed Double-Precision Floating-Point Sign Mask", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVMSKPS", AliasOf: "", Summary: "Extract Packed Single-Precision Floating-Point Sign Mask", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVNTDQ", AliasOf: "MOVNTO", Summary: "Store Double Quadword Using Non-Temporal Hint", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVNTDQA", AliasOf: "", Summary: "Load Double Quadword Non-Temporal Aligned Hint", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVNTIL", AliasOf: "", Summary: "Store Doubleword Using Non-Temporal Hint", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVNTIQ", AliasOf: "", Summary: "Store Doubleword Using Non-Temporal Hint", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVNTO", AliasOf: "", Summary: "Store Double Quadword Using Non-Temporal Hint", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVNTPD", AliasOf: "", Summary: "Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVNTPS", AliasOf: "", Summary: "Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVO", AliasOf: "", Summary: "Move Aligned Double Quadword", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVOA", AliasOf: "MOVO", Summary: "Move Aligned Double Quadword", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVOU", AliasOf: "", Summary: "Move Unaligned Double Quadword", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVQ", AliasOf: "", Summary: "Move", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm64", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVSD", AliasOf: "", Summary: "Move Scalar Double-Precision Floating-Point Value", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVSHDUP", AliasOf: "", Summary: "Move Packed Single-FP High and Duplicate", Forms: []inst.Form{inst.Form{ISA: []string{"SSE3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVSLDUP", AliasOf: "", Summary: "Move Packed Single-FP Low and Duplicate", Forms: []inst.Form{inst.Form{ISA: []string{"SSE3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVSS", AliasOf: "", Summary: "Move Scalar Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVUPD", AliasOf: "", Summary: "Move Unaligned Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVUPS", AliasOf: "", Summary: "Move Unaligned Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVW", AliasOf: "", Summary: "Move", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm16", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm16", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "m16", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVWLSX", AliasOf: "", Summary: "Move with Sign-Extension", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVWLZX", AliasOf: "", Summary: "Move with Zero-Extend", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVWQSX", AliasOf: "", Summary: "Move with Sign-Extension", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MOVWQZX", AliasOf: "", Summary: "Move with Zero-Extend", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MPSADBW", AliasOf: "", Summary: "Compute Multiple Packed Sums of Absolute Difference", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MULB", AliasOf: "", Summary: "Unsigned Multiply", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "ax", Action: 0x2}, inst.ImplicitOperand{Register: "al", Action: 0x1}}, CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "ax", Action: 0x2}, inst.ImplicitOperand{Register: "al", Action: 0x1}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "MULL", AliasOf: "", Summary: "Unsigned Multiply", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "eax", Action: 0x3}, inst.ImplicitOperand{Register: "edx", Action: 0x2}}, CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "eax", Action: 0x3}, inst.ImplicitOperand{Register: "edx", Action: 0x2}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "MULPD", AliasOf: "", Summary: "Multiply Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MULPS", AliasOf: "", Summary: "Multiply Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MULQ", AliasOf: "", Summary: "Unsigned Multiply", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "rax", Action: 0x3}, inst.ImplicitOperand{Register: "rdx", Action: 0x2}}, CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "rax", Action: 0x3}, inst.ImplicitOperand{Register: "rdx", Action: 0x2}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "MULSD", AliasOf: "", Summary: "Multiply Scalar Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MULSS", AliasOf: "", Summary: "Multiply Scalar Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "MULW", AliasOf: "", Summary: "Unsigned Multiply", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "ax", Action: 0x3}, inst.ImplicitOperand{Register: "dx", Action: 0x2}}, CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "ax", Action: 0x3}, inst.ImplicitOperand{Register: "dx", Action: 0x2}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "MULXL", AliasOf: "", Summary: "Unsigned Multiply Without Affecting Flags", Forms: []inst.Form{inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "edx", Action: 0x1}}, CancellingInputs: false}, inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "edx", Action: 0x1}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "MULXQ", AliasOf: "", Summary: "Unsigned Multiply Without Affecting Flags", Forms: []inst.Form{inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "rdx", Action: 0x1}}, CancellingInputs: false}, inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "rdx", Action: 0x1}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "MWAIT", AliasOf: "", Summary: "Monitor Wait", Forms: []inst.Form{inst.Form{ISA: []string{"MONITOR"}, Operands: []inst.Operand{}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "eax", Action: 0x1}, inst.ImplicitOperand{Register: "ecx", Action: 0x1}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "NEGB", AliasOf: "", Summary: "Two's Complement Negation", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "NEGL", AliasOf: "", Summary: "Two's Complement Negation", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "NEGQ", AliasOf: "", Summary: "Two's Complement Negation", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "NEGW", AliasOf: "", Summary: "Two's Complement Negation", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "NOP", AliasOf: "", Summary: "No Operation", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "NOTB", AliasOf: "", Summary: "One's Complement Negation", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "NOTL", AliasOf: "", Summary: "One's Complement Negation", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "NOTQ", AliasOf: "", Summary: "One's Complement Negation", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "NOTW", AliasOf: "", Summary: "One's Complement Negation", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ORB", AliasOf: "", Summary: "Logical Inclusive OR", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "al", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x1}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ORL", AliasOf: "", Summary: "Logical Inclusive OR", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "eax", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ORPD", AliasOf: "", Summary: "Bitwise Logical OR of Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ORPS", AliasOf: "", Summary: "Bitwise Logical OR of Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ORQ", AliasOf: "", Summary: "Logical Inclusive OR", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "rax", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ORW", AliasOf: "", Summary: "Logical Inclusive OR", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm16", Action: 0x0}, inst.Operand{Type: "ax", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm16", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm16", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PABSB", AliasOf: "", Summary: "Packed Absolute Value of Byte Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PABSD", AliasOf: "", Summary: "Packed Absolute Value of Doubleword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PABSW", AliasOf: "", Summary: "Packed Absolute Value of Word Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PACKSSLW", AliasOf: "", Summary: "Pack Doublewords into Words with Signed Saturation", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PACKSSWB", AliasOf: "", Summary: "Pack Words into Bytes with Signed Saturation", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PACKUSDW", AliasOf: "", Summary: "Pack Doublewords into Words with Unsigned Saturation", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PACKUSWB", AliasOf: "", Summary: "Pack Words into Bytes with Unsigned Saturation", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PADDB", AliasOf: "", Summary: "Add Packed Byte Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PADDD", AliasOf: "PADDL", Summary: "Add Packed Doubleword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PADDL", AliasOf: "", Summary: "Add Packed Doubleword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PADDQ", AliasOf: "", Summary: "Add Packed Quadword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PADDSB", AliasOf: "", Summary: "Add Packed Signed Byte Integers with Signed Saturation", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PADDSW", AliasOf: "", Summary: "Add Packed Signed Word Integers with Signed Saturation", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PADDUSB", AliasOf: "", Summary: "Add Packed Unsigned Byte Integers with Unsigned Saturation", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PADDUSW", AliasOf: "", Summary: "Add Packed Unsigned Word Integers with Unsigned Saturation", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PADDW", AliasOf: "", Summary: "Add Packed Word Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PALIGNR", AliasOf: "", Summary: "Packed Align Right", Forms: []inst.Form{inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PAND", AliasOf: "", Summary: "Packed Bitwise Logical AND", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PANDN", AliasOf: "", Summary: "Packed Bitwise Logical AND NOT", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PAUSE", AliasOf: "", Summary: "Spin Loop Hint", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PAVGB", AliasOf: "", Summary: "Average Packed Byte Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PAVGW", AliasOf: "", Summary: "Average Packed Word Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PBLENDVB", AliasOf: "", Summary: "Variable Blend Packed Bytes", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm0", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm0", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PBLENDW", AliasOf: "", Summary: "Blend Packed Words", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PCLMULQDQ", AliasOf: "", Summary: "Carry-Less Quadword Multiplication", Forms: []inst.Form{inst.Form{ISA: []string{"PCLMULQDQ"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"PCLMULQDQ"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PCMPEQB", AliasOf: "", Summary: "Compare Packed Byte Data for Equality", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PCMPEQL", AliasOf: "", Summary: "Compare Packed Doubleword Data for Equality", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PCMPEQQ", AliasOf: "", Summary: "Compare Packed Quadword Data for Equality", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PCMPEQW", AliasOf: "", Summary: "Compare Packed Word Data for Equality", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PCMPESTRI", AliasOf: "", Summary: "Packed Compare Explicit Length Strings, Return Index", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "eax", Action: 0x1}, inst.ImplicitOperand{Register: "ecx", Action: 0x2}, inst.ImplicitOperand{Register: "edx", Action: 0x1}}, CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "eax", Action: 0x1}, inst.ImplicitOperand{Register: "ecx", Action: 0x2}, inst.ImplicitOperand{Register: "edx", Action: 0x1}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "PCMPESTRM", AliasOf: "", Summary: "Packed Compare Explicit Length Strings, Return Mask", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "eax", Action: 0x1}, inst.ImplicitOperand{Register: "edx", Action: 0x1}, inst.ImplicitOperand{Register: "xmm0", Action: 0x2}}, CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "eax", Action: 0x1}, inst.ImplicitOperand{Register: "edx", Action: 0x1}, inst.ImplicitOperand{Register: "xmm0", Action: 0x2}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "PCMPGTB", AliasOf: "", Summary: "Compare Packed Signed Byte Integers for Greater Than", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PCMPGTL", AliasOf: "", Summary: "Compare Packed Signed Doubleword Integers for Greater Than", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PCMPGTQ", AliasOf: "", Summary: "Compare Packed Data for Greater Than", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"SSE4.2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PCMPGTW", AliasOf: "", Summary: "Compare Packed Signed Word Integers for Greater Than", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PCMPISTRI", AliasOf: "", Summary: "Packed Compare Implicit Length Strings, Return Index", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "ecx", Action: 0x2}}, CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "ecx", Action: 0x2}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "PCMPISTRM", AliasOf: "", Summary: "Packed Compare Implicit Length Strings, Return Mask", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "xmm0", Action: 0x2}}, CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "xmm0", Action: 0x2}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "PDEPL", AliasOf: "", Summary: "Parallel Bits Deposit", Forms: []inst.Form{inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PDEPQ", AliasOf: "", Summary: "Parallel Bits Deposit", Forms: []inst.Form{inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PEXTL", AliasOf: "", Summary: "Parallel Bits Extract", Forms: []inst.Form{inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PEXTQ", AliasOf: "", Summary: "Parallel Bits Extract", Forms: []inst.Form{inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PEXTRB", AliasOf: "", Summary: "Extract Byte", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PEXTRD", AliasOf: "", Summary: "Extract Doubleword", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PEXTRQ", AliasOf: "", Summary: "Extract Quadword", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PEXTRW", AliasOf: "", Summary: "Extract Word", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m16", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PHADDD", AliasOf: "", Summary: "Packed Horizontal Add Doubleword Integer", Forms: []inst.Form{inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PHADDSW", AliasOf: "", Summary: "Packed Horizontal Add Signed Word Integers with Signed Saturation", Forms: []inst.Form{inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PHADDW", AliasOf: "", Summary: "Packed Horizontal Add Word Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PHMINPOSUW", AliasOf: "", Summary: "Packed Horizontal Minimum of Unsigned Word Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PHSUBD", AliasOf: "", Summary: "Packed Horizontal Subtract Doubleword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PHSUBSW", AliasOf: "", Summary: "Packed Horizontal Subtract Signed Word Integers with Signed Saturation", Forms: []inst.Form{inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PHSUBW", AliasOf: "", Summary: "Packed Horizontal Subtract Word Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PINSRB", AliasOf: "", Summary: "Insert Byte", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m8", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PINSRD", AliasOf: "", Summary: "Insert Doubleword", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PINSRQ", AliasOf: "", Summary: "Insert Quadword", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PINSRW", AliasOf: "", Summary: "Insert Word", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMADDUBSW", AliasOf: "", Summary: "Multiply and Add Packed Signed and Unsigned Byte Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMADDWL", AliasOf: "", Summary: "Multiply and Add Packed Signed Word Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMAXSB", AliasOf: "", Summary: "Maximum of Packed Signed Byte Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMAXSD", AliasOf: "", Summary: "Maximum of Packed Signed Doubleword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMAXSW", AliasOf: "", Summary: "Maximum of Packed Signed Word Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMAXUB", AliasOf: "", Summary: "Maximum of Packed Unsigned Byte Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMAXUD", AliasOf: "", Summary: "Maximum of Packed Unsigned Doubleword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMAXUW", AliasOf: "", Summary: "Maximum of Packed Unsigned Word Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMINSB", AliasOf: "", Summary: "Minimum of Packed Signed Byte Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMINSD", AliasOf: "", Summary: "Minimum of Packed Signed Doubleword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMINSW", AliasOf: "", Summary: "Minimum of Packed Signed Word Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMINUB", AliasOf: "", Summary: "Minimum of Packed Unsigned Byte Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMINUD", AliasOf: "", Summary: "Minimum of Packed Unsigned Doubleword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMINUW", AliasOf: "", Summary: "Minimum of Packed Unsigned Word Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMOVMSKB", AliasOf: "", Summary: "Move Byte Mask", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMOVSXBD", AliasOf: "", Summary: "Move Packed Byte Integers to Doubleword Integers with Sign Extension", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMOVSXBQ", AliasOf: "", Summary: "Move Packed Byte Integers to Quadword Integers with Sign Extension", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMOVSXBW", AliasOf: "", Summary: "Move Packed Byte Integers to Word Integers with Sign Extension", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMOVSXDQ", AliasOf: "", Summary: "Move Packed Doubleword Integers to Quadword Integers with Sign Extension", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMOVSXWD", AliasOf: "", Summary: "Move Packed Word Integers to Doubleword Integers with Sign Extension", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMOVSXWQ", AliasOf: "", Summary: "Move Packed Word Integers to Quadword Integers with Sign Extension", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMOVZXBD", AliasOf: "", Summary: "Move Packed Byte Integers to Doubleword Integers with Zero Extension", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMOVZXBQ", AliasOf: "", Summary: "Move Packed Byte Integers to Quadword Integers with Zero Extension", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMOVZXBW", AliasOf: "", Summary: "Move Packed Byte Integers to Word Integers with Zero Extension", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMOVZXDQ", AliasOf: "", Summary: "Move Packed Doubleword Integers to Quadword Integers with Zero Extension", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMOVZXWD", AliasOf: "", Summary: "Move Packed Word Integers to Doubleword Integers with Zero Extension", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMOVZXWQ", AliasOf: "", Summary: "Move Packed Word Integers to Quadword Integers with Zero Extension", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMULDQ", AliasOf: "", Summary: "Multiply Packed Signed Doubleword Integers and Store Quadword Result", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMULHRSW", AliasOf: "", Summary: "Packed Multiply Signed Word Integers and Store High Result with Round and Scale", Forms: []inst.Form{inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMULHUW", AliasOf: "", Summary: "Multiply Packed Unsigned Word Integers and Store High Result", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMULHW", AliasOf: "", Summary: "Multiply Packed Signed Word Integers and Store High Result", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMULLD", AliasOf: "", Summary: "Multiply Packed Signed Doubleword Integers and Store Low Result", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMULLW", AliasOf: "", Summary: "Multiply Packed Signed Word Integers and Store Low Result", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PMULULQ", AliasOf: "", Summary: "Multiply Packed Unsigned Doubleword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "POPCNTL", AliasOf: "", Summary: "Count of Number of Bits Set to 1", Forms: []inst.Form{inst.Form{ISA: []string{"POPCNT"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"POPCNT"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "POPCNTQ", AliasOf: "", Summary: "Count of Number of Bits Set to 1", Forms: []inst.Form{inst.Form{ISA: []string{"POPCNT"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"POPCNT"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "POPCNTW", AliasOf: "", Summary: "Count of Number of Bits Set to 1", Forms: []inst.Form{inst.Form{ISA: []string{"POPCNT"}, Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"POPCNT"}, Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "POPQ", AliasOf: "", Summary: "Pop a Value from the Stack", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "POPW", AliasOf: "", Summary: "Pop a Value from the Stack", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "POR", AliasOf: "", Summary: "Packed Bitwise Logical OR", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PREFETCHNTA", AliasOf: "", Summary: "Prefetch Data Into Caches using NTA Hint", Forms: []inst.Form{inst.Form{ISA: []string{"MMX+"}, Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PREFETCHT0", AliasOf: "", Summary: "Prefetch Data Into Caches using T0 Hint", Forms: []inst.Form{inst.Form{ISA: []string{"MMX+"}, Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PREFETCHT1", AliasOf: "", Summary: "Prefetch Data Into Caches using T1 Hint", Forms: []inst.Form{inst.Form{ISA: []string{"MMX+"}, Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PREFETCHT2", AliasOf: "", Summary: "Prefetch Data Into Caches using T2 Hint", Forms: []inst.Form{inst.Form{ISA: []string{"MMX+"}, Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PSADBW", AliasOf: "", Summary: "Compute Sum of Absolute Differences", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PSHUFB", AliasOf: "", Summary: "Packed Shuffle Bytes", Forms: []inst.Form{inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PSHUFD", AliasOf: "PSHUFL", Summary: "Shuffle Packed Doublewords", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PSHUFHW", AliasOf: "", Summary: "Shuffle Packed High Words", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PSHUFL", AliasOf: "", Summary: "Shuffle Packed Doublewords", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PSHUFLW", AliasOf: "", Summary: "Shuffle Packed Low Words", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PSIGNB", AliasOf: "", Summary: "Packed Sign of Byte Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PSIGND", AliasOf: "", Summary: "Packed Sign of Doubleword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PSIGNW", AliasOf: "", Summary: "Packed Sign of Word Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSSE3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PSLLDQ", AliasOf: "PSLLO", Summary: "Shift Packed Double Quadword Left Logical", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PSLLL", AliasOf: "", Summary: "Shift Packed Doubleword Data Left Logical", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PSLLO", AliasOf: "", Summary: "Shift Packed Double Quadword Left Logical", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PSLLQ", AliasOf: "", Summary: "Shift Packed Quadword Data Left Logical", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PSLLW", AliasOf: "", Summary: "Shift Packed Word Data Left Logical", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PSRAL", AliasOf: "", Summary: "Shift Packed Doubleword Data Right Arithmetic", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PSRAW", AliasOf: "", Summary: "Shift Packed Word Data Right Arithmetic", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PSRLDQ", AliasOf: "PSRLO", Summary: "Shift Packed Double Quadword Right Logical", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PSRLL", AliasOf: "", Summary: "Shift Packed Doubleword Data Right Logical", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PSRLO", AliasOf: "", Summary: "Shift Packed Double Quadword Right Logical", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PSRLQ", AliasOf: "", Summary: "Shift Packed Quadword Data Right Logical", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PSRLW", AliasOf: "", Summary: "Shift Packed Word Data Right Logical", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PSUBB", AliasOf: "", Summary: "Subtract Packed Byte Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PSUBL", AliasOf: "", Summary: "Subtract Packed Doubleword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PSUBQ", AliasOf: "", Summary: "Subtract Packed Quadword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PSUBSB", AliasOf: "", Summary: "Subtract Packed Signed Byte Integers with Signed Saturation", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PSUBSW", AliasOf: "", Summary: "Subtract Packed Signed Word Integers with Signed Saturation", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PSUBUSB", AliasOf: "", Summary: "Subtract Packed Unsigned Byte Integers with Unsigned Saturation", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PSUBUSW", AliasOf: "", Summary: "Subtract Packed Unsigned Word Integers with Unsigned Saturation", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PSUBW", AliasOf: "", Summary: "Subtract Packed Word Integers", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PTEST", AliasOf: "", Summary: "Packed Logical Compare", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PUNPCKHBW", AliasOf: "", Summary: "Unpack and Interleave High-Order Bytes into Words", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PUNPCKHLQ", AliasOf: "", Summary: "Unpack and Interleave High-Order Doublewords into Quadwords", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PUNPCKHQDQ", AliasOf: "", Summary: "Unpack and Interleave High-Order Quadwords into Double Quadwords", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PUNPCKHWL", AliasOf: "", Summary: "Unpack and Interleave High-Order Words into Doublewords", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PUNPCKLBW", AliasOf: "", Summary: "Unpack and Interleave Low-Order Bytes into Words", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PUNPCKLLQ", AliasOf: "", Summary: "Unpack and Interleave Low-Order Doublewords into Quadwords", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PUNPCKLQDQ", AliasOf: "", Summary: "Unpack and Interleave Low-Order Quadwords into Double Quadwords", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PUNPCKLWL", AliasOf: "", Summary: "Unpack and Interleave Low-Order Words into Doublewords", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PUSHQ", AliasOf: "", Summary: "Push Value Onto the Stack", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PUSHW", AliasOf: "", Summary: "Push Value Onto the Stack", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "PXOR", AliasOf: "", Summary: "Packed Bitwise Logical Exclusive OR", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "RCLB", AliasOf: "", Summary: "Rotate Left through Carry Flag", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "RCLL", AliasOf: "", Summary: "Rotate Left through Carry Flag", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "RCLQ", AliasOf: "", Summary: "Rotate Left through Carry Flag", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "RCLW", AliasOf: "", Summary: "Rotate Left through Carry Flag", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "RCPPS", AliasOf: "", Summary: "Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "RCPSS", AliasOf: "", Summary: "Compute Approximate Reciprocal of Scalar Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "RCRB", AliasOf: "", Summary: "Rotate Right through Carry Flag", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "RCRL", AliasOf: "", Summary: "Rotate Right through Carry Flag", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "RCRQ", AliasOf: "", Summary: "Rotate Right through Carry Flag", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "RCRW", AliasOf: "", Summary: "Rotate Right through Carry Flag", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "RDRANDL", AliasOf: "", Summary: "Read Random Number", Forms: []inst.Form{inst.Form{ISA: []string{"RDRAND"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "RDRANDQ", AliasOf: "", Summary: "Read Random Number", Forms: []inst.Form{inst.Form{ISA: []string{"RDRAND"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "RDRANDW", AliasOf: "", Summary: "Read Random Number", Forms: []inst.Form{inst.Form{ISA: []string{"RDRAND"}, Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "RDSEEDL", AliasOf: "", Summary: "Read Random SEED", Forms: []inst.Form{inst.Form{ISA: []string{"RDSEED"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "RDSEEDQ", AliasOf: "", Summary: "Read Random SEED", Forms: []inst.Form{inst.Form{ISA: []string{"RDSEED"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "RDSEEDW", AliasOf: "", Summary: "Read Random SEED", Forms: []inst.Form{inst.Form{ISA: []string{"RDSEED"}, Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "RDTSC", AliasOf: "", Summary: "Read Time-Stamp Counter", Forms: []inst.Form{inst.Form{ISA: []string{"RDTSC"}, Operands: []inst.Operand{}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "eax", Action: 0x2}, inst.ImplicitOperand{Register: "edx", Action: 0x2}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "RDTSCP", AliasOf: "", Summary: "Read Time-Stamp Counter and Processor ID", Forms: []inst.Form{inst.Form{ISA: []string{"RDTSCP"}, Operands: []inst.Operand{}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "eax", Action: 0x2}, inst.ImplicitOperand{Register: "ecx", Action: 0x2}, inst.ImplicitOperand{Register: "edx", Action: 0x2}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "RET", AliasOf: "", Summary: "Return from Procedure", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "RETFL", AliasOf: "", Summary: "Return from Procedure", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm16", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "RETFQ", AliasOf: "", Summary: "Return from Procedure", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm16", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "RETFW", AliasOf: "", Summary: "Return from Procedure", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm16", Action: 0x0}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ROLB", AliasOf: "", Summary: "Rotate Left", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ROLL", AliasOf: "", Summary: "Rotate Left", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ROLQ", AliasOf: "", Summary: "Rotate Left", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ROLW", AliasOf: "", Summary: "Rotate Left", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "RORB", AliasOf: "", Summary: "Rotate Right", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "RORL", AliasOf: "", Summary: "Rotate Right", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "RORQ", AliasOf: "", Summary: "Rotate Right", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "RORW", AliasOf: "", Summary: "Rotate Right", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "RORXL", AliasOf: "", Summary: "Rotate Right Logical Without Affecting Flags", Forms: []inst.Form{inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "RORXQ", AliasOf: "", Summary: "Rotate Right Logical Without Affecting Flags", Forms: []inst.Form{inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ROUNDPD", AliasOf: "", Summary: "Round Packed Double Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ROUNDPS", AliasOf: "", Summary: "Round Packed Single Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ROUNDSD", AliasOf: "", Summary: "Round Scalar Double Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "ROUNDSS", AliasOf: "", Summary: "Round Scalar Single Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE4.1"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "RSQRTPS", AliasOf: "", Summary: "Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "RSQRTSS", AliasOf: "", Summary: "Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SALB", AliasOf: "", Summary: "Arithmetic Shift Left", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SALL", AliasOf: "", Summary: "Arithmetic Shift Left", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SALQ", AliasOf: "", Summary: "Arithmetic Shift Left", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SALW", AliasOf: "", Summary: "Arithmetic Shift Left", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SARB", AliasOf: "", Summary: "Arithmetic Shift Right", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SARL", AliasOf: "", Summary: "Arithmetic Shift Right", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SARQ", AliasOf: "", Summary: "Arithmetic Shift Right", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SARW", AliasOf: "", Summary: "Arithmetic Shift Right", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SARXL", AliasOf: "", Summary: "Arithmetic Shift Right Without Affecting Flags", Forms: []inst.Form{inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SARXQ", AliasOf: "", Summary: "Arithmetic Shift Right Without Affecting Flags", Forms: []inst.Form{inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SBBB", AliasOf: "", Summary: "Subtract with Borrow", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "al", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x1}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SBBL", AliasOf: "", Summary: "Subtract with Borrow", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "eax", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SBBQ", AliasOf: "", Summary: "Subtract with Borrow", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "rax", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SBBW", AliasOf: "", Summary: "Subtract with Borrow", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm16", Action: 0x0}, inst.Operand{Type: "ax", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm16", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm16", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SETCC", AliasOf: "", Summary: "Set byte if above or equal (CF == 0)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SETCS", AliasOf: "", Summary: "Set byte if below (CF == 1)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SETEQ", AliasOf: "", Summary: "Set byte if equal (ZF == 1)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SETGE", AliasOf: "", Summary: "Set byte if greater or equal (SF == OF)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SETGT", AliasOf: "", Summary: "Set byte if greater (ZF == 0 and SF == OF)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SETHI", AliasOf: "", Summary: "Set byte if above (CF == 0 and ZF == 0)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SETLE", AliasOf: "", Summary: "Set byte if less or equal (ZF == 1 or SF != OF)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SETLS", AliasOf: "", Summary: "Set byte if below or equal (CF == 1 or ZF == 1)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SETLT", AliasOf: "", Summary: "Set byte if less (SF != OF)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SETMI", AliasOf: "", Summary: "Set byte if sign (SF == 1)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SETNE", AliasOf: "", Summary: "Set byte if not equal (ZF == 0)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SETOC", AliasOf: "", Summary: "Set byte if not overflow (OF == 0)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SETOS", AliasOf: "", Summary: "Set byte if overflow (OF == 1)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SETPC", AliasOf: "", Summary: "Set byte if not parity (PF == 0)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SETPL", AliasOf: "", Summary: "Set byte if not sign (SF == 0)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SETPS", AliasOf: "", Summary: "Set byte if parity (PF == 1)", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SFENCE", AliasOf: "", Summary: "Store Fence", Forms: []inst.Form{inst.Form{ISA: []string{"MMX+"}, Operands: []inst.Operand{}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SHA1MSG1", AliasOf: "", Summary: "Perform an Intermediate Calculation for the Next Four SHA1 Message Doublewords", Forms: []inst.Form{inst.Form{ISA: []string{"SHA"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SHA"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SHA1MSG2", AliasOf: "", Summary: "Perform a Final Calculation for the Next Four SHA1 Message Doublewords", Forms: []inst.Form{inst.Form{ISA: []string{"SHA"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SHA"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SHA1NEXTE", AliasOf: "", Summary: "Calculate SHA1 State Variable E after Four Rounds", Forms: []inst.Form{inst.Form{ISA: []string{"SHA"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SHA"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SHA1RNDS4", AliasOf: "", Summary: "Perform Four Rounds of SHA1 Operation", Forms: []inst.Form{inst.Form{ISA: []string{"SHA"}, Operands: []inst.Operand{inst.Operand{Type: "imm2u", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SHA"}, Operands: []inst.Operand{inst.Operand{Type: "imm2u", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SHA256MSG1", AliasOf: "", Summary: "Perform an Intermediate Calculation for the Next Four SHA256 Message Doublewords", Forms: []inst.Form{inst.Form{ISA: []string{"SHA"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SHA"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SHA256MSG2", AliasOf: "", Summary: "Perform a Final Calculation for the Next Four SHA256 Message Doublewords", Forms: []inst.Form{inst.Form{ISA: []string{"SHA"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SHA"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SHA256RNDS2", AliasOf: "", Summary: "Perform Two Rounds of SHA256 Operation", Forms: []inst.Form{inst.Form{ISA: []string{"SHA"}, Operands: []inst.Operand{inst.Operand{Type: "xmm0", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SHA"}, Operands: []inst.Operand{inst.Operand{Type: "xmm0", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SHLB", AliasOf: "", Summary: "Logical Shift Left", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SHLL", AliasOf: "", Summary: "Logical Shift Left", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SHLQ", AliasOf: "", Summary: "Logical Shift Left", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SHLW", AliasOf: "", Summary: "Logical Shift Left", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SHLXL", AliasOf: "", Summary: "Logical Shift Left Without Affecting Flags", Forms: []inst.Form{inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SHLXQ", AliasOf: "", Summary: "Logical Shift Left Without Affecting Flags", Forms: []inst.Form{inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SHRB", AliasOf: "", Summary: "Logical Shift Right", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SHRL", AliasOf: "", Summary: "Logical Shift Right", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SHRQ", AliasOf: "", Summary: "Logical Shift Right", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SHRW", AliasOf: "", Summary: "Logical Shift Right", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "1", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "cl", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SHRXL", AliasOf: "", Summary: "Logical Shift Right Without Affecting Flags", Forms: []inst.Form{inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SHRXQ", AliasOf: "", Summary: "Logical Shift Right Without Affecting Flags", Forms: []inst.Form{inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"BMI2"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SHUFPD", AliasOf: "", Summary: "Shuffle Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SHUFPS", AliasOf: "", Summary: "Shuffle Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SQRTPD", AliasOf: "", Summary: "Compute Square Roots of Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SQRTPS", AliasOf: "", Summary: "Compute Square Roots of Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SQRTSD", AliasOf: "", Summary: "Compute Square Root of Scalar Double-Precision Floating-Point Value", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SQRTSS", AliasOf: "", Summary: "Compute Square Root of Scalar Single-Precision Floating-Point Value", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "STC", AliasOf: "", Summary: "Set Carry Flag", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "STD", AliasOf: "", Summary: "Set Direction Flag", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "STMXCSR", AliasOf: "", Summary: "Store MXCSR Register State", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SUBB", AliasOf: "", Summary: "Subtract", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "al", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x1}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SUBL", AliasOf: "", Summary: "Subtract", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "eax", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SUBPD", AliasOf: "", Summary: "Subtract Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SUBPS", AliasOf: "", Summary: "Subtract Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SUBQ", AliasOf: "", Summary: "Subtract", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "rax", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SUBSD", AliasOf: "", Summary: "Subtract Scalar Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SUBSS", AliasOf: "", Summary: "Subtract Scalar Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SUBW", AliasOf: "", Summary: "Subtract", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm16", Action: 0x0}, inst.Operand{Type: "ax", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm16", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm16", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "SYSCALL", AliasOf: "", Summary: "Fast System Call", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "r11", Action: 0x2}, inst.ImplicitOperand{Register: "rcx", Action: 0x2}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "TESTB", AliasOf: "", Summary: "Logical Compare", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "al", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r8", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}, inst.Operand{Type: "r8", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m8", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}, inst.Operand{Type: "m8", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "TESTL", AliasOf: "", Summary: "Logical Compare", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "eax", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "TESTQ", AliasOf: "", Summary: "Logical Compare", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "rax", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "TESTW", AliasOf: "", Summary: "Logical Compare", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm16", Action: 0x0}, inst.Operand{Type: "ax", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm16", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm16", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "m16", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "TZCNTL", AliasOf: "", Summary: "Count the Number of Trailing Zero Bits", Forms: []inst.Form{inst.Form{ISA: []string{"BMI"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"BMI"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "TZCNTQ", AliasOf: "", Summary: "Count the Number of Trailing Zero Bits", Forms: []inst.Form{inst.Form{ISA: []string{"BMI"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"BMI"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "TZCNTW", AliasOf: "", Summary: "Count the Number of Trailing Zero Bits", Forms: []inst.Form{inst.Form{ISA: []string{"BMI"}, Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"BMI"}, Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "UCOMISD", AliasOf: "", Summary: "Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "UCOMISS", AliasOf: "", Summary: "Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "UD2", AliasOf: "", Summary: "Undefined Instruction", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "UNPCKHPD", AliasOf: "", Summary: "Unpack and Interleave High Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "UNPCKHPS", AliasOf: "", Summary: "Unpack and Interleave High Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "UNPCKLPD", AliasOf: "", Summary: "Unpack and Interleave Low Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "UNPCKLPS", AliasOf: "", Summary: "Unpack and Interleave Low Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VADDPD", AliasOf: "", Summary: "Add Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VADDPS", AliasOf: "", Summary: "Add Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VADDSD", AliasOf: "", Summary: "Add Scalar Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VADDSS", AliasOf: "", Summary: "Add Scalar Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VADDSUBPD", AliasOf: "", Summary: "Packed Double-FP Add/Subtract", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VADDSUBPS", AliasOf: "", Summary: "Packed Single-FP Add/Subtract", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VAESDEC", AliasOf: "", Summary: "Perform One Round of an AES Decryption Flow", Forms: []inst.Form{inst.Form{ISA: []string{"AVX", "AES"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX", "AES"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VAESDECLAST", AliasOf: "", Summary: "Perform Last Round of an AES Decryption Flow", Forms: []inst.Form{inst.Form{ISA: []string{"AVX", "AES"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX", "AES"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VAESENC", AliasOf: "", Summary: "Perform One Round of an AES Encryption Flow", Forms: []inst.Form{inst.Form{ISA: []string{"AVX", "AES"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX", "AES"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VAESENCLAST", AliasOf: "", Summary: "Perform Last Round of an AES Encryption Flow", Forms: []inst.Form{inst.Form{ISA: []string{"AVX", "AES"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX", "AES"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VAESIMC", AliasOf: "", Summary: "Perform the AES InvMixColumn Transformation", Forms: []inst.Form{inst.Form{ISA: []string{"AVX", "AES"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX", "AES"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VAESKEYGENASSIST", AliasOf: "", Summary: "AES Round Key Generation Assist", Forms: []inst.Form{inst.Form{ISA: []string{"AVX", "AES"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX", "AES"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VANDNPD", AliasOf: "", Summary: "Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VANDNPS", AliasOf: "", Summary: "Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VANDPD", AliasOf: "", Summary: "Bitwise Logical AND of Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VANDPS", AliasOf: "", Summary: "Bitwise Logical AND of Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VBLENDPD", AliasOf: "", Summary: "Blend Packed Double Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VBLENDPS", AliasOf: "", Summary: " Blend Packed Single Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VBLENDVPD", AliasOf: "", Summary: " Variable Blend Packed Double Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VBLENDVPS", AliasOf: "", Summary: " Variable Blend Packed Single Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VBROADCASTF128", AliasOf: "", Summary: "Broadcast 128 Bit of Floating-Point Data", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VBROADCASTI128", AliasOf: "", Summary: "Broadcast 128 Bits of Integer Data", Forms: []inst.Form{inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VBROADCASTSD", AliasOf: "", Summary: "Broadcast Double-Precision Floating-Point Element", Forms: []inst.Form{inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VBROADCASTSS", AliasOf: "", Summary: "Broadcast Single-Precision Floating-Point Element", Forms: []inst.Form{inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCMPPD", AliasOf: "", Summary: "Compare Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCMPPS", AliasOf: "", Summary: "Compare Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCMPSD", AliasOf: "", Summary: "Compare Scalar Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCMPSS", AliasOf: "", Summary: "Compare Scalar Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCOMISD", AliasOf: "", Summary: "Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCOMISS", AliasOf: "", Summary: "Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCVTDQ2PD", AliasOf: "", Summary: "Convert Packed Dword Integers to Packed Double-Precision FP Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCVTDQ2PS", AliasOf: "", Summary: "Convert Packed Dword Integers to Packed Single-Precision FP Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCVTPD2DQX", AliasOf: "", Summary: "Convert Packed Double-Precision FP Values to Packed Dword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCVTPD2DQY", AliasOf: "", Summary: "Convert Packed Double-Precision FP Values to Packed Dword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCVTPD2PSX", AliasOf: "", Summary: "Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCVTPD2PSY", AliasOf: "", Summary: "Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCVTPH2PS", AliasOf: "", Summary: "Convert Half-Precision FP Values to Single-Precision FP Values", Forms: []inst.Form{inst.Form{ISA: []string{"F16C"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"F16C"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"F16C"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"F16C"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCVTPS2DQ", AliasOf: "", Summary: "Convert Packed Single-Precision FP Values to Packed Dword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCVTPS2PD", AliasOf: "", Summary: "Convert Packed Single-Precision FP Values to Packed Double-Precision FP Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCVTPS2PH", AliasOf: "", Summary: "Convert Single-Precision FP value to Half-Precision FP value", Forms: []inst.Form{inst.Form{ISA: []string{"F16C"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"F16C"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"F16C"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"F16C"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCVTSD2SI", AliasOf: "", Summary: "Convert Scalar Double-Precision FP Value to Integer", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCVTSD2SIQ", AliasOf: "", Summary: "Convert Scalar Double-Precision FP Value to Integer", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCVTSD2SS", AliasOf: "", Summary: "Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCVTSI2SDL", AliasOf: "", Summary: "Convert Dword Integer to Scalar Double-Precision FP Value", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCVTSI2SDQ", AliasOf: "", Summary: "Convert Dword Integer to Scalar Double-Precision FP Value", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCVTSI2SSL", AliasOf: "", Summary: "Convert Dword Integer to Scalar Single-Precision FP Value", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCVTSI2SSQ", AliasOf: "", Summary: "Convert Dword Integer to Scalar Single-Precision FP Value", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCVTSS2SD", AliasOf: "", Summary: "Convert Scalar Single-Precision FP Value to Scalar Double-Precision FP Value", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCVTSS2SI", AliasOf: "", Summary: "Convert Scalar Single-Precision FP Value to Dword Integer", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCVTSS2SIQ", AliasOf: "", Summary: "Convert Scalar Single-Precision FP Value to Dword Integer", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCVTTPD2DQX", AliasOf: "", Summary: "Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCVTTPD2DQY", AliasOf: "", Summary: "Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCVTTPS2DQ", AliasOf: "", Summary: "Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCVTTSD2SI", AliasOf: "", Summary: "Convert with Truncation Scalar Double-Precision FP Value to Signed Integer", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCVTTSD2SIQ", AliasOf: "", Summary: "Convert with Truncation Scalar Double-Precision FP Value to Signed Integer", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCVTTSS2SI", AliasOf: "", Summary: "Convert with Truncation Scalar Single-Precision FP Value to Dword Integer", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VCVTTSS2SIQ", AliasOf: "", Summary: "Convert with Truncation Scalar Single-Precision FP Value to Dword Integer", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VDIVPD", AliasOf: "", Summary: "Divide Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VDIVPS", AliasOf: "", Summary: "Divide Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VDIVSD", AliasOf: "", Summary: "Divide Scalar Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VDIVSS", AliasOf: "", Summary: "Divide Scalar Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VDPPD", AliasOf: "", Summary: "Dot Product of Packed Double Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VDPPS", AliasOf: "", Summary: "Dot Product of Packed Single Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VEXTRACTF128", AliasOf: "", Summary: "Extract Packed Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VEXTRACTI128", AliasOf: "", Summary: "Extract Packed Integer Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VEXTRACTPS", AliasOf: "", Summary: "Extract Packed Single Precision Floating-Point Value", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMADD132PD", AliasOf: "", Summary: "Fused Multiply-Add of Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMADD132PS", AliasOf: "", Summary: "Fused Multiply-Add of Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMADD132SD", AliasOf: "", Summary: "Fused Multiply-Add of Scalar Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMADD132SS", AliasOf: "", Summary: "Fused Multiply-Add of Scalar Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMADD213PD", AliasOf: "", Summary: "Fused Multiply-Add of Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMADD213PS", AliasOf: "", Summary: "Fused Multiply-Add of Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMADD213SD", AliasOf: "", Summary: "Fused Multiply-Add of Scalar Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMADD213SS", AliasOf: "", Summary: "Fused Multiply-Add of Scalar Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMADD231PD", AliasOf: "", Summary: "Fused Multiply-Add of Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMADD231PS", AliasOf: "", Summary: "Fused Multiply-Add of Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMADD231SD", AliasOf: "", Summary: "Fused Multiply-Add of Scalar Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMADD231SS", AliasOf: "", Summary: "Fused Multiply-Add of Scalar Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMADDSUB132PD", AliasOf: "", Summary: "Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMADDSUB132PS", AliasOf: "", Summary: "Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMADDSUB213PD", AliasOf: "", Summary: "Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMADDSUB213PS", AliasOf: "", Summary: "Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMADDSUB231PD", AliasOf: "", Summary: "Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMADDSUB231PS", AliasOf: "", Summary: "Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMSUB132PD", AliasOf: "", Summary: "Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMSUB132PS", AliasOf: "", Summary: "Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMSUB132SD", AliasOf: "", Summary: "Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMSUB132SS", AliasOf: "", Summary: "Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMSUB213PD", AliasOf: "", Summary: "Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMSUB213PS", AliasOf: "", Summary: "Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMSUB213SD", AliasOf: "", Summary: "Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMSUB213SS", AliasOf: "", Summary: "Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMSUB231PD", AliasOf: "", Summary: "Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMSUB231PS", AliasOf: "", Summary: "Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMSUB231SD", AliasOf: "", Summary: "Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMSUB231SS", AliasOf: "", Summary: "Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMSUBADD132PD", AliasOf: "", Summary: "Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMSUBADD132PS", AliasOf: "", Summary: "Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMSUBADD213PD", AliasOf: "", Summary: "Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMSUBADD213PS", AliasOf: "", Summary: "Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMSUBADD231PD", AliasOf: "", Summary: "Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFMSUBADD231PS", AliasOf: "", Summary: "Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFNMADD132PD", AliasOf: "", Summary: "Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFNMADD132PS", AliasOf: "", Summary: "Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFNMADD132SD", AliasOf: "", Summary: "Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFNMADD132SS", AliasOf: "", Summary: "Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFNMADD213PD", AliasOf: "", Summary: "Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFNMADD213PS", AliasOf: "", Summary: "Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFNMADD213SD", AliasOf: "", Summary: "Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFNMADD213SS", AliasOf: "", Summary: "Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFNMADD231PD", AliasOf: "", Summary: "Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFNMADD231PS", AliasOf: "", Summary: "Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFNMADD231SD", AliasOf: "", Summary: "Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFNMADD231SS", AliasOf: "", Summary: "Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFNMSUB132PD", AliasOf: "", Summary: "Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFNMSUB132PS", AliasOf: "", Summary: "Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFNMSUB132SD", AliasOf: "", Summary: "Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFNMSUB132SS", AliasOf: "", Summary: "Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFNMSUB213PD", AliasOf: "", Summary: "Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFNMSUB213PS", AliasOf: "", Summary: "Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFNMSUB213SD", AliasOf: "", Summary: "Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFNMSUB213SS", AliasOf: "", Summary: "Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFNMSUB231PD", AliasOf: "", Summary: "Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFNMSUB231PS", AliasOf: "", Summary: "Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFNMSUB231SD", AliasOf: "", Summary: "Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VFNMSUB231SS", AliasOf: "", Summary: "Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"FMA3"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VGATHERDPD", AliasOf: "", Summary: "Gather Packed Double-Precision Floating-Point Values Using Signed Doubleword Indices", Forms: []inst.Form{inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x3}, inst.Operand{Type: "vm32x", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x3}, inst.Operand{Type: "vm32x", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VGATHERDPS", AliasOf: "", Summary: "Gather Packed Single-Precision Floating-Point Values Using Signed Doubleword Indices", Forms: []inst.Form{inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x3}, inst.Operand{Type: "vm32x", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x3}, inst.Operand{Type: "vm32y", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VGATHERQPD", AliasOf: "", Summary: "Gather Packed Double-Precision Floating-Point Values Using Signed Quadword Indices", Forms: []inst.Form{inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x3}, inst.Operand{Type: "vm64x", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x3}, inst.Operand{Type: "vm64y", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VGATHERQPS", AliasOf: "", Summary: "Gather Packed Single-Precision Floating-Point Values Using Signed Quadword Indices", Forms: []inst.Form{inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x3}, inst.Operand{Type: "vm64x", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x3}, inst.Operand{Type: "vm64y", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VHADDPD", AliasOf: "", Summary: "Packed Double-FP Horizontal Add", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VHADDPS", AliasOf: "", Summary: "Packed Single-FP Horizontal Add", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VHSUBPD", AliasOf: "", Summary: "Packed Double-FP Horizontal Subtract", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VHSUBPS", AliasOf: "", Summary: "Packed Single-FP Horizontal Subtract", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VINSERTF128", AliasOf: "", Summary: "Insert Packed Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VINSERTI128", AliasOf: "", Summary: "Insert Packed Integer Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VINSERTPS", AliasOf: "", Summary: "Insert Packed Single Precision Floating-Point Value", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VLDDQU", AliasOf: "", Summary: "Load Unaligned Integer 128 Bits", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VLDMXCSR", AliasOf: "", Summary: "Load MXCSR Register", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMASKMOVDQU", AliasOf: "", Summary: "Store Selected Bytes of Double Quadword", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "rdi", Action: 0x1}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "VMASKMOVPD", AliasOf: "", Summary: "Conditional Move Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "m256", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMASKMOVPS", AliasOf: "", Summary: "Conditional Move Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "m256", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMAXPD", AliasOf: "", Summary: "Return Maximum Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMAXPS", AliasOf: "", Summary: "Return Maximum Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMAXSD", AliasOf: "", Summary: "Return Maximum Scalar Double-Precision Floating-Point Value", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMAXSS", AliasOf: "", Summary: "Return Maximum Scalar Single-Precision Floating-Point Value", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMINPD", AliasOf: "", Summary: "Return Minimum Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMINPS", AliasOf: "", Summary: "Return Minimum Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMINSD", AliasOf: "", Summary: "Return Minimum Scalar Double-Precision Floating-Point Value", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMINSS", AliasOf: "", Summary: "Return Minimum Scalar Single-Precision Floating-Point Value", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMOVAPD", AliasOf: "", Summary: "Move Aligned Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "m256", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMOVAPS", AliasOf: "", Summary: "Move Aligned Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "m256", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMOVD", AliasOf: "", Summary: "Move Doubleword", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMOVDDUP", AliasOf: "", Summary: "Move One Double-FP and Duplicate", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMOVDQA", AliasOf: "", Summary: "Move Aligned Double Quadword", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "m256", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMOVDQU", AliasOf: "", Summary: "Move Unaligned Double Quadword", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "m256", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMOVHLPS", AliasOf: "", Summary: "Move Packed Single-Precision Floating-Point Values High to Low", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMOVHPD", AliasOf: "", Summary: "Move High Packed Double-Precision Floating-Point Value", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMOVHPS", AliasOf: "", Summary: "Move High Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMOVLHPS", AliasOf: "", Summary: "Move Packed Single-Precision Floating-Point Values Low to High", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMOVLPD", AliasOf: "", Summary: "Move Low Packed Double-Precision Floating-Point Value", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMOVLPS", AliasOf: "", Summary: "Move Low Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMOVMSKPD", AliasOf: "", Summary: "Extract Packed Double-Precision Floating-Point Sign Mask", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMOVMSKPS", AliasOf: "", Summary: "Extract Packed Single-Precision Floating-Point Sign Mask", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMOVNTDQ", AliasOf: "", Summary: "Store Double Quadword Using Non-Temporal Hint", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "m256", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMOVNTDQA", AliasOf: "", Summary: "Load Double Quadword Non-Temporal Aligned Hint", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMOVNTPD", AliasOf: "", Summary: "Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "m256", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMOVNTPS", AliasOf: "", Summary: "Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "m256", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMOVQ", AliasOf: "", Summary: "Move Quadword", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMOVSD", AliasOf: "", Summary: "Move Scalar Double-Precision Floating-Point Value", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMOVSHDUP", AliasOf: "", Summary: "Move Packed Single-FP High and Duplicate", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMOVSLDUP", AliasOf: "", Summary: "Move Packed Single-FP Low and Duplicate", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMOVSS", AliasOf: "", Summary: "Move Scalar Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMOVUPD", AliasOf: "", Summary: "Move Unaligned Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "m256", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMOVUPS", AliasOf: "", Summary: "Move Unaligned Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "m256", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMPSADBW", AliasOf: "", Summary: "Compute Multiple Packed Sums of Absolute Difference", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMULPD", AliasOf: "", Summary: "Multiply Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMULPS", AliasOf: "", Summary: "Multiply Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMULSD", AliasOf: "", Summary: "Multiply Scalar Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VMULSS", AliasOf: "", Summary: "Multiply Scalar Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VORPD", AliasOf: "", Summary: "Bitwise Logical OR of Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VORPS", AliasOf: "", Summary: "Bitwise Logical OR of Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPABSB", AliasOf: "", Summary: "Packed Absolute Value of Byte Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPABSD", AliasOf: "", Summary: "Packed Absolute Value of Doubleword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPABSW", AliasOf: "", Summary: "Packed Absolute Value of Word Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPACKSSDW", AliasOf: "", Summary: "Pack Doublewords into Words with Signed Saturation", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPACKSSWB", AliasOf: "", Summary: "Pack Words into Bytes with Signed Saturation", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPACKUSDW", AliasOf: "", Summary: "Pack Doublewords into Words with Unsigned Saturation", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPACKUSWB", AliasOf: "", Summary: "Pack Words into Bytes with Unsigned Saturation", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPADDB", AliasOf: "", Summary: "Add Packed Byte Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPADDD", AliasOf: "", Summary: "Add Packed Doubleword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPADDQ", AliasOf: "", Summary: "Add Packed Quadword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPADDSB", AliasOf: "", Summary: "Add Packed Signed Byte Integers with Signed Saturation", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPADDSW", AliasOf: "", Summary: "Add Packed Signed Word Integers with Signed Saturation", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPADDUSB", AliasOf: "", Summary: "Add Packed Unsigned Byte Integers with Unsigned Saturation", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPADDUSW", AliasOf: "", Summary: "Add Packed Unsigned Word Integers with Unsigned Saturation", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPADDW", AliasOf: "", Summary: "Add Packed Word Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPALIGNR", AliasOf: "", Summary: "Packed Align Right", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPAND", AliasOf: "", Summary: "Packed Bitwise Logical AND", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPANDN", AliasOf: "", Summary: "Packed Bitwise Logical AND NOT", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPAVGB", AliasOf: "", Summary: "Average Packed Byte Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPAVGW", AliasOf: "", Summary: "Average Packed Word Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPBLENDD", AliasOf: "", Summary: "Blend Packed Doublewords", Forms: []inst.Form{inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPBLENDVB", AliasOf: "", Summary: "Variable Blend Packed Bytes", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPBLENDW", AliasOf: "", Summary: "Blend Packed Words", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPBROADCASTB", AliasOf: "", Summary: "Broadcast Byte Integer", Forms: []inst.Form{inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPBROADCASTD", AliasOf: "", Summary: "Broadcast Doubleword Integer", Forms: []inst.Form{inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPBROADCASTQ", AliasOf: "", Summary: "Broadcast Quadword Integer", Forms: []inst.Form{inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPBROADCASTW", AliasOf: "", Summary: "Broadcast Word Integer", Forms: []inst.Form{inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPCLMULQDQ", AliasOf: "", Summary: "Carry-Less Quadword Multiplication", Forms: []inst.Form{inst.Form{ISA: []string{"AVX", "PCLMULQDQ"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX", "PCLMULQDQ"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPCMPEQB", AliasOf: "", Summary: "Compare Packed Byte Data for Equality", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPCMPEQD", AliasOf: "", Summary: "Compare Packed Doubleword Data for Equality", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPCMPEQQ", AliasOf: "", Summary: "Compare Packed Quadword Data for Equality", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPCMPEQW", AliasOf: "", Summary: "Compare Packed Word Data for Equality", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPCMPESTRI", AliasOf: "", Summary: "Packed Compare Explicit Length Strings, Return Index", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "eax", Action: 0x1}, inst.ImplicitOperand{Register: "ecx", Action: 0x2}, inst.ImplicitOperand{Register: "edx", Action: 0x1}}, CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "eax", Action: 0x1}, inst.ImplicitOperand{Register: "ecx", Action: 0x2}, inst.ImplicitOperand{Register: "edx", Action: 0x1}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "VPCMPESTRM", AliasOf: "", Summary: "Packed Compare Explicit Length Strings, Return Mask", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "eax", Action: 0x1}, inst.ImplicitOperand{Register: "edx", Action: 0x1}, inst.ImplicitOperand{Register: "xmm0", Action: 0x2}}, CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "eax", Action: 0x1}, inst.ImplicitOperand{Register: "edx", Action: 0x1}, inst.ImplicitOperand{Register: "xmm0", Action: 0x2}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "VPCMPGTB", AliasOf: "", Summary: "Compare Packed Signed Byte Integers for Greater Than", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPCMPGTD", AliasOf: "", Summary: "Compare Packed Signed Doubleword Integers for Greater Than", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPCMPGTQ", AliasOf: "", Summary: "Compare Packed Data for Greater Than", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPCMPGTW", AliasOf: "", Summary: "Compare Packed Signed Word Integers for Greater Than", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPCMPISTRI", AliasOf: "", Summary: "Packed Compare Implicit Length Strings, Return Index", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "ecx", Action: 0x2}}, CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "ecx", Action: 0x2}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "VPCMPISTRM", AliasOf: "", Summary: "Packed Compare Implicit Length Strings, Return Mask", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "xmm0", Action: 0x2}}, CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "xmm0", Action: 0x2}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "VPERM2F128", AliasOf: "", Summary: "Permute Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPERM2I128", AliasOf: "", Summary: "Permute 128-Bit Integer Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPERMD", AliasOf: "", Summary: "Permute Doubleword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPERMILPD", AliasOf: "", Summary: "Permute Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPERMILPS", AliasOf: "", Summary: "Permute Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPERMPD", AliasOf: "", Summary: "Permute Double-Precision Floating-Point Elements", Forms: []inst.Form{inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPERMPS", AliasOf: "", Summary: "Permute Single-Precision Floating-Point Elements", Forms: []inst.Form{inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPERMQ", AliasOf: "", Summary: "Permute Quadword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPEXTRB", AliasOf: "", Summary: "Extract Byte", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m8", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPEXTRD", AliasOf: "", Summary: "Extract Doubleword", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPEXTRQ", AliasOf: "", Summary: "Extract Quadword", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPEXTRW", AliasOf: "", Summary: "Extract Word", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m16", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPGATHERDD", AliasOf: "", Summary: "Gather Packed Doubleword Values Using Signed Doubleword Indices", Forms: []inst.Form{inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x3}, inst.Operand{Type: "vm32x", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x3}, inst.Operand{Type: "vm32y", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPGATHERDQ", AliasOf: "", Summary: "Gather Packed Quadword Values Using Signed Doubleword Indices", Forms: []inst.Form{inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x3}, inst.Operand{Type: "vm32x", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x3}, inst.Operand{Type: "vm32x", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPGATHERQD", AliasOf: "", Summary: "Gather Packed Doubleword Values Using Signed Quadword Indices", Forms: []inst.Form{inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x3}, inst.Operand{Type: "vm64x", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x3}, inst.Operand{Type: "vm64y", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPGATHERQQ", AliasOf: "", Summary: "Gather Packed Quadword Values Using Signed Quadword Indices", Forms: []inst.Form{inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x3}, inst.Operand{Type: "vm64x", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x3}, inst.Operand{Type: "vm64y", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPHADDD", AliasOf: "", Summary: "Packed Horizontal Add Doubleword Integer", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPHADDSW", AliasOf: "", Summary: "Packed Horizontal Add Signed Word Integers with Signed Saturation", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPHADDW", AliasOf: "", Summary: "Packed Horizontal Add Word Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPHMINPOSUW", AliasOf: "", Summary: "Packed Horizontal Minimum of Unsigned Word Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPHSUBD", AliasOf: "", Summary: "Packed Horizontal Subtract Doubleword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPHSUBSW", AliasOf: "", Summary: "Packed Horizontal Subtract Signed Word Integers with Signed Saturation", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPHSUBW", AliasOf: "", Summary: "Packed Horizontal Subtract Word Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPINSRB", AliasOf: "", Summary: "Insert Byte", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m8", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPINSRD", AliasOf: "", Summary: "Insert Doubleword", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPINSRQ", AliasOf: "", Summary: "Insert Quadword", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPINSRW", AliasOf: "", Summary: "Insert Word", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMADDUBSW", AliasOf: "", Summary: "Multiply and Add Packed Signed and Unsigned Byte Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMADDWD", AliasOf: "", Summary: "Multiply and Add Packed Signed Word Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMASKMOVD", AliasOf: "", Summary: "Conditional Move Packed Doubleword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "m256", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMASKMOVQ", AliasOf: "", Summary: "Conditional Move Packed Quadword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "m128", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "m256", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMAXSB", AliasOf: "", Summary: "Maximum of Packed Signed Byte Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMAXSD", AliasOf: "", Summary: "Maximum of Packed Signed Doubleword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMAXSW", AliasOf: "", Summary: "Maximum of Packed Signed Word Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMAXUB", AliasOf: "", Summary: "Maximum of Packed Unsigned Byte Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMAXUD", AliasOf: "", Summary: "Maximum of Packed Unsigned Doubleword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMAXUW", AliasOf: "", Summary: "Maximum of Packed Unsigned Word Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMINSB", AliasOf: "", Summary: "Minimum of Packed Signed Byte Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMINSD", AliasOf: "", Summary: "Minimum of Packed Signed Doubleword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMINSW", AliasOf: "", Summary: "Minimum of Packed Signed Word Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMINUB", AliasOf: "", Summary: "Minimum of Packed Unsigned Byte Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMINUD", AliasOf: "", Summary: "Minimum of Packed Unsigned Doubleword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMINUW", AliasOf: "", Summary: "Minimum of Packed Unsigned Word Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMOVMSKB", AliasOf: "", Summary: "Move Byte Mask", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMOVSXBD", AliasOf: "", Summary: "Move Packed Byte Integers to Doubleword Integers with Sign Extension", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMOVSXBQ", AliasOf: "", Summary: "Move Packed Byte Integers to Quadword Integers with Sign Extension", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMOVSXBW", AliasOf: "", Summary: "Move Packed Byte Integers to Word Integers with Sign Extension", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMOVSXDQ", AliasOf: "", Summary: "Move Packed Doubleword Integers to Quadword Integers with Sign Extension", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMOVSXWD", AliasOf: "", Summary: "Move Packed Word Integers to Doubleword Integers with Sign Extension", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMOVSXWQ", AliasOf: "", Summary: "Move Packed Word Integers to Quadword Integers with Sign Extension", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMOVZXBD", AliasOf: "", Summary: "Move Packed Byte Integers to Doubleword Integers with Zero Extension", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMOVZXBQ", AliasOf: "", Summary: "Move Packed Byte Integers to Quadword Integers with Zero Extension", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMOVZXBW", AliasOf: "", Summary: "Move Packed Byte Integers to Word Integers with Zero Extension", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMOVZXDQ", AliasOf: "", Summary: "Move Packed Doubleword Integers to Quadword Integers with Zero Extension", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMOVZXWD", AliasOf: "", Summary: "Move Packed Word Integers to Doubleword Integers with Zero Extension", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMOVZXWQ", AliasOf: "", Summary: "Move Packed Word Integers to Quadword Integers with Zero Extension", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMULDQ", AliasOf: "", Summary: "Multiply Packed Signed Doubleword Integers and Store Quadword Result", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMULHRSW", AliasOf: "", Summary: "Packed Multiply Signed Word Integers and Store High Result with Round and Scale", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMULHUW", AliasOf: "", Summary: "Multiply Packed Unsigned Word Integers and Store High Result", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMULHW", AliasOf: "", Summary: "Multiply Packed Signed Word Integers and Store High Result", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMULLD", AliasOf: "", Summary: "Multiply Packed Signed Doubleword Integers and Store Low Result", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMULLW", AliasOf: "", Summary: "Multiply Packed Signed Word Integers and Store Low Result", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPMULUDQ", AliasOf: "", Summary: "Multiply Packed Unsigned Doubleword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPOR", AliasOf: "", Summary: "Packed Bitwise Logical OR", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPSADBW", AliasOf: "", Summary: "Compute Sum of Absolute Differences", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPSHUFB", AliasOf: "", Summary: "Packed Shuffle Bytes", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPSHUFD", AliasOf: "", Summary: "Shuffle Packed Doublewords", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPSHUFHW", AliasOf: "", Summary: "Shuffle Packed High Words", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPSHUFLW", AliasOf: "", Summary: "Shuffle Packed Low Words", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPSIGNB", AliasOf: "", Summary: "Packed Sign of Byte Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPSIGND", AliasOf: "", Summary: "Packed Sign of Doubleword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPSIGNW", AliasOf: "", Summary: "Packed Sign of Word Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPSLLD", AliasOf: "", Summary: "Shift Packed Doubleword Data Left Logical", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPSLLDQ", AliasOf: "", Summary: "Shift Packed Double Quadword Left Logical", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPSLLQ", AliasOf: "", Summary: "Shift Packed Quadword Data Left Logical", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPSLLVD", AliasOf: "", Summary: "Variable Shift Packed Doubleword Data Left Logical", Forms: []inst.Form{inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPSLLVQ", AliasOf: "", Summary: "Variable Shift Packed Quadword Data Left Logical", Forms: []inst.Form{inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPSLLW", AliasOf: "", Summary: "Shift Packed Word Data Left Logical", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPSRAD", AliasOf: "", Summary: "Shift Packed Doubleword Data Right Arithmetic", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPSRAVD", AliasOf: "", Summary: "Variable Shift Packed Doubleword Data Right Arithmetic", Forms: []inst.Form{inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPSRAW", AliasOf: "", Summary: "Shift Packed Word Data Right Arithmetic", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPSRLD", AliasOf: "", Summary: "Shift Packed Doubleword Data Right Logical", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPSRLDQ", AliasOf: "", Summary: "Shift Packed Double Quadword Right Logical", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPSRLQ", AliasOf: "", Summary: "Shift Packed Quadword Data Right Logical", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPSRLVD", AliasOf: "", Summary: "Variable Shift Packed Doubleword Data Right Logical", Forms: []inst.Form{inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPSRLVQ", AliasOf: "", Summary: "Variable Shift Packed Quadword Data Right Logical", Forms: []inst.Form{inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPSRLW", AliasOf: "", Summary: "Shift Packed Word Data Right Logical", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPSUBB", AliasOf: "", Summary: "Subtract Packed Byte Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPSUBD", AliasOf: "", Summary: "Subtract Packed Doubleword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPSUBQ", AliasOf: "", Summary: "Subtract Packed Quadword Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPSUBSB", AliasOf: "", Summary: "Subtract Packed Signed Byte Integers with Signed Saturation", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPSUBSW", AliasOf: "", Summary: "Subtract Packed Signed Word Integers with Signed Saturation", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPSUBUSB", AliasOf: "", Summary: "Subtract Packed Unsigned Byte Integers with Unsigned Saturation", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPSUBUSW", AliasOf: "", Summary: "Subtract Packed Unsigned Word Integers with Unsigned Saturation", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPSUBW", AliasOf: "", Summary: "Subtract Packed Word Integers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPTEST", AliasOf: "", Summary: "Packed Logical Compare", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPUNPCKHBW", AliasOf: "", Summary: "Unpack and Interleave High-Order Bytes into Words", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPUNPCKHDQ", AliasOf: "", Summary: "Unpack and Interleave High-Order Doublewords into Quadwords", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPUNPCKHQDQ", AliasOf: "", Summary: "Unpack and Interleave High-Order Quadwords into Double Quadwords", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPUNPCKHWD", AliasOf: "", Summary: "Unpack and Interleave High-Order Words into Doublewords", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPUNPCKLBW", AliasOf: "", Summary: "Unpack and Interleave Low-Order Bytes into Words", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPUNPCKLDQ", AliasOf: "", Summary: "Unpack and Interleave Low-Order Doublewords into Quadwords", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPUNPCKLQDQ", AliasOf: "", Summary: "Unpack and Interleave Low-Order Quadwords into Double Quadwords", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPUNPCKLWD", AliasOf: "", Summary: "Unpack and Interleave Low-Order Words into Doublewords", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VPXOR", AliasOf: "", Summary: "Packed Bitwise Logical Exclusive OR", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX2"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VRCPPS", AliasOf: "", Summary: "Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VRCPSS", AliasOf: "", Summary: "Compute Approximate Reciprocal of Scalar Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VROUNDPD", AliasOf: "", Summary: "Round Packed Double Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VROUNDPS", AliasOf: "", Summary: "Round Packed Single Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VROUNDSD", AliasOf: "", Summary: "Round Scalar Double Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VROUNDSS", AliasOf: "", Summary: "Round Scalar Single Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VRSQRTPS", AliasOf: "", Summary: "Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VRSQRTSS", AliasOf: "", Summary: "Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VSHUFPD", AliasOf: "", Summary: "Shuffle Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VSHUFPS", AliasOf: "", Summary: "Shuffle Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VSQRTPD", AliasOf: "", Summary: "Compute Square Roots of Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VSQRTPS", AliasOf: "", Summary: "Compute Square Roots of Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VSQRTSD", AliasOf: "", Summary: "Compute Square Root of Scalar Double-Precision Floating-Point Value", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VSQRTSS", AliasOf: "", Summary: "Compute Square Root of Scalar Single-Precision Floating-Point Value", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VSTMXCSR", AliasOf: "", Summary: "Store MXCSR Register State", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VSUBPD", AliasOf: "", Summary: "Subtract Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VSUBPS", AliasOf: "", Summary: "Subtract Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VSUBSD", AliasOf: "", Summary: "Subtract Scalar Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VSUBSS", AliasOf: "", Summary: "Subtract Scalar Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VTESTPD", AliasOf: "", Summary: "Packed Double-Precision Floating-Point Bit Test", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VTESTPS", AliasOf: "", Summary: "Packed Single-Precision Floating-Point Bit Test", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VUCOMISD", AliasOf: "", Summary: "Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VUCOMISS", AliasOf: "", Summary: "Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VUNPCKHPD", AliasOf: "", Summary: "Unpack and Interleave High Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VUNPCKHPS", AliasOf: "", Summary: "Unpack and Interleave High Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VUNPCKLPD", AliasOf: "", Summary: "Unpack and Interleave Low Packed Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VUNPCKLPS", AliasOf: "", Summary: "Unpack and Interleave Low Packed Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VXORPD", AliasOf: "", Summary: "Bitwise Logical XOR for Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VXORPS", AliasOf: "", Summary: "Bitwise Logical XOR for Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{inst.Operand{Type: "m256", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x1}, inst.Operand{Type: "ymm", Action: 0x2}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VZEROALL", AliasOf: "", Summary: "Zero All YMM Registers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "VZEROUPPER", AliasOf: "", Summary: "Zero Upper Bits of YMM Registers", Forms: []inst.Form{inst.Form{ISA: []string{"AVX"}, Operands: []inst.Operand{}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "XADDB", AliasOf: "", Summary: "Exchange and Add", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x3}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x3}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "XADDL", AliasOf: "", Summary: "Exchange and Add", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x3}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x3}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "XADDQ", AliasOf: "", Summary: "Exchange and Add", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x3}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x3}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "XADDW", AliasOf: "", Summary: "Exchange and Add", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x3}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x3}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "XCHGB", AliasOf: "", Summary: "Exchange Register/Memory with Register", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x3}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x3}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x3}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "XCHGL", AliasOf: "", Summary: "Exchange Register/Memory with Register", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x3}, inst.Operand{Type: "eax", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "eax", Action: 0x3}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x3}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x3}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x3}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "XCHGQ", AliasOf: "", Summary: "Exchange Register/Memory with Register", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x3}, inst.Operand{Type: "rax", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "rax", Action: 0x3}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x3}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x3}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x3}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "XCHGW", AliasOf: "", Summary: "Exchange Register/Memory with Register", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x3}, inst.Operand{Type: "ax", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "ax", Action: 0x3}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x3}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x3}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x3}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "XGETBV", AliasOf: "", Summary: "Get Value of Extended Control Register", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "eax", Action: 0x2}, inst.ImplicitOperand{Register: "ecx", Action: 0x1}, inst.ImplicitOperand{Register: "edx", Action: 0x2}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "XLAT", AliasOf: "", Summary: "Table Look-up Translation", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{}, ImplicitOperands: []inst.ImplicitOperand{inst.ImplicitOperand{Register: "al", Action: 0x3}, inst.ImplicitOperand{Register: "ebx", Action: 0x1}}, CancellingInputs: false}}}, inst.Instruction{Opcode: "XORB", AliasOf: "", Summary: "Logical Exclusive OR", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "al", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m8", Action: 0x1}, inst.Operand{Type: "r8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r8", Action: 0x1}, inst.Operand{Type: "m8", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "XORL", AliasOf: "", Summary: "Logical Exclusive OR", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "eax", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m32", Action: 0x1}, inst.Operand{Type: "r32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r32", Action: 0x1}, inst.Operand{Type: "m32", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "XORPD", AliasOf: "", Summary: "Bitwise Logical XOR for Double-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"SSE2"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "XORPS", AliasOf: "", Summary: "Bitwise Logical XOR for Single-Precision Floating-Point Values", Forms: []inst.Form{inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "xmm", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string{"SSE"}, Operands: []inst.Operand{inst.Operand{Type: "m128", Action: 0x1}, inst.Operand{Type: "xmm", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "XORQ", AliasOf: "", Summary: "Logical Exclusive OR", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "rax", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m64", Action: 0x1}, inst.Operand{Type: "r64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm32", Action: 0x0}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r64", Action: 0x1}, inst.Operand{Type: "m64", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}, inst.Instruction{Opcode: "XORW", AliasOf: "", Summary: "Logical Exclusive OR", Forms: []inst.Form{inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm16", Action: 0x0}, inst.Operand{Type: "ax", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm16", Action: 0x0}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: true}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "m16", Action: 0x1}, inst.Operand{Type: "r16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm8", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "imm16", Action: 0x0}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}, inst.Form{ISA: []string(nil), Operands: []inst.Operand{inst.Operand{Type: "r16", Action: 0x1}, inst.Operand{Type: "m16", Action: 0x3}}, ImplicitOperands: []inst.ImplicitOperand(nil), CancellingInputs: false}}}} - -func TestVerifyInstructionsList(t *testing.T) { - if !reflect.DeepEqual(raw, inst.Instructions) { - t.Fatal("bad code generation for instructions list") - } -} diff --git a/internal/load/load.go b/internal/load/load.go index 1fc5bd8c..7170d878 100644 --- a/internal/load/load.go +++ b/internal/load/load.go @@ -1,8 +1,11 @@ package load import ( + "errors" + "fmt" "path/filepath" "reflect" + "regexp" "sort" "strconv" "strings" @@ -12,6 +15,18 @@ import ( "github.com/mmcloughlin/avo/internal/opcodesxml" ) +// This file is a mess. Some of this complexity is unavoidable, since the state +// of x86 instruction databases is also a mess, especially when it comes to +// idiosyncrasies of the Go assembler implementation. Some of the complexity is +// probably avoidable by migrating to using Intel XED +// (https://github.com/mmcloughlin/avo/issues/23), but for now this is an unholy +// mix of PeachPy's Opcodes database and Go's x86 CSV file. +// +// The goal is simply to keep as much of the uglyness in this file as possible, +// producing a clean instruction database for the rest of avo to use. Any nasty +// logic here should be backed up with a test somewhere to ensure the result is +// correct, even if the code that produced it is awful. + // Expected data source filenames. const ( DefaultCSVName = "x86.v0.2.csv" @@ -64,7 +79,8 @@ func (l *Loader) Load() ([]inst.Instruction, error) { Summary: i.Summary, } } - im[opcode].Forms = append(im[opcode].Forms, l.form(opcode, f)) + forms := l.forms(opcode, f) + im[opcode].Forms = append(im[opcode].Forms, forms...) } } } @@ -94,7 +110,15 @@ func (l *Loader) Load() ([]inst.Instruction, error) { i.Forms = dedupe(i.Forms) } - // Convert to a slice, sorted by opcode. + // Resolve forms that have VEX and EVEX encoded forms. + for _, i := range im { + i.Forms, err = vexevex(i.Forms) + if err != nil { + return nil, err + } + } + + // Convert to a slice. Sort instructions and forms for reproducibility. is := make([]inst.Instruction, 0, len(im)) for _, i := range im { is = append(is, *i) @@ -104,6 +128,10 @@ func (l *Loader) Load() ([]inst.Instruction, error) { return is[i].Opcode < is[j].Opcode }) + for _, i := range im { + sortforms(i.Forms) + } + return is, nil } @@ -132,6 +160,9 @@ func (l Loader) include(f opcodesxml.Form) bool { // AMD-only. case "TBM", "CLZERO", "FMA4", "XOP", "SSE4A", "3dnow!", "3dnow!+": return false + // AVX512PF doesn't work without some special case handling, and is only on Knights Landing/Knights Mill. + case "AVX512PF": + return false // Incomplete support for some prefetching instructions. case "PREFETCH", "PREFETCHW", "PREFETCHWT1", "CLWB": return false @@ -139,11 +170,6 @@ func (l Loader) include(f opcodesxml.Form) bool { case "MONITORX", "FEMMS": return false } - - // TODO(mbm): support AVX512 - if strings.HasPrefix(isa.ID, "AVX512") { - return false - } } // Go appears to have skeleton support for MMX instructions. See the many TODO lines in the testcases: @@ -277,32 +303,12 @@ func (l Loader) gonames(f opcodesxml.Form) []string { n := strings.ToUpper(f.GASName) // Some need data sizes added to them. - // TODO(mbm): is there a better way of determining which ones these are? - suffix := map[int]string{16: "W", 32: "L", 64: "Q", 128: "X", 256: "Y"} - switch n { - case "VCVTUSI2SS", "VCVTSD2USI", "VCVTSS2USI", "VCVTUSI2SD", "VCVTTSS2USI", "VCVTTSD2USI": - fallthrough - case "MOVBEW", "MOVBEL", "MOVBEQ": - // MOVEBE* instructions seem to be inconsistent with x86 CSV. - // - // Reference: https://github.com/golang/arch/blob/b19384d3c130858bb31a343ea8fce26be71b5998/x86/x86spec/format.go#L282-L287 - // - // "MOVBE r16, m16": "movbeww", - // "MOVBE m16, r16": "movbeww", - // "MOVBE m32, r32": "movbell", - // "MOVBE r32, m32": "movbell", - // "MOVBE m64, r64": "movbeqq", - // "MOVBE r64, m64": "movbeqq", - // - fallthrough - case "RDRAND", "RDSEED": - n += suffix[s] - } + n += sizesuffix(n, f) return []string{n} } -func (l Loader) form(opcode string, f opcodesxml.Form) inst.Form { +func (l Loader) forms(opcode string, f opcodesxml.Form) []inst.Form { // Map operands to avo format and ensure correct order. ops := operands(f.Operands) @@ -357,13 +363,36 @@ func (l Loader) form(opcode string, f opcodesxml.Form) inst.Form { for _, isa := range f.ISA { isas = append(isas, isa.ID) } + sort.Strings(isas) - return inst.Form{ + // Initialize form. + form := inst.Form{ ISA: isas, Operands: ops, ImplicitOperands: implicits, + EncodingType: enctype(f), CancellingInputs: f.CancellingInputs, } + + // Apply modification stages to produce final list of forms. + stages := []func(string, inst.Form) []inst.Form{ + avx512rounding, + avx512sae, + avx512bcst, + avx512masking, + avx512zeroing, + } + + forms := []inst.Form{form} + for _, stage := range stages { + var next []inst.Form + for _, f := range forms { + next = append(next, stage(opcode, f)...) + } + forms = next + } + + return forms } // operands maps Opcodes XML operands to avo format. Returned in Intel order. @@ -384,6 +413,187 @@ func operand(op opcodesxml.Operand) inst.Operand { } } +// avx512rounding handles AVX-512 embedded rounding. Opcodes database represents +// these as {er} operands, whereas Go uses instruction suffixes. Remove the +// operand if present and set the corresponding flag. +func avx512rounding(opcode string, f inst.Form) []inst.Form { + i, found := findoperand(f.Operands, "{er}") + if !found { + return []inst.Form{f} + } + + // Delete the {er} operand. + f.Operands = append(f.Operands[:i], f.Operands[i+1:]...) + + // Create a second form with the rounding flag. + er := f.Clone() + er.EmbeddedRounding = true + + return []inst.Form{f, er} +} + +// avx512sae handles AVX-512 "suppress all exceptions". Opcodes database +// represents these as {sae} operands, whereas Go uses instruction suffixes. +// Remove the operand if present and set the corresponding flag. +func avx512sae(opcode string, f inst.Form) []inst.Form { + i, found := findoperand(f.Operands, "{sae}") + if !found { + return []inst.Form{f} + } + + // Delete the {sae} operand. + f.Operands = append(f.Operands[:i], f.Operands[i+1:]...) + + // Create a second form with the rounding flag. + sae := f.Clone() + sae.SuppressAllExceptions = true + + return []inst.Form{f, sae} +} + +// avx512bcst handles AVX-512 broadcast. Opcodes database uses operands like +// "m512/m64bcst" to indicate broadcast. Go uses the BCST suffix to enable it. +// Split the form into two, the regular and broadcast versions. +func avx512bcst(opcode string, f inst.Form) []inst.Form { + // Look for broadcast operand. + idx := -1 + for i, op := range f.Operands { + if bcstrx.MatchString(op.Type) { + idx = i + break + } + } + + if idx < 0 { + return []inst.Form{f} + } + + // Create two forms. + match := bcstrx.FindStringSubmatch(f.Operands[idx].Type) + + mem := f.Clone() + mem.Operands[idx].Type = match[1] + + bcst := f.Clone() + bcst.Broadcast = true + bcst.Operands[idx].Type = match[2] + + return []inst.Form{mem, bcst} +} + +var bcstrx = regexp.MustCompile(`^(m\d+)/(m\d+)bcst$`) + +// avx512masking handles AVX-512 masking forms. +func avx512masking(opcode string, f inst.Form) []inst.Form { + // In order to support implicit masking (with K0), Go has two instruction + // forms, one with the mask and one without. The mask register precedes the + // output register. The Opcodes database (similar to Intel manuals) + // represents masking with the {k} operand suffix, possibly with {z} for + // zeroing. + + // Look for masking with possible zeroing. Zeroing is handled by a later + // processing stage, but we need to be sure to notice and preserve it here. + masking := false + zeroing := false + idx := -1 + for i := range f.Operands { + op := &f.Operands[i] + if strings.HasSuffix(op.Type, "{z}") { + zeroing = true + op.Type = strings.TrimSuffix(op.Type, "{z}") + } + if strings.HasSuffix(op.Type, "{k}") { + masking = true + idx = i + op.Type = strings.TrimSuffix(op.Type, "{k}") + break + } + } + + // Bail if no masking. + if !masking { + return []inst.Form{f} + } + + // Unmasked variant. + unmasked := f.Clone() + + // Masked form has "k" operand inserted. + masked := f.Clone() + mask := inst.Operand{Type: "k", Action: inst.R} + ops := append([]inst.Operand(nil), masked.Operands[:idx]...) + ops = append(ops, mask) + ops = append(ops, masked.Operands[idx:]...) + masked.Operands = ops + + // Restore zeroing suffix, so it can he handled later. + if zeroing { + masked.Operands[idx+1].Type += "{z}" + } + + // Almost all instructions take an optional mask, apart from a few + // special cases. + if maskrequired[opcode] { + return []inst.Form{masked} + } + return []inst.Form{unmasked, masked} +} + +// avx512zeroing handles AVX-512 zeroing forms. +func avx512zeroing(opcode string, f inst.Form) []inst.Form { + // Zeroing in Go is handled with the Z opcode suffix. Note that zeroing has + // an important effect on the instruction form, since the merge masking form + // has an input dependency for the output register, and the zeroing form + // does not. + + // Look for zeroing operand. + idx := -1 + for i := range f.Operands { + op := &f.Operands[i] + if strings.HasSuffix(op.Type, "{z}") { + idx = i + op.Type = strings.TrimSuffix(op.Type, "{z}") + } + } + + if idx < 0 { + return []inst.Form{f} + } + + // Duplicate into two forms for merging and zeroing. + merging := f.Clone() + merging.Operands[idx].Action |= inst.R + + zeroing := f.Clone() + zeroing.Zeroing = true + + return []inst.Form{merging, zeroing} +} + +// findoperand looks for an operand type and returns its index, if found. +func findoperand(ops []inst.Operand, t string) (int, bool) { + for i, op := range ops { + if op.Type == t { + return i, true + } + } + return 0, false +} + +// enctype selects the encoding type for the instruction form. +func enctype(f opcodesxml.Form) inst.EncodingType { + switch { + case f.Encoding.EVEX != nil: + return inst.EncodingTypeEVEX + case f.Encoding.VEX != nil: + return inst.EncodingTypeVEX + case f.Encoding.REX != nil: + return inst.EncodingTypeREX + default: + return inst.EncodingTypeLegacy + } +} + // datasize (intelligently) guesses the datasize of an instruction form. func datasize(f opcodesxml.Form) int { // Determine from encoding bits. @@ -413,6 +623,220 @@ func operandsize(op opcodesxml.Operand) int { return 0 } +// sizesuffix returns an optional size suffix to be added to the opcode name. +func sizesuffix(n string, f opcodesxml.Form) string { + // Reference: https://github.com/golang/arch/blob/5de9028c2478e6cb4e1c1b1f4386f3f0a93e383a/x86/x86avxgen/main.go#L275-L322 + // + // func addGoSuffixes(ctx *context) { + // var opcodeSuffixMatchers map[string][]string + // { + // opXY := []string{"VL=0", "X", "VL=1", "Y"} + // opXYZ := []string{"VL=0", "X", "VL=1", "Y", "VL=2", "Z"} + // opQ := []string{"REXW=1", "Q"} + // opLQ := []string{"REXW=0", "L", "REXW=1", "Q"} + // + // opcodeSuffixMatchers = map[string][]string{ + // "VCVTPD2DQ": opXY, + // "VCVTPD2PS": opXY, + // "VCVTTPD2DQ": opXY, + // "VCVTQQ2PS": opXY, + // "VCVTUQQ2PS": opXY, + // "VCVTPD2UDQ": opXY, + // "VCVTTPD2UDQ": opXY, + // + // "VFPCLASSPD": opXYZ, + // "VFPCLASSPS": opXYZ, + // + // "VCVTSD2SI": opQ, + // "VCVTTSD2SI": opQ, + // "VCVTTSS2SI": opQ, + // "VCVTSS2SI": opQ, + // + // "VCVTSD2USI": opLQ, + // "VCVTSS2USI": opLQ, + // "VCVTTSD2USI": opLQ, + // "VCVTTSS2USI": opLQ, + // "VCVTUSI2SD": opLQ, + // "VCVTUSI2SS": opLQ, + // "VCVTSI2SD": opLQ, + // "VCVTSI2SS": opLQ, + // "ANDN": opLQ, + // "BEXTR": opLQ, + // "BLSI": opLQ, + // "BLSMSK": opLQ, + // "BLSR": opLQ, + // "BZHI": opLQ, + // "MULX": opLQ, + // "PDEP": opLQ, + // "PEXT": opLQ, + // "RORX": opLQ, + // "SARX": opLQ, + // "SHLX": opLQ, + // "SHRX": opLQ, + // } + // } + // + + type rule struct { + Size func(opcodesxml.Form) int + Suffix map[int]string + } + + var ( + XY = rule{evexLLsize, map[int]string{128: "X", 256: "Y"}} + XYZ = rule{evexLLsize, map[int]string{128: "X", 256: "Y", 512: "Z"}} + Q = rule{rexWsize, map[int]string{64: "Q"}} + LQ = rule{rexWsize, map[int]string{32: "L", 64: "Q"}} + WLQ = rule{datasize, map[int]string{16: "W", 32: "L", 64: "Q"}} + ) + + rules := map[string]rule{ + "VCVTPD2DQ": XY, + "VCVTPD2PS": XY, + "VCVTTPD2DQ": XY, + "VCVTQQ2PS": XY, + "VCVTUQQ2PS": XY, + "VCVTPD2UDQ": XY, + "VCVTTPD2UDQ": XY, + + "VFPCLASSPD": XYZ, + "VFPCLASSPS": XYZ, + + "VCVTSD2SI": Q, + "VCVTTSD2SI": Q, + "VCVTTSS2SI": Q, + "VCVTSS2SI": Q, + + "VCVTSD2USI": LQ, + "VCVTSS2USI": LQ, + "VCVTTSD2USI": LQ, + "VCVTTSS2USI": LQ, + "VCVTUSI2SD": LQ, + "VCVTUSI2SS": LQ, + "VCVTSI2SD": LQ, + "VCVTSI2SS": LQ, + "ANDN": LQ, + "BEXTR": LQ, + "BLSI": LQ, + "BLSMSK": LQ, + "BLSR": LQ, + "BZHI": LQ, + "MULX": LQ, + "PDEP": LQ, + "PEXT": LQ, + "RORX": LQ, + "SARX": LQ, + "SHLX": LQ, + "SHRX": LQ, + + "RDRAND": LQ, + "RDSEED": LQ, + + // MOVEBE* instructions seem to be inconsistent with x86 CSV. + // + // Reference: https://github.com/golang/arch/blob/b19384d3c130858bb31a343ea8fce26be71b5998/x86/x86spec/format.go#L282-L287 + // + // "MOVBE r16, m16": "movbeww", + // "MOVBE m16, r16": "movbeww", + // "MOVBE m32, r32": "movbell", + // "MOVBE r32, m32": "movbell", + // "MOVBE m64, r64": "movbeqq", + // "MOVBE r64, m64": "movbeqq", + // + "MOVBEW": WLQ, + "MOVBEL": WLQ, + "MOVBEQ": WLQ, + } + + r, ok := rules[n] + if !ok { + return "" + } + + s := r.Size(f) + return r.Suffix[s] +} + +func rexWsize(f opcodesxml.Form) int { + e := f.Encoding + switch { + case e.EVEX != nil && e.EVEX.W != nil: + return 32 << *e.EVEX.W + default: + return 32 + } +} + +func evexLLsize(f opcodesxml.Form) int { + e := f.Encoding + if e.EVEX == nil { + return 0 + } + size := map[string]int{"00": 128, "01": 256, "10": 512} + return size[e.EVEX.LL] +} + +// vexevex fixes instructions that have both VEX and EVEX encoded forms with the +// same operand types. Go uses the VEX encoded form unless EVEX-only features +// are used. This function will only keep the VEX encoded version in the case +// where both exist. +// +// Note this is somewhat of a hack. There are real reasons to use the EVEX +// encoded version even when both exist. The main reason to use the EVEX version +// rather than VEX is to use the registers Z16, Z17, ... and up. However, avo +// does not implement the logic to distinguish between the two halfs of the +// vector registers. So in its current state the only reason to need the EVEX +// version is to encode suffixes, and these are represented by other instruction +// forms. +// +// TODO(mbm): restrict use of vector registers https://github.com/mmcloughlin/avo/issues/146 +func vexevex(fs []inst.Form) ([]inst.Form, error) { + // Group forms by deduping ID. + byid := map[string][]inst.Form{} + for _, f := range fs { + id := fmt.Sprintf( + "%s {%t,%t,%t,%t}", + strings.Join(f.Signature(), "_"), + f.Zeroing, + f.EmbeddedRounding, + f.SuppressAllExceptions, + f.Broadcast, + ) + byid[id] = append(byid[id], f) + } + + // Resolve overlaps. + var results []inst.Form + for id, group := range byid { + if len(group) < 2 { + results = append(results, group...) + continue + } + + // We expect these conflicts are caused by VEX/EVEX pairs. Bail if it's + // something else. + if len(group) > 2 { + return nil, fmt.Errorf("more than two forms of type %q", id) + } + + if group[0].EncodingType == inst.EncodingTypeEVEX { + group[0], group[1] = group[1], group[0] + } + + if group[0].EncodingType != inst.EncodingTypeVEX || group[1].EncodingType != inst.EncodingTypeEVEX { + fmt.Println(group) + return nil, errors.New("expected pair of VEX/EVEX encoded forms") + } + + vex := group[0] + + // In this case we only keep the VEX encoded form. + results = append(results, vex) + } + + return results, nil +} + // dedupe a list of forms. func dedupe(fs []inst.Form) []inst.Form { uniq := make([]inst.Form, 0, len(fs)) @@ -430,3 +854,14 @@ func dedupe(fs []inst.Form) []inst.Form { } return uniq } + +// sortforms sorts a list of forms +func sortforms(fs []inst.Form) { + sort.Slice(fs, func(i, j int) bool { + return sortkey(fs[i]) < sortkey(fs[j]) + }) +} + +func sortkey(f inst.Form) string { + return fmt.Sprintf("%d %v %v", f.EncodingType, f.ISA, f) +} diff --git a/internal/load/tables.go b/internal/load/tables.go index d00c9500..67ac40be 100644 --- a/internal/load/tables.go +++ b/internal/load/tables.go @@ -95,6 +95,54 @@ func init() { aliases = append(aliases, annoyingaliases...) } +// maskrequired is a set of AVX-512 opcodes where the mask register is required. +// Usually the mask register can be omitted, in which case K0 is implied. +var maskrequired = map[string]bool{ + // Reference: https://github.com/golang/go/blob/4fd94558820100129b98f284e21b19fc27a99926/src/cmd/internal/obj/x86/asm6.go#L4219-L4240 + // + // // Checks to warn about instruction/arguments combinations that + // // will unconditionally trigger illegal instruction trap (#UD). + // switch p.As { + // case AVGATHERDPD, + // AVGATHERQPD, + // AVGATHERDPS, + // AVGATHERQPS, + // AVPGATHERDD, + // AVPGATHERQD, + // AVPGATHERDQ, + // AVPGATHERQQ: + // // AVX512 gather requires explicit K mask. + // if p.GetFrom3().Reg >= REG_K0 && p.GetFrom3().Reg <= REG_K7 { + // if !avx512gatherValid(ctxt, p) { + // return + // } + // } else { + // if !avx2gatherValid(ctxt, p) { + // return + // } + // } + // } + // + "VGATHERDPD": true, + "VGATHERQPD": true, + "VGATHERDPS": true, + "VGATHERQPS": true, + "VPGATHERDD": true, + "VPGATHERQD": true, + "VPGATHERDQ": true, + "VPGATHERQQ": true, + + // Restriction applies to SCATTER instructions too. + "VPSCATTERDD": true, + "VPSCATTERDQ": true, + "VPSCATTERQD": true, + "VPSCATTERQQ": true, + "VSCATTERDPD": true, + "VSCATTERDPS": true, + "VSCATTERQPD": true, + "VSCATTERQPS": true, +} + // extras is simply a list of extra instructions to add to the database. var extras = []*inst.Instruction{ // MOVLQZX does not appear in either x86 CSV or Opcodes, but does appear in stdlib assembly. diff --git a/internal/prnt/printer.go b/internal/prnt/printer.go index 904d1b2f..cc9e89ef 100644 --- a/internal/prnt/printer.go +++ b/internal/prnt/printer.go @@ -75,6 +75,11 @@ func (g *Generator) Comment(lines ...string) { } } +// BuildTag outputs a build tag. +func (g *Generator) BuildTag(tag string) { + g.Comment("+build " + tag) +} + // AddError records an error in code generation. The first non-nil error will // prevent printing operations from writing anything else, and the error will be // returned from Result(). diff --git a/ir/ir.go b/ir/ir.go index 6fb92169..74b20348 100644 --- a/ir/ir.go +++ b/ir/ir.go @@ -37,6 +37,7 @@ func NewComment(lines ...string) *Comment { // Instruction is a single instruction in a function. type Instruction struct { Opcode string + Suffixes []string Operands []operand.Op Inputs []operand.Op @@ -61,6 +62,15 @@ type Instruction struct { func (i *Instruction) node() {} +// OpcodeWithSuffixes returns the full opcode, including dot-separated suffixes. +func (i *Instruction) OpcodeWithSuffixes() string { + opcode := i.Opcode + for _, s := range i.Suffixes { + opcode += "." + s + } + return opcode +} + // IsUnconditionalBranch reports whether i is an unconditional branch. func (i Instruction) IsUnconditionalBranch() bool { return i.IsBranch && !i.IsConditional diff --git a/operand/checks.go b/operand/checks.go index 28de231d..ba1760bb 100644 --- a/operand/checks.go +++ b/operand/checks.go @@ -131,6 +131,16 @@ func IsYMM(op Op) bool { return IsRegisterKindSize(op, reg.KindVector, 32) } +// IsZMM returns true if op is a 512-bit ZMM register. +func IsZMM(op Op) bool { + return IsRegisterKindSize(op, reg.KindVector, 64) +} + +// IsK returns true if op is an Opmask register. +func IsK(op Op) bool { + return IsRegisterKind(op, reg.KindOpmask) +} + // IsRegisterKindSize returns true if op is a register of the given kind and size in bytes. func IsRegisterKindSize(op Op, k reg.Kind, n uint) bool { r, ok := op.(reg.Register) @@ -200,6 +210,12 @@ func IsM256(op Op) bool { return IsM64(op) } +// IsM512 returns true if op is a 512-bit memory operand. +func IsM512(op Op) bool { + // TODO(mbm): should "m512" be the same as "m64"? + return IsM64(op) +} + // IsVM32X returns true if op is a vector memory operand with 32-bit XMM index. func IsVM32X(op Op) bool { return IsVmx(op) @@ -230,6 +246,21 @@ func IsVmy(op Op) bool { return isvm(op, IsYMM) } +// IsVM32Z returns true if op is a vector memory operand with 32-bit ZMM index. +func IsVM32Z(op Op) bool { + return IsVmz(op) +} + +// IsVM64Z returns true if op is a vector memory operand with 64-bit ZMM index. +func IsVM64Z(op Op) bool { + return IsVmz(op) +} + +// IsVmz returns true if op is a vector memory operand with ZMM index. +func IsVmz(op Op) bool { + return isvm(op, IsZMM) +} + func isvm(op Op, idx func(Op) bool) bool { m, ok := op.(Mem) return ok && IsR64(m.Base) && idx(m.Index) diff --git a/operand/checks_test.go b/operand/checks_test.go index 1d35df5f..37063e05 100644 --- a/operand/checks_test.go +++ b/operand/checks_test.go @@ -127,6 +127,9 @@ func TestChecks(t *testing.T) { {IsM256, Mem{Base: reg.RBX, Index: reg.R12, Scale: 2}, true}, {IsM256, Mem{Base: reg.X0}, false}, + {IsM512, Mem{Base: reg.RBX, Index: reg.R12, Scale: 2}, true}, + {IsM512, Mem{Base: reg.X0}, false}, + // Argument references (special cases of memory operands) {IsM, NewParamAddr("foo", 4), true}, {IsM8, NewParamAddr("foo", 4), true}, @@ -151,6 +154,14 @@ func TestChecks(t *testing.T) { {IsVM64Y, Mem{Base: reg.R11L, Index: reg.Y11}, false}, {IsVM64Y, Mem{Base: reg.R8, Index: reg.Z11}, false}, + {IsVM32Z, Mem{Base: reg.R9, Index: reg.Z11}, true}, + {IsVM32Z, Mem{Base: reg.R11L, Index: reg.Z11}, false}, + {IsVM32Z, Mem{Base: reg.R8, Index: reg.Y11}, false}, + + {IsVM64Z, Mem{Base: reg.R9, Index: reg.Z11}, true}, + {IsVM64Z, Mem{Base: reg.R11L, Index: reg.Z11}, false}, + {IsVM64Z, Mem{Base: reg.R8, Index: reg.X11}, false}, + // Relative operands {IsREL8, Rel(math.MinInt8), true}, {IsREL8, Rel(math.MaxInt8), true}, diff --git a/printer/goasm.go b/printer/goasm.go index 66b8485f..23f5b2f7 100644 --- a/printer/goasm.go +++ b/printer/goasm.go @@ -132,17 +132,18 @@ func (p *goasm) flush() { // considered in this calculation. width := 0 for _, i := range p.instructions { - if len(i.Operands) > 0 && len(i.Opcode) > width { - width = len(i.Opcode) + opcode := i.OpcodeWithSuffixes() + if len(i.Operands) > 0 && len(opcode) > width { + width = len(opcode) } } // Output instruction block. for _, i := range p.instructions { if len(i.Operands) > 0 { - p.Printf("\t%-*s%s\n", width+1, i.Opcode, joinOperands(i.Operands)) + p.Printf("\t%-*s%s\n", width+1, i.OpcodeWithSuffixes(), joinOperands(i.Operands)) } else { - p.Printf("\t%s\n", i.Opcode) + p.Printf("\t%s\n", i.OpcodeWithSuffixes()) } } diff --git a/printer/goasm_test.go b/printer/goasm_test.go index c974a2fb..e8b4fe1e 100644 --- a/printer/goasm_test.go +++ b/printer/goasm_test.go @@ -117,3 +117,21 @@ func TestAlignmentNoOperands(t *testing.T) { "", }) } + +func TestOpcodeSuffixes(t *testing.T) { + ctx := build.NewContext() + ctx.Function("suffixes") + ctx.SignatureExpr("func()") + ctx.VADDPD_RD_SAE_Z(reg.Z1, reg.Z2, reg.K1, reg.Z3) + ctx.ADDQ(reg.RAX, reg.RBX) + + AssertPrintsLines(t, ctx, printer.NewGoAsm, []string{ + "// Code generated by avo. DO NOT EDIT.", + "", + "// func suffixes()", + "TEXT ·suffixes(SB), $0", + "\tVADDPD.RD_SAE.Z Z1, Z2, K1, Z3", + "\tADDQ AX, BX", // suffixes count towards alignment width + "", + }) +} diff --git a/reg/collection.go b/reg/collection.go index d35c3a03..d1a744d9 100644 --- a/reg/collection.go +++ b/reg/collection.go @@ -52,3 +52,6 @@ func (c *Collection) ZMM() VecVirtual { return c.Vec(S512) } // Vec allocates and returns a vector register of the given width. func (c *Collection) Vec(s Spec) VecVirtual { return newvecv(c.VirtualRegister(KindVector, s)) } + +// K allocates and returns an opmask register. +func (c *Collection) K() OpmaskVirtual { return newopmaskv(c.VirtualRegister(KindOpmask, S64)) } diff --git a/reg/reg_test.go b/reg/reg_test.go index 07e0b8c3..aec40d90 100644 --- a/reg/reg_test.go +++ b/reg/reg_test.go @@ -19,6 +19,7 @@ func TestIDIsVirtual(t *testing.T) { cases := []Virtual{ GeneralPurpose.Virtual(42, S64), Vector.Virtual(42, S128), + Opmask.Virtual(42, S64), } for _, r := range cases { if !r.ID().IsVirtual() { @@ -28,7 +29,7 @@ func TestIDIsVirtual(t *testing.T) { } func TestIDIsPhysical(t *testing.T) { - cases := []Physical{AL, AH, AX, EAX, RAX, X1, Y2, Z31} + cases := []Physical{AL, AH, AX, EAX, RAX, X1, Y2, Z31, K1} for _, r := range cases { if !r.ID().IsPhysical() { t.FailNow() @@ -98,6 +99,9 @@ func TestFamilyLookup(t *testing.T) { {Vector, 27, S512, Z27}, {Vector, 1, S16, nil}, {Vector, 299, S256, nil}, + {Opmask, 1, S64, K1}, + {Opmask, 8, S64, nil}, + {Opmask, 0, S64, K0}, } for _, c := range cases { got := c.Family.Lookup(c.ID, c.Spec) @@ -156,6 +160,8 @@ func TestLookupPhysical(t *testing.T) { {KindVector, 7, S128, X7}, {KindVector, 17, S256, Y17}, {KindVector, 27, S512, Z27}, + + {KindOpmask, 1, S64, K1}, } for _, c := range cases { if got := LookupPhysical(c.Kind, c.Index, c.Spec); !Equal(got, c.Expect) { @@ -165,7 +171,7 @@ func TestLookupPhysical(t *testing.T) { } func TestLookupIDSelf(t *testing.T) { - cases := []Physical{AL, AH, AX, EAX, RAX, X1, Y2, Z31} + cases := []Physical{AL, AH, AX, EAX, RAX, X1, Y2, Z31, K1} for _, r := range cases { if got := LookupID(r.ID(), r.spec()); !Equal(got, r) { t.FailNow() diff --git a/reg/x86.go b/reg/x86.go index a911671b..1cf68d15 100644 --- a/reg/x86.go +++ b/reg/x86.go @@ -5,6 +5,7 @@ const ( KindPseudo Kind = iota KindGP KindVector + KindOpmask ) // Declare register families. @@ -12,11 +13,13 @@ var ( Pseudo = &Family{Kind: KindPseudo} GeneralPurpose = &Family{Kind: KindGP} Vector = &Family{Kind: KindVector} + Opmask = &Family{Kind: KindOpmask} Families = []*Family{ Pseudo, GeneralPurpose, Vector, + Opmask, } ) @@ -329,3 +332,52 @@ var ( Z30 = vec(S512, 30, "Z30") Z31 = vec(S512, 31, "Z31") ) + +// OpmaskPhysical is a opmask physical register. +type OpmaskPhysical interface { + Physical +} + +type opmaskp struct { + Physical +} + +func newopmaskp(r Physical) OpmaskPhysical { return opmaskp{Physical: r} } + +// OpmaskVirtual is a virtual opmask register. +type OpmaskVirtual interface { + Virtual +} + +type opmaskv struct { + Virtual +} + +func newopmaskv(v Virtual) OpmaskVirtual { return opmaskv{Virtual: v} } + +func opmask(s Spec, id Index, name string, flags ...Info) OpmaskPhysical { + r := newopmaskp(newregister(Opmask, s, id, name, flags...)) + Opmask.add(r) + return r +} + +// Opmask registers. +// +// Note that while K0 is a physical opmask register (it is a valid opmask source +// and destination operand), it cannot be used as an opmask predicate value +// because in that context K0 means "all true" or "no mask" regardless of the +// actual contents of the physical register. For that reason, K0 should never be +// assigned as a "general purpose" opmask register. However, it can be +// explicitly operated upon by name as non-predicate operand, for example to +// hold a constant or temporary value during calculations on other opmask +// registers. +var ( + K0 = opmask(S64, 0, "K0", Restricted) + K1 = opmask(S64, 1, "K1") + K2 = opmask(S64, 2, "K2") + K3 = opmask(S64, 3, "K3") + K4 = opmask(S64, 4, "K4") + K5 = opmask(S64, 5, "K5") + K6 = opmask(S64, 6, "K6") + K7 = opmask(S64, 7, "K7") +) diff --git a/script/covermain b/script/covermain index 4bd5406e..5afbd1eb 100755 --- a/script/covermain +++ b/script/covermain @@ -21,7 +21,7 @@ EOF # Execute the test with coverage. testbin="${workdir}/testbin" output="${workdir}/cover.out" -go test -o ${testbin} -covermode=count -coverpkg="github.com/mmcloughlin/avo/..." ${workdir}/*.go +go test -tags=integration -o ${testbin} -covermode=count -coverpkg="github.com/mmcloughlin/avo/..." ${workdir}/*.go ${testbin} -test.coverprofile=${output} cp ${output} ${coverprofile} diff --git a/tests/alloc/zeroing/asm.go b/tests/alloc/zeroing/asm.go new file mode 100644 index 00000000..9c7734e2 --- /dev/null +++ b/tests/alloc/zeroing/asm.go @@ -0,0 +1,79 @@ +//go:build ignore +// +build ignore + +package main + +import ( + "strconv" + + . "github.com/mmcloughlin/avo/build" + . "github.com/mmcloughlin/avo/operand" + . "github.com/mmcloughlin/avo/reg" +) + +// The goal of this test is to confirm correct liveness analysis of zeroing mode +// when masking in AVX-512. In merge masking, some of the bits of the output +// register will be preserved, so the register is live coming into the +// instruction. Zeroing mode removes any input dependency. +// +// This synthetic test sets up a situation where we allocate multiple temporary +// registers. Allocation is only feasible if the liveness pass correctly +// identifies that they are not all live at once. + +func main() { + const n = 32 + + TEXT("Zeroing", NOSPLIT, "func(out *[8]uint64)") + Doc("Zeroing computes the sum 1+2+...+" + strconv.Itoa(n) + " in 8 lanes of 512-bit register.") + + out := Load(Param("out"), GP64()) + + Comment("Initialize sum.") + s := ZMM() + VPXORD(s, s, s) + + // Allocate registers for the terms of the sum. Write garbage to them. + // + // The point here is that under merge-masking, or an incorrect handling of + // zeroing-masking, these registers would be live from this point. And there + // would be too many of them so register allocation would fail. + Comment("Initialize summand registers.") + filler := GP64() + MOVQ(U64(0x9e77d78aacb8cbcc), filler) + + z := make([]VecVirtual, n) + for i := 0; i < n; i++ { + z[i] = ZMM() + VPBROADCASTQ(filler, z[i]) + } + + // Prepare a mask register set to all ones. + Comment("Prepare mask register.") + k := K() + KXNORW(k, k, k) + + // Prepare an increment register set to 1 in each lane. + Comment("Prepare constant registers.") + one := GP64() + MOVQ(U64(1), one) + ones := ZMM() + VPBROADCASTQ(one, ones) + + zero := ZMM() + VPXORD(zero, zero, zero) + + last := zero + for i := 0; i < n; i++ { + Commentf("Summand %d.", i+1) + VPADDD_Z(last, ones, k, z[i]) + VPADDD(s, z[i], s) + last = z[i] + } + + Comment("Write result to output pointer.") + VMOVDQU64(s, Mem{Base: out}) + + RET() + + Generate() +} diff --git a/tests/alloc/zeroing/doc.go b/tests/alloc/zeroing/doc.go new file mode 100644 index 00000000..1f5a7d1e --- /dev/null +++ b/tests/alloc/zeroing/doc.go @@ -0,0 +1,2 @@ +// Package zeroing tests liveness analysis of AVX-512 operations with zeroing masking. +package zeroing diff --git a/tests/alloc/zeroing/stub.go b/tests/alloc/zeroing/stub.go new file mode 100644 index 00000000..512a47bb --- /dev/null +++ b/tests/alloc/zeroing/stub.go @@ -0,0 +1,6 @@ +// Code generated by command: go run asm.go -out zeroing.s -stubs stub.go. DO NOT EDIT. + +package zeroing + +// Zeroing computes the sum 1+2+...+32 in 8 lanes of 512-bit register. +func Zeroing(out *[8]uint64) diff --git a/tests/alloc/zeroing/zeroing.s b/tests/alloc/zeroing/zeroing.s new file mode 100644 index 00000000..1084a9a2 --- /dev/null +++ b/tests/alloc/zeroing/zeroing.s @@ -0,0 +1,186 @@ +// Code generated by command: go run asm.go -out zeroing.s -stubs stub.go. DO NOT EDIT. + +#include "textflag.h" + +// func Zeroing(out *[8]uint64) +// Requires: AVX512F +TEXT ·Zeroing(SB), NOSPLIT, $0-8 + MOVQ out+0(FP), AX + + // Initialize sum. + VPXORD Z0, Z0, Z0 + + // Initialize summand registers. + MOVQ $0x9e77d78aacb8cbcc, CX + VPBROADCASTQ CX, Z1 + VPBROADCASTQ CX, Z1 + VPBROADCASTQ CX, Z1 + VPBROADCASTQ CX, Z1 + VPBROADCASTQ CX, Z1 + VPBROADCASTQ CX, Z1 + VPBROADCASTQ CX, Z1 + VPBROADCASTQ CX, Z1 + VPBROADCASTQ CX, Z1 + VPBROADCASTQ CX, Z1 + VPBROADCASTQ CX, Z1 + VPBROADCASTQ CX, Z1 + VPBROADCASTQ CX, Z1 + VPBROADCASTQ CX, Z1 + VPBROADCASTQ CX, Z1 + VPBROADCASTQ CX, Z1 + VPBROADCASTQ CX, Z1 + VPBROADCASTQ CX, Z1 + VPBROADCASTQ CX, Z1 + VPBROADCASTQ CX, Z1 + VPBROADCASTQ CX, Z1 + VPBROADCASTQ CX, Z1 + VPBROADCASTQ CX, Z1 + VPBROADCASTQ CX, Z1 + VPBROADCASTQ CX, Z1 + VPBROADCASTQ CX, Z1 + VPBROADCASTQ CX, Z1 + VPBROADCASTQ CX, Z1 + VPBROADCASTQ CX, Z1 + VPBROADCASTQ CX, Z1 + VPBROADCASTQ CX, Z1 + VPBROADCASTQ CX, Z1 + + // Prepare mask register. + KXNORW K1, K1, K1 + + // Prepare constant registers. + MOVQ $0x0000000000000001, CX + VPBROADCASTQ CX, Z2 + VPXORD Z3, Z3, Z3 + + // Summand 1. + VPADDD.Z Z3, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Summand 2. + VPADDD.Z Z1, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Summand 3. + VPADDD.Z Z1, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Summand 4. + VPADDD.Z Z1, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Summand 5. + VPADDD.Z Z1, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Summand 6. + VPADDD.Z Z1, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Summand 7. + VPADDD.Z Z1, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Summand 8. + VPADDD.Z Z1, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Summand 9. + VPADDD.Z Z1, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Summand 10. + VPADDD.Z Z1, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Summand 11. + VPADDD.Z Z1, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Summand 12. + VPADDD.Z Z1, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Summand 13. + VPADDD.Z Z1, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Summand 14. + VPADDD.Z Z1, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Summand 15. + VPADDD.Z Z1, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Summand 16. + VPADDD.Z Z1, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Summand 17. + VPADDD.Z Z1, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Summand 18. + VPADDD.Z Z1, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Summand 19. + VPADDD.Z Z1, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Summand 20. + VPADDD.Z Z1, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Summand 21. + VPADDD.Z Z1, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Summand 22. + VPADDD.Z Z1, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Summand 23. + VPADDD.Z Z1, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Summand 24. + VPADDD.Z Z1, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Summand 25. + VPADDD.Z Z1, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Summand 26. + VPADDD.Z Z1, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Summand 27. + VPADDD.Z Z1, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Summand 28. + VPADDD.Z Z1, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Summand 29. + VPADDD.Z Z1, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Summand 30. + VPADDD.Z Z1, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Summand 31. + VPADDD.Z Z1, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Summand 32. + VPADDD.Z Z1, Z2, K1, Z1 + VPADDD Z0, Z1, Z0 + + // Write result to output pointer. + VMOVDQU64 Z0, (AX) + RET diff --git a/tests/alloc/zeroing/zeroing_test.go b/tests/alloc/zeroing/zeroing_test.go new file mode 100644 index 00000000..e28b3722 --- /dev/null +++ b/tests/alloc/zeroing/zeroing_test.go @@ -0,0 +1,29 @@ +package zeroing + +import ( + "testing" + + "golang.org/x/sys/cpu" +) + +//go:generate go run asm.go -out zeroing.s -stubs stub.go + +func TestZeroing(t *testing.T) { + const ( + n = 32 + expect = n * (n + 1) / 2 + ) + + if !cpu.X86.HasAVX512F { + t.Skip("require AVX512F") + } + + var got [8]uint64 + Zeroing(&got) + + for i := 0; i < 8; i++ { + if got[i] != expect { + t.Errorf("got[%d] = %d; expect %d", i, got[i], expect) + } + } +} diff --git a/tests/thirdparty/packages.json b/tests/thirdparty/packages.json index 69e5438c..fdcbb285 100644 --- a/tests/thirdparty/packages.json +++ b/tests/thirdparty/packages.json @@ -458,7 +458,8 @@ "make --always-make build" ] } - ] + ], + "known_issue": 229 }, { "repository": { diff --git a/x86/gen.go b/x86/gen.go index 25d15fa6..c2e667af 100644 --- a/x86/gen.go +++ b/x86/gen.go @@ -1,4 +1,5 @@ package x86 +//go:generate avogen -output zoptab.go optab //go:generate avogen -output zctors.go ctors //go:generate avogen -output zctors_test.go ctorstest diff --git a/x86/inst_test.go b/x86/inst_test.go new file mode 100644 index 00000000..c35297eb --- /dev/null +++ b/x86/inst_test.go @@ -0,0 +1,100 @@ +package x86 + +import ( + "reflect" + "testing" + + "github.com/mmcloughlin/avo/ir" + "github.com/mmcloughlin/avo/operand" + "github.com/mmcloughlin/avo/reg" +) + +func TestCases(t *testing.T) { + must := MustInstruction(t) + + m128 := operand.Mem{Base: reg.RAX} + + cases := []struct { + Name string + Instruction *ir.Instruction + Expect *ir.Instruction + }{ + // In the merge-masking case, the output register should also be an + // input. This test confirms that Z3 appears in the input operands list. + { + Name: "avx512_masking_merging_input_registers", + Instruction: must(VPADDD(reg.Z1, reg.Z2, reg.K1, reg.Z3)), + Expect: &ir.Instruction{ + Opcode: "VPADDD", + Operands: []operand.Op{reg.Z1, reg.Z2, reg.K1, reg.Z3}, + Inputs: []operand.Op{reg.Z1, reg.Z2, reg.K1, reg.Z3}, + Outputs: []operand.Op{reg.Z3}, + ISA: []string{"AVX512F"}, + }, + }, + // In the zeroing-masking case, the output register is not an input. + // This test case is the same as above, but with the zeroing suffix. In + // this case Z3 should not be an input. + { + Name: "avx512_masking_zeroing_input_registers", + Instruction: must(VPADDD_Z(reg.Z1, reg.Z2, reg.K1, reg.Z3)), + Expect: &ir.Instruction{ + Opcode: "VPADDD", + Suffixes: []string{"Z"}, + Operands: []operand.Op{reg.Z1, reg.Z2, reg.K1, reg.Z3}, + Inputs: []operand.Op{reg.Z1, reg.Z2, reg.K1}, // not Z3 + Outputs: []operand.Op{reg.Z3}, + ISA: []string{"AVX512F"}, + }, + }, + // Many existing AVX instructions gained EVEX-encoded forms when AVX-512 + // was added. In a previous broken implementation, this led to multiple + // forms of the same instruction in the database, both the VEX and EVEX + // encoded versions. This causes the computed ISA list to be wrong, + // since it can think AVX-512 is required when in fact the instruction + // existed before. These test cases confirm the correct ISA is selected. + { + Name: "vex_evex_xmm_xmm_xmm", + Instruction: must(VFMADD132PS(reg.X1, reg.X2, reg.X3)), + Expect: &ir.Instruction{ + Opcode: "VFMADD132PS", + Operands: []operand.Op{reg.X1, reg.X2, reg.X3}, + Inputs: []operand.Op{reg.X1, reg.X2, reg.X3}, + Outputs: []operand.Op{reg.X3}, + ISA: []string{"FMA3"}, // not AVX512F + }, + }, + { + Name: "vex_evex_m128_xmm_xmm", + Instruction: must(VFMADD132PS(m128, reg.X2, reg.X3)), + Expect: &ir.Instruction{ + Opcode: "VFMADD132PS", + Operands: []operand.Op{m128, reg.X2, reg.X3}, + Inputs: []operand.Op{m128, reg.X2, reg.X3}, + Outputs: []operand.Op{reg.X3}, + ISA: []string{"FMA3"}, // not AVX512F + }, + }, + } + + for _, c := range cases { + c := c // scopelint + t.Run(c.Name, func(t *testing.T) { + if !reflect.DeepEqual(c.Instruction, c.Expect) { + t.Logf(" got = %#v", c.Instruction) + t.Logf("expect = %#v", c.Expect) + t.FailNow() + } + }) + } +} + +func MustInstruction(t *testing.T) func(*ir.Instruction, error) *ir.Instruction { + return func(i *ir.Instruction, err error) *ir.Instruction { + t.Helper() + if err != nil { + t.Fatal(err) + } + return i + } +} diff --git a/x86/optab.go b/x86/optab.go new file mode 100644 index 00000000..677c569b --- /dev/null +++ b/x86/optab.go @@ -0,0 +1,130 @@ +package x86 + +import ( + "errors" + + "github.com/mmcloughlin/avo/ir" + "github.com/mmcloughlin/avo/operand" +) + +// build constructs an instruction object from a list of acceptable forms, and +// given input operands and suffixes. +func build(forms []form, suffixes sffxs, ops []operand.Op) (*ir.Instruction, error) { + for i := range forms { + f := &forms[i] + if f.match(suffixes, ops) { + return f.build(suffixes, ops), nil + } + } + return nil, errors.New("bad operands") +} + +// form represents an instruction form. +type form struct { + Opcode opc + SuffixesClass sffxscls + Features feature + ISAs isas + Arity uint8 + Operands oprnds +} + +// feature is a flags enumeration type representing instruction properties. +type feature uint8 + +const ( + featureTerminal feature = 1 << iota + featureBranch + featureConditionalBranch + featureCancellingInputs +) + +// oprnds is a list of explicit and implicit operands of an instruction form. +// The size of the array is output by optab generator. +type oprnds [maxoperands]oprnd + +// oprnd represents an explicit or implicit operand to an instruction form. +type oprnd struct { + Type uint8 + Implicit bool + Action action +} + +// action an instruction form applies to an operand. +type action uint8 + +const ( + actionN action = iota + actionR + actionW + actionRW action = actionR | actionW +) + +// Read reports if the action includes read. +func (a action) Read() bool { return (a & actionR) != 0 } + +// Read reports if the action includes write. +func (a action) Write() bool { return (a & actionW) != 0 } + +// match reports whether this form matches the given suffixes and operand +// list. +func (f *form) match(suffixes sffxs, ops []operand.Op) bool { + // Match suffix. + accept := f.SuffixesClass.SuffixesSet() + if !accept[suffixes] { + return false + } + + // Match operands. + if len(ops) != int(f.Arity) { + return false + } + + for i, op := range ops { + t := oprndtype(f.Operands[i].Type) + if !t.Match(op) { + return false + } + } + + return true +} + +// build the full instruction object for this form and the given suffixes and +// operands. Assumes the form already matches the inputs. +func (f *form) build(suffixes sffxs, ops []operand.Op) *ir.Instruction { + // Base instruction properties. + i := &ir.Instruction{ + Opcode: f.Opcode.String(), + Suffixes: suffixes.Strings(), + Operands: ops, + IsTerminal: (f.Features & featureTerminal) != 0, + IsBranch: (f.Features & featureBranch) != 0, + IsConditional: (f.Features & featureConditionalBranch) != 0, + CancellingInputs: (f.Features & featureCancellingInputs) != 0, + ISA: f.ISAs.List(), + } + + // Input/output operands. + for _, spec := range f.Operands { + if spec.Type == 0 { + break + } + + var op operand.Op + if spec.Implicit { + op = implreg(spec.Type).Register() + } else { + op, ops = ops[0], ops[1:] + } + + if spec.Action.Read() { + i.Inputs = append(i.Inputs, op) + } + if spec.Action.Write() { + i.Outputs = append(i.Outputs, op) + } + } + + return i +} diff --git a/x86/stress_test.go b/x86/stress_test.go new file mode 100644 index 00000000..50e96a26 --- /dev/null +++ b/x86/stress_test.go @@ -0,0 +1,10 @@ +// Constructors test that rely on huge generated files that bloat compile time +// are limited to stress-test mode. + +//go:build stress +// +build stress + +package x86 + +//go:generate avogen -output zstress_test.go ctorsstress +//go:generate avogen -output zbench_test.go ctorsbench diff --git a/x86/zctors.go b/x86/zctors.go index 447c0a1a..b17013cd 100644 --- a/x86/zctors.go +++ b/x86/zctors.go @@ -3,11 +3,8 @@ package x86 import ( - "errors" - intrep "github.com/mmcloughlin/avo/ir" "github.com/mmcloughlin/avo/operand" - "github.com/mmcloughlin/avo/reg" ) // ADCB: Add with Carry. @@ -15,57 +12,13 @@ import ( // Forms: // // ADCB imm8 al +// ADCB imm8 m8 // ADCB imm8 r8 -// ADCB r8 r8 // ADCB m8 r8 -// ADCB imm8 m8 // ADCB r8 m8 +// ADCB r8 r8 func ADCB(imr, amr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(imr) && operand.IsAL(amr): - return &intrep.Instruction{ - Opcode: "ADCB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM8(imr) && operand.IsR8(amr): - return &intrep.Instruction{ - Opcode: "ADCB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsR8(imr) && operand.IsR8(amr): - return &intrep.Instruction{ - Opcode: "ADCB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsM8(imr) && operand.IsR8(amr): - return &intrep.Instruction{ - Opcode: "ADCB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM8(imr) && operand.IsM8(amr): - return &intrep.Instruction{ - Opcode: "ADCB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsR8(imr) && operand.IsM8(amr): - return &intrep.Instruction{ - Opcode: "ADCB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - } - return nil, errors.New("ADCB: bad operands") + return build(opcADCB.Forms(), sffxs{}, []operand.Op{imr, amr}) } // ADCL: Add with Carry. @@ -73,147 +26,31 @@ func ADCB(imr, amr operand.Op) (*intrep.Instruction, error) { // Forms: // // ADCL imm32 eax -// ADCL imm8 r32 +// ADCL imm32 m32 // ADCL imm32 r32 -// ADCL r32 r32 -// ADCL m32 r32 // ADCL imm8 m32 -// ADCL imm32 m32 +// ADCL imm8 r32 +// ADCL m32 r32 // ADCL r32 m32 +// ADCL r32 r32 func ADCL(imr, emr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM32(imr) && operand.IsEAX(emr): - return &intrep.Instruction{ - Opcode: "ADCL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsIMM8(imr) && operand.IsR32(emr): - return &intrep.Instruction{ - Opcode: "ADCL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsIMM32(imr) && operand.IsR32(emr): - return &intrep.Instruction{ - Opcode: "ADCL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsR32(imr) && operand.IsR32(emr): - return &intrep.Instruction{ - Opcode: "ADCL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{imr, emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsM32(imr) && operand.IsR32(emr): - return &intrep.Instruction{ - Opcode: "ADCL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{imr, emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsIMM8(imr) && operand.IsM32(emr): - return &intrep.Instruction{ - Opcode: "ADCL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsIMM32(imr) && operand.IsM32(emr): - return &intrep.Instruction{ - Opcode: "ADCL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsR32(imr) && operand.IsM32(emr): - return &intrep.Instruction{ - Opcode: "ADCL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{imr, emr}, - Outputs: []operand.Op{emr}, - }, nil - } - return nil, errors.New("ADCL: bad operands") + return build(opcADCL.Forms(), sffxs{}, []operand.Op{imr, emr}) } // ADCQ: Add with Carry. // // Forms: // +// ADCQ imm32 m64 +// ADCQ imm32 r64 // ADCQ imm32 rax +// ADCQ imm8 m64 // ADCQ imm8 r64 -// ADCQ imm32 r64 -// ADCQ r64 r64 // ADCQ m64 r64 -// ADCQ imm8 m64 -// ADCQ imm32 m64 // ADCQ r64 m64 +// ADCQ r64 r64 func ADCQ(imr, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM32(imr) && operand.IsRAX(mr): - return &intrep.Instruction{ - Opcode: "ADCQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(imr) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "ADCQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM32(imr) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "ADCQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR64(imr) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "ADCQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{imr, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM64(imr) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "ADCQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{imr, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(imr) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "ADCQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM32(imr) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "ADCQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR64(imr) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "ADCQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{imr, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("ADCQ: bad operands") + return build(opcADCQ.Forms(), sffxs{}, []operand.Op{imr, mr}) } // ADCW: Add with Carry. @@ -221,129 +58,35 @@ func ADCQ(imr, mr operand.Op) (*intrep.Instruction, error) { // Forms: // // ADCW imm16 ax -// ADCW imm8 r16 +// ADCW imm16 m16 // ADCW imm16 r16 -// ADCW r16 r16 -// ADCW m16 r16 // ADCW imm8 m16 -// ADCW imm16 m16 +// ADCW imm8 r16 +// ADCW m16 r16 // ADCW r16 m16 +// ADCW r16 r16 func ADCW(imr, amr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM16(imr) && operand.IsAX(amr): - return &intrep.Instruction{ - Opcode: "ADCW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM8(imr) && operand.IsR16(amr): - return &intrep.Instruction{ - Opcode: "ADCW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM16(imr) && operand.IsR16(amr): - return &intrep.Instruction{ - Opcode: "ADCW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsR16(imr) && operand.IsR16(amr): - return &intrep.Instruction{ - Opcode: "ADCW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsM16(imr) && operand.IsR16(amr): - return &intrep.Instruction{ - Opcode: "ADCW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM8(imr) && operand.IsM16(amr): - return &intrep.Instruction{ - Opcode: "ADCW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM16(imr) && operand.IsM16(amr): - return &intrep.Instruction{ - Opcode: "ADCW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsR16(imr) && operand.IsM16(amr): - return &intrep.Instruction{ - Opcode: "ADCW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - } - return nil, errors.New("ADCW: bad operands") + return build(opcADCW.Forms(), sffxs{}, []operand.Op{imr, amr}) } // ADCXL: Unsigned Integer Addition of Two Operands with Carry Flag. // // Forms: // -// ADCXL r32 r32 // ADCXL m32 r32 +// ADCXL r32 r32 func ADCXL(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "ADCXL", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"ADX"}, - }, nil - case operand.IsM32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "ADCXL", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"ADX"}, - }, nil - } - return nil, errors.New("ADCXL: bad operands") + return build(opcADCXL.Forms(), sffxs{}, []operand.Op{mr, r}) } // ADCXQ: Unsigned Integer Addition of Two Operands with Carry Flag. // // Forms: // -// ADCXQ r64 r64 // ADCXQ m64 r64 +// ADCXQ r64 r64 func ADCXQ(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "ADCXQ", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"ADX"}, - }, nil - case operand.IsM64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "ADCXQ", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"ADX"}, - }, nil - } - return nil, errors.New("ADCXQ: bad operands") + return build(opcADCXQ.Forms(), sffxs{}, []operand.Op{mr, r}) } // ADDB: Add. @@ -351,57 +94,13 @@ func ADCXQ(mr, r operand.Op) (*intrep.Instruction, error) { // Forms: // // ADDB imm8 al +// ADDB imm8 m8 // ADDB imm8 r8 -// ADDB r8 r8 // ADDB m8 r8 -// ADDB imm8 m8 // ADDB r8 m8 +// ADDB r8 r8 func ADDB(imr, amr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(imr) && operand.IsAL(amr): - return &intrep.Instruction{ - Opcode: "ADDB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM8(imr) && operand.IsR8(amr): - return &intrep.Instruction{ - Opcode: "ADDB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsR8(imr) && operand.IsR8(amr): - return &intrep.Instruction{ - Opcode: "ADDB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsM8(imr) && operand.IsR8(amr): - return &intrep.Instruction{ - Opcode: "ADDB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM8(imr) && operand.IsM8(amr): - return &intrep.Instruction{ - Opcode: "ADDB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsR8(imr) && operand.IsM8(amr): - return &intrep.Instruction{ - Opcode: "ADDB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - } - return nil, errors.New("ADDB: bad operands") + return build(opcADDB.Forms(), sffxs{}, []operand.Op{imr, amr}) } // ADDL: Add. @@ -409,315 +108,91 @@ func ADDB(imr, amr operand.Op) (*intrep.Instruction, error) { // Forms: // // ADDL imm32 eax -// ADDL imm8 r32 +// ADDL imm32 m32 // ADDL imm32 r32 -// ADDL r32 r32 -// ADDL m32 r32 // ADDL imm8 m32 -// ADDL imm32 m32 +// ADDL imm8 r32 +// ADDL m32 r32 // ADDL r32 m32 +// ADDL r32 r32 func ADDL(imr, emr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM32(imr) && operand.IsEAX(emr): - return &intrep.Instruction{ - Opcode: "ADDL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsIMM8(imr) && operand.IsR32(emr): - return &intrep.Instruction{ - Opcode: "ADDL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsIMM32(imr) && operand.IsR32(emr): - return &intrep.Instruction{ - Opcode: "ADDL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsR32(imr) && operand.IsR32(emr): - return &intrep.Instruction{ - Opcode: "ADDL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{imr, emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsM32(imr) && operand.IsR32(emr): - return &intrep.Instruction{ - Opcode: "ADDL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{imr, emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsIMM8(imr) && operand.IsM32(emr): - return &intrep.Instruction{ - Opcode: "ADDL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsIMM32(imr) && operand.IsM32(emr): - return &intrep.Instruction{ - Opcode: "ADDL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsR32(imr) && operand.IsM32(emr): - return &intrep.Instruction{ - Opcode: "ADDL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{imr, emr}, - Outputs: []operand.Op{emr}, - }, nil - } - return nil, errors.New("ADDL: bad operands") + return build(opcADDL.Forms(), sffxs{}, []operand.Op{imr, emr}) } // ADDPD: Add Packed Double-Precision Floating-Point Values. // // Forms: // -// ADDPD xmm xmm // ADDPD m128 xmm +// ADDPD xmm xmm func ADDPD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ADDPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ADDPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("ADDPD: bad operands") + return build(opcADDPD.Forms(), sffxs{}, []operand.Op{mx, x}) } // ADDPS: Add Packed Single-Precision Floating-Point Values. // // Forms: // -// ADDPS xmm xmm // ADDPS m128 xmm +// ADDPS xmm xmm func ADDPS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ADDPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ADDPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("ADDPS: bad operands") + return build(opcADDPS.Forms(), sffxs{}, []operand.Op{mx, x}) } // ADDQ: Add. // // Forms: // +// ADDQ imm32 m64 +// ADDQ imm32 r64 // ADDQ imm32 rax +// ADDQ imm8 m64 // ADDQ imm8 r64 -// ADDQ imm32 r64 -// ADDQ r64 r64 // ADDQ m64 r64 -// ADDQ imm8 m64 -// ADDQ imm32 m64 // ADDQ r64 m64 +// ADDQ r64 r64 func ADDQ(imr, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM32(imr) && operand.IsRAX(mr): - return &intrep.Instruction{ - Opcode: "ADDQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(imr) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "ADDQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM32(imr) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "ADDQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR64(imr) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "ADDQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{imr, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM64(imr) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "ADDQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{imr, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(imr) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "ADDQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM32(imr) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "ADDQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR64(imr) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "ADDQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{imr, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("ADDQ: bad operands") + return build(opcADDQ.Forms(), sffxs{}, []operand.Op{imr, mr}) } // ADDSD: Add Scalar Double-Precision Floating-Point Values. // // Forms: // -// ADDSD xmm xmm // ADDSD m64 xmm +// ADDSD xmm xmm func ADDSD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ADDSD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ADDSD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("ADDSD: bad operands") + return build(opcADDSD.Forms(), sffxs{}, []operand.Op{mx, x}) } // ADDSS: Add Scalar Single-Precision Floating-Point Values. // // Forms: // -// ADDSS xmm xmm // ADDSS m32 xmm +// ADDSS xmm xmm func ADDSS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ADDSS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ADDSS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("ADDSS: bad operands") + return build(opcADDSS.Forms(), sffxs{}, []operand.Op{mx, x}) } // ADDSUBPD: Packed Double-FP Add/Subtract. // // Forms: // -// ADDSUBPD xmm xmm // ADDSUBPD m128 xmm +// ADDSUBPD xmm xmm func ADDSUBPD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ADDSUBPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE3"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ADDSUBPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE3"}, - }, nil - } - return nil, errors.New("ADDSUBPD: bad operands") + return build(opcADDSUBPD.Forms(), sffxs{}, []operand.Op{mx, x}) } // ADDSUBPS: Packed Single-FP Add/Subtract. // // Forms: // -// ADDSUBPS xmm xmm // ADDSUBPS m128 xmm +// ADDSUBPS xmm xmm func ADDSUBPS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ADDSUBPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE3"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ADDSUBPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE3"}, - }, nil - } - return nil, errors.New("ADDSUBPS: bad operands") + return build(opcADDSUBPS.Forms(), sffxs{}, []operand.Op{mx, x}) } // ADDW: Add. @@ -725,297 +200,95 @@ func ADDSUBPS(mx, x operand.Op) (*intrep.Instruction, error) { // Forms: // // ADDW imm16 ax -// ADDW imm8 r16 +// ADDW imm16 m16 // ADDW imm16 r16 -// ADDW r16 r16 -// ADDW m16 r16 // ADDW imm8 m16 -// ADDW imm16 m16 +// ADDW imm8 r16 +// ADDW m16 r16 // ADDW r16 m16 +// ADDW r16 r16 func ADDW(imr, amr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM16(imr) && operand.IsAX(amr): - return &intrep.Instruction{ - Opcode: "ADDW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM8(imr) && operand.IsR16(amr): - return &intrep.Instruction{ - Opcode: "ADDW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM16(imr) && operand.IsR16(amr): - return &intrep.Instruction{ - Opcode: "ADDW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsR16(imr) && operand.IsR16(amr): - return &intrep.Instruction{ - Opcode: "ADDW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsM16(imr) && operand.IsR16(amr): - return &intrep.Instruction{ - Opcode: "ADDW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM8(imr) && operand.IsM16(amr): - return &intrep.Instruction{ - Opcode: "ADDW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM16(imr) && operand.IsM16(amr): - return &intrep.Instruction{ - Opcode: "ADDW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsR16(imr) && operand.IsM16(amr): - return &intrep.Instruction{ - Opcode: "ADDW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - } - return nil, errors.New("ADDW: bad operands") + return build(opcADDW.Forms(), sffxs{}, []operand.Op{imr, amr}) } // ADOXL: Unsigned Integer Addition of Two Operands with Overflow Flag. // // Forms: // -// ADOXL r32 r32 // ADOXL m32 r32 +// ADOXL r32 r32 func ADOXL(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "ADOXL", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"ADX"}, - }, nil - case operand.IsM32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "ADOXL", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"ADX"}, - }, nil - } - return nil, errors.New("ADOXL: bad operands") + return build(opcADOXL.Forms(), sffxs{}, []operand.Op{mr, r}) } // ADOXQ: Unsigned Integer Addition of Two Operands with Overflow Flag. // // Forms: // -// ADOXQ r64 r64 // ADOXQ m64 r64 +// ADOXQ r64 r64 func ADOXQ(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "ADOXQ", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"ADX"}, - }, nil - case operand.IsM64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "ADOXQ", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"ADX"}, - }, nil - } - return nil, errors.New("ADOXQ: bad operands") + return build(opcADOXQ.Forms(), sffxs{}, []operand.Op{mr, r}) } // AESDEC: Perform One Round of an AES Decryption Flow. // // Forms: // -// AESDEC xmm xmm // AESDEC m128 xmm +// AESDEC xmm xmm func AESDEC(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "AESDEC", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"AES"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "AESDEC", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"AES"}, - }, nil - } - return nil, errors.New("AESDEC: bad operands") + return build(opcAESDEC.Forms(), sffxs{}, []operand.Op{mx, x}) } // AESDECLAST: Perform Last Round of an AES Decryption Flow. // // Forms: // -// AESDECLAST xmm xmm // AESDECLAST m128 xmm +// AESDECLAST xmm xmm func AESDECLAST(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "AESDECLAST", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"AES"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "AESDECLAST", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"AES"}, - }, nil - } - return nil, errors.New("AESDECLAST: bad operands") + return build(opcAESDECLAST.Forms(), sffxs{}, []operand.Op{mx, x}) } // AESENC: Perform One Round of an AES Encryption Flow. // // Forms: // -// AESENC xmm xmm // AESENC m128 xmm +// AESENC xmm xmm func AESENC(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "AESENC", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"AES"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "AESENC", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"AES"}, - }, nil - } - return nil, errors.New("AESENC: bad operands") + return build(opcAESENC.Forms(), sffxs{}, []operand.Op{mx, x}) } // AESENCLAST: Perform Last Round of an AES Encryption Flow. // // Forms: // -// AESENCLAST xmm xmm // AESENCLAST m128 xmm +// AESENCLAST xmm xmm func AESENCLAST(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "AESENCLAST", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"AES"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "AESENCLAST", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"AES"}, - }, nil - } - return nil, errors.New("AESENCLAST: bad operands") + return build(opcAESENCLAST.Forms(), sffxs{}, []operand.Op{mx, x}) } // AESIMC: Perform the AES InvMixColumn Transformation. // // Forms: // -// AESIMC xmm xmm // AESIMC m128 xmm +// AESIMC xmm xmm func AESIMC(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "AESIMC", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"AES"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "AESIMC", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"AES"}, - }, nil - } - return nil, errors.New("AESIMC: bad operands") + return build(opcAESIMC.Forms(), sffxs{}, []operand.Op{mx, x}) } // AESKEYGENASSIST: AES Round Key Generation Assist. // // Forms: // -// AESKEYGENASSIST imm8 xmm xmm // AESKEYGENASSIST imm8 m128 xmm +// AESKEYGENASSIST imm8 xmm xmm func AESKEYGENASSIST(i, mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "AESKEYGENASSIST", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"AES"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "AESKEYGENASSIST", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"AES"}, - }, nil - } - return nil, errors.New("AESKEYGENASSIST: bad operands") + return build(opcAESKEYGENASSIST.Forms(), sffxs{}, []operand.Op{i, mx, x}) } // ANDB: Logical AND. @@ -1023,57 +296,13 @@ func AESKEYGENASSIST(i, mx, x operand.Op) (*intrep.Instruction, error) { // Forms: // // ANDB imm8 al +// ANDB imm8 m8 // ANDB imm8 r8 -// ANDB r8 r8 // ANDB m8 r8 -// ANDB imm8 m8 // ANDB r8 m8 +// ANDB r8 r8 func ANDB(imr, amr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(imr) && operand.IsAL(amr): - return &intrep.Instruction{ - Opcode: "ANDB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM8(imr) && operand.IsR8(amr): - return &intrep.Instruction{ - Opcode: "ANDB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsR8(imr) && operand.IsR8(amr): - return &intrep.Instruction{ - Opcode: "ANDB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsM8(imr) && operand.IsR8(amr): - return &intrep.Instruction{ - Opcode: "ANDB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM8(imr) && operand.IsM8(amr): - return &intrep.Instruction{ - Opcode: "ANDB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsR8(imr) && operand.IsM8(amr): - return &intrep.Instruction{ - Opcode: "ANDB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - } - return nil, errors.New("ANDB: bad operands") + return build(opcANDB.Forms(), sffxs{}, []operand.Op{imr, amr}) } // ANDL: Logical AND. @@ -1081,319 +310,91 @@ func ANDB(imr, amr operand.Op) (*intrep.Instruction, error) { // Forms: // // ANDL imm32 eax -// ANDL imm8 r32 +// ANDL imm32 m32 // ANDL imm32 r32 -// ANDL r32 r32 -// ANDL m32 r32 // ANDL imm8 m32 -// ANDL imm32 m32 +// ANDL imm8 r32 +// ANDL m32 r32 // ANDL r32 m32 +// ANDL r32 r32 func ANDL(imr, emr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM32(imr) && operand.IsEAX(emr): - return &intrep.Instruction{ - Opcode: "ANDL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsIMM8(imr) && operand.IsR32(emr): - return &intrep.Instruction{ - Opcode: "ANDL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsIMM32(imr) && operand.IsR32(emr): - return &intrep.Instruction{ - Opcode: "ANDL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsR32(imr) && operand.IsR32(emr): - return &intrep.Instruction{ - Opcode: "ANDL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{imr, emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsM32(imr) && operand.IsR32(emr): - return &intrep.Instruction{ - Opcode: "ANDL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{imr, emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsIMM8(imr) && operand.IsM32(emr): - return &intrep.Instruction{ - Opcode: "ANDL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsIMM32(imr) && operand.IsM32(emr): - return &intrep.Instruction{ - Opcode: "ANDL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsR32(imr) && operand.IsM32(emr): - return &intrep.Instruction{ - Opcode: "ANDL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{imr, emr}, - Outputs: []operand.Op{emr}, - }, nil - } - return nil, errors.New("ANDL: bad operands") + return build(opcANDL.Forms(), sffxs{}, []operand.Op{imr, emr}) } // ANDNL: Logical AND NOT. // // Forms: // -// ANDNL r32 r32 r32 // ANDNL m32 r32 r32 +// ANDNL r32 r32 r32 func ANDNL(mr, r, r1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR32(r) && operand.IsR32(r1): - return &intrep.Instruction{ - Opcode: "ANDNL", - Operands: []operand.Op{mr, r, r1}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI"}, - CancellingInputs: true, - }, nil - case operand.IsM32(mr) && operand.IsR32(r) && operand.IsR32(r1): - return &intrep.Instruction{ - Opcode: "ANDNL", - Operands: []operand.Op{mr, r, r1}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI"}, - }, nil - } - return nil, errors.New("ANDNL: bad operands") + return build(opcANDNL.Forms(), sffxs{}, []operand.Op{mr, r, r1}) } // ANDNPD: Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values. // // Forms: // -// ANDNPD xmm xmm // ANDNPD m128 xmm +// ANDNPD xmm xmm func ANDNPD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ANDNPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ANDNPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("ANDNPD: bad operands") + return build(opcANDNPD.Forms(), sffxs{}, []operand.Op{mx, x}) } // ANDNPS: Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values. // // Forms: // -// ANDNPS xmm xmm // ANDNPS m128 xmm +// ANDNPS xmm xmm func ANDNPS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ANDNPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ANDNPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("ANDNPS: bad operands") + return build(opcANDNPS.Forms(), sffxs{}, []operand.Op{mx, x}) } // ANDNQ: Logical AND NOT. // // Forms: // -// ANDNQ r64 r64 r64 // ANDNQ m64 r64 r64 +// ANDNQ r64 r64 r64 func ANDNQ(mr, r, r1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsR64(r) && operand.IsR64(r1): - return &intrep.Instruction{ - Opcode: "ANDNQ", - Operands: []operand.Op{mr, r, r1}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI"}, - CancellingInputs: true, - }, nil - case operand.IsM64(mr) && operand.IsR64(r) && operand.IsR64(r1): - return &intrep.Instruction{ - Opcode: "ANDNQ", - Operands: []operand.Op{mr, r, r1}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI"}, - }, nil - } - return nil, errors.New("ANDNQ: bad operands") + return build(opcANDNQ.Forms(), sffxs{}, []operand.Op{mr, r, r1}) } // ANDPD: Bitwise Logical AND of Packed Double-Precision Floating-Point Values. // // Forms: // -// ANDPD xmm xmm // ANDPD m128 xmm +// ANDPD xmm xmm func ANDPD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ANDPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ANDPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("ANDPD: bad operands") + return build(opcANDPD.Forms(), sffxs{}, []operand.Op{mx, x}) } // ANDPS: Bitwise Logical AND of Packed Single-Precision Floating-Point Values. // // Forms: // -// ANDPS xmm xmm // ANDPS m128 xmm +// ANDPS xmm xmm func ANDPS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ANDPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ANDPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("ANDPS: bad operands") + return build(opcANDPS.Forms(), sffxs{}, []operand.Op{mx, x}) } // ANDQ: Logical AND. // // Forms: // +// ANDQ imm32 m64 +// ANDQ imm32 r64 // ANDQ imm32 rax +// ANDQ imm8 m64 // ANDQ imm8 r64 -// ANDQ imm32 r64 -// ANDQ r64 r64 // ANDQ m64 r64 -// ANDQ imm8 m64 -// ANDQ imm32 m64 // ANDQ r64 m64 +// ANDQ r64 r64 func ANDQ(imr, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM32(imr) && operand.IsRAX(mr): - return &intrep.Instruction{ - Opcode: "ANDQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(imr) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "ANDQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM32(imr) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "ANDQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR64(imr) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "ANDQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{imr, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM64(imr) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "ANDQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{imr, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(imr) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "ANDQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM32(imr) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "ANDQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR64(imr) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "ANDQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{imr, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("ANDQ: bad operands") + return build(opcANDQ.Forms(), sffxs{}, []operand.Op{imr, mr}) } // ANDW: Logical AND. @@ -1401,565 +402,195 @@ func ANDQ(imr, mr operand.Op) (*intrep.Instruction, error) { // Forms: // // ANDW imm16 ax -// ANDW imm8 r16 +// ANDW imm16 m16 // ANDW imm16 r16 -// ANDW r16 r16 -// ANDW m16 r16 // ANDW imm8 m16 -// ANDW imm16 m16 +// ANDW imm8 r16 +// ANDW m16 r16 // ANDW r16 m16 +// ANDW r16 r16 func ANDW(imr, amr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM16(imr) && operand.IsAX(amr): - return &intrep.Instruction{ - Opcode: "ANDW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM8(imr) && operand.IsR16(amr): - return &intrep.Instruction{ - Opcode: "ANDW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM16(imr) && operand.IsR16(amr): - return &intrep.Instruction{ - Opcode: "ANDW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsR16(imr) && operand.IsR16(amr): - return &intrep.Instruction{ - Opcode: "ANDW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsM16(imr) && operand.IsR16(amr): - return &intrep.Instruction{ - Opcode: "ANDW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM8(imr) && operand.IsM16(amr): - return &intrep.Instruction{ - Opcode: "ANDW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM16(imr) && operand.IsM16(amr): - return &intrep.Instruction{ - Opcode: "ANDW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsR16(imr) && operand.IsM16(amr): - return &intrep.Instruction{ - Opcode: "ANDW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - } - return nil, errors.New("ANDW: bad operands") + return build(opcANDW.Forms(), sffxs{}, []operand.Op{imr, amr}) } // BEXTRL: Bit Field Extract. // // Forms: // -// BEXTRL r32 r32 r32 // BEXTRL r32 m32 r32 +// BEXTRL r32 r32 r32 func BEXTRL(r, mr, r1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(r) && operand.IsR32(mr) && operand.IsR32(r1): - return &intrep.Instruction{ - Opcode: "BEXTRL", - Operands: []operand.Op{r, mr, r1}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI"}, - }, nil - case operand.IsR32(r) && operand.IsM32(mr) && operand.IsR32(r1): - return &intrep.Instruction{ - Opcode: "BEXTRL", - Operands: []operand.Op{r, mr, r1}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI"}, - }, nil - } - return nil, errors.New("BEXTRL: bad operands") + return build(opcBEXTRL.Forms(), sffxs{}, []operand.Op{r, mr, r1}) } // BEXTRQ: Bit Field Extract. // // Forms: // -// BEXTRQ r64 r64 r64 // BEXTRQ r64 m64 r64 +// BEXTRQ r64 r64 r64 func BEXTRQ(r, mr, r1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(r) && operand.IsR64(mr) && operand.IsR64(r1): - return &intrep.Instruction{ - Opcode: "BEXTRQ", - Operands: []operand.Op{r, mr, r1}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI"}, - }, nil - case operand.IsR64(r) && operand.IsM64(mr) && operand.IsR64(r1): - return &intrep.Instruction{ - Opcode: "BEXTRQ", - Operands: []operand.Op{r, mr, r1}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI"}, - }, nil - } - return nil, errors.New("BEXTRQ: bad operands") + return build(opcBEXTRQ.Forms(), sffxs{}, []operand.Op{r, mr, r1}) } // BLENDPD: Blend Packed Double Precision Floating-Point Values. // // Forms: // -// BLENDPD imm8 xmm xmm // BLENDPD imm8 m128 xmm +// BLENDPD imm8 xmm xmm func BLENDPD(i, mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "BLENDPD", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "BLENDPD", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("BLENDPD: bad operands") + return build(opcBLENDPD.Forms(), sffxs{}, []operand.Op{i, mx, x}) } // BLENDPS: Blend Packed Single Precision Floating-Point Values. // // Forms: // -// BLENDPS imm8 xmm xmm // BLENDPS imm8 m128 xmm +// BLENDPS imm8 xmm xmm func BLENDPS(i, mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "BLENDPS", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "BLENDPS", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("BLENDPS: bad operands") + return build(opcBLENDPS.Forms(), sffxs{}, []operand.Op{i, mx, x}) } // BLENDVPD: Variable Blend Packed Double Precision Floating-Point Values. // // Forms: // -// BLENDVPD xmm0 xmm xmm // BLENDVPD xmm0 m128 xmm +// BLENDVPD xmm0 xmm xmm func BLENDVPD(x, mx, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM0(x) && operand.IsXMM(mx) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "BLENDVPD", - Operands: []operand.Op{x, mx, x1}, - Inputs: []operand.Op{x, mx, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsXMM0(x) && operand.IsM128(mx) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "BLENDVPD", - Operands: []operand.Op{x, mx, x1}, - Inputs: []operand.Op{x, mx, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("BLENDVPD: bad operands") + return build(opcBLENDVPD.Forms(), sffxs{}, []operand.Op{x, mx, x1}) } // BLENDVPS: Variable Blend Packed Single Precision Floating-Point Values. // // Forms: // -// BLENDVPS xmm0 xmm xmm // BLENDVPS xmm0 m128 xmm +// BLENDVPS xmm0 xmm xmm func BLENDVPS(x, mx, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM0(x) && operand.IsXMM(mx) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "BLENDVPS", - Operands: []operand.Op{x, mx, x1}, - Inputs: []operand.Op{x, mx, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsXMM0(x) && operand.IsM128(mx) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "BLENDVPS", - Operands: []operand.Op{x, mx, x1}, - Inputs: []operand.Op{x, mx, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("BLENDVPS: bad operands") + return build(opcBLENDVPS.Forms(), sffxs{}, []operand.Op{x, mx, x1}) } // BLSIL: Isolate Lowest Set Bit. // // Forms: // -// BLSIL r32 r32 // BLSIL m32 r32 +// BLSIL r32 r32 func BLSIL(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "BLSIL", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"BMI"}, - }, nil - case operand.IsM32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "BLSIL", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"BMI"}, - }, nil - } - return nil, errors.New("BLSIL: bad operands") + return build(opcBLSIL.Forms(), sffxs{}, []operand.Op{mr, r}) } // BLSIQ: Isolate Lowest Set Bit. // // Forms: // -// BLSIQ r64 r64 // BLSIQ m64 r64 +// BLSIQ r64 r64 func BLSIQ(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "BLSIQ", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"BMI"}, - }, nil - case operand.IsM64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "BLSIQ", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"BMI"}, - }, nil - } - return nil, errors.New("BLSIQ: bad operands") + return build(opcBLSIQ.Forms(), sffxs{}, []operand.Op{mr, r}) } // BLSMSKL: Mask From Lowest Set Bit. // // Forms: // -// BLSMSKL r32 r32 // BLSMSKL m32 r32 +// BLSMSKL r32 r32 func BLSMSKL(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "BLSMSKL", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"BMI"}, - }, nil - case operand.IsM32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "BLSMSKL", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"BMI"}, - }, nil - } - return nil, errors.New("BLSMSKL: bad operands") + return build(opcBLSMSKL.Forms(), sffxs{}, []operand.Op{mr, r}) } // BLSMSKQ: Mask From Lowest Set Bit. // // Forms: // -// BLSMSKQ r64 r64 // BLSMSKQ m64 r64 +// BLSMSKQ r64 r64 func BLSMSKQ(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "BLSMSKQ", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"BMI"}, - }, nil - case operand.IsM64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "BLSMSKQ", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"BMI"}, - }, nil - } - return nil, errors.New("BLSMSKQ: bad operands") + return build(opcBLSMSKQ.Forms(), sffxs{}, []operand.Op{mr, r}) } // BLSRL: Reset Lowest Set Bit. // // Forms: // -// BLSRL r32 r32 // BLSRL m32 r32 +// BLSRL r32 r32 func BLSRL(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "BLSRL", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"BMI"}, - }, nil - case operand.IsM32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "BLSRL", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"BMI"}, - }, nil - } - return nil, errors.New("BLSRL: bad operands") + return build(opcBLSRL.Forms(), sffxs{}, []operand.Op{mr, r}) } // BLSRQ: Reset Lowest Set Bit. // // Forms: // -// BLSRQ r64 r64 // BLSRQ m64 r64 +// BLSRQ r64 r64 func BLSRQ(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "BLSRQ", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"BMI"}, - }, nil - case operand.IsM64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "BLSRQ", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"BMI"}, - }, nil - } - return nil, errors.New("BLSRQ: bad operands") + return build(opcBLSRQ.Forms(), sffxs{}, []operand.Op{mr, r}) } // BSFL: Bit Scan Forward. // // Forms: // -// BSFL r32 r32 // BSFL m32 r32 +// BSFL r32 r32 func BSFL(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "BSFL", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - }, nil - case operand.IsM32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "BSFL", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - }, nil - } - return nil, errors.New("BSFL: bad operands") + return build(opcBSFL.Forms(), sffxs{}, []operand.Op{mr, r}) } // BSFQ: Bit Scan Forward. // // Forms: // -// BSFQ r64 r64 // BSFQ m64 r64 +// BSFQ r64 r64 func BSFQ(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "BSFQ", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - }, nil - case operand.IsM64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "BSFQ", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - }, nil - } - return nil, errors.New("BSFQ: bad operands") + return build(opcBSFQ.Forms(), sffxs{}, []operand.Op{mr, r}) } // BSFW: Bit Scan Forward. // // Forms: // -// BSFW r16 r16 // BSFW m16 r16 +// BSFW r16 r16 func BSFW(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "BSFW", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - }, nil - case operand.IsM16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "BSFW", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - }, nil - } - return nil, errors.New("BSFW: bad operands") + return build(opcBSFW.Forms(), sffxs{}, []operand.Op{mr, r}) } // BSRL: Bit Scan Reverse. // // Forms: // -// BSRL r32 r32 // BSRL m32 r32 +// BSRL r32 r32 func BSRL(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "BSRL", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - }, nil - case operand.IsM32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "BSRL", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - }, nil - } - return nil, errors.New("BSRL: bad operands") + return build(opcBSRL.Forms(), sffxs{}, []operand.Op{mr, r}) } // BSRQ: Bit Scan Reverse. // // Forms: // -// BSRQ r64 r64 // BSRQ m64 r64 +// BSRQ r64 r64 func BSRQ(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "BSRQ", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - }, nil - case operand.IsM64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "BSRQ", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - }, nil - } - return nil, errors.New("BSRQ: bad operands") + return build(opcBSRQ.Forms(), sffxs{}, []operand.Op{mr, r}) } // BSRW: Bit Scan Reverse. // // Forms: // -// BSRW r16 r16 // BSRW m16 r16 +// BSRW r16 r16 func BSRW(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "BSRW", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - }, nil - case operand.IsM16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "BSRW", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - }, nil - } - return nil, errors.New("BSRW: bad operands") + return build(opcBSRW.Forms(), sffxs{}, []operand.Op{mr, r}) } // BSWAPL: Byte Swap. @@ -1968,16 +599,7 @@ func BSRW(mr, r operand.Op) (*intrep.Instruction, error) { // // BSWAPL r32 func BSWAPL(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "BSWAPL", - Operands: []operand.Op{r}, - Inputs: []operand.Op{r}, - Outputs: []operand.Op{r}, - }, nil - } - return nil, errors.New("BSWAPL: bad operands") + return build(opcBSWAPL.Forms(), sffxs{}, []operand.Op{r}) } // BSWAPQ: Byte Swap. @@ -1986,576 +608,171 @@ func BSWAPL(r operand.Op) (*intrep.Instruction, error) { // // BSWAPQ r64 func BSWAPQ(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "BSWAPQ", - Operands: []operand.Op{r}, - Inputs: []operand.Op{r}, - Outputs: []operand.Op{r}, - }, nil - } - return nil, errors.New("BSWAPQ: bad operands") + return build(opcBSWAPQ.Forms(), sffxs{}, []operand.Op{r}) } // BTCL: Bit Test and Complement. // // Forms: // -// BTCL imm8 r32 -// BTCL r32 r32 // BTCL imm8 m32 +// BTCL imm8 r32 // BTCL r32 m32 +// BTCL r32 r32 func BTCL(ir, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(ir) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "BTCL", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR32(ir) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "BTCL", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{ir, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ir) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "BTCL", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR32(ir) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "BTCL", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{ir, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("BTCL: bad operands") + return build(opcBTCL.Forms(), sffxs{}, []operand.Op{ir, mr}) } // BTCQ: Bit Test and Complement. // // Forms: // -// BTCQ imm8 r64 -// BTCQ r64 r64 // BTCQ imm8 m64 +// BTCQ imm8 r64 // BTCQ r64 m64 +// BTCQ r64 r64 func BTCQ(ir, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(ir) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "BTCQ", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR64(ir) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "BTCQ", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{ir, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ir) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "BTCQ", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR64(ir) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "BTCQ", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{ir, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("BTCQ: bad operands") + return build(opcBTCQ.Forms(), sffxs{}, []operand.Op{ir, mr}) } // BTCW: Bit Test and Complement. // // Forms: // -// BTCW imm8 r16 -// BTCW r16 r16 // BTCW imm8 m16 +// BTCW imm8 r16 // BTCW r16 m16 +// BTCW r16 r16 func BTCW(ir, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(ir) && operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "BTCW", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR16(ir) && operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "BTCW", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{ir, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ir) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "BTCW", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR16(ir) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "BTCW", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{ir, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("BTCW: bad operands") + return build(opcBTCW.Forms(), sffxs{}, []operand.Op{ir, mr}) } // BTL: Bit Test. // // Forms: // -// BTL imm8 r32 -// BTL r32 r32 // BTL imm8 m32 +// BTL imm8 r32 // BTL r32 m32 +// BTL r32 r32 func BTL(ir, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(ir) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "BTL", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsR32(ir) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "BTL", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{ir, mr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsIMM8(ir) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "BTL", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsR32(ir) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "BTL", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{ir, mr}, - Outputs: []operand.Op{}, - }, nil - } - return nil, errors.New("BTL: bad operands") + return build(opcBTL.Forms(), sffxs{}, []operand.Op{ir, mr}) } // BTQ: Bit Test. // // Forms: // -// BTQ imm8 r64 -// BTQ r64 r64 // BTQ imm8 m64 +// BTQ imm8 r64 // BTQ r64 m64 +// BTQ r64 r64 func BTQ(ir, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(ir) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "BTQ", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsR64(ir) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "BTQ", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{ir, mr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsIMM8(ir) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "BTQ", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsR64(ir) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "BTQ", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{ir, mr}, - Outputs: []operand.Op{}, - }, nil - } - return nil, errors.New("BTQ: bad operands") + return build(opcBTQ.Forms(), sffxs{}, []operand.Op{ir, mr}) } // BTRL: Bit Test and Reset. // // Forms: // -// BTRL imm8 r32 -// BTRL r32 r32 // BTRL imm8 m32 +// BTRL imm8 r32 // BTRL r32 m32 +// BTRL r32 r32 func BTRL(ir, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(ir) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "BTRL", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR32(ir) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "BTRL", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{ir, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ir) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "BTRL", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR32(ir) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "BTRL", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{ir, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("BTRL: bad operands") + return build(opcBTRL.Forms(), sffxs{}, []operand.Op{ir, mr}) } // BTRQ: Bit Test and Reset. // // Forms: // -// BTRQ imm8 r64 -// BTRQ r64 r64 // BTRQ imm8 m64 +// BTRQ imm8 r64 // BTRQ r64 m64 +// BTRQ r64 r64 func BTRQ(ir, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(ir) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "BTRQ", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR64(ir) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "BTRQ", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{ir, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ir) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "BTRQ", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR64(ir) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "BTRQ", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{ir, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("BTRQ: bad operands") + return build(opcBTRQ.Forms(), sffxs{}, []operand.Op{ir, mr}) } // BTRW: Bit Test and Reset. // // Forms: // -// BTRW imm8 r16 -// BTRW r16 r16 // BTRW imm8 m16 +// BTRW imm8 r16 // BTRW r16 m16 +// BTRW r16 r16 func BTRW(ir, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(ir) && operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "BTRW", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR16(ir) && operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "BTRW", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{ir, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ir) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "BTRW", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR16(ir) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "BTRW", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{ir, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("BTRW: bad operands") + return build(opcBTRW.Forms(), sffxs{}, []operand.Op{ir, mr}) } // BTSL: Bit Test and Set. // // Forms: // -// BTSL imm8 r32 -// BTSL r32 r32 // BTSL imm8 m32 +// BTSL imm8 r32 // BTSL r32 m32 +// BTSL r32 r32 func BTSL(ir, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(ir) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "BTSL", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR32(ir) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "BTSL", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{ir, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ir) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "BTSL", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR32(ir) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "BTSL", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{ir, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("BTSL: bad operands") + return build(opcBTSL.Forms(), sffxs{}, []operand.Op{ir, mr}) } // BTSQ: Bit Test and Set. // // Forms: // -// BTSQ imm8 r64 -// BTSQ r64 r64 // BTSQ imm8 m64 +// BTSQ imm8 r64 // BTSQ r64 m64 +// BTSQ r64 r64 func BTSQ(ir, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(ir) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "BTSQ", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR64(ir) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "BTSQ", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{ir, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ir) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "BTSQ", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR64(ir) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "BTSQ", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{ir, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("BTSQ: bad operands") + return build(opcBTSQ.Forms(), sffxs{}, []operand.Op{ir, mr}) } // BTSW: Bit Test and Set. // // Forms: // -// BTSW imm8 r16 -// BTSW r16 r16 // BTSW imm8 m16 +// BTSW imm8 r16 // BTSW r16 m16 +// BTSW r16 r16 func BTSW(ir, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(ir) && operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "BTSW", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR16(ir) && operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "BTSW", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{ir, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ir) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "BTSW", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR16(ir) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "BTSW", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{ir, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("BTSW: bad operands") + return build(opcBTSW.Forms(), sffxs{}, []operand.Op{ir, mr}) } // BTW: Bit Test. // // Forms: // -// BTW imm8 r16 -// BTW r16 r16 // BTW imm8 m16 +// BTW imm8 r16 // BTW r16 m16 +// BTW r16 r16 func BTW(ir, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(ir) && operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "BTW", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsR16(ir) && operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "BTW", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{ir, mr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsIMM8(ir) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "BTW", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsR16(ir) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "BTW", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{ir, mr}, - Outputs: []operand.Op{}, - }, nil - } - return nil, errors.New("BTW: bad operands") + return build(opcBTW.Forms(), sffxs{}, []operand.Op{ir, mr}) } // BZHIL: Zero High Bits Starting with Specified Bit Position. // // Forms: // -// BZHIL r32 r32 r32 // BZHIL r32 m32 r32 +// BZHIL r32 r32 r32 func BZHIL(r, mr, r1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(r) && operand.IsR32(mr) && operand.IsR32(r1): - return &intrep.Instruction{ - Opcode: "BZHIL", - Operands: []operand.Op{r, mr, r1}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI2"}, - }, nil - case operand.IsR32(r) && operand.IsM32(mr) && operand.IsR32(r1): - return &intrep.Instruction{ - Opcode: "BZHIL", - Operands: []operand.Op{r, mr, r1}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI2"}, - }, nil - } - return nil, errors.New("BZHIL: bad operands") + return build(opcBZHIL.Forms(), sffxs{}, []operand.Op{r, mr, r1}) } // BZHIQ: Zero High Bits Starting with Specified Bit Position. // // Forms: // -// BZHIQ r64 r64 r64 // BZHIQ r64 m64 r64 +// BZHIQ r64 r64 r64 func BZHIQ(r, mr, r1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(r) && operand.IsR64(mr) && operand.IsR64(r1): - return &intrep.Instruction{ - Opcode: "BZHIQ", - Operands: []operand.Op{r, mr, r1}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI2"}, - }, nil - case operand.IsR64(r) && operand.IsM64(mr) && operand.IsR64(r1): - return &intrep.Instruction{ - Opcode: "BZHIQ", - Operands: []operand.Op{r, mr, r1}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI2"}, - }, nil - } - return nil, errors.New("BZHIQ: bad operands") + return build(opcBZHIQ.Forms(), sffxs{}, []operand.Op{r, mr, r1}) } // CALL: Call Procedure. @@ -2564,16 +781,7 @@ func BZHIQ(r, mr, r1 operand.Op) (*intrep.Instruction, error) { // // CALL rel32 func CALL(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "CALL", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - }, nil - } - return nil, errors.New("CALL: bad operands") + return build(opcCALL.Forms(), sffxs{}, []operand.Op{r}) } // CBW: Convert Byte to Word. @@ -2582,12 +790,7 @@ func CALL(r operand.Op) (*intrep.Instruction, error) { // // CBW func CBW() (*intrep.Instruction, error) { - return &intrep.Instruction{ - Opcode: "CBW", - Operands: nil, - Inputs: []operand.Op{reg.AL}, - Outputs: []operand.Op{reg.AX}, - }, nil + return build(opcCBW.Forms(), sffxs{}, []operand.Op{}) } // CDQ: Convert Doubleword to Quadword. @@ -2596,12 +799,7 @@ func CBW() (*intrep.Instruction, error) { // // CDQ func CDQ() (*intrep.Instruction, error) { - return &intrep.Instruction{ - Opcode: "CDQ", - Operands: nil, - Inputs: []operand.Op{reg.EAX}, - Outputs: []operand.Op{reg.EDX}, - }, nil + return build(opcCDQ.Forms(), sffxs{}, []operand.Op{}) } // CDQE: Convert Doubleword to Quadword. @@ -2610,12 +808,7 @@ func CDQ() (*intrep.Instruction, error) { // // CDQE func CDQE() (*intrep.Instruction, error) { - return &intrep.Instruction{ - Opcode: "CDQE", - Operands: nil, - Inputs: []operand.Op{reg.EAX}, - Outputs: []operand.Op{reg.RAX}, - }, nil + return build(opcCDQE.Forms(), sffxs{}, []operand.Op{}) } // CLC: Clear Carry Flag. @@ -2624,12 +817,7 @@ func CDQE() (*intrep.Instruction, error) { // // CLC func CLC() (*intrep.Instruction, error) { - return &intrep.Instruction{ - Opcode: "CLC", - Operands: nil, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - }, nil + return build(opcCLC.Forms(), sffxs{}, []operand.Op{}) } // CLD: Clear Direction Flag. @@ -2638,12 +826,7 @@ func CLC() (*intrep.Instruction, error) { // // CLD func CLD() (*intrep.Instruction, error) { - return &intrep.Instruction{ - Opcode: "CLD", - Operands: nil, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - }, nil + return build(opcCLD.Forms(), sffxs{}, []operand.Op{}) } // CLFLUSH: Flush Cache Line. @@ -2652,17 +835,7 @@ func CLD() (*intrep.Instruction, error) { // // CLFLUSH m8 func CLFLUSH(m operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM8(m): - return &intrep.Instruction{ - Opcode: "CLFLUSH", - Operands: []operand.Op{m}, - Inputs: []operand.Op{m}, - Outputs: []operand.Op{}, - ISA: []string{"CLFLUSH"}, - }, nil - } - return nil, errors.New("CLFLUSH: bad operands") + return build(opcCLFLUSH.Forms(), sffxs{}, []operand.Op{m}) } // CLFLUSHOPT: Flush Cache Line Optimized. @@ -2671,17 +844,7 @@ func CLFLUSH(m operand.Op) (*intrep.Instruction, error) { // // CLFLUSHOPT m8 func CLFLUSHOPT(m operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM8(m): - return &intrep.Instruction{ - Opcode: "CLFLUSHOPT", - Operands: []operand.Op{m}, - Inputs: []operand.Op{m}, - Outputs: []operand.Op{}, - ISA: []string{"CLFLUSHOPT"}, - }, nil - } - return nil, errors.New("CLFLUSHOPT: bad operands") + return build(opcCLFLUSHOPT.Forms(), sffxs{}, []operand.Op{m}) } // CMC: Complement Carry Flag. @@ -2690,1356 +853,487 @@ func CLFLUSHOPT(m operand.Op) (*intrep.Instruction, error) { // // CMC func CMC() (*intrep.Instruction, error) { - return &intrep.Instruction{ - Opcode: "CMC", - Operands: nil, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - }, nil + return build(opcCMC.Forms(), sffxs{}, []operand.Op{}) } // CMOVLCC: Move if above or equal (CF == 0). // // Forms: // -// CMOVLCC r32 r32 // CMOVLCC m32 r32 +// CMOVLCC r32 r32 func CMOVLCC(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLCC", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLCC", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVLCC: bad operands") + return build(opcCMOVLCC.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVLCS: Move if below (CF == 1). // // Forms: // -// CMOVLCS r32 r32 // CMOVLCS m32 r32 +// CMOVLCS r32 r32 func CMOVLCS(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLCS", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLCS", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVLCS: bad operands") + return build(opcCMOVLCS.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVLEQ: Move if equal (ZF == 1). // // Forms: // -// CMOVLEQ r32 r32 // CMOVLEQ m32 r32 +// CMOVLEQ r32 r32 func CMOVLEQ(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLEQ", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLEQ", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVLEQ: bad operands") + return build(opcCMOVLEQ.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVLGE: Move if greater or equal (SF == OF). // // Forms: // -// CMOVLGE r32 r32 // CMOVLGE m32 r32 +// CMOVLGE r32 r32 func CMOVLGE(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLGE", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLGE", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVLGE: bad operands") + return build(opcCMOVLGE.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVLGT: Move if greater (ZF == 0 and SF == OF). // // Forms: // -// CMOVLGT r32 r32 // CMOVLGT m32 r32 +// CMOVLGT r32 r32 func CMOVLGT(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLGT", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLGT", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVLGT: bad operands") + return build(opcCMOVLGT.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVLHI: Move if above (CF == 0 and ZF == 0). // // Forms: // -// CMOVLHI r32 r32 // CMOVLHI m32 r32 +// CMOVLHI r32 r32 func CMOVLHI(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLHI", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLHI", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVLHI: bad operands") + return build(opcCMOVLHI.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVLLE: Move if less or equal (ZF == 1 or SF != OF). // // Forms: // -// CMOVLLE r32 r32 // CMOVLLE m32 r32 +// CMOVLLE r32 r32 func CMOVLLE(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLLE", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLLE", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVLLE: bad operands") + return build(opcCMOVLLE.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVLLS: Move if below or equal (CF == 1 or ZF == 1). // // Forms: // -// CMOVLLS r32 r32 // CMOVLLS m32 r32 +// CMOVLLS r32 r32 func CMOVLLS(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLLS", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLLS", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVLLS: bad operands") + return build(opcCMOVLLS.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVLLT: Move if less (SF != OF). // // Forms: // -// CMOVLLT r32 r32 // CMOVLLT m32 r32 +// CMOVLLT r32 r32 func CMOVLLT(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLLT", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLLT", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVLLT: bad operands") + return build(opcCMOVLLT.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVLMI: Move if sign (SF == 1). // // Forms: // -// CMOVLMI r32 r32 // CMOVLMI m32 r32 +// CMOVLMI r32 r32 func CMOVLMI(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLMI", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLMI", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVLMI: bad operands") + return build(opcCMOVLMI.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVLNE: Move if not equal (ZF == 0). // // Forms: // -// CMOVLNE r32 r32 // CMOVLNE m32 r32 +// CMOVLNE r32 r32 func CMOVLNE(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLNE", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLNE", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVLNE: bad operands") + return build(opcCMOVLNE.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVLOC: Move if not overflow (OF == 0). // // Forms: // -// CMOVLOC r32 r32 // CMOVLOC m32 r32 +// CMOVLOC r32 r32 func CMOVLOC(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLOC", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLOC", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVLOC: bad operands") + return build(opcCMOVLOC.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVLOS: Move if overflow (OF == 1). // // Forms: // -// CMOVLOS r32 r32 // CMOVLOS m32 r32 +// CMOVLOS r32 r32 func CMOVLOS(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLOS", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLOS", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVLOS: bad operands") + return build(opcCMOVLOS.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVLPC: Move if not parity (PF == 0). // // Forms: // -// CMOVLPC r32 r32 // CMOVLPC m32 r32 +// CMOVLPC r32 r32 func CMOVLPC(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLPC", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLPC", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVLPC: bad operands") + return build(opcCMOVLPC.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVLPL: Move if not sign (SF == 0). // // Forms: // -// CMOVLPL r32 r32 // CMOVLPL m32 r32 +// CMOVLPL r32 r32 func CMOVLPL(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLPL", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLPL", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVLPL: bad operands") + return build(opcCMOVLPL.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVLPS: Move if parity (PF == 1). // // Forms: // -// CMOVLPS r32 r32 // CMOVLPS m32 r32 +// CMOVLPS r32 r32 func CMOVLPS(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLPS", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CMOVLPS", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVLPS: bad operands") + return build(opcCMOVLPS.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVQCC: Move if above or equal (CF == 0). // // Forms: // -// CMOVQCC r64 r64 // CMOVQCC m64 r64 +// CMOVQCC r64 r64 func CMOVQCC(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQCC", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQCC", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVQCC: bad operands") + return build(opcCMOVQCC.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVQCS: Move if below (CF == 1). // // Forms: // -// CMOVQCS r64 r64 // CMOVQCS m64 r64 +// CMOVQCS r64 r64 func CMOVQCS(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQCS", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQCS", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVQCS: bad operands") + return build(opcCMOVQCS.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVQEQ: Move if equal (ZF == 1). // // Forms: // -// CMOVQEQ r64 r64 // CMOVQEQ m64 r64 +// CMOVQEQ r64 r64 func CMOVQEQ(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQEQ", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQEQ", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVQEQ: bad operands") + return build(opcCMOVQEQ.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVQGE: Move if greater or equal (SF == OF). // // Forms: // -// CMOVQGE r64 r64 // CMOVQGE m64 r64 +// CMOVQGE r64 r64 func CMOVQGE(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQGE", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQGE", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVQGE: bad operands") + return build(opcCMOVQGE.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVQGT: Move if greater (ZF == 0 and SF == OF). // // Forms: // -// CMOVQGT r64 r64 // CMOVQGT m64 r64 +// CMOVQGT r64 r64 func CMOVQGT(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQGT", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQGT", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVQGT: bad operands") + return build(opcCMOVQGT.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVQHI: Move if above (CF == 0 and ZF == 0). // // Forms: // -// CMOVQHI r64 r64 // CMOVQHI m64 r64 +// CMOVQHI r64 r64 func CMOVQHI(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQHI", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQHI", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVQHI: bad operands") + return build(opcCMOVQHI.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVQLE: Move if less or equal (ZF == 1 or SF != OF). // // Forms: // -// CMOVQLE r64 r64 // CMOVQLE m64 r64 +// CMOVQLE r64 r64 func CMOVQLE(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQLE", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQLE", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVQLE: bad operands") + return build(opcCMOVQLE.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVQLS: Move if below or equal (CF == 1 or ZF == 1). // // Forms: // -// CMOVQLS r64 r64 // CMOVQLS m64 r64 +// CMOVQLS r64 r64 func CMOVQLS(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQLS", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQLS", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVQLS: bad operands") + return build(opcCMOVQLS.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVQLT: Move if less (SF != OF). // // Forms: // -// CMOVQLT r64 r64 // CMOVQLT m64 r64 +// CMOVQLT r64 r64 func CMOVQLT(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQLT", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQLT", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVQLT: bad operands") + return build(opcCMOVQLT.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVQMI: Move if sign (SF == 1). // // Forms: // -// CMOVQMI r64 r64 // CMOVQMI m64 r64 +// CMOVQMI r64 r64 func CMOVQMI(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQMI", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQMI", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVQMI: bad operands") + return build(opcCMOVQMI.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVQNE: Move if not equal (ZF == 0). // // Forms: // -// CMOVQNE r64 r64 // CMOVQNE m64 r64 +// CMOVQNE r64 r64 func CMOVQNE(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQNE", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQNE", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVQNE: bad operands") + return build(opcCMOVQNE.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVQOC: Move if not overflow (OF == 0). // // Forms: // -// CMOVQOC r64 r64 // CMOVQOC m64 r64 +// CMOVQOC r64 r64 func CMOVQOC(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQOC", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQOC", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVQOC: bad operands") + return build(opcCMOVQOC.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVQOS: Move if overflow (OF == 1). // // Forms: // -// CMOVQOS r64 r64 // CMOVQOS m64 r64 +// CMOVQOS r64 r64 func CMOVQOS(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQOS", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQOS", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVQOS: bad operands") + return build(opcCMOVQOS.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVQPC: Move if not parity (PF == 0). // // Forms: // -// CMOVQPC r64 r64 // CMOVQPC m64 r64 +// CMOVQPC r64 r64 func CMOVQPC(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQPC", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQPC", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVQPC: bad operands") + return build(opcCMOVQPC.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVQPL: Move if not sign (SF == 0). // // Forms: // -// CMOVQPL r64 r64 // CMOVQPL m64 r64 +// CMOVQPL r64 r64 func CMOVQPL(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQPL", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQPL", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVQPL: bad operands") + return build(opcCMOVQPL.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVQPS: Move if parity (PF == 1). // // Forms: // -// CMOVQPS r64 r64 // CMOVQPS m64 r64 +// CMOVQPS r64 r64 func CMOVQPS(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQPS", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CMOVQPS", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVQPS: bad operands") + return build(opcCMOVQPS.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVWCC: Move if above or equal (CF == 0). // // Forms: // -// CMOVWCC r16 r16 // CMOVWCC m16 r16 +// CMOVWCC r16 r16 func CMOVWCC(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWCC", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWCC", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVWCC: bad operands") + return build(opcCMOVWCC.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVWCS: Move if below (CF == 1). // // Forms: // -// CMOVWCS r16 r16 // CMOVWCS m16 r16 +// CMOVWCS r16 r16 func CMOVWCS(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWCS", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWCS", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVWCS: bad operands") + return build(opcCMOVWCS.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVWEQ: Move if equal (ZF == 1). // // Forms: // -// CMOVWEQ r16 r16 // CMOVWEQ m16 r16 +// CMOVWEQ r16 r16 func CMOVWEQ(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWEQ", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWEQ", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVWEQ: bad operands") + return build(opcCMOVWEQ.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVWGE: Move if greater or equal (SF == OF). // // Forms: // -// CMOVWGE r16 r16 // CMOVWGE m16 r16 +// CMOVWGE r16 r16 func CMOVWGE(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWGE", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWGE", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVWGE: bad operands") + return build(opcCMOVWGE.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVWGT: Move if greater (ZF == 0 and SF == OF). // // Forms: // -// CMOVWGT r16 r16 // CMOVWGT m16 r16 +// CMOVWGT r16 r16 func CMOVWGT(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWGT", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWGT", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVWGT: bad operands") + return build(opcCMOVWGT.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVWHI: Move if above (CF == 0 and ZF == 0). // // Forms: // -// CMOVWHI r16 r16 // CMOVWHI m16 r16 +// CMOVWHI r16 r16 func CMOVWHI(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWHI", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWHI", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVWHI: bad operands") + return build(opcCMOVWHI.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVWLE: Move if less or equal (ZF == 1 or SF != OF). // // Forms: // -// CMOVWLE r16 r16 // CMOVWLE m16 r16 +// CMOVWLE r16 r16 func CMOVWLE(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWLE", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWLE", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVWLE: bad operands") + return build(opcCMOVWLE.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVWLS: Move if below or equal (CF == 1 or ZF == 1). // // Forms: // -// CMOVWLS r16 r16 // CMOVWLS m16 r16 +// CMOVWLS r16 r16 func CMOVWLS(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWLS", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWLS", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVWLS: bad operands") + return build(opcCMOVWLS.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVWLT: Move if less (SF != OF). // // Forms: // -// CMOVWLT r16 r16 // CMOVWLT m16 r16 +// CMOVWLT r16 r16 func CMOVWLT(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWLT", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWLT", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVWLT: bad operands") + return build(opcCMOVWLT.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVWMI: Move if sign (SF == 1). // // Forms: // -// CMOVWMI r16 r16 // CMOVWMI m16 r16 +// CMOVWMI r16 r16 func CMOVWMI(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWMI", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWMI", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVWMI: bad operands") + return build(opcCMOVWMI.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVWNE: Move if not equal (ZF == 0). // // Forms: // -// CMOVWNE r16 r16 // CMOVWNE m16 r16 +// CMOVWNE r16 r16 func CMOVWNE(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWNE", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWNE", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVWNE: bad operands") + return build(opcCMOVWNE.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVWOC: Move if not overflow (OF == 0). // // Forms: // -// CMOVWOC r16 r16 // CMOVWOC m16 r16 +// CMOVWOC r16 r16 func CMOVWOC(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWOC", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWOC", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVWOC: bad operands") + return build(opcCMOVWOC.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVWOS: Move if overflow (OF == 1). // // Forms: // -// CMOVWOS r16 r16 // CMOVWOS m16 r16 +// CMOVWOS r16 r16 func CMOVWOS(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWOS", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWOS", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVWOS: bad operands") + return build(opcCMOVWOS.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVWPC: Move if not parity (PF == 0). // // Forms: // -// CMOVWPC r16 r16 // CMOVWPC m16 r16 +// CMOVWPC r16 r16 func CMOVWPC(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWPC", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWPC", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVWPC: bad operands") + return build(opcCMOVWPC.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVWPL: Move if not sign (SF == 0). // // Forms: // -// CMOVWPL r16 r16 // CMOVWPL m16 r16 +// CMOVWPL r16 r16 func CMOVWPL(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWPL", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWPL", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVWPL: bad operands") + return build(opcCMOVWPL.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMOVWPS: Move if parity (PF == 1). // // Forms: // -// CMOVWPS r16 r16 // CMOVWPS m16 r16 +// CMOVWPS r16 r16 func CMOVWPS(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWPS", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - case operand.IsM16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "CMOVWPS", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"CMOV"}, - }, nil - } - return nil, errors.New("CMOVWPS: bad operands") + return build(opcCMOVWPS.Forms(), sffxs{}, []operand.Op{mr, r}) } // CMPB: Compare Two Operands. @@ -4047,58 +1341,13 @@ func CMOVWPS(mr, r operand.Op) (*intrep.Instruction, error) { // Forms: // // CMPB al imm8 -// CMPB r8 imm8 -// CMPB r8 r8 -// CMPB r8 m8 // CMPB m8 imm8 // CMPB m8 r8 +// CMPB r8 imm8 +// CMPB r8 m8 +// CMPB r8 r8 func CMPB(amr, imr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsAL(amr) && operand.IsIMM8(imr): - return &intrep.Instruction{ - Opcode: "CMPB", - Operands: []operand.Op{amr, imr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsR8(amr) && operand.IsIMM8(imr): - return &intrep.Instruction{ - Opcode: "CMPB", - Operands: []operand.Op{amr, imr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsR8(amr) && operand.IsR8(imr): - return &intrep.Instruction{ - Opcode: "CMPB", - Operands: []operand.Op{amr, imr}, - Inputs: []operand.Op{amr, imr}, - Outputs: []operand.Op{}, - CancellingInputs: true, - }, nil - case operand.IsR8(amr) && operand.IsM8(imr): - return &intrep.Instruction{ - Opcode: "CMPB", - Operands: []operand.Op{amr, imr}, - Inputs: []operand.Op{amr, imr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsM8(amr) && operand.IsIMM8(imr): - return &intrep.Instruction{ - Opcode: "CMPB", - Operands: []operand.Op{amr, imr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsM8(amr) && operand.IsR8(imr): - return &intrep.Instruction{ - Opcode: "CMPB", - Operands: []operand.Op{amr, imr}, - Inputs: []operand.Op{amr, imr}, - Outputs: []operand.Op{}, - }, nil - } - return nil, errors.New("CMPB: bad operands") + return build(opcCMPB.Forms(), sffxs{}, []operand.Op{amr, imr}) } // CMPL: Compare Two Operands. @@ -4106,261 +1355,71 @@ func CMPB(amr, imr operand.Op) (*intrep.Instruction, error) { // Forms: // // CMPL eax imm32 -// CMPL r32 imm8 -// CMPL r32 imm32 -// CMPL r32 r32 -// CMPL r32 m32 -// CMPL m32 imm8 // CMPL m32 imm32 +// CMPL m32 imm8 // CMPL m32 r32 +// CMPL r32 imm32 +// CMPL r32 imm8 +// CMPL r32 m32 +// CMPL r32 r32 func CMPL(emr, imr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsEAX(emr) && operand.IsIMM32(imr): - return &intrep.Instruction{ - Opcode: "CMPL", - Operands: []operand.Op{emr, imr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsR32(emr) && operand.IsIMM8(imr): - return &intrep.Instruction{ - Opcode: "CMPL", - Operands: []operand.Op{emr, imr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsR32(emr) && operand.IsIMM32(imr): - return &intrep.Instruction{ - Opcode: "CMPL", - Operands: []operand.Op{emr, imr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsR32(emr) && operand.IsR32(imr): - return &intrep.Instruction{ - Opcode: "CMPL", - Operands: []operand.Op{emr, imr}, - Inputs: []operand.Op{emr, imr}, - Outputs: []operand.Op{}, - CancellingInputs: true, - }, nil - case operand.IsR32(emr) && operand.IsM32(imr): - return &intrep.Instruction{ - Opcode: "CMPL", - Operands: []operand.Op{emr, imr}, - Inputs: []operand.Op{emr, imr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsM32(emr) && operand.IsIMM8(imr): - return &intrep.Instruction{ - Opcode: "CMPL", - Operands: []operand.Op{emr, imr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsM32(emr) && operand.IsIMM32(imr): - return &intrep.Instruction{ - Opcode: "CMPL", - Operands: []operand.Op{emr, imr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsM32(emr) && operand.IsR32(imr): - return &intrep.Instruction{ - Opcode: "CMPL", - Operands: []operand.Op{emr, imr}, - Inputs: []operand.Op{emr, imr}, - Outputs: []operand.Op{}, - }, nil - } - return nil, errors.New("CMPL: bad operands") + return build(opcCMPL.Forms(), sffxs{}, []operand.Op{emr, imr}) } // CMPPD: Compare Packed Double-Precision Floating-Point Values. // // Forms: // -// CMPPD xmm xmm imm8 // CMPPD m128 xmm imm8 +// CMPPD xmm xmm imm8 func CMPPD(mx, x, i operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsIMM8(i): - return &intrep.Instruction{ - Opcode: "CMPPD", - Operands: []operand.Op{mx, x, i}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x) && operand.IsIMM8(i): - return &intrep.Instruction{ - Opcode: "CMPPD", - Operands: []operand.Op{mx, x, i}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("CMPPD: bad operands") + return build(opcCMPPD.Forms(), sffxs{}, []operand.Op{mx, x, i}) } // CMPPS: Compare Packed Single-Precision Floating-Point Values. // // Forms: // -// CMPPS xmm xmm imm8 // CMPPS m128 xmm imm8 +// CMPPS xmm xmm imm8 func CMPPS(mx, x, i operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsIMM8(i): - return &intrep.Instruction{ - Opcode: "CMPPS", - Operands: []operand.Op{mx, x, i}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x) && operand.IsIMM8(i): - return &intrep.Instruction{ - Opcode: "CMPPS", - Operands: []operand.Op{mx, x, i}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("CMPPS: bad operands") + return build(opcCMPPS.Forms(), sffxs{}, []operand.Op{mx, x, i}) } // CMPQ: Compare Two Operands. // // Forms: // -// CMPQ rax imm32 -// CMPQ r64 imm8 -// CMPQ r64 imm32 -// CMPQ r64 r64 -// CMPQ r64 m64 -// CMPQ m64 imm8 // CMPQ m64 imm32 +// CMPQ m64 imm8 // CMPQ m64 r64 +// CMPQ r64 imm32 +// CMPQ r64 imm8 +// CMPQ r64 m64 +// CMPQ r64 r64 +// CMPQ rax imm32 func CMPQ(mr, imr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsRAX(mr) && operand.IsIMM32(imr): - return &intrep.Instruction{ - Opcode: "CMPQ", - Operands: []operand.Op{mr, imr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsR64(mr) && operand.IsIMM8(imr): - return &intrep.Instruction{ - Opcode: "CMPQ", - Operands: []operand.Op{mr, imr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsR64(mr) && operand.IsIMM32(imr): - return &intrep.Instruction{ - Opcode: "CMPQ", - Operands: []operand.Op{mr, imr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsR64(mr) && operand.IsR64(imr): - return &intrep.Instruction{ - Opcode: "CMPQ", - Operands: []operand.Op{mr, imr}, - Inputs: []operand.Op{mr, imr}, - Outputs: []operand.Op{}, - CancellingInputs: true, - }, nil - case operand.IsR64(mr) && operand.IsM64(imr): - return &intrep.Instruction{ - Opcode: "CMPQ", - Operands: []operand.Op{mr, imr}, - Inputs: []operand.Op{mr, imr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsM64(mr) && operand.IsIMM8(imr): - return &intrep.Instruction{ - Opcode: "CMPQ", - Operands: []operand.Op{mr, imr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsM64(mr) && operand.IsIMM32(imr): - return &intrep.Instruction{ - Opcode: "CMPQ", - Operands: []operand.Op{mr, imr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsM64(mr) && operand.IsR64(imr): - return &intrep.Instruction{ - Opcode: "CMPQ", - Operands: []operand.Op{mr, imr}, - Inputs: []operand.Op{mr, imr}, - Outputs: []operand.Op{}, - }, nil - } - return nil, errors.New("CMPQ: bad operands") + return build(opcCMPQ.Forms(), sffxs{}, []operand.Op{mr, imr}) } // CMPSD: Compare Scalar Double-Precision Floating-Point Values. // // Forms: // -// CMPSD xmm xmm imm8 // CMPSD m64 xmm imm8 +// CMPSD xmm xmm imm8 func CMPSD(mx, x, i operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsIMM8(i): - return &intrep.Instruction{ - Opcode: "CMPSD", - Operands: []operand.Op{mx, x, i}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x) && operand.IsIMM8(i): - return &intrep.Instruction{ - Opcode: "CMPSD", - Operands: []operand.Op{mx, x, i}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("CMPSD: bad operands") + return build(opcCMPSD.Forms(), sffxs{}, []operand.Op{mx, x, i}) } // CMPSS: Compare Scalar Single-Precision Floating-Point Values. // // Forms: // -// CMPSS xmm xmm imm8 // CMPSS m32 xmm imm8 +// CMPSS xmm xmm imm8 func CMPSS(mx, x, i operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsIMM8(i): - return &intrep.Instruction{ - Opcode: "CMPSS", - Operands: []operand.Op{mx, x, i}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x) && operand.IsIMM8(i): - return &intrep.Instruction{ - Opcode: "CMPSS", - Operands: []operand.Op{mx, x, i}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("CMPSS: bad operands") + return build(opcCMPSS.Forms(), sffxs{}, []operand.Op{mx, x, i}) } // CMPW: Compare Two Operands. @@ -4368,74 +1427,15 @@ func CMPSS(mx, x, i operand.Op) (*intrep.Instruction, error) { // Forms: // // CMPW ax imm16 -// CMPW r16 imm8 -// CMPW r16 imm16 -// CMPW r16 r16 -// CMPW r16 m16 -// CMPW m16 imm8 // CMPW m16 imm16 +// CMPW m16 imm8 // CMPW m16 r16 +// CMPW r16 imm16 +// CMPW r16 imm8 +// CMPW r16 m16 +// CMPW r16 r16 func CMPW(amr, imr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsAX(amr) && operand.IsIMM16(imr): - return &intrep.Instruction{ - Opcode: "CMPW", - Operands: []operand.Op{amr, imr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsR16(amr) && operand.IsIMM8(imr): - return &intrep.Instruction{ - Opcode: "CMPW", - Operands: []operand.Op{amr, imr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsR16(amr) && operand.IsIMM16(imr): - return &intrep.Instruction{ - Opcode: "CMPW", - Operands: []operand.Op{amr, imr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsR16(amr) && operand.IsR16(imr): - return &intrep.Instruction{ - Opcode: "CMPW", - Operands: []operand.Op{amr, imr}, - Inputs: []operand.Op{amr, imr}, - Outputs: []operand.Op{}, - CancellingInputs: true, - }, nil - case operand.IsR16(amr) && operand.IsM16(imr): - return &intrep.Instruction{ - Opcode: "CMPW", - Operands: []operand.Op{amr, imr}, - Inputs: []operand.Op{amr, imr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsM16(amr) && operand.IsIMM8(imr): - return &intrep.Instruction{ - Opcode: "CMPW", - Operands: []operand.Op{amr, imr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsM16(amr) && operand.IsIMM16(imr): - return &intrep.Instruction{ - Opcode: "CMPW", - Operands: []operand.Op{amr, imr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsM16(amr) && operand.IsR16(imr): - return &intrep.Instruction{ - Opcode: "CMPW", - Operands: []operand.Op{amr, imr}, - Inputs: []operand.Op{amr, imr}, - Outputs: []operand.Op{}, - }, nil - } - return nil, errors.New("CMPW: bad operands") + return build(opcCMPW.Forms(), sffxs{}, []operand.Op{amr, imr}) } // CMPXCHG16B: Compare and Exchange 16 Bytes. @@ -4444,16 +1444,7 @@ func CMPW(amr, imr operand.Op) (*intrep.Instruction, error) { // // CMPXCHG16B m128 func CMPXCHG16B(m operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM128(m): - return &intrep.Instruction{ - Opcode: "CMPXCHG16B", - Operands: []operand.Op{m}, - Inputs: []operand.Op{m, reg.RAX, reg.RBX, reg.RCX, reg.RDX}, - Outputs: []operand.Op{reg.RAX, reg.RDX}, - }, nil - } - return nil, errors.New("CMPXCHG16B: bad operands") + return build(opcCMPXCHG16B.Forms(), sffxs{}, []operand.Op{m}) } // CMPXCHG8B: Compare and Exchange 8 Bytes. @@ -4462,176 +1453,67 @@ func CMPXCHG16B(m operand.Op) (*intrep.Instruction, error) { // // CMPXCHG8B m64 func CMPXCHG8B(m operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM64(m): - return &intrep.Instruction{ - Opcode: "CMPXCHG8B", - Operands: []operand.Op{m}, - Inputs: []operand.Op{m, reg.EAX, reg.EBX, reg.ECX, reg.EDX}, - Outputs: []operand.Op{reg.EAX, reg.EDX}, - }, nil - } - return nil, errors.New("CMPXCHG8B: bad operands") + return build(opcCMPXCHG8B.Forms(), sffxs{}, []operand.Op{m}) } // CMPXCHGB: Compare and Exchange. // // Forms: // -// CMPXCHGB r8 r8 // CMPXCHGB r8 m8 +// CMPXCHGB r8 r8 func CMPXCHGB(r, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(r) && operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "CMPXCHGB", - Operands: []operand.Op{r, mr}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR8(r) && operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "CMPXCHGB", - Operands: []operand.Op{r, mr}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("CMPXCHGB: bad operands") + return build(opcCMPXCHGB.Forms(), sffxs{}, []operand.Op{r, mr}) } // CMPXCHGL: Compare and Exchange. // // Forms: // -// CMPXCHGL r32 r32 // CMPXCHGL r32 m32 +// CMPXCHGL r32 r32 func CMPXCHGL(r, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(r) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "CMPXCHGL", - Operands: []operand.Op{r, mr}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR32(r) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "CMPXCHGL", - Operands: []operand.Op{r, mr}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("CMPXCHGL: bad operands") + return build(opcCMPXCHGL.Forms(), sffxs{}, []operand.Op{r, mr}) } // CMPXCHGQ: Compare and Exchange. // // Forms: // -// CMPXCHGQ r64 r64 // CMPXCHGQ r64 m64 +// CMPXCHGQ r64 r64 func CMPXCHGQ(r, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(r) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "CMPXCHGQ", - Operands: []operand.Op{r, mr}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR64(r) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "CMPXCHGQ", - Operands: []operand.Op{r, mr}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("CMPXCHGQ: bad operands") + return build(opcCMPXCHGQ.Forms(), sffxs{}, []operand.Op{r, mr}) } // CMPXCHGW: Compare and Exchange. // // Forms: // -// CMPXCHGW r16 r16 // CMPXCHGW r16 m16 +// CMPXCHGW r16 r16 func CMPXCHGW(r, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(r) && operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "CMPXCHGW", - Operands: []operand.Op{r, mr}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR16(r) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "CMPXCHGW", - Operands: []operand.Op{r, mr}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("CMPXCHGW: bad operands") + return build(opcCMPXCHGW.Forms(), sffxs{}, []operand.Op{r, mr}) } // COMISD: Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS. // // Forms: // -// COMISD xmm xmm // COMISD m64 xmm +// COMISD xmm xmm func COMISD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "COMISD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "COMISD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("COMISD: bad operands") + return build(opcCOMISD.Forms(), sffxs{}, []operand.Op{mx, x}) } // COMISS: Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS. // // Forms: // -// COMISS xmm xmm // COMISS m32 xmm +// COMISS xmm xmm func COMISS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "COMISS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "COMISS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("COMISS: bad operands") + return build(opcCOMISS.Forms(), sffxs{}, []operand.Op{mx, x}) } // CPUID: CPU Identification. @@ -4640,13 +1522,7 @@ func COMISS(mx, x operand.Op) (*intrep.Instruction, error) { // // CPUID func CPUID() (*intrep.Instruction, error) { - return &intrep.Instruction{ - Opcode: "CPUID", - Operands: nil, - Inputs: []operand.Op{reg.EAX, reg.ECX}, - Outputs: []operand.Op{reg.EAX, reg.EBX, reg.ECX, reg.EDX}, - ISA: []string{"CPUID"}, - }, nil + return build(opcCPUID.Forms(), sffxs{}, []operand.Op{}) } // CQO: Convert Quadword to Octaword. @@ -4655,728 +1531,245 @@ func CPUID() (*intrep.Instruction, error) { // // CQO func CQO() (*intrep.Instruction, error) { - return &intrep.Instruction{ - Opcode: "CQO", - Operands: nil, - Inputs: []operand.Op{reg.RAX}, - Outputs: []operand.Op{reg.RDX}, - }, nil + return build(opcCQO.Forms(), sffxs{}, []operand.Op{}) } // CRC32B: Accumulate CRC32 Value. // // Forms: // -// CRC32B r8 r32 // CRC32B m8 r32 -// CRC32B r8 r64 // CRC32B m8 r64 +// CRC32B r8 r32 +// CRC32B r8 r64 func CRC32B(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CRC32B", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"SSE4.2"}, - }, nil - case operand.IsM8(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CRC32B", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"SSE4.2"}, - }, nil - case operand.IsR8(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CRC32B", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"SSE4.2"}, - }, nil - case operand.IsM8(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CRC32B", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"SSE4.2"}, - }, nil - } - return nil, errors.New("CRC32B: bad operands") + return build(opcCRC32B.Forms(), sffxs{}, []operand.Op{mr, r}) } // CRC32L: Accumulate CRC32 Value. // // Forms: // -// CRC32L r32 r32 // CRC32L m32 r32 +// CRC32L r32 r32 func CRC32L(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CRC32L", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"SSE4.2"}, - }, nil - case operand.IsM32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CRC32L", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"SSE4.2"}, - }, nil - } - return nil, errors.New("CRC32L: bad operands") + return build(opcCRC32L.Forms(), sffxs{}, []operand.Op{mr, r}) } // CRC32Q: Accumulate CRC32 Value. // // Forms: // -// CRC32Q r64 r64 // CRC32Q m64 r64 +// CRC32Q r64 r64 func CRC32Q(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CRC32Q", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"SSE4.2"}, - }, nil - case operand.IsM64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CRC32Q", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"SSE4.2"}, - }, nil - } - return nil, errors.New("CRC32Q: bad operands") + return build(opcCRC32Q.Forms(), sffxs{}, []operand.Op{mr, r}) } // CRC32W: Accumulate CRC32 Value. // // Forms: // -// CRC32W r16 r32 // CRC32W m16 r32 +// CRC32W r16 r32 func CRC32W(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CRC32W", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"SSE4.2"}, - }, nil - case operand.IsM16(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CRC32W", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r}, - ISA: []string{"SSE4.2"}, - }, nil - } - return nil, errors.New("CRC32W: bad operands") + return build(opcCRC32W.Forms(), sffxs{}, []operand.Op{mr, r}) } // CVTPD2PL: Convert Packed Double-Precision FP Values to Packed Dword Integers. // // Forms: // -// CVTPD2PL xmm xmm // CVTPD2PL m128 xmm +// CVTPD2PL xmm xmm func CVTPD2PL(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "CVTPD2PL", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "CVTPD2PL", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("CVTPD2PL: bad operands") + return build(opcCVTPD2PL.Forms(), sffxs{}, []operand.Op{mx, x}) } // CVTPD2PS: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values. // // Forms: // -// CVTPD2PS xmm xmm // CVTPD2PS m128 xmm +// CVTPD2PS xmm xmm func CVTPD2PS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "CVTPD2PS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "CVTPD2PS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("CVTPD2PS: bad operands") + return build(opcCVTPD2PS.Forms(), sffxs{}, []operand.Op{mx, x}) } // CVTPL2PD: Convert Packed Dword Integers to Packed Double-Precision FP Values. // // Forms: // -// CVTPL2PD xmm xmm // CVTPL2PD m64 xmm +// CVTPL2PD xmm xmm func CVTPL2PD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "CVTPL2PD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "CVTPL2PD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("CVTPL2PD: bad operands") + return build(opcCVTPL2PD.Forms(), sffxs{}, []operand.Op{mx, x}) } // CVTPL2PS: Convert Packed Dword Integers to Packed Single-Precision FP Values. // // Forms: // -// CVTPL2PS xmm xmm // CVTPL2PS m128 xmm +// CVTPL2PS xmm xmm func CVTPL2PS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "CVTPL2PS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "CVTPL2PS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("CVTPL2PS: bad operands") + return build(opcCVTPL2PS.Forms(), sffxs{}, []operand.Op{mx, x}) } // CVTPS2PD: Convert Packed Single-Precision FP Values to Packed Double-Precision FP Values. // // Forms: // -// CVTPS2PD xmm xmm // CVTPS2PD m64 xmm +// CVTPS2PD xmm xmm func CVTPS2PD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "CVTPS2PD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "CVTPS2PD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("CVTPS2PD: bad operands") + return build(opcCVTPS2PD.Forms(), sffxs{}, []operand.Op{mx, x}) } // CVTPS2PL: Convert Packed Single-Precision FP Values to Packed Dword Integers. // // Forms: // -// CVTPS2PL xmm xmm // CVTPS2PL m128 xmm +// CVTPS2PL xmm xmm func CVTPS2PL(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "CVTPS2PL", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "CVTPS2PL", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("CVTPS2PL: bad operands") + return build(opcCVTPS2PL.Forms(), sffxs{}, []operand.Op{mx, x}) } // CVTSD2SL: Convert Scalar Double-Precision FP Value to Integer. // // Forms: // -// CVTSD2SL xmm r32 // CVTSD2SL m64 r32 -// CVTSD2SL xmm r64 // CVTSD2SL m64 r64 +// CVTSD2SL xmm r32 +// CVTSD2SL xmm r64 func CVTSD2SL(mx, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CVTSD2SL", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM64(mx) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CVTSD2SL", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsXMM(mx) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CVTSD2SL", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM64(mx) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CVTSD2SL", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("CVTSD2SL: bad operands") + return build(opcCVTSD2SL.Forms(), sffxs{}, []operand.Op{mx, r}) } // CVTSD2SS: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value. // // Forms: // -// CVTSD2SS xmm xmm // CVTSD2SS m64 xmm +// CVTSD2SS xmm xmm func CVTSD2SS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "CVTSD2SS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "CVTSD2SS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("CVTSD2SS: bad operands") + return build(opcCVTSD2SS.Forms(), sffxs{}, []operand.Op{mx, x}) } // CVTSL2SD: Convert Dword Integer to Scalar Double-Precision FP Value. // // Forms: // -// CVTSL2SD r32 xmm // CVTSL2SD m32 xmm +// CVTSL2SD r32 xmm func CVTSL2SD(mr, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "CVTSL2SD", - Operands: []operand.Op{mr, x}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM32(mr) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "CVTSL2SD", - Operands: []operand.Op{mr, x}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("CVTSL2SD: bad operands") + return build(opcCVTSL2SD.Forms(), sffxs{}, []operand.Op{mr, x}) } // CVTSL2SS: Convert Dword Integer to Scalar Single-Precision FP Value. // // Forms: // -// CVTSL2SS r32 xmm // CVTSL2SS m32 xmm +// CVTSL2SS r32 xmm func CVTSL2SS(mr, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "CVTSL2SS", - Operands: []operand.Op{mr, x}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM32(mr) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "CVTSL2SS", - Operands: []operand.Op{mr, x}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("CVTSL2SS: bad operands") + return build(opcCVTSL2SS.Forms(), sffxs{}, []operand.Op{mr, x}) } // CVTSQ2SD: Convert Dword Integer to Scalar Double-Precision FP Value. // // Forms: // -// CVTSQ2SD r64 xmm // CVTSQ2SD m64 xmm +// CVTSQ2SD r64 xmm func CVTSQ2SD(mr, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "CVTSQ2SD", - Operands: []operand.Op{mr, x}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM64(mr) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "CVTSQ2SD", - Operands: []operand.Op{mr, x}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("CVTSQ2SD: bad operands") + return build(opcCVTSQ2SD.Forms(), sffxs{}, []operand.Op{mr, x}) } // CVTSQ2SS: Convert Dword Integer to Scalar Single-Precision FP Value. // // Forms: // -// CVTSQ2SS r64 xmm // CVTSQ2SS m64 xmm +// CVTSQ2SS r64 xmm func CVTSQ2SS(mr, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "CVTSQ2SS", - Operands: []operand.Op{mr, x}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM64(mr) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "CVTSQ2SS", - Operands: []operand.Op{mr, x}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("CVTSQ2SS: bad operands") + return build(opcCVTSQ2SS.Forms(), sffxs{}, []operand.Op{mr, x}) } // CVTSS2SD: Convert Scalar Single-Precision FP Value to Scalar Double-Precision FP Value. // // Forms: // -// CVTSS2SD xmm xmm // CVTSS2SD m32 xmm +// CVTSS2SD xmm xmm func CVTSS2SD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "CVTSS2SD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "CVTSS2SD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("CVTSS2SD: bad operands") + return build(opcCVTSS2SD.Forms(), sffxs{}, []operand.Op{mx, x}) } // CVTSS2SL: Convert Scalar Single-Precision FP Value to Dword Integer. // // Forms: // -// CVTSS2SL xmm r32 // CVTSS2SL m32 r32 -// CVTSS2SL xmm r64 // CVTSS2SL m32 r64 +// CVTSS2SL xmm r32 +// CVTSS2SL xmm r64 func CVTSS2SL(mx, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CVTSS2SL", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM32(mx) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CVTSS2SL", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"SSE"}, - }, nil - case operand.IsXMM(mx) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CVTSS2SL", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM32(mx) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CVTSS2SL", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("CVTSS2SL: bad operands") + return build(opcCVTSS2SL.Forms(), sffxs{}, []operand.Op{mx, r}) } // CVTTPD2PL: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers. // // Forms: // -// CVTTPD2PL xmm xmm // CVTTPD2PL m128 xmm +// CVTTPD2PL xmm xmm func CVTTPD2PL(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "CVTTPD2PL", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "CVTTPD2PL", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("CVTTPD2PL: bad operands") + return build(opcCVTTPD2PL.Forms(), sffxs{}, []operand.Op{mx, x}) } // CVTTPS2PL: Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers. // // Forms: // -// CVTTPS2PL xmm xmm // CVTTPS2PL m128 xmm +// CVTTPS2PL xmm xmm func CVTTPS2PL(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "CVTTPS2PL", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "CVTTPS2PL", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("CVTTPS2PL: bad operands") + return build(opcCVTTPS2PL.Forms(), sffxs{}, []operand.Op{mx, x}) } // CVTTSD2SL: Convert with Truncation Scalar Double-Precision FP Value to Signed Integer. // // Forms: // -// CVTTSD2SL xmm r32 // CVTTSD2SL m64 r32 +// CVTTSD2SL xmm r32 func CVTTSD2SL(mx, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CVTTSD2SL", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM64(mx) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CVTTSD2SL", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("CVTTSD2SL: bad operands") + return build(opcCVTTSD2SL.Forms(), sffxs{}, []operand.Op{mx, r}) } // CVTTSD2SQ: Convert with Truncation Scalar Double-Precision FP Value to Signed Integer. // // Forms: // -// CVTTSD2SQ xmm r64 // CVTTSD2SQ m64 r64 +// CVTTSD2SQ xmm r64 func CVTTSD2SQ(mx, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CVTTSD2SQ", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM64(mx) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CVTTSD2SQ", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("CVTTSD2SQ: bad operands") + return build(opcCVTTSD2SQ.Forms(), sffxs{}, []operand.Op{mx, r}) } // CVTTSS2SL: Convert with Truncation Scalar Single-Precision FP Value to Dword Integer. // // Forms: // -// CVTTSS2SL xmm r32 // CVTTSS2SL m32 r32 -// CVTTSS2SL xmm r64 // CVTTSS2SL m32 r64 +// CVTTSS2SL xmm r32 +// CVTTSS2SL xmm r64 func CVTTSS2SL(mx, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CVTTSS2SL", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM32(mx) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "CVTTSS2SL", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"SSE"}, - }, nil - case operand.IsXMM(mx) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CVTTSS2SL", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM32(mx) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "CVTTSS2SL", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("CVTTSS2SL: bad operands") + return build(opcCVTTSS2SL.Forms(), sffxs{}, []operand.Op{mx, r}) } // CWD: Convert Word to Doubleword. @@ -5385,12 +1778,7 @@ func CVTTSS2SL(mx, r operand.Op) (*intrep.Instruction, error) { // // CWD func CWD() (*intrep.Instruction, error) { - return &intrep.Instruction{ - Opcode: "CWD", - Operands: nil, - Inputs: []operand.Op{reg.AX}, - Outputs: []operand.Op{reg.DX}, - }, nil + return build(opcCWD.Forms(), sffxs{}, []operand.Op{}) } // CWDE: Convert Word to Doubleword. @@ -5399,1042 +1787,369 @@ func CWD() (*intrep.Instruction, error) { // // CWDE func CWDE() (*intrep.Instruction, error) { - return &intrep.Instruction{ - Opcode: "CWDE", - Operands: nil, - Inputs: []operand.Op{reg.AX}, - Outputs: []operand.Op{reg.EAX}, - }, nil + return build(opcCWDE.Forms(), sffxs{}, []operand.Op{}) } // DECB: Decrement by 1. // // Forms: // -// DECB r8 // DECB m8 +// DECB r8 func DECB(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "DECB", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "DECB", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("DECB: bad operands") + return build(opcDECB.Forms(), sffxs{}, []operand.Op{mr}) } // DECL: Decrement by 1. // // Forms: // -// DECL r32 // DECL m32 +// DECL r32 func DECL(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "DECL", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "DECL", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("DECL: bad operands") + return build(opcDECL.Forms(), sffxs{}, []operand.Op{mr}) } // DECQ: Decrement by 1. // // Forms: // -// DECQ r64 // DECQ m64 +// DECQ r64 func DECQ(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "DECQ", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "DECQ", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("DECQ: bad operands") + return build(opcDECQ.Forms(), sffxs{}, []operand.Op{mr}) } // DECW: Decrement by 1. // // Forms: // -// DECW r16 // DECW m16 +// DECW r16 func DECW(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "DECW", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "DECW", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("DECW: bad operands") + return build(opcDECW.Forms(), sffxs{}, []operand.Op{mr}) } // DIVB: Unsigned Divide. // // Forms: // -// DIVB r8 // DIVB m8 +// DIVB r8 func DIVB(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "DIVB", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr, reg.AX}, - Outputs: []operand.Op{reg.AX}, - }, nil - case operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "DIVB", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr, reg.AX}, - Outputs: []operand.Op{reg.AX}, - }, nil - } - return nil, errors.New("DIVB: bad operands") + return build(opcDIVB.Forms(), sffxs{}, []operand.Op{mr}) } // DIVL: Unsigned Divide. // // Forms: // -// DIVL r32 // DIVL m32 +// DIVL r32 func DIVL(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "DIVL", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr, reg.EAX, reg.EDX}, - Outputs: []operand.Op{reg.EAX, reg.EDX}, - }, nil - case operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "DIVL", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr, reg.EAX, reg.EDX}, - Outputs: []operand.Op{reg.EAX, reg.EDX}, - }, nil - } - return nil, errors.New("DIVL: bad operands") + return build(opcDIVL.Forms(), sffxs{}, []operand.Op{mr}) } // DIVPD: Divide Packed Double-Precision Floating-Point Values. // // Forms: // -// DIVPD xmm xmm // DIVPD m128 xmm +// DIVPD xmm xmm func DIVPD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "DIVPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "DIVPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("DIVPD: bad operands") + return build(opcDIVPD.Forms(), sffxs{}, []operand.Op{mx, x}) } // DIVPS: Divide Packed Single-Precision Floating-Point Values. // // Forms: // -// DIVPS xmm xmm // DIVPS m128 xmm +// DIVPS xmm xmm func DIVPS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "DIVPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "DIVPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("DIVPS: bad operands") + return build(opcDIVPS.Forms(), sffxs{}, []operand.Op{mx, x}) } // DIVQ: Unsigned Divide. // // Forms: // -// DIVQ r64 // DIVQ m64 +// DIVQ r64 func DIVQ(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "DIVQ", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr, reg.RAX, reg.RDX}, - Outputs: []operand.Op{reg.RAX, reg.RDX}, - }, nil - case operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "DIVQ", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr, reg.RAX, reg.RDX}, - Outputs: []operand.Op{reg.RAX, reg.RDX}, - }, nil - } - return nil, errors.New("DIVQ: bad operands") + return build(opcDIVQ.Forms(), sffxs{}, []operand.Op{mr}) } // DIVSD: Divide Scalar Double-Precision Floating-Point Values. // // Forms: // -// DIVSD xmm xmm // DIVSD m64 xmm +// DIVSD xmm xmm func DIVSD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "DIVSD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "DIVSD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("DIVSD: bad operands") + return build(opcDIVSD.Forms(), sffxs{}, []operand.Op{mx, x}) } // DIVSS: Divide Scalar Single-Precision Floating-Point Values. // // Forms: // -// DIVSS xmm xmm // DIVSS m32 xmm +// DIVSS xmm xmm func DIVSS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "DIVSS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "DIVSS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("DIVSS: bad operands") + return build(opcDIVSS.Forms(), sffxs{}, []operand.Op{mx, x}) } // DIVW: Unsigned Divide. // // Forms: // -// DIVW r16 // DIVW m16 +// DIVW r16 func DIVW(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "DIVW", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr, reg.AX, reg.DX}, - Outputs: []operand.Op{reg.AX, reg.DX}, - }, nil - case operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "DIVW", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr, reg.AX, reg.DX}, - Outputs: []operand.Op{reg.AX, reg.DX}, - }, nil - } - return nil, errors.New("DIVW: bad operands") + return build(opcDIVW.Forms(), sffxs{}, []operand.Op{mr}) } // DPPD: Dot Product of Packed Double Precision Floating-Point Values. // // Forms: // -// DPPD imm8 xmm xmm // DPPD imm8 m128 xmm +// DPPD imm8 xmm xmm func DPPD(i, mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "DPPD", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "DPPD", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("DPPD: bad operands") + return build(opcDPPD.Forms(), sffxs{}, []operand.Op{i, mx, x}) } // DPPS: Dot Product of Packed Single Precision Floating-Point Values. // // Forms: // -// DPPS imm8 xmm xmm // DPPS imm8 m128 xmm +// DPPS imm8 xmm xmm func DPPS(i, mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "DPPS", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "DPPS", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("DPPS: bad operands") + return build(opcDPPS.Forms(), sffxs{}, []operand.Op{i, mx, x}) } // EXTRACTPS: Extract Packed Single Precision Floating-Point Value. // // Forms: // -// EXTRACTPS imm2u xmm r32 // EXTRACTPS imm2u xmm m32 +// EXTRACTPS imm2u xmm r32 func EXTRACTPS(i, x, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM2U(i) && operand.IsXMM(x) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "EXTRACTPS", - Operands: []operand.Op{i, x, mr}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{mr}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsIMM2U(i) && operand.IsXMM(x) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "EXTRACTPS", - Operands: []operand.Op{i, x, mr}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{mr}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("EXTRACTPS: bad operands") + return build(opcEXTRACTPS.Forms(), sffxs{}, []operand.Op{i, x, mr}) } // HADDPD: Packed Double-FP Horizontal Add. // // Forms: // -// HADDPD xmm xmm // HADDPD m128 xmm +// HADDPD xmm xmm func HADDPD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "HADDPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE3"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "HADDPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE3"}, - }, nil - } - return nil, errors.New("HADDPD: bad operands") + return build(opcHADDPD.Forms(), sffxs{}, []operand.Op{mx, x}) } // HADDPS: Packed Single-FP Horizontal Add. // // Forms: // -// HADDPS xmm xmm // HADDPS m128 xmm +// HADDPS xmm xmm func HADDPS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "HADDPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE3"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "HADDPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE3"}, - }, nil - } - return nil, errors.New("HADDPS: bad operands") + return build(opcHADDPS.Forms(), sffxs{}, []operand.Op{mx, x}) } // HSUBPD: Packed Double-FP Horizontal Subtract. // // Forms: // -// HSUBPD xmm xmm // HSUBPD m128 xmm +// HSUBPD xmm xmm func HSUBPD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "HSUBPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE3"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "HSUBPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE3"}, - }, nil - } - return nil, errors.New("HSUBPD: bad operands") + return build(opcHSUBPD.Forms(), sffxs{}, []operand.Op{mx, x}) } // HSUBPS: Packed Single-FP Horizontal Subtract. // // Forms: // -// HSUBPS xmm xmm // HSUBPS m128 xmm +// HSUBPS xmm xmm func HSUBPS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "HSUBPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE3"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "HSUBPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE3"}, - }, nil - } - return nil, errors.New("HSUBPS: bad operands") + return build(opcHSUBPS.Forms(), sffxs{}, []operand.Op{mx, x}) } // IDIVB: Signed Divide. // // Forms: // -// IDIVB r8 // IDIVB m8 +// IDIVB r8 func IDIVB(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "IDIVB", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr, reg.AX}, - Outputs: []operand.Op{reg.AX}, - }, nil - case operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "IDIVB", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr, reg.AX}, - Outputs: []operand.Op{reg.AX}, - }, nil - } - return nil, errors.New("IDIVB: bad operands") + return build(opcIDIVB.Forms(), sffxs{}, []operand.Op{mr}) } // IDIVL: Signed Divide. // // Forms: // -// IDIVL r32 // IDIVL m32 +// IDIVL r32 func IDIVL(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "IDIVL", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr, reg.EAX, reg.EDX}, - Outputs: []operand.Op{reg.EAX, reg.EDX}, - }, nil - case operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "IDIVL", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr, reg.EAX, reg.EDX}, - Outputs: []operand.Op{reg.EAX, reg.EDX}, - }, nil - } - return nil, errors.New("IDIVL: bad operands") + return build(opcIDIVL.Forms(), sffxs{}, []operand.Op{mr}) } // IDIVQ: Signed Divide. // // Forms: // -// IDIVQ r64 // IDIVQ m64 +// IDIVQ r64 func IDIVQ(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "IDIVQ", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr, reg.RAX, reg.RDX}, - Outputs: []operand.Op{reg.RAX, reg.RDX}, - }, nil - case operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "IDIVQ", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr, reg.RAX, reg.RDX}, - Outputs: []operand.Op{reg.RAX, reg.RDX}, - }, nil - } - return nil, errors.New("IDIVQ: bad operands") + return build(opcIDIVQ.Forms(), sffxs{}, []operand.Op{mr}) } // IDIVW: Signed Divide. // // Forms: // -// IDIVW r16 // IDIVW m16 +// IDIVW r16 func IDIVW(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "IDIVW", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr, reg.AX, reg.DX}, - Outputs: []operand.Op{reg.AX, reg.DX}, - }, nil - case operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "IDIVW", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr, reg.AX, reg.DX}, - Outputs: []operand.Op{reg.AX, reg.DX}, - }, nil - } - return nil, errors.New("IDIVW: bad operands") + return build(opcIDIVW.Forms(), sffxs{}, []operand.Op{mr}) } // IMUL3L: Signed Multiply. // // Forms: // -// IMUL3L imm8 r32 r32 +// IMUL3L imm32 m32 r32 // IMUL3L imm32 r32 r32 // IMUL3L imm8 m32 r32 -// IMUL3L imm32 m32 r32 +// IMUL3L imm8 r32 r32 func IMUL3L(i, mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsR32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "IMUL3L", - Operands: []operand.Op{i, mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - case operand.IsIMM32(i) && operand.IsR32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "IMUL3L", - Operands: []operand.Op{i, mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - case operand.IsIMM8(i) && operand.IsM32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "IMUL3L", - Operands: []operand.Op{i, mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - case operand.IsIMM32(i) && operand.IsM32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "IMUL3L", - Operands: []operand.Op{i, mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - } - return nil, errors.New("IMUL3L: bad operands") + return build(opcIMUL3L.Forms(), sffxs{}, []operand.Op{i, mr, r}) } // IMUL3Q: Signed Multiply. // // Forms: // -// IMUL3Q imm8 r64 r64 +// IMUL3Q imm32 m64 r64 // IMUL3Q imm32 r64 r64 // IMUL3Q imm8 m64 r64 -// IMUL3Q imm32 m64 r64 +// IMUL3Q imm8 r64 r64 func IMUL3Q(i, mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsR64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "IMUL3Q", - Operands: []operand.Op{i, mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - case operand.IsIMM32(i) && operand.IsR64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "IMUL3Q", - Operands: []operand.Op{i, mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - case operand.IsIMM8(i) && operand.IsM64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "IMUL3Q", - Operands: []operand.Op{i, mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - case operand.IsIMM32(i) && operand.IsM64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "IMUL3Q", - Operands: []operand.Op{i, mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - } - return nil, errors.New("IMUL3Q: bad operands") + return build(opcIMUL3Q.Forms(), sffxs{}, []operand.Op{i, mr, r}) } // IMUL3W: Signed Multiply. // // Forms: // -// IMUL3W imm8 r16 r16 +// IMUL3W imm16 m16 r16 // IMUL3W imm16 r16 r16 // IMUL3W imm8 m16 r16 -// IMUL3W imm16 m16 r16 +// IMUL3W imm8 r16 r16 func IMUL3W(i, mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsR16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "IMUL3W", - Operands: []operand.Op{i, mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - case operand.IsIMM16(i) && operand.IsR16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "IMUL3W", - Operands: []operand.Op{i, mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - case operand.IsIMM8(i) && operand.IsM16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "IMUL3W", - Operands: []operand.Op{i, mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - case operand.IsIMM16(i) && operand.IsM16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "IMUL3W", - Operands: []operand.Op{i, mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - } - return nil, errors.New("IMUL3W: bad operands") + return build(opcIMUL3W.Forms(), sffxs{}, []operand.Op{i, mr, r}) } // IMULB: Signed Multiply. // // Forms: // -// IMULB r8 // IMULB m8 +// IMULB r8 func IMULB(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "IMULB", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr, reg.AL}, - Outputs: []operand.Op{reg.AX}, - }, nil - case operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "IMULB", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr, reg.AL}, - Outputs: []operand.Op{reg.AX}, - }, nil - } - return nil, errors.New("IMULB: bad operands") + return build(opcIMULB.Forms(), sffxs{}, []operand.Op{mr}) } // IMULL: Signed Multiply. // // Forms: // -// IMULL r32 +// IMULL m32 r32 // IMULL m32 // IMULL r32 r32 -// IMULL m32 r32 +// IMULL r32 func IMULL(ops ...operand.Op) (*intrep.Instruction, error) { - switch { - case len(ops) == 1 && operand.IsR32(ops[0]): - return &intrep.Instruction{ - Opcode: "IMULL", - Operands: ops, - Inputs: []operand.Op{ops[0], reg.EAX}, - Outputs: []operand.Op{reg.EAX, reg.EDX}, - }, nil - case len(ops) == 1 && operand.IsM32(ops[0]): - return &intrep.Instruction{ - Opcode: "IMULL", - Operands: ops, - Inputs: []operand.Op{ops[0], reg.EAX}, - Outputs: []operand.Op{reg.EAX, reg.EDX}, - }, nil - case len(ops) == 2 && operand.IsR32(ops[0]) && operand.IsR32(ops[1]): - return &intrep.Instruction{ - Opcode: "IMULL", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.IsM32(ops[0]) && operand.IsR32(ops[1]): - return &intrep.Instruction{ - Opcode: "IMULL", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - } - return nil, errors.New("IMULL: bad operands") + return build(opcIMULL.Forms(), sffxs{}, ops) } // IMULQ: Signed Multiply. // // Forms: // -// IMULQ r64 +// IMULQ m64 r64 // IMULQ m64 // IMULQ r64 r64 -// IMULQ m64 r64 +// IMULQ r64 func IMULQ(ops ...operand.Op) (*intrep.Instruction, error) { - switch { - case len(ops) == 1 && operand.IsR64(ops[0]): - return &intrep.Instruction{ - Opcode: "IMULQ", - Operands: ops, - Inputs: []operand.Op{ops[0], reg.RAX}, - Outputs: []operand.Op{reg.RAX, reg.RDX}, - }, nil - case len(ops) == 1 && operand.IsM64(ops[0]): - return &intrep.Instruction{ - Opcode: "IMULQ", - Operands: ops, - Inputs: []operand.Op{ops[0], reg.RAX}, - Outputs: []operand.Op{reg.RAX, reg.RDX}, - }, nil - case len(ops) == 2 && operand.IsR64(ops[0]) && operand.IsR64(ops[1]): - return &intrep.Instruction{ - Opcode: "IMULQ", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.IsM64(ops[0]) && operand.IsR64(ops[1]): - return &intrep.Instruction{ - Opcode: "IMULQ", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - } - return nil, errors.New("IMULQ: bad operands") + return build(opcIMULQ.Forms(), sffxs{}, ops) } // IMULW: Signed Multiply. // // Forms: // -// IMULW r16 +// IMULW m16 r16 // IMULW m16 // IMULW r16 r16 -// IMULW m16 r16 +// IMULW r16 func IMULW(ops ...operand.Op) (*intrep.Instruction, error) { - switch { - case len(ops) == 1 && operand.IsR16(ops[0]): - return &intrep.Instruction{ - Opcode: "IMULW", - Operands: ops, - Inputs: []operand.Op{ops[0], reg.AX}, - Outputs: []operand.Op{reg.AX, reg.DX}, - }, nil - case len(ops) == 1 && operand.IsM16(ops[0]): - return &intrep.Instruction{ - Opcode: "IMULW", - Operands: ops, - Inputs: []operand.Op{ops[0], reg.AX}, - Outputs: []operand.Op{reg.AX, reg.DX}, - }, nil - case len(ops) == 2 && operand.IsR16(ops[0]) && operand.IsR16(ops[1]): - return &intrep.Instruction{ - Opcode: "IMULW", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.IsM16(ops[0]) && operand.IsR16(ops[1]): - return &intrep.Instruction{ - Opcode: "IMULW", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - } - return nil, errors.New("IMULW: bad operands") + return build(opcIMULW.Forms(), sffxs{}, ops) } // INCB: Increment by 1. // // Forms: // -// INCB r8 // INCB m8 +// INCB r8 func INCB(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "INCB", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "INCB", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("INCB: bad operands") + return build(opcINCB.Forms(), sffxs{}, []operand.Op{mr}) } // INCL: Increment by 1. // // Forms: // -// INCL r32 // INCL m32 +// INCL r32 func INCL(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "INCL", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "INCL", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("INCL: bad operands") + return build(opcINCL.Forms(), sffxs{}, []operand.Op{mr}) } // INCQ: Increment by 1. // // Forms: // -// INCQ r64 // INCQ m64 +// INCQ r64 func INCQ(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "INCQ", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "INCQ", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("INCQ: bad operands") + return build(opcINCQ.Forms(), sffxs{}, []operand.Op{mr}) } // INCW: Increment by 1. // // Forms: // -// INCW r16 // INCW m16 +// INCW r16 func INCW(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "INCW", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "INCW", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("INCW: bad operands") + return build(opcINCW.Forms(), sffxs{}, []operand.Op{mr}) } // INSERTPS: Insert Packed Single Precision Floating-Point Value. // // Forms: // -// INSERTPS imm8 xmm xmm // INSERTPS imm8 m32 xmm +// INSERTPS imm8 xmm xmm func INSERTPS(i, mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "INSERTPS", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsIMM8(i) && operand.IsM32(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "INSERTPS", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("INSERTPS: bad operands") + return build(opcINSERTPS.Forms(), sffxs{}, []operand.Op{i, mx, x}) } // INT: Call to Interrupt Procedure. @@ -6444,233 +2159,77 @@ func INSERTPS(i, mx, x operand.Op) (*intrep.Instruction, error) { // INT 3 // INT imm8 func INT(i operand.Op) (*intrep.Instruction, error) { - switch { - case operand.Is3(i): - return &intrep.Instruction{ - Opcode: "INT", - Operands: []operand.Op{i}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - }, nil - case operand.IsIMM8(i): - return &intrep.Instruction{ - Opcode: "INT", - Operands: []operand.Op{i}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - }, nil - } - return nil, errors.New("INT: bad operands") + return build(opcINT.Forms(), sffxs{}, []operand.Op{i}) } // JA: Jump if above (CF == 0 and ZF == 0). // // Forms: // -// JA rel8 // JA rel32 +// JA rel8 func JA(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JA", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JA", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JA: bad operands") + return build(opcJA.Forms(), sffxs{}, []operand.Op{r}) } // JAE: Jump if above or equal (CF == 0). // // Forms: // -// JAE rel8 // JAE rel32 +// JAE rel8 func JAE(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JAE", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JAE", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JAE: bad operands") + return build(opcJAE.Forms(), sffxs{}, []operand.Op{r}) } // JB: Jump if below (CF == 1). // // Forms: // -// JB rel8 // JB rel32 +// JB rel8 func JB(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JB", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JB", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JB: bad operands") + return build(opcJB.Forms(), sffxs{}, []operand.Op{r}) } // JBE: Jump if below or equal (CF == 1 or ZF == 1). // // Forms: // -// JBE rel8 // JBE rel32 +// JBE rel8 func JBE(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JBE", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JBE", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JBE: bad operands") + return build(opcJBE.Forms(), sffxs{}, []operand.Op{r}) } // JC: Jump if below (CF == 1). // // Forms: // -// JC rel8 // JC rel32 +// JC rel8 func JC(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JC", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JC", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JC: bad operands") + return build(opcJC.Forms(), sffxs{}, []operand.Op{r}) } // JCC: Jump if above or equal (CF == 0). // // Forms: // -// JCC rel8 // JCC rel32 +// JCC rel8 func JCC(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JCC", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JCC", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JCC: bad operands") + return build(opcJCC.Forms(), sffxs{}, []operand.Op{r}) } // JCS: Jump if below (CF == 1). // // Forms: // -// JCS rel8 // JCS rel32 +// JCS rel8 func JCS(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JCS", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JCS", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JCS: bad operands") + return build(opcJCS.Forms(), sffxs{}, []operand.Op{r}) } // JCXZL: Jump if ECX register is 0. @@ -6679,18 +2238,7 @@ func JCS(r operand.Op) (*intrep.Instruction, error) { // // JCXZL rel8 func JCXZL(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JCXZL", - Operands: []operand.Op{r}, - Inputs: []operand.Op{reg.ECX}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JCXZL: bad operands") + return build(opcJCXZL.Forms(), sffxs{}, []operand.Op{r}) } // JCXZQ: Jump if RCX register is 0. @@ -6699,27245 +2247,34893 @@ func JCXZL(r operand.Op) (*intrep.Instruction, error) { // // JCXZQ rel8 func JCXZQ(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JCXZQ", - Operands: []operand.Op{r}, - Inputs: []operand.Op{reg.RCX}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JCXZQ: bad operands") + return build(opcJCXZQ.Forms(), sffxs{}, []operand.Op{r}) } // JE: Jump if equal (ZF == 1). // // Forms: // -// JE rel8 // JE rel32 +// JE rel8 func JE(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JE", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JE", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JE: bad operands") + return build(opcJE.Forms(), sffxs{}, []operand.Op{r}) } // JEQ: Jump if equal (ZF == 1). // // Forms: // -// JEQ rel8 // JEQ rel32 +// JEQ rel8 func JEQ(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JEQ", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JEQ", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JEQ: bad operands") + return build(opcJEQ.Forms(), sffxs{}, []operand.Op{r}) } // JG: Jump if greater (ZF == 0 and SF == OF). // // Forms: // -// JG rel8 // JG rel32 +// JG rel8 func JG(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JG", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JG", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JG: bad operands") + return build(opcJG.Forms(), sffxs{}, []operand.Op{r}) } // JGE: Jump if greater or equal (SF == OF). // // Forms: // -// JGE rel8 // JGE rel32 +// JGE rel8 func JGE(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JGE", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JGE", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JGE: bad operands") + return build(opcJGE.Forms(), sffxs{}, []operand.Op{r}) } // JGT: Jump if greater (ZF == 0 and SF == OF). // // Forms: // -// JGT rel8 // JGT rel32 +// JGT rel8 func JGT(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JGT", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JGT", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JGT: bad operands") + return build(opcJGT.Forms(), sffxs{}, []operand.Op{r}) } // JHI: Jump if above (CF == 0 and ZF == 0). // // Forms: // -// JHI rel8 // JHI rel32 +// JHI rel8 func JHI(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JHI", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JHI", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JHI: bad operands") + return build(opcJHI.Forms(), sffxs{}, []operand.Op{r}) } // JHS: Jump if above or equal (CF == 0). // // Forms: // -// JHS rel8 // JHS rel32 +// JHS rel8 func JHS(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JHS", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JHS", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JHS: bad operands") + return build(opcJHS.Forms(), sffxs{}, []operand.Op{r}) } // JL: Jump if less (SF != OF). // // Forms: // -// JL rel8 // JL rel32 +// JL rel8 func JL(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JL", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JL", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JL: bad operands") + return build(opcJL.Forms(), sffxs{}, []operand.Op{r}) } // JLE: Jump if less or equal (ZF == 1 or SF != OF). // // Forms: // -// JLE rel8 // JLE rel32 +// JLE rel8 func JLE(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JLE", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JLE", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JLE: bad operands") + return build(opcJLE.Forms(), sffxs{}, []operand.Op{r}) } // JLO: Jump if below (CF == 1). // // Forms: // -// JLO rel8 // JLO rel32 +// JLO rel8 func JLO(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JLO", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JLO", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JLO: bad operands") + return build(opcJLO.Forms(), sffxs{}, []operand.Op{r}) } // JLS: Jump if below or equal (CF == 1 or ZF == 1). // // Forms: // -// JLS rel8 // JLS rel32 +// JLS rel8 func JLS(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JLS", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JLS", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JLS: bad operands") + return build(opcJLS.Forms(), sffxs{}, []operand.Op{r}) } // JLT: Jump if less (SF != OF). // // Forms: // -// JLT rel8 // JLT rel32 +// JLT rel8 func JLT(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JLT", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JLT", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JLT: bad operands") + return build(opcJLT.Forms(), sffxs{}, []operand.Op{r}) } // JMI: Jump if sign (SF == 1). // // Forms: // -// JMI rel8 // JMI rel32 +// JMI rel8 func JMI(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JMI", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JMI", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JMI: bad operands") + return build(opcJMI.Forms(), sffxs{}, []operand.Op{r}) } // JMP: Jump Unconditionally. // // Forms: // -// JMP rel8 // JMP rel32 -// JMP r64 +// JMP rel8 // JMP m64 +// JMP r64 func JMP(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(mr): - return &intrep.Instruction{ - Opcode: "JMP", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: false, - }, nil - case operand.IsREL32(mr): - return &intrep.Instruction{ - Opcode: "JMP", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: false, - }, nil - case operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "JMP", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: false, - }, nil - case operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "JMP", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: false, - }, nil - } - return nil, errors.New("JMP: bad operands") + return build(opcJMP.Forms(), sffxs{}, []operand.Op{mr}) } // JNA: Jump if below or equal (CF == 1 or ZF == 1). // // Forms: // -// JNA rel8 // JNA rel32 +// JNA rel8 func JNA(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JNA", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JNA", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JNA: bad operands") + return build(opcJNA.Forms(), sffxs{}, []operand.Op{r}) } // JNAE: Jump if below (CF == 1). // // Forms: // -// JNAE rel8 // JNAE rel32 +// JNAE rel8 func JNAE(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JNAE", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JNAE", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JNAE: bad operands") + return build(opcJNAE.Forms(), sffxs{}, []operand.Op{r}) } // JNB: Jump if above or equal (CF == 0). // // Forms: // -// JNB rel8 // JNB rel32 +// JNB rel8 func JNB(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JNB", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JNB", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JNB: bad operands") + return build(opcJNB.Forms(), sffxs{}, []operand.Op{r}) } // JNBE: Jump if above (CF == 0 and ZF == 0). // // Forms: // -// JNBE rel8 // JNBE rel32 +// JNBE rel8 func JNBE(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JNBE", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JNBE", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JNBE: bad operands") + return build(opcJNBE.Forms(), sffxs{}, []operand.Op{r}) } // JNC: Jump if above or equal (CF == 0). // // Forms: // -// JNC rel8 // JNC rel32 +// JNC rel8 func JNC(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JNC", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JNC", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JNC: bad operands") + return build(opcJNC.Forms(), sffxs{}, []operand.Op{r}) } // JNE: Jump if not equal (ZF == 0). // // Forms: // -// JNE rel8 // JNE rel32 +// JNE rel8 func JNE(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JNE", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JNE", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JNE: bad operands") + return build(opcJNE.Forms(), sffxs{}, []operand.Op{r}) } // JNG: Jump if less or equal (ZF == 1 or SF != OF). // // Forms: // -// JNG rel8 // JNG rel32 +// JNG rel8 func JNG(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JNG", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JNG", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JNG: bad operands") + return build(opcJNG.Forms(), sffxs{}, []operand.Op{r}) } // JNGE: Jump if less (SF != OF). // // Forms: // -// JNGE rel8 // JNGE rel32 +// JNGE rel8 func JNGE(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JNGE", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JNGE", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JNGE: bad operands") + return build(opcJNGE.Forms(), sffxs{}, []operand.Op{r}) } // JNL: Jump if greater or equal (SF == OF). // // Forms: // -// JNL rel8 // JNL rel32 +// JNL rel8 func JNL(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JNL", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JNL", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JNL: bad operands") + return build(opcJNL.Forms(), sffxs{}, []operand.Op{r}) } // JNLE: Jump if greater (ZF == 0 and SF == OF). // // Forms: // -// JNLE rel8 // JNLE rel32 +// JNLE rel8 func JNLE(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JNLE", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JNLE", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JNLE: bad operands") + return build(opcJNLE.Forms(), sffxs{}, []operand.Op{r}) } // JNO: Jump if not overflow (OF == 0). // // Forms: // -// JNO rel8 // JNO rel32 +// JNO rel8 func JNO(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JNO", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JNO", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JNO: bad operands") + return build(opcJNO.Forms(), sffxs{}, []operand.Op{r}) } // JNP: Jump if not parity (PF == 0). // // Forms: // -// JNP rel8 // JNP rel32 +// JNP rel8 func JNP(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JNP", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JNP", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JNP: bad operands") + return build(opcJNP.Forms(), sffxs{}, []operand.Op{r}) } // JNS: Jump if not sign (SF == 0). // // Forms: // -// JNS rel8 // JNS rel32 +// JNS rel8 func JNS(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JNS", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JNS", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JNS: bad operands") + return build(opcJNS.Forms(), sffxs{}, []operand.Op{r}) } // JNZ: Jump if not equal (ZF == 0). // // Forms: // -// JNZ rel8 // JNZ rel32 +// JNZ rel8 func JNZ(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JNZ", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JNZ", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JNZ: bad operands") + return build(opcJNZ.Forms(), sffxs{}, []operand.Op{r}) } // JO: Jump if overflow (OF == 1). // // Forms: // -// JO rel8 // JO rel32 +// JO rel8 func JO(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JO", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JO", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JO: bad operands") + return build(opcJO.Forms(), sffxs{}, []operand.Op{r}) } // JOC: Jump if not overflow (OF == 0). // // Forms: // -// JOC rel8 // JOC rel32 +// JOC rel8 func JOC(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JOC", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JOC", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JOC: bad operands") + return build(opcJOC.Forms(), sffxs{}, []operand.Op{r}) } // JOS: Jump if overflow (OF == 1). // // Forms: // -// JOS rel8 // JOS rel32 +// JOS rel8 func JOS(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JOS", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JOS", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JOS: bad operands") + return build(opcJOS.Forms(), sffxs{}, []operand.Op{r}) } // JP: Jump if parity (PF == 1). // // Forms: // -// JP rel8 // JP rel32 +// JP rel8 func JP(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JP", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JP", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JP: bad operands") + return build(opcJP.Forms(), sffxs{}, []operand.Op{r}) } // JPC: Jump if not parity (PF == 0). // // Forms: // -// JPC rel8 // JPC rel32 +// JPC rel8 func JPC(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JPC", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JPC", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JPC: bad operands") + return build(opcJPC.Forms(), sffxs{}, []operand.Op{r}) } // JPE: Jump if parity (PF == 1). // // Forms: // -// JPE rel8 // JPE rel32 +// JPE rel8 func JPE(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JPE", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JPE", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JPE: bad operands") + return build(opcJPE.Forms(), sffxs{}, []operand.Op{r}) } // JPL: Jump if not sign (SF == 0). // // Forms: // -// JPL rel8 // JPL rel32 +// JPL rel8 func JPL(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JPL", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JPL", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JPL: bad operands") + return build(opcJPL.Forms(), sffxs{}, []operand.Op{r}) } // JPO: Jump if not parity (PF == 0). // // Forms: // -// JPO rel8 // JPO rel32 +// JPO rel8 func JPO(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JPO", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JPO", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JPO: bad operands") + return build(opcJPO.Forms(), sffxs{}, []operand.Op{r}) } // JPS: Jump if parity (PF == 1). // // Forms: // -// JPS rel8 // JPS rel32 +// JPS rel8 func JPS(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JPS", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JPS", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JPS: bad operands") + return build(opcJPS.Forms(), sffxs{}, []operand.Op{r}) } // JS: Jump if sign (SF == 1). // // Forms: // -// JS rel8 // JS rel32 +// JS rel8 func JS(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JS", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JS", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JS: bad operands") + return build(opcJS.Forms(), sffxs{}, []operand.Op{r}) } // JZ: Jump if equal (ZF == 1). // // Forms: // -// JZ rel8 // JZ rel32 +// JZ rel8 func JZ(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsREL8(r): - return &intrep.Instruction{ - Opcode: "JZ", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - case operand.IsREL32(r): - return &intrep.Instruction{ - Opcode: "JZ", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsBranch: true, - IsConditional: true, - }, nil - } - return nil, errors.New("JZ: bad operands") + return build(opcJZ.Forms(), sffxs{}, []operand.Op{r}) } -// LDDQU: Load Unaligned Integer 128 Bits. +// KADDB: ADD Two 8-bit Masks. // // Forms: // -// LDDQU m128 xmm -func LDDQU(m, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM128(m) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "LDDQU", - Operands: []operand.Op{m, x}, - Inputs: []operand.Op{m}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE3"}, - }, nil - } - return nil, errors.New("LDDQU: bad operands") +// KADDB k k k +func KADDB(k, k1, k2 operand.Op) (*intrep.Instruction, error) { + return build(opcKADDB.Forms(), sffxs{}, []operand.Op{k, k1, k2}) } -// LDMXCSR: Load MXCSR Register. +// KADDD: ADD Two 32-bit Masks. // // Forms: // -// LDMXCSR m32 -func LDMXCSR(m operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM32(m): - return &intrep.Instruction{ - Opcode: "LDMXCSR", - Operands: []operand.Op{m}, - Inputs: []operand.Op{m}, - Outputs: []operand.Op{}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("LDMXCSR: bad operands") +// KADDD k k k +func KADDD(k, k1, k2 operand.Op) (*intrep.Instruction, error) { + return build(opcKADDD.Forms(), sffxs{}, []operand.Op{k, k1, k2}) } -// LEAL: Load Effective Address. +// KADDQ: ADD Two 64-bit Masks. // // Forms: // -// LEAL m r32 -func LEAL(m, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM(m) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "LEAL", - Operands: []operand.Op{m, r}, - Inputs: []operand.Op{m}, - Outputs: []operand.Op{r}, - }, nil - } - return nil, errors.New("LEAL: bad operands") +// KADDQ k k k +func KADDQ(k, k1, k2 operand.Op) (*intrep.Instruction, error) { + return build(opcKADDQ.Forms(), sffxs{}, []operand.Op{k, k1, k2}) } -// LEAQ: Load Effective Address. +// KADDW: ADD Two 16-bit Masks. // // Forms: // -// LEAQ m r64 -func LEAQ(m, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM(m) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "LEAQ", - Operands: []operand.Op{m, r}, - Inputs: []operand.Op{m}, - Outputs: []operand.Op{r}, - }, nil - } - return nil, errors.New("LEAQ: bad operands") +// KADDW k k k +func KADDW(k, k1, k2 operand.Op) (*intrep.Instruction, error) { + return build(opcKADDW.Forms(), sffxs{}, []operand.Op{k, k1, k2}) } -// LEAW: Load Effective Address. +// KANDB: Bitwise Logical AND 8-bit Masks. // // Forms: // -// LEAW m r16 -func LEAW(m, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM(m) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "LEAW", - Operands: []operand.Op{m, r}, - Inputs: []operand.Op{m}, - Outputs: []operand.Op{r}, - }, nil - } - return nil, errors.New("LEAW: bad operands") +// KANDB k k k +func KANDB(k, k1, k2 operand.Op) (*intrep.Instruction, error) { + return build(opcKANDB.Forms(), sffxs{}, []operand.Op{k, k1, k2}) } -// LFENCE: Load Fence. +// KANDD: Bitwise Logical AND 32-bit Masks. // // Forms: // -// LFENCE -func LFENCE() (*intrep.Instruction, error) { - return &intrep.Instruction{ - Opcode: "LFENCE", - Operands: nil, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - ISA: []string{"SSE2"}, - }, nil +// KANDD k k k +func KANDD(k, k1, k2 operand.Op) (*intrep.Instruction, error) { + return build(opcKANDD.Forms(), sffxs{}, []operand.Op{k, k1, k2}) } -// LZCNTL: Count the Number of Leading Zero Bits. +// KANDNB: Bitwise Logical AND NOT 8-bit Masks. // // Forms: // -// LZCNTL r32 r32 -// LZCNTL m32 r32 -func LZCNTL(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "LZCNTL", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"LZCNT"}, - }, nil - case operand.IsM32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "LZCNTL", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"LZCNT"}, - }, nil - } - return nil, errors.New("LZCNTL: bad operands") +// KANDNB k k k +func KANDNB(k, k1, k2 operand.Op) (*intrep.Instruction, error) { + return build(opcKANDNB.Forms(), sffxs{}, []operand.Op{k, k1, k2}) } -// LZCNTQ: Count the Number of Leading Zero Bits. +// KANDND: Bitwise Logical AND NOT 32-bit Masks. // // Forms: // -// LZCNTQ r64 r64 -// LZCNTQ m64 r64 -func LZCNTQ(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "LZCNTQ", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"LZCNT"}, - }, nil - case operand.IsM64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "LZCNTQ", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"LZCNT"}, - }, nil - } - return nil, errors.New("LZCNTQ: bad operands") +// KANDND k k k +func KANDND(k, k1, k2 operand.Op) (*intrep.Instruction, error) { + return build(opcKANDND.Forms(), sffxs{}, []operand.Op{k, k1, k2}) } -// LZCNTW: Count the Number of Leading Zero Bits. +// KANDNQ: Bitwise Logical AND NOT 64-bit Masks. // // Forms: // -// LZCNTW r16 r16 -// LZCNTW m16 r16 -func LZCNTW(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "LZCNTW", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"LZCNT"}, - }, nil - case operand.IsM16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "LZCNTW", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"LZCNT"}, - }, nil - } - return nil, errors.New("LZCNTW: bad operands") +// KANDNQ k k k +func KANDNQ(k, k1, k2 operand.Op) (*intrep.Instruction, error) { + return build(opcKANDNQ.Forms(), sffxs{}, []operand.Op{k, k1, k2}) } -// MASKMOVDQU: Store Selected Bytes of Double Quadword. +// KANDNW: Bitwise Logical AND NOT 16-bit Masks. // // Forms: // -// MASKMOVDQU xmm xmm -func MASKMOVDQU(x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "MASKMOVDQU", - Operands: []operand.Op{x, x1}, - Inputs: []operand.Op{x, x1, reg.RDI}, - Outputs: []operand.Op{}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("MASKMOVDQU: bad operands") +// KANDNW k k k +func KANDNW(k, k1, k2 operand.Op) (*intrep.Instruction, error) { + return build(opcKANDNW.Forms(), sffxs{}, []operand.Op{k, k1, k2}) } -// MASKMOVOU: Store Selected Bytes of Double Quadword. +// KANDQ: Bitwise Logical AND 64-bit Masks. // // Forms: // -// MASKMOVOU xmm xmm -func MASKMOVOU(x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "MASKMOVOU", - Operands: []operand.Op{x, x1}, - Inputs: []operand.Op{x, x1, reg.RDI}, - Outputs: []operand.Op{}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("MASKMOVOU: bad operands") +// KANDQ k k k +func KANDQ(k, k1, k2 operand.Op) (*intrep.Instruction, error) { + return build(opcKANDQ.Forms(), sffxs{}, []operand.Op{k, k1, k2}) } -// MAXPD: Return Maximum Packed Double-Precision Floating-Point Values. +// KANDW: Bitwise Logical AND 16-bit Masks. // // Forms: // -// MAXPD xmm xmm -// MAXPD m128 xmm -func MAXPD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MAXPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MAXPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("MAXPD: bad operands") +// KANDW k k k +func KANDW(k, k1, k2 operand.Op) (*intrep.Instruction, error) { + return build(opcKANDW.Forms(), sffxs{}, []operand.Op{k, k1, k2}) } -// MAXPS: Return Maximum Packed Single-Precision Floating-Point Values. +// KMOVB: Move 8-bit Mask. // // Forms: // -// MAXPS xmm xmm -// MAXPS m128 xmm -func MAXPS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MAXPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MAXPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("MAXPS: bad operands") +// KMOVB k k +// KMOVB k m8 +// KMOVB k r32 +// KMOVB m8 k +// KMOVB r32 k +func KMOVB(kmr, kmr1 operand.Op) (*intrep.Instruction, error) { + return build(opcKMOVB.Forms(), sffxs{}, []operand.Op{kmr, kmr1}) } -// MAXSD: Return Maximum Scalar Double-Precision Floating-Point Value. +// KMOVD: Move 32-bit Mask. // // Forms: // -// MAXSD xmm xmm -// MAXSD m64 xmm -func MAXSD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MAXSD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MAXSD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("MAXSD: bad operands") +// KMOVD k k +// KMOVD k m32 +// KMOVD k r32 +// KMOVD m32 k +// KMOVD r32 k +func KMOVD(kmr, kmr1 operand.Op) (*intrep.Instruction, error) { + return build(opcKMOVD.Forms(), sffxs{}, []operand.Op{kmr, kmr1}) } -// MAXSS: Return Maximum Scalar Single-Precision Floating-Point Value. +// KMOVQ: Move 64-bit Mask. // // Forms: // -// MAXSS xmm xmm -// MAXSS m32 xmm -func MAXSS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MAXSS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MAXSS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("MAXSS: bad operands") +// KMOVQ k k +// KMOVQ k m64 +// KMOVQ k r64 +// KMOVQ m64 k +// KMOVQ r64 k +func KMOVQ(kmr, kmr1 operand.Op) (*intrep.Instruction, error) { + return build(opcKMOVQ.Forms(), sffxs{}, []operand.Op{kmr, kmr1}) } -// MFENCE: Memory Fence. +// KMOVW: Move 16-bit Mask. // // Forms: // -// MFENCE -func MFENCE() (*intrep.Instruction, error) { - return &intrep.Instruction{ - Opcode: "MFENCE", - Operands: nil, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - ISA: []string{"SSE2"}, - }, nil +// KMOVW k k +// KMOVW k m16 +// KMOVW k r32 +// KMOVW m16 k +// KMOVW r32 k +func KMOVW(kmr, kmr1 operand.Op) (*intrep.Instruction, error) { + return build(opcKMOVW.Forms(), sffxs{}, []operand.Op{kmr, kmr1}) } -// MINPD: Return Minimum Packed Double-Precision Floating-Point Values. +// KNOTB: NOT 8-bit Mask Register. // // Forms: // -// MINPD xmm xmm -// MINPD m128 xmm -func MINPD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MINPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MINPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("MINPD: bad operands") +// KNOTB k k +func KNOTB(k, k1 operand.Op) (*intrep.Instruction, error) { + return build(opcKNOTB.Forms(), sffxs{}, []operand.Op{k, k1}) } -// MINPS: Return Minimum Packed Single-Precision Floating-Point Values. +// KNOTD: NOT 32-bit Mask Register. // // Forms: // -// MINPS xmm xmm -// MINPS m128 xmm -func MINPS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MINPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MINPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("MINPS: bad operands") +// KNOTD k k +func KNOTD(k, k1 operand.Op) (*intrep.Instruction, error) { + return build(opcKNOTD.Forms(), sffxs{}, []operand.Op{k, k1}) } -// MINSD: Return Minimum Scalar Double-Precision Floating-Point Value. +// KNOTQ: NOT 64-bit Mask Register. // // Forms: // -// MINSD xmm xmm -// MINSD m64 xmm -func MINSD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MINSD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MINSD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("MINSD: bad operands") +// KNOTQ k k +func KNOTQ(k, k1 operand.Op) (*intrep.Instruction, error) { + return build(opcKNOTQ.Forms(), sffxs{}, []operand.Op{k, k1}) } -// MINSS: Return Minimum Scalar Single-Precision Floating-Point Value. +// KNOTW: NOT 16-bit Mask Register. // // Forms: // -// MINSS xmm xmm -// MINSS m32 xmm -func MINSS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MINSS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MINSS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("MINSS: bad operands") +// KNOTW k k +func KNOTW(k, k1 operand.Op) (*intrep.Instruction, error) { + return build(opcKNOTW.Forms(), sffxs{}, []operand.Op{k, k1}) } -// MONITOR: Monitor a Linear Address Range. +// KORB: Bitwise Logical OR 8-bit Masks. // // Forms: // -// MONITOR -func MONITOR() (*intrep.Instruction, error) { - return &intrep.Instruction{ - Opcode: "MONITOR", - Operands: nil, - Inputs: []operand.Op{reg.RAX, reg.ECX, reg.EDX}, - Outputs: []operand.Op{}, - ISA: []string{"MONITOR"}, - }, nil +// KORB k k k +func KORB(k, k1, k2 operand.Op) (*intrep.Instruction, error) { + return build(opcKORB.Forms(), sffxs{}, []operand.Op{k, k1, k2}) } -// MOVAPD: Move Aligned Packed Double-Precision Floating-Point Values. +// KORD: Bitwise Logical OR 32-bit Masks. // // Forms: // -// MOVAPD xmm xmm -// MOVAPD m128 xmm -// MOVAPD xmm m128 -func MOVAPD(mx, mx1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(mx1): - return &intrep.Instruction{ - Opcode: "MOVAPD", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(mx1): - return &intrep.Instruction{ - Opcode: "MOVAPD", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsXMM(mx) && operand.IsM128(mx1): - return &intrep.Instruction{ - Opcode: "MOVAPD", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("MOVAPD: bad operands") +// KORD k k k +func KORD(k, k1, k2 operand.Op) (*intrep.Instruction, error) { + return build(opcKORD.Forms(), sffxs{}, []operand.Op{k, k1, k2}) } -// MOVAPS: Move Aligned Packed Single-Precision Floating-Point Values. +// KORQ: Bitwise Logical OR 64-bit Masks. // // Forms: // -// MOVAPS xmm xmm -// MOVAPS m128 xmm -// MOVAPS xmm m128 -func MOVAPS(mx, mx1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(mx1): - return &intrep.Instruction{ - Opcode: "MOVAPS", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(mx1): - return &intrep.Instruction{ - Opcode: "MOVAPS", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE"}, - }, nil - case operand.IsXMM(mx) && operand.IsM128(mx1): - return &intrep.Instruction{ - Opcode: "MOVAPS", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("MOVAPS: bad operands") +// KORQ k k k +func KORQ(k, k1, k2 operand.Op) (*intrep.Instruction, error) { + return build(opcKORQ.Forms(), sffxs{}, []operand.Op{k, k1, k2}) } -// MOVB: Move. +// KORTESTB: OR 8-bit Masks and Set Flags. // // Forms: // -// MOVB imm8 r8 -// MOVB r8 r8 -// MOVB m8 r8 -// MOVB imm8 m8 -// MOVB r8 m8 -func MOVB(imr, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(imr) && operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "MOVB", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR8(imr) && operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "MOVB", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{imr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM8(imr) && operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "MOVB", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{imr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(imr) && operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "MOVB", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR8(imr) && operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "MOVB", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{imr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("MOVB: bad operands") +// KORTESTB k k +func KORTESTB(k, k1 operand.Op) (*intrep.Instruction, error) { + return build(opcKORTESTB.Forms(), sffxs{}, []operand.Op{k, k1}) } -// MOVBELL: Move Data After Swapping Bytes. +// KORTESTD: OR 32-bit Masks and Set Flags. // // Forms: // -// MOVBELL m32 r32 -// MOVBELL r32 m32 -func MOVBELL(mr, mr1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM32(mr) && operand.IsR32(mr1): - return &intrep.Instruction{ - Opcode: "MOVBELL", - Operands: []operand.Op{mr, mr1}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr1}, - ISA: []string{"MOVBE"}, - }, nil - case operand.IsR32(mr) && operand.IsM32(mr1): - return &intrep.Instruction{ - Opcode: "MOVBELL", - Operands: []operand.Op{mr, mr1}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr1}, - ISA: []string{"MOVBE"}, - }, nil - } - return nil, errors.New("MOVBELL: bad operands") +// KORTESTD k k +func KORTESTD(k, k1 operand.Op) (*intrep.Instruction, error) { + return build(opcKORTESTD.Forms(), sffxs{}, []operand.Op{k, k1}) } -// MOVBEQQ: Move Data After Swapping Bytes. +// KORTESTQ: OR 64-bit Masks and Set Flags. // // Forms: // -// MOVBEQQ m64 r64 -// MOVBEQQ r64 m64 -func MOVBEQQ(mr, mr1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM64(mr) && operand.IsR64(mr1): - return &intrep.Instruction{ - Opcode: "MOVBEQQ", - Operands: []operand.Op{mr, mr1}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr1}, - ISA: []string{"MOVBE"}, - }, nil - case operand.IsR64(mr) && operand.IsM64(mr1): - return &intrep.Instruction{ - Opcode: "MOVBEQQ", - Operands: []operand.Op{mr, mr1}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr1}, - ISA: []string{"MOVBE"}, - }, nil - } - return nil, errors.New("MOVBEQQ: bad operands") +// KORTESTQ k k +func KORTESTQ(k, k1 operand.Op) (*intrep.Instruction, error) { + return build(opcKORTESTQ.Forms(), sffxs{}, []operand.Op{k, k1}) } -// MOVBEWW: Move Data After Swapping Bytes. +// KORTESTW: OR 16-bit Masks and Set Flags. // // Forms: // -// MOVBEWW m16 r16 -// MOVBEWW r16 m16 -func MOVBEWW(mr, mr1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM16(mr) && operand.IsR16(mr1): - return &intrep.Instruction{ - Opcode: "MOVBEWW", - Operands: []operand.Op{mr, mr1}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr1}, - ISA: []string{"MOVBE"}, - }, nil - case operand.IsR16(mr) && operand.IsM16(mr1): - return &intrep.Instruction{ - Opcode: "MOVBEWW", - Operands: []operand.Op{mr, mr1}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr1}, - ISA: []string{"MOVBE"}, - }, nil - } - return nil, errors.New("MOVBEWW: bad operands") +// KORTESTW k k +func KORTESTW(k, k1 operand.Op) (*intrep.Instruction, error) { + return build(opcKORTESTW.Forms(), sffxs{}, []operand.Op{k, k1}) } -// MOVBLSX: Move with Sign-Extension. +// KORW: Bitwise Logical OR 16-bit Masks. // // Forms: // -// MOVBLSX r8 r32 -// MOVBLSX m8 r32 -func MOVBLSX(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "MOVBLSX", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - case operand.IsM8(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "MOVBLSX", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - } - return nil, errors.New("MOVBLSX: bad operands") +// KORW k k k +func KORW(k, k1, k2 operand.Op) (*intrep.Instruction, error) { + return build(opcKORW.Forms(), sffxs{}, []operand.Op{k, k1, k2}) } -// MOVBLZX: Move with Zero-Extend. +// KSHIFTLB: Shift Left 8-bit Masks. // // Forms: // -// MOVBLZX r8 r32 -// MOVBLZX m8 r32 -func MOVBLZX(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "MOVBLZX", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - case operand.IsM8(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "MOVBLZX", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - } - return nil, errors.New("MOVBLZX: bad operands") +// KSHIFTLB imm8 k k +func KSHIFTLB(i, k, k1 operand.Op) (*intrep.Instruction, error) { + return build(opcKSHIFTLB.Forms(), sffxs{}, []operand.Op{i, k, k1}) } -// MOVBQSX: Move with Sign-Extension. +// KSHIFTLD: Shift Left 32-bit Masks. // // Forms: // -// MOVBQSX r8 r64 -// MOVBQSX m8 r64 -func MOVBQSX(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "MOVBQSX", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - case operand.IsM8(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "MOVBQSX", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - } - return nil, errors.New("MOVBQSX: bad operands") +// KSHIFTLD imm8 k k +func KSHIFTLD(i, k, k1 operand.Op) (*intrep.Instruction, error) { + return build(opcKSHIFTLD.Forms(), sffxs{}, []operand.Op{i, k, k1}) } -// MOVBQZX: Move with Zero-Extend. +// KSHIFTLQ: Shift Left 64-bit Masks. // // Forms: // -// MOVBQZX r8 r64 -// MOVBQZX m8 r64 -func MOVBQZX(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "MOVBQZX", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - case operand.IsM8(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "MOVBQZX", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - } - return nil, errors.New("MOVBQZX: bad operands") +// KSHIFTLQ imm8 k k +func KSHIFTLQ(i, k, k1 operand.Op) (*intrep.Instruction, error) { + return build(opcKSHIFTLQ.Forms(), sffxs{}, []operand.Op{i, k, k1}) } -// MOVBWSX: Move with Sign-Extension. +// KSHIFTLW: Shift Left 16-bit Masks. // // Forms: // -// MOVBWSX r8 r16 -// MOVBWSX m8 r16 -func MOVBWSX(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "MOVBWSX", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - case operand.IsM8(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "MOVBWSX", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - } - return nil, errors.New("MOVBWSX: bad operands") +// KSHIFTLW imm8 k k +func KSHIFTLW(i, k, k1 operand.Op) (*intrep.Instruction, error) { + return build(opcKSHIFTLW.Forms(), sffxs{}, []operand.Op{i, k, k1}) } -// MOVBWZX: Move with Zero-Extend. +// KSHIFTRB: Shift Right 8-bit Masks. // // Forms: // -// MOVBWZX r8 r16 -// MOVBWZX m8 r16 -func MOVBWZX(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "MOVBWZX", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - case operand.IsM8(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "MOVBWZX", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - } - return nil, errors.New("MOVBWZX: bad operands") +// KSHIFTRB imm8 k k +func KSHIFTRB(i, k, k1 operand.Op) (*intrep.Instruction, error) { + return build(opcKSHIFTRB.Forms(), sffxs{}, []operand.Op{i, k, k1}) } -// MOVD: Move. +// KSHIFTRD: Shift Right 32-bit Masks. // // Forms: // -// MOVD imm32 r64 -// MOVD imm64 r64 -// MOVD r64 r64 -// MOVD m64 r64 -// MOVD imm32 m64 -// MOVD r64 m64 -// MOVD xmm r64 -// MOVD r64 xmm -// MOVD xmm xmm -// MOVD m64 xmm -// MOVD xmm m64 -// MOVD xmm r32 -// MOVD r32 xmm -// MOVD m32 xmm -// MOVD xmm m32 -func MOVD(imrx, mrx operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM32(imrx) && operand.IsR64(mrx): - return &intrep.Instruction{ - Opcode: "MOVD", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mrx}, - }, nil - case operand.IsIMM64(imrx) && operand.IsR64(mrx): - return &intrep.Instruction{ - Opcode: "MOVD", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mrx}, - }, nil - case operand.IsR64(imrx) && operand.IsR64(mrx): - return &intrep.Instruction{ - Opcode: "MOVD", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - }, nil - case operand.IsM64(imrx) && operand.IsR64(mrx): - return &intrep.Instruction{ - Opcode: "MOVD", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - }, nil - case operand.IsIMM32(imrx) && operand.IsM64(mrx): - return &intrep.Instruction{ - Opcode: "MOVD", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mrx}, - }, nil - case operand.IsR64(imrx) && operand.IsM64(mrx): - return &intrep.Instruction{ - Opcode: "MOVD", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - }, nil - case operand.IsXMM(imrx) && operand.IsR64(mrx): - return &intrep.Instruction{ - Opcode: "MOVD", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsR64(imrx) && operand.IsXMM(mrx): - return &intrep.Instruction{ - Opcode: "MOVD", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsXMM(imrx) && operand.IsXMM(mrx): - return &intrep.Instruction{ - Opcode: "MOVD", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM64(imrx) && operand.IsXMM(mrx): - return &intrep.Instruction{ - Opcode: "MOVD", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsXMM(imrx) && operand.IsM64(mrx): - return &intrep.Instruction{ - Opcode: "MOVD", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsXMM(imrx) && operand.IsR32(mrx): - return &intrep.Instruction{ - Opcode: "MOVD", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsR32(imrx) && operand.IsXMM(mrx): - return &intrep.Instruction{ - Opcode: "MOVD", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM32(imrx) && operand.IsXMM(mrx): - return &intrep.Instruction{ - Opcode: "MOVD", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsXMM(imrx) && operand.IsM32(mrx): - return &intrep.Instruction{ - Opcode: "MOVD", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("MOVD: bad operands") +// KSHIFTRD imm8 k k +func KSHIFTRD(i, k, k1 operand.Op) (*intrep.Instruction, error) { + return build(opcKSHIFTRD.Forms(), sffxs{}, []operand.Op{i, k, k1}) } -// MOVDDUP: Move One Double-FP and Duplicate. +// KSHIFTRQ: Shift Right 64-bit Masks. // // Forms: // -// MOVDDUP xmm xmm -// MOVDDUP m64 xmm -func MOVDDUP(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MOVDDUP", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE3"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MOVDDUP", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE3"}, - }, nil - } - return nil, errors.New("MOVDDUP: bad operands") +// KSHIFTRQ imm8 k k +func KSHIFTRQ(i, k, k1 operand.Op) (*intrep.Instruction, error) { + return build(opcKSHIFTRQ.Forms(), sffxs{}, []operand.Op{i, k, k1}) } -// MOVDQ2Q: Move. +// KSHIFTRW: Shift Right 16-bit Masks. // // Forms: // -// MOVDQ2Q imm32 r64 -// MOVDQ2Q imm64 r64 -// MOVDQ2Q r64 r64 -// MOVDQ2Q m64 r64 -// MOVDQ2Q imm32 m64 -// MOVDQ2Q r64 m64 -// MOVDQ2Q xmm r64 -// MOVDQ2Q r64 xmm -// MOVDQ2Q xmm xmm -// MOVDQ2Q m64 xmm -// MOVDQ2Q xmm m64 -// MOVDQ2Q xmm r32 -// MOVDQ2Q r32 xmm -// MOVDQ2Q m32 xmm -// MOVDQ2Q xmm m32 -func MOVDQ2Q(imrx, mrx operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM32(imrx) && operand.IsR64(mrx): - return &intrep.Instruction{ - Opcode: "MOVDQ2Q", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mrx}, - }, nil - case operand.IsIMM64(imrx) && operand.IsR64(mrx): - return &intrep.Instruction{ - Opcode: "MOVDQ2Q", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mrx}, - }, nil - case operand.IsR64(imrx) && operand.IsR64(mrx): - return &intrep.Instruction{ - Opcode: "MOVDQ2Q", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - }, nil - case operand.IsM64(imrx) && operand.IsR64(mrx): - return &intrep.Instruction{ - Opcode: "MOVDQ2Q", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - }, nil - case operand.IsIMM32(imrx) && operand.IsM64(mrx): - return &intrep.Instruction{ - Opcode: "MOVDQ2Q", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mrx}, - }, nil - case operand.IsR64(imrx) && operand.IsM64(mrx): - return &intrep.Instruction{ - Opcode: "MOVDQ2Q", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - }, nil - case operand.IsXMM(imrx) && operand.IsR64(mrx): - return &intrep.Instruction{ - Opcode: "MOVDQ2Q", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsR64(imrx) && operand.IsXMM(mrx): - return &intrep.Instruction{ - Opcode: "MOVDQ2Q", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsXMM(imrx) && operand.IsXMM(mrx): - return &intrep.Instruction{ - Opcode: "MOVDQ2Q", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM64(imrx) && operand.IsXMM(mrx): - return &intrep.Instruction{ - Opcode: "MOVDQ2Q", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsXMM(imrx) && operand.IsM64(mrx): - return &intrep.Instruction{ - Opcode: "MOVDQ2Q", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsXMM(imrx) && operand.IsR32(mrx): - return &intrep.Instruction{ - Opcode: "MOVDQ2Q", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsR32(imrx) && operand.IsXMM(mrx): - return &intrep.Instruction{ - Opcode: "MOVDQ2Q", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM32(imrx) && operand.IsXMM(mrx): - return &intrep.Instruction{ - Opcode: "MOVDQ2Q", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsXMM(imrx) && operand.IsM32(mrx): - return &intrep.Instruction{ - Opcode: "MOVDQ2Q", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("MOVDQ2Q: bad operands") +// KSHIFTRW imm8 k k +func KSHIFTRW(i, k, k1 operand.Op) (*intrep.Instruction, error) { + return build(opcKSHIFTRW.Forms(), sffxs{}, []operand.Op{i, k, k1}) } -// MOVHLPS: Move Packed Single-Precision Floating-Point Values High to Low. +// KTESTB: Bit Test 8-bit Masks and Set Flags. // // Forms: // -// MOVHLPS xmm xmm +// KTESTB k k +func KTESTB(k, k1 operand.Op) (*intrep.Instruction, error) { + return build(opcKTESTB.Forms(), sffxs{}, []operand.Op{k, k1}) +} + +// KTESTD: Bit Test 32-bit Masks and Set Flags. +// +// Forms: +// +// KTESTD k k +func KTESTD(k, k1 operand.Op) (*intrep.Instruction, error) { + return build(opcKTESTD.Forms(), sffxs{}, []operand.Op{k, k1}) +} + +// KTESTQ: Bit Test 64-bit Masks and Set Flags. +// +// Forms: +// +// KTESTQ k k +func KTESTQ(k, k1 operand.Op) (*intrep.Instruction, error) { + return build(opcKTESTQ.Forms(), sffxs{}, []operand.Op{k, k1}) +} + +// KTESTW: Bit Test 16-bit Masks and Set Flags. +// +// Forms: +// +// KTESTW k k +func KTESTW(k, k1 operand.Op) (*intrep.Instruction, error) { + return build(opcKTESTW.Forms(), sffxs{}, []operand.Op{k, k1}) +} + +// KUNPCKBW: Unpack and Interleave 8-bit Masks. +// +// Forms: +// +// KUNPCKBW k k k +func KUNPCKBW(k, k1, k2 operand.Op) (*intrep.Instruction, error) { + return build(opcKUNPCKBW.Forms(), sffxs{}, []operand.Op{k, k1, k2}) +} + +// KUNPCKDQ: Unpack and Interleave 32-bit Masks. +// +// Forms: +// +// KUNPCKDQ k k k +func KUNPCKDQ(k, k1, k2 operand.Op) (*intrep.Instruction, error) { + return build(opcKUNPCKDQ.Forms(), sffxs{}, []operand.Op{k, k1, k2}) +} + +// KUNPCKWD: Unpack and Interleave 16-bit Masks. +// +// Forms: +// +// KUNPCKWD k k k +func KUNPCKWD(k, k1, k2 operand.Op) (*intrep.Instruction, error) { + return build(opcKUNPCKWD.Forms(), sffxs{}, []operand.Op{k, k1, k2}) +} + +// KXNORB: Bitwise Logical XNOR 8-bit Masks. +// +// Forms: +// +// KXNORB k k k +func KXNORB(k, k1, k2 operand.Op) (*intrep.Instruction, error) { + return build(opcKXNORB.Forms(), sffxs{}, []operand.Op{k, k1, k2}) +} + +// KXNORD: Bitwise Logical XNOR 32-bit Masks. +// +// Forms: +// +// KXNORD k k k +func KXNORD(k, k1, k2 operand.Op) (*intrep.Instruction, error) { + return build(opcKXNORD.Forms(), sffxs{}, []operand.Op{k, k1, k2}) +} + +// KXNORQ: Bitwise Logical XNOR 64-bit Masks. +// +// Forms: +// +// KXNORQ k k k +func KXNORQ(k, k1, k2 operand.Op) (*intrep.Instruction, error) { + return build(opcKXNORQ.Forms(), sffxs{}, []operand.Op{k, k1, k2}) +} + +// KXNORW: Bitwise Logical XNOR 16-bit Masks. +// +// Forms: +// +// KXNORW k k k +func KXNORW(k, k1, k2 operand.Op) (*intrep.Instruction, error) { + return build(opcKXNORW.Forms(), sffxs{}, []operand.Op{k, k1, k2}) +} + +// KXORB: Bitwise Logical XOR 8-bit Masks. +// +// Forms: +// +// KXORB k k k +func KXORB(k, k1, k2 operand.Op) (*intrep.Instruction, error) { + return build(opcKXORB.Forms(), sffxs{}, []operand.Op{k, k1, k2}) +} + +// KXORD: Bitwise Logical XOR 32-bit Masks. +// +// Forms: +// +// KXORD k k k +func KXORD(k, k1, k2 operand.Op) (*intrep.Instruction, error) { + return build(opcKXORD.Forms(), sffxs{}, []operand.Op{k, k1, k2}) +} + +// KXORQ: Bitwise Logical XOR 64-bit Masks. +// +// Forms: +// +// KXORQ k k k +func KXORQ(k, k1, k2 operand.Op) (*intrep.Instruction, error) { + return build(opcKXORQ.Forms(), sffxs{}, []operand.Op{k, k1, k2}) +} + +// KXORW: Bitwise Logical XOR 16-bit Masks. +// +// Forms: +// +// KXORW k k k +func KXORW(k, k1, k2 operand.Op) (*intrep.Instruction, error) { + return build(opcKXORW.Forms(), sffxs{}, []operand.Op{k, k1, k2}) +} + +// LDDQU: Load Unaligned Integer 128 Bits. +// +// Forms: +// +// LDDQU m128 xmm +func LDDQU(m, x operand.Op) (*intrep.Instruction, error) { + return build(opcLDDQU.Forms(), sffxs{}, []operand.Op{m, x}) +} + +// LDMXCSR: Load MXCSR Register. +// +// Forms: +// +// LDMXCSR m32 +func LDMXCSR(m operand.Op) (*intrep.Instruction, error) { + return build(opcLDMXCSR.Forms(), sffxs{}, []operand.Op{m}) +} + +// LEAL: Load Effective Address. +// +// Forms: +// +// LEAL m r32 +func LEAL(m, r operand.Op) (*intrep.Instruction, error) { + return build(opcLEAL.Forms(), sffxs{}, []operand.Op{m, r}) +} + +// LEAQ: Load Effective Address. +// +// Forms: +// +// LEAQ m r64 +func LEAQ(m, r operand.Op) (*intrep.Instruction, error) { + return build(opcLEAQ.Forms(), sffxs{}, []operand.Op{m, r}) +} + +// LEAW: Load Effective Address. +// +// Forms: +// +// LEAW m r16 +func LEAW(m, r operand.Op) (*intrep.Instruction, error) { + return build(opcLEAW.Forms(), sffxs{}, []operand.Op{m, r}) +} + +// LFENCE: Load Fence. +// +// Forms: +// +// LFENCE +func LFENCE() (*intrep.Instruction, error) { + return build(opcLFENCE.Forms(), sffxs{}, []operand.Op{}) +} + +// LZCNTL: Count the Number of Leading Zero Bits. +// +// Forms: +// +// LZCNTL m32 r32 +// LZCNTL r32 r32 +func LZCNTL(mr, r operand.Op) (*intrep.Instruction, error) { + return build(opcLZCNTL.Forms(), sffxs{}, []operand.Op{mr, r}) +} + +// LZCNTQ: Count the Number of Leading Zero Bits. +// +// Forms: +// +// LZCNTQ m64 r64 +// LZCNTQ r64 r64 +func LZCNTQ(mr, r operand.Op) (*intrep.Instruction, error) { + return build(opcLZCNTQ.Forms(), sffxs{}, []operand.Op{mr, r}) +} + +// LZCNTW: Count the Number of Leading Zero Bits. +// +// Forms: +// +// LZCNTW m16 r16 +// LZCNTW r16 r16 +func LZCNTW(mr, r operand.Op) (*intrep.Instruction, error) { + return build(opcLZCNTW.Forms(), sffxs{}, []operand.Op{mr, r}) +} + +// MASKMOVDQU: Store Selected Bytes of Double Quadword. +// +// Forms: +// +// MASKMOVDQU xmm xmm +func MASKMOVDQU(x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcMASKMOVDQU.Forms(), sffxs{}, []operand.Op{x, x1}) +} + +// MASKMOVOU: Store Selected Bytes of Double Quadword. +// +// Forms: +// +// MASKMOVOU xmm xmm +func MASKMOVOU(x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcMASKMOVOU.Forms(), sffxs{}, []operand.Op{x, x1}) +} + +// MAXPD: Return Maximum Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// MAXPD m128 xmm +// MAXPD xmm xmm +func MAXPD(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcMAXPD.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// MAXPS: Return Maximum Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// MAXPS m128 xmm +// MAXPS xmm xmm +func MAXPS(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcMAXPS.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// MAXSD: Return Maximum Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// MAXSD m64 xmm +// MAXSD xmm xmm +func MAXSD(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcMAXSD.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// MAXSS: Return Maximum Scalar Single-Precision Floating-Point Value. +// +// Forms: +// +// MAXSS m32 xmm +// MAXSS xmm xmm +func MAXSS(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcMAXSS.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// MFENCE: Memory Fence. +// +// Forms: +// +// MFENCE +func MFENCE() (*intrep.Instruction, error) { + return build(opcMFENCE.Forms(), sffxs{}, []operand.Op{}) +} + +// MINPD: Return Minimum Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// MINPD m128 xmm +// MINPD xmm xmm +func MINPD(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcMINPD.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// MINPS: Return Minimum Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// MINPS m128 xmm +// MINPS xmm xmm +func MINPS(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcMINPS.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// MINSD: Return Minimum Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// MINSD m64 xmm +// MINSD xmm xmm +func MINSD(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcMINSD.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// MINSS: Return Minimum Scalar Single-Precision Floating-Point Value. +// +// Forms: +// +// MINSS m32 xmm +// MINSS xmm xmm +func MINSS(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcMINSS.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// MONITOR: Monitor a Linear Address Range. +// +// Forms: +// +// MONITOR +func MONITOR() (*intrep.Instruction, error) { + return build(opcMONITOR.Forms(), sffxs{}, []operand.Op{}) +} + +// MOVAPD: Move Aligned Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// MOVAPD m128 xmm +// MOVAPD xmm m128 +// MOVAPD xmm xmm +func MOVAPD(mx, mx1 operand.Op) (*intrep.Instruction, error) { + return build(opcMOVAPD.Forms(), sffxs{}, []operand.Op{mx, mx1}) +} + +// MOVAPS: Move Aligned Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// MOVAPS m128 xmm +// MOVAPS xmm m128 +// MOVAPS xmm xmm +func MOVAPS(mx, mx1 operand.Op) (*intrep.Instruction, error) { + return build(opcMOVAPS.Forms(), sffxs{}, []operand.Op{mx, mx1}) +} + +// MOVB: Move. +// +// Forms: +// +// MOVB imm8 m8 +// MOVB imm8 r8 +// MOVB m8 r8 +// MOVB r8 m8 +// MOVB r8 r8 +func MOVB(imr, mr operand.Op) (*intrep.Instruction, error) { + return build(opcMOVB.Forms(), sffxs{}, []operand.Op{imr, mr}) +} + +// MOVBELL: Move Data After Swapping Bytes. +// +// Forms: +// +// MOVBELL m32 r32 +// MOVBELL r32 m32 +func MOVBELL(mr, mr1 operand.Op) (*intrep.Instruction, error) { + return build(opcMOVBELL.Forms(), sffxs{}, []operand.Op{mr, mr1}) +} + +// MOVBEQQ: Move Data After Swapping Bytes. +// +// Forms: +// +// MOVBEQQ m64 r64 +// MOVBEQQ r64 m64 +func MOVBEQQ(mr, mr1 operand.Op) (*intrep.Instruction, error) { + return build(opcMOVBEQQ.Forms(), sffxs{}, []operand.Op{mr, mr1}) +} + +// MOVBEWW: Move Data After Swapping Bytes. +// +// Forms: +// +// MOVBEWW m16 r16 +// MOVBEWW r16 m16 +func MOVBEWW(mr, mr1 operand.Op) (*intrep.Instruction, error) { + return build(opcMOVBEWW.Forms(), sffxs{}, []operand.Op{mr, mr1}) +} + +// MOVBLSX: Move with Sign-Extension. +// +// Forms: +// +// MOVBLSX m8 r32 +// MOVBLSX r8 r32 +func MOVBLSX(mr, r operand.Op) (*intrep.Instruction, error) { + return build(opcMOVBLSX.Forms(), sffxs{}, []operand.Op{mr, r}) +} + +// MOVBLZX: Move with Zero-Extend. +// +// Forms: +// +// MOVBLZX m8 r32 +// MOVBLZX r8 r32 +func MOVBLZX(mr, r operand.Op) (*intrep.Instruction, error) { + return build(opcMOVBLZX.Forms(), sffxs{}, []operand.Op{mr, r}) +} + +// MOVBQSX: Move with Sign-Extension. +// +// Forms: +// +// MOVBQSX m8 r64 +// MOVBQSX r8 r64 +func MOVBQSX(mr, r operand.Op) (*intrep.Instruction, error) { + return build(opcMOVBQSX.Forms(), sffxs{}, []operand.Op{mr, r}) +} + +// MOVBQZX: Move with Zero-Extend. +// +// Forms: +// +// MOVBQZX m8 r64 +// MOVBQZX r8 r64 +func MOVBQZX(mr, r operand.Op) (*intrep.Instruction, error) { + return build(opcMOVBQZX.Forms(), sffxs{}, []operand.Op{mr, r}) +} + +// MOVBWSX: Move with Sign-Extension. +// +// Forms: +// +// MOVBWSX m8 r16 +// MOVBWSX r8 r16 +func MOVBWSX(mr, r operand.Op) (*intrep.Instruction, error) { + return build(opcMOVBWSX.Forms(), sffxs{}, []operand.Op{mr, r}) +} + +// MOVBWZX: Move with Zero-Extend. +// +// Forms: +// +// MOVBWZX m8 r16 +// MOVBWZX r8 r16 +func MOVBWZX(mr, r operand.Op) (*intrep.Instruction, error) { + return build(opcMOVBWZX.Forms(), sffxs{}, []operand.Op{mr, r}) +} + +// MOVD: Move. +// +// Forms: +// +// MOVD m32 xmm +// MOVD m64 xmm +// MOVD r32 xmm +// MOVD r64 xmm +// MOVD xmm m32 +// MOVD xmm m64 +// MOVD xmm r32 +// MOVD xmm r64 +// MOVD xmm xmm +// MOVD imm32 m64 +// MOVD imm32 r64 +// MOVD imm64 r64 +// MOVD m64 r64 +// MOVD r64 m64 +// MOVD r64 r64 +func MOVD(imrx, mrx operand.Op) (*intrep.Instruction, error) { + return build(opcMOVD.Forms(), sffxs{}, []operand.Op{imrx, mrx}) +} + +// MOVDDUP: Move One Double-FP and Duplicate. +// +// Forms: +// +// MOVDDUP m64 xmm +// MOVDDUP xmm xmm +func MOVDDUP(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcMOVDDUP.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// MOVDQ2Q: Move. +// +// Forms: +// +// MOVDQ2Q m32 xmm +// MOVDQ2Q m64 xmm +// MOVDQ2Q r32 xmm +// MOVDQ2Q r64 xmm +// MOVDQ2Q xmm m32 +// MOVDQ2Q xmm m64 +// MOVDQ2Q xmm r32 +// MOVDQ2Q xmm r64 +// MOVDQ2Q xmm xmm +// MOVDQ2Q imm32 m64 +// MOVDQ2Q imm32 r64 +// MOVDQ2Q imm64 r64 +// MOVDQ2Q m64 r64 +// MOVDQ2Q r64 m64 +// MOVDQ2Q r64 r64 +func MOVDQ2Q(imrx, mrx operand.Op) (*intrep.Instruction, error) { + return build(opcMOVDQ2Q.Forms(), sffxs{}, []operand.Op{imrx, mrx}) +} + +// MOVHLPS: Move Packed Single-Precision Floating-Point Values High to Low. +// +// Forms: +// +// MOVHLPS xmm xmm func MOVHLPS(x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "MOVHLPS", - Operands: []operand.Op{x, x1}, - Inputs: []operand.Op{x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("MOVHLPS: bad operands") + return build(opcMOVHLPS.Forms(), sffxs{}, []operand.Op{x, x1}) +} + +// MOVHPD: Move High Packed Double-Precision Floating-Point Value. +// +// Forms: +// +// MOVHPD m64 xmm +// MOVHPD xmm m64 +func MOVHPD(mx, mx1 operand.Op) (*intrep.Instruction, error) { + return build(opcMOVHPD.Forms(), sffxs{}, []operand.Op{mx, mx1}) +} + +// MOVHPS: Move High Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// MOVHPS m64 xmm +// MOVHPS xmm m64 +func MOVHPS(mx, mx1 operand.Op) (*intrep.Instruction, error) { + return build(opcMOVHPS.Forms(), sffxs{}, []operand.Op{mx, mx1}) +} + +// MOVL: Move. +// +// Forms: +// +// MOVL imm32 m32 +// MOVL imm32 r32 +// MOVL m32 r32 +// MOVL r32 m32 +// MOVL r32 r32 +func MOVL(imr, mr operand.Op) (*intrep.Instruction, error) { + return build(opcMOVL.Forms(), sffxs{}, []operand.Op{imr, mr}) +} + +// MOVLHPS: Move Packed Single-Precision Floating-Point Values Low to High. +// +// Forms: +// +// MOVLHPS xmm xmm +func MOVLHPS(x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcMOVLHPS.Forms(), sffxs{}, []operand.Op{x, x1}) +} + +// MOVLPD: Move Low Packed Double-Precision Floating-Point Value. +// +// Forms: +// +// MOVLPD m64 xmm +// MOVLPD xmm m64 +func MOVLPD(mx, mx1 operand.Op) (*intrep.Instruction, error) { + return build(opcMOVLPD.Forms(), sffxs{}, []operand.Op{mx, mx1}) +} + +// MOVLPS: Move Low Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// MOVLPS m64 xmm +// MOVLPS xmm m64 +func MOVLPS(mx, mx1 operand.Op) (*intrep.Instruction, error) { + return build(opcMOVLPS.Forms(), sffxs{}, []operand.Op{mx, mx1}) +} + +// MOVLQSX: Move Doubleword to Quadword with Sign-Extension. +// +// Forms: +// +// MOVLQSX m32 r64 +// MOVLQSX r32 r64 +func MOVLQSX(mr, r operand.Op) (*intrep.Instruction, error) { + return build(opcMOVLQSX.Forms(), sffxs{}, []operand.Op{mr, r}) +} + +// MOVLQZX: Move with Zero-Extend. +// +// Forms: +// +// MOVLQZX m32 r64 +func MOVLQZX(m, r operand.Op) (*intrep.Instruction, error) { + return build(opcMOVLQZX.Forms(), sffxs{}, []operand.Op{m, r}) +} + +// MOVMSKPD: Extract Packed Double-Precision Floating-Point Sign Mask. +// +// Forms: +// +// MOVMSKPD xmm r32 +func MOVMSKPD(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcMOVMSKPD.Forms(), sffxs{}, []operand.Op{x, r}) +} + +// MOVMSKPS: Extract Packed Single-Precision Floating-Point Sign Mask. +// +// Forms: +// +// MOVMSKPS xmm r32 +func MOVMSKPS(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcMOVMSKPS.Forms(), sffxs{}, []operand.Op{x, r}) +} + +// MOVNTDQ: Store Double Quadword Using Non-Temporal Hint. +// +// Forms: +// +// MOVNTDQ xmm m128 +func MOVNTDQ(x, m operand.Op) (*intrep.Instruction, error) { + return build(opcMOVNTDQ.Forms(), sffxs{}, []operand.Op{x, m}) +} + +// MOVNTDQA: Load Double Quadword Non-Temporal Aligned Hint. +// +// Forms: +// +// MOVNTDQA m128 xmm +func MOVNTDQA(m, x operand.Op) (*intrep.Instruction, error) { + return build(opcMOVNTDQA.Forms(), sffxs{}, []operand.Op{m, x}) +} + +// MOVNTIL: Store Doubleword Using Non-Temporal Hint. +// +// Forms: +// +// MOVNTIL r32 m32 +func MOVNTIL(r, m operand.Op) (*intrep.Instruction, error) { + return build(opcMOVNTIL.Forms(), sffxs{}, []operand.Op{r, m}) +} + +// MOVNTIQ: Store Doubleword Using Non-Temporal Hint. +// +// Forms: +// +// MOVNTIQ r64 m64 +func MOVNTIQ(r, m operand.Op) (*intrep.Instruction, error) { + return build(opcMOVNTIQ.Forms(), sffxs{}, []operand.Op{r, m}) +} + +// MOVNTO: Store Double Quadword Using Non-Temporal Hint. +// +// Forms: +// +// MOVNTO xmm m128 +func MOVNTO(x, m operand.Op) (*intrep.Instruction, error) { + return build(opcMOVNTO.Forms(), sffxs{}, []operand.Op{x, m}) +} + +// MOVNTPD: Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint. +// +// Forms: +// +// MOVNTPD xmm m128 +func MOVNTPD(x, m operand.Op) (*intrep.Instruction, error) { + return build(opcMOVNTPD.Forms(), sffxs{}, []operand.Op{x, m}) +} + +// MOVNTPS: Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint. +// +// Forms: +// +// MOVNTPS xmm m128 +func MOVNTPS(x, m operand.Op) (*intrep.Instruction, error) { + return build(opcMOVNTPS.Forms(), sffxs{}, []operand.Op{x, m}) +} + +// MOVO: Move Aligned Double Quadword. +// +// Forms: +// +// MOVO m128 xmm +// MOVO xmm m128 +// MOVO xmm xmm +func MOVO(mx, mx1 operand.Op) (*intrep.Instruction, error) { + return build(opcMOVO.Forms(), sffxs{}, []operand.Op{mx, mx1}) +} + +// MOVOA: Move Aligned Double Quadword. +// +// Forms: +// +// MOVOA m128 xmm +// MOVOA xmm m128 +// MOVOA xmm xmm +func MOVOA(mx, mx1 operand.Op) (*intrep.Instruction, error) { + return build(opcMOVOA.Forms(), sffxs{}, []operand.Op{mx, mx1}) +} + +// MOVOU: Move Unaligned Double Quadword. +// +// Forms: +// +// MOVOU m128 xmm +// MOVOU xmm m128 +// MOVOU xmm xmm +func MOVOU(mx, mx1 operand.Op) (*intrep.Instruction, error) { + return build(opcMOVOU.Forms(), sffxs{}, []operand.Op{mx, mx1}) +} + +// MOVQ: Move. +// +// Forms: +// +// MOVQ m32 xmm +// MOVQ m64 xmm +// MOVQ r32 xmm +// MOVQ r64 xmm +// MOVQ xmm m32 +// MOVQ xmm m64 +// MOVQ xmm r32 +// MOVQ xmm r64 +// MOVQ xmm xmm +// MOVQ imm32 m64 +// MOVQ imm32 r64 +// MOVQ imm64 r64 +// MOVQ m64 r64 +// MOVQ r64 m64 +// MOVQ r64 r64 +func MOVQ(imrx, mrx operand.Op) (*intrep.Instruction, error) { + return build(opcMOVQ.Forms(), sffxs{}, []operand.Op{imrx, mrx}) +} + +// MOVSD: Move Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// MOVSD m64 xmm +// MOVSD xmm m64 +// MOVSD xmm xmm +func MOVSD(mx, mx1 operand.Op) (*intrep.Instruction, error) { + return build(opcMOVSD.Forms(), sffxs{}, []operand.Op{mx, mx1}) +} + +// MOVSHDUP: Move Packed Single-FP High and Duplicate. +// +// Forms: +// +// MOVSHDUP m128 xmm +// MOVSHDUP xmm xmm +func MOVSHDUP(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcMOVSHDUP.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// MOVSLDUP: Move Packed Single-FP Low and Duplicate. +// +// Forms: +// +// MOVSLDUP m128 xmm +// MOVSLDUP xmm xmm +func MOVSLDUP(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcMOVSLDUP.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// MOVSS: Move Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// MOVSS m32 xmm +// MOVSS xmm m32 +// MOVSS xmm xmm +func MOVSS(mx, mx1 operand.Op) (*intrep.Instruction, error) { + return build(opcMOVSS.Forms(), sffxs{}, []operand.Op{mx, mx1}) +} + +// MOVUPD: Move Unaligned Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// MOVUPD m128 xmm +// MOVUPD xmm m128 +// MOVUPD xmm xmm +func MOVUPD(mx, mx1 operand.Op) (*intrep.Instruction, error) { + return build(opcMOVUPD.Forms(), sffxs{}, []operand.Op{mx, mx1}) +} + +// MOVUPS: Move Unaligned Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// MOVUPS m128 xmm +// MOVUPS xmm m128 +// MOVUPS xmm xmm +func MOVUPS(mx, mx1 operand.Op) (*intrep.Instruction, error) { + return build(opcMOVUPS.Forms(), sffxs{}, []operand.Op{mx, mx1}) +} + +// MOVW: Move. +// +// Forms: +// +// MOVW imm16 m16 +// MOVW imm16 r16 +// MOVW m16 r16 +// MOVW r16 m16 +// MOVW r16 r16 +func MOVW(imr, mr operand.Op) (*intrep.Instruction, error) { + return build(opcMOVW.Forms(), sffxs{}, []operand.Op{imr, mr}) +} + +// MOVWLSX: Move with Sign-Extension. +// +// Forms: +// +// MOVWLSX m16 r32 +// MOVWLSX r16 r32 +func MOVWLSX(mr, r operand.Op) (*intrep.Instruction, error) { + return build(opcMOVWLSX.Forms(), sffxs{}, []operand.Op{mr, r}) +} + +// MOVWLZX: Move with Zero-Extend. +// +// Forms: +// +// MOVWLZX m16 r32 +// MOVWLZX r16 r32 +func MOVWLZX(mr, r operand.Op) (*intrep.Instruction, error) { + return build(opcMOVWLZX.Forms(), sffxs{}, []operand.Op{mr, r}) +} + +// MOVWQSX: Move with Sign-Extension. +// +// Forms: +// +// MOVWQSX m16 r64 +// MOVWQSX r16 r64 +func MOVWQSX(mr, r operand.Op) (*intrep.Instruction, error) { + return build(opcMOVWQSX.Forms(), sffxs{}, []operand.Op{mr, r}) +} + +// MOVWQZX: Move with Zero-Extend. +// +// Forms: +// +// MOVWQZX m16 r64 +// MOVWQZX r16 r64 +func MOVWQZX(mr, r operand.Op) (*intrep.Instruction, error) { + return build(opcMOVWQZX.Forms(), sffxs{}, []operand.Op{mr, r}) +} + +// MPSADBW: Compute Multiple Packed Sums of Absolute Difference. +// +// Forms: +// +// MPSADBW imm8 m128 xmm +// MPSADBW imm8 xmm xmm +func MPSADBW(i, mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcMPSADBW.Forms(), sffxs{}, []operand.Op{i, mx, x}) +} + +// MULB: Unsigned Multiply. +// +// Forms: +// +// MULB m8 +// MULB r8 +func MULB(mr operand.Op) (*intrep.Instruction, error) { + return build(opcMULB.Forms(), sffxs{}, []operand.Op{mr}) +} + +// MULL: Unsigned Multiply. +// +// Forms: +// +// MULL m32 +// MULL r32 +func MULL(mr operand.Op) (*intrep.Instruction, error) { + return build(opcMULL.Forms(), sffxs{}, []operand.Op{mr}) +} + +// MULPD: Multiply Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// MULPD m128 xmm +// MULPD xmm xmm +func MULPD(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcMULPD.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// MULPS: Multiply Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// MULPS m128 xmm +// MULPS xmm xmm +func MULPS(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcMULPS.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// MULQ: Unsigned Multiply. +// +// Forms: +// +// MULQ m64 +// MULQ r64 +func MULQ(mr operand.Op) (*intrep.Instruction, error) { + return build(opcMULQ.Forms(), sffxs{}, []operand.Op{mr}) +} + +// MULSD: Multiply Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// MULSD m64 xmm +// MULSD xmm xmm +func MULSD(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcMULSD.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// MULSS: Multiply Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// MULSS m32 xmm +// MULSS xmm xmm +func MULSS(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcMULSS.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// MULW: Unsigned Multiply. +// +// Forms: +// +// MULW m16 +// MULW r16 +func MULW(mr operand.Op) (*intrep.Instruction, error) { + return build(opcMULW.Forms(), sffxs{}, []operand.Op{mr}) +} + +// MULXL: Unsigned Multiply Without Affecting Flags. +// +// Forms: +// +// MULXL m32 r32 r32 +// MULXL r32 r32 r32 +func MULXL(mr, r, r1 operand.Op) (*intrep.Instruction, error) { + return build(opcMULXL.Forms(), sffxs{}, []operand.Op{mr, r, r1}) +} + +// MULXQ: Unsigned Multiply Without Affecting Flags. +// +// Forms: +// +// MULXQ m64 r64 r64 +// MULXQ r64 r64 r64 +func MULXQ(mr, r, r1 operand.Op) (*intrep.Instruction, error) { + return build(opcMULXQ.Forms(), sffxs{}, []operand.Op{mr, r, r1}) +} + +// MWAIT: Monitor Wait. +// +// Forms: +// +// MWAIT +func MWAIT() (*intrep.Instruction, error) { + return build(opcMWAIT.Forms(), sffxs{}, []operand.Op{}) +} + +// NEGB: Two's Complement Negation. +// +// Forms: +// +// NEGB m8 +// NEGB r8 +func NEGB(mr operand.Op) (*intrep.Instruction, error) { + return build(opcNEGB.Forms(), sffxs{}, []operand.Op{mr}) +} + +// NEGL: Two's Complement Negation. +// +// Forms: +// +// NEGL m32 +// NEGL r32 +func NEGL(mr operand.Op) (*intrep.Instruction, error) { + return build(opcNEGL.Forms(), sffxs{}, []operand.Op{mr}) +} + +// NEGQ: Two's Complement Negation. +// +// Forms: +// +// NEGQ m64 +// NEGQ r64 +func NEGQ(mr operand.Op) (*intrep.Instruction, error) { + return build(opcNEGQ.Forms(), sffxs{}, []operand.Op{mr}) +} + +// NEGW: Two's Complement Negation. +// +// Forms: +// +// NEGW m16 +// NEGW r16 +func NEGW(mr operand.Op) (*intrep.Instruction, error) { + return build(opcNEGW.Forms(), sffxs{}, []operand.Op{mr}) +} + +// NOP: No Operation. +// +// Forms: +// +// NOP +func NOP() (*intrep.Instruction, error) { + return build(opcNOP.Forms(), sffxs{}, []operand.Op{}) +} + +// NOTB: One's Complement Negation. +// +// Forms: +// +// NOTB m8 +// NOTB r8 +func NOTB(mr operand.Op) (*intrep.Instruction, error) { + return build(opcNOTB.Forms(), sffxs{}, []operand.Op{mr}) +} + +// NOTL: One's Complement Negation. +// +// Forms: +// +// NOTL m32 +// NOTL r32 +func NOTL(mr operand.Op) (*intrep.Instruction, error) { + return build(opcNOTL.Forms(), sffxs{}, []operand.Op{mr}) +} + +// NOTQ: One's Complement Negation. +// +// Forms: +// +// NOTQ m64 +// NOTQ r64 +func NOTQ(mr operand.Op) (*intrep.Instruction, error) { + return build(opcNOTQ.Forms(), sffxs{}, []operand.Op{mr}) +} + +// NOTW: One's Complement Negation. +// +// Forms: +// +// NOTW m16 +// NOTW r16 +func NOTW(mr operand.Op) (*intrep.Instruction, error) { + return build(opcNOTW.Forms(), sffxs{}, []operand.Op{mr}) +} + +// ORB: Logical Inclusive OR. +// +// Forms: +// +// ORB imm8 al +// ORB imm8 m8 +// ORB imm8 r8 +// ORB m8 r8 +// ORB r8 m8 +// ORB r8 r8 +func ORB(imr, amr operand.Op) (*intrep.Instruction, error) { + return build(opcORB.Forms(), sffxs{}, []operand.Op{imr, amr}) +} + +// ORL: Logical Inclusive OR. +// +// Forms: +// +// ORL imm32 eax +// ORL imm32 m32 +// ORL imm32 r32 +// ORL imm8 m32 +// ORL imm8 r32 +// ORL m32 r32 +// ORL r32 m32 +// ORL r32 r32 +func ORL(imr, emr operand.Op) (*intrep.Instruction, error) { + return build(opcORL.Forms(), sffxs{}, []operand.Op{imr, emr}) +} + +// ORPD: Bitwise Logical OR of Double-Precision Floating-Point Values. +// +// Forms: +// +// ORPD m128 xmm +// ORPD xmm xmm +func ORPD(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcORPD.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// ORPS: Bitwise Logical OR of Single-Precision Floating-Point Values. +// +// Forms: +// +// ORPS m128 xmm +// ORPS xmm xmm +func ORPS(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcORPS.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// ORQ: Logical Inclusive OR. +// +// Forms: +// +// ORQ imm32 m64 +// ORQ imm32 r64 +// ORQ imm32 rax +// ORQ imm8 m64 +// ORQ imm8 r64 +// ORQ m64 r64 +// ORQ r64 m64 +// ORQ r64 r64 +func ORQ(imr, mr operand.Op) (*intrep.Instruction, error) { + return build(opcORQ.Forms(), sffxs{}, []operand.Op{imr, mr}) +} + +// ORW: Logical Inclusive OR. +// +// Forms: +// +// ORW imm16 ax +// ORW imm16 m16 +// ORW imm16 r16 +// ORW imm8 m16 +// ORW imm8 r16 +// ORW m16 r16 +// ORW r16 m16 +// ORW r16 r16 +func ORW(imr, amr operand.Op) (*intrep.Instruction, error) { + return build(opcORW.Forms(), sffxs{}, []operand.Op{imr, amr}) +} + +// PABSB: Packed Absolute Value of Byte Integers. +// +// Forms: +// +// PABSB m128 xmm +// PABSB xmm xmm +func PABSB(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPABSB.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PABSD: Packed Absolute Value of Doubleword Integers. +// +// Forms: +// +// PABSD m128 xmm +// PABSD xmm xmm +func PABSD(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPABSD.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PABSW: Packed Absolute Value of Word Integers. +// +// Forms: +// +// PABSW m128 xmm +// PABSW xmm xmm +func PABSW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPABSW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PACKSSLW: Pack Doublewords into Words with Signed Saturation. +// +// Forms: +// +// PACKSSLW m128 xmm +// PACKSSLW xmm xmm +func PACKSSLW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPACKSSLW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PACKSSWB: Pack Words into Bytes with Signed Saturation. +// +// Forms: +// +// PACKSSWB m128 xmm +// PACKSSWB xmm xmm +func PACKSSWB(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPACKSSWB.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PACKUSDW: Pack Doublewords into Words with Unsigned Saturation. +// +// Forms: +// +// PACKUSDW m128 xmm +// PACKUSDW xmm xmm +func PACKUSDW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPACKUSDW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PACKUSWB: Pack Words into Bytes with Unsigned Saturation. +// +// Forms: +// +// PACKUSWB m128 xmm +// PACKUSWB xmm xmm +func PACKUSWB(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPACKUSWB.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PADDB: Add Packed Byte Integers. +// +// Forms: +// +// PADDB m128 xmm +// PADDB xmm xmm +func PADDB(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPADDB.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PADDD: Add Packed Doubleword Integers. +// +// Forms: +// +// PADDD m128 xmm +// PADDD xmm xmm +func PADDD(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPADDD.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PADDL: Add Packed Doubleword Integers. +// +// Forms: +// +// PADDL m128 xmm +// PADDL xmm xmm +func PADDL(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPADDL.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PADDQ: Add Packed Quadword Integers. +// +// Forms: +// +// PADDQ m128 xmm +// PADDQ xmm xmm +func PADDQ(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPADDQ.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PADDSB: Add Packed Signed Byte Integers with Signed Saturation. +// +// Forms: +// +// PADDSB m128 xmm +// PADDSB xmm xmm +func PADDSB(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPADDSB.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PADDSW: Add Packed Signed Word Integers with Signed Saturation. +// +// Forms: +// +// PADDSW m128 xmm +// PADDSW xmm xmm +func PADDSW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPADDSW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PADDUSB: Add Packed Unsigned Byte Integers with Unsigned Saturation. +// +// Forms: +// +// PADDUSB m128 xmm +// PADDUSB xmm xmm +func PADDUSB(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPADDUSB.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PADDUSW: Add Packed Unsigned Word Integers with Unsigned Saturation. +// +// Forms: +// +// PADDUSW m128 xmm +// PADDUSW xmm xmm +func PADDUSW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPADDUSW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PADDW: Add Packed Word Integers. +// +// Forms: +// +// PADDW m128 xmm +// PADDW xmm xmm +func PADDW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPADDW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PALIGNR: Packed Align Right. +// +// Forms: +// +// PALIGNR imm8 m128 xmm +// PALIGNR imm8 xmm xmm +func PALIGNR(i, mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPALIGNR.Forms(), sffxs{}, []operand.Op{i, mx, x}) +} + +// PAND: Packed Bitwise Logical AND. +// +// Forms: +// +// PAND m128 xmm +// PAND xmm xmm +func PAND(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPAND.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PANDN: Packed Bitwise Logical AND NOT. +// +// Forms: +// +// PANDN m128 xmm +// PANDN xmm xmm +func PANDN(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPANDN.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PAUSE: Spin Loop Hint. +// +// Forms: +// +// PAUSE +func PAUSE() (*intrep.Instruction, error) { + return build(opcPAUSE.Forms(), sffxs{}, []operand.Op{}) +} + +// PAVGB: Average Packed Byte Integers. +// +// Forms: +// +// PAVGB m128 xmm +// PAVGB xmm xmm +func PAVGB(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPAVGB.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PAVGW: Average Packed Word Integers. +// +// Forms: +// +// PAVGW m128 xmm +// PAVGW xmm xmm +func PAVGW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPAVGW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PBLENDVB: Variable Blend Packed Bytes. +// +// Forms: +// +// PBLENDVB xmm0 m128 xmm +// PBLENDVB xmm0 xmm xmm +func PBLENDVB(x, mx, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcPBLENDVB.Forms(), sffxs{}, []operand.Op{x, mx, x1}) +} + +// PBLENDW: Blend Packed Words. +// +// Forms: +// +// PBLENDW imm8 m128 xmm +// PBLENDW imm8 xmm xmm +func PBLENDW(i, mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPBLENDW.Forms(), sffxs{}, []operand.Op{i, mx, x}) +} + +// PCLMULQDQ: Carry-Less Quadword Multiplication. +// +// Forms: +// +// PCLMULQDQ imm8 m128 xmm +// PCLMULQDQ imm8 xmm xmm +func PCLMULQDQ(i, mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPCLMULQDQ.Forms(), sffxs{}, []operand.Op{i, mx, x}) +} + +// PCMPEQB: Compare Packed Byte Data for Equality. +// +// Forms: +// +// PCMPEQB m128 xmm +// PCMPEQB xmm xmm +func PCMPEQB(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPCMPEQB.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PCMPEQL: Compare Packed Doubleword Data for Equality. +// +// Forms: +// +// PCMPEQL m128 xmm +// PCMPEQL xmm xmm +func PCMPEQL(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPCMPEQL.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PCMPEQQ: Compare Packed Quadword Data for Equality. +// +// Forms: +// +// PCMPEQQ m128 xmm +// PCMPEQQ xmm xmm +func PCMPEQQ(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPCMPEQQ.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PCMPEQW: Compare Packed Word Data for Equality. +// +// Forms: +// +// PCMPEQW m128 xmm +// PCMPEQW xmm xmm +func PCMPEQW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPCMPEQW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PCMPESTRI: Packed Compare Explicit Length Strings, Return Index. +// +// Forms: +// +// PCMPESTRI imm8 m128 xmm +// PCMPESTRI imm8 xmm xmm +func PCMPESTRI(i, mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPCMPESTRI.Forms(), sffxs{}, []operand.Op{i, mx, x}) +} + +// PCMPESTRM: Packed Compare Explicit Length Strings, Return Mask. +// +// Forms: +// +// PCMPESTRM imm8 m128 xmm +// PCMPESTRM imm8 xmm xmm +func PCMPESTRM(i, mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPCMPESTRM.Forms(), sffxs{}, []operand.Op{i, mx, x}) +} + +// PCMPGTB: Compare Packed Signed Byte Integers for Greater Than. +// +// Forms: +// +// PCMPGTB m128 xmm +// PCMPGTB xmm xmm +func PCMPGTB(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPCMPGTB.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PCMPGTL: Compare Packed Signed Doubleword Integers for Greater Than. +// +// Forms: +// +// PCMPGTL m128 xmm +// PCMPGTL xmm xmm +func PCMPGTL(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPCMPGTL.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PCMPGTQ: Compare Packed Data for Greater Than. +// +// Forms: +// +// PCMPGTQ m128 xmm +// PCMPGTQ xmm xmm +func PCMPGTQ(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPCMPGTQ.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PCMPGTW: Compare Packed Signed Word Integers for Greater Than. +// +// Forms: +// +// PCMPGTW m128 xmm +// PCMPGTW xmm xmm +func PCMPGTW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPCMPGTW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PCMPISTRI: Packed Compare Implicit Length Strings, Return Index. +// +// Forms: +// +// PCMPISTRI imm8 m128 xmm +// PCMPISTRI imm8 xmm xmm +func PCMPISTRI(i, mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPCMPISTRI.Forms(), sffxs{}, []operand.Op{i, mx, x}) +} + +// PCMPISTRM: Packed Compare Implicit Length Strings, Return Mask. +// +// Forms: +// +// PCMPISTRM imm8 m128 xmm +// PCMPISTRM imm8 xmm xmm +func PCMPISTRM(i, mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPCMPISTRM.Forms(), sffxs{}, []operand.Op{i, mx, x}) +} + +// PDEPL: Parallel Bits Deposit. +// +// Forms: +// +// PDEPL m32 r32 r32 +// PDEPL r32 r32 r32 +func PDEPL(mr, r, r1 operand.Op) (*intrep.Instruction, error) { + return build(opcPDEPL.Forms(), sffxs{}, []operand.Op{mr, r, r1}) +} + +// PDEPQ: Parallel Bits Deposit. +// +// Forms: +// +// PDEPQ m64 r64 r64 +// PDEPQ r64 r64 r64 +func PDEPQ(mr, r, r1 operand.Op) (*intrep.Instruction, error) { + return build(opcPDEPQ.Forms(), sffxs{}, []operand.Op{mr, r, r1}) +} + +// PEXTL: Parallel Bits Extract. +// +// Forms: +// +// PEXTL m32 r32 r32 +// PEXTL r32 r32 r32 +func PEXTL(mr, r, r1 operand.Op) (*intrep.Instruction, error) { + return build(opcPEXTL.Forms(), sffxs{}, []operand.Op{mr, r, r1}) +} + +// PEXTQ: Parallel Bits Extract. +// +// Forms: +// +// PEXTQ m64 r64 r64 +// PEXTQ r64 r64 r64 +func PEXTQ(mr, r, r1 operand.Op) (*intrep.Instruction, error) { + return build(opcPEXTQ.Forms(), sffxs{}, []operand.Op{mr, r, r1}) +} + +// PEXTRB: Extract Byte. +// +// Forms: +// +// PEXTRB imm8 xmm m8 +// PEXTRB imm8 xmm r32 +func PEXTRB(i, x, mr operand.Op) (*intrep.Instruction, error) { + return build(opcPEXTRB.Forms(), sffxs{}, []operand.Op{i, x, mr}) +} + +// PEXTRD: Extract Doubleword. +// +// Forms: +// +// PEXTRD imm8 xmm m32 +// PEXTRD imm8 xmm r32 +func PEXTRD(i, x, mr operand.Op) (*intrep.Instruction, error) { + return build(opcPEXTRD.Forms(), sffxs{}, []operand.Op{i, x, mr}) +} + +// PEXTRQ: Extract Quadword. +// +// Forms: +// +// PEXTRQ imm8 xmm m64 +// PEXTRQ imm8 xmm r64 +func PEXTRQ(i, x, mr operand.Op) (*intrep.Instruction, error) { + return build(opcPEXTRQ.Forms(), sffxs{}, []operand.Op{i, x, mr}) +} + +// PEXTRW: Extract Word. +// +// Forms: +// +// PEXTRW imm8 xmm m16 +// PEXTRW imm8 xmm r32 +func PEXTRW(i, x, mr operand.Op) (*intrep.Instruction, error) { + return build(opcPEXTRW.Forms(), sffxs{}, []operand.Op{i, x, mr}) +} + +// PHADDD: Packed Horizontal Add Doubleword Integer. +// +// Forms: +// +// PHADDD m128 xmm +// PHADDD xmm xmm +func PHADDD(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPHADDD.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PHADDSW: Packed Horizontal Add Signed Word Integers with Signed Saturation. +// +// Forms: +// +// PHADDSW m128 xmm +// PHADDSW xmm xmm +func PHADDSW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPHADDSW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PHADDW: Packed Horizontal Add Word Integers. +// +// Forms: +// +// PHADDW m128 xmm +// PHADDW xmm xmm +func PHADDW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPHADDW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PHMINPOSUW: Packed Horizontal Minimum of Unsigned Word Integers. +// +// Forms: +// +// PHMINPOSUW m128 xmm +// PHMINPOSUW xmm xmm +func PHMINPOSUW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPHMINPOSUW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PHSUBD: Packed Horizontal Subtract Doubleword Integers. +// +// Forms: +// +// PHSUBD m128 xmm +// PHSUBD xmm xmm +func PHSUBD(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPHSUBD.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PHSUBSW: Packed Horizontal Subtract Signed Word Integers with Signed Saturation. +// +// Forms: +// +// PHSUBSW m128 xmm +// PHSUBSW xmm xmm +func PHSUBSW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPHSUBSW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PHSUBW: Packed Horizontal Subtract Word Integers. +// +// Forms: +// +// PHSUBW m128 xmm +// PHSUBW xmm xmm +func PHSUBW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPHSUBW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PINSRB: Insert Byte. +// +// Forms: +// +// PINSRB imm8 m8 xmm +// PINSRB imm8 r32 xmm +func PINSRB(i, mr, x operand.Op) (*intrep.Instruction, error) { + return build(opcPINSRB.Forms(), sffxs{}, []operand.Op{i, mr, x}) +} + +// PINSRD: Insert Doubleword. +// +// Forms: +// +// PINSRD imm8 m32 xmm +// PINSRD imm8 r32 xmm +func PINSRD(i, mr, x operand.Op) (*intrep.Instruction, error) { + return build(opcPINSRD.Forms(), sffxs{}, []operand.Op{i, mr, x}) +} + +// PINSRQ: Insert Quadword. +// +// Forms: +// +// PINSRQ imm8 m64 xmm +// PINSRQ imm8 r64 xmm +func PINSRQ(i, mr, x operand.Op) (*intrep.Instruction, error) { + return build(opcPINSRQ.Forms(), sffxs{}, []operand.Op{i, mr, x}) +} + +// PINSRW: Insert Word. +// +// Forms: +// +// PINSRW imm8 m16 xmm +// PINSRW imm8 r32 xmm +func PINSRW(i, mr, x operand.Op) (*intrep.Instruction, error) { + return build(opcPINSRW.Forms(), sffxs{}, []operand.Op{i, mr, x}) +} + +// PMADDUBSW: Multiply and Add Packed Signed and Unsigned Byte Integers. +// +// Forms: +// +// PMADDUBSW m128 xmm +// PMADDUBSW xmm xmm +func PMADDUBSW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMADDUBSW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMADDWL: Multiply and Add Packed Signed Word Integers. +// +// Forms: +// +// PMADDWL m128 xmm +// PMADDWL xmm xmm +func PMADDWL(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMADDWL.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMAXSB: Maximum of Packed Signed Byte Integers. +// +// Forms: +// +// PMAXSB m128 xmm +// PMAXSB xmm xmm +func PMAXSB(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMAXSB.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMAXSD: Maximum of Packed Signed Doubleword Integers. +// +// Forms: +// +// PMAXSD m128 xmm +// PMAXSD xmm xmm +func PMAXSD(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMAXSD.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMAXSW: Maximum of Packed Signed Word Integers. +// +// Forms: +// +// PMAXSW m128 xmm +// PMAXSW xmm xmm +func PMAXSW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMAXSW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMAXUB: Maximum of Packed Unsigned Byte Integers. +// +// Forms: +// +// PMAXUB m128 xmm +// PMAXUB xmm xmm +func PMAXUB(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMAXUB.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMAXUD: Maximum of Packed Unsigned Doubleword Integers. +// +// Forms: +// +// PMAXUD m128 xmm +// PMAXUD xmm xmm +func PMAXUD(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMAXUD.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMAXUW: Maximum of Packed Unsigned Word Integers. +// +// Forms: +// +// PMAXUW m128 xmm +// PMAXUW xmm xmm +func PMAXUW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMAXUW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMINSB: Minimum of Packed Signed Byte Integers. +// +// Forms: +// +// PMINSB m128 xmm +// PMINSB xmm xmm +func PMINSB(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMINSB.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMINSD: Minimum of Packed Signed Doubleword Integers. +// +// Forms: +// +// PMINSD m128 xmm +// PMINSD xmm xmm +func PMINSD(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMINSD.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMINSW: Minimum of Packed Signed Word Integers. +// +// Forms: +// +// PMINSW m128 xmm +// PMINSW xmm xmm +func PMINSW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMINSW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMINUB: Minimum of Packed Unsigned Byte Integers. +// +// Forms: +// +// PMINUB m128 xmm +// PMINUB xmm xmm +func PMINUB(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMINUB.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMINUD: Minimum of Packed Unsigned Doubleword Integers. +// +// Forms: +// +// PMINUD m128 xmm +// PMINUD xmm xmm +func PMINUD(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMINUD.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMINUW: Minimum of Packed Unsigned Word Integers. +// +// Forms: +// +// PMINUW m128 xmm +// PMINUW xmm xmm +func PMINUW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMINUW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMOVMSKB: Move Byte Mask. +// +// Forms: +// +// PMOVMSKB xmm r32 +func PMOVMSKB(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcPMOVMSKB.Forms(), sffxs{}, []operand.Op{x, r}) +} + +// PMOVSXBD: Move Packed Byte Integers to Doubleword Integers with Sign Extension. +// +// Forms: +// +// PMOVSXBD m32 xmm +// PMOVSXBD xmm xmm +func PMOVSXBD(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMOVSXBD.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMOVSXBQ: Move Packed Byte Integers to Quadword Integers with Sign Extension. +// +// Forms: +// +// PMOVSXBQ m16 xmm +// PMOVSXBQ xmm xmm +func PMOVSXBQ(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMOVSXBQ.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMOVSXBW: Move Packed Byte Integers to Word Integers with Sign Extension. +// +// Forms: +// +// PMOVSXBW m64 xmm +// PMOVSXBW xmm xmm +func PMOVSXBW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMOVSXBW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMOVSXDQ: Move Packed Doubleword Integers to Quadword Integers with Sign Extension. +// +// Forms: +// +// PMOVSXDQ m64 xmm +// PMOVSXDQ xmm xmm +func PMOVSXDQ(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMOVSXDQ.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMOVSXWD: Move Packed Word Integers to Doubleword Integers with Sign Extension. +// +// Forms: +// +// PMOVSXWD m64 xmm +// PMOVSXWD xmm xmm +func PMOVSXWD(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMOVSXWD.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMOVSXWQ: Move Packed Word Integers to Quadword Integers with Sign Extension. +// +// Forms: +// +// PMOVSXWQ m32 xmm +// PMOVSXWQ xmm xmm +func PMOVSXWQ(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMOVSXWQ.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMOVZXBD: Move Packed Byte Integers to Doubleword Integers with Zero Extension. +// +// Forms: +// +// PMOVZXBD m32 xmm +// PMOVZXBD xmm xmm +func PMOVZXBD(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMOVZXBD.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMOVZXBQ: Move Packed Byte Integers to Quadword Integers with Zero Extension. +// +// Forms: +// +// PMOVZXBQ m16 xmm +// PMOVZXBQ xmm xmm +func PMOVZXBQ(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMOVZXBQ.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMOVZXBW: Move Packed Byte Integers to Word Integers with Zero Extension. +// +// Forms: +// +// PMOVZXBW m64 xmm +// PMOVZXBW xmm xmm +func PMOVZXBW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMOVZXBW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMOVZXDQ: Move Packed Doubleword Integers to Quadword Integers with Zero Extension. +// +// Forms: +// +// PMOVZXDQ m64 xmm +// PMOVZXDQ xmm xmm +func PMOVZXDQ(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMOVZXDQ.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMOVZXWD: Move Packed Word Integers to Doubleword Integers with Zero Extension. +// +// Forms: +// +// PMOVZXWD m64 xmm +// PMOVZXWD xmm xmm +func PMOVZXWD(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMOVZXWD.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMOVZXWQ: Move Packed Word Integers to Quadword Integers with Zero Extension. +// +// Forms: +// +// PMOVZXWQ m32 xmm +// PMOVZXWQ xmm xmm +func PMOVZXWQ(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMOVZXWQ.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMULDQ: Multiply Packed Signed Doubleword Integers and Store Quadword Result. +// +// Forms: +// +// PMULDQ m128 xmm +// PMULDQ xmm xmm +func PMULDQ(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMULDQ.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMULHRSW: Packed Multiply Signed Word Integers and Store High Result with Round and Scale. +// +// Forms: +// +// PMULHRSW m128 xmm +// PMULHRSW xmm xmm +func PMULHRSW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMULHRSW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMULHUW: Multiply Packed Unsigned Word Integers and Store High Result. +// +// Forms: +// +// PMULHUW m128 xmm +// PMULHUW xmm xmm +func PMULHUW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMULHUW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMULHW: Multiply Packed Signed Word Integers and Store High Result. +// +// Forms: +// +// PMULHW m128 xmm +// PMULHW xmm xmm +func PMULHW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMULHW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMULLD: Multiply Packed Signed Doubleword Integers and Store Low Result. +// +// Forms: +// +// PMULLD m128 xmm +// PMULLD xmm xmm +func PMULLD(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMULLD.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMULLW: Multiply Packed Signed Word Integers and Store Low Result. +// +// Forms: +// +// PMULLW m128 xmm +// PMULLW xmm xmm +func PMULLW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMULLW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PMULULQ: Multiply Packed Unsigned Doubleword Integers. +// +// Forms: +// +// PMULULQ m128 xmm +// PMULULQ xmm xmm +func PMULULQ(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPMULULQ.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// POPCNTL: Count of Number of Bits Set to 1. +// +// Forms: +// +// POPCNTL m32 r32 +// POPCNTL r32 r32 +func POPCNTL(mr, r operand.Op) (*intrep.Instruction, error) { + return build(opcPOPCNTL.Forms(), sffxs{}, []operand.Op{mr, r}) +} + +// POPCNTQ: Count of Number of Bits Set to 1. +// +// Forms: +// +// POPCNTQ m64 r64 +// POPCNTQ r64 r64 +func POPCNTQ(mr, r operand.Op) (*intrep.Instruction, error) { + return build(opcPOPCNTQ.Forms(), sffxs{}, []operand.Op{mr, r}) +} + +// POPCNTW: Count of Number of Bits Set to 1. +// +// Forms: +// +// POPCNTW m16 r16 +// POPCNTW r16 r16 +func POPCNTW(mr, r operand.Op) (*intrep.Instruction, error) { + return build(opcPOPCNTW.Forms(), sffxs{}, []operand.Op{mr, r}) +} + +// POPQ: Pop a Value from the Stack. +// +// Forms: +// +// POPQ m64 +// POPQ r64 +func POPQ(mr operand.Op) (*intrep.Instruction, error) { + return build(opcPOPQ.Forms(), sffxs{}, []operand.Op{mr}) +} + +// POPW: Pop a Value from the Stack. +// +// Forms: +// +// POPW m16 +// POPW r16 +func POPW(mr operand.Op) (*intrep.Instruction, error) { + return build(opcPOPW.Forms(), sffxs{}, []operand.Op{mr}) +} + +// POR: Packed Bitwise Logical OR. +// +// Forms: +// +// POR m128 xmm +// POR xmm xmm +func POR(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPOR.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PREFETCHNTA: Prefetch Data Into Caches using NTA Hint. +// +// Forms: +// +// PREFETCHNTA m8 +func PREFETCHNTA(m operand.Op) (*intrep.Instruction, error) { + return build(opcPREFETCHNTA.Forms(), sffxs{}, []operand.Op{m}) +} + +// PREFETCHT0: Prefetch Data Into Caches using T0 Hint. +// +// Forms: +// +// PREFETCHT0 m8 +func PREFETCHT0(m operand.Op) (*intrep.Instruction, error) { + return build(opcPREFETCHT0.Forms(), sffxs{}, []operand.Op{m}) +} + +// PREFETCHT1: Prefetch Data Into Caches using T1 Hint. +// +// Forms: +// +// PREFETCHT1 m8 +func PREFETCHT1(m operand.Op) (*intrep.Instruction, error) { + return build(opcPREFETCHT1.Forms(), sffxs{}, []operand.Op{m}) +} + +// PREFETCHT2: Prefetch Data Into Caches using T2 Hint. +// +// Forms: +// +// PREFETCHT2 m8 +func PREFETCHT2(m operand.Op) (*intrep.Instruction, error) { + return build(opcPREFETCHT2.Forms(), sffxs{}, []operand.Op{m}) +} + +// PSADBW: Compute Sum of Absolute Differences. +// +// Forms: +// +// PSADBW m128 xmm +// PSADBW xmm xmm +func PSADBW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPSADBW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PSHUFB: Packed Shuffle Bytes. +// +// Forms: +// +// PSHUFB m128 xmm +// PSHUFB xmm xmm +func PSHUFB(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPSHUFB.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PSHUFD: Shuffle Packed Doublewords. +// +// Forms: +// +// PSHUFD imm8 m128 xmm +// PSHUFD imm8 xmm xmm +func PSHUFD(i, mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPSHUFD.Forms(), sffxs{}, []operand.Op{i, mx, x}) +} + +// PSHUFHW: Shuffle Packed High Words. +// +// Forms: +// +// PSHUFHW imm8 m128 xmm +// PSHUFHW imm8 xmm xmm +func PSHUFHW(i, mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPSHUFHW.Forms(), sffxs{}, []operand.Op{i, mx, x}) +} + +// PSHUFL: Shuffle Packed Doublewords. +// +// Forms: +// +// PSHUFL imm8 m128 xmm +// PSHUFL imm8 xmm xmm +func PSHUFL(i, mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPSHUFL.Forms(), sffxs{}, []operand.Op{i, mx, x}) +} + +// PSHUFLW: Shuffle Packed Low Words. +// +// Forms: +// +// PSHUFLW imm8 m128 xmm +// PSHUFLW imm8 xmm xmm +func PSHUFLW(i, mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPSHUFLW.Forms(), sffxs{}, []operand.Op{i, mx, x}) +} + +// PSIGNB: Packed Sign of Byte Integers. +// +// Forms: +// +// PSIGNB m128 xmm +// PSIGNB xmm xmm +func PSIGNB(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPSIGNB.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PSIGND: Packed Sign of Doubleword Integers. +// +// Forms: +// +// PSIGND m128 xmm +// PSIGND xmm xmm +func PSIGND(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPSIGND.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PSIGNW: Packed Sign of Word Integers. +// +// Forms: +// +// PSIGNW m128 xmm +// PSIGNW xmm xmm +func PSIGNW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPSIGNW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PSLLDQ: Shift Packed Double Quadword Left Logical. +// +// Forms: +// +// PSLLDQ imm8 xmm +func PSLLDQ(i, x operand.Op) (*intrep.Instruction, error) { + return build(opcPSLLDQ.Forms(), sffxs{}, []operand.Op{i, x}) +} + +// PSLLL: Shift Packed Doubleword Data Left Logical. +// +// Forms: +// +// PSLLL imm8 xmm +// PSLLL m128 xmm +// PSLLL xmm xmm +func PSLLL(imx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPSLLL.Forms(), sffxs{}, []operand.Op{imx, x}) +} + +// PSLLO: Shift Packed Double Quadword Left Logical. +// +// Forms: +// +// PSLLO imm8 xmm +func PSLLO(i, x operand.Op) (*intrep.Instruction, error) { + return build(opcPSLLO.Forms(), sffxs{}, []operand.Op{i, x}) +} + +// PSLLQ: Shift Packed Quadword Data Left Logical. +// +// Forms: +// +// PSLLQ imm8 xmm +// PSLLQ m128 xmm +// PSLLQ xmm xmm +func PSLLQ(imx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPSLLQ.Forms(), sffxs{}, []operand.Op{imx, x}) +} + +// PSLLW: Shift Packed Word Data Left Logical. +// +// Forms: +// +// PSLLW imm8 xmm +// PSLLW m128 xmm +// PSLLW xmm xmm +func PSLLW(imx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPSLLW.Forms(), sffxs{}, []operand.Op{imx, x}) +} + +// PSRAL: Shift Packed Doubleword Data Right Arithmetic. +// +// Forms: +// +// PSRAL imm8 xmm +// PSRAL m128 xmm +// PSRAL xmm xmm +func PSRAL(imx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPSRAL.Forms(), sffxs{}, []operand.Op{imx, x}) +} + +// PSRAW: Shift Packed Word Data Right Arithmetic. +// +// Forms: +// +// PSRAW imm8 xmm +// PSRAW m128 xmm +// PSRAW xmm xmm +func PSRAW(imx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPSRAW.Forms(), sffxs{}, []operand.Op{imx, x}) +} + +// PSRLDQ: Shift Packed Double Quadword Right Logical. +// +// Forms: +// +// PSRLDQ imm8 xmm +func PSRLDQ(i, x operand.Op) (*intrep.Instruction, error) { + return build(opcPSRLDQ.Forms(), sffxs{}, []operand.Op{i, x}) +} + +// PSRLL: Shift Packed Doubleword Data Right Logical. +// +// Forms: +// +// PSRLL imm8 xmm +// PSRLL m128 xmm +// PSRLL xmm xmm +func PSRLL(imx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPSRLL.Forms(), sffxs{}, []operand.Op{imx, x}) +} + +// PSRLO: Shift Packed Double Quadword Right Logical. +// +// Forms: +// +// PSRLO imm8 xmm +func PSRLO(i, x operand.Op) (*intrep.Instruction, error) { + return build(opcPSRLO.Forms(), sffxs{}, []operand.Op{i, x}) +} + +// PSRLQ: Shift Packed Quadword Data Right Logical. +// +// Forms: +// +// PSRLQ imm8 xmm +// PSRLQ m128 xmm +// PSRLQ xmm xmm +func PSRLQ(imx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPSRLQ.Forms(), sffxs{}, []operand.Op{imx, x}) +} + +// PSRLW: Shift Packed Word Data Right Logical. +// +// Forms: +// +// PSRLW imm8 xmm +// PSRLW m128 xmm +// PSRLW xmm xmm +func PSRLW(imx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPSRLW.Forms(), sffxs{}, []operand.Op{imx, x}) +} + +// PSUBB: Subtract Packed Byte Integers. +// +// Forms: +// +// PSUBB m128 xmm +// PSUBB xmm xmm +func PSUBB(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPSUBB.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PSUBL: Subtract Packed Doubleword Integers. +// +// Forms: +// +// PSUBL m128 xmm +// PSUBL xmm xmm +func PSUBL(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPSUBL.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PSUBQ: Subtract Packed Quadword Integers. +// +// Forms: +// +// PSUBQ m128 xmm +// PSUBQ xmm xmm +func PSUBQ(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPSUBQ.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PSUBSB: Subtract Packed Signed Byte Integers with Signed Saturation. +// +// Forms: +// +// PSUBSB m128 xmm +// PSUBSB xmm xmm +func PSUBSB(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPSUBSB.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PSUBSW: Subtract Packed Signed Word Integers with Signed Saturation. +// +// Forms: +// +// PSUBSW m128 xmm +// PSUBSW xmm xmm +func PSUBSW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPSUBSW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PSUBUSB: Subtract Packed Unsigned Byte Integers with Unsigned Saturation. +// +// Forms: +// +// PSUBUSB m128 xmm +// PSUBUSB xmm xmm +func PSUBUSB(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPSUBUSB.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PSUBUSW: Subtract Packed Unsigned Word Integers with Unsigned Saturation. +// +// Forms: +// +// PSUBUSW m128 xmm +// PSUBUSW xmm xmm +func PSUBUSW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPSUBUSW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PSUBW: Subtract Packed Word Integers. +// +// Forms: +// +// PSUBW m128 xmm +// PSUBW xmm xmm +func PSUBW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPSUBW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PTEST: Packed Logical Compare. +// +// Forms: +// +// PTEST m128 xmm +// PTEST xmm xmm +func PTEST(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPTEST.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PUNPCKHBW: Unpack and Interleave High-Order Bytes into Words. +// +// Forms: +// +// PUNPCKHBW m128 xmm +// PUNPCKHBW xmm xmm +func PUNPCKHBW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPUNPCKHBW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PUNPCKHLQ: Unpack and Interleave High-Order Doublewords into Quadwords. +// +// Forms: +// +// PUNPCKHLQ m128 xmm +// PUNPCKHLQ xmm xmm +func PUNPCKHLQ(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPUNPCKHLQ.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PUNPCKHQDQ: Unpack and Interleave High-Order Quadwords into Double Quadwords. +// +// Forms: +// +// PUNPCKHQDQ m128 xmm +// PUNPCKHQDQ xmm xmm +func PUNPCKHQDQ(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPUNPCKHQDQ.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PUNPCKHWL: Unpack and Interleave High-Order Words into Doublewords. +// +// Forms: +// +// PUNPCKHWL m128 xmm +// PUNPCKHWL xmm xmm +func PUNPCKHWL(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPUNPCKHWL.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PUNPCKLBW: Unpack and Interleave Low-Order Bytes into Words. +// +// Forms: +// +// PUNPCKLBW m128 xmm +// PUNPCKLBW xmm xmm +func PUNPCKLBW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPUNPCKLBW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PUNPCKLLQ: Unpack and Interleave Low-Order Doublewords into Quadwords. +// +// Forms: +// +// PUNPCKLLQ m128 xmm +// PUNPCKLLQ xmm xmm +func PUNPCKLLQ(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPUNPCKLLQ.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PUNPCKLQDQ: Unpack and Interleave Low-Order Quadwords into Double Quadwords. +// +// Forms: +// +// PUNPCKLQDQ m128 xmm +// PUNPCKLQDQ xmm xmm +func PUNPCKLQDQ(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPUNPCKLQDQ.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PUNPCKLWL: Unpack and Interleave Low-Order Words into Doublewords. +// +// Forms: +// +// PUNPCKLWL m128 xmm +// PUNPCKLWL xmm xmm +func PUNPCKLWL(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPUNPCKLWL.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// PUSHQ: Push Value Onto the Stack. +// +// Forms: +// +// PUSHQ imm32 +// PUSHQ imm8 +// PUSHQ m64 +// PUSHQ r64 +func PUSHQ(imr operand.Op) (*intrep.Instruction, error) { + return build(opcPUSHQ.Forms(), sffxs{}, []operand.Op{imr}) +} + +// PUSHW: Push Value Onto the Stack. +// +// Forms: +// +// PUSHW m16 +// PUSHW r16 +func PUSHW(mr operand.Op) (*intrep.Instruction, error) { + return build(opcPUSHW.Forms(), sffxs{}, []operand.Op{mr}) +} + +// PXOR: Packed Bitwise Logical Exclusive OR. +// +// Forms: +// +// PXOR m128 xmm +// PXOR xmm xmm +func PXOR(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcPXOR.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// RCLB: Rotate Left through Carry Flag. +// +// Forms: +// +// RCLB 1 m8 +// RCLB 1 r8 +// RCLB cl m8 +// RCLB cl r8 +// RCLB imm8 m8 +// RCLB imm8 r8 +func RCLB(ci, mr operand.Op) (*intrep.Instruction, error) { + return build(opcRCLB.Forms(), sffxs{}, []operand.Op{ci, mr}) +} + +// RCLL: Rotate Left through Carry Flag. +// +// Forms: +// +// RCLL 1 m32 +// RCLL 1 r32 +// RCLL cl m32 +// RCLL cl r32 +// RCLL imm8 m32 +// RCLL imm8 r32 +func RCLL(ci, mr operand.Op) (*intrep.Instruction, error) { + return build(opcRCLL.Forms(), sffxs{}, []operand.Op{ci, mr}) +} + +// RCLQ: Rotate Left through Carry Flag. +// +// Forms: +// +// RCLQ 1 m64 +// RCLQ 1 r64 +// RCLQ cl m64 +// RCLQ cl r64 +// RCLQ imm8 m64 +// RCLQ imm8 r64 +func RCLQ(ci, mr operand.Op) (*intrep.Instruction, error) { + return build(opcRCLQ.Forms(), sffxs{}, []operand.Op{ci, mr}) +} + +// RCLW: Rotate Left through Carry Flag. +// +// Forms: +// +// RCLW 1 m16 +// RCLW 1 r16 +// RCLW cl m16 +// RCLW cl r16 +// RCLW imm8 m16 +// RCLW imm8 r16 +func RCLW(ci, mr operand.Op) (*intrep.Instruction, error) { + return build(opcRCLW.Forms(), sffxs{}, []operand.Op{ci, mr}) +} + +// RCPPS: Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// RCPPS m128 xmm +// RCPPS xmm xmm +func RCPPS(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcRCPPS.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// RCPSS: Compute Approximate Reciprocal of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// RCPSS m32 xmm +// RCPSS xmm xmm +func RCPSS(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcRCPSS.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// RCRB: Rotate Right through Carry Flag. +// +// Forms: +// +// RCRB 1 m8 +// RCRB 1 r8 +// RCRB cl m8 +// RCRB cl r8 +// RCRB imm8 m8 +// RCRB imm8 r8 +func RCRB(ci, mr operand.Op) (*intrep.Instruction, error) { + return build(opcRCRB.Forms(), sffxs{}, []operand.Op{ci, mr}) +} + +// RCRL: Rotate Right through Carry Flag. +// +// Forms: +// +// RCRL 1 m32 +// RCRL 1 r32 +// RCRL cl m32 +// RCRL cl r32 +// RCRL imm8 m32 +// RCRL imm8 r32 +func RCRL(ci, mr operand.Op) (*intrep.Instruction, error) { + return build(opcRCRL.Forms(), sffxs{}, []operand.Op{ci, mr}) +} + +// RCRQ: Rotate Right through Carry Flag. +// +// Forms: +// +// RCRQ 1 m64 +// RCRQ 1 r64 +// RCRQ cl m64 +// RCRQ cl r64 +// RCRQ imm8 m64 +// RCRQ imm8 r64 +func RCRQ(ci, mr operand.Op) (*intrep.Instruction, error) { + return build(opcRCRQ.Forms(), sffxs{}, []operand.Op{ci, mr}) +} + +// RCRW: Rotate Right through Carry Flag. +// +// Forms: +// +// RCRW 1 m16 +// RCRW 1 r16 +// RCRW cl m16 +// RCRW cl r16 +// RCRW imm8 m16 +// RCRW imm8 r16 +func RCRW(ci, mr operand.Op) (*intrep.Instruction, error) { + return build(opcRCRW.Forms(), sffxs{}, []operand.Op{ci, mr}) +} + +// RDRANDL: Read Random Number. +// +// Forms: +// +// RDRANDL r16 +// RDRANDL r32 +// RDRANDL r64 +func RDRANDL(r operand.Op) (*intrep.Instruction, error) { + return build(opcRDRANDL.Forms(), sffxs{}, []operand.Op{r}) +} + +// RDSEEDL: Read Random SEED. +// +// Forms: +// +// RDSEEDL r16 +// RDSEEDL r32 +// RDSEEDL r64 +func RDSEEDL(r operand.Op) (*intrep.Instruction, error) { + return build(opcRDSEEDL.Forms(), sffxs{}, []operand.Op{r}) +} + +// RDTSC: Read Time-Stamp Counter. +// +// Forms: +// +// RDTSC +func RDTSC() (*intrep.Instruction, error) { + return build(opcRDTSC.Forms(), sffxs{}, []operand.Op{}) +} + +// RDTSCP: Read Time-Stamp Counter and Processor ID. +// +// Forms: +// +// RDTSCP +func RDTSCP() (*intrep.Instruction, error) { + return build(opcRDTSCP.Forms(), sffxs{}, []operand.Op{}) +} + +// RET: Return from Procedure. +// +// Forms: +// +// RET +func RET() (*intrep.Instruction, error) { + return build(opcRET.Forms(), sffxs{}, []operand.Op{}) +} + +// RETFL: Return from Procedure. +// +// Forms: +// +// RETFL imm16 +func RETFL(i operand.Op) (*intrep.Instruction, error) { + return build(opcRETFL.Forms(), sffxs{}, []operand.Op{i}) +} + +// RETFQ: Return from Procedure. +// +// Forms: +// +// RETFQ imm16 +func RETFQ(i operand.Op) (*intrep.Instruction, error) { + return build(opcRETFQ.Forms(), sffxs{}, []operand.Op{i}) +} + +// RETFW: Return from Procedure. +// +// Forms: +// +// RETFW imm16 +func RETFW(i operand.Op) (*intrep.Instruction, error) { + return build(opcRETFW.Forms(), sffxs{}, []operand.Op{i}) +} + +// ROLB: Rotate Left. +// +// Forms: +// +// ROLB 1 m8 +// ROLB 1 r8 +// ROLB cl m8 +// ROLB cl r8 +// ROLB imm8 m8 +// ROLB imm8 r8 +func ROLB(ci, mr operand.Op) (*intrep.Instruction, error) { + return build(opcROLB.Forms(), sffxs{}, []operand.Op{ci, mr}) +} + +// ROLL: Rotate Left. +// +// Forms: +// +// ROLL 1 m32 +// ROLL 1 r32 +// ROLL cl m32 +// ROLL cl r32 +// ROLL imm8 m32 +// ROLL imm8 r32 +func ROLL(ci, mr operand.Op) (*intrep.Instruction, error) { + return build(opcROLL.Forms(), sffxs{}, []operand.Op{ci, mr}) +} + +// ROLQ: Rotate Left. +// +// Forms: +// +// ROLQ 1 m64 +// ROLQ 1 r64 +// ROLQ cl m64 +// ROLQ cl r64 +// ROLQ imm8 m64 +// ROLQ imm8 r64 +func ROLQ(ci, mr operand.Op) (*intrep.Instruction, error) { + return build(opcROLQ.Forms(), sffxs{}, []operand.Op{ci, mr}) +} + +// ROLW: Rotate Left. +// +// Forms: +// +// ROLW 1 m16 +// ROLW 1 r16 +// ROLW cl m16 +// ROLW cl r16 +// ROLW imm8 m16 +// ROLW imm8 r16 +func ROLW(ci, mr operand.Op) (*intrep.Instruction, error) { + return build(opcROLW.Forms(), sffxs{}, []operand.Op{ci, mr}) +} + +// RORB: Rotate Right. +// +// Forms: +// +// RORB 1 m8 +// RORB 1 r8 +// RORB cl m8 +// RORB cl r8 +// RORB imm8 m8 +// RORB imm8 r8 +func RORB(ci, mr operand.Op) (*intrep.Instruction, error) { + return build(opcRORB.Forms(), sffxs{}, []operand.Op{ci, mr}) +} + +// RORL: Rotate Right. +// +// Forms: +// +// RORL 1 m32 +// RORL 1 r32 +// RORL cl m32 +// RORL cl r32 +// RORL imm8 m32 +// RORL imm8 r32 +func RORL(ci, mr operand.Op) (*intrep.Instruction, error) { + return build(opcRORL.Forms(), sffxs{}, []operand.Op{ci, mr}) +} + +// RORQ: Rotate Right. +// +// Forms: +// +// RORQ 1 m64 +// RORQ 1 r64 +// RORQ cl m64 +// RORQ cl r64 +// RORQ imm8 m64 +// RORQ imm8 r64 +func RORQ(ci, mr operand.Op) (*intrep.Instruction, error) { + return build(opcRORQ.Forms(), sffxs{}, []operand.Op{ci, mr}) +} + +// RORW: Rotate Right. +// +// Forms: +// +// RORW 1 m16 +// RORW 1 r16 +// RORW cl m16 +// RORW cl r16 +// RORW imm8 m16 +// RORW imm8 r16 +func RORW(ci, mr operand.Op) (*intrep.Instruction, error) { + return build(opcRORW.Forms(), sffxs{}, []operand.Op{ci, mr}) +} + +// RORXL: Rotate Right Logical Without Affecting Flags. +// +// Forms: +// +// RORXL imm8 m32 r32 +// RORXL imm8 r32 r32 +func RORXL(i, mr, r operand.Op) (*intrep.Instruction, error) { + return build(opcRORXL.Forms(), sffxs{}, []operand.Op{i, mr, r}) +} + +// RORXQ: Rotate Right Logical Without Affecting Flags. +// +// Forms: +// +// RORXQ imm8 m64 r64 +// RORXQ imm8 r64 r64 +func RORXQ(i, mr, r operand.Op) (*intrep.Instruction, error) { + return build(opcRORXQ.Forms(), sffxs{}, []operand.Op{i, mr, r}) +} + +// ROUNDPD: Round Packed Double Precision Floating-Point Values. +// +// Forms: +// +// ROUNDPD imm8 m128 xmm +// ROUNDPD imm8 xmm xmm +func ROUNDPD(i, mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcROUNDPD.Forms(), sffxs{}, []operand.Op{i, mx, x}) +} + +// ROUNDPS: Round Packed Single Precision Floating-Point Values. +// +// Forms: +// +// ROUNDPS imm8 m128 xmm +// ROUNDPS imm8 xmm xmm +func ROUNDPS(i, mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcROUNDPS.Forms(), sffxs{}, []operand.Op{i, mx, x}) +} + +// ROUNDSD: Round Scalar Double Precision Floating-Point Values. +// +// Forms: +// +// ROUNDSD imm8 m64 xmm +// ROUNDSD imm8 xmm xmm +func ROUNDSD(i, mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcROUNDSD.Forms(), sffxs{}, []operand.Op{i, mx, x}) +} + +// ROUNDSS: Round Scalar Single Precision Floating-Point Values. +// +// Forms: +// +// ROUNDSS imm8 m32 xmm +// ROUNDSS imm8 xmm xmm +func ROUNDSS(i, mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcROUNDSS.Forms(), sffxs{}, []operand.Op{i, mx, x}) +} + +// RSQRTPS: Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// RSQRTPS m128 xmm +// RSQRTPS xmm xmm +func RSQRTPS(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcRSQRTPS.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// RSQRTSS: Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value. +// +// Forms: +// +// RSQRTSS m32 xmm +// RSQRTSS xmm xmm +func RSQRTSS(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcRSQRTSS.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// SALB: Arithmetic Shift Left. +// +// Forms: +// +// SALB 1 m8 +// SALB 1 r8 +// SALB cl m8 +// SALB cl r8 +// SALB imm8 m8 +// SALB imm8 r8 +func SALB(ci, mr operand.Op) (*intrep.Instruction, error) { + return build(opcSALB.Forms(), sffxs{}, []operand.Op{ci, mr}) +} + +// SALL: Arithmetic Shift Left. +// +// Forms: +// +// SALL 1 m32 +// SALL 1 r32 +// SALL cl m32 +// SALL cl r32 +// SALL imm8 m32 +// SALL imm8 r32 +func SALL(ci, mr operand.Op) (*intrep.Instruction, error) { + return build(opcSALL.Forms(), sffxs{}, []operand.Op{ci, mr}) +} + +// SALQ: Arithmetic Shift Left. +// +// Forms: +// +// SALQ 1 m64 +// SALQ 1 r64 +// SALQ cl m64 +// SALQ cl r64 +// SALQ imm8 m64 +// SALQ imm8 r64 +func SALQ(ci, mr operand.Op) (*intrep.Instruction, error) { + return build(opcSALQ.Forms(), sffxs{}, []operand.Op{ci, mr}) +} + +// SALW: Arithmetic Shift Left. +// +// Forms: +// +// SALW 1 m16 +// SALW 1 r16 +// SALW cl m16 +// SALW cl r16 +// SALW imm8 m16 +// SALW imm8 r16 +func SALW(ci, mr operand.Op) (*intrep.Instruction, error) { + return build(opcSALW.Forms(), sffxs{}, []operand.Op{ci, mr}) +} + +// SARB: Arithmetic Shift Right. +// +// Forms: +// +// SARB 1 m8 +// SARB 1 r8 +// SARB cl m8 +// SARB cl r8 +// SARB imm8 m8 +// SARB imm8 r8 +func SARB(ci, mr operand.Op) (*intrep.Instruction, error) { + return build(opcSARB.Forms(), sffxs{}, []operand.Op{ci, mr}) +} + +// SARL: Arithmetic Shift Right. +// +// Forms: +// +// SARL 1 m32 +// SARL 1 r32 +// SARL cl m32 +// SARL cl r32 +// SARL imm8 m32 +// SARL imm8 r32 +func SARL(ci, mr operand.Op) (*intrep.Instruction, error) { + return build(opcSARL.Forms(), sffxs{}, []operand.Op{ci, mr}) +} + +// SARQ: Arithmetic Shift Right. +// +// Forms: +// +// SARQ 1 m64 +// SARQ 1 r64 +// SARQ cl m64 +// SARQ cl r64 +// SARQ imm8 m64 +// SARQ imm8 r64 +func SARQ(ci, mr operand.Op) (*intrep.Instruction, error) { + return build(opcSARQ.Forms(), sffxs{}, []operand.Op{ci, mr}) +} + +// SARW: Arithmetic Shift Right. +// +// Forms: +// +// SARW 1 m16 +// SARW 1 r16 +// SARW cl m16 +// SARW cl r16 +// SARW imm8 m16 +// SARW imm8 r16 +func SARW(ci, mr operand.Op) (*intrep.Instruction, error) { + return build(opcSARW.Forms(), sffxs{}, []operand.Op{ci, mr}) +} + +// SARXL: Arithmetic Shift Right Without Affecting Flags. +// +// Forms: +// +// SARXL r32 m32 r32 +// SARXL r32 r32 r32 +func SARXL(r, mr, r1 operand.Op) (*intrep.Instruction, error) { + return build(opcSARXL.Forms(), sffxs{}, []operand.Op{r, mr, r1}) +} + +// SARXQ: Arithmetic Shift Right Without Affecting Flags. +// +// Forms: +// +// SARXQ r64 m64 r64 +// SARXQ r64 r64 r64 +func SARXQ(r, mr, r1 operand.Op) (*intrep.Instruction, error) { + return build(opcSARXQ.Forms(), sffxs{}, []operand.Op{r, mr, r1}) +} + +// SBBB: Subtract with Borrow. +// +// Forms: +// +// SBBB imm8 al +// SBBB imm8 m8 +// SBBB imm8 r8 +// SBBB m8 r8 +// SBBB r8 m8 +// SBBB r8 r8 +func SBBB(imr, amr operand.Op) (*intrep.Instruction, error) { + return build(opcSBBB.Forms(), sffxs{}, []operand.Op{imr, amr}) +} + +// SBBL: Subtract with Borrow. +// +// Forms: +// +// SBBL imm32 eax +// SBBL imm32 m32 +// SBBL imm32 r32 +// SBBL imm8 m32 +// SBBL imm8 r32 +// SBBL m32 r32 +// SBBL r32 m32 +// SBBL r32 r32 +func SBBL(imr, emr operand.Op) (*intrep.Instruction, error) { + return build(opcSBBL.Forms(), sffxs{}, []operand.Op{imr, emr}) +} + +// SBBQ: Subtract with Borrow. +// +// Forms: +// +// SBBQ imm32 m64 +// SBBQ imm32 r64 +// SBBQ imm32 rax +// SBBQ imm8 m64 +// SBBQ imm8 r64 +// SBBQ m64 r64 +// SBBQ r64 m64 +// SBBQ r64 r64 +func SBBQ(imr, mr operand.Op) (*intrep.Instruction, error) { + return build(opcSBBQ.Forms(), sffxs{}, []operand.Op{imr, mr}) +} + +// SBBW: Subtract with Borrow. +// +// Forms: +// +// SBBW imm16 ax +// SBBW imm16 m16 +// SBBW imm16 r16 +// SBBW imm8 m16 +// SBBW imm8 r16 +// SBBW m16 r16 +// SBBW r16 m16 +// SBBW r16 r16 +func SBBW(imr, amr operand.Op) (*intrep.Instruction, error) { + return build(opcSBBW.Forms(), sffxs{}, []operand.Op{imr, amr}) +} + +// SETCC: Set byte if above or equal (CF == 0). +// +// Forms: +// +// SETCC m8 +// SETCC r8 +func SETCC(mr operand.Op) (*intrep.Instruction, error) { + return build(opcSETCC.Forms(), sffxs{}, []operand.Op{mr}) +} + +// SETCS: Set byte if below (CF == 1). +// +// Forms: +// +// SETCS m8 +// SETCS r8 +func SETCS(mr operand.Op) (*intrep.Instruction, error) { + return build(opcSETCS.Forms(), sffxs{}, []operand.Op{mr}) +} + +// SETEQ: Set byte if equal (ZF == 1). +// +// Forms: +// +// SETEQ m8 +// SETEQ r8 +func SETEQ(mr operand.Op) (*intrep.Instruction, error) { + return build(opcSETEQ.Forms(), sffxs{}, []operand.Op{mr}) +} + +// SETGE: Set byte if greater or equal (SF == OF). +// +// Forms: +// +// SETGE m8 +// SETGE r8 +func SETGE(mr operand.Op) (*intrep.Instruction, error) { + return build(opcSETGE.Forms(), sffxs{}, []operand.Op{mr}) +} + +// SETGT: Set byte if greater (ZF == 0 and SF == OF). +// +// Forms: +// +// SETGT m8 +// SETGT r8 +func SETGT(mr operand.Op) (*intrep.Instruction, error) { + return build(opcSETGT.Forms(), sffxs{}, []operand.Op{mr}) +} + +// SETHI: Set byte if above (CF == 0 and ZF == 0). +// +// Forms: +// +// SETHI m8 +// SETHI r8 +func SETHI(mr operand.Op) (*intrep.Instruction, error) { + return build(opcSETHI.Forms(), sffxs{}, []operand.Op{mr}) +} + +// SETLE: Set byte if less or equal (ZF == 1 or SF != OF). +// +// Forms: +// +// SETLE m8 +// SETLE r8 +func SETLE(mr operand.Op) (*intrep.Instruction, error) { + return build(opcSETLE.Forms(), sffxs{}, []operand.Op{mr}) +} + +// SETLS: Set byte if below or equal (CF == 1 or ZF == 1). +// +// Forms: +// +// SETLS m8 +// SETLS r8 +func SETLS(mr operand.Op) (*intrep.Instruction, error) { + return build(opcSETLS.Forms(), sffxs{}, []operand.Op{mr}) +} + +// SETLT: Set byte if less (SF != OF). +// +// Forms: +// +// SETLT m8 +// SETLT r8 +func SETLT(mr operand.Op) (*intrep.Instruction, error) { + return build(opcSETLT.Forms(), sffxs{}, []operand.Op{mr}) +} + +// SETMI: Set byte if sign (SF == 1). +// +// Forms: +// +// SETMI m8 +// SETMI r8 +func SETMI(mr operand.Op) (*intrep.Instruction, error) { + return build(opcSETMI.Forms(), sffxs{}, []operand.Op{mr}) +} + +// SETNE: Set byte if not equal (ZF == 0). +// +// Forms: +// +// SETNE m8 +// SETNE r8 +func SETNE(mr operand.Op) (*intrep.Instruction, error) { + return build(opcSETNE.Forms(), sffxs{}, []operand.Op{mr}) +} + +// SETOC: Set byte if not overflow (OF == 0). +// +// Forms: +// +// SETOC m8 +// SETOC r8 +func SETOC(mr operand.Op) (*intrep.Instruction, error) { + return build(opcSETOC.Forms(), sffxs{}, []operand.Op{mr}) +} + +// SETOS: Set byte if overflow (OF == 1). +// +// Forms: +// +// SETOS m8 +// SETOS r8 +func SETOS(mr operand.Op) (*intrep.Instruction, error) { + return build(opcSETOS.Forms(), sffxs{}, []operand.Op{mr}) +} + +// SETPC: Set byte if not parity (PF == 0). +// +// Forms: +// +// SETPC m8 +// SETPC r8 +func SETPC(mr operand.Op) (*intrep.Instruction, error) { + return build(opcSETPC.Forms(), sffxs{}, []operand.Op{mr}) +} + +// SETPL: Set byte if not sign (SF == 0). +// +// Forms: +// +// SETPL m8 +// SETPL r8 +func SETPL(mr operand.Op) (*intrep.Instruction, error) { + return build(opcSETPL.Forms(), sffxs{}, []operand.Op{mr}) +} + +// SETPS: Set byte if parity (PF == 1). +// +// Forms: +// +// SETPS m8 +// SETPS r8 +func SETPS(mr operand.Op) (*intrep.Instruction, error) { + return build(opcSETPS.Forms(), sffxs{}, []operand.Op{mr}) +} + +// SFENCE: Store Fence. +// +// Forms: +// +// SFENCE +func SFENCE() (*intrep.Instruction, error) { + return build(opcSFENCE.Forms(), sffxs{}, []operand.Op{}) +} + +// SHA1MSG1: Perform an Intermediate Calculation for the Next Four SHA1 Message Doublewords. +// +// Forms: +// +// SHA1MSG1 m128 xmm +// SHA1MSG1 xmm xmm +func SHA1MSG1(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcSHA1MSG1.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// SHA1MSG2: Perform a Final Calculation for the Next Four SHA1 Message Doublewords. +// +// Forms: +// +// SHA1MSG2 m128 xmm +// SHA1MSG2 xmm xmm +func SHA1MSG2(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcSHA1MSG2.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// SHA1NEXTE: Calculate SHA1 State Variable E after Four Rounds. +// +// Forms: +// +// SHA1NEXTE m128 xmm +// SHA1NEXTE xmm xmm +func SHA1NEXTE(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcSHA1NEXTE.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// SHA1RNDS4: Perform Four Rounds of SHA1 Operation. +// +// Forms: +// +// SHA1RNDS4 imm2u m128 xmm +// SHA1RNDS4 imm2u xmm xmm +func SHA1RNDS4(i, mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcSHA1RNDS4.Forms(), sffxs{}, []operand.Op{i, mx, x}) +} + +// SHA256MSG1: Perform an Intermediate Calculation for the Next Four SHA256 Message Doublewords. +// +// Forms: +// +// SHA256MSG1 m128 xmm +// SHA256MSG1 xmm xmm +func SHA256MSG1(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcSHA256MSG1.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// SHA256MSG2: Perform a Final Calculation for the Next Four SHA256 Message Doublewords. +// +// Forms: +// +// SHA256MSG2 m128 xmm +// SHA256MSG2 xmm xmm +func SHA256MSG2(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcSHA256MSG2.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// SHA256RNDS2: Perform Two Rounds of SHA256 Operation. +// +// Forms: +// +// SHA256RNDS2 xmm0 m128 xmm +// SHA256RNDS2 xmm0 xmm xmm +func SHA256RNDS2(x, mx, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcSHA256RNDS2.Forms(), sffxs{}, []operand.Op{x, mx, x1}) +} + +// SHLB: Logical Shift Left. +// +// Forms: +// +// SHLB 1 m8 +// SHLB 1 r8 +// SHLB cl m8 +// SHLB cl r8 +// SHLB imm8 m8 +// SHLB imm8 r8 +func SHLB(ci, mr operand.Op) (*intrep.Instruction, error) { + return build(opcSHLB.Forms(), sffxs{}, []operand.Op{ci, mr}) +} + +// SHLL: Logical Shift Left. +// +// Forms: +// +// SHLL 1 m32 +// SHLL 1 r32 +// SHLL cl m32 +// SHLL cl r32 +// SHLL cl r32 m32 +// SHLL cl r32 r32 +// SHLL imm8 m32 +// SHLL imm8 r32 +// SHLL imm8 r32 m32 +// SHLL imm8 r32 r32 +func SHLL(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcSHLL.Forms(), sffxs{}, ops) +} + +// SHLQ: Logical Shift Left. +// +// Forms: +// +// SHLQ 1 m64 +// SHLQ 1 r64 +// SHLQ cl m64 +// SHLQ cl r64 +// SHLQ cl r64 m64 +// SHLQ cl r64 r64 +// SHLQ imm8 m64 +// SHLQ imm8 r64 +// SHLQ imm8 r64 m64 +// SHLQ imm8 r64 r64 +func SHLQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcSHLQ.Forms(), sffxs{}, ops) +} + +// SHLW: Logical Shift Left. +// +// Forms: +// +// SHLW 1 m16 +// SHLW 1 r16 +// SHLW cl m16 +// SHLW cl r16 +// SHLW cl r16 m16 +// SHLW cl r16 r16 +// SHLW imm8 m16 +// SHLW imm8 r16 +// SHLW imm8 r16 m16 +// SHLW imm8 r16 r16 +func SHLW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcSHLW.Forms(), sffxs{}, ops) +} + +// SHLXL: Logical Shift Left Without Affecting Flags. +// +// Forms: +// +// SHLXL r32 m32 r32 +// SHLXL r32 r32 r32 +func SHLXL(r, mr, r1 operand.Op) (*intrep.Instruction, error) { + return build(opcSHLXL.Forms(), sffxs{}, []operand.Op{r, mr, r1}) +} + +// SHLXQ: Logical Shift Left Without Affecting Flags. +// +// Forms: +// +// SHLXQ r64 m64 r64 +// SHLXQ r64 r64 r64 +func SHLXQ(r, mr, r1 operand.Op) (*intrep.Instruction, error) { + return build(opcSHLXQ.Forms(), sffxs{}, []operand.Op{r, mr, r1}) +} + +// SHRB: Logical Shift Right. +// +// Forms: +// +// SHRB 1 m8 +// SHRB 1 r8 +// SHRB cl m8 +// SHRB cl r8 +// SHRB imm8 m8 +// SHRB imm8 r8 +func SHRB(ci, mr operand.Op) (*intrep.Instruction, error) { + return build(opcSHRB.Forms(), sffxs{}, []operand.Op{ci, mr}) +} + +// SHRL: Logical Shift Right. +// +// Forms: +// +// SHRL 1 m32 +// SHRL 1 r32 +// SHRL cl m32 +// SHRL cl r32 +// SHRL cl r32 m32 +// SHRL cl r32 r32 +// SHRL imm8 m32 +// SHRL imm8 r32 +// SHRL imm8 r32 m32 +// SHRL imm8 r32 r32 +func SHRL(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcSHRL.Forms(), sffxs{}, ops) +} + +// SHRQ: Logical Shift Right. +// +// Forms: +// +// SHRQ 1 m64 +// SHRQ 1 r64 +// SHRQ cl m64 +// SHRQ cl r64 +// SHRQ cl r64 m64 +// SHRQ cl r64 r64 +// SHRQ imm8 m64 +// SHRQ imm8 r64 +// SHRQ imm8 r64 m64 +// SHRQ imm8 r64 r64 +func SHRQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcSHRQ.Forms(), sffxs{}, ops) +} + +// SHRW: Logical Shift Right. +// +// Forms: +// +// SHRW 1 m16 +// SHRW 1 r16 +// SHRW cl m16 +// SHRW cl r16 +// SHRW cl r16 m16 +// SHRW cl r16 r16 +// SHRW imm8 m16 +// SHRW imm8 r16 +// SHRW imm8 r16 m16 +// SHRW imm8 r16 r16 +func SHRW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcSHRW.Forms(), sffxs{}, ops) +} + +// SHRXL: Logical Shift Right Without Affecting Flags. +// +// Forms: +// +// SHRXL r32 m32 r32 +// SHRXL r32 r32 r32 +func SHRXL(r, mr, r1 operand.Op) (*intrep.Instruction, error) { + return build(opcSHRXL.Forms(), sffxs{}, []operand.Op{r, mr, r1}) +} + +// SHRXQ: Logical Shift Right Without Affecting Flags. +// +// Forms: +// +// SHRXQ r64 m64 r64 +// SHRXQ r64 r64 r64 +func SHRXQ(r, mr, r1 operand.Op) (*intrep.Instruction, error) { + return build(opcSHRXQ.Forms(), sffxs{}, []operand.Op{r, mr, r1}) +} + +// SHUFPD: Shuffle Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// SHUFPD imm8 m128 xmm +// SHUFPD imm8 xmm xmm +func SHUFPD(i, mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcSHUFPD.Forms(), sffxs{}, []operand.Op{i, mx, x}) +} + +// SHUFPS: Shuffle Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// SHUFPS imm8 m128 xmm +// SHUFPS imm8 xmm xmm +func SHUFPS(i, mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcSHUFPS.Forms(), sffxs{}, []operand.Op{i, mx, x}) +} + +// SQRTPD: Compute Square Roots of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// SQRTPD m128 xmm +// SQRTPD xmm xmm +func SQRTPD(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcSQRTPD.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// SQRTPS: Compute Square Roots of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// SQRTPS m128 xmm +// SQRTPS xmm xmm +func SQRTPS(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcSQRTPS.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// SQRTSD: Compute Square Root of Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// SQRTSD m64 xmm +// SQRTSD xmm xmm +func SQRTSD(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcSQRTSD.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// SQRTSS: Compute Square Root of Scalar Single-Precision Floating-Point Value. +// +// Forms: +// +// SQRTSS m32 xmm +// SQRTSS xmm xmm +func SQRTSS(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcSQRTSS.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// STC: Set Carry Flag. +// +// Forms: +// +// STC +func STC() (*intrep.Instruction, error) { + return build(opcSTC.Forms(), sffxs{}, []operand.Op{}) +} + +// STD: Set Direction Flag. +// +// Forms: +// +// STD +func STD() (*intrep.Instruction, error) { + return build(opcSTD.Forms(), sffxs{}, []operand.Op{}) +} + +// STMXCSR: Store MXCSR Register State. +// +// Forms: +// +// STMXCSR m32 +func STMXCSR(m operand.Op) (*intrep.Instruction, error) { + return build(opcSTMXCSR.Forms(), sffxs{}, []operand.Op{m}) +} + +// SUBB: Subtract. +// +// Forms: +// +// SUBB imm8 al +// SUBB imm8 m8 +// SUBB imm8 r8 +// SUBB m8 r8 +// SUBB r8 m8 +// SUBB r8 r8 +func SUBB(imr, amr operand.Op) (*intrep.Instruction, error) { + return build(opcSUBB.Forms(), sffxs{}, []operand.Op{imr, amr}) +} + +// SUBL: Subtract. +// +// Forms: +// +// SUBL imm32 eax +// SUBL imm32 m32 +// SUBL imm32 r32 +// SUBL imm8 m32 +// SUBL imm8 r32 +// SUBL m32 r32 +// SUBL r32 m32 +// SUBL r32 r32 +func SUBL(imr, emr operand.Op) (*intrep.Instruction, error) { + return build(opcSUBL.Forms(), sffxs{}, []operand.Op{imr, emr}) +} + +// SUBPD: Subtract Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// SUBPD m128 xmm +// SUBPD xmm xmm +func SUBPD(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcSUBPD.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// SUBPS: Subtract Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// SUBPS m128 xmm +// SUBPS xmm xmm +func SUBPS(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcSUBPS.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// SUBQ: Subtract. +// +// Forms: +// +// SUBQ imm32 m64 +// SUBQ imm32 r64 +// SUBQ imm32 rax +// SUBQ imm8 m64 +// SUBQ imm8 r64 +// SUBQ m64 r64 +// SUBQ r64 m64 +// SUBQ r64 r64 +func SUBQ(imr, mr operand.Op) (*intrep.Instruction, error) { + return build(opcSUBQ.Forms(), sffxs{}, []operand.Op{imr, mr}) +} + +// SUBSD: Subtract Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// SUBSD m64 xmm +// SUBSD xmm xmm +func SUBSD(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcSUBSD.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// SUBSS: Subtract Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// SUBSS m32 xmm +// SUBSS xmm xmm +func SUBSS(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcSUBSS.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// SUBW: Subtract. +// +// Forms: +// +// SUBW imm16 ax +// SUBW imm16 m16 +// SUBW imm16 r16 +// SUBW imm8 m16 +// SUBW imm8 r16 +// SUBW m16 r16 +// SUBW r16 m16 +// SUBW r16 r16 +func SUBW(imr, amr operand.Op) (*intrep.Instruction, error) { + return build(opcSUBW.Forms(), sffxs{}, []operand.Op{imr, amr}) +} + +// SYSCALL: Fast System Call. +// +// Forms: +// +// SYSCALL +func SYSCALL() (*intrep.Instruction, error) { + return build(opcSYSCALL.Forms(), sffxs{}, []operand.Op{}) +} + +// TESTB: Logical Compare. +// +// Forms: +// +// TESTB imm8 al +// TESTB imm8 m8 +// TESTB imm8 r8 +// TESTB r8 m8 +// TESTB r8 r8 +func TESTB(ir, amr operand.Op) (*intrep.Instruction, error) { + return build(opcTESTB.Forms(), sffxs{}, []operand.Op{ir, amr}) +} + +// TESTL: Logical Compare. +// +// Forms: +// +// TESTL imm32 eax +// TESTL imm32 m32 +// TESTL imm32 r32 +// TESTL r32 m32 +// TESTL r32 r32 +func TESTL(ir, emr operand.Op) (*intrep.Instruction, error) { + return build(opcTESTL.Forms(), sffxs{}, []operand.Op{ir, emr}) +} + +// TESTQ: Logical Compare. +// +// Forms: +// +// TESTQ imm32 m64 +// TESTQ imm32 r64 +// TESTQ imm32 rax +// TESTQ r64 m64 +// TESTQ r64 r64 +func TESTQ(ir, mr operand.Op) (*intrep.Instruction, error) { + return build(opcTESTQ.Forms(), sffxs{}, []operand.Op{ir, mr}) +} + +// TESTW: Logical Compare. +// +// Forms: +// +// TESTW imm16 ax +// TESTW imm16 m16 +// TESTW imm16 r16 +// TESTW r16 m16 +// TESTW r16 r16 +func TESTW(ir, amr operand.Op) (*intrep.Instruction, error) { + return build(opcTESTW.Forms(), sffxs{}, []operand.Op{ir, amr}) +} + +// TZCNTL: Count the Number of Trailing Zero Bits. +// +// Forms: +// +// TZCNTL m32 r32 +// TZCNTL r32 r32 +func TZCNTL(mr, r operand.Op) (*intrep.Instruction, error) { + return build(opcTZCNTL.Forms(), sffxs{}, []operand.Op{mr, r}) +} + +// TZCNTQ: Count the Number of Trailing Zero Bits. +// +// Forms: +// +// TZCNTQ m64 r64 +// TZCNTQ r64 r64 +func TZCNTQ(mr, r operand.Op) (*intrep.Instruction, error) { + return build(opcTZCNTQ.Forms(), sffxs{}, []operand.Op{mr, r}) +} + +// TZCNTW: Count the Number of Trailing Zero Bits. +// +// Forms: +// +// TZCNTW m16 r16 +// TZCNTW r16 r16 +func TZCNTW(mr, r operand.Op) (*intrep.Instruction, error) { + return build(opcTZCNTW.Forms(), sffxs{}, []operand.Op{mr, r}) +} + +// UCOMISD: Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS. +// +// Forms: +// +// UCOMISD m64 xmm +// UCOMISD xmm xmm +func UCOMISD(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcUCOMISD.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// UCOMISS: Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS. +// +// Forms: +// +// UCOMISS m32 xmm +// UCOMISS xmm xmm +func UCOMISS(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcUCOMISS.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// UD2: Undefined Instruction. +// +// Forms: +// +// UD2 +func UD2() (*intrep.Instruction, error) { + return build(opcUD2.Forms(), sffxs{}, []operand.Op{}) +} + +// UNPCKHPD: Unpack and Interleave High Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// UNPCKHPD m128 xmm +// UNPCKHPD xmm xmm +func UNPCKHPD(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcUNPCKHPD.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// UNPCKHPS: Unpack and Interleave High Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// UNPCKHPS m128 xmm +// UNPCKHPS xmm xmm +func UNPCKHPS(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcUNPCKHPS.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// UNPCKLPD: Unpack and Interleave Low Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// UNPCKLPD m128 xmm +// UNPCKLPD xmm xmm +func UNPCKLPD(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcUNPCKLPD.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// UNPCKLPS: Unpack and Interleave Low Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// UNPCKLPS m128 xmm +// UNPCKLPS xmm xmm +func UNPCKLPS(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcUNPCKLPS.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// VADDPD: Add Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VADDPD m128 xmm xmm +// VADDPD m256 ymm ymm +// VADDPD xmm xmm xmm +// VADDPD ymm ymm ymm +// VADDPD m128 xmm k xmm +// VADDPD m256 ymm k ymm +// VADDPD xmm xmm k xmm +// VADDPD ymm ymm k ymm +// VADDPD m512 zmm k zmm +// VADDPD m512 zmm zmm +// VADDPD zmm zmm k zmm +// VADDPD zmm zmm zmm +func VADDPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVADDPD.Forms(), sffxs{}, ops) +} + +// VADDPD_BCST: Add Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VADDPD.BCST m64 xmm k xmm +// VADDPD.BCST m64 xmm xmm +// VADDPD.BCST m64 ymm k ymm +// VADDPD.BCST m64 ymm ymm +// VADDPD.BCST m64 zmm k zmm +// VADDPD.BCST m64 zmm zmm +func VADDPD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVADDPD.Forms(), sffxs{sffxBCST}, ops) +} + +// VADDPD_BCST_Z: Add Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VADDPD.BCST.Z m64 xmm k xmm +// VADDPD.BCST.Z m64 ymm k ymm +// VADDPD.BCST.Z m64 zmm k zmm +func VADDPD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVADDPD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VADDPD_RD_SAE: Add Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VADDPD.RD_SAE zmm zmm k zmm +// VADDPD.RD_SAE zmm zmm zmm +func VADDPD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVADDPD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VADDPD_RD_SAE_Z: Add Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VADDPD.RD_SAE.Z zmm zmm k zmm +func VADDPD_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVADDPD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VADDPD_RN_SAE: Add Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VADDPD.RN_SAE zmm zmm k zmm +// VADDPD.RN_SAE zmm zmm zmm +func VADDPD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVADDPD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VADDPD_RN_SAE_Z: Add Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VADDPD.RN_SAE.Z zmm zmm k zmm +func VADDPD_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVADDPD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VADDPD_RU_SAE: Add Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VADDPD.RU_SAE zmm zmm k zmm +// VADDPD.RU_SAE zmm zmm zmm +func VADDPD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVADDPD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VADDPD_RU_SAE_Z: Add Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VADDPD.RU_SAE.Z zmm zmm k zmm +func VADDPD_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVADDPD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VADDPD_RZ_SAE: Add Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VADDPD.RZ_SAE zmm zmm k zmm +// VADDPD.RZ_SAE zmm zmm zmm +func VADDPD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVADDPD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VADDPD_RZ_SAE_Z: Add Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VADDPD.RZ_SAE.Z zmm zmm k zmm +func VADDPD_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVADDPD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VADDPD_Z: Add Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VADDPD.Z m128 xmm k xmm +// VADDPD.Z m256 ymm k ymm +// VADDPD.Z xmm xmm k xmm +// VADDPD.Z ymm ymm k ymm +// VADDPD.Z m512 zmm k zmm +// VADDPD.Z zmm zmm k zmm +func VADDPD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVADDPD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VADDPS: Add Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VADDPS m128 xmm xmm +// VADDPS m256 ymm ymm +// VADDPS xmm xmm xmm +// VADDPS ymm ymm ymm +// VADDPS m128 xmm k xmm +// VADDPS m256 ymm k ymm +// VADDPS xmm xmm k xmm +// VADDPS ymm ymm k ymm +// VADDPS m512 zmm k zmm +// VADDPS m512 zmm zmm +// VADDPS zmm zmm k zmm +// VADDPS zmm zmm zmm +func VADDPS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVADDPS.Forms(), sffxs{}, ops) +} + +// VADDPS_BCST: Add Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VADDPS.BCST m32 xmm k xmm +// VADDPS.BCST m32 xmm xmm +// VADDPS.BCST m32 ymm k ymm +// VADDPS.BCST m32 ymm ymm +// VADDPS.BCST m32 zmm k zmm +// VADDPS.BCST m32 zmm zmm +func VADDPS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVADDPS.Forms(), sffxs{sffxBCST}, ops) +} + +// VADDPS_BCST_Z: Add Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VADDPS.BCST.Z m32 xmm k xmm +// VADDPS.BCST.Z m32 ymm k ymm +// VADDPS.BCST.Z m32 zmm k zmm +func VADDPS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVADDPS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VADDPS_RD_SAE: Add Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VADDPS.RD_SAE zmm zmm k zmm +// VADDPS.RD_SAE zmm zmm zmm +func VADDPS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVADDPS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VADDPS_RD_SAE_Z: Add Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VADDPS.RD_SAE.Z zmm zmm k zmm +func VADDPS_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVADDPS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VADDPS_RN_SAE: Add Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VADDPS.RN_SAE zmm zmm k zmm +// VADDPS.RN_SAE zmm zmm zmm +func VADDPS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVADDPS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VADDPS_RN_SAE_Z: Add Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VADDPS.RN_SAE.Z zmm zmm k zmm +func VADDPS_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVADDPS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VADDPS_RU_SAE: Add Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VADDPS.RU_SAE zmm zmm k zmm +// VADDPS.RU_SAE zmm zmm zmm +func VADDPS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVADDPS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VADDPS_RU_SAE_Z: Add Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VADDPS.RU_SAE.Z zmm zmm k zmm +func VADDPS_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVADDPS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VADDPS_RZ_SAE: Add Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VADDPS.RZ_SAE zmm zmm k zmm +// VADDPS.RZ_SAE zmm zmm zmm +func VADDPS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVADDPS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VADDPS_RZ_SAE_Z: Add Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VADDPS.RZ_SAE.Z zmm zmm k zmm +func VADDPS_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVADDPS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VADDPS_Z: Add Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VADDPS.Z m128 xmm k xmm +// VADDPS.Z m256 ymm k ymm +// VADDPS.Z xmm xmm k xmm +// VADDPS.Z ymm ymm k ymm +// VADDPS.Z m512 zmm k zmm +// VADDPS.Z zmm zmm k zmm +func VADDPS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVADDPS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VADDSD: Add Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VADDSD m64 xmm xmm +// VADDSD xmm xmm xmm +// VADDSD m64 xmm k xmm +// VADDSD xmm xmm k xmm +func VADDSD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVADDSD.Forms(), sffxs{}, ops) +} + +// VADDSD_RD_SAE: Add Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VADDSD.RD_SAE xmm xmm k xmm +// VADDSD.RD_SAE xmm xmm xmm +func VADDSD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVADDSD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VADDSD_RD_SAE_Z: Add Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VADDSD.RD_SAE.Z xmm xmm k xmm +func VADDSD_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVADDSD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VADDSD_RN_SAE: Add Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VADDSD.RN_SAE xmm xmm k xmm +// VADDSD.RN_SAE xmm xmm xmm +func VADDSD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVADDSD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VADDSD_RN_SAE_Z: Add Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VADDSD.RN_SAE.Z xmm xmm k xmm +func VADDSD_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVADDSD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VADDSD_RU_SAE: Add Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VADDSD.RU_SAE xmm xmm k xmm +// VADDSD.RU_SAE xmm xmm xmm +func VADDSD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVADDSD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VADDSD_RU_SAE_Z: Add Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VADDSD.RU_SAE.Z xmm xmm k xmm +func VADDSD_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVADDSD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VADDSD_RZ_SAE: Add Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VADDSD.RZ_SAE xmm xmm k xmm +// VADDSD.RZ_SAE xmm xmm xmm +func VADDSD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVADDSD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VADDSD_RZ_SAE_Z: Add Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VADDSD.RZ_SAE.Z xmm xmm k xmm +func VADDSD_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVADDSD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VADDSD_Z: Add Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VADDSD.Z m64 xmm k xmm +// VADDSD.Z xmm xmm k xmm +func VADDSD_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVADDSD.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VADDSS: Add Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VADDSS m32 xmm xmm +// VADDSS xmm xmm xmm +// VADDSS m32 xmm k xmm +// VADDSS xmm xmm k xmm +func VADDSS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVADDSS.Forms(), sffxs{}, ops) +} + +// VADDSS_RD_SAE: Add Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VADDSS.RD_SAE xmm xmm k xmm +// VADDSS.RD_SAE xmm xmm xmm +func VADDSS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVADDSS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VADDSS_RD_SAE_Z: Add Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VADDSS.RD_SAE.Z xmm xmm k xmm +func VADDSS_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVADDSS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VADDSS_RN_SAE: Add Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VADDSS.RN_SAE xmm xmm k xmm +// VADDSS.RN_SAE xmm xmm xmm +func VADDSS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVADDSS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VADDSS_RN_SAE_Z: Add Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VADDSS.RN_SAE.Z xmm xmm k xmm +func VADDSS_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVADDSS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VADDSS_RU_SAE: Add Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VADDSS.RU_SAE xmm xmm k xmm +// VADDSS.RU_SAE xmm xmm xmm +func VADDSS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVADDSS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VADDSS_RU_SAE_Z: Add Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VADDSS.RU_SAE.Z xmm xmm k xmm +func VADDSS_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVADDSS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VADDSS_RZ_SAE: Add Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VADDSS.RZ_SAE xmm xmm k xmm +// VADDSS.RZ_SAE xmm xmm xmm +func VADDSS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVADDSS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VADDSS_RZ_SAE_Z: Add Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VADDSS.RZ_SAE.Z xmm xmm k xmm +func VADDSS_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVADDSS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VADDSS_Z: Add Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VADDSS.Z m32 xmm k xmm +// VADDSS.Z xmm xmm k xmm +func VADDSS_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVADDSS.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VADDSUBPD: Packed Double-FP Add/Subtract. +// +// Forms: +// +// VADDSUBPD m128 xmm xmm +// VADDSUBPD m256 ymm ymm +// VADDSUBPD xmm xmm xmm +// VADDSUBPD ymm ymm ymm +func VADDSUBPD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { + return build(opcVADDSUBPD.Forms(), sffxs{}, []operand.Op{mxy, xy, xy1}) +} + +// VADDSUBPS: Packed Single-FP Add/Subtract. +// +// Forms: +// +// VADDSUBPS m128 xmm xmm +// VADDSUBPS m256 ymm ymm +// VADDSUBPS xmm xmm xmm +// VADDSUBPS ymm ymm ymm +func VADDSUBPS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { + return build(opcVADDSUBPS.Forms(), sffxs{}, []operand.Op{mxy, xy, xy1}) +} + +// VAESDEC: Perform One Round of an AES Decryption Flow. +// +// Forms: +// +// VAESDEC m128 xmm xmm +// VAESDEC xmm xmm xmm +func VAESDEC(mx, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVAESDEC.Forms(), sffxs{}, []operand.Op{mx, x, x1}) +} + +// VAESDECLAST: Perform Last Round of an AES Decryption Flow. +// +// Forms: +// +// VAESDECLAST m128 xmm xmm +// VAESDECLAST xmm xmm xmm +func VAESDECLAST(mx, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVAESDECLAST.Forms(), sffxs{}, []operand.Op{mx, x, x1}) +} + +// VAESENC: Perform One Round of an AES Encryption Flow. +// +// Forms: +// +// VAESENC m128 xmm xmm +// VAESENC xmm xmm xmm +func VAESENC(mx, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVAESENC.Forms(), sffxs{}, []operand.Op{mx, x, x1}) +} + +// VAESENCLAST: Perform Last Round of an AES Encryption Flow. +// +// Forms: +// +// VAESENCLAST m128 xmm xmm +// VAESENCLAST xmm xmm xmm +func VAESENCLAST(mx, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVAESENCLAST.Forms(), sffxs{}, []operand.Op{mx, x, x1}) +} + +// VAESIMC: Perform the AES InvMixColumn Transformation. +// +// Forms: +// +// VAESIMC m128 xmm +// VAESIMC xmm xmm +func VAESIMC(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcVAESIMC.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// VAESKEYGENASSIST: AES Round Key Generation Assist. +// +// Forms: +// +// VAESKEYGENASSIST imm8 m128 xmm +// VAESKEYGENASSIST imm8 xmm xmm +func VAESKEYGENASSIST(i, mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcVAESKEYGENASSIST.Forms(), sffxs{}, []operand.Op{i, mx, x}) +} + +// VALIGND: Align Doubleword Vectors. +// +// Forms: +// +// VALIGND imm8 m128 xmm k xmm +// VALIGND imm8 m128 xmm xmm +// VALIGND imm8 m256 ymm k ymm +// VALIGND imm8 m256 ymm ymm +// VALIGND imm8 xmm xmm k xmm +// VALIGND imm8 xmm xmm xmm +// VALIGND imm8 ymm ymm k ymm +// VALIGND imm8 ymm ymm ymm +// VALIGND imm8 m512 zmm k zmm +// VALIGND imm8 m512 zmm zmm +// VALIGND imm8 zmm zmm k zmm +// VALIGND imm8 zmm zmm zmm +func VALIGND(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVALIGND.Forms(), sffxs{}, ops) +} + +// VALIGND_BCST: Align Doubleword Vectors (Broadcast). +// +// Forms: +// +// VALIGND.BCST imm8 m32 xmm k xmm +// VALIGND.BCST imm8 m32 xmm xmm +// VALIGND.BCST imm8 m32 ymm k ymm +// VALIGND.BCST imm8 m32 ymm ymm +// VALIGND.BCST imm8 m32 zmm k zmm +// VALIGND.BCST imm8 m32 zmm zmm +func VALIGND_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVALIGND.Forms(), sffxs{sffxBCST}, ops) +} + +// VALIGND_BCST_Z: Align Doubleword Vectors (Broadcast, Zeroing Masking). +// +// Forms: +// +// VALIGND.BCST.Z imm8 m32 xmm k xmm +// VALIGND.BCST.Z imm8 m32 ymm k ymm +// VALIGND.BCST.Z imm8 m32 zmm k zmm +func VALIGND_BCST_Z(i, m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVALIGND.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{i, m, xyz, k, xyz1}) +} + +// VALIGND_Z: Align Doubleword Vectors (Zeroing Masking). +// +// Forms: +// +// VALIGND.Z imm8 m128 xmm k xmm +// VALIGND.Z imm8 m256 ymm k ymm +// VALIGND.Z imm8 xmm xmm k xmm +// VALIGND.Z imm8 ymm ymm k ymm +// VALIGND.Z imm8 m512 zmm k zmm +// VALIGND.Z imm8 zmm zmm k zmm +func VALIGND_Z(i, mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVALIGND.Forms(), sffxs{sffxZ}, []operand.Op{i, mxyz, xyz, k, xyz1}) +} + +// VALIGNQ: Align Quadword Vectors. +// +// Forms: +// +// VALIGNQ imm8 m128 xmm k xmm +// VALIGNQ imm8 m128 xmm xmm +// VALIGNQ imm8 m256 ymm k ymm +// VALIGNQ imm8 m256 ymm ymm +// VALIGNQ imm8 xmm xmm k xmm +// VALIGNQ imm8 xmm xmm xmm +// VALIGNQ imm8 ymm ymm k ymm +// VALIGNQ imm8 ymm ymm ymm +// VALIGNQ imm8 m512 zmm k zmm +// VALIGNQ imm8 m512 zmm zmm +// VALIGNQ imm8 zmm zmm k zmm +// VALIGNQ imm8 zmm zmm zmm +func VALIGNQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVALIGNQ.Forms(), sffxs{}, ops) +} + +// VALIGNQ_BCST: Align Quadword Vectors (Broadcast). +// +// Forms: +// +// VALIGNQ.BCST imm8 m64 xmm k xmm +// VALIGNQ.BCST imm8 m64 xmm xmm +// VALIGNQ.BCST imm8 m64 ymm k ymm +// VALIGNQ.BCST imm8 m64 ymm ymm +// VALIGNQ.BCST imm8 m64 zmm k zmm +// VALIGNQ.BCST imm8 m64 zmm zmm +func VALIGNQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVALIGNQ.Forms(), sffxs{sffxBCST}, ops) +} + +// VALIGNQ_BCST_Z: Align Quadword Vectors (Broadcast, Zeroing Masking). +// +// Forms: +// +// VALIGNQ.BCST.Z imm8 m64 xmm k xmm +// VALIGNQ.BCST.Z imm8 m64 ymm k ymm +// VALIGNQ.BCST.Z imm8 m64 zmm k zmm +func VALIGNQ_BCST_Z(i, m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVALIGNQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{i, m, xyz, k, xyz1}) +} + +// VALIGNQ_Z: Align Quadword Vectors (Zeroing Masking). +// +// Forms: +// +// VALIGNQ.Z imm8 m128 xmm k xmm +// VALIGNQ.Z imm8 m256 ymm k ymm +// VALIGNQ.Z imm8 xmm xmm k xmm +// VALIGNQ.Z imm8 ymm ymm k ymm +// VALIGNQ.Z imm8 m512 zmm k zmm +// VALIGNQ.Z imm8 zmm zmm k zmm +func VALIGNQ_Z(i, mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVALIGNQ.Forms(), sffxs{sffxZ}, []operand.Op{i, mxyz, xyz, k, xyz1}) +} + +// VANDNPD: Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VANDNPD m128 xmm xmm +// VANDNPD m256 ymm ymm +// VANDNPD xmm xmm xmm +// VANDNPD ymm ymm ymm +// VANDNPD m128 xmm k xmm +// VANDNPD m256 ymm k ymm +// VANDNPD xmm xmm k xmm +// VANDNPD ymm ymm k ymm +// VANDNPD m512 zmm k zmm +// VANDNPD m512 zmm zmm +// VANDNPD zmm zmm k zmm +// VANDNPD zmm zmm zmm +func VANDNPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVANDNPD.Forms(), sffxs{}, ops) +} + +// VANDNPD_BCST: Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VANDNPD.BCST m64 xmm k xmm +// VANDNPD.BCST m64 xmm xmm +// VANDNPD.BCST m64 ymm k ymm +// VANDNPD.BCST m64 ymm ymm +// VANDNPD.BCST m64 zmm k zmm +// VANDNPD.BCST m64 zmm zmm +func VANDNPD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVANDNPD.Forms(), sffxs{sffxBCST}, ops) +} + +// VANDNPD_BCST_Z: Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VANDNPD.BCST.Z m64 xmm k xmm +// VANDNPD.BCST.Z m64 ymm k ymm +// VANDNPD.BCST.Z m64 zmm k zmm +func VANDNPD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVANDNPD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VANDNPD_Z: Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VANDNPD.Z m128 xmm k xmm +// VANDNPD.Z m256 ymm k ymm +// VANDNPD.Z xmm xmm k xmm +// VANDNPD.Z ymm ymm k ymm +// VANDNPD.Z m512 zmm k zmm +// VANDNPD.Z zmm zmm k zmm +func VANDNPD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVANDNPD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VANDNPS: Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VANDNPS m128 xmm xmm +// VANDNPS m256 ymm ymm +// VANDNPS xmm xmm xmm +// VANDNPS ymm ymm ymm +// VANDNPS m128 xmm k xmm +// VANDNPS m256 ymm k ymm +// VANDNPS xmm xmm k xmm +// VANDNPS ymm ymm k ymm +// VANDNPS m512 zmm k zmm +// VANDNPS m512 zmm zmm +// VANDNPS zmm zmm k zmm +// VANDNPS zmm zmm zmm +func VANDNPS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVANDNPS.Forms(), sffxs{}, ops) +} + +// VANDNPS_BCST: Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VANDNPS.BCST m32 xmm k xmm +// VANDNPS.BCST m32 xmm xmm +// VANDNPS.BCST m32 ymm k ymm +// VANDNPS.BCST m32 ymm ymm +// VANDNPS.BCST m32 zmm k zmm +// VANDNPS.BCST m32 zmm zmm +func VANDNPS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVANDNPS.Forms(), sffxs{sffxBCST}, ops) +} + +// VANDNPS_BCST_Z: Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VANDNPS.BCST.Z m32 xmm k xmm +// VANDNPS.BCST.Z m32 ymm k ymm +// VANDNPS.BCST.Z m32 zmm k zmm +func VANDNPS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVANDNPS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VANDNPS_Z: Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VANDNPS.Z m128 xmm k xmm +// VANDNPS.Z m256 ymm k ymm +// VANDNPS.Z xmm xmm k xmm +// VANDNPS.Z ymm ymm k ymm +// VANDNPS.Z m512 zmm k zmm +// VANDNPS.Z zmm zmm k zmm +func VANDNPS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVANDNPS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VANDPD: Bitwise Logical AND of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VANDPD m128 xmm xmm +// VANDPD m256 ymm ymm +// VANDPD xmm xmm xmm +// VANDPD ymm ymm ymm +// VANDPD m128 xmm k xmm +// VANDPD m256 ymm k ymm +// VANDPD xmm xmm k xmm +// VANDPD ymm ymm k ymm +// VANDPD m512 zmm k zmm +// VANDPD m512 zmm zmm +// VANDPD zmm zmm k zmm +// VANDPD zmm zmm zmm +func VANDPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVANDPD.Forms(), sffxs{}, ops) +} + +// VANDPD_BCST: Bitwise Logical AND of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VANDPD.BCST m64 xmm k xmm +// VANDPD.BCST m64 xmm xmm +// VANDPD.BCST m64 ymm k ymm +// VANDPD.BCST m64 ymm ymm +// VANDPD.BCST m64 zmm k zmm +// VANDPD.BCST m64 zmm zmm +func VANDPD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVANDPD.Forms(), sffxs{sffxBCST}, ops) +} + +// VANDPD_BCST_Z: Bitwise Logical AND of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VANDPD.BCST.Z m64 xmm k xmm +// VANDPD.BCST.Z m64 ymm k ymm +// VANDPD.BCST.Z m64 zmm k zmm +func VANDPD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVANDPD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VANDPD_Z: Bitwise Logical AND of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VANDPD.Z m128 xmm k xmm +// VANDPD.Z m256 ymm k ymm +// VANDPD.Z xmm xmm k xmm +// VANDPD.Z ymm ymm k ymm +// VANDPD.Z m512 zmm k zmm +// VANDPD.Z zmm zmm k zmm +func VANDPD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVANDPD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VANDPS: Bitwise Logical AND of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VANDPS m128 xmm xmm +// VANDPS m256 ymm ymm +// VANDPS xmm xmm xmm +// VANDPS ymm ymm ymm +// VANDPS m128 xmm k xmm +// VANDPS m256 ymm k ymm +// VANDPS xmm xmm k xmm +// VANDPS ymm ymm k ymm +// VANDPS m512 zmm k zmm +// VANDPS m512 zmm zmm +// VANDPS zmm zmm k zmm +// VANDPS zmm zmm zmm +func VANDPS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVANDPS.Forms(), sffxs{}, ops) +} + +// VANDPS_BCST: Bitwise Logical AND of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VANDPS.BCST m32 xmm k xmm +// VANDPS.BCST m32 xmm xmm +// VANDPS.BCST m32 ymm k ymm +// VANDPS.BCST m32 ymm ymm +// VANDPS.BCST m32 zmm k zmm +// VANDPS.BCST m32 zmm zmm +func VANDPS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVANDPS.Forms(), sffxs{sffxBCST}, ops) +} + +// VANDPS_BCST_Z: Bitwise Logical AND of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VANDPS.BCST.Z m32 xmm k xmm +// VANDPS.BCST.Z m32 ymm k ymm +// VANDPS.BCST.Z m32 zmm k zmm +func VANDPS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVANDPS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VANDPS_Z: Bitwise Logical AND of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VANDPS.Z m128 xmm k xmm +// VANDPS.Z m256 ymm k ymm +// VANDPS.Z xmm xmm k xmm +// VANDPS.Z ymm ymm k ymm +// VANDPS.Z m512 zmm k zmm +// VANDPS.Z zmm zmm k zmm +func VANDPS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVANDPS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VBLENDMPD: Blend Packed Double-Precision Floating-Point Vectors Using an OpMask Control. +// +// Forms: +// +// VBLENDMPD m128 xmm k xmm +// VBLENDMPD m128 xmm xmm +// VBLENDMPD m256 ymm k ymm +// VBLENDMPD m256 ymm ymm +// VBLENDMPD xmm xmm k xmm +// VBLENDMPD xmm xmm xmm +// VBLENDMPD ymm ymm k ymm +// VBLENDMPD ymm ymm ymm +// VBLENDMPD m512 zmm k zmm +// VBLENDMPD m512 zmm zmm +// VBLENDMPD zmm zmm k zmm +// VBLENDMPD zmm zmm zmm +func VBLENDMPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVBLENDMPD.Forms(), sffxs{}, ops) +} + +// VBLENDMPD_BCST: Blend Packed Double-Precision Floating-Point Vectors Using an OpMask Control (Broadcast). +// +// Forms: +// +// VBLENDMPD.BCST m64 xmm k xmm +// VBLENDMPD.BCST m64 xmm xmm +// VBLENDMPD.BCST m64 ymm k ymm +// VBLENDMPD.BCST m64 ymm ymm +// VBLENDMPD.BCST m64 zmm k zmm +// VBLENDMPD.BCST m64 zmm zmm +func VBLENDMPD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVBLENDMPD.Forms(), sffxs{sffxBCST}, ops) +} + +// VBLENDMPD_BCST_Z: Blend Packed Double-Precision Floating-Point Vectors Using an OpMask Control (Broadcast, Zeroing Masking). +// +// Forms: +// +// VBLENDMPD.BCST.Z m64 xmm k xmm +// VBLENDMPD.BCST.Z m64 ymm k ymm +// VBLENDMPD.BCST.Z m64 zmm k zmm +func VBLENDMPD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVBLENDMPD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VBLENDMPD_Z: Blend Packed Double-Precision Floating-Point Vectors Using an OpMask Control (Zeroing Masking). +// +// Forms: +// +// VBLENDMPD.Z m128 xmm k xmm +// VBLENDMPD.Z m256 ymm k ymm +// VBLENDMPD.Z xmm xmm k xmm +// VBLENDMPD.Z ymm ymm k ymm +// VBLENDMPD.Z m512 zmm k zmm +// VBLENDMPD.Z zmm zmm k zmm +func VBLENDMPD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVBLENDMPD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VBLENDMPS: Blend Packed Single-Precision Floating-Point Vectors Using an OpMask Control. +// +// Forms: +// +// VBLENDMPS m128 xmm k xmm +// VBLENDMPS m128 xmm xmm +// VBLENDMPS m256 ymm k ymm +// VBLENDMPS m256 ymm ymm +// VBLENDMPS xmm xmm k xmm +// VBLENDMPS xmm xmm xmm +// VBLENDMPS ymm ymm k ymm +// VBLENDMPS ymm ymm ymm +// VBLENDMPS m512 zmm k zmm +// VBLENDMPS m512 zmm zmm +// VBLENDMPS zmm zmm k zmm +// VBLENDMPS zmm zmm zmm +func VBLENDMPS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVBLENDMPS.Forms(), sffxs{}, ops) +} + +// VBLENDMPS_BCST: Blend Packed Single-Precision Floating-Point Vectors Using an OpMask Control (Broadcast). +// +// Forms: +// +// VBLENDMPS.BCST m32 xmm k xmm +// VBLENDMPS.BCST m32 xmm xmm +// VBLENDMPS.BCST m32 ymm k ymm +// VBLENDMPS.BCST m32 ymm ymm +// VBLENDMPS.BCST m32 zmm k zmm +// VBLENDMPS.BCST m32 zmm zmm +func VBLENDMPS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVBLENDMPS.Forms(), sffxs{sffxBCST}, ops) +} + +// VBLENDMPS_BCST_Z: Blend Packed Single-Precision Floating-Point Vectors Using an OpMask Control (Broadcast, Zeroing Masking). +// +// Forms: +// +// VBLENDMPS.BCST.Z m32 xmm k xmm +// VBLENDMPS.BCST.Z m32 ymm k ymm +// VBLENDMPS.BCST.Z m32 zmm k zmm +func VBLENDMPS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVBLENDMPS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VBLENDMPS_Z: Blend Packed Single-Precision Floating-Point Vectors Using an OpMask Control (Zeroing Masking). +// +// Forms: +// +// VBLENDMPS.Z m128 xmm k xmm +// VBLENDMPS.Z m256 ymm k ymm +// VBLENDMPS.Z xmm xmm k xmm +// VBLENDMPS.Z ymm ymm k ymm +// VBLENDMPS.Z m512 zmm k zmm +// VBLENDMPS.Z zmm zmm k zmm +func VBLENDMPS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVBLENDMPS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VBLENDPD: Blend Packed Double Precision Floating-Point Values. +// +// Forms: +// +// VBLENDPD imm8 m128 xmm xmm +// VBLENDPD imm8 m256 ymm ymm +// VBLENDPD imm8 xmm xmm xmm +// VBLENDPD imm8 ymm ymm ymm +func VBLENDPD(i, mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { + return build(opcVBLENDPD.Forms(), sffxs{}, []operand.Op{i, mxy, xy, xy1}) +} + +// VBLENDPS: Blend Packed Single Precision Floating-Point Values. +// +// Forms: +// +// VBLENDPS imm8 m128 xmm xmm +// VBLENDPS imm8 m256 ymm ymm +// VBLENDPS imm8 xmm xmm xmm +// VBLENDPS imm8 ymm ymm ymm +func VBLENDPS(i, mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { + return build(opcVBLENDPS.Forms(), sffxs{}, []operand.Op{i, mxy, xy, xy1}) +} + +// VBLENDVPD: Variable Blend Packed Double Precision Floating-Point Values. +// +// Forms: +// +// VBLENDVPD xmm m128 xmm xmm +// VBLENDVPD xmm xmm xmm xmm +// VBLENDVPD ymm m256 ymm ymm +// VBLENDVPD ymm ymm ymm ymm +func VBLENDVPD(xy, mxy, xy1, xy2 operand.Op) (*intrep.Instruction, error) { + return build(opcVBLENDVPD.Forms(), sffxs{}, []operand.Op{xy, mxy, xy1, xy2}) +} + +// VBLENDVPS: Variable Blend Packed Single Precision Floating-Point Values. +// +// Forms: +// +// VBLENDVPS xmm m128 xmm xmm +// VBLENDVPS xmm xmm xmm xmm +// VBLENDVPS ymm m256 ymm ymm +// VBLENDVPS ymm ymm ymm ymm +func VBLENDVPS(xy, mxy, xy1, xy2 operand.Op) (*intrep.Instruction, error) { + return build(opcVBLENDVPS.Forms(), sffxs{}, []operand.Op{xy, mxy, xy1, xy2}) +} + +// VBROADCASTF128: Broadcast 128 Bit of Floating-Point Data. +// +// Forms: +// +// VBROADCASTF128 m128 ymm +func VBROADCASTF128(m, y operand.Op) (*intrep.Instruction, error) { + return build(opcVBROADCASTF128.Forms(), sffxs{}, []operand.Op{m, y}) +} + +// VBROADCASTF32X2: Broadcast Two Single-Precision Floating-Point Elements. +// +// Forms: +// +// VBROADCASTF32X2 m64 k ymm +// VBROADCASTF32X2 m64 ymm +// VBROADCASTF32X2 xmm k ymm +// VBROADCASTF32X2 xmm ymm +// VBROADCASTF32X2 m64 k zmm +// VBROADCASTF32X2 m64 zmm +// VBROADCASTF32X2 xmm k zmm +// VBROADCASTF32X2 xmm zmm +func VBROADCASTF32X2(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVBROADCASTF32X2.Forms(), sffxs{}, ops) +} + +// VBROADCASTF32X2_Z: Broadcast Two Single-Precision Floating-Point Elements (Zeroing Masking). +// +// Forms: +// +// VBROADCASTF32X2.Z m64 k ymm +// VBROADCASTF32X2.Z xmm k ymm +// VBROADCASTF32X2.Z m64 k zmm +// VBROADCASTF32X2.Z xmm k zmm +func VBROADCASTF32X2_Z(mx, k, yz operand.Op) (*intrep.Instruction, error) { + return build(opcVBROADCASTF32X2.Forms(), sffxs{sffxZ}, []operand.Op{mx, k, yz}) +} + +// VBROADCASTF32X4: Broadcast Four Single-Precision Floating-Point Elements. +// +// Forms: +// +// VBROADCASTF32X4 m128 k ymm +// VBROADCASTF32X4 m128 ymm +// VBROADCASTF32X4 m128 k zmm +// VBROADCASTF32X4 m128 zmm +func VBROADCASTF32X4(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVBROADCASTF32X4.Forms(), sffxs{}, ops) +} + +// VBROADCASTF32X4_Z: Broadcast Four Single-Precision Floating-Point Elements (Zeroing Masking). +// +// Forms: +// +// VBROADCASTF32X4.Z m128 k ymm +// VBROADCASTF32X4.Z m128 k zmm +func VBROADCASTF32X4_Z(m, k, yz operand.Op) (*intrep.Instruction, error) { + return build(opcVBROADCASTF32X4.Forms(), sffxs{sffxZ}, []operand.Op{m, k, yz}) +} + +// VBROADCASTF32X8: Broadcast Eight Single-Precision Floating-Point Elements. +// +// Forms: +// +// VBROADCASTF32X8 m256 k zmm +// VBROADCASTF32X8 m256 zmm +func VBROADCASTF32X8(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVBROADCASTF32X8.Forms(), sffxs{}, ops) +} + +// VBROADCASTF32X8_Z: Broadcast Eight Single-Precision Floating-Point Elements (Zeroing Masking). +// +// Forms: +// +// VBROADCASTF32X8.Z m256 k zmm +func VBROADCASTF32X8_Z(m, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVBROADCASTF32X8.Forms(), sffxs{sffxZ}, []operand.Op{m, k, z}) +} + +// VBROADCASTF64X2: Broadcast Two Double-Precision Floating-Point Elements. +// +// Forms: +// +// VBROADCASTF64X2 m128 k ymm +// VBROADCASTF64X2 m128 ymm +// VBROADCASTF64X2 m128 k zmm +// VBROADCASTF64X2 m128 zmm +func VBROADCASTF64X2(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVBROADCASTF64X2.Forms(), sffxs{}, ops) +} + +// VBROADCASTF64X2_Z: Broadcast Two Double-Precision Floating-Point Elements (Zeroing Masking). +// +// Forms: +// +// VBROADCASTF64X2.Z m128 k ymm +// VBROADCASTF64X2.Z m128 k zmm +func VBROADCASTF64X2_Z(m, k, yz operand.Op) (*intrep.Instruction, error) { + return build(opcVBROADCASTF64X2.Forms(), sffxs{sffxZ}, []operand.Op{m, k, yz}) +} + +// VBROADCASTF64X4: Broadcast Four Double-Precision Floating-Point Elements. +// +// Forms: +// +// VBROADCASTF64X4 m256 k zmm +// VBROADCASTF64X4 m256 zmm +func VBROADCASTF64X4(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVBROADCASTF64X4.Forms(), sffxs{}, ops) +} + +// VBROADCASTF64X4_Z: Broadcast Four Double-Precision Floating-Point Elements (Zeroing Masking). +// +// Forms: +// +// VBROADCASTF64X4.Z m256 k zmm +func VBROADCASTF64X4_Z(m, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVBROADCASTF64X4.Forms(), sffxs{sffxZ}, []operand.Op{m, k, z}) +} + +// VBROADCASTI128: Broadcast 128 Bits of Integer Data. +// +// Forms: +// +// VBROADCASTI128 m128 ymm +func VBROADCASTI128(m, y operand.Op) (*intrep.Instruction, error) { + return build(opcVBROADCASTI128.Forms(), sffxs{}, []operand.Op{m, y}) +} + +// VBROADCASTI32X2: Broadcast Two Doubleword Elements. +// +// Forms: +// +// VBROADCASTI32X2 m64 k xmm +// VBROADCASTI32X2 m64 k ymm +// VBROADCASTI32X2 m64 xmm +// VBROADCASTI32X2 m64 ymm +// VBROADCASTI32X2 xmm k xmm +// VBROADCASTI32X2 xmm k ymm +// VBROADCASTI32X2 xmm xmm +// VBROADCASTI32X2 xmm ymm +// VBROADCASTI32X2 m64 k zmm +// VBROADCASTI32X2 m64 zmm +// VBROADCASTI32X2 xmm k zmm +// VBROADCASTI32X2 xmm zmm +func VBROADCASTI32X2(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVBROADCASTI32X2.Forms(), sffxs{}, ops) +} + +// VBROADCASTI32X2_Z: Broadcast Two Doubleword Elements (Zeroing Masking). +// +// Forms: +// +// VBROADCASTI32X2.Z m64 k xmm +// VBROADCASTI32X2.Z m64 k ymm +// VBROADCASTI32X2.Z xmm k xmm +// VBROADCASTI32X2.Z xmm k ymm +// VBROADCASTI32X2.Z m64 k zmm +// VBROADCASTI32X2.Z xmm k zmm +func VBROADCASTI32X2_Z(mx, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVBROADCASTI32X2.Forms(), sffxs{sffxZ}, []operand.Op{mx, k, xyz}) +} + +// VBROADCASTI32X4: Broadcast Four Doubleword Elements. +// +// Forms: +// +// VBROADCASTI32X4 m128 k ymm +// VBROADCASTI32X4 m128 ymm +// VBROADCASTI32X4 m128 k zmm +// VBROADCASTI32X4 m128 zmm +func VBROADCASTI32X4(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVBROADCASTI32X4.Forms(), sffxs{}, ops) +} + +// VBROADCASTI32X4_Z: Broadcast Four Doubleword Elements (Zeroing Masking). +// +// Forms: +// +// VBROADCASTI32X4.Z m128 k ymm +// VBROADCASTI32X4.Z m128 k zmm +func VBROADCASTI32X4_Z(m, k, yz operand.Op) (*intrep.Instruction, error) { + return build(opcVBROADCASTI32X4.Forms(), sffxs{sffxZ}, []operand.Op{m, k, yz}) +} + +// VBROADCASTI32X8: Broadcast Eight Doubleword Elements. +// +// Forms: +// +// VBROADCASTI32X8 m256 k zmm +// VBROADCASTI32X8 m256 zmm +func VBROADCASTI32X8(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVBROADCASTI32X8.Forms(), sffxs{}, ops) +} + +// VBROADCASTI32X8_Z: Broadcast Eight Doubleword Elements (Zeroing Masking). +// +// Forms: +// +// VBROADCASTI32X8.Z m256 k zmm +func VBROADCASTI32X8_Z(m, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVBROADCASTI32X8.Forms(), sffxs{sffxZ}, []operand.Op{m, k, z}) +} + +// VBROADCASTI64X2: Broadcast Two Quadword Elements. +// +// Forms: +// +// VBROADCASTI64X2 m128 k ymm +// VBROADCASTI64X2 m128 ymm +// VBROADCASTI64X2 m128 k zmm +// VBROADCASTI64X2 m128 zmm +func VBROADCASTI64X2(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVBROADCASTI64X2.Forms(), sffxs{}, ops) +} + +// VBROADCASTI64X2_Z: Broadcast Two Quadword Elements (Zeroing Masking). +// +// Forms: +// +// VBROADCASTI64X2.Z m128 k ymm +// VBROADCASTI64X2.Z m128 k zmm +func VBROADCASTI64X2_Z(m, k, yz operand.Op) (*intrep.Instruction, error) { + return build(opcVBROADCASTI64X2.Forms(), sffxs{sffxZ}, []operand.Op{m, k, yz}) +} + +// VBROADCASTI64X4: Broadcast Four Quadword Elements. +// +// Forms: +// +// VBROADCASTI64X4 m256 k zmm +// VBROADCASTI64X4 m256 zmm +func VBROADCASTI64X4(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVBROADCASTI64X4.Forms(), sffxs{}, ops) +} + +// VBROADCASTI64X4_Z: Broadcast Four Quadword Elements (Zeroing Masking). +// +// Forms: +// +// VBROADCASTI64X4.Z m256 k zmm +func VBROADCASTI64X4_Z(m, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVBROADCASTI64X4.Forms(), sffxs{sffxZ}, []operand.Op{m, k, z}) +} + +// VBROADCASTSD: Broadcast Double-Precision Floating-Point Element. +// +// Forms: +// +// VBROADCASTSD xmm ymm +// VBROADCASTSD m64 ymm +// VBROADCASTSD m64 k ymm +// VBROADCASTSD xmm k ymm +// VBROADCASTSD m64 k zmm +// VBROADCASTSD m64 zmm +// VBROADCASTSD xmm k zmm +// VBROADCASTSD xmm zmm +func VBROADCASTSD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVBROADCASTSD.Forms(), sffxs{}, ops) +} + +// VBROADCASTSD_Z: Broadcast Double-Precision Floating-Point Element (Zeroing Masking). +// +// Forms: +// +// VBROADCASTSD.Z m64 k ymm +// VBROADCASTSD.Z xmm k ymm +// VBROADCASTSD.Z m64 k zmm +// VBROADCASTSD.Z xmm k zmm +func VBROADCASTSD_Z(mx, k, yz operand.Op) (*intrep.Instruction, error) { + return build(opcVBROADCASTSD.Forms(), sffxs{sffxZ}, []operand.Op{mx, k, yz}) +} + +// VBROADCASTSS: Broadcast Single-Precision Floating-Point Element. +// +// Forms: +// +// VBROADCASTSS xmm xmm +// VBROADCASTSS xmm ymm +// VBROADCASTSS m32 xmm +// VBROADCASTSS m32 ymm +// VBROADCASTSS m32 k ymm +// VBROADCASTSS xmm k ymm +// VBROADCASTSS m32 k zmm +// VBROADCASTSS m32 zmm +// VBROADCASTSS xmm k zmm +// VBROADCASTSS xmm zmm +func VBROADCASTSS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVBROADCASTSS.Forms(), sffxs{}, ops) +} + +// VBROADCASTSS_Z: Broadcast Single-Precision Floating-Point Element (Zeroing Masking). +// +// Forms: +// +// VBROADCASTSS.Z m32 k ymm +// VBROADCASTSS.Z xmm k ymm +// VBROADCASTSS.Z m32 k zmm +// VBROADCASTSS.Z xmm k zmm +func VBROADCASTSS_Z(mx, k, yz operand.Op) (*intrep.Instruction, error) { + return build(opcVBROADCASTSS.Forms(), sffxs{sffxZ}, []operand.Op{mx, k, yz}) +} + +// VCMPPD: Compare Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VCMPPD imm8 m128 xmm xmm +// VCMPPD imm8 m256 ymm ymm +// VCMPPD imm8 xmm xmm xmm +// VCMPPD imm8 ymm ymm ymm +// VCMPPD imm8 m128 xmm k k +// VCMPPD imm8 m128 xmm k +// VCMPPD imm8 m256 ymm k k +// VCMPPD imm8 m256 ymm k +// VCMPPD imm8 xmm xmm k k +// VCMPPD imm8 xmm xmm k +// VCMPPD imm8 ymm ymm k k +// VCMPPD imm8 ymm ymm k +// VCMPPD imm8 m512 zmm k k +// VCMPPD imm8 m512 zmm k +// VCMPPD imm8 zmm zmm k k +// VCMPPD imm8 zmm zmm k +func VCMPPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCMPPD.Forms(), sffxs{}, ops) +} + +// VCMPPD_BCST: Compare Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCMPPD.BCST imm8 m64 xmm k k +// VCMPPD.BCST imm8 m64 xmm k +// VCMPPD.BCST imm8 m64 ymm k k +// VCMPPD.BCST imm8 m64 ymm k +// VCMPPD.BCST imm8 m64 zmm k k +// VCMPPD.BCST imm8 m64 zmm k +func VCMPPD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCMPPD.Forms(), sffxs{sffxBCST}, ops) +} + +// VCMPPD_SAE: Compare Packed Double-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VCMPPD.SAE imm8 zmm zmm k k +// VCMPPD.SAE imm8 zmm zmm k +func VCMPPD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCMPPD.Forms(), sffxs{sffxSAE}, ops) +} + +// VCMPPS: Compare Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VCMPPS imm8 m128 xmm xmm +// VCMPPS imm8 m256 ymm ymm +// VCMPPS imm8 xmm xmm xmm +// VCMPPS imm8 ymm ymm ymm +// VCMPPS imm8 m128 xmm k k +// VCMPPS imm8 m128 xmm k +// VCMPPS imm8 m256 ymm k k +// VCMPPS imm8 m256 ymm k +// VCMPPS imm8 xmm xmm k k +// VCMPPS imm8 xmm xmm k +// VCMPPS imm8 ymm ymm k k +// VCMPPS imm8 ymm ymm k +// VCMPPS imm8 m512 zmm k k +// VCMPPS imm8 m512 zmm k +// VCMPPS imm8 zmm zmm k k +// VCMPPS imm8 zmm zmm k +func VCMPPS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCMPPS.Forms(), sffxs{}, ops) +} + +// VCMPPS_BCST: Compare Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCMPPS.BCST imm8 m32 xmm k k +// VCMPPS.BCST imm8 m32 xmm k +// VCMPPS.BCST imm8 m32 ymm k k +// VCMPPS.BCST imm8 m32 ymm k +// VCMPPS.BCST imm8 m32 zmm k k +// VCMPPS.BCST imm8 m32 zmm k +func VCMPPS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCMPPS.Forms(), sffxs{sffxBCST}, ops) +} + +// VCMPPS_SAE: Compare Packed Single-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VCMPPS.SAE imm8 zmm zmm k k +// VCMPPS.SAE imm8 zmm zmm k +func VCMPPS_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCMPPS.Forms(), sffxs{sffxSAE}, ops) +} + +// VCMPSD: Compare Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VCMPSD imm8 m64 xmm xmm +// VCMPSD imm8 xmm xmm xmm +// VCMPSD imm8 m64 xmm k k +// VCMPSD imm8 m64 xmm k +// VCMPSD imm8 xmm xmm k k +// VCMPSD imm8 xmm xmm k +func VCMPSD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCMPSD.Forms(), sffxs{}, ops) +} + +// VCMPSD_SAE: Compare Scalar Double-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VCMPSD.SAE imm8 xmm xmm k k +// VCMPSD.SAE imm8 xmm xmm k +func VCMPSD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCMPSD.Forms(), sffxs{sffxSAE}, ops) +} + +// VCMPSS: Compare Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VCMPSS imm8 m32 xmm xmm +// VCMPSS imm8 xmm xmm xmm +// VCMPSS imm8 m32 xmm k k +// VCMPSS imm8 m32 xmm k +// VCMPSS imm8 xmm xmm k k +// VCMPSS imm8 xmm xmm k +func VCMPSS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCMPSS.Forms(), sffxs{}, ops) +} + +// VCMPSS_SAE: Compare Scalar Single-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VCMPSS.SAE imm8 xmm xmm k k +// VCMPSS.SAE imm8 xmm xmm k +func VCMPSS_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCMPSS.Forms(), sffxs{sffxSAE}, ops) +} + +// VCOMISD: Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS. +// +// Forms: +// +// VCOMISD m64 xmm +// VCOMISD xmm xmm +func VCOMISD(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcVCOMISD.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// VCOMISD_SAE: Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS (Suppress All Exceptions). +// +// Forms: +// +// VCOMISD.SAE xmm xmm +func VCOMISD_SAE(x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCOMISD.Forms(), sffxs{sffxSAE}, []operand.Op{x, x1}) +} + +// VCOMISS: Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS. +// +// Forms: +// +// VCOMISS m32 xmm +// VCOMISS xmm xmm +func VCOMISS(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcVCOMISS.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// VCOMISS_SAE: Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS (Suppress All Exceptions). +// +// Forms: +// +// VCOMISS.SAE xmm xmm +func VCOMISS_SAE(x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCOMISS.Forms(), sffxs{sffxSAE}, []operand.Op{x, x1}) +} + +// VCOMPRESSPD: Store Sparse Packed Double-Precision Floating-Point Values into Dense Memory/Register. +// +// Forms: +// +// VCOMPRESSPD xmm k m128 +// VCOMPRESSPD xmm k xmm +// VCOMPRESSPD xmm m128 +// VCOMPRESSPD xmm xmm +// VCOMPRESSPD ymm k m256 +// VCOMPRESSPD ymm k ymm +// VCOMPRESSPD ymm m256 +// VCOMPRESSPD ymm ymm +// VCOMPRESSPD zmm k m512 +// VCOMPRESSPD zmm k zmm +// VCOMPRESSPD zmm m512 +// VCOMPRESSPD zmm zmm +func VCOMPRESSPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCOMPRESSPD.Forms(), sffxs{}, ops) +} + +// VCOMPRESSPD_Z: Store Sparse Packed Double-Precision Floating-Point Values into Dense Memory/Register (Zeroing Masking). +// +// Forms: +// +// VCOMPRESSPD.Z xmm k m128 +// VCOMPRESSPD.Z xmm k xmm +// VCOMPRESSPD.Z ymm k m256 +// VCOMPRESSPD.Z ymm k ymm +// VCOMPRESSPD.Z zmm k m512 +// VCOMPRESSPD.Z zmm k zmm +func VCOMPRESSPD_Z(xyz, k, mxyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCOMPRESSPD.Forms(), sffxs{sffxZ}, []operand.Op{xyz, k, mxyz}) +} + +// VCOMPRESSPS: Store Sparse Packed Single-Precision Floating-Point Values into Dense Memory/Register. +// +// Forms: +// +// VCOMPRESSPS xmm k m128 +// VCOMPRESSPS xmm k xmm +// VCOMPRESSPS xmm m128 +// VCOMPRESSPS xmm xmm +// VCOMPRESSPS ymm k m256 +// VCOMPRESSPS ymm k ymm +// VCOMPRESSPS ymm m256 +// VCOMPRESSPS ymm ymm +// VCOMPRESSPS zmm k m512 +// VCOMPRESSPS zmm k zmm +// VCOMPRESSPS zmm m512 +// VCOMPRESSPS zmm zmm +func VCOMPRESSPS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCOMPRESSPS.Forms(), sffxs{}, ops) +} + +// VCOMPRESSPS_Z: Store Sparse Packed Single-Precision Floating-Point Values into Dense Memory/Register (Zeroing Masking). +// +// Forms: +// +// VCOMPRESSPS.Z xmm k m128 +// VCOMPRESSPS.Z xmm k xmm +// VCOMPRESSPS.Z ymm k m256 +// VCOMPRESSPS.Z ymm k ymm +// VCOMPRESSPS.Z zmm k m512 +// VCOMPRESSPS.Z zmm k zmm +func VCOMPRESSPS_Z(xyz, k, mxyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCOMPRESSPS.Forms(), sffxs{sffxZ}, []operand.Op{xyz, k, mxyz}) +} + +// VCVTDQ2PD: Convert Packed Dword Integers to Packed Double-Precision FP Values. +// +// Forms: +// +// VCVTDQ2PD m128 ymm +// VCVTDQ2PD m64 xmm +// VCVTDQ2PD xmm xmm +// VCVTDQ2PD xmm ymm +// VCVTDQ2PD m128 k ymm +// VCVTDQ2PD m64 k xmm +// VCVTDQ2PD xmm k xmm +// VCVTDQ2PD xmm k ymm +// VCVTDQ2PD m256 k zmm +// VCVTDQ2PD m256 zmm +// VCVTDQ2PD ymm k zmm +// VCVTDQ2PD ymm zmm +func VCVTDQ2PD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTDQ2PD.Forms(), sffxs{}, ops) +} + +// VCVTDQ2PD_BCST: Convert Packed Dword Integers to Packed Double-Precision FP Values (Broadcast). +// +// Forms: +// +// VCVTDQ2PD.BCST m32 k xmm +// VCVTDQ2PD.BCST m32 k ymm +// VCVTDQ2PD.BCST m32 xmm +// VCVTDQ2PD.BCST m32 ymm +// VCVTDQ2PD.BCST m32 k zmm +// VCVTDQ2PD.BCST m32 zmm +func VCVTDQ2PD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTDQ2PD.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTDQ2PD_BCST_Z: Convert Packed Dword Integers to Packed Double-Precision FP Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTDQ2PD.BCST.Z m32 k xmm +// VCVTDQ2PD.BCST.Z m32 k ymm +// VCVTDQ2PD.BCST.Z m32 k zmm +func VCVTDQ2PD_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTDQ2PD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) +} + +// VCVTDQ2PD_Z: Convert Packed Dword Integers to Packed Double-Precision FP Values (Zeroing Masking). +// +// Forms: +// +// VCVTDQ2PD.Z m128 k ymm +// VCVTDQ2PD.Z m64 k xmm +// VCVTDQ2PD.Z xmm k xmm +// VCVTDQ2PD.Z xmm k ymm +// VCVTDQ2PD.Z m256 k zmm +// VCVTDQ2PD.Z ymm k zmm +func VCVTDQ2PD_Z(mxy, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTDQ2PD.Forms(), sffxs{sffxZ}, []operand.Op{mxy, k, xyz}) +} + +// VCVTDQ2PS: Convert Packed Dword Integers to Packed Single-Precision FP Values. +// +// Forms: +// +// VCVTDQ2PS m128 xmm +// VCVTDQ2PS m256 ymm +// VCVTDQ2PS xmm xmm +// VCVTDQ2PS ymm ymm +// VCVTDQ2PS m128 k xmm +// VCVTDQ2PS m256 k ymm +// VCVTDQ2PS xmm k xmm +// VCVTDQ2PS ymm k ymm +// VCVTDQ2PS m512 k zmm +// VCVTDQ2PS m512 zmm +// VCVTDQ2PS zmm k zmm +// VCVTDQ2PS zmm zmm +func VCVTDQ2PS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTDQ2PS.Forms(), sffxs{}, ops) +} + +// VCVTDQ2PS_BCST: Convert Packed Dword Integers to Packed Single-Precision FP Values (Broadcast). +// +// Forms: +// +// VCVTDQ2PS.BCST m32 k xmm +// VCVTDQ2PS.BCST m32 k ymm +// VCVTDQ2PS.BCST m32 xmm +// VCVTDQ2PS.BCST m32 ymm +// VCVTDQ2PS.BCST m32 k zmm +// VCVTDQ2PS.BCST m32 zmm +func VCVTDQ2PS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTDQ2PS.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTDQ2PS_BCST_Z: Convert Packed Dword Integers to Packed Single-Precision FP Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTDQ2PS.BCST.Z m32 k xmm +// VCVTDQ2PS.BCST.Z m32 k ymm +// VCVTDQ2PS.BCST.Z m32 k zmm +func VCVTDQ2PS_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTDQ2PS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) +} + +// VCVTDQ2PS_RD_SAE: Convert Packed Dword Integers to Packed Single-Precision FP Values (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTDQ2PS.RD_SAE zmm k zmm +// VCVTDQ2PS.RD_SAE zmm zmm +func VCVTDQ2PS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTDQ2PS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VCVTDQ2PS_RD_SAE_Z: Convert Packed Dword Integers to Packed Single-Precision FP Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTDQ2PS.RD_SAE.Z zmm k zmm +func VCVTDQ2PS_RD_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTDQ2PS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTDQ2PS_RN_SAE: Convert Packed Dword Integers to Packed Single-Precision FP Values (Round Towards Nearest). +// +// Forms: +// +// VCVTDQ2PS.RN_SAE zmm k zmm +// VCVTDQ2PS.RN_SAE zmm zmm +func VCVTDQ2PS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTDQ2PS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VCVTDQ2PS_RN_SAE_Z: Convert Packed Dword Integers to Packed Single-Precision FP Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTDQ2PS.RN_SAE.Z zmm k zmm +func VCVTDQ2PS_RN_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTDQ2PS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTDQ2PS_RU_SAE: Convert Packed Dword Integers to Packed Single-Precision FP Values (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTDQ2PS.RU_SAE zmm k zmm +// VCVTDQ2PS.RU_SAE zmm zmm +func VCVTDQ2PS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTDQ2PS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VCVTDQ2PS_RU_SAE_Z: Convert Packed Dword Integers to Packed Single-Precision FP Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTDQ2PS.RU_SAE.Z zmm k zmm +func VCVTDQ2PS_RU_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTDQ2PS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTDQ2PS_RZ_SAE: Convert Packed Dword Integers to Packed Single-Precision FP Values (Round Towards Zero). +// +// Forms: +// +// VCVTDQ2PS.RZ_SAE zmm k zmm +// VCVTDQ2PS.RZ_SAE zmm zmm +func VCVTDQ2PS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTDQ2PS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VCVTDQ2PS_RZ_SAE_Z: Convert Packed Dword Integers to Packed Single-Precision FP Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTDQ2PS.RZ_SAE.Z zmm k zmm +func VCVTDQ2PS_RZ_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTDQ2PS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTDQ2PS_Z: Convert Packed Dword Integers to Packed Single-Precision FP Values (Zeroing Masking). +// +// Forms: +// +// VCVTDQ2PS.Z m128 k xmm +// VCVTDQ2PS.Z m256 k ymm +// VCVTDQ2PS.Z xmm k xmm +// VCVTDQ2PS.Z ymm k ymm +// VCVTDQ2PS.Z m512 k zmm +// VCVTDQ2PS.Z zmm k zmm +func VCVTDQ2PS_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTDQ2PS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) +} + +// VCVTPD2DQ: Convert Packed Double-Precision FP Values to Packed Dword Integers. +// +// Forms: +// +// VCVTPD2DQ m512 k ymm +// VCVTPD2DQ m512 ymm +// VCVTPD2DQ zmm k ymm +// VCVTPD2DQ zmm ymm +func VCVTPD2DQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2DQ.Forms(), sffxs{}, ops) +} + +// VCVTPD2DQX: Convert Packed Double-Precision FP Values to Packed Dword Integers. +// +// Forms: +// +// VCVTPD2DQX m128 xmm +// VCVTPD2DQX xmm xmm +// VCVTPD2DQX m128 k xmm +// VCVTPD2DQX xmm k xmm +func VCVTPD2DQX(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2DQX.Forms(), sffxs{}, ops) +} + +// VCVTPD2DQX_BCST: Convert Packed Double-Precision FP Values to Packed Dword Integers (Broadcast). +// +// Forms: +// +// VCVTPD2DQX.BCST m64 k xmm +// VCVTPD2DQX.BCST m64 xmm +func VCVTPD2DQX_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2DQX.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTPD2DQX_BCST_Z: Convert Packed Double-Precision FP Values to Packed Dword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2DQX.BCST.Z m64 k xmm +func VCVTPD2DQX_BCST_Z(m, k, x operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2DQX.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, x}) +} + +// VCVTPD2DQX_Z: Convert Packed Double-Precision FP Values to Packed Dword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTPD2DQX.Z m128 k xmm +// VCVTPD2DQX.Z xmm k xmm +func VCVTPD2DQX_Z(mx, k, x operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2DQX.Forms(), sffxs{sffxZ}, []operand.Op{mx, k, x}) +} + +// VCVTPD2DQY: Convert Packed Double-Precision FP Values to Packed Dword Integers. +// +// Forms: +// +// VCVTPD2DQY m256 xmm +// VCVTPD2DQY ymm xmm +// VCVTPD2DQY m256 k xmm +// VCVTPD2DQY ymm k xmm +func VCVTPD2DQY(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2DQY.Forms(), sffxs{}, ops) +} + +// VCVTPD2DQY_BCST: Convert Packed Double-Precision FP Values to Packed Dword Integers (Broadcast). +// +// Forms: +// +// VCVTPD2DQY.BCST m64 k xmm +// VCVTPD2DQY.BCST m64 xmm +func VCVTPD2DQY_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2DQY.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTPD2DQY_BCST_Z: Convert Packed Double-Precision FP Values to Packed Dword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2DQY.BCST.Z m64 k xmm +func VCVTPD2DQY_BCST_Z(m, k, x operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2DQY.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, x}) +} + +// VCVTPD2DQY_Z: Convert Packed Double-Precision FP Values to Packed Dword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTPD2DQY.Z m256 k xmm +// VCVTPD2DQY.Z ymm k xmm +func VCVTPD2DQY_Z(my, k, x operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2DQY.Forms(), sffxs{sffxZ}, []operand.Op{my, k, x}) +} + +// VCVTPD2DQ_BCST: Convert Packed Double-Precision FP Values to Packed Dword Integers (Broadcast). +// +// Forms: +// +// VCVTPD2DQ.BCST m64 k ymm +// VCVTPD2DQ.BCST m64 ymm +func VCVTPD2DQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2DQ.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTPD2DQ_BCST_Z: Convert Packed Double-Precision FP Values to Packed Dword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2DQ.BCST.Z m64 k ymm +func VCVTPD2DQ_BCST_Z(m, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2DQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, y}) +} + +// VCVTPD2DQ_RD_SAE: Convert Packed Double-Precision FP Values to Packed Dword Integers (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTPD2DQ.RD_SAE zmm k ymm +// VCVTPD2DQ.RD_SAE zmm ymm +func VCVTPD2DQ_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2DQ.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VCVTPD2DQ_RD_SAE_Z: Convert Packed Double-Precision FP Values to Packed Dword Integers (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPD2DQ.RD_SAE.Z zmm k ymm +func VCVTPD2DQ_RD_SAE_Z(z, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2DQ.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, k, y}) +} + +// VCVTPD2DQ_RN_SAE: Convert Packed Double-Precision FP Values to Packed Dword Integers (Round Towards Nearest). +// +// Forms: +// +// VCVTPD2DQ.RN_SAE zmm k ymm +// VCVTPD2DQ.RN_SAE zmm ymm +func VCVTPD2DQ_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2DQ.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VCVTPD2DQ_RN_SAE_Z: Convert Packed Double-Precision FP Values to Packed Dword Integers (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTPD2DQ.RN_SAE.Z zmm k ymm +func VCVTPD2DQ_RN_SAE_Z(z, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2DQ.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, k, y}) +} + +// VCVTPD2DQ_RU_SAE: Convert Packed Double-Precision FP Values to Packed Dword Integers (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTPD2DQ.RU_SAE zmm k ymm +// VCVTPD2DQ.RU_SAE zmm ymm +func VCVTPD2DQ_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2DQ.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VCVTPD2DQ_RU_SAE_Z: Convert Packed Double-Precision FP Values to Packed Dword Integers (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPD2DQ.RU_SAE.Z zmm k ymm +func VCVTPD2DQ_RU_SAE_Z(z, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2DQ.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, k, y}) +} + +// VCVTPD2DQ_RZ_SAE: Convert Packed Double-Precision FP Values to Packed Dword Integers (Round Towards Zero). +// +// Forms: +// +// VCVTPD2DQ.RZ_SAE zmm k ymm +// VCVTPD2DQ.RZ_SAE zmm ymm +func VCVTPD2DQ_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2DQ.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VCVTPD2DQ_RZ_SAE_Z: Convert Packed Double-Precision FP Values to Packed Dword Integers (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTPD2DQ.RZ_SAE.Z zmm k ymm +func VCVTPD2DQ_RZ_SAE_Z(z, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2DQ.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, k, y}) +} + +// VCVTPD2DQ_Z: Convert Packed Double-Precision FP Values to Packed Dword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTPD2DQ.Z m512 k ymm +// VCVTPD2DQ.Z zmm k ymm +func VCVTPD2DQ_Z(mz, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2DQ.Forms(), sffxs{sffxZ}, []operand.Op{mz, k, y}) +} + +// VCVTPD2PS: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values. +// +// Forms: +// +// VCVTPD2PS m512 k ymm +// VCVTPD2PS m512 ymm +// VCVTPD2PS zmm k ymm +// VCVTPD2PS zmm ymm +func VCVTPD2PS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2PS.Forms(), sffxs{}, ops) +} + +// VCVTPD2PSX: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values. +// +// Forms: +// +// VCVTPD2PSX m128 xmm +// VCVTPD2PSX xmm xmm +// VCVTPD2PSX m128 k xmm +// VCVTPD2PSX xmm k xmm +func VCVTPD2PSX(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2PSX.Forms(), sffxs{}, ops) +} + +// VCVTPD2PSX_BCST: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Broadcast). +// +// Forms: +// +// VCVTPD2PSX.BCST m64 k xmm +// VCVTPD2PSX.BCST m64 xmm +func VCVTPD2PSX_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2PSX.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTPD2PSX_BCST_Z: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2PSX.BCST.Z m64 k xmm +func VCVTPD2PSX_BCST_Z(m, k, x operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2PSX.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, x}) +} + +// VCVTPD2PSX_Z: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Zeroing Masking). +// +// Forms: +// +// VCVTPD2PSX.Z m128 k xmm +// VCVTPD2PSX.Z xmm k xmm +func VCVTPD2PSX_Z(mx, k, x operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2PSX.Forms(), sffxs{sffxZ}, []operand.Op{mx, k, x}) +} + +// VCVTPD2PSY: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values. +// +// Forms: +// +// VCVTPD2PSY m256 xmm +// VCVTPD2PSY ymm xmm +// VCVTPD2PSY m256 k xmm +// VCVTPD2PSY ymm k xmm +func VCVTPD2PSY(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2PSY.Forms(), sffxs{}, ops) +} + +// VCVTPD2PSY_BCST: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Broadcast). +// +// Forms: +// +// VCVTPD2PSY.BCST m64 k xmm +// VCVTPD2PSY.BCST m64 xmm +func VCVTPD2PSY_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2PSY.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTPD2PSY_BCST_Z: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2PSY.BCST.Z m64 k xmm +func VCVTPD2PSY_BCST_Z(m, k, x operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2PSY.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, x}) +} + +// VCVTPD2PSY_Z: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Zeroing Masking). +// +// Forms: +// +// VCVTPD2PSY.Z m256 k xmm +// VCVTPD2PSY.Z ymm k xmm +func VCVTPD2PSY_Z(my, k, x operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2PSY.Forms(), sffxs{sffxZ}, []operand.Op{my, k, x}) +} + +// VCVTPD2PS_BCST: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Broadcast). +// +// Forms: +// +// VCVTPD2PS.BCST m64 k ymm +// VCVTPD2PS.BCST m64 ymm +func VCVTPD2PS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2PS.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTPD2PS_BCST_Z: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2PS.BCST.Z m64 k ymm +func VCVTPD2PS_BCST_Z(m, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2PS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, y}) +} + +// VCVTPD2PS_RD_SAE: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTPD2PS.RD_SAE zmm k ymm +// VCVTPD2PS.RD_SAE zmm ymm +func VCVTPD2PS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2PS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VCVTPD2PS_RD_SAE_Z: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPD2PS.RD_SAE.Z zmm k ymm +func VCVTPD2PS_RD_SAE_Z(z, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2PS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, k, y}) +} + +// VCVTPD2PS_RN_SAE: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Round Towards Nearest). +// +// Forms: +// +// VCVTPD2PS.RN_SAE zmm k ymm +// VCVTPD2PS.RN_SAE zmm ymm +func VCVTPD2PS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2PS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VCVTPD2PS_RN_SAE_Z: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTPD2PS.RN_SAE.Z zmm k ymm +func VCVTPD2PS_RN_SAE_Z(z, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2PS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, k, y}) +} + +// VCVTPD2PS_RU_SAE: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTPD2PS.RU_SAE zmm k ymm +// VCVTPD2PS.RU_SAE zmm ymm +func VCVTPD2PS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2PS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VCVTPD2PS_RU_SAE_Z: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPD2PS.RU_SAE.Z zmm k ymm +func VCVTPD2PS_RU_SAE_Z(z, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2PS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, k, y}) +} + +// VCVTPD2PS_RZ_SAE: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Round Towards Zero). +// +// Forms: +// +// VCVTPD2PS.RZ_SAE zmm k ymm +// VCVTPD2PS.RZ_SAE zmm ymm +func VCVTPD2PS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2PS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VCVTPD2PS_RZ_SAE_Z: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTPD2PS.RZ_SAE.Z zmm k ymm +func VCVTPD2PS_RZ_SAE_Z(z, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2PS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, k, y}) +} + +// VCVTPD2PS_Z: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values (Zeroing Masking). +// +// Forms: +// +// VCVTPD2PS.Z m512 k ymm +// VCVTPD2PS.Z zmm k ymm +func VCVTPD2PS_Z(mz, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2PS.Forms(), sffxs{sffxZ}, []operand.Op{mz, k, y}) +} + +// VCVTPD2QQ: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers. +// +// Forms: +// +// VCVTPD2QQ m128 k xmm +// VCVTPD2QQ m128 xmm +// VCVTPD2QQ m256 k ymm +// VCVTPD2QQ m256 ymm +// VCVTPD2QQ xmm k xmm +// VCVTPD2QQ xmm xmm +// VCVTPD2QQ ymm k ymm +// VCVTPD2QQ ymm ymm +// VCVTPD2QQ m512 k zmm +// VCVTPD2QQ m512 zmm +// VCVTPD2QQ zmm k zmm +// VCVTPD2QQ zmm zmm +func VCVTPD2QQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2QQ.Forms(), sffxs{}, ops) +} + +// VCVTPD2QQ_BCST: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Broadcast). +// +// Forms: +// +// VCVTPD2QQ.BCST m64 k xmm +// VCVTPD2QQ.BCST m64 k ymm +// VCVTPD2QQ.BCST m64 xmm +// VCVTPD2QQ.BCST m64 ymm +// VCVTPD2QQ.BCST m64 k zmm +// VCVTPD2QQ.BCST m64 zmm +func VCVTPD2QQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2QQ.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTPD2QQ_BCST_Z: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2QQ.BCST.Z m64 k xmm +// VCVTPD2QQ.BCST.Z m64 k ymm +// VCVTPD2QQ.BCST.Z m64 k zmm +func VCVTPD2QQ_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2QQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) +} + +// VCVTPD2QQ_RD_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTPD2QQ.RD_SAE zmm k zmm +// VCVTPD2QQ.RD_SAE zmm zmm +func VCVTPD2QQ_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2QQ.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VCVTPD2QQ_RD_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPD2QQ.RD_SAE.Z zmm k zmm +func VCVTPD2QQ_RD_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2QQ.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTPD2QQ_RN_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Round Towards Nearest). +// +// Forms: +// +// VCVTPD2QQ.RN_SAE zmm k zmm +// VCVTPD2QQ.RN_SAE zmm zmm +func VCVTPD2QQ_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2QQ.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VCVTPD2QQ_RN_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTPD2QQ.RN_SAE.Z zmm k zmm +func VCVTPD2QQ_RN_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2QQ.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTPD2QQ_RU_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTPD2QQ.RU_SAE zmm k zmm +// VCVTPD2QQ.RU_SAE zmm zmm +func VCVTPD2QQ_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2QQ.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VCVTPD2QQ_RU_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPD2QQ.RU_SAE.Z zmm k zmm +func VCVTPD2QQ_RU_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2QQ.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTPD2QQ_RZ_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Round Towards Zero). +// +// Forms: +// +// VCVTPD2QQ.RZ_SAE zmm k zmm +// VCVTPD2QQ.RZ_SAE zmm zmm +func VCVTPD2QQ_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2QQ.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VCVTPD2QQ_RZ_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTPD2QQ.RZ_SAE.Z zmm k zmm +func VCVTPD2QQ_RZ_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2QQ.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTPD2QQ_Z: Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTPD2QQ.Z m128 k xmm +// VCVTPD2QQ.Z m256 k ymm +// VCVTPD2QQ.Z xmm k xmm +// VCVTPD2QQ.Z ymm k ymm +// VCVTPD2QQ.Z m512 k zmm +// VCVTPD2QQ.Z zmm k zmm +func VCVTPD2QQ_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2QQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) +} + +// VCVTPD2UDQ: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers. +// +// Forms: +// +// VCVTPD2UDQ m512 k ymm +// VCVTPD2UDQ m512 ymm +// VCVTPD2UDQ zmm k ymm +// VCVTPD2UDQ zmm ymm +func VCVTPD2UDQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UDQ.Forms(), sffxs{}, ops) +} + +// VCVTPD2UDQX: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers. +// +// Forms: +// +// VCVTPD2UDQX m128 k xmm +// VCVTPD2UDQX m128 xmm +// VCVTPD2UDQX xmm k xmm +// VCVTPD2UDQX xmm xmm +func VCVTPD2UDQX(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UDQX.Forms(), sffxs{}, ops) +} + +// VCVTPD2UDQX_BCST: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast). +// +// Forms: +// +// VCVTPD2UDQX.BCST m64 k xmm +// VCVTPD2UDQX.BCST m64 xmm +func VCVTPD2UDQX_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UDQX.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTPD2UDQX_BCST_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UDQX.BCST.Z m64 k xmm +func VCVTPD2UDQX_BCST_Z(m, k, x operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UDQX.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, x}) +} + +// VCVTPD2UDQX_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTPD2UDQX.Z m128 k xmm +// VCVTPD2UDQX.Z xmm k xmm +func VCVTPD2UDQX_Z(mx, k, x operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UDQX.Forms(), sffxs{sffxZ}, []operand.Op{mx, k, x}) +} + +// VCVTPD2UDQY: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers. +// +// Forms: +// +// VCVTPD2UDQY m256 k xmm +// VCVTPD2UDQY m256 xmm +// VCVTPD2UDQY ymm k xmm +// VCVTPD2UDQY ymm xmm +func VCVTPD2UDQY(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UDQY.Forms(), sffxs{}, ops) +} + +// VCVTPD2UDQY_BCST: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast). +// +// Forms: +// +// VCVTPD2UDQY.BCST m64 k xmm +// VCVTPD2UDQY.BCST m64 xmm +func VCVTPD2UDQY_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UDQY.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTPD2UDQY_BCST_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UDQY.BCST.Z m64 k xmm +func VCVTPD2UDQY_BCST_Z(m, k, x operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UDQY.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, x}) +} + +// VCVTPD2UDQY_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTPD2UDQY.Z m256 k xmm +// VCVTPD2UDQY.Z ymm k xmm +func VCVTPD2UDQY_Z(my, k, x operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UDQY.Forms(), sffxs{sffxZ}, []operand.Op{my, k, x}) +} + +// VCVTPD2UDQ_BCST: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast). +// +// Forms: +// +// VCVTPD2UDQ.BCST m64 k ymm +// VCVTPD2UDQ.BCST m64 ymm +func VCVTPD2UDQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UDQ.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTPD2UDQ_BCST_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UDQ.BCST.Z m64 k ymm +func VCVTPD2UDQ_BCST_Z(m, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UDQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, y}) +} + +// VCVTPD2UDQ_RD_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTPD2UDQ.RD_SAE zmm k ymm +// VCVTPD2UDQ.RD_SAE zmm ymm +func VCVTPD2UDQ_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UDQ.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VCVTPD2UDQ_RD_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UDQ.RD_SAE.Z zmm k ymm +func VCVTPD2UDQ_RD_SAE_Z(z, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UDQ.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, k, y}) +} + +// VCVTPD2UDQ_RN_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Round Towards Nearest). +// +// Forms: +// +// VCVTPD2UDQ.RN_SAE zmm k ymm +// VCVTPD2UDQ.RN_SAE zmm ymm +func VCVTPD2UDQ_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UDQ.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VCVTPD2UDQ_RN_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UDQ.RN_SAE.Z zmm k ymm +func VCVTPD2UDQ_RN_SAE_Z(z, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UDQ.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, k, y}) +} + +// VCVTPD2UDQ_RU_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTPD2UDQ.RU_SAE zmm k ymm +// VCVTPD2UDQ.RU_SAE zmm ymm +func VCVTPD2UDQ_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UDQ.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VCVTPD2UDQ_RU_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UDQ.RU_SAE.Z zmm k ymm +func VCVTPD2UDQ_RU_SAE_Z(z, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UDQ.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, k, y}) +} + +// VCVTPD2UDQ_RZ_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Round Towards Zero). +// +// Forms: +// +// VCVTPD2UDQ.RZ_SAE zmm k ymm +// VCVTPD2UDQ.RZ_SAE zmm ymm +func VCVTPD2UDQ_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UDQ.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VCVTPD2UDQ_RZ_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UDQ.RZ_SAE.Z zmm k ymm +func VCVTPD2UDQ_RZ_SAE_Z(z, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UDQ.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, k, y}) +} + +// VCVTPD2UDQ_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTPD2UDQ.Z m512 k ymm +// VCVTPD2UDQ.Z zmm k ymm +func VCVTPD2UDQ_Z(mz, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UDQ.Forms(), sffxs{sffxZ}, []operand.Op{mz, k, y}) +} + +// VCVTPD2UQQ: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers. +// +// Forms: +// +// VCVTPD2UQQ m128 k xmm +// VCVTPD2UQQ m128 xmm +// VCVTPD2UQQ m256 k ymm +// VCVTPD2UQQ m256 ymm +// VCVTPD2UQQ xmm k xmm +// VCVTPD2UQQ xmm xmm +// VCVTPD2UQQ ymm k ymm +// VCVTPD2UQQ ymm ymm +// VCVTPD2UQQ m512 k zmm +// VCVTPD2UQQ m512 zmm +// VCVTPD2UQQ zmm k zmm +// VCVTPD2UQQ zmm zmm +func VCVTPD2UQQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UQQ.Forms(), sffxs{}, ops) +} + +// VCVTPD2UQQ_BCST: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Broadcast). +// +// Forms: +// +// VCVTPD2UQQ.BCST m64 k xmm +// VCVTPD2UQQ.BCST m64 k ymm +// VCVTPD2UQQ.BCST m64 xmm +// VCVTPD2UQQ.BCST m64 ymm +// VCVTPD2UQQ.BCST m64 k zmm +// VCVTPD2UQQ.BCST m64 zmm +func VCVTPD2UQQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UQQ.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTPD2UQQ_BCST_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UQQ.BCST.Z m64 k xmm +// VCVTPD2UQQ.BCST.Z m64 k ymm +// VCVTPD2UQQ.BCST.Z m64 k zmm +func VCVTPD2UQQ_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UQQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) +} + +// VCVTPD2UQQ_RD_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTPD2UQQ.RD_SAE zmm k zmm +// VCVTPD2UQQ.RD_SAE zmm zmm +func VCVTPD2UQQ_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UQQ.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VCVTPD2UQQ_RD_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UQQ.RD_SAE.Z zmm k zmm +func VCVTPD2UQQ_RD_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UQQ.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTPD2UQQ_RN_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Round Towards Nearest). +// +// Forms: +// +// VCVTPD2UQQ.RN_SAE zmm k zmm +// VCVTPD2UQQ.RN_SAE zmm zmm +func VCVTPD2UQQ_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UQQ.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VCVTPD2UQQ_RN_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UQQ.RN_SAE.Z zmm k zmm +func VCVTPD2UQQ_RN_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UQQ.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTPD2UQQ_RU_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTPD2UQQ.RU_SAE zmm k zmm +// VCVTPD2UQQ.RU_SAE zmm zmm +func VCVTPD2UQQ_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UQQ.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VCVTPD2UQQ_RU_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UQQ.RU_SAE.Z zmm k zmm +func VCVTPD2UQQ_RU_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UQQ.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTPD2UQQ_RZ_SAE: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Round Towards Zero). +// +// Forms: +// +// VCVTPD2UQQ.RZ_SAE zmm k zmm +// VCVTPD2UQQ.RZ_SAE zmm zmm +func VCVTPD2UQQ_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UQQ.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VCVTPD2UQQ_RZ_SAE_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTPD2UQQ.RZ_SAE.Z zmm k zmm +func VCVTPD2UQQ_RZ_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UQQ.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTPD2UQQ_Z: Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTPD2UQQ.Z m128 k xmm +// VCVTPD2UQQ.Z m256 k ymm +// VCVTPD2UQQ.Z xmm k xmm +// VCVTPD2UQQ.Z ymm k ymm +// VCVTPD2UQQ.Z m512 k zmm +// VCVTPD2UQQ.Z zmm k zmm +func VCVTPD2UQQ_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPD2UQQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) +} + +// VCVTPH2PS: Convert Half-Precision FP Values to Single-Precision FP Values. +// +// Forms: +// +// VCVTPH2PS m128 ymm +// VCVTPH2PS m64 xmm +// VCVTPH2PS xmm xmm +// VCVTPH2PS xmm ymm +// VCVTPH2PS m128 k ymm +// VCVTPH2PS m64 k xmm +// VCVTPH2PS xmm k xmm +// VCVTPH2PS xmm k ymm +// VCVTPH2PS m256 k zmm +// VCVTPH2PS m256 zmm +// VCVTPH2PS ymm k zmm +// VCVTPH2PS ymm zmm +func VCVTPH2PS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPH2PS.Forms(), sffxs{}, ops) +} + +// VCVTPH2PS_SAE: Convert Half-Precision FP Values to Single-Precision FP Values (Suppress All Exceptions). +// +// Forms: +// +// VCVTPH2PS.SAE ymm k zmm +// VCVTPH2PS.SAE ymm zmm +func VCVTPH2PS_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPH2PS.Forms(), sffxs{sffxSAE}, ops) +} + +// VCVTPH2PS_SAE_Z: Convert Half-Precision FP Values to Single-Precision FP Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTPH2PS.SAE.Z ymm k zmm +func VCVTPH2PS_SAE_Z(y, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPH2PS.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{y, k, z}) +} + +// VCVTPH2PS_Z: Convert Half-Precision FP Values to Single-Precision FP Values (Zeroing Masking). +// +// Forms: +// +// VCVTPH2PS.Z m128 k ymm +// VCVTPH2PS.Z m64 k xmm +// VCVTPH2PS.Z xmm k xmm +// VCVTPH2PS.Z xmm k ymm +// VCVTPH2PS.Z m256 k zmm +// VCVTPH2PS.Z ymm k zmm +func VCVTPH2PS_Z(mxy, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPH2PS.Forms(), sffxs{sffxZ}, []operand.Op{mxy, k, xyz}) +} + +// VCVTPS2DQ: Convert Packed Single-Precision FP Values to Packed Dword Integers. +// +// Forms: +// +// VCVTPS2DQ m128 xmm +// VCVTPS2DQ m256 ymm +// VCVTPS2DQ xmm xmm +// VCVTPS2DQ ymm ymm +// VCVTPS2DQ m128 k xmm +// VCVTPS2DQ m256 k ymm +// VCVTPS2DQ xmm k xmm +// VCVTPS2DQ ymm k ymm +// VCVTPS2DQ m512 k zmm +// VCVTPS2DQ m512 zmm +// VCVTPS2DQ zmm k zmm +// VCVTPS2DQ zmm zmm +func VCVTPS2DQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2DQ.Forms(), sffxs{}, ops) +} + +// VCVTPS2DQ_BCST: Convert Packed Single-Precision FP Values to Packed Dword Integers (Broadcast). +// +// Forms: +// +// VCVTPS2DQ.BCST m32 k xmm +// VCVTPS2DQ.BCST m32 k ymm +// VCVTPS2DQ.BCST m32 xmm +// VCVTPS2DQ.BCST m32 ymm +// VCVTPS2DQ.BCST m32 k zmm +// VCVTPS2DQ.BCST m32 zmm +func VCVTPS2DQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2DQ.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTPS2DQ_BCST_Z: Convert Packed Single-Precision FP Values to Packed Dword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPS2DQ.BCST.Z m32 k xmm +// VCVTPS2DQ.BCST.Z m32 k ymm +// VCVTPS2DQ.BCST.Z m32 k zmm +func VCVTPS2DQ_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2DQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) +} + +// VCVTPS2DQ_RD_SAE: Convert Packed Single-Precision FP Values to Packed Dword Integers (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTPS2DQ.RD_SAE zmm k zmm +// VCVTPS2DQ.RD_SAE zmm zmm +func VCVTPS2DQ_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2DQ.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VCVTPS2DQ_RD_SAE_Z: Convert Packed Single-Precision FP Values to Packed Dword Integers (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPS2DQ.RD_SAE.Z zmm k zmm +func VCVTPS2DQ_RD_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2DQ.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTPS2DQ_RN_SAE: Convert Packed Single-Precision FP Values to Packed Dword Integers (Round Towards Nearest). +// +// Forms: +// +// VCVTPS2DQ.RN_SAE zmm k zmm +// VCVTPS2DQ.RN_SAE zmm zmm +func VCVTPS2DQ_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2DQ.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VCVTPS2DQ_RN_SAE_Z: Convert Packed Single-Precision FP Values to Packed Dword Integers (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTPS2DQ.RN_SAE.Z zmm k zmm +func VCVTPS2DQ_RN_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2DQ.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTPS2DQ_RU_SAE: Convert Packed Single-Precision FP Values to Packed Dword Integers (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTPS2DQ.RU_SAE zmm k zmm +// VCVTPS2DQ.RU_SAE zmm zmm +func VCVTPS2DQ_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2DQ.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VCVTPS2DQ_RU_SAE_Z: Convert Packed Single-Precision FP Values to Packed Dword Integers (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPS2DQ.RU_SAE.Z zmm k zmm +func VCVTPS2DQ_RU_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2DQ.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTPS2DQ_RZ_SAE: Convert Packed Single-Precision FP Values to Packed Dword Integers (Round Towards Zero). +// +// Forms: +// +// VCVTPS2DQ.RZ_SAE zmm k zmm +// VCVTPS2DQ.RZ_SAE zmm zmm +func VCVTPS2DQ_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2DQ.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VCVTPS2DQ_RZ_SAE_Z: Convert Packed Single-Precision FP Values to Packed Dword Integers (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTPS2DQ.RZ_SAE.Z zmm k zmm +func VCVTPS2DQ_RZ_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2DQ.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTPS2DQ_Z: Convert Packed Single-Precision FP Values to Packed Dword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTPS2DQ.Z m128 k xmm +// VCVTPS2DQ.Z m256 k ymm +// VCVTPS2DQ.Z xmm k xmm +// VCVTPS2DQ.Z ymm k ymm +// VCVTPS2DQ.Z m512 k zmm +// VCVTPS2DQ.Z zmm k zmm +func VCVTPS2DQ_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2DQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) +} + +// VCVTPS2PD: Convert Packed Single-Precision FP Values to Packed Double-Precision FP Values. +// +// Forms: +// +// VCVTPS2PD m128 ymm +// VCVTPS2PD m64 xmm +// VCVTPS2PD xmm xmm +// VCVTPS2PD xmm ymm +// VCVTPS2PD m64 k xmm +// VCVTPS2PD xmm k xmm +// VCVTPS2PD m256 k zmm +// VCVTPS2PD m256 zmm +// VCVTPS2PD ymm k zmm +// VCVTPS2PD ymm zmm +// VCVTPS2PD m128 k ymm +// VCVTPS2PD xmm k ymm +func VCVTPS2PD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2PD.Forms(), sffxs{}, ops) +} + +// VCVTPS2PD_BCST: Convert Packed Single-Precision FP Values to Packed Double-Precision FP Values (Broadcast). +// +// Forms: +// +// VCVTPS2PD.BCST m32 k xmm +// VCVTPS2PD.BCST m32 xmm +// VCVTPS2PD.BCST m32 k zmm +// VCVTPS2PD.BCST m32 zmm +// VCVTPS2PD.BCST m32 k ymm +// VCVTPS2PD.BCST m32 ymm +func VCVTPS2PD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2PD.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTPS2PD_BCST_Z: Convert Packed Single-Precision FP Values to Packed Double-Precision FP Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPS2PD.BCST.Z m32 k xmm +// VCVTPS2PD.BCST.Z m32 k zmm +// VCVTPS2PD.BCST.Z m32 k ymm +func VCVTPS2PD_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2PD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) +} + +// VCVTPS2PD_SAE: Convert Packed Single-Precision FP Values to Packed Double-Precision FP Values (Suppress All Exceptions). +// +// Forms: +// +// VCVTPS2PD.SAE ymm k zmm +// VCVTPS2PD.SAE ymm zmm +func VCVTPS2PD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2PD.Forms(), sffxs{sffxSAE}, ops) +} + +// VCVTPS2PD_SAE_Z: Convert Packed Single-Precision FP Values to Packed Double-Precision FP Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTPS2PD.SAE.Z ymm k zmm +func VCVTPS2PD_SAE_Z(y, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2PD.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{y, k, z}) +} + +// VCVTPS2PD_Z: Convert Packed Single-Precision FP Values to Packed Double-Precision FP Values (Zeroing Masking). +// +// Forms: +// +// VCVTPS2PD.Z m64 k xmm +// VCVTPS2PD.Z xmm k xmm +// VCVTPS2PD.Z m256 k zmm +// VCVTPS2PD.Z ymm k zmm +// VCVTPS2PD.Z m128 k ymm +// VCVTPS2PD.Z xmm k ymm +func VCVTPS2PD_Z(mxy, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2PD.Forms(), sffxs{sffxZ}, []operand.Op{mxy, k, xyz}) +} + +// VCVTPS2PH: Convert Single-Precision FP value to Half-Precision FP value. +// +// Forms: +// +// VCVTPS2PH imm8 xmm m64 +// VCVTPS2PH imm8 xmm xmm +// VCVTPS2PH imm8 ymm m128 +// VCVTPS2PH imm8 ymm xmm +// VCVTPS2PH imm8 xmm k m64 +// VCVTPS2PH imm8 xmm k xmm +// VCVTPS2PH imm8 ymm k m128 +// VCVTPS2PH imm8 ymm k xmm +// VCVTPS2PH imm8 zmm k m256 +// VCVTPS2PH imm8 zmm k ymm +// VCVTPS2PH imm8 zmm m256 +// VCVTPS2PH imm8 zmm ymm +func VCVTPS2PH(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2PH.Forms(), sffxs{}, ops) +} + +// VCVTPS2PH_SAE: Convert Single-Precision FP value to Half-Precision FP value (Suppress All Exceptions). +// +// Forms: +// +// VCVTPS2PH.SAE imm8 zmm k ymm +// VCVTPS2PH.SAE imm8 zmm ymm +func VCVTPS2PH_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2PH.Forms(), sffxs{sffxSAE}, ops) +} + +// VCVTPS2PH_SAE_Z: Convert Single-Precision FP value to Half-Precision FP value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTPS2PH.SAE.Z imm8 zmm k ymm +func VCVTPS2PH_SAE_Z(i, z, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2PH.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{i, z, k, y}) +} + +// VCVTPS2PH_Z: Convert Single-Precision FP value to Half-Precision FP value (Zeroing Masking). +// +// Forms: +// +// VCVTPS2PH.Z imm8 xmm k m64 +// VCVTPS2PH.Z imm8 xmm k xmm +// VCVTPS2PH.Z imm8 ymm k m128 +// VCVTPS2PH.Z imm8 ymm k xmm +// VCVTPS2PH.Z imm8 zmm k m256 +// VCVTPS2PH.Z imm8 zmm k ymm +func VCVTPS2PH_Z(i, xyz, k, mxy operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2PH.Forms(), sffxs{sffxZ}, []operand.Op{i, xyz, k, mxy}) +} + +// VCVTPS2QQ: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values. +// +// Forms: +// +// VCVTPS2QQ m128 k ymm +// VCVTPS2QQ m128 ymm +// VCVTPS2QQ m64 k xmm +// VCVTPS2QQ m64 xmm +// VCVTPS2QQ xmm k xmm +// VCVTPS2QQ xmm k ymm +// VCVTPS2QQ xmm xmm +// VCVTPS2QQ xmm ymm +// VCVTPS2QQ m256 k zmm +// VCVTPS2QQ m256 zmm +// VCVTPS2QQ ymm k zmm +// VCVTPS2QQ ymm zmm +func VCVTPS2QQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2QQ.Forms(), sffxs{}, ops) +} + +// VCVTPS2QQ_BCST: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Broadcast). +// +// Forms: +// +// VCVTPS2QQ.BCST m32 k xmm +// VCVTPS2QQ.BCST m32 k ymm +// VCVTPS2QQ.BCST m32 xmm +// VCVTPS2QQ.BCST m32 ymm +// VCVTPS2QQ.BCST m32 k zmm +// VCVTPS2QQ.BCST m32 zmm +func VCVTPS2QQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2QQ.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTPS2QQ_BCST_Z: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPS2QQ.BCST.Z m32 k xmm +// VCVTPS2QQ.BCST.Z m32 k ymm +// VCVTPS2QQ.BCST.Z m32 k zmm +func VCVTPS2QQ_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2QQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) +} + +// VCVTPS2QQ_RD_SAE: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTPS2QQ.RD_SAE ymm k zmm +// VCVTPS2QQ.RD_SAE ymm zmm +func VCVTPS2QQ_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2QQ.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VCVTPS2QQ_RD_SAE_Z: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPS2QQ.RD_SAE.Z ymm k zmm +func VCVTPS2QQ_RD_SAE_Z(y, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2QQ.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{y, k, z}) +} + +// VCVTPS2QQ_RN_SAE: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Round Towards Nearest). +// +// Forms: +// +// VCVTPS2QQ.RN_SAE ymm k zmm +// VCVTPS2QQ.RN_SAE ymm zmm +func VCVTPS2QQ_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2QQ.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VCVTPS2QQ_RN_SAE_Z: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTPS2QQ.RN_SAE.Z ymm k zmm +func VCVTPS2QQ_RN_SAE_Z(y, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2QQ.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{y, k, z}) +} + +// VCVTPS2QQ_RU_SAE: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTPS2QQ.RU_SAE ymm k zmm +// VCVTPS2QQ.RU_SAE ymm zmm +func VCVTPS2QQ_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2QQ.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VCVTPS2QQ_RU_SAE_Z: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPS2QQ.RU_SAE.Z ymm k zmm +func VCVTPS2QQ_RU_SAE_Z(y, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2QQ.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{y, k, z}) +} + +// VCVTPS2QQ_RZ_SAE: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Round Towards Zero). +// +// Forms: +// +// VCVTPS2QQ.RZ_SAE ymm k zmm +// VCVTPS2QQ.RZ_SAE ymm zmm +func VCVTPS2QQ_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2QQ.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VCVTPS2QQ_RZ_SAE_Z: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTPS2QQ.RZ_SAE.Z ymm k zmm +func VCVTPS2QQ_RZ_SAE_Z(y, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2QQ.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{y, k, z}) +} + +// VCVTPS2QQ_Z: Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Zeroing Masking). +// +// Forms: +// +// VCVTPS2QQ.Z m128 k ymm +// VCVTPS2QQ.Z m64 k xmm +// VCVTPS2QQ.Z xmm k xmm +// VCVTPS2QQ.Z xmm k ymm +// VCVTPS2QQ.Z m256 k zmm +// VCVTPS2QQ.Z ymm k zmm +func VCVTPS2QQ_Z(mxy, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2QQ.Forms(), sffxs{sffxZ}, []operand.Op{mxy, k, xyz}) +} + +// VCVTPS2UDQ: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values. +// +// Forms: +// +// VCVTPS2UDQ m128 k xmm +// VCVTPS2UDQ m128 xmm +// VCVTPS2UDQ m256 k ymm +// VCVTPS2UDQ m256 ymm +// VCVTPS2UDQ xmm k xmm +// VCVTPS2UDQ xmm xmm +// VCVTPS2UDQ ymm k ymm +// VCVTPS2UDQ ymm ymm +// VCVTPS2UDQ m512 k zmm +// VCVTPS2UDQ m512 zmm +// VCVTPS2UDQ zmm k zmm +// VCVTPS2UDQ zmm zmm +func VCVTPS2UDQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2UDQ.Forms(), sffxs{}, ops) +} + +// VCVTPS2UDQ_BCST: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Broadcast). +// +// Forms: +// +// VCVTPS2UDQ.BCST m32 k xmm +// VCVTPS2UDQ.BCST m32 k ymm +// VCVTPS2UDQ.BCST m32 xmm +// VCVTPS2UDQ.BCST m32 ymm +// VCVTPS2UDQ.BCST m32 k zmm +// VCVTPS2UDQ.BCST m32 zmm +func VCVTPS2UDQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2UDQ.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTPS2UDQ_BCST_Z: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPS2UDQ.BCST.Z m32 k xmm +// VCVTPS2UDQ.BCST.Z m32 k ymm +// VCVTPS2UDQ.BCST.Z m32 k zmm +func VCVTPS2UDQ_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2UDQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) +} + +// VCVTPS2UDQ_RD_SAE: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTPS2UDQ.RD_SAE zmm k zmm +// VCVTPS2UDQ.RD_SAE zmm zmm +func VCVTPS2UDQ_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2UDQ.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VCVTPS2UDQ_RD_SAE_Z: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPS2UDQ.RD_SAE.Z zmm k zmm +func VCVTPS2UDQ_RD_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2UDQ.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTPS2UDQ_RN_SAE: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Round Towards Nearest). +// +// Forms: +// +// VCVTPS2UDQ.RN_SAE zmm k zmm +// VCVTPS2UDQ.RN_SAE zmm zmm +func VCVTPS2UDQ_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2UDQ.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VCVTPS2UDQ_RN_SAE_Z: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTPS2UDQ.RN_SAE.Z zmm k zmm +func VCVTPS2UDQ_RN_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2UDQ.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTPS2UDQ_RU_SAE: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTPS2UDQ.RU_SAE zmm k zmm +// VCVTPS2UDQ.RU_SAE zmm zmm +func VCVTPS2UDQ_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2UDQ.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VCVTPS2UDQ_RU_SAE_Z: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPS2UDQ.RU_SAE.Z zmm k zmm +func VCVTPS2UDQ_RU_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2UDQ.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTPS2UDQ_RZ_SAE: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Round Towards Zero). +// +// Forms: +// +// VCVTPS2UDQ.RZ_SAE zmm k zmm +// VCVTPS2UDQ.RZ_SAE zmm zmm +func VCVTPS2UDQ_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2UDQ.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VCVTPS2UDQ_RZ_SAE_Z: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTPS2UDQ.RZ_SAE.Z zmm k zmm +func VCVTPS2UDQ_RZ_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2UDQ.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTPS2UDQ_Z: Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Zeroing Masking). +// +// Forms: +// +// VCVTPS2UDQ.Z m128 k xmm +// VCVTPS2UDQ.Z m256 k ymm +// VCVTPS2UDQ.Z xmm k xmm +// VCVTPS2UDQ.Z ymm k ymm +// VCVTPS2UDQ.Z m512 k zmm +// VCVTPS2UDQ.Z zmm k zmm +func VCVTPS2UDQ_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2UDQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) +} + +// VCVTPS2UQQ: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values. +// +// Forms: +// +// VCVTPS2UQQ m128 k ymm +// VCVTPS2UQQ m128 ymm +// VCVTPS2UQQ m64 k xmm +// VCVTPS2UQQ m64 xmm +// VCVTPS2UQQ xmm k xmm +// VCVTPS2UQQ xmm k ymm +// VCVTPS2UQQ xmm xmm +// VCVTPS2UQQ xmm ymm +// VCVTPS2UQQ m256 k zmm +// VCVTPS2UQQ m256 zmm +// VCVTPS2UQQ ymm k zmm +// VCVTPS2UQQ ymm zmm +func VCVTPS2UQQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2UQQ.Forms(), sffxs{}, ops) +} + +// VCVTPS2UQQ_BCST: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Broadcast). +// +// Forms: +// +// VCVTPS2UQQ.BCST m32 k xmm +// VCVTPS2UQQ.BCST m32 k ymm +// VCVTPS2UQQ.BCST m32 xmm +// VCVTPS2UQQ.BCST m32 ymm +// VCVTPS2UQQ.BCST m32 k zmm +// VCVTPS2UQQ.BCST m32 zmm +func VCVTPS2UQQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2UQQ.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTPS2UQQ_BCST_Z: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTPS2UQQ.BCST.Z m32 k xmm +// VCVTPS2UQQ.BCST.Z m32 k ymm +// VCVTPS2UQQ.BCST.Z m32 k zmm +func VCVTPS2UQQ_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2UQQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) +} + +// VCVTPS2UQQ_RD_SAE: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTPS2UQQ.RD_SAE ymm k zmm +// VCVTPS2UQQ.RD_SAE ymm zmm +func VCVTPS2UQQ_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2UQQ.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VCVTPS2UQQ_RD_SAE_Z: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPS2UQQ.RD_SAE.Z ymm k zmm +func VCVTPS2UQQ_RD_SAE_Z(y, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2UQQ.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{y, k, z}) +} + +// VCVTPS2UQQ_RN_SAE: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Round Towards Nearest). +// +// Forms: +// +// VCVTPS2UQQ.RN_SAE ymm k zmm +// VCVTPS2UQQ.RN_SAE ymm zmm +func VCVTPS2UQQ_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2UQQ.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VCVTPS2UQQ_RN_SAE_Z: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTPS2UQQ.RN_SAE.Z ymm k zmm +func VCVTPS2UQQ_RN_SAE_Z(y, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2UQQ.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{y, k, z}) +} + +// VCVTPS2UQQ_RU_SAE: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTPS2UQQ.RU_SAE ymm k zmm +// VCVTPS2UQQ.RU_SAE ymm zmm +func VCVTPS2UQQ_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2UQQ.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VCVTPS2UQQ_RU_SAE_Z: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTPS2UQQ.RU_SAE.Z ymm k zmm +func VCVTPS2UQQ_RU_SAE_Z(y, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2UQQ.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{y, k, z}) +} + +// VCVTPS2UQQ_RZ_SAE: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Round Towards Zero). +// +// Forms: +// +// VCVTPS2UQQ.RZ_SAE ymm k zmm +// VCVTPS2UQQ.RZ_SAE ymm zmm +func VCVTPS2UQQ_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2UQQ.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VCVTPS2UQQ_RZ_SAE_Z: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTPS2UQQ.RZ_SAE.Z ymm k zmm +func VCVTPS2UQQ_RZ_SAE_Z(y, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2UQQ.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{y, k, z}) +} + +// VCVTPS2UQQ_Z: Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Zeroing Masking). +// +// Forms: +// +// VCVTPS2UQQ.Z m128 k ymm +// VCVTPS2UQQ.Z m64 k xmm +// VCVTPS2UQQ.Z xmm k xmm +// VCVTPS2UQQ.Z xmm k ymm +// VCVTPS2UQQ.Z m256 k zmm +// VCVTPS2UQQ.Z ymm k zmm +func VCVTPS2UQQ_Z(mxy, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTPS2UQQ.Forms(), sffxs{sffxZ}, []operand.Op{mxy, k, xyz}) +} + +// VCVTQQ2PD: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VCVTQQ2PD m128 k xmm +// VCVTQQ2PD m128 xmm +// VCVTQQ2PD m256 k ymm +// VCVTQQ2PD m256 ymm +// VCVTQQ2PD xmm k xmm +// VCVTQQ2PD xmm xmm +// VCVTQQ2PD ymm k ymm +// VCVTQQ2PD ymm ymm +// VCVTQQ2PD m512 k zmm +// VCVTQQ2PD m512 zmm +// VCVTQQ2PD zmm k zmm +// VCVTQQ2PD zmm zmm +func VCVTQQ2PD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PD.Forms(), sffxs{}, ops) +} + +// VCVTQQ2PD_BCST: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCVTQQ2PD.BCST m64 k xmm +// VCVTQQ2PD.BCST m64 k ymm +// VCVTQQ2PD.BCST m64 xmm +// VCVTQQ2PD.BCST m64 ymm +// VCVTQQ2PD.BCST m64 k zmm +// VCVTQQ2PD.BCST m64 zmm +func VCVTQQ2PD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PD.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTQQ2PD_BCST_Z: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PD.BCST.Z m64 k xmm +// VCVTQQ2PD.BCST.Z m64 k ymm +// VCVTQQ2PD.BCST.Z m64 k zmm +func VCVTQQ2PD_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) +} + +// VCVTQQ2PD_RD_SAE: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTQQ2PD.RD_SAE zmm k zmm +// VCVTQQ2PD.RD_SAE zmm zmm +func VCVTQQ2PD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VCVTQQ2PD_RD_SAE_Z: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PD.RD_SAE.Z zmm k zmm +func VCVTQQ2PD_RD_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTQQ2PD_RN_SAE: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VCVTQQ2PD.RN_SAE zmm k zmm +// VCVTQQ2PD.RN_SAE zmm zmm +func VCVTQQ2PD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VCVTQQ2PD_RN_SAE_Z: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PD.RN_SAE.Z zmm k zmm +func VCVTQQ2PD_RN_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTQQ2PD_RU_SAE: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTQQ2PD.RU_SAE zmm k zmm +// VCVTQQ2PD.RU_SAE zmm zmm +func VCVTQQ2PD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VCVTQQ2PD_RU_SAE_Z: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PD.RU_SAE.Z zmm k zmm +func VCVTQQ2PD_RU_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTQQ2PD_RZ_SAE: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VCVTQQ2PD.RZ_SAE zmm k zmm +// VCVTQQ2PD.RZ_SAE zmm zmm +func VCVTQQ2PD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VCVTQQ2PD_RZ_SAE_Z: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PD.RZ_SAE.Z zmm k zmm +func VCVTQQ2PD_RZ_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTQQ2PD_Z: Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PD.Z m128 k xmm +// VCVTQQ2PD.Z m256 k ymm +// VCVTQQ2PD.Z xmm k xmm +// VCVTQQ2PD.Z ymm k ymm +// VCVTQQ2PD.Z m512 k zmm +// VCVTQQ2PD.Z zmm k zmm +func VCVTQQ2PD_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) +} + +// VCVTQQ2PS: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VCVTQQ2PS m512 k ymm +// VCVTQQ2PS m512 ymm +// VCVTQQ2PS zmm k ymm +// VCVTQQ2PS zmm ymm +func VCVTQQ2PS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PS.Forms(), sffxs{}, ops) +} + +// VCVTQQ2PSX: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VCVTQQ2PSX m128 k xmm +// VCVTQQ2PSX m128 xmm +// VCVTQQ2PSX xmm k xmm +// VCVTQQ2PSX xmm xmm +func VCVTQQ2PSX(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PSX.Forms(), sffxs{}, ops) +} + +// VCVTQQ2PSX_BCST: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCVTQQ2PSX.BCST m64 k xmm +// VCVTQQ2PSX.BCST m64 xmm +func VCVTQQ2PSX_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PSX.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTQQ2PSX_BCST_Z: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PSX.BCST.Z m64 k xmm +func VCVTQQ2PSX_BCST_Z(m, k, x operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PSX.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, x}) +} + +// VCVTQQ2PSX_Z: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PSX.Z m128 k xmm +// VCVTQQ2PSX.Z xmm k xmm +func VCVTQQ2PSX_Z(mx, k, x operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PSX.Forms(), sffxs{sffxZ}, []operand.Op{mx, k, x}) +} + +// VCVTQQ2PSY: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VCVTQQ2PSY m256 k xmm +// VCVTQQ2PSY m256 xmm +// VCVTQQ2PSY ymm k xmm +// VCVTQQ2PSY ymm xmm +func VCVTQQ2PSY(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PSY.Forms(), sffxs{}, ops) +} + +// VCVTQQ2PSY_BCST: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCVTQQ2PSY.BCST m64 k xmm +// VCVTQQ2PSY.BCST m64 xmm +func VCVTQQ2PSY_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PSY.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTQQ2PSY_BCST_Z: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PSY.BCST.Z m64 k xmm +func VCVTQQ2PSY_BCST_Z(m, k, x operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PSY.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, x}) +} + +// VCVTQQ2PSY_Z: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PSY.Z m256 k xmm +// VCVTQQ2PSY.Z ymm k xmm +func VCVTQQ2PSY_Z(my, k, x operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PSY.Forms(), sffxs{sffxZ}, []operand.Op{my, k, x}) +} + +// VCVTQQ2PS_BCST: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCVTQQ2PS.BCST m64 k ymm +// VCVTQQ2PS.BCST m64 ymm +func VCVTQQ2PS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PS.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTQQ2PS_BCST_Z: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PS.BCST.Z m64 k ymm +func VCVTQQ2PS_BCST_Z(m, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, y}) +} + +// VCVTQQ2PS_RD_SAE: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTQQ2PS.RD_SAE zmm k ymm +// VCVTQQ2PS.RD_SAE zmm ymm +func VCVTQQ2PS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VCVTQQ2PS_RD_SAE_Z: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PS.RD_SAE.Z zmm k ymm +func VCVTQQ2PS_RD_SAE_Z(z, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, k, y}) +} + +// VCVTQQ2PS_RN_SAE: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VCVTQQ2PS.RN_SAE zmm k ymm +// VCVTQQ2PS.RN_SAE zmm ymm +func VCVTQQ2PS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VCVTQQ2PS_RN_SAE_Z: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PS.RN_SAE.Z zmm k ymm +func VCVTQQ2PS_RN_SAE_Z(z, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, k, y}) +} + +// VCVTQQ2PS_RU_SAE: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTQQ2PS.RU_SAE zmm k ymm +// VCVTQQ2PS.RU_SAE zmm ymm +func VCVTQQ2PS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VCVTQQ2PS_RU_SAE_Z: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PS.RU_SAE.Z zmm k ymm +func VCVTQQ2PS_RU_SAE_Z(z, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, k, y}) +} + +// VCVTQQ2PS_RZ_SAE: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VCVTQQ2PS.RZ_SAE zmm k ymm +// VCVTQQ2PS.RZ_SAE zmm ymm +func VCVTQQ2PS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VCVTQQ2PS_RZ_SAE_Z: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PS.RZ_SAE.Z zmm k ymm +func VCVTQQ2PS_RZ_SAE_Z(z, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, k, y}) +} + +// VCVTQQ2PS_Z: Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VCVTQQ2PS.Z m512 k ymm +// VCVTQQ2PS.Z zmm k ymm +func VCVTQQ2PS_Z(mz, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTQQ2PS.Forms(), sffxs{sffxZ}, []operand.Op{mz, k, y}) +} + +// VCVTSD2SI: Convert Scalar Double-Precision FP Value to Integer. +// +// Forms: +// +// VCVTSD2SI m64 r32 +// VCVTSD2SI xmm r32 +func VCVTSD2SI(mx, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSD2SI.Forms(), sffxs{}, []operand.Op{mx, r}) +} + +// VCVTSD2SIQ: Convert Scalar Double-Precision FP Value to Integer. +// +// Forms: +// +// VCVTSD2SIQ m64 r64 +// VCVTSD2SIQ xmm r64 +func VCVTSD2SIQ(mx, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSD2SIQ.Forms(), sffxs{}, []operand.Op{mx, r}) +} + +// VCVTSD2SIQ_RD_SAE: Convert Scalar Double-Precision FP Value to Integer (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSD2SIQ.RD_SAE xmm r64 +func VCVTSD2SIQ_RD_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSD2SIQ.Forms(), sffxs{sffxRD_SAE}, []operand.Op{x, r}) +} + +// VCVTSD2SIQ_RN_SAE: Convert Scalar Double-Precision FP Value to Integer (Round Towards Nearest). +// +// Forms: +// +// VCVTSD2SIQ.RN_SAE xmm r64 +func VCVTSD2SIQ_RN_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSD2SIQ.Forms(), sffxs{sffxRN_SAE}, []operand.Op{x, r}) +} + +// VCVTSD2SIQ_RU_SAE: Convert Scalar Double-Precision FP Value to Integer (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSD2SIQ.RU_SAE xmm r64 +func VCVTSD2SIQ_RU_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSD2SIQ.Forms(), sffxs{sffxRU_SAE}, []operand.Op{x, r}) +} + +// VCVTSD2SIQ_RZ_SAE: Convert Scalar Double-Precision FP Value to Integer (Round Towards Zero). +// +// Forms: +// +// VCVTSD2SIQ.RZ_SAE xmm r64 +func VCVTSD2SIQ_RZ_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSD2SIQ.Forms(), sffxs{sffxRZ_SAE}, []operand.Op{x, r}) +} + +// VCVTSD2SI_RD_SAE: Convert Scalar Double-Precision FP Value to Integer (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSD2SI.RD_SAE xmm r32 +func VCVTSD2SI_RD_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSD2SI.Forms(), sffxs{sffxRD_SAE}, []operand.Op{x, r}) +} + +// VCVTSD2SI_RN_SAE: Convert Scalar Double-Precision FP Value to Integer (Round Towards Nearest). +// +// Forms: +// +// VCVTSD2SI.RN_SAE xmm r32 +func VCVTSD2SI_RN_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSD2SI.Forms(), sffxs{sffxRN_SAE}, []operand.Op{x, r}) +} + +// VCVTSD2SI_RU_SAE: Convert Scalar Double-Precision FP Value to Integer (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSD2SI.RU_SAE xmm r32 +func VCVTSD2SI_RU_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSD2SI.Forms(), sffxs{sffxRU_SAE}, []operand.Op{x, r}) +} + +// VCVTSD2SI_RZ_SAE: Convert Scalar Double-Precision FP Value to Integer (Round Towards Zero). +// +// Forms: +// +// VCVTSD2SI.RZ_SAE xmm r32 +func VCVTSD2SI_RZ_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSD2SI.Forms(), sffxs{sffxRZ_SAE}, []operand.Op{x, r}) +} + +// VCVTSD2SS: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value. +// +// Forms: +// +// VCVTSD2SS m64 xmm xmm +// VCVTSD2SS xmm xmm xmm +// VCVTSD2SS m64 xmm k xmm +// VCVTSD2SS xmm xmm k xmm +func VCVTSD2SS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSD2SS.Forms(), sffxs{}, ops) +} + +// VCVTSD2SS_RD_SAE: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSD2SS.RD_SAE xmm xmm k xmm +// VCVTSD2SS.RD_SAE xmm xmm xmm +func VCVTSD2SS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSD2SS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VCVTSD2SS_RD_SAE_Z: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTSD2SS.RD_SAE.Z xmm xmm k xmm +func VCVTSD2SS_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSD2SS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VCVTSD2SS_RN_SAE: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value (Round Towards Nearest). +// +// Forms: +// +// VCVTSD2SS.RN_SAE xmm xmm k xmm +// VCVTSD2SS.RN_SAE xmm xmm xmm +func VCVTSD2SS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSD2SS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VCVTSD2SS_RN_SAE_Z: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTSD2SS.RN_SAE.Z xmm xmm k xmm +func VCVTSD2SS_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSD2SS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VCVTSD2SS_RU_SAE: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSD2SS.RU_SAE xmm xmm k xmm +// VCVTSD2SS.RU_SAE xmm xmm xmm +func VCVTSD2SS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSD2SS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VCVTSD2SS_RU_SAE_Z: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTSD2SS.RU_SAE.Z xmm xmm k xmm +func VCVTSD2SS_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSD2SS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VCVTSD2SS_RZ_SAE: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value (Round Towards Zero). +// +// Forms: +// +// VCVTSD2SS.RZ_SAE xmm xmm k xmm +// VCVTSD2SS.RZ_SAE xmm xmm xmm +func VCVTSD2SS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSD2SS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VCVTSD2SS_RZ_SAE_Z: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTSD2SS.RZ_SAE.Z xmm xmm k xmm +func VCVTSD2SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSD2SS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VCVTSD2SS_Z: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value (Zeroing Masking). +// +// Forms: +// +// VCVTSD2SS.Z m64 xmm k xmm +// VCVTSD2SS.Z xmm xmm k xmm +func VCVTSD2SS_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSD2SS.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VCVTSD2USIL: Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer. +// +// Forms: +// +// VCVTSD2USIL m64 r32 +// VCVTSD2USIL xmm r32 +func VCVTSD2USIL(mx, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSD2USIL.Forms(), sffxs{}, []operand.Op{mx, r}) +} + +// VCVTSD2USIL_RD_SAE: Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSD2USIL.RD_SAE xmm r32 +func VCVTSD2USIL_RD_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSD2USIL.Forms(), sffxs{sffxRD_SAE}, []operand.Op{x, r}) +} + +// VCVTSD2USIL_RN_SAE: Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Nearest). +// +// Forms: +// +// VCVTSD2USIL.RN_SAE xmm r32 +func VCVTSD2USIL_RN_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSD2USIL.Forms(), sffxs{sffxRN_SAE}, []operand.Op{x, r}) +} + +// VCVTSD2USIL_RU_SAE: Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSD2USIL.RU_SAE xmm r32 +func VCVTSD2USIL_RU_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSD2USIL.Forms(), sffxs{sffxRU_SAE}, []operand.Op{x, r}) +} + +// VCVTSD2USIL_RZ_SAE: Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Zero). +// +// Forms: +// +// VCVTSD2USIL.RZ_SAE xmm r32 +func VCVTSD2USIL_RZ_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSD2USIL.Forms(), sffxs{sffxRZ_SAE}, []operand.Op{x, r}) +} + +// VCVTSD2USIQ: Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer. +// +// Forms: +// +// VCVTSD2USIQ m64 r64 +// VCVTSD2USIQ xmm r64 +func VCVTSD2USIQ(mx, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSD2USIQ.Forms(), sffxs{}, []operand.Op{mx, r}) +} + +// VCVTSD2USIQ_RD_SAE: Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSD2USIQ.RD_SAE xmm r64 +func VCVTSD2USIQ_RD_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSD2USIQ.Forms(), sffxs{sffxRD_SAE}, []operand.Op{x, r}) +} + +// VCVTSD2USIQ_RN_SAE: Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Nearest). +// +// Forms: +// +// VCVTSD2USIQ.RN_SAE xmm r64 +func VCVTSD2USIQ_RN_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSD2USIQ.Forms(), sffxs{sffxRN_SAE}, []operand.Op{x, r}) +} + +// VCVTSD2USIQ_RU_SAE: Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSD2USIQ.RU_SAE xmm r64 +func VCVTSD2USIQ_RU_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSD2USIQ.Forms(), sffxs{sffxRU_SAE}, []operand.Op{x, r}) +} + +// VCVTSD2USIQ_RZ_SAE: Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Zero). +// +// Forms: +// +// VCVTSD2USIQ.RZ_SAE xmm r64 +func VCVTSD2USIQ_RZ_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSD2USIQ.Forms(), sffxs{sffxRZ_SAE}, []operand.Op{x, r}) +} + +// VCVTSI2SDL: Convert Dword Integer to Scalar Double-Precision FP Value. +// +// Forms: +// +// VCVTSI2SDL m32 xmm xmm +// VCVTSI2SDL r32 xmm xmm +func VCVTSI2SDL(mr, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSI2SDL.Forms(), sffxs{}, []operand.Op{mr, x, x1}) +} + +// VCVTSI2SDQ: Convert Dword Integer to Scalar Double-Precision FP Value. +// +// Forms: +// +// VCVTSI2SDQ m64 xmm xmm +// VCVTSI2SDQ r64 xmm xmm +func VCVTSI2SDQ(mr, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSI2SDQ.Forms(), sffxs{}, []operand.Op{mr, x, x1}) +} + +// VCVTSI2SDQ_RD_SAE: Convert Dword Integer to Scalar Double-Precision FP Value (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSI2SDQ.RD_SAE r64 xmm xmm +func VCVTSI2SDQ_RD_SAE(r, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSI2SDQ.Forms(), sffxs{sffxRD_SAE}, []operand.Op{r, x, x1}) +} + +// VCVTSI2SDQ_RN_SAE: Convert Dword Integer to Scalar Double-Precision FP Value (Round Towards Nearest). +// +// Forms: +// +// VCVTSI2SDQ.RN_SAE r64 xmm xmm +func VCVTSI2SDQ_RN_SAE(r, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSI2SDQ.Forms(), sffxs{sffxRN_SAE}, []operand.Op{r, x, x1}) +} + +// VCVTSI2SDQ_RU_SAE: Convert Dword Integer to Scalar Double-Precision FP Value (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSI2SDQ.RU_SAE r64 xmm xmm +func VCVTSI2SDQ_RU_SAE(r, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSI2SDQ.Forms(), sffxs{sffxRU_SAE}, []operand.Op{r, x, x1}) +} + +// VCVTSI2SDQ_RZ_SAE: Convert Dword Integer to Scalar Double-Precision FP Value (Round Towards Zero). +// +// Forms: +// +// VCVTSI2SDQ.RZ_SAE r64 xmm xmm +func VCVTSI2SDQ_RZ_SAE(r, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSI2SDQ.Forms(), sffxs{sffxRZ_SAE}, []operand.Op{r, x, x1}) +} + +// VCVTSI2SSL: Convert Dword Integer to Scalar Single-Precision FP Value. +// +// Forms: +// +// VCVTSI2SSL m32 xmm xmm +// VCVTSI2SSL r32 xmm xmm +func VCVTSI2SSL(mr, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSI2SSL.Forms(), sffxs{}, []operand.Op{mr, x, x1}) +} + +// VCVTSI2SSL_RD_SAE: Convert Dword Integer to Scalar Single-Precision FP Value (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSI2SSL.RD_SAE r32 xmm xmm +func VCVTSI2SSL_RD_SAE(r, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSI2SSL.Forms(), sffxs{sffxRD_SAE}, []operand.Op{r, x, x1}) +} + +// VCVTSI2SSL_RN_SAE: Convert Dword Integer to Scalar Single-Precision FP Value (Round Towards Nearest). +// +// Forms: +// +// VCVTSI2SSL.RN_SAE r32 xmm xmm +func VCVTSI2SSL_RN_SAE(r, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSI2SSL.Forms(), sffxs{sffxRN_SAE}, []operand.Op{r, x, x1}) +} + +// VCVTSI2SSL_RU_SAE: Convert Dword Integer to Scalar Single-Precision FP Value (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSI2SSL.RU_SAE r32 xmm xmm +func VCVTSI2SSL_RU_SAE(r, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSI2SSL.Forms(), sffxs{sffxRU_SAE}, []operand.Op{r, x, x1}) +} + +// VCVTSI2SSL_RZ_SAE: Convert Dword Integer to Scalar Single-Precision FP Value (Round Towards Zero). +// +// Forms: +// +// VCVTSI2SSL.RZ_SAE r32 xmm xmm +func VCVTSI2SSL_RZ_SAE(r, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSI2SSL.Forms(), sffxs{sffxRZ_SAE}, []operand.Op{r, x, x1}) +} + +// VCVTSI2SSQ: Convert Dword Integer to Scalar Single-Precision FP Value. +// +// Forms: +// +// VCVTSI2SSQ m64 xmm xmm +// VCVTSI2SSQ r64 xmm xmm +func VCVTSI2SSQ(mr, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSI2SSQ.Forms(), sffxs{}, []operand.Op{mr, x, x1}) +} + +// VCVTSI2SSQ_RD_SAE: Convert Dword Integer to Scalar Single-Precision FP Value (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSI2SSQ.RD_SAE r64 xmm xmm +func VCVTSI2SSQ_RD_SAE(r, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSI2SSQ.Forms(), sffxs{sffxRD_SAE}, []operand.Op{r, x, x1}) +} + +// VCVTSI2SSQ_RN_SAE: Convert Dword Integer to Scalar Single-Precision FP Value (Round Towards Nearest). +// +// Forms: +// +// VCVTSI2SSQ.RN_SAE r64 xmm xmm +func VCVTSI2SSQ_RN_SAE(r, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSI2SSQ.Forms(), sffxs{sffxRN_SAE}, []operand.Op{r, x, x1}) +} + +// VCVTSI2SSQ_RU_SAE: Convert Dword Integer to Scalar Single-Precision FP Value (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSI2SSQ.RU_SAE r64 xmm xmm +func VCVTSI2SSQ_RU_SAE(r, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSI2SSQ.Forms(), sffxs{sffxRU_SAE}, []operand.Op{r, x, x1}) +} + +// VCVTSI2SSQ_RZ_SAE: Convert Dword Integer to Scalar Single-Precision FP Value (Round Towards Zero). +// +// Forms: +// +// VCVTSI2SSQ.RZ_SAE r64 xmm xmm +func VCVTSI2SSQ_RZ_SAE(r, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSI2SSQ.Forms(), sffxs{sffxRZ_SAE}, []operand.Op{r, x, x1}) +} + +// VCVTSS2SD: Convert Scalar Single-Precision FP Value to Scalar Double-Precision FP Value. +// +// Forms: +// +// VCVTSS2SD m32 xmm xmm +// VCVTSS2SD xmm xmm xmm +// VCVTSS2SD m32 xmm k xmm +// VCVTSS2SD xmm xmm k xmm +func VCVTSS2SD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSS2SD.Forms(), sffxs{}, ops) +} + +// VCVTSS2SD_SAE: Convert Scalar Single-Precision FP Value to Scalar Double-Precision FP Value (Suppress All Exceptions). +// +// Forms: +// +// VCVTSS2SD.SAE xmm xmm k xmm +// VCVTSS2SD.SAE xmm xmm xmm +func VCVTSS2SD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSS2SD.Forms(), sffxs{sffxSAE}, ops) +} + +// VCVTSS2SD_SAE_Z: Convert Scalar Single-Precision FP Value to Scalar Double-Precision FP Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTSS2SD.SAE.Z xmm xmm k xmm +func VCVTSS2SD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSS2SD.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VCVTSS2SD_Z: Convert Scalar Single-Precision FP Value to Scalar Double-Precision FP Value (Zeroing Masking). +// +// Forms: +// +// VCVTSS2SD.Z m32 xmm k xmm +// VCVTSS2SD.Z xmm xmm k xmm +func VCVTSS2SD_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSS2SD.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VCVTSS2SI: Convert Scalar Single-Precision FP Value to Dword Integer. +// +// Forms: +// +// VCVTSS2SI m32 r32 +// VCVTSS2SI xmm r32 +func VCVTSS2SI(mx, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSS2SI.Forms(), sffxs{}, []operand.Op{mx, r}) +} + +// VCVTSS2SIQ: Convert Scalar Single-Precision FP Value to Dword Integer. +// +// Forms: +// +// VCVTSS2SIQ m32 r64 +// VCVTSS2SIQ xmm r64 +func VCVTSS2SIQ(mx, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSS2SIQ.Forms(), sffxs{}, []operand.Op{mx, r}) +} + +// VCVTSS2SIQ_RD_SAE: Convert Scalar Single-Precision FP Value to Dword Integer (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSS2SIQ.RD_SAE xmm r64 +func VCVTSS2SIQ_RD_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSS2SIQ.Forms(), sffxs{sffxRD_SAE}, []operand.Op{x, r}) +} + +// VCVTSS2SIQ_RN_SAE: Convert Scalar Single-Precision FP Value to Dword Integer (Round Towards Nearest). +// +// Forms: +// +// VCVTSS2SIQ.RN_SAE xmm r64 +func VCVTSS2SIQ_RN_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSS2SIQ.Forms(), sffxs{sffxRN_SAE}, []operand.Op{x, r}) +} + +// VCVTSS2SIQ_RU_SAE: Convert Scalar Single-Precision FP Value to Dword Integer (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSS2SIQ.RU_SAE xmm r64 +func VCVTSS2SIQ_RU_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSS2SIQ.Forms(), sffxs{sffxRU_SAE}, []operand.Op{x, r}) +} + +// VCVTSS2SIQ_RZ_SAE: Convert Scalar Single-Precision FP Value to Dword Integer (Round Towards Zero). +// +// Forms: +// +// VCVTSS2SIQ.RZ_SAE xmm r64 +func VCVTSS2SIQ_RZ_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSS2SIQ.Forms(), sffxs{sffxRZ_SAE}, []operand.Op{x, r}) +} + +// VCVTSS2SI_RD_SAE: Convert Scalar Single-Precision FP Value to Dword Integer (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSS2SI.RD_SAE xmm r32 +func VCVTSS2SI_RD_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSS2SI.Forms(), sffxs{sffxRD_SAE}, []operand.Op{x, r}) +} + +// VCVTSS2SI_RN_SAE: Convert Scalar Single-Precision FP Value to Dword Integer (Round Towards Nearest). +// +// Forms: +// +// VCVTSS2SI.RN_SAE xmm r32 +func VCVTSS2SI_RN_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSS2SI.Forms(), sffxs{sffxRN_SAE}, []operand.Op{x, r}) +} + +// VCVTSS2SI_RU_SAE: Convert Scalar Single-Precision FP Value to Dword Integer (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSS2SI.RU_SAE xmm r32 +func VCVTSS2SI_RU_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSS2SI.Forms(), sffxs{sffxRU_SAE}, []operand.Op{x, r}) +} + +// VCVTSS2SI_RZ_SAE: Convert Scalar Single-Precision FP Value to Dword Integer (Round Towards Zero). +// +// Forms: +// +// VCVTSS2SI.RZ_SAE xmm r32 +func VCVTSS2SI_RZ_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSS2SI.Forms(), sffxs{sffxRZ_SAE}, []operand.Op{x, r}) +} + +// VCVTSS2USIL: Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer. +// +// Forms: +// +// VCVTSS2USIL m32 r32 +// VCVTSS2USIL xmm r32 +func VCVTSS2USIL(mx, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSS2USIL.Forms(), sffxs{}, []operand.Op{mx, r}) +} + +// VCVTSS2USIL_RD_SAE: Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSS2USIL.RD_SAE xmm r32 +func VCVTSS2USIL_RD_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSS2USIL.Forms(), sffxs{sffxRD_SAE}, []operand.Op{x, r}) +} + +// VCVTSS2USIL_RN_SAE: Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Nearest). +// +// Forms: +// +// VCVTSS2USIL.RN_SAE xmm r32 +func VCVTSS2USIL_RN_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSS2USIL.Forms(), sffxs{sffxRN_SAE}, []operand.Op{x, r}) +} + +// VCVTSS2USIL_RU_SAE: Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSS2USIL.RU_SAE xmm r32 +func VCVTSS2USIL_RU_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSS2USIL.Forms(), sffxs{sffxRU_SAE}, []operand.Op{x, r}) +} + +// VCVTSS2USIL_RZ_SAE: Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Zero). +// +// Forms: +// +// VCVTSS2USIL.RZ_SAE xmm r32 +func VCVTSS2USIL_RZ_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSS2USIL.Forms(), sffxs{sffxRZ_SAE}, []operand.Op{x, r}) +} + +// VCVTSS2USIQ: Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer. +// +// Forms: +// +// VCVTSS2USIQ m32 r64 +// VCVTSS2USIQ xmm r64 +func VCVTSS2USIQ(mx, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSS2USIQ.Forms(), sffxs{}, []operand.Op{mx, r}) +} + +// VCVTSS2USIQ_RD_SAE: Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTSS2USIQ.RD_SAE xmm r64 +func VCVTSS2USIQ_RD_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSS2USIQ.Forms(), sffxs{sffxRD_SAE}, []operand.Op{x, r}) +} + +// VCVTSS2USIQ_RN_SAE: Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Nearest). +// +// Forms: +// +// VCVTSS2USIQ.RN_SAE xmm r64 +func VCVTSS2USIQ_RN_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSS2USIQ.Forms(), sffxs{sffxRN_SAE}, []operand.Op{x, r}) +} + +// VCVTSS2USIQ_RU_SAE: Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTSS2USIQ.RU_SAE xmm r64 +func VCVTSS2USIQ_RU_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSS2USIQ.Forms(), sffxs{sffxRU_SAE}, []operand.Op{x, r}) +} + +// VCVTSS2USIQ_RZ_SAE: Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer (Round Towards Zero). +// +// Forms: +// +// VCVTSS2USIQ.RZ_SAE xmm r64 +func VCVTSS2USIQ_RZ_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTSS2USIQ.Forms(), sffxs{sffxRZ_SAE}, []operand.Op{x, r}) +} + +// VCVTTPD2DQ: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers. +// +// Forms: +// +// VCVTTPD2DQ m512 k ymm +// VCVTTPD2DQ m512 ymm +// VCVTTPD2DQ zmm k ymm +// VCVTTPD2DQ zmm ymm +func VCVTTPD2DQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2DQ.Forms(), sffxs{}, ops) +} + +// VCVTTPD2DQX: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers. +// +// Forms: +// +// VCVTTPD2DQX m128 xmm +// VCVTTPD2DQX xmm xmm +// VCVTTPD2DQX m128 k xmm +// VCVTTPD2DQX xmm k xmm +func VCVTTPD2DQX(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2DQX.Forms(), sffxs{}, ops) +} + +// VCVTTPD2DQX_BCST: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Broadcast). +// +// Forms: +// +// VCVTTPD2DQX.BCST m64 k xmm +// VCVTTPD2DQX.BCST m64 xmm +func VCVTTPD2DQX_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2DQX.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTTPD2DQX_BCST_Z: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2DQX.BCST.Z m64 k xmm +func VCVTTPD2DQX_BCST_Z(m, k, x operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2DQX.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, x}) +} + +// VCVTTPD2DQX_Z: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTTPD2DQX.Z m128 k xmm +// VCVTTPD2DQX.Z xmm k xmm +func VCVTTPD2DQX_Z(mx, k, x operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2DQX.Forms(), sffxs{sffxZ}, []operand.Op{mx, k, x}) +} + +// VCVTTPD2DQY: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers. +// +// Forms: +// +// VCVTTPD2DQY m256 xmm +// VCVTTPD2DQY ymm xmm +// VCVTTPD2DQY m256 k xmm +// VCVTTPD2DQY ymm k xmm +func VCVTTPD2DQY(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2DQY.Forms(), sffxs{}, ops) +} + +// VCVTTPD2DQY_BCST: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Broadcast). +// +// Forms: +// +// VCVTTPD2DQY.BCST m64 k xmm +// VCVTTPD2DQY.BCST m64 xmm +func VCVTTPD2DQY_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2DQY.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTTPD2DQY_BCST_Z: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2DQY.BCST.Z m64 k xmm +func VCVTTPD2DQY_BCST_Z(m, k, x operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2DQY.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, x}) +} + +// VCVTTPD2DQY_Z: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTTPD2DQY.Z m256 k xmm +// VCVTTPD2DQY.Z ymm k xmm +func VCVTTPD2DQY_Z(my, k, x operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2DQY.Forms(), sffxs{sffxZ}, []operand.Op{my, k, x}) +} + +// VCVTTPD2DQ_BCST: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Broadcast). +// +// Forms: +// +// VCVTTPD2DQ.BCST m64 k ymm +// VCVTTPD2DQ.BCST m64 ymm +func VCVTTPD2DQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2DQ.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTTPD2DQ_BCST_Z: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2DQ.BCST.Z m64 k ymm +func VCVTTPD2DQ_BCST_Z(m, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2DQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, y}) +} + +// VCVTTPD2DQ_SAE: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Suppress All Exceptions). +// +// Forms: +// +// VCVTTPD2DQ.SAE zmm k ymm +// VCVTTPD2DQ.SAE zmm ymm +func VCVTTPD2DQ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2DQ.Forms(), sffxs{sffxSAE}, ops) +} + +// VCVTTPD2DQ_SAE_Z: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2DQ.SAE.Z zmm k ymm +func VCVTTPD2DQ_SAE_Z(z, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2DQ.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{z, k, y}) +} + +// VCVTTPD2DQ_Z: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTTPD2DQ.Z m512 k ymm +// VCVTTPD2DQ.Z zmm k ymm +func VCVTTPD2DQ_Z(mz, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2DQ.Forms(), sffxs{sffxZ}, []operand.Op{mz, k, y}) +} + +// VCVTTPD2QQ: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers. +// +// Forms: +// +// VCVTTPD2QQ m128 k xmm +// VCVTTPD2QQ m128 xmm +// VCVTTPD2QQ m256 k ymm +// VCVTTPD2QQ m256 ymm +// VCVTTPD2QQ xmm k xmm +// VCVTTPD2QQ xmm xmm +// VCVTTPD2QQ ymm k ymm +// VCVTTPD2QQ ymm ymm +// VCVTTPD2QQ m512 k zmm +// VCVTTPD2QQ m512 zmm +// VCVTTPD2QQ zmm k zmm +// VCVTTPD2QQ zmm zmm +func VCVTTPD2QQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2QQ.Forms(), sffxs{}, ops) +} + +// VCVTTPD2QQ_BCST: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Broadcast). +// +// Forms: +// +// VCVTTPD2QQ.BCST m64 k xmm +// VCVTTPD2QQ.BCST m64 k ymm +// VCVTTPD2QQ.BCST m64 xmm +// VCVTTPD2QQ.BCST m64 ymm +// VCVTTPD2QQ.BCST m64 k zmm +// VCVTTPD2QQ.BCST m64 zmm +func VCVTTPD2QQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2QQ.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTTPD2QQ_BCST_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2QQ.BCST.Z m64 k xmm +// VCVTTPD2QQ.BCST.Z m64 k ymm +// VCVTTPD2QQ.BCST.Z m64 k zmm +func VCVTTPD2QQ_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2QQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) +} + +// VCVTTPD2QQ_SAE: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Suppress All Exceptions). +// +// Forms: +// +// VCVTTPD2QQ.SAE zmm k zmm +// VCVTTPD2QQ.SAE zmm zmm +func VCVTTPD2QQ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2QQ.Forms(), sffxs{sffxSAE}, ops) +} + +// VCVTTPD2QQ_SAE_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2QQ.SAE.Z zmm k zmm +func VCVTTPD2QQ_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2QQ.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTTPD2QQ_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTTPD2QQ.Z m128 k xmm +// VCVTTPD2QQ.Z m256 k ymm +// VCVTTPD2QQ.Z xmm k xmm +// VCVTTPD2QQ.Z ymm k ymm +// VCVTTPD2QQ.Z m512 k zmm +// VCVTTPD2QQ.Z zmm k zmm +func VCVTTPD2QQ_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2QQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) +} + +// VCVTTPD2UDQ: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers. +// +// Forms: +// +// VCVTTPD2UDQ m512 k ymm +// VCVTTPD2UDQ m512 ymm +// VCVTTPD2UDQ zmm k ymm +// VCVTTPD2UDQ zmm ymm +func VCVTTPD2UDQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2UDQ.Forms(), sffxs{}, ops) +} + +// VCVTTPD2UDQX: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers. +// +// Forms: +// +// VCVTTPD2UDQX m128 k xmm +// VCVTTPD2UDQX m128 xmm +// VCVTTPD2UDQX xmm k xmm +// VCVTTPD2UDQX xmm xmm +func VCVTTPD2UDQX(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2UDQX.Forms(), sffxs{}, ops) +} + +// VCVTTPD2UDQX_BCST: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast). +// +// Forms: +// +// VCVTTPD2UDQX.BCST m64 k xmm +// VCVTTPD2UDQX.BCST m64 xmm +func VCVTTPD2UDQX_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2UDQX.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTTPD2UDQX_BCST_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2UDQX.BCST.Z m64 k xmm +func VCVTTPD2UDQX_BCST_Z(m, k, x operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2UDQX.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, x}) +} + +// VCVTTPD2UDQX_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTTPD2UDQX.Z m128 k xmm +// VCVTTPD2UDQX.Z xmm k xmm +func VCVTTPD2UDQX_Z(mx, k, x operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2UDQX.Forms(), sffxs{sffxZ}, []operand.Op{mx, k, x}) +} + +// VCVTTPD2UDQY: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers. +// +// Forms: +// +// VCVTTPD2UDQY m256 k xmm +// VCVTTPD2UDQY m256 xmm +// VCVTTPD2UDQY ymm k xmm +// VCVTTPD2UDQY ymm xmm +func VCVTTPD2UDQY(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2UDQY.Forms(), sffxs{}, ops) +} + +// VCVTTPD2UDQY_BCST: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast). +// +// Forms: +// +// VCVTTPD2UDQY.BCST m64 k xmm +// VCVTTPD2UDQY.BCST m64 xmm +func VCVTTPD2UDQY_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2UDQY.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTTPD2UDQY_BCST_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2UDQY.BCST.Z m64 k xmm +func VCVTTPD2UDQY_BCST_Z(m, k, x operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2UDQY.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, x}) +} + +// VCVTTPD2UDQY_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTTPD2UDQY.Z m256 k xmm +// VCVTTPD2UDQY.Z ymm k xmm +func VCVTTPD2UDQY_Z(my, k, x operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2UDQY.Forms(), sffxs{sffxZ}, []operand.Op{my, k, x}) +} + +// VCVTTPD2UDQ_BCST: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast). +// +// Forms: +// +// VCVTTPD2UDQ.BCST m64 k ymm +// VCVTTPD2UDQ.BCST m64 ymm +func VCVTTPD2UDQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2UDQ.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTTPD2UDQ_BCST_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2UDQ.BCST.Z m64 k ymm +func VCVTTPD2UDQ_BCST_Z(m, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2UDQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, y}) +} + +// VCVTTPD2UDQ_SAE: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Suppress All Exceptions). +// +// Forms: +// +// VCVTTPD2UDQ.SAE zmm k ymm +// VCVTTPD2UDQ.SAE zmm ymm +func VCVTTPD2UDQ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2UDQ.Forms(), sffxs{sffxSAE}, ops) +} + +// VCVTTPD2UDQ_SAE_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2UDQ.SAE.Z zmm k ymm +func VCVTTPD2UDQ_SAE_Z(z, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2UDQ.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{z, k, y}) +} + +// VCVTTPD2UDQ_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTTPD2UDQ.Z m512 k ymm +// VCVTTPD2UDQ.Z zmm k ymm +func VCVTTPD2UDQ_Z(mz, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2UDQ.Forms(), sffxs{sffxZ}, []operand.Op{mz, k, y}) +} + +// VCVTTPD2UQQ: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers. +// +// Forms: +// +// VCVTTPD2UQQ m128 k xmm +// VCVTTPD2UQQ m128 xmm +// VCVTTPD2UQQ m256 k ymm +// VCVTTPD2UQQ m256 ymm +// VCVTTPD2UQQ xmm k xmm +// VCVTTPD2UQQ xmm xmm +// VCVTTPD2UQQ ymm k ymm +// VCVTTPD2UQQ ymm ymm +// VCVTTPD2UQQ m512 k zmm +// VCVTTPD2UQQ m512 zmm +// VCVTTPD2UQQ zmm k zmm +// VCVTTPD2UQQ zmm zmm +func VCVTTPD2UQQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2UQQ.Forms(), sffxs{}, ops) +} + +// VCVTTPD2UQQ_BCST: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Broadcast). +// +// Forms: +// +// VCVTTPD2UQQ.BCST m64 k xmm +// VCVTTPD2UQQ.BCST m64 k ymm +// VCVTTPD2UQQ.BCST m64 xmm +// VCVTTPD2UQQ.BCST m64 ymm +// VCVTTPD2UQQ.BCST m64 k zmm +// VCVTTPD2UQQ.BCST m64 zmm +func VCVTTPD2UQQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2UQQ.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTTPD2UQQ_BCST_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2UQQ.BCST.Z m64 k xmm +// VCVTTPD2UQQ.BCST.Z m64 k ymm +// VCVTTPD2UQQ.BCST.Z m64 k zmm +func VCVTTPD2UQQ_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2UQQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) +} + +// VCVTTPD2UQQ_SAE: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Suppress All Exceptions). +// +// Forms: +// +// VCVTTPD2UQQ.SAE zmm k zmm +// VCVTTPD2UQQ.SAE zmm zmm +func VCVTTPD2UQQ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2UQQ.Forms(), sffxs{sffxSAE}, ops) +} + +// VCVTTPD2UQQ_SAE_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTTPD2UQQ.SAE.Z zmm k zmm +func VCVTTPD2UQQ_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2UQQ.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTTPD2UQQ_Z: Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTTPD2UQQ.Z m128 k xmm +// VCVTTPD2UQQ.Z m256 k ymm +// VCVTTPD2UQQ.Z xmm k xmm +// VCVTTPD2UQQ.Z ymm k ymm +// VCVTTPD2UQQ.Z m512 k zmm +// VCVTTPD2UQQ.Z zmm k zmm +func VCVTTPD2UQQ_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPD2UQQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) +} + +// VCVTTPS2DQ: Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers. +// +// Forms: +// +// VCVTTPS2DQ m128 xmm +// VCVTTPS2DQ m256 ymm +// VCVTTPS2DQ xmm xmm +// VCVTTPS2DQ ymm ymm +// VCVTTPS2DQ m128 k xmm +// VCVTTPS2DQ m256 k ymm +// VCVTTPS2DQ xmm k xmm +// VCVTTPS2DQ ymm k ymm +// VCVTTPS2DQ m512 k zmm +// VCVTTPS2DQ m512 zmm +// VCVTTPS2DQ zmm k zmm +// VCVTTPS2DQ zmm zmm +func VCVTTPS2DQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPS2DQ.Forms(), sffxs{}, ops) +} + +// VCVTTPS2DQ_BCST: Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers (Broadcast). +// +// Forms: +// +// VCVTTPS2DQ.BCST m32 k xmm +// VCVTTPS2DQ.BCST m32 k ymm +// VCVTTPS2DQ.BCST m32 xmm +// VCVTTPS2DQ.BCST m32 ymm +// VCVTTPS2DQ.BCST m32 k zmm +// VCVTTPS2DQ.BCST m32 zmm +func VCVTTPS2DQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPS2DQ.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTTPS2DQ_BCST_Z: Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPS2DQ.BCST.Z m32 k xmm +// VCVTTPS2DQ.BCST.Z m32 k ymm +// VCVTTPS2DQ.BCST.Z m32 k zmm +func VCVTTPS2DQ_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPS2DQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) +} + +// VCVTTPS2DQ_SAE: Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers (Suppress All Exceptions). +// +// Forms: +// +// VCVTTPS2DQ.SAE zmm k zmm +// VCVTTPS2DQ.SAE zmm zmm +func VCVTTPS2DQ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPS2DQ.Forms(), sffxs{sffxSAE}, ops) +} + +// VCVTTPS2DQ_SAE_Z: Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTTPS2DQ.SAE.Z zmm k zmm +func VCVTTPS2DQ_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPS2DQ.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTTPS2DQ_Z: Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers (Zeroing Masking). +// +// Forms: +// +// VCVTTPS2DQ.Z m128 k xmm +// VCVTTPS2DQ.Z m256 k ymm +// VCVTTPS2DQ.Z xmm k xmm +// VCVTTPS2DQ.Z ymm k ymm +// VCVTTPS2DQ.Z m512 k zmm +// VCVTTPS2DQ.Z zmm k zmm +func VCVTTPS2DQ_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPS2DQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) +} + +// VCVTTPS2QQ: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values. +// +// Forms: +// +// VCVTTPS2QQ m128 k ymm +// VCVTTPS2QQ m128 ymm +// VCVTTPS2QQ m64 k xmm +// VCVTTPS2QQ m64 xmm +// VCVTTPS2QQ xmm k xmm +// VCVTTPS2QQ xmm k ymm +// VCVTTPS2QQ xmm xmm +// VCVTTPS2QQ xmm ymm +// VCVTTPS2QQ m256 k zmm +// VCVTTPS2QQ m256 zmm +// VCVTTPS2QQ ymm k zmm +// VCVTTPS2QQ ymm zmm +func VCVTTPS2QQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPS2QQ.Forms(), sffxs{}, ops) +} + +// VCVTTPS2QQ_BCST: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Broadcast). +// +// Forms: +// +// VCVTTPS2QQ.BCST m32 k xmm +// VCVTTPS2QQ.BCST m32 k ymm +// VCVTTPS2QQ.BCST m32 xmm +// VCVTTPS2QQ.BCST m32 ymm +// VCVTTPS2QQ.BCST m32 k zmm +// VCVTTPS2QQ.BCST m32 zmm +func VCVTTPS2QQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPS2QQ.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTTPS2QQ_BCST_Z: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPS2QQ.BCST.Z m32 k xmm +// VCVTTPS2QQ.BCST.Z m32 k ymm +// VCVTTPS2QQ.BCST.Z m32 k zmm +func VCVTTPS2QQ_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPS2QQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) +} + +// VCVTTPS2QQ_SAE: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Suppress All Exceptions). +// +// Forms: +// +// VCVTTPS2QQ.SAE ymm k zmm +// VCVTTPS2QQ.SAE ymm zmm +func VCVTTPS2QQ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPS2QQ.Forms(), sffxs{sffxSAE}, ops) +} + +// VCVTTPS2QQ_SAE_Z: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTTPS2QQ.SAE.Z ymm k zmm +func VCVTTPS2QQ_SAE_Z(y, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPS2QQ.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{y, k, z}) +} + +// VCVTTPS2QQ_Z: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values (Zeroing Masking). +// +// Forms: +// +// VCVTTPS2QQ.Z m128 k ymm +// VCVTTPS2QQ.Z m64 k xmm +// VCVTTPS2QQ.Z xmm k xmm +// VCVTTPS2QQ.Z xmm k ymm +// VCVTTPS2QQ.Z m256 k zmm +// VCVTTPS2QQ.Z ymm k zmm +func VCVTTPS2QQ_Z(mxy, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPS2QQ.Forms(), sffxs{sffxZ}, []operand.Op{mxy, k, xyz}) +} + +// VCVTTPS2UDQ: Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values. +// +// Forms: +// +// VCVTTPS2UDQ m128 k xmm +// VCVTTPS2UDQ m128 xmm +// VCVTTPS2UDQ m256 k ymm +// VCVTTPS2UDQ m256 ymm +// VCVTTPS2UDQ xmm k xmm +// VCVTTPS2UDQ xmm xmm +// VCVTTPS2UDQ ymm k ymm +// VCVTTPS2UDQ ymm ymm +// VCVTTPS2UDQ m512 k zmm +// VCVTTPS2UDQ m512 zmm +// VCVTTPS2UDQ zmm k zmm +// VCVTTPS2UDQ zmm zmm +func VCVTTPS2UDQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPS2UDQ.Forms(), sffxs{}, ops) +} + +// VCVTTPS2UDQ_BCST: Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Broadcast). +// +// Forms: +// +// VCVTTPS2UDQ.BCST m32 k xmm +// VCVTTPS2UDQ.BCST m32 k ymm +// VCVTTPS2UDQ.BCST m32 xmm +// VCVTTPS2UDQ.BCST m32 ymm +// VCVTTPS2UDQ.BCST m32 k zmm +// VCVTTPS2UDQ.BCST m32 zmm +func VCVTTPS2UDQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPS2UDQ.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTTPS2UDQ_BCST_Z: Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPS2UDQ.BCST.Z m32 k xmm +// VCVTTPS2UDQ.BCST.Z m32 k ymm +// VCVTTPS2UDQ.BCST.Z m32 k zmm +func VCVTTPS2UDQ_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPS2UDQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) +} + +// VCVTTPS2UDQ_SAE: Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Suppress All Exceptions). +// +// Forms: +// +// VCVTTPS2UDQ.SAE zmm k zmm +// VCVTTPS2UDQ.SAE zmm zmm +func VCVTTPS2UDQ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPS2UDQ.Forms(), sffxs{sffxSAE}, ops) +} + +// VCVTTPS2UDQ_SAE_Z: Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTTPS2UDQ.SAE.Z zmm k zmm +func VCVTTPS2UDQ_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPS2UDQ.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTTPS2UDQ_Z: Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values (Zeroing Masking). +// +// Forms: +// +// VCVTTPS2UDQ.Z m128 k xmm +// VCVTTPS2UDQ.Z m256 k ymm +// VCVTTPS2UDQ.Z xmm k xmm +// VCVTTPS2UDQ.Z ymm k ymm +// VCVTTPS2UDQ.Z m512 k zmm +// VCVTTPS2UDQ.Z zmm k zmm +func VCVTTPS2UDQ_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPS2UDQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) +} + +// VCVTTPS2UQQ: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values. +// +// Forms: +// +// VCVTTPS2UQQ m128 k ymm +// VCVTTPS2UQQ m128 ymm +// VCVTTPS2UQQ m64 k xmm +// VCVTTPS2UQQ m64 xmm +// VCVTTPS2UQQ xmm k xmm +// VCVTTPS2UQQ xmm k ymm +// VCVTTPS2UQQ xmm xmm +// VCVTTPS2UQQ xmm ymm +// VCVTTPS2UQQ m256 k zmm +// VCVTTPS2UQQ m256 zmm +// VCVTTPS2UQQ ymm k zmm +// VCVTTPS2UQQ ymm zmm +func VCVTTPS2UQQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPS2UQQ.Forms(), sffxs{}, ops) +} + +// VCVTTPS2UQQ_BCST: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Broadcast). +// +// Forms: +// +// VCVTTPS2UQQ.BCST m32 k xmm +// VCVTTPS2UQQ.BCST m32 k ymm +// VCVTTPS2UQQ.BCST m32 xmm +// VCVTTPS2UQQ.BCST m32 ymm +// VCVTTPS2UQQ.BCST m32 k zmm +// VCVTTPS2UQQ.BCST m32 zmm +func VCVTTPS2UQQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPS2UQQ.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTTPS2UQQ_BCST_Z: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTTPS2UQQ.BCST.Z m32 k xmm +// VCVTTPS2UQQ.BCST.Z m32 k ymm +// VCVTTPS2UQQ.BCST.Z m32 k zmm +func VCVTTPS2UQQ_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPS2UQQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) +} + +// VCVTTPS2UQQ_SAE: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Suppress All Exceptions). +// +// Forms: +// +// VCVTTPS2UQQ.SAE ymm k zmm +// VCVTTPS2UQQ.SAE ymm zmm +func VCVTTPS2UQQ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPS2UQQ.Forms(), sffxs{sffxSAE}, ops) +} + +// VCVTTPS2UQQ_SAE_Z: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VCVTTPS2UQQ.SAE.Z ymm k zmm +func VCVTTPS2UQQ_SAE_Z(y, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPS2UQQ.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{y, k, z}) +} + +// VCVTTPS2UQQ_Z: Convert with Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values (Zeroing Masking). +// +// Forms: +// +// VCVTTPS2UQQ.Z m128 k ymm +// VCVTTPS2UQQ.Z m64 k xmm +// VCVTTPS2UQQ.Z xmm k xmm +// VCVTTPS2UQQ.Z xmm k ymm +// VCVTTPS2UQQ.Z m256 k zmm +// VCVTTPS2UQQ.Z ymm k zmm +func VCVTTPS2UQQ_Z(mxy, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTPS2UQQ.Forms(), sffxs{sffxZ}, []operand.Op{mxy, k, xyz}) +} + +// VCVTTSD2SI: Convert with Truncation Scalar Double-Precision FP Value to Signed Integer. +// +// Forms: +// +// VCVTTSD2SI m64 r32 +// VCVTTSD2SI xmm r32 +func VCVTTSD2SI(mx, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTSD2SI.Forms(), sffxs{}, []operand.Op{mx, r}) +} + +// VCVTTSD2SIQ: Convert with Truncation Scalar Double-Precision FP Value to Signed Integer. +// +// Forms: +// +// VCVTTSD2SIQ m64 r64 +// VCVTTSD2SIQ xmm r64 +func VCVTTSD2SIQ(mx, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTSD2SIQ.Forms(), sffxs{}, []operand.Op{mx, r}) +} + +// VCVTTSD2SIQ_SAE: Convert with Truncation Scalar Double-Precision FP Value to Signed Integer (Suppress All Exceptions). +// +// Forms: +// +// VCVTTSD2SIQ.SAE xmm r64 +func VCVTTSD2SIQ_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTSD2SIQ.Forms(), sffxs{sffxSAE}, []operand.Op{x, r}) +} + +// VCVTTSD2SI_SAE: Convert with Truncation Scalar Double-Precision FP Value to Signed Integer (Suppress All Exceptions). +// +// Forms: +// +// VCVTTSD2SI.SAE xmm r32 +func VCVTTSD2SI_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTSD2SI.Forms(), sffxs{sffxSAE}, []operand.Op{x, r}) +} + +// VCVTTSD2USIL: Convert with Truncation Scalar Double-Precision Floating-Point Value to Unsigned Integer. +// +// Forms: +// +// VCVTTSD2USIL m64 r32 +// VCVTTSD2USIL xmm r32 +func VCVTTSD2USIL(mx, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTSD2USIL.Forms(), sffxs{}, []operand.Op{mx, r}) +} + +// VCVTTSD2USIL_SAE: Convert with Truncation Scalar Double-Precision Floating-Point Value to Unsigned Integer (Suppress All Exceptions). +// +// Forms: +// +// VCVTTSD2USIL.SAE xmm r32 +func VCVTTSD2USIL_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTSD2USIL.Forms(), sffxs{sffxSAE}, []operand.Op{x, r}) +} + +// VCVTTSD2USIQ: Convert with Truncation Scalar Double-Precision Floating-Point Value to Unsigned Integer. +// +// Forms: +// +// VCVTTSD2USIQ m64 r64 +// VCVTTSD2USIQ xmm r64 +func VCVTTSD2USIQ(mx, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTSD2USIQ.Forms(), sffxs{}, []operand.Op{mx, r}) +} + +// VCVTTSD2USIQ_SAE: Convert with Truncation Scalar Double-Precision Floating-Point Value to Unsigned Integer (Suppress All Exceptions). +// +// Forms: +// +// VCVTTSD2USIQ.SAE xmm r64 +func VCVTTSD2USIQ_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTSD2USIQ.Forms(), sffxs{sffxSAE}, []operand.Op{x, r}) +} + +// VCVTTSS2SI: Convert with Truncation Scalar Single-Precision FP Value to Dword Integer. +// +// Forms: +// +// VCVTTSS2SI m32 r32 +// VCVTTSS2SI xmm r32 +func VCVTTSS2SI(mx, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTSS2SI.Forms(), sffxs{}, []operand.Op{mx, r}) +} + +// VCVTTSS2SIQ: Convert with Truncation Scalar Single-Precision FP Value to Dword Integer. +// +// Forms: +// +// VCVTTSS2SIQ m32 r64 +// VCVTTSS2SIQ xmm r64 +func VCVTTSS2SIQ(mx, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTSS2SIQ.Forms(), sffxs{}, []operand.Op{mx, r}) +} + +// VCVTTSS2SIQ_SAE: Convert with Truncation Scalar Single-Precision FP Value to Dword Integer (Suppress All Exceptions). +// +// Forms: +// +// VCVTTSS2SIQ.SAE xmm r64 +func VCVTTSS2SIQ_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTSS2SIQ.Forms(), sffxs{sffxSAE}, []operand.Op{x, r}) +} + +// VCVTTSS2SI_SAE: Convert with Truncation Scalar Single-Precision FP Value to Dword Integer (Suppress All Exceptions). +// +// Forms: +// +// VCVTTSS2SI.SAE xmm r32 +func VCVTTSS2SI_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTSS2SI.Forms(), sffxs{sffxSAE}, []operand.Op{x, r}) +} + +// VCVTTSS2USIL: Convert with Truncation Scalar Single-Precision Floating-Point Value to Unsigned Integer. +// +// Forms: +// +// VCVTTSS2USIL m32 r32 +// VCVTTSS2USIL xmm r32 +func VCVTTSS2USIL(mx, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTSS2USIL.Forms(), sffxs{}, []operand.Op{mx, r}) +} + +// VCVTTSS2USIL_SAE: Convert with Truncation Scalar Single-Precision Floating-Point Value to Unsigned Integer (Suppress All Exceptions). +// +// Forms: +// +// VCVTTSS2USIL.SAE xmm r32 +func VCVTTSS2USIL_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTSS2USIL.Forms(), sffxs{sffxSAE}, []operand.Op{x, r}) +} + +// VCVTTSS2USIQ: Convert with Truncation Scalar Single-Precision Floating-Point Value to Unsigned Integer. +// +// Forms: +// +// VCVTTSS2USIQ m32 r64 +// VCVTTSS2USIQ xmm r64 +func VCVTTSS2USIQ(mx, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTSS2USIQ.Forms(), sffxs{}, []operand.Op{mx, r}) +} + +// VCVTTSS2USIQ_SAE: Convert with Truncation Scalar Single-Precision Floating-Point Value to Unsigned Integer (Suppress All Exceptions). +// +// Forms: +// +// VCVTTSS2USIQ.SAE xmm r64 +func VCVTTSS2USIQ_SAE(x, r operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTTSS2USIQ.Forms(), sffxs{sffxSAE}, []operand.Op{x, r}) +} + +// VCVTUDQ2PD: Convert Packed Unsigned Doubleword Integers to Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VCVTUDQ2PD m128 k ymm +// VCVTUDQ2PD m128 ymm +// VCVTUDQ2PD m64 k xmm +// VCVTUDQ2PD m64 xmm +// VCVTUDQ2PD xmm k xmm +// VCVTUDQ2PD xmm k ymm +// VCVTUDQ2PD xmm xmm +// VCVTUDQ2PD xmm ymm +// VCVTUDQ2PD m256 k zmm +// VCVTUDQ2PD m256 zmm +// VCVTUDQ2PD ymm k zmm +// VCVTUDQ2PD ymm zmm +func VCVTUDQ2PD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUDQ2PD.Forms(), sffxs{}, ops) +} + +// VCVTUDQ2PD_BCST: Convert Packed Unsigned Doubleword Integers to Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCVTUDQ2PD.BCST m32 k xmm +// VCVTUDQ2PD.BCST m32 k ymm +// VCVTUDQ2PD.BCST m32 xmm +// VCVTUDQ2PD.BCST m32 ymm +// VCVTUDQ2PD.BCST m32 k zmm +// VCVTUDQ2PD.BCST m32 zmm +func VCVTUDQ2PD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUDQ2PD.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTUDQ2PD_BCST_Z: Convert Packed Unsigned Doubleword Integers to Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTUDQ2PD.BCST.Z m32 k xmm +// VCVTUDQ2PD.BCST.Z m32 k ymm +// VCVTUDQ2PD.BCST.Z m32 k zmm +func VCVTUDQ2PD_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUDQ2PD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) +} + +// VCVTUDQ2PD_Z: Convert Packed Unsigned Doubleword Integers to Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VCVTUDQ2PD.Z m128 k ymm +// VCVTUDQ2PD.Z m64 k xmm +// VCVTUDQ2PD.Z xmm k xmm +// VCVTUDQ2PD.Z xmm k ymm +// VCVTUDQ2PD.Z m256 k zmm +// VCVTUDQ2PD.Z ymm k zmm +func VCVTUDQ2PD_Z(mxy, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUDQ2PD.Forms(), sffxs{sffxZ}, []operand.Op{mxy, k, xyz}) +} + +// VCVTUDQ2PS: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VCVTUDQ2PS m128 k xmm +// VCVTUDQ2PS m128 xmm +// VCVTUDQ2PS m256 k ymm +// VCVTUDQ2PS m256 ymm +// VCVTUDQ2PS xmm k xmm +// VCVTUDQ2PS xmm xmm +// VCVTUDQ2PS ymm k ymm +// VCVTUDQ2PS ymm ymm +// VCVTUDQ2PS m512 k zmm +// VCVTUDQ2PS m512 zmm +// VCVTUDQ2PS zmm k zmm +// VCVTUDQ2PS zmm zmm +func VCVTUDQ2PS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUDQ2PS.Forms(), sffxs{}, ops) +} + +// VCVTUDQ2PS_BCST: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCVTUDQ2PS.BCST m32 k xmm +// VCVTUDQ2PS.BCST m32 k ymm +// VCVTUDQ2PS.BCST m32 xmm +// VCVTUDQ2PS.BCST m32 ymm +// VCVTUDQ2PS.BCST m32 k zmm +// VCVTUDQ2PS.BCST m32 zmm +func VCVTUDQ2PS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUDQ2PS.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTUDQ2PS_BCST_Z: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTUDQ2PS.BCST.Z m32 k xmm +// VCVTUDQ2PS.BCST.Z m32 k ymm +// VCVTUDQ2PS.BCST.Z m32 k zmm +func VCVTUDQ2PS_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUDQ2PS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) +} + +// VCVTUDQ2PS_RD_SAE: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTUDQ2PS.RD_SAE zmm k zmm +// VCVTUDQ2PS.RD_SAE zmm zmm +func VCVTUDQ2PS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUDQ2PS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VCVTUDQ2PS_RD_SAE_Z: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTUDQ2PS.RD_SAE.Z zmm k zmm +func VCVTUDQ2PS_RD_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUDQ2PS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTUDQ2PS_RN_SAE: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VCVTUDQ2PS.RN_SAE zmm k zmm +// VCVTUDQ2PS.RN_SAE zmm zmm +func VCVTUDQ2PS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUDQ2PS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VCVTUDQ2PS_RN_SAE_Z: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTUDQ2PS.RN_SAE.Z zmm k zmm +func VCVTUDQ2PS_RN_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUDQ2PS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTUDQ2PS_RU_SAE: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTUDQ2PS.RU_SAE zmm k zmm +// VCVTUDQ2PS.RU_SAE zmm zmm +func VCVTUDQ2PS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUDQ2PS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VCVTUDQ2PS_RU_SAE_Z: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTUDQ2PS.RU_SAE.Z zmm k zmm +func VCVTUDQ2PS_RU_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUDQ2PS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTUDQ2PS_RZ_SAE: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VCVTUDQ2PS.RZ_SAE zmm k zmm +// VCVTUDQ2PS.RZ_SAE zmm zmm +func VCVTUDQ2PS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUDQ2PS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VCVTUDQ2PS_RZ_SAE_Z: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTUDQ2PS.RZ_SAE.Z zmm k zmm +func VCVTUDQ2PS_RZ_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUDQ2PS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTUDQ2PS_Z: Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VCVTUDQ2PS.Z m128 k xmm +// VCVTUDQ2PS.Z m256 k ymm +// VCVTUDQ2PS.Z xmm k xmm +// VCVTUDQ2PS.Z ymm k ymm +// VCVTUDQ2PS.Z m512 k zmm +// VCVTUDQ2PS.Z zmm k zmm +func VCVTUDQ2PS_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUDQ2PS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) +} + +// VCVTUQQ2PD: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VCVTUQQ2PD m128 k xmm +// VCVTUQQ2PD m128 xmm +// VCVTUQQ2PD m256 k ymm +// VCVTUQQ2PD m256 ymm +// VCVTUQQ2PD xmm k xmm +// VCVTUQQ2PD xmm xmm +// VCVTUQQ2PD ymm k ymm +// VCVTUQQ2PD ymm ymm +// VCVTUQQ2PD m512 k zmm +// VCVTUQQ2PD m512 zmm +// VCVTUQQ2PD zmm k zmm +// VCVTUQQ2PD zmm zmm +func VCVTUQQ2PD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PD.Forms(), sffxs{}, ops) +} + +// VCVTUQQ2PD_BCST: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCVTUQQ2PD.BCST m64 k xmm +// VCVTUQQ2PD.BCST m64 k ymm +// VCVTUQQ2PD.BCST m64 xmm +// VCVTUQQ2PD.BCST m64 ymm +// VCVTUQQ2PD.BCST m64 k zmm +// VCVTUQQ2PD.BCST m64 zmm +func VCVTUQQ2PD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PD.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTUQQ2PD_BCST_Z: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PD.BCST.Z m64 k xmm +// VCVTUQQ2PD.BCST.Z m64 k ymm +// VCVTUQQ2PD.BCST.Z m64 k zmm +func VCVTUQQ2PD_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) +} + +// VCVTUQQ2PD_RD_SAE: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTUQQ2PD.RD_SAE zmm k zmm +// VCVTUQQ2PD.RD_SAE zmm zmm +func VCVTUQQ2PD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VCVTUQQ2PD_RD_SAE_Z: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PD.RD_SAE.Z zmm k zmm +func VCVTUQQ2PD_RD_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTUQQ2PD_RN_SAE: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VCVTUQQ2PD.RN_SAE zmm k zmm +// VCVTUQQ2PD.RN_SAE zmm zmm +func VCVTUQQ2PD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VCVTUQQ2PD_RN_SAE_Z: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PD.RN_SAE.Z zmm k zmm +func VCVTUQQ2PD_RN_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTUQQ2PD_RU_SAE: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTUQQ2PD.RU_SAE zmm k zmm +// VCVTUQQ2PD.RU_SAE zmm zmm +func VCVTUQQ2PD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VCVTUQQ2PD_RU_SAE_Z: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PD.RU_SAE.Z zmm k zmm +func VCVTUQQ2PD_RU_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTUQQ2PD_RZ_SAE: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VCVTUQQ2PD.RZ_SAE zmm k zmm +// VCVTUQQ2PD.RZ_SAE zmm zmm +func VCVTUQQ2PD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VCVTUQQ2PD_RZ_SAE_Z: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PD.RZ_SAE.Z zmm k zmm +func VCVTUQQ2PD_RZ_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VCVTUQQ2PD_Z: Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PD.Z m128 k xmm +// VCVTUQQ2PD.Z m256 k ymm +// VCVTUQQ2PD.Z xmm k xmm +// VCVTUQQ2PD.Z ymm k ymm +// VCVTUQQ2PD.Z m512 k zmm +// VCVTUQQ2PD.Z zmm k zmm +func VCVTUQQ2PD_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) +} + +// VCVTUQQ2PS: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VCVTUQQ2PS m512 k ymm +// VCVTUQQ2PS m512 ymm +// VCVTUQQ2PS zmm k ymm +// VCVTUQQ2PS zmm ymm +func VCVTUQQ2PS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PS.Forms(), sffxs{}, ops) +} + +// VCVTUQQ2PSX: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VCVTUQQ2PSX m128 k xmm +// VCVTUQQ2PSX m128 xmm +// VCVTUQQ2PSX xmm k xmm +// VCVTUQQ2PSX xmm xmm +func VCVTUQQ2PSX(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PSX.Forms(), sffxs{}, ops) +} + +// VCVTUQQ2PSX_BCST: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCVTUQQ2PSX.BCST m64 k xmm +// VCVTUQQ2PSX.BCST m64 xmm +func VCVTUQQ2PSX_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PSX.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTUQQ2PSX_BCST_Z: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PSX.BCST.Z m64 k xmm +func VCVTUQQ2PSX_BCST_Z(m, k, x operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PSX.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, x}) +} + +// VCVTUQQ2PSX_Z: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PSX.Z m128 k xmm +// VCVTUQQ2PSX.Z xmm k xmm +func VCVTUQQ2PSX_Z(mx, k, x operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PSX.Forms(), sffxs{sffxZ}, []operand.Op{mx, k, x}) +} + +// VCVTUQQ2PSY: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VCVTUQQ2PSY m256 k xmm +// VCVTUQQ2PSY m256 xmm +// VCVTUQQ2PSY ymm k xmm +// VCVTUQQ2PSY ymm xmm +func VCVTUQQ2PSY(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PSY.Forms(), sffxs{}, ops) +} + +// VCVTUQQ2PSY_BCST: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCVTUQQ2PSY.BCST m64 k xmm +// VCVTUQQ2PSY.BCST m64 xmm +func VCVTUQQ2PSY_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PSY.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTUQQ2PSY_BCST_Z: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PSY.BCST.Z m64 k xmm +func VCVTUQQ2PSY_BCST_Z(m, k, x operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PSY.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, x}) +} + +// VCVTUQQ2PSY_Z: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PSY.Z m256 k xmm +// VCVTUQQ2PSY.Z ymm k xmm +func VCVTUQQ2PSY_Z(my, k, x operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PSY.Forms(), sffxs{sffxZ}, []operand.Op{my, k, x}) +} + +// VCVTUQQ2PS_BCST: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VCVTUQQ2PS.BCST m64 k ymm +// VCVTUQQ2PS.BCST m64 ymm +func VCVTUQQ2PS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PS.Forms(), sffxs{sffxBCST}, ops) +} + +// VCVTUQQ2PS_BCST_Z: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PS.BCST.Z m64 k ymm +func VCVTUQQ2PS_BCST_Z(m, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, y}) +} + +// VCVTUQQ2PS_RD_SAE: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTUQQ2PS.RD_SAE zmm k ymm +// VCVTUQQ2PS.RD_SAE zmm ymm +func VCVTUQQ2PS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VCVTUQQ2PS_RD_SAE_Z: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PS.RD_SAE.Z zmm k ymm +func VCVTUQQ2PS_RD_SAE_Z(z, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, k, y}) +} + +// VCVTUQQ2PS_RN_SAE: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VCVTUQQ2PS.RN_SAE zmm k ymm +// VCVTUQQ2PS.RN_SAE zmm ymm +func VCVTUQQ2PS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VCVTUQQ2PS_RN_SAE_Z: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PS.RN_SAE.Z zmm k ymm +func VCVTUQQ2PS_RN_SAE_Z(z, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, k, y}) +} + +// VCVTUQQ2PS_RU_SAE: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTUQQ2PS.RU_SAE zmm k ymm +// VCVTUQQ2PS.RU_SAE zmm ymm +func VCVTUQQ2PS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VCVTUQQ2PS_RU_SAE_Z: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PS.RU_SAE.Z zmm k ymm +func VCVTUQQ2PS_RU_SAE_Z(z, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, k, y}) +} + +// VCVTUQQ2PS_RZ_SAE: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VCVTUQQ2PS.RZ_SAE zmm k ymm +// VCVTUQQ2PS.RZ_SAE zmm ymm +func VCVTUQQ2PS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VCVTUQQ2PS_RZ_SAE_Z: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PS.RZ_SAE.Z zmm k ymm +func VCVTUQQ2PS_RZ_SAE_Z(z, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, k, y}) +} + +// VCVTUQQ2PS_Z: Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VCVTUQQ2PS.Z m512 k ymm +// VCVTUQQ2PS.Z zmm k ymm +func VCVTUQQ2PS_Z(mz, k, y operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUQQ2PS.Forms(), sffxs{sffxZ}, []operand.Op{mz, k, y}) +} + +// VCVTUSI2SDL: Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// VCVTUSI2SDL m32 xmm xmm +// VCVTUSI2SDL r32 xmm xmm +func VCVTUSI2SDL(mr, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUSI2SDL.Forms(), sffxs{}, []operand.Op{mr, x, x1}) +} + +// VCVTUSI2SDQ: Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// VCVTUSI2SDQ m64 xmm xmm +// VCVTUSI2SDQ r64 xmm xmm +func VCVTUSI2SDQ(mr, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUSI2SDQ.Forms(), sffxs{}, []operand.Op{mr, x, x1}) +} + +// VCVTUSI2SDQ_RD_SAE: Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTUSI2SDQ.RD_SAE r64 xmm xmm +func VCVTUSI2SDQ_RD_SAE(r, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUSI2SDQ.Forms(), sffxs{sffxRD_SAE}, []operand.Op{r, x, x1}) +} + +// VCVTUSI2SDQ_RN_SAE: Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value (Round Towards Nearest). +// +// Forms: +// +// VCVTUSI2SDQ.RN_SAE r64 xmm xmm +func VCVTUSI2SDQ_RN_SAE(r, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUSI2SDQ.Forms(), sffxs{sffxRN_SAE}, []operand.Op{r, x, x1}) +} + +// VCVTUSI2SDQ_RU_SAE: Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTUSI2SDQ.RU_SAE r64 xmm xmm +func VCVTUSI2SDQ_RU_SAE(r, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUSI2SDQ.Forms(), sffxs{sffxRU_SAE}, []operand.Op{r, x, x1}) +} + +// VCVTUSI2SDQ_RZ_SAE: Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value (Round Towards Zero). +// +// Forms: +// +// VCVTUSI2SDQ.RZ_SAE r64 xmm xmm +func VCVTUSI2SDQ_RZ_SAE(r, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUSI2SDQ.Forms(), sffxs{sffxRZ_SAE}, []operand.Op{r, x, x1}) +} + +// VCVTUSI2SSL: Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value. +// +// Forms: +// +// VCVTUSI2SSL m32 xmm xmm +// VCVTUSI2SSL r32 xmm xmm +func VCVTUSI2SSL(mr, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUSI2SSL.Forms(), sffxs{}, []operand.Op{mr, x, x1}) +} + +// VCVTUSI2SSL_RD_SAE: Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTUSI2SSL.RD_SAE r32 xmm xmm +func VCVTUSI2SSL_RD_SAE(r, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUSI2SSL.Forms(), sffxs{sffxRD_SAE}, []operand.Op{r, x, x1}) +} + +// VCVTUSI2SSL_RN_SAE: Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value (Round Towards Nearest). +// +// Forms: +// +// VCVTUSI2SSL.RN_SAE r32 xmm xmm +func VCVTUSI2SSL_RN_SAE(r, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUSI2SSL.Forms(), sffxs{sffxRN_SAE}, []operand.Op{r, x, x1}) +} + +// VCVTUSI2SSL_RU_SAE: Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTUSI2SSL.RU_SAE r32 xmm xmm +func VCVTUSI2SSL_RU_SAE(r, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUSI2SSL.Forms(), sffxs{sffxRU_SAE}, []operand.Op{r, x, x1}) +} + +// VCVTUSI2SSL_RZ_SAE: Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value (Round Towards Zero). +// +// Forms: +// +// VCVTUSI2SSL.RZ_SAE r32 xmm xmm +func VCVTUSI2SSL_RZ_SAE(r, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUSI2SSL.Forms(), sffxs{sffxRZ_SAE}, []operand.Op{r, x, x1}) +} + +// VCVTUSI2SSQ: Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value. +// +// Forms: +// +// VCVTUSI2SSQ m64 xmm xmm +// VCVTUSI2SSQ r64 xmm xmm +func VCVTUSI2SSQ(mr, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUSI2SSQ.Forms(), sffxs{}, []operand.Op{mr, x, x1}) +} + +// VCVTUSI2SSQ_RD_SAE: Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value (Round Towards Negative Infinity). +// +// Forms: +// +// VCVTUSI2SSQ.RD_SAE r64 xmm xmm +func VCVTUSI2SSQ_RD_SAE(r, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUSI2SSQ.Forms(), sffxs{sffxRD_SAE}, []operand.Op{r, x, x1}) +} + +// VCVTUSI2SSQ_RN_SAE: Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value (Round Towards Nearest). +// +// Forms: +// +// VCVTUSI2SSQ.RN_SAE r64 xmm xmm +func VCVTUSI2SSQ_RN_SAE(r, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUSI2SSQ.Forms(), sffxs{sffxRN_SAE}, []operand.Op{r, x, x1}) +} + +// VCVTUSI2SSQ_RU_SAE: Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value (Round Towards Positive Infinity). +// +// Forms: +// +// VCVTUSI2SSQ.RU_SAE r64 xmm xmm +func VCVTUSI2SSQ_RU_SAE(r, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUSI2SSQ.Forms(), sffxs{sffxRU_SAE}, []operand.Op{r, x, x1}) +} + +// VCVTUSI2SSQ_RZ_SAE: Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value (Round Towards Zero). +// +// Forms: +// +// VCVTUSI2SSQ.RZ_SAE r64 xmm xmm +func VCVTUSI2SSQ_RZ_SAE(r, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVCVTUSI2SSQ.Forms(), sffxs{sffxRZ_SAE}, []operand.Op{r, x, x1}) +} + +// VDBPSADBW: Double Block Packed Sum-Absolute-Differences on Unsigned Bytes. +// +// Forms: +// +// VDBPSADBW imm8 m128 xmm k xmm +// VDBPSADBW imm8 m128 xmm xmm +// VDBPSADBW imm8 m256 ymm k ymm +// VDBPSADBW imm8 m256 ymm ymm +// VDBPSADBW imm8 xmm xmm k xmm +// VDBPSADBW imm8 xmm xmm xmm +// VDBPSADBW imm8 ymm ymm k ymm +// VDBPSADBW imm8 ymm ymm ymm +// VDBPSADBW imm8 m512 zmm k zmm +// VDBPSADBW imm8 m512 zmm zmm +// VDBPSADBW imm8 zmm zmm k zmm +// VDBPSADBW imm8 zmm zmm zmm +func VDBPSADBW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVDBPSADBW.Forms(), sffxs{}, ops) +} + +// VDBPSADBW_Z: Double Block Packed Sum-Absolute-Differences on Unsigned Bytes (Zeroing Masking). +// +// Forms: +// +// VDBPSADBW.Z imm8 m128 xmm k xmm +// VDBPSADBW.Z imm8 m256 ymm k ymm +// VDBPSADBW.Z imm8 xmm xmm k xmm +// VDBPSADBW.Z imm8 ymm ymm k ymm +// VDBPSADBW.Z imm8 m512 zmm k zmm +// VDBPSADBW.Z imm8 zmm zmm k zmm +func VDBPSADBW_Z(i, mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVDBPSADBW.Forms(), sffxs{sffxZ}, []operand.Op{i, mxyz, xyz, k, xyz1}) +} + +// VDIVPD: Divide Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VDIVPD m128 xmm xmm +// VDIVPD m256 ymm ymm +// VDIVPD xmm xmm xmm +// VDIVPD ymm ymm ymm +// VDIVPD m128 xmm k xmm +// VDIVPD m256 ymm k ymm +// VDIVPD xmm xmm k xmm +// VDIVPD ymm ymm k ymm +// VDIVPD m512 zmm k zmm +// VDIVPD m512 zmm zmm +// VDIVPD zmm zmm k zmm +// VDIVPD zmm zmm zmm +func VDIVPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVPD.Forms(), sffxs{}, ops) +} + +// VDIVPD_BCST: Divide Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VDIVPD.BCST m64 xmm k xmm +// VDIVPD.BCST m64 xmm xmm +// VDIVPD.BCST m64 ymm k ymm +// VDIVPD.BCST m64 ymm ymm +// VDIVPD.BCST m64 zmm k zmm +// VDIVPD.BCST m64 zmm zmm +func VDIVPD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVPD.Forms(), sffxs{sffxBCST}, ops) +} + +// VDIVPD_BCST_Z: Divide Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VDIVPD.BCST.Z m64 xmm k xmm +// VDIVPD.BCST.Z m64 ymm k ymm +// VDIVPD.BCST.Z m64 zmm k zmm +func VDIVPD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVPD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VDIVPD_RD_SAE: Divide Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VDIVPD.RD_SAE zmm zmm k zmm +// VDIVPD.RD_SAE zmm zmm zmm +func VDIVPD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVPD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VDIVPD_RD_SAE_Z: Divide Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VDIVPD.RD_SAE.Z zmm zmm k zmm +func VDIVPD_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVPD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VDIVPD_RN_SAE: Divide Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VDIVPD.RN_SAE zmm zmm k zmm +// VDIVPD.RN_SAE zmm zmm zmm +func VDIVPD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVPD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VDIVPD_RN_SAE_Z: Divide Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VDIVPD.RN_SAE.Z zmm zmm k zmm +func VDIVPD_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVPD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VDIVPD_RU_SAE: Divide Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VDIVPD.RU_SAE zmm zmm k zmm +// VDIVPD.RU_SAE zmm zmm zmm +func VDIVPD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVPD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VDIVPD_RU_SAE_Z: Divide Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VDIVPD.RU_SAE.Z zmm zmm k zmm +func VDIVPD_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVPD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VDIVPD_RZ_SAE: Divide Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VDIVPD.RZ_SAE zmm zmm k zmm +// VDIVPD.RZ_SAE zmm zmm zmm +func VDIVPD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVPD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VDIVPD_RZ_SAE_Z: Divide Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VDIVPD.RZ_SAE.Z zmm zmm k zmm +func VDIVPD_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVPD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VDIVPD_Z: Divide Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VDIVPD.Z m128 xmm k xmm +// VDIVPD.Z m256 ymm k ymm +// VDIVPD.Z xmm xmm k xmm +// VDIVPD.Z ymm ymm k ymm +// VDIVPD.Z m512 zmm k zmm +// VDIVPD.Z zmm zmm k zmm +func VDIVPD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVPD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VDIVPS: Divide Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VDIVPS m128 xmm xmm +// VDIVPS m256 ymm ymm +// VDIVPS xmm xmm xmm +// VDIVPS ymm ymm ymm +// VDIVPS m128 xmm k xmm +// VDIVPS m256 ymm k ymm +// VDIVPS xmm xmm k xmm +// VDIVPS ymm ymm k ymm +// VDIVPS m512 zmm k zmm +// VDIVPS m512 zmm zmm +// VDIVPS zmm zmm k zmm +// VDIVPS zmm zmm zmm +func VDIVPS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVPS.Forms(), sffxs{}, ops) +} + +// VDIVPS_BCST: Divide Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VDIVPS.BCST m32 xmm k xmm +// VDIVPS.BCST m32 xmm xmm +// VDIVPS.BCST m32 ymm k ymm +// VDIVPS.BCST m32 ymm ymm +// VDIVPS.BCST m32 zmm k zmm +// VDIVPS.BCST m32 zmm zmm +func VDIVPS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVPS.Forms(), sffxs{sffxBCST}, ops) +} + +// VDIVPS_BCST_Z: Divide Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VDIVPS.BCST.Z m32 xmm k xmm +// VDIVPS.BCST.Z m32 ymm k ymm +// VDIVPS.BCST.Z m32 zmm k zmm +func VDIVPS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVPS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VDIVPS_RD_SAE: Divide Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VDIVPS.RD_SAE zmm zmm k zmm +// VDIVPS.RD_SAE zmm zmm zmm +func VDIVPS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVPS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VDIVPS_RD_SAE_Z: Divide Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VDIVPS.RD_SAE.Z zmm zmm k zmm +func VDIVPS_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVPS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VDIVPS_RN_SAE: Divide Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VDIVPS.RN_SAE zmm zmm k zmm +// VDIVPS.RN_SAE zmm zmm zmm +func VDIVPS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVPS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VDIVPS_RN_SAE_Z: Divide Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VDIVPS.RN_SAE.Z zmm zmm k zmm +func VDIVPS_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVPS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VDIVPS_RU_SAE: Divide Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VDIVPS.RU_SAE zmm zmm k zmm +// VDIVPS.RU_SAE zmm zmm zmm +func VDIVPS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVPS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VDIVPS_RU_SAE_Z: Divide Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VDIVPS.RU_SAE.Z zmm zmm k zmm +func VDIVPS_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVPS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VDIVPS_RZ_SAE: Divide Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VDIVPS.RZ_SAE zmm zmm k zmm +// VDIVPS.RZ_SAE zmm zmm zmm +func VDIVPS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVPS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VDIVPS_RZ_SAE_Z: Divide Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VDIVPS.RZ_SAE.Z zmm zmm k zmm +func VDIVPS_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVPS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VDIVPS_Z: Divide Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VDIVPS.Z m128 xmm k xmm +// VDIVPS.Z m256 ymm k ymm +// VDIVPS.Z xmm xmm k xmm +// VDIVPS.Z ymm ymm k ymm +// VDIVPS.Z m512 zmm k zmm +// VDIVPS.Z zmm zmm k zmm +func VDIVPS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVPS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VDIVSD: Divide Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VDIVSD m64 xmm xmm +// VDIVSD xmm xmm xmm +// VDIVSD m64 xmm k xmm +// VDIVSD xmm xmm k xmm +func VDIVSD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVSD.Forms(), sffxs{}, ops) +} + +// VDIVSD_RD_SAE: Divide Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VDIVSD.RD_SAE xmm xmm k xmm +// VDIVSD.RD_SAE xmm xmm xmm +func VDIVSD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVSD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VDIVSD_RD_SAE_Z: Divide Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VDIVSD.RD_SAE.Z xmm xmm k xmm +func VDIVSD_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVSD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VDIVSD_RN_SAE: Divide Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VDIVSD.RN_SAE xmm xmm k xmm +// VDIVSD.RN_SAE xmm xmm xmm +func VDIVSD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVSD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VDIVSD_RN_SAE_Z: Divide Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VDIVSD.RN_SAE.Z xmm xmm k xmm +func VDIVSD_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVSD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VDIVSD_RU_SAE: Divide Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VDIVSD.RU_SAE xmm xmm k xmm +// VDIVSD.RU_SAE xmm xmm xmm +func VDIVSD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVSD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VDIVSD_RU_SAE_Z: Divide Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VDIVSD.RU_SAE.Z xmm xmm k xmm +func VDIVSD_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVSD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VDIVSD_RZ_SAE: Divide Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VDIVSD.RZ_SAE xmm xmm k xmm +// VDIVSD.RZ_SAE xmm xmm xmm +func VDIVSD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVSD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VDIVSD_RZ_SAE_Z: Divide Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VDIVSD.RZ_SAE.Z xmm xmm k xmm +func VDIVSD_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVSD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VDIVSD_Z: Divide Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VDIVSD.Z m64 xmm k xmm +// VDIVSD.Z xmm xmm k xmm +func VDIVSD_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVSD.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VDIVSS: Divide Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VDIVSS m32 xmm xmm +// VDIVSS xmm xmm xmm +// VDIVSS m32 xmm k xmm +// VDIVSS xmm xmm k xmm +func VDIVSS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVSS.Forms(), sffxs{}, ops) +} + +// VDIVSS_RD_SAE: Divide Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VDIVSS.RD_SAE xmm xmm k xmm +// VDIVSS.RD_SAE xmm xmm xmm +func VDIVSS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVSS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VDIVSS_RD_SAE_Z: Divide Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VDIVSS.RD_SAE.Z xmm xmm k xmm +func VDIVSS_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVSS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VDIVSS_RN_SAE: Divide Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VDIVSS.RN_SAE xmm xmm k xmm +// VDIVSS.RN_SAE xmm xmm xmm +func VDIVSS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVSS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VDIVSS_RN_SAE_Z: Divide Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VDIVSS.RN_SAE.Z xmm xmm k xmm +func VDIVSS_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVSS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VDIVSS_RU_SAE: Divide Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VDIVSS.RU_SAE xmm xmm k xmm +// VDIVSS.RU_SAE xmm xmm xmm +func VDIVSS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVSS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VDIVSS_RU_SAE_Z: Divide Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VDIVSS.RU_SAE.Z xmm xmm k xmm +func VDIVSS_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVSS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VDIVSS_RZ_SAE: Divide Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VDIVSS.RZ_SAE xmm xmm k xmm +// VDIVSS.RZ_SAE xmm xmm xmm +func VDIVSS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVSS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VDIVSS_RZ_SAE_Z: Divide Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VDIVSS.RZ_SAE.Z xmm xmm k xmm +func VDIVSS_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVSS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VDIVSS_Z: Divide Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VDIVSS.Z m32 xmm k xmm +// VDIVSS.Z xmm xmm k xmm +func VDIVSS_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVDIVSS.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VDPPD: Dot Product of Packed Double Precision Floating-Point Values. +// +// Forms: +// +// VDPPD imm8 m128 xmm xmm +// VDPPD imm8 xmm xmm xmm +func VDPPD(i, mx, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVDPPD.Forms(), sffxs{}, []operand.Op{i, mx, x, x1}) +} + +// VDPPS: Dot Product of Packed Single Precision Floating-Point Values. +// +// Forms: +// +// VDPPS imm8 m128 xmm xmm +// VDPPS imm8 m256 ymm ymm +// VDPPS imm8 xmm xmm xmm +// VDPPS imm8 ymm ymm ymm +func VDPPS(i, mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { + return build(opcVDPPS.Forms(), sffxs{}, []operand.Op{i, mxy, xy, xy1}) +} + +// VEXP2PD: Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point Values with Less Than 2^-23 Relative Error. +// +// Forms: +// +// VEXP2PD m512 k zmm +// VEXP2PD m512 zmm +// VEXP2PD zmm k zmm +// VEXP2PD zmm zmm +func VEXP2PD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVEXP2PD.Forms(), sffxs{}, ops) +} + +// VEXP2PD_BCST: Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point Values with Less Than 2^-23 Relative Error (Broadcast). +// +// Forms: +// +// VEXP2PD.BCST m64 k zmm +// VEXP2PD.BCST m64 zmm +func VEXP2PD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVEXP2PD.Forms(), sffxs{sffxBCST}, ops) +} + +// VEXP2PD_BCST_Z: Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point Values with Less Than 2^-23 Relative Error (Broadcast, Zeroing Masking). +// +// Forms: +// +// VEXP2PD.BCST.Z m64 k zmm +func VEXP2PD_BCST_Z(m, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVEXP2PD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, z}) +} + +// VEXP2PD_SAE: Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point Values with Less Than 2^-23 Relative Error (Suppress All Exceptions). +// +// Forms: +// +// VEXP2PD.SAE zmm k zmm +// VEXP2PD.SAE zmm zmm +func VEXP2PD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVEXP2PD.Forms(), sffxs{sffxSAE}, ops) +} + +// VEXP2PD_SAE_Z: Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point Values with Less Than 2^-23 Relative Error (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VEXP2PD.SAE.Z zmm k zmm +func VEXP2PD_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVEXP2PD.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VEXP2PD_Z: Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point Values with Less Than 2^-23 Relative Error (Zeroing Masking). +// +// Forms: +// +// VEXP2PD.Z m512 k zmm +// VEXP2PD.Z zmm k zmm +func VEXP2PD_Z(mz, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVEXP2PD.Forms(), sffxs{sffxZ}, []operand.Op{mz, k, z}) +} + +// VEXP2PS: Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point Values with Less Than 2^-23 Relative Error. +// +// Forms: +// +// VEXP2PS m512 k zmm +// VEXP2PS m512 zmm +// VEXP2PS zmm k zmm +// VEXP2PS zmm zmm +func VEXP2PS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVEXP2PS.Forms(), sffxs{}, ops) +} + +// VEXP2PS_BCST: Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point Values with Less Than 2^-23 Relative Error (Broadcast). +// +// Forms: +// +// VEXP2PS.BCST m32 k zmm +// VEXP2PS.BCST m32 zmm +func VEXP2PS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVEXP2PS.Forms(), sffxs{sffxBCST}, ops) +} + +// VEXP2PS_BCST_Z: Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point Values with Less Than 2^-23 Relative Error (Broadcast, Zeroing Masking). +// +// Forms: +// +// VEXP2PS.BCST.Z m32 k zmm +func VEXP2PS_BCST_Z(m, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVEXP2PS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, z}) +} + +// VEXP2PS_SAE: Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point Values with Less Than 2^-23 Relative Error (Suppress All Exceptions). +// +// Forms: +// +// VEXP2PS.SAE zmm k zmm +// VEXP2PS.SAE zmm zmm +func VEXP2PS_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVEXP2PS.Forms(), sffxs{sffxSAE}, ops) +} + +// VEXP2PS_SAE_Z: Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point Values with Less Than 2^-23 Relative Error (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VEXP2PS.SAE.Z zmm k zmm +func VEXP2PS_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVEXP2PS.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VEXP2PS_Z: Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point Values with Less Than 2^-23 Relative Error (Zeroing Masking). +// +// Forms: +// +// VEXP2PS.Z m512 k zmm +// VEXP2PS.Z zmm k zmm +func VEXP2PS_Z(mz, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVEXP2PS.Forms(), sffxs{sffxZ}, []operand.Op{mz, k, z}) +} + +// VEXPANDPD: Load Sparse Packed Double-Precision Floating-Point Values from Dense Memory. +// +// Forms: +// +// VEXPANDPD m256 k ymm +// VEXPANDPD m256 ymm +// VEXPANDPD ymm k ymm +// VEXPANDPD ymm ymm +// VEXPANDPD m512 k zmm +// VEXPANDPD m512 zmm +// VEXPANDPD zmm k zmm +// VEXPANDPD zmm zmm +// VEXPANDPD m128 k xmm +// VEXPANDPD m128 xmm +// VEXPANDPD xmm k xmm +// VEXPANDPD xmm xmm +func VEXPANDPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVEXPANDPD.Forms(), sffxs{}, ops) +} + +// VEXPANDPD_Z: Load Sparse Packed Double-Precision Floating-Point Values from Dense Memory (Zeroing Masking). +// +// Forms: +// +// VEXPANDPD.Z m256 k ymm +// VEXPANDPD.Z ymm k ymm +// VEXPANDPD.Z m512 k zmm +// VEXPANDPD.Z zmm k zmm +// VEXPANDPD.Z m128 k xmm +// VEXPANDPD.Z xmm k xmm +func VEXPANDPD_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVEXPANDPD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) +} + +// VEXPANDPS: Load Sparse Packed Single-Precision Floating-Point Values from Dense Memory. +// +// Forms: +// +// VEXPANDPS m128 k xmm +// VEXPANDPS m128 xmm +// VEXPANDPS m256 k ymm +// VEXPANDPS m256 ymm +// VEXPANDPS xmm k xmm +// VEXPANDPS xmm xmm +// VEXPANDPS ymm k ymm +// VEXPANDPS ymm ymm +// VEXPANDPS m512 k zmm +// VEXPANDPS m512 zmm +// VEXPANDPS zmm k zmm +// VEXPANDPS zmm zmm +func VEXPANDPS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVEXPANDPS.Forms(), sffxs{}, ops) +} + +// VEXPANDPS_Z: Load Sparse Packed Single-Precision Floating-Point Values from Dense Memory (Zeroing Masking). +// +// Forms: +// +// VEXPANDPS.Z m128 k xmm +// VEXPANDPS.Z m256 k ymm +// VEXPANDPS.Z xmm k xmm +// VEXPANDPS.Z ymm k ymm +// VEXPANDPS.Z m512 k zmm +// VEXPANDPS.Z zmm k zmm +func VEXPANDPS_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVEXPANDPS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) +} + +// VEXTRACTF128: Extract Packed Floating-Point Values. +// +// Forms: +// +// VEXTRACTF128 imm8 ymm m128 +// VEXTRACTF128 imm8 ymm xmm +func VEXTRACTF128(i, y, mx operand.Op) (*intrep.Instruction, error) { + return build(opcVEXTRACTF128.Forms(), sffxs{}, []operand.Op{i, y, mx}) +} + +// VEXTRACTF32X4: Extract 128 Bits of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VEXTRACTF32X4 imm8 ymm k m128 +// VEXTRACTF32X4 imm8 ymm k xmm +// VEXTRACTF32X4 imm8 ymm m128 +// VEXTRACTF32X4 imm8 ymm xmm +// VEXTRACTF32X4 imm8 zmm k m128 +// VEXTRACTF32X4 imm8 zmm k xmm +// VEXTRACTF32X4 imm8 zmm m128 +// VEXTRACTF32X4 imm8 zmm xmm +func VEXTRACTF32X4(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVEXTRACTF32X4.Forms(), sffxs{}, ops) +} + +// VEXTRACTF32X4_Z: Extract 128 Bits of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VEXTRACTF32X4.Z imm8 ymm k m128 +// VEXTRACTF32X4.Z imm8 ymm k xmm +// VEXTRACTF32X4.Z imm8 zmm k m128 +// VEXTRACTF32X4.Z imm8 zmm k xmm +func VEXTRACTF32X4_Z(i, yz, k, mx operand.Op) (*intrep.Instruction, error) { + return build(opcVEXTRACTF32X4.Forms(), sffxs{sffxZ}, []operand.Op{i, yz, k, mx}) +} + +// VEXTRACTF32X8: Extract 256 Bits of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VEXTRACTF32X8 imm8 zmm k m256 +// VEXTRACTF32X8 imm8 zmm k ymm +// VEXTRACTF32X8 imm8 zmm m256 +// VEXTRACTF32X8 imm8 zmm ymm +func VEXTRACTF32X8(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVEXTRACTF32X8.Forms(), sffxs{}, ops) +} + +// VEXTRACTF32X8_Z: Extract 256 Bits of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VEXTRACTF32X8.Z imm8 zmm k m256 +// VEXTRACTF32X8.Z imm8 zmm k ymm +func VEXTRACTF32X8_Z(i, z, k, my operand.Op) (*intrep.Instruction, error) { + return build(opcVEXTRACTF32X8.Forms(), sffxs{sffxZ}, []operand.Op{i, z, k, my}) +} + +// VEXTRACTF64X2: Extract 128 Bits of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VEXTRACTF64X2 imm8 ymm k m128 +// VEXTRACTF64X2 imm8 ymm k xmm +// VEXTRACTF64X2 imm8 ymm m128 +// VEXTRACTF64X2 imm8 ymm xmm +// VEXTRACTF64X2 imm8 zmm k m128 +// VEXTRACTF64X2 imm8 zmm k xmm +// VEXTRACTF64X2 imm8 zmm m128 +// VEXTRACTF64X2 imm8 zmm xmm +func VEXTRACTF64X2(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVEXTRACTF64X2.Forms(), sffxs{}, ops) +} + +// VEXTRACTF64X2_Z: Extract 128 Bits of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VEXTRACTF64X2.Z imm8 ymm k m128 +// VEXTRACTF64X2.Z imm8 ymm k xmm +// VEXTRACTF64X2.Z imm8 zmm k m128 +// VEXTRACTF64X2.Z imm8 zmm k xmm +func VEXTRACTF64X2_Z(i, yz, k, mx operand.Op) (*intrep.Instruction, error) { + return build(opcVEXTRACTF64X2.Forms(), sffxs{sffxZ}, []operand.Op{i, yz, k, mx}) +} + +// VEXTRACTF64X4: Extract 256 Bits of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VEXTRACTF64X4 imm8 zmm k m256 +// VEXTRACTF64X4 imm8 zmm k ymm +// VEXTRACTF64X4 imm8 zmm m256 +// VEXTRACTF64X4 imm8 zmm ymm +func VEXTRACTF64X4(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVEXTRACTF64X4.Forms(), sffxs{}, ops) +} + +// VEXTRACTF64X4_Z: Extract 256 Bits of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VEXTRACTF64X4.Z imm8 zmm k m256 +// VEXTRACTF64X4.Z imm8 zmm k ymm +func VEXTRACTF64X4_Z(i, z, k, my operand.Op) (*intrep.Instruction, error) { + return build(opcVEXTRACTF64X4.Forms(), sffxs{sffxZ}, []operand.Op{i, z, k, my}) +} + +// VEXTRACTI128: Extract Packed Integer Values. +// +// Forms: +// +// VEXTRACTI128 imm8 ymm m128 +// VEXTRACTI128 imm8 ymm xmm +func VEXTRACTI128(i, y, mx operand.Op) (*intrep.Instruction, error) { + return build(opcVEXTRACTI128.Forms(), sffxs{}, []operand.Op{i, y, mx}) +} + +// VEXTRACTI32X4: Extract 128 Bits of Packed Doubleword Integer Values. +// +// Forms: +// +// VEXTRACTI32X4 imm8 ymm k m128 +// VEXTRACTI32X4 imm8 ymm k xmm +// VEXTRACTI32X4 imm8 ymm m128 +// VEXTRACTI32X4 imm8 ymm xmm +// VEXTRACTI32X4 imm8 zmm k m128 +// VEXTRACTI32X4 imm8 zmm k xmm +// VEXTRACTI32X4 imm8 zmm m128 +// VEXTRACTI32X4 imm8 zmm xmm +func VEXTRACTI32X4(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVEXTRACTI32X4.Forms(), sffxs{}, ops) +} + +// VEXTRACTI32X4_Z: Extract 128 Bits of Packed Doubleword Integer Values (Zeroing Masking). +// +// Forms: +// +// VEXTRACTI32X4.Z imm8 ymm k m128 +// VEXTRACTI32X4.Z imm8 ymm k xmm +// VEXTRACTI32X4.Z imm8 zmm k m128 +// VEXTRACTI32X4.Z imm8 zmm k xmm +func VEXTRACTI32X4_Z(i, yz, k, mx operand.Op) (*intrep.Instruction, error) { + return build(opcVEXTRACTI32X4.Forms(), sffxs{sffxZ}, []operand.Op{i, yz, k, mx}) +} + +// VEXTRACTI32X8: Extract 256 Bits of Packed Doubleword Integer Values. +// +// Forms: +// +// VEXTRACTI32X8 imm8 zmm k m256 +// VEXTRACTI32X8 imm8 zmm k ymm +// VEXTRACTI32X8 imm8 zmm m256 +// VEXTRACTI32X8 imm8 zmm ymm +func VEXTRACTI32X8(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVEXTRACTI32X8.Forms(), sffxs{}, ops) +} + +// VEXTRACTI32X8_Z: Extract 256 Bits of Packed Doubleword Integer Values (Zeroing Masking). +// +// Forms: +// +// VEXTRACTI32X8.Z imm8 zmm k m256 +// VEXTRACTI32X8.Z imm8 zmm k ymm +func VEXTRACTI32X8_Z(i, z, k, my operand.Op) (*intrep.Instruction, error) { + return build(opcVEXTRACTI32X8.Forms(), sffxs{sffxZ}, []operand.Op{i, z, k, my}) +} + +// VEXTRACTI64X2: Extract 128 Bits of Packed Quadword Integer Values. +// +// Forms: +// +// VEXTRACTI64X2 imm8 ymm k m128 +// VEXTRACTI64X2 imm8 ymm k xmm +// VEXTRACTI64X2 imm8 ymm m128 +// VEXTRACTI64X2 imm8 ymm xmm +// VEXTRACTI64X2 imm8 zmm k m128 +// VEXTRACTI64X2 imm8 zmm k xmm +// VEXTRACTI64X2 imm8 zmm m128 +// VEXTRACTI64X2 imm8 zmm xmm +func VEXTRACTI64X2(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVEXTRACTI64X2.Forms(), sffxs{}, ops) +} + +// VEXTRACTI64X2_Z: Extract 128 Bits of Packed Quadword Integer Values (Zeroing Masking). +// +// Forms: +// +// VEXTRACTI64X2.Z imm8 ymm k m128 +// VEXTRACTI64X2.Z imm8 ymm k xmm +// VEXTRACTI64X2.Z imm8 zmm k m128 +// VEXTRACTI64X2.Z imm8 zmm k xmm +func VEXTRACTI64X2_Z(i, yz, k, mx operand.Op) (*intrep.Instruction, error) { + return build(opcVEXTRACTI64X2.Forms(), sffxs{sffxZ}, []operand.Op{i, yz, k, mx}) +} + +// VEXTRACTI64X4: Extract 256 Bits of Packed Quadword Integer Values. +// +// Forms: +// +// VEXTRACTI64X4 imm8 zmm k m256 +// VEXTRACTI64X4 imm8 zmm k ymm +// VEXTRACTI64X4 imm8 zmm m256 +// VEXTRACTI64X4 imm8 zmm ymm +func VEXTRACTI64X4(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVEXTRACTI64X4.Forms(), sffxs{}, ops) +} + +// VEXTRACTI64X4_Z: Extract 256 Bits of Packed Quadword Integer Values (Zeroing Masking). +// +// Forms: +// +// VEXTRACTI64X4.Z imm8 zmm k m256 +// VEXTRACTI64X4.Z imm8 zmm k ymm +func VEXTRACTI64X4_Z(i, z, k, my operand.Op) (*intrep.Instruction, error) { + return build(opcVEXTRACTI64X4.Forms(), sffxs{sffxZ}, []operand.Op{i, z, k, my}) +} + +// VEXTRACTPS: Extract Packed Single Precision Floating-Point Value. +// +// Forms: +// +// VEXTRACTPS imm8 xmm m32 +// VEXTRACTPS imm8 xmm r32 +func VEXTRACTPS(i, x, mr operand.Op) (*intrep.Instruction, error) { + return build(opcVEXTRACTPS.Forms(), sffxs{}, []operand.Op{i, x, mr}) +} + +// VFIXUPIMMPD: Fix Up Special Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFIXUPIMMPD imm8 m128 xmm k xmm +// VFIXUPIMMPD imm8 m128 xmm xmm +// VFIXUPIMMPD imm8 m256 ymm k ymm +// VFIXUPIMMPD imm8 m256 ymm ymm +// VFIXUPIMMPD imm8 xmm xmm k xmm +// VFIXUPIMMPD imm8 xmm xmm xmm +// VFIXUPIMMPD imm8 ymm ymm k ymm +// VFIXUPIMMPD imm8 ymm ymm ymm +// VFIXUPIMMPD imm8 m512 zmm k zmm +// VFIXUPIMMPD imm8 m512 zmm zmm +// VFIXUPIMMPD imm8 zmm zmm k zmm +// VFIXUPIMMPD imm8 zmm zmm zmm +func VFIXUPIMMPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFIXUPIMMPD.Forms(), sffxs{}, ops) +} + +// VFIXUPIMMPD_BCST: Fix Up Special Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFIXUPIMMPD.BCST imm8 m64 xmm k xmm +// VFIXUPIMMPD.BCST imm8 m64 xmm xmm +// VFIXUPIMMPD.BCST imm8 m64 ymm k ymm +// VFIXUPIMMPD.BCST imm8 m64 ymm ymm +// VFIXUPIMMPD.BCST imm8 m64 zmm k zmm +// VFIXUPIMMPD.BCST imm8 m64 zmm zmm +func VFIXUPIMMPD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFIXUPIMMPD.Forms(), sffxs{sffxBCST}, ops) +} + +// VFIXUPIMMPD_BCST_Z: Fix Up Special Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFIXUPIMMPD.BCST.Z imm8 m64 xmm k xmm +// VFIXUPIMMPD.BCST.Z imm8 m64 ymm k ymm +// VFIXUPIMMPD.BCST.Z imm8 m64 zmm k zmm +func VFIXUPIMMPD_BCST_Z(i, m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFIXUPIMMPD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{i, m, xyz, k, xyz1}) +} + +// VFIXUPIMMPD_SAE: Fix Up Special Packed Double-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VFIXUPIMMPD.SAE imm8 zmm zmm k zmm +// VFIXUPIMMPD.SAE imm8 zmm zmm zmm +func VFIXUPIMMPD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFIXUPIMMPD.Forms(), sffxs{sffxSAE}, ops) +} + +// VFIXUPIMMPD_SAE_Z: Fix Up Special Packed Double-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VFIXUPIMMPD.SAE.Z imm8 zmm zmm k zmm +func VFIXUPIMMPD_SAE_Z(i, z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFIXUPIMMPD.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{i, z, z1, k, z2}) +} + +// VFIXUPIMMPD_Z: Fix Up Special Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFIXUPIMMPD.Z imm8 m128 xmm k xmm +// VFIXUPIMMPD.Z imm8 m256 ymm k ymm +// VFIXUPIMMPD.Z imm8 xmm xmm k xmm +// VFIXUPIMMPD.Z imm8 ymm ymm k ymm +// VFIXUPIMMPD.Z imm8 m512 zmm k zmm +// VFIXUPIMMPD.Z imm8 zmm zmm k zmm +func VFIXUPIMMPD_Z(i, mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFIXUPIMMPD.Forms(), sffxs{sffxZ}, []operand.Op{i, mxyz, xyz, k, xyz1}) +} + +// VFIXUPIMMPS: Fix Up Special Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFIXUPIMMPS imm8 m256 ymm k ymm +// VFIXUPIMMPS imm8 m256 ymm ymm +// VFIXUPIMMPS imm8 ymm ymm k ymm +// VFIXUPIMMPS imm8 ymm ymm ymm +// VFIXUPIMMPS imm8 m512 zmm k zmm +// VFIXUPIMMPS imm8 m512 zmm zmm +// VFIXUPIMMPS imm8 zmm zmm k zmm +// VFIXUPIMMPS imm8 zmm zmm zmm +// VFIXUPIMMPS imm8 m128 xmm k xmm +// VFIXUPIMMPS imm8 m128 xmm xmm +// VFIXUPIMMPS imm8 xmm xmm k xmm +// VFIXUPIMMPS imm8 xmm xmm xmm +func VFIXUPIMMPS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFIXUPIMMPS.Forms(), sffxs{}, ops) +} + +// VFIXUPIMMPS_BCST: Fix Up Special Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFIXUPIMMPS.BCST imm8 m32 ymm k ymm +// VFIXUPIMMPS.BCST imm8 m32 ymm ymm +// VFIXUPIMMPS.BCST imm8 m32 zmm k zmm +// VFIXUPIMMPS.BCST imm8 m32 zmm zmm +// VFIXUPIMMPS.BCST imm8 m32 xmm k xmm +// VFIXUPIMMPS.BCST imm8 m32 xmm xmm +func VFIXUPIMMPS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFIXUPIMMPS.Forms(), sffxs{sffxBCST}, ops) +} + +// VFIXUPIMMPS_BCST_Z: Fix Up Special Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFIXUPIMMPS.BCST.Z imm8 m32 ymm k ymm +// VFIXUPIMMPS.BCST.Z imm8 m32 zmm k zmm +// VFIXUPIMMPS.BCST.Z imm8 m32 xmm k xmm +func VFIXUPIMMPS_BCST_Z(i, m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFIXUPIMMPS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{i, m, xyz, k, xyz1}) +} + +// VFIXUPIMMPS_SAE: Fix Up Special Packed Single-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VFIXUPIMMPS.SAE imm8 zmm zmm k zmm +// VFIXUPIMMPS.SAE imm8 zmm zmm zmm +func VFIXUPIMMPS_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFIXUPIMMPS.Forms(), sffxs{sffxSAE}, ops) +} + +// VFIXUPIMMPS_SAE_Z: Fix Up Special Packed Single-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VFIXUPIMMPS.SAE.Z imm8 zmm zmm k zmm +func VFIXUPIMMPS_SAE_Z(i, z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFIXUPIMMPS.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{i, z, z1, k, z2}) +} + +// VFIXUPIMMPS_Z: Fix Up Special Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFIXUPIMMPS.Z imm8 m256 ymm k ymm +// VFIXUPIMMPS.Z imm8 ymm ymm k ymm +// VFIXUPIMMPS.Z imm8 m512 zmm k zmm +// VFIXUPIMMPS.Z imm8 zmm zmm k zmm +// VFIXUPIMMPS.Z imm8 m128 xmm k xmm +// VFIXUPIMMPS.Z imm8 xmm xmm k xmm +func VFIXUPIMMPS_Z(i, mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFIXUPIMMPS.Forms(), sffxs{sffxZ}, []operand.Op{i, mxyz, xyz, k, xyz1}) +} + +// VFIXUPIMMSD: Fix Up Special Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// VFIXUPIMMSD imm8 m64 xmm k xmm +// VFIXUPIMMSD imm8 m64 xmm xmm +// VFIXUPIMMSD imm8 xmm xmm k xmm +// VFIXUPIMMSD imm8 xmm xmm xmm +func VFIXUPIMMSD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFIXUPIMMSD.Forms(), sffxs{}, ops) +} + +// VFIXUPIMMSD_SAE: Fix Up Special Scalar Double-Precision Floating-Point Value (Suppress All Exceptions). +// +// Forms: +// +// VFIXUPIMMSD.SAE imm8 xmm xmm k xmm +// VFIXUPIMMSD.SAE imm8 xmm xmm xmm +func VFIXUPIMMSD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFIXUPIMMSD.Forms(), sffxs{sffxSAE}, ops) +} + +// VFIXUPIMMSD_SAE_Z: Fix Up Special Scalar Double-Precision Floating-Point Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VFIXUPIMMSD.SAE.Z imm8 xmm xmm k xmm +func VFIXUPIMMSD_SAE_Z(i, x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFIXUPIMMSD.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{i, x, x1, k, x2}) +} + +// VFIXUPIMMSD_Z: Fix Up Special Scalar Double-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VFIXUPIMMSD.Z imm8 m64 xmm k xmm +// VFIXUPIMMSD.Z imm8 xmm xmm k xmm +func VFIXUPIMMSD_Z(i, mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFIXUPIMMSD.Forms(), sffxs{sffxZ}, []operand.Op{i, mx, x, k, x1}) +} + +// VFIXUPIMMSS: Fix Up Special Scalar Single-Precision Floating-Point Value. +// +// Forms: +// +// VFIXUPIMMSS imm8 m32 xmm k xmm +// VFIXUPIMMSS imm8 m32 xmm xmm +// VFIXUPIMMSS imm8 xmm xmm k xmm +// VFIXUPIMMSS imm8 xmm xmm xmm +func VFIXUPIMMSS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFIXUPIMMSS.Forms(), sffxs{}, ops) +} + +// VFIXUPIMMSS_SAE: Fix Up Special Scalar Single-Precision Floating-Point Value (Suppress All Exceptions). +// +// Forms: +// +// VFIXUPIMMSS.SAE imm8 xmm xmm k xmm +// VFIXUPIMMSS.SAE imm8 xmm xmm xmm +func VFIXUPIMMSS_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFIXUPIMMSS.Forms(), sffxs{sffxSAE}, ops) +} + +// VFIXUPIMMSS_SAE_Z: Fix Up Special Scalar Single-Precision Floating-Point Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VFIXUPIMMSS.SAE.Z imm8 xmm xmm k xmm +func VFIXUPIMMSS_SAE_Z(i, x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFIXUPIMMSS.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{i, x, x1, k, x2}) +} + +// VFIXUPIMMSS_Z: Fix Up Special Scalar Single-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VFIXUPIMMSS.Z imm8 m32 xmm k xmm +// VFIXUPIMMSS.Z imm8 xmm xmm k xmm +func VFIXUPIMMSS_Z(i, mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFIXUPIMMSS.Forms(), sffxs{sffxZ}, []operand.Op{i, mx, x, k, x1}) +} + +// VFMADD132PD: Fused Multiply-Add of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD132PD m128 xmm xmm +// VFMADD132PD m256 ymm ymm +// VFMADD132PD xmm xmm xmm +// VFMADD132PD ymm ymm ymm +// VFMADD132PD m128 xmm k xmm +// VFMADD132PD m256 ymm k ymm +// VFMADD132PD xmm xmm k xmm +// VFMADD132PD ymm ymm k ymm +// VFMADD132PD m512 zmm k zmm +// VFMADD132PD m512 zmm zmm +// VFMADD132PD zmm zmm k zmm +// VFMADD132PD zmm zmm zmm +func VFMADD132PD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132PD.Forms(), sffxs{}, ops) +} + +// VFMADD132PD_BCST: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADD132PD.BCST m64 xmm k xmm +// VFMADD132PD.BCST m64 xmm xmm +// VFMADD132PD.BCST m64 ymm k ymm +// VFMADD132PD.BCST m64 ymm ymm +// VFMADD132PD.BCST m64 zmm k zmm +// VFMADD132PD.BCST m64 zmm zmm +func VFMADD132PD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132PD.Forms(), sffxs{sffxBCST}, ops) +} + +// VFMADD132PD_BCST_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADD132PD.BCST.Z m64 xmm k xmm +// VFMADD132PD.BCST.Z m64 ymm k ymm +// VFMADD132PD.BCST.Z m64 zmm k zmm +func VFMADD132PD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132PD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFMADD132PD_RD_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD132PD.RD_SAE zmm zmm k zmm +// VFMADD132PD.RD_SAE zmm zmm zmm +func VFMADD132PD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132PD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMADD132PD_RD_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD132PD.RD_SAE.Z zmm zmm k zmm +func VFMADD132PD_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132PD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADD132PD_RN_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD132PD.RN_SAE zmm zmm k zmm +// VFMADD132PD.RN_SAE zmm zmm zmm +func VFMADD132PD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132PD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMADD132PD_RN_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD132PD.RN_SAE.Z zmm zmm k zmm +func VFMADD132PD_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132PD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADD132PD_RU_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD132PD.RU_SAE zmm zmm k zmm +// VFMADD132PD.RU_SAE zmm zmm zmm +func VFMADD132PD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132PD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMADD132PD_RU_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD132PD.RU_SAE.Z zmm zmm k zmm +func VFMADD132PD_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132PD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADD132PD_RZ_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD132PD.RZ_SAE zmm zmm k zmm +// VFMADD132PD.RZ_SAE zmm zmm zmm +func VFMADD132PD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132PD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMADD132PD_RZ_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD132PD.RZ_SAE.Z zmm zmm k zmm +func VFMADD132PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132PD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADD132PD_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD132PD.Z m128 xmm k xmm +// VFMADD132PD.Z m256 ymm k ymm +// VFMADD132PD.Z xmm xmm k xmm +// VFMADD132PD.Z ymm ymm k ymm +// VFMADD132PD.Z m512 zmm k zmm +// VFMADD132PD.Z zmm zmm k zmm +func VFMADD132PD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132PD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFMADD132PS: Fused Multiply-Add of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD132PS m128 xmm xmm +// VFMADD132PS m256 ymm ymm +// VFMADD132PS xmm xmm xmm +// VFMADD132PS ymm ymm ymm +// VFMADD132PS m128 xmm k xmm +// VFMADD132PS m256 ymm k ymm +// VFMADD132PS xmm xmm k xmm +// VFMADD132PS ymm ymm k ymm +// VFMADD132PS m512 zmm k zmm +// VFMADD132PS m512 zmm zmm +// VFMADD132PS zmm zmm k zmm +// VFMADD132PS zmm zmm zmm +func VFMADD132PS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132PS.Forms(), sffxs{}, ops) +} + +// VFMADD132PS_BCST: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADD132PS.BCST m32 xmm k xmm +// VFMADD132PS.BCST m32 xmm xmm +// VFMADD132PS.BCST m32 ymm k ymm +// VFMADD132PS.BCST m32 ymm ymm +// VFMADD132PS.BCST m32 zmm k zmm +// VFMADD132PS.BCST m32 zmm zmm +func VFMADD132PS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132PS.Forms(), sffxs{sffxBCST}, ops) +} + +// VFMADD132PS_BCST_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADD132PS.BCST.Z m32 xmm k xmm +// VFMADD132PS.BCST.Z m32 ymm k ymm +// VFMADD132PS.BCST.Z m32 zmm k zmm +func VFMADD132PS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132PS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFMADD132PS_RD_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD132PS.RD_SAE zmm zmm k zmm +// VFMADD132PS.RD_SAE zmm zmm zmm +func VFMADD132PS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132PS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMADD132PS_RD_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD132PS.RD_SAE.Z zmm zmm k zmm +func VFMADD132PS_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132PS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADD132PS_RN_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD132PS.RN_SAE zmm zmm k zmm +// VFMADD132PS.RN_SAE zmm zmm zmm +func VFMADD132PS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132PS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMADD132PS_RN_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD132PS.RN_SAE.Z zmm zmm k zmm +func VFMADD132PS_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132PS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADD132PS_RU_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD132PS.RU_SAE zmm zmm k zmm +// VFMADD132PS.RU_SAE zmm zmm zmm +func VFMADD132PS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132PS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMADD132PS_RU_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD132PS.RU_SAE.Z zmm zmm k zmm +func VFMADD132PS_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132PS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADD132PS_RZ_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD132PS.RZ_SAE zmm zmm k zmm +// VFMADD132PS.RZ_SAE zmm zmm zmm +func VFMADD132PS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132PS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMADD132PS_RZ_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD132PS.RZ_SAE.Z zmm zmm k zmm +func VFMADD132PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132PS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADD132PS_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD132PS.Z m128 xmm k xmm +// VFMADD132PS.Z m256 ymm k ymm +// VFMADD132PS.Z xmm xmm k xmm +// VFMADD132PS.Z ymm ymm k ymm +// VFMADD132PS.Z m512 zmm k zmm +// VFMADD132PS.Z zmm zmm k zmm +func VFMADD132PS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132PS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFMADD132SD: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD132SD m64 xmm xmm +// VFMADD132SD xmm xmm xmm +// VFMADD132SD m64 xmm k xmm +// VFMADD132SD xmm xmm k xmm +func VFMADD132SD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132SD.Forms(), sffxs{}, ops) +} + +// VFMADD132SD_RD_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD132SD.RD_SAE xmm xmm k xmm +// VFMADD132SD.RD_SAE xmm xmm xmm +func VFMADD132SD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132SD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMADD132SD_RD_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD132SD.RD_SAE.Z xmm xmm k xmm +func VFMADD132SD_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132SD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMADD132SD_RN_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD132SD.RN_SAE xmm xmm k xmm +// VFMADD132SD.RN_SAE xmm xmm xmm +func VFMADD132SD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132SD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMADD132SD_RN_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD132SD.RN_SAE.Z xmm xmm k xmm +func VFMADD132SD_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132SD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMADD132SD_RU_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD132SD.RU_SAE xmm xmm k xmm +// VFMADD132SD.RU_SAE xmm xmm xmm +func VFMADD132SD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132SD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMADD132SD_RU_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD132SD.RU_SAE.Z xmm xmm k xmm +func VFMADD132SD_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132SD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMADD132SD_RZ_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD132SD.RZ_SAE xmm xmm k xmm +// VFMADD132SD.RZ_SAE xmm xmm xmm +func VFMADD132SD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132SD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMADD132SD_RZ_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD132SD.RZ_SAE.Z xmm xmm k xmm +func VFMADD132SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132SD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMADD132SD_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD132SD.Z m64 xmm k xmm +// VFMADD132SD.Z xmm xmm k xmm +func VFMADD132SD_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132SD.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VFMADD132SS: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD132SS m32 xmm xmm +// VFMADD132SS xmm xmm xmm +// VFMADD132SS m32 xmm k xmm +// VFMADD132SS xmm xmm k xmm +func VFMADD132SS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132SS.Forms(), sffxs{}, ops) +} + +// VFMADD132SS_RD_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD132SS.RD_SAE xmm xmm k xmm +// VFMADD132SS.RD_SAE xmm xmm xmm +func VFMADD132SS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132SS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMADD132SS_RD_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD132SS.RD_SAE.Z xmm xmm k xmm +func VFMADD132SS_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132SS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMADD132SS_RN_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD132SS.RN_SAE xmm xmm k xmm +// VFMADD132SS.RN_SAE xmm xmm xmm +func VFMADD132SS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132SS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMADD132SS_RN_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD132SS.RN_SAE.Z xmm xmm k xmm +func VFMADD132SS_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132SS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMADD132SS_RU_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD132SS.RU_SAE xmm xmm k xmm +// VFMADD132SS.RU_SAE xmm xmm xmm +func VFMADD132SS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132SS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMADD132SS_RU_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD132SS.RU_SAE.Z xmm xmm k xmm +func VFMADD132SS_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132SS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMADD132SS_RZ_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD132SS.RZ_SAE xmm xmm k xmm +// VFMADD132SS.RZ_SAE xmm xmm xmm +func VFMADD132SS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132SS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMADD132SS_RZ_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD132SS.RZ_SAE.Z xmm xmm k xmm +func VFMADD132SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132SS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMADD132SS_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD132SS.Z m32 xmm k xmm +// VFMADD132SS.Z xmm xmm k xmm +func VFMADD132SS_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD132SS.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VFMADD213PD: Fused Multiply-Add of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD213PD m128 xmm xmm +// VFMADD213PD m256 ymm ymm +// VFMADD213PD xmm xmm xmm +// VFMADD213PD ymm ymm ymm +// VFMADD213PD m128 xmm k xmm +// VFMADD213PD m256 ymm k ymm +// VFMADD213PD xmm xmm k xmm +// VFMADD213PD ymm ymm k ymm +// VFMADD213PD m512 zmm k zmm +// VFMADD213PD m512 zmm zmm +// VFMADD213PD zmm zmm k zmm +// VFMADD213PD zmm zmm zmm +func VFMADD213PD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213PD.Forms(), sffxs{}, ops) +} + +// VFMADD213PD_BCST: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADD213PD.BCST m64 xmm k xmm +// VFMADD213PD.BCST m64 xmm xmm +// VFMADD213PD.BCST m64 ymm k ymm +// VFMADD213PD.BCST m64 ymm ymm +// VFMADD213PD.BCST m64 zmm k zmm +// VFMADD213PD.BCST m64 zmm zmm +func VFMADD213PD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213PD.Forms(), sffxs{sffxBCST}, ops) +} + +// VFMADD213PD_BCST_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADD213PD.BCST.Z m64 xmm k xmm +// VFMADD213PD.BCST.Z m64 ymm k ymm +// VFMADD213PD.BCST.Z m64 zmm k zmm +func VFMADD213PD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213PD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFMADD213PD_RD_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD213PD.RD_SAE zmm zmm k zmm +// VFMADD213PD.RD_SAE zmm zmm zmm +func VFMADD213PD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213PD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMADD213PD_RD_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD213PD.RD_SAE.Z zmm zmm k zmm +func VFMADD213PD_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213PD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADD213PD_RN_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD213PD.RN_SAE zmm zmm k zmm +// VFMADD213PD.RN_SAE zmm zmm zmm +func VFMADD213PD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213PD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMADD213PD_RN_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD213PD.RN_SAE.Z zmm zmm k zmm +func VFMADD213PD_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213PD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADD213PD_RU_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD213PD.RU_SAE zmm zmm k zmm +// VFMADD213PD.RU_SAE zmm zmm zmm +func VFMADD213PD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213PD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMADD213PD_RU_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD213PD.RU_SAE.Z zmm zmm k zmm +func VFMADD213PD_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213PD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADD213PD_RZ_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD213PD.RZ_SAE zmm zmm k zmm +// VFMADD213PD.RZ_SAE zmm zmm zmm +func VFMADD213PD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213PD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMADD213PD_RZ_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD213PD.RZ_SAE.Z zmm zmm k zmm +func VFMADD213PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213PD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADD213PD_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD213PD.Z m128 xmm k xmm +// VFMADD213PD.Z m256 ymm k ymm +// VFMADD213PD.Z xmm xmm k xmm +// VFMADD213PD.Z ymm ymm k ymm +// VFMADD213PD.Z m512 zmm k zmm +// VFMADD213PD.Z zmm zmm k zmm +func VFMADD213PD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213PD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFMADD213PS: Fused Multiply-Add of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD213PS m128 xmm xmm +// VFMADD213PS m256 ymm ymm +// VFMADD213PS xmm xmm xmm +// VFMADD213PS ymm ymm ymm +// VFMADD213PS m128 xmm k xmm +// VFMADD213PS m256 ymm k ymm +// VFMADD213PS xmm xmm k xmm +// VFMADD213PS ymm ymm k ymm +// VFMADD213PS m512 zmm k zmm +// VFMADD213PS m512 zmm zmm +// VFMADD213PS zmm zmm k zmm +// VFMADD213PS zmm zmm zmm +func VFMADD213PS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213PS.Forms(), sffxs{}, ops) +} + +// VFMADD213PS_BCST: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADD213PS.BCST m32 xmm k xmm +// VFMADD213PS.BCST m32 xmm xmm +// VFMADD213PS.BCST m32 ymm k ymm +// VFMADD213PS.BCST m32 ymm ymm +// VFMADD213PS.BCST m32 zmm k zmm +// VFMADD213PS.BCST m32 zmm zmm +func VFMADD213PS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213PS.Forms(), sffxs{sffxBCST}, ops) +} + +// VFMADD213PS_BCST_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADD213PS.BCST.Z m32 xmm k xmm +// VFMADD213PS.BCST.Z m32 ymm k ymm +// VFMADD213PS.BCST.Z m32 zmm k zmm +func VFMADD213PS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213PS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFMADD213PS_RD_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD213PS.RD_SAE zmm zmm k zmm +// VFMADD213PS.RD_SAE zmm zmm zmm +func VFMADD213PS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213PS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMADD213PS_RD_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD213PS.RD_SAE.Z zmm zmm k zmm +func VFMADD213PS_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213PS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADD213PS_RN_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD213PS.RN_SAE zmm zmm k zmm +// VFMADD213PS.RN_SAE zmm zmm zmm +func VFMADD213PS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213PS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMADD213PS_RN_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD213PS.RN_SAE.Z zmm zmm k zmm +func VFMADD213PS_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213PS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADD213PS_RU_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD213PS.RU_SAE zmm zmm k zmm +// VFMADD213PS.RU_SAE zmm zmm zmm +func VFMADD213PS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213PS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMADD213PS_RU_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD213PS.RU_SAE.Z zmm zmm k zmm +func VFMADD213PS_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213PS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADD213PS_RZ_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD213PS.RZ_SAE zmm zmm k zmm +// VFMADD213PS.RZ_SAE zmm zmm zmm +func VFMADD213PS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213PS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMADD213PS_RZ_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD213PS.RZ_SAE.Z zmm zmm k zmm +func VFMADD213PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213PS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADD213PS_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD213PS.Z m128 xmm k xmm +// VFMADD213PS.Z m256 ymm k ymm +// VFMADD213PS.Z xmm xmm k xmm +// VFMADD213PS.Z ymm ymm k ymm +// VFMADD213PS.Z m512 zmm k zmm +// VFMADD213PS.Z zmm zmm k zmm +func VFMADD213PS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213PS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFMADD213SD: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD213SD m64 xmm xmm +// VFMADD213SD xmm xmm xmm +// VFMADD213SD m64 xmm k xmm +// VFMADD213SD xmm xmm k xmm +func VFMADD213SD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213SD.Forms(), sffxs{}, ops) +} + +// VFMADD213SD_RD_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD213SD.RD_SAE xmm xmm k xmm +// VFMADD213SD.RD_SAE xmm xmm xmm +func VFMADD213SD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213SD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMADD213SD_RD_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD213SD.RD_SAE.Z xmm xmm k xmm +func VFMADD213SD_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213SD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMADD213SD_RN_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD213SD.RN_SAE xmm xmm k xmm +// VFMADD213SD.RN_SAE xmm xmm xmm +func VFMADD213SD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213SD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMADD213SD_RN_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD213SD.RN_SAE.Z xmm xmm k xmm +func VFMADD213SD_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213SD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMADD213SD_RU_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD213SD.RU_SAE xmm xmm k xmm +// VFMADD213SD.RU_SAE xmm xmm xmm +func VFMADD213SD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213SD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMADD213SD_RU_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD213SD.RU_SAE.Z xmm xmm k xmm +func VFMADD213SD_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213SD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMADD213SD_RZ_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD213SD.RZ_SAE xmm xmm k xmm +// VFMADD213SD.RZ_SAE xmm xmm xmm +func VFMADD213SD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213SD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMADD213SD_RZ_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD213SD.RZ_SAE.Z xmm xmm k xmm +func VFMADD213SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213SD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMADD213SD_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD213SD.Z m64 xmm k xmm +// VFMADD213SD.Z xmm xmm k xmm +func VFMADD213SD_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213SD.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VFMADD213SS: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD213SS m32 xmm xmm +// VFMADD213SS xmm xmm xmm +// VFMADD213SS m32 xmm k xmm +// VFMADD213SS xmm xmm k xmm +func VFMADD213SS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213SS.Forms(), sffxs{}, ops) +} + +// VFMADD213SS_RD_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD213SS.RD_SAE xmm xmm k xmm +// VFMADD213SS.RD_SAE xmm xmm xmm +func VFMADD213SS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213SS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMADD213SS_RD_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD213SS.RD_SAE.Z xmm xmm k xmm +func VFMADD213SS_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213SS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMADD213SS_RN_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD213SS.RN_SAE xmm xmm k xmm +// VFMADD213SS.RN_SAE xmm xmm xmm +func VFMADD213SS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213SS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMADD213SS_RN_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD213SS.RN_SAE.Z xmm xmm k xmm +func VFMADD213SS_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213SS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMADD213SS_RU_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD213SS.RU_SAE xmm xmm k xmm +// VFMADD213SS.RU_SAE xmm xmm xmm +func VFMADD213SS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213SS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMADD213SS_RU_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD213SS.RU_SAE.Z xmm xmm k xmm +func VFMADD213SS_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213SS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMADD213SS_RZ_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD213SS.RZ_SAE xmm xmm k xmm +// VFMADD213SS.RZ_SAE xmm xmm xmm +func VFMADD213SS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213SS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMADD213SS_RZ_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD213SS.RZ_SAE.Z xmm xmm k xmm +func VFMADD213SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213SS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMADD213SS_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD213SS.Z m32 xmm k xmm +// VFMADD213SS.Z xmm xmm k xmm +func VFMADD213SS_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD213SS.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VFMADD231PD: Fused Multiply-Add of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD231PD m128 xmm xmm +// VFMADD231PD m256 ymm ymm +// VFMADD231PD xmm xmm xmm +// VFMADD231PD ymm ymm ymm +// VFMADD231PD m128 xmm k xmm +// VFMADD231PD m256 ymm k ymm +// VFMADD231PD xmm xmm k xmm +// VFMADD231PD ymm ymm k ymm +// VFMADD231PD m512 zmm k zmm +// VFMADD231PD m512 zmm zmm +// VFMADD231PD zmm zmm k zmm +// VFMADD231PD zmm zmm zmm +func VFMADD231PD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231PD.Forms(), sffxs{}, ops) +} + +// VFMADD231PD_BCST: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADD231PD.BCST m64 xmm k xmm +// VFMADD231PD.BCST m64 xmm xmm +// VFMADD231PD.BCST m64 ymm k ymm +// VFMADD231PD.BCST m64 ymm ymm +// VFMADD231PD.BCST m64 zmm k zmm +// VFMADD231PD.BCST m64 zmm zmm +func VFMADD231PD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231PD.Forms(), sffxs{sffxBCST}, ops) +} + +// VFMADD231PD_BCST_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADD231PD.BCST.Z m64 xmm k xmm +// VFMADD231PD.BCST.Z m64 ymm k ymm +// VFMADD231PD.BCST.Z m64 zmm k zmm +func VFMADD231PD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231PD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFMADD231PD_RD_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD231PD.RD_SAE zmm zmm k zmm +// VFMADD231PD.RD_SAE zmm zmm zmm +func VFMADD231PD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231PD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMADD231PD_RD_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD231PD.RD_SAE.Z zmm zmm k zmm +func VFMADD231PD_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231PD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADD231PD_RN_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD231PD.RN_SAE zmm zmm k zmm +// VFMADD231PD.RN_SAE zmm zmm zmm +func VFMADD231PD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231PD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMADD231PD_RN_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD231PD.RN_SAE.Z zmm zmm k zmm +func VFMADD231PD_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231PD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADD231PD_RU_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD231PD.RU_SAE zmm zmm k zmm +// VFMADD231PD.RU_SAE zmm zmm zmm +func VFMADD231PD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231PD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMADD231PD_RU_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD231PD.RU_SAE.Z zmm zmm k zmm +func VFMADD231PD_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231PD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADD231PD_RZ_SAE: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD231PD.RZ_SAE zmm zmm k zmm +// VFMADD231PD.RZ_SAE zmm zmm zmm +func VFMADD231PD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231PD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMADD231PD_RZ_SAE_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD231PD.RZ_SAE.Z zmm zmm k zmm +func VFMADD231PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231PD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADD231PD_Z: Fused Multiply-Add of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD231PD.Z m128 xmm k xmm +// VFMADD231PD.Z m256 ymm k ymm +// VFMADD231PD.Z xmm xmm k xmm +// VFMADD231PD.Z ymm ymm k ymm +// VFMADD231PD.Z m512 zmm k zmm +// VFMADD231PD.Z zmm zmm k zmm +func VFMADD231PD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231PD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFMADD231PS: Fused Multiply-Add of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD231PS m128 xmm xmm +// VFMADD231PS m256 ymm ymm +// VFMADD231PS xmm xmm xmm +// VFMADD231PS ymm ymm ymm +// VFMADD231PS m128 xmm k xmm +// VFMADD231PS m256 ymm k ymm +// VFMADD231PS xmm xmm k xmm +// VFMADD231PS ymm ymm k ymm +// VFMADD231PS m512 zmm k zmm +// VFMADD231PS m512 zmm zmm +// VFMADD231PS zmm zmm k zmm +// VFMADD231PS zmm zmm zmm +func VFMADD231PS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231PS.Forms(), sffxs{}, ops) +} + +// VFMADD231PS_BCST: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADD231PS.BCST m32 xmm k xmm +// VFMADD231PS.BCST m32 xmm xmm +// VFMADD231PS.BCST m32 ymm k ymm +// VFMADD231PS.BCST m32 ymm ymm +// VFMADD231PS.BCST m32 zmm k zmm +// VFMADD231PS.BCST m32 zmm zmm +func VFMADD231PS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231PS.Forms(), sffxs{sffxBCST}, ops) +} + +// VFMADD231PS_BCST_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADD231PS.BCST.Z m32 xmm k xmm +// VFMADD231PS.BCST.Z m32 ymm k ymm +// VFMADD231PS.BCST.Z m32 zmm k zmm +func VFMADD231PS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231PS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFMADD231PS_RD_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD231PS.RD_SAE zmm zmm k zmm +// VFMADD231PS.RD_SAE zmm zmm zmm +func VFMADD231PS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231PS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMADD231PS_RD_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD231PS.RD_SAE.Z zmm zmm k zmm +func VFMADD231PS_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231PS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADD231PS_RN_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD231PS.RN_SAE zmm zmm k zmm +// VFMADD231PS.RN_SAE zmm zmm zmm +func VFMADD231PS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231PS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMADD231PS_RN_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD231PS.RN_SAE.Z zmm zmm k zmm +func VFMADD231PS_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231PS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADD231PS_RU_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD231PS.RU_SAE zmm zmm k zmm +// VFMADD231PS.RU_SAE zmm zmm zmm +func VFMADD231PS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231PS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMADD231PS_RU_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD231PS.RU_SAE.Z zmm zmm k zmm +func VFMADD231PS_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231PS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADD231PS_RZ_SAE: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD231PS.RZ_SAE zmm zmm k zmm +// VFMADD231PS.RZ_SAE zmm zmm zmm +func VFMADD231PS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231PS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMADD231PS_RZ_SAE_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD231PS.RZ_SAE.Z zmm zmm k zmm +func VFMADD231PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231PS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADD231PS_Z: Fused Multiply-Add of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD231PS.Z m128 xmm k xmm +// VFMADD231PS.Z m256 ymm k ymm +// VFMADD231PS.Z xmm xmm k xmm +// VFMADD231PS.Z ymm ymm k ymm +// VFMADD231PS.Z m512 zmm k zmm +// VFMADD231PS.Z zmm zmm k zmm +func VFMADD231PS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231PS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFMADD231SD: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD231SD m64 xmm xmm +// VFMADD231SD xmm xmm xmm +// VFMADD231SD m64 xmm k xmm +// VFMADD231SD xmm xmm k xmm +func VFMADD231SD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231SD.Forms(), sffxs{}, ops) +} + +// VFMADD231SD_RD_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD231SD.RD_SAE xmm xmm k xmm +// VFMADD231SD.RD_SAE xmm xmm xmm +func VFMADD231SD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231SD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMADD231SD_RD_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD231SD.RD_SAE.Z xmm xmm k xmm +func VFMADD231SD_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231SD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMADD231SD_RN_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD231SD.RN_SAE xmm xmm k xmm +// VFMADD231SD.RN_SAE xmm xmm xmm +func VFMADD231SD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231SD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMADD231SD_RN_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD231SD.RN_SAE.Z xmm xmm k xmm +func VFMADD231SD_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231SD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMADD231SD_RU_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD231SD.RU_SAE xmm xmm k xmm +// VFMADD231SD.RU_SAE xmm xmm xmm +func VFMADD231SD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231SD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMADD231SD_RU_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD231SD.RU_SAE.Z xmm xmm k xmm +func VFMADD231SD_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231SD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMADD231SD_RZ_SAE: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD231SD.RZ_SAE xmm xmm k xmm +// VFMADD231SD.RZ_SAE xmm xmm xmm +func VFMADD231SD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231SD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMADD231SD_RZ_SAE_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD231SD.RZ_SAE.Z xmm xmm k xmm +func VFMADD231SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231SD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMADD231SD_Z: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD231SD.Z m64 xmm k xmm +// VFMADD231SD.Z xmm xmm k xmm +func VFMADD231SD_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231SD.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VFMADD231SS: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMADD231SS m32 xmm xmm +// VFMADD231SS xmm xmm xmm +// VFMADD231SS m32 xmm k xmm +// VFMADD231SS xmm xmm k xmm +func VFMADD231SS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231SS.Forms(), sffxs{}, ops) +} + +// VFMADD231SS_RD_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADD231SS.RD_SAE xmm xmm k xmm +// VFMADD231SS.RD_SAE xmm xmm xmm +func VFMADD231SS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231SS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMADD231SS_RD_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD231SS.RD_SAE.Z xmm xmm k xmm +func VFMADD231SS_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231SS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMADD231SS_RN_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADD231SS.RN_SAE xmm xmm k xmm +// VFMADD231SS.RN_SAE xmm xmm xmm +func VFMADD231SS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231SS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMADD231SS_RN_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADD231SS.RN_SAE.Z xmm xmm k xmm +func VFMADD231SS_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231SS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMADD231SS_RU_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADD231SS.RU_SAE xmm xmm k xmm +// VFMADD231SS.RU_SAE xmm xmm xmm +func VFMADD231SS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231SS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMADD231SS_RU_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADD231SS.RU_SAE.Z xmm xmm k xmm +func VFMADD231SS_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231SS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMADD231SS_RZ_SAE: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADD231SS.RZ_SAE xmm xmm k xmm +// VFMADD231SS.RZ_SAE xmm xmm xmm +func VFMADD231SS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231SS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMADD231SS_RZ_SAE_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADD231SS.RZ_SAE.Z xmm xmm k xmm +func VFMADD231SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231SS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMADD231SS_Z: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADD231SS.Z m32 xmm k xmm +// VFMADD231SS.Z xmm xmm k xmm +func VFMADD231SS_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADD231SS.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VFMADDSUB132PD: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMADDSUB132PD m128 xmm xmm +// VFMADDSUB132PD m256 ymm ymm +// VFMADDSUB132PD xmm xmm xmm +// VFMADDSUB132PD ymm ymm ymm +// VFMADDSUB132PD m128 xmm k xmm +// VFMADDSUB132PD m256 ymm k ymm +// VFMADDSUB132PD xmm xmm k xmm +// VFMADDSUB132PD ymm ymm k ymm +// VFMADDSUB132PD m512 zmm k zmm +// VFMADDSUB132PD m512 zmm zmm +// VFMADDSUB132PD zmm zmm k zmm +// VFMADDSUB132PD zmm zmm zmm +func VFMADDSUB132PD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB132PD.Forms(), sffxs{}, ops) +} + +// VFMADDSUB132PD_BCST: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADDSUB132PD.BCST m64 xmm k xmm +// VFMADDSUB132PD.BCST m64 xmm xmm +// VFMADDSUB132PD.BCST m64 ymm k ymm +// VFMADDSUB132PD.BCST m64 ymm ymm +// VFMADDSUB132PD.BCST m64 zmm k zmm +// VFMADDSUB132PD.BCST m64 zmm zmm +func VFMADDSUB132PD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB132PD.Forms(), sffxs{sffxBCST}, ops) +} + +// VFMADDSUB132PD_BCST_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PD.BCST.Z m64 xmm k xmm +// VFMADDSUB132PD.BCST.Z m64 ymm k ymm +// VFMADDSUB132PD.BCST.Z m64 zmm k zmm +func VFMADDSUB132PD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB132PD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFMADDSUB132PD_RD_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADDSUB132PD.RD_SAE zmm zmm k zmm +// VFMADDSUB132PD.RD_SAE zmm zmm zmm +func VFMADDSUB132PD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB132PD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMADDSUB132PD_RD_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PD.RD_SAE.Z zmm zmm k zmm +func VFMADDSUB132PD_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB132PD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADDSUB132PD_RN_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADDSUB132PD.RN_SAE zmm zmm k zmm +// VFMADDSUB132PD.RN_SAE zmm zmm zmm +func VFMADDSUB132PD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB132PD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMADDSUB132PD_RN_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PD.RN_SAE.Z zmm zmm k zmm +func VFMADDSUB132PD_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB132PD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADDSUB132PD_RU_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADDSUB132PD.RU_SAE zmm zmm k zmm +// VFMADDSUB132PD.RU_SAE zmm zmm zmm +func VFMADDSUB132PD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB132PD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMADDSUB132PD_RU_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PD.RU_SAE.Z zmm zmm k zmm +func VFMADDSUB132PD_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB132PD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADDSUB132PD_RZ_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADDSUB132PD.RZ_SAE zmm zmm k zmm +// VFMADDSUB132PD.RZ_SAE zmm zmm zmm +func VFMADDSUB132PD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB132PD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMADDSUB132PD_RZ_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PD.RZ_SAE.Z zmm zmm k zmm +func VFMADDSUB132PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB132PD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADDSUB132PD_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PD.Z m128 xmm k xmm +// VFMADDSUB132PD.Z m256 ymm k ymm +// VFMADDSUB132PD.Z xmm xmm k xmm +// VFMADDSUB132PD.Z ymm ymm k ymm +// VFMADDSUB132PD.Z m512 zmm k zmm +// VFMADDSUB132PD.Z zmm zmm k zmm +func VFMADDSUB132PD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB132PD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFMADDSUB132PS: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMADDSUB132PS m128 xmm xmm +// VFMADDSUB132PS m256 ymm ymm +// VFMADDSUB132PS xmm xmm xmm +// VFMADDSUB132PS ymm ymm ymm +// VFMADDSUB132PS m128 xmm k xmm +// VFMADDSUB132PS m256 ymm k ymm +// VFMADDSUB132PS xmm xmm k xmm +// VFMADDSUB132PS ymm ymm k ymm +// VFMADDSUB132PS m512 zmm k zmm +// VFMADDSUB132PS m512 zmm zmm +// VFMADDSUB132PS zmm zmm k zmm +// VFMADDSUB132PS zmm zmm zmm +func VFMADDSUB132PS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB132PS.Forms(), sffxs{}, ops) +} + +// VFMADDSUB132PS_BCST: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADDSUB132PS.BCST m32 xmm k xmm +// VFMADDSUB132PS.BCST m32 xmm xmm +// VFMADDSUB132PS.BCST m32 ymm k ymm +// VFMADDSUB132PS.BCST m32 ymm ymm +// VFMADDSUB132PS.BCST m32 zmm k zmm +// VFMADDSUB132PS.BCST m32 zmm zmm +func VFMADDSUB132PS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB132PS.Forms(), sffxs{sffxBCST}, ops) +} + +// VFMADDSUB132PS_BCST_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PS.BCST.Z m32 xmm k xmm +// VFMADDSUB132PS.BCST.Z m32 ymm k ymm +// VFMADDSUB132PS.BCST.Z m32 zmm k zmm +func VFMADDSUB132PS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB132PS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFMADDSUB132PS_RD_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADDSUB132PS.RD_SAE zmm zmm k zmm +// VFMADDSUB132PS.RD_SAE zmm zmm zmm +func VFMADDSUB132PS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB132PS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMADDSUB132PS_RD_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PS.RD_SAE.Z zmm zmm k zmm +func VFMADDSUB132PS_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB132PS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADDSUB132PS_RN_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADDSUB132PS.RN_SAE zmm zmm k zmm +// VFMADDSUB132PS.RN_SAE zmm zmm zmm +func VFMADDSUB132PS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB132PS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMADDSUB132PS_RN_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PS.RN_SAE.Z zmm zmm k zmm +func VFMADDSUB132PS_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB132PS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADDSUB132PS_RU_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADDSUB132PS.RU_SAE zmm zmm k zmm +// VFMADDSUB132PS.RU_SAE zmm zmm zmm +func VFMADDSUB132PS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB132PS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMADDSUB132PS_RU_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PS.RU_SAE.Z zmm zmm k zmm +func VFMADDSUB132PS_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB132PS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADDSUB132PS_RZ_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADDSUB132PS.RZ_SAE zmm zmm k zmm +// VFMADDSUB132PS.RZ_SAE zmm zmm zmm +func VFMADDSUB132PS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB132PS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMADDSUB132PS_RZ_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PS.RZ_SAE.Z zmm zmm k zmm +func VFMADDSUB132PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB132PS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADDSUB132PS_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADDSUB132PS.Z m128 xmm k xmm +// VFMADDSUB132PS.Z m256 ymm k ymm +// VFMADDSUB132PS.Z xmm xmm k xmm +// VFMADDSUB132PS.Z ymm ymm k ymm +// VFMADDSUB132PS.Z m512 zmm k zmm +// VFMADDSUB132PS.Z zmm zmm k zmm +func VFMADDSUB132PS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB132PS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFMADDSUB213PD: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMADDSUB213PD m128 xmm xmm +// VFMADDSUB213PD m256 ymm ymm +// VFMADDSUB213PD xmm xmm xmm +// VFMADDSUB213PD ymm ymm ymm +// VFMADDSUB213PD m128 xmm k xmm +// VFMADDSUB213PD m256 ymm k ymm +// VFMADDSUB213PD xmm xmm k xmm +// VFMADDSUB213PD ymm ymm k ymm +// VFMADDSUB213PD m512 zmm k zmm +// VFMADDSUB213PD m512 zmm zmm +// VFMADDSUB213PD zmm zmm k zmm +// VFMADDSUB213PD zmm zmm zmm +func VFMADDSUB213PD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB213PD.Forms(), sffxs{}, ops) +} + +// VFMADDSUB213PD_BCST: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADDSUB213PD.BCST m64 xmm k xmm +// VFMADDSUB213PD.BCST m64 xmm xmm +// VFMADDSUB213PD.BCST m64 ymm k ymm +// VFMADDSUB213PD.BCST m64 ymm ymm +// VFMADDSUB213PD.BCST m64 zmm k zmm +// VFMADDSUB213PD.BCST m64 zmm zmm +func VFMADDSUB213PD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB213PD.Forms(), sffxs{sffxBCST}, ops) +} + +// VFMADDSUB213PD_BCST_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PD.BCST.Z m64 xmm k xmm +// VFMADDSUB213PD.BCST.Z m64 ymm k ymm +// VFMADDSUB213PD.BCST.Z m64 zmm k zmm +func VFMADDSUB213PD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB213PD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFMADDSUB213PD_RD_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADDSUB213PD.RD_SAE zmm zmm k zmm +// VFMADDSUB213PD.RD_SAE zmm zmm zmm +func VFMADDSUB213PD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB213PD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMADDSUB213PD_RD_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PD.RD_SAE.Z zmm zmm k zmm +func VFMADDSUB213PD_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB213PD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADDSUB213PD_RN_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADDSUB213PD.RN_SAE zmm zmm k zmm +// VFMADDSUB213PD.RN_SAE zmm zmm zmm +func VFMADDSUB213PD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB213PD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMADDSUB213PD_RN_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PD.RN_SAE.Z zmm zmm k zmm +func VFMADDSUB213PD_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB213PD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADDSUB213PD_RU_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADDSUB213PD.RU_SAE zmm zmm k zmm +// VFMADDSUB213PD.RU_SAE zmm zmm zmm +func VFMADDSUB213PD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB213PD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMADDSUB213PD_RU_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PD.RU_SAE.Z zmm zmm k zmm +func VFMADDSUB213PD_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB213PD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADDSUB213PD_RZ_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADDSUB213PD.RZ_SAE zmm zmm k zmm +// VFMADDSUB213PD.RZ_SAE zmm zmm zmm +func VFMADDSUB213PD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB213PD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMADDSUB213PD_RZ_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PD.RZ_SAE.Z zmm zmm k zmm +func VFMADDSUB213PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB213PD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADDSUB213PD_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PD.Z m128 xmm k xmm +// VFMADDSUB213PD.Z m256 ymm k ymm +// VFMADDSUB213PD.Z xmm xmm k xmm +// VFMADDSUB213PD.Z ymm ymm k ymm +// VFMADDSUB213PD.Z m512 zmm k zmm +// VFMADDSUB213PD.Z zmm zmm k zmm +func VFMADDSUB213PD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB213PD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFMADDSUB213PS: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMADDSUB213PS m128 xmm xmm +// VFMADDSUB213PS m256 ymm ymm +// VFMADDSUB213PS xmm xmm xmm +// VFMADDSUB213PS ymm ymm ymm +// VFMADDSUB213PS m128 xmm k xmm +// VFMADDSUB213PS m256 ymm k ymm +// VFMADDSUB213PS xmm xmm k xmm +// VFMADDSUB213PS ymm ymm k ymm +// VFMADDSUB213PS m512 zmm k zmm +// VFMADDSUB213PS m512 zmm zmm +// VFMADDSUB213PS zmm zmm k zmm +// VFMADDSUB213PS zmm zmm zmm +func VFMADDSUB213PS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB213PS.Forms(), sffxs{}, ops) +} + +// VFMADDSUB213PS_BCST: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADDSUB213PS.BCST m32 xmm k xmm +// VFMADDSUB213PS.BCST m32 xmm xmm +// VFMADDSUB213PS.BCST m32 ymm k ymm +// VFMADDSUB213PS.BCST m32 ymm ymm +// VFMADDSUB213PS.BCST m32 zmm k zmm +// VFMADDSUB213PS.BCST m32 zmm zmm +func VFMADDSUB213PS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB213PS.Forms(), sffxs{sffxBCST}, ops) +} + +// VFMADDSUB213PS_BCST_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PS.BCST.Z m32 xmm k xmm +// VFMADDSUB213PS.BCST.Z m32 ymm k ymm +// VFMADDSUB213PS.BCST.Z m32 zmm k zmm +func VFMADDSUB213PS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB213PS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFMADDSUB213PS_RD_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADDSUB213PS.RD_SAE zmm zmm k zmm +// VFMADDSUB213PS.RD_SAE zmm zmm zmm +func VFMADDSUB213PS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB213PS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMADDSUB213PS_RD_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PS.RD_SAE.Z zmm zmm k zmm +func VFMADDSUB213PS_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB213PS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADDSUB213PS_RN_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADDSUB213PS.RN_SAE zmm zmm k zmm +// VFMADDSUB213PS.RN_SAE zmm zmm zmm +func VFMADDSUB213PS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB213PS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMADDSUB213PS_RN_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PS.RN_SAE.Z zmm zmm k zmm +func VFMADDSUB213PS_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB213PS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADDSUB213PS_RU_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADDSUB213PS.RU_SAE zmm zmm k zmm +// VFMADDSUB213PS.RU_SAE zmm zmm zmm +func VFMADDSUB213PS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB213PS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMADDSUB213PS_RU_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PS.RU_SAE.Z zmm zmm k zmm +func VFMADDSUB213PS_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB213PS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADDSUB213PS_RZ_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADDSUB213PS.RZ_SAE zmm zmm k zmm +// VFMADDSUB213PS.RZ_SAE zmm zmm zmm +func VFMADDSUB213PS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB213PS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMADDSUB213PS_RZ_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PS.RZ_SAE.Z zmm zmm k zmm +func VFMADDSUB213PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB213PS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADDSUB213PS_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADDSUB213PS.Z m128 xmm k xmm +// VFMADDSUB213PS.Z m256 ymm k ymm +// VFMADDSUB213PS.Z xmm xmm k xmm +// VFMADDSUB213PS.Z ymm ymm k ymm +// VFMADDSUB213PS.Z m512 zmm k zmm +// VFMADDSUB213PS.Z zmm zmm k zmm +func VFMADDSUB213PS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB213PS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFMADDSUB231PD: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMADDSUB231PD m128 xmm xmm +// VFMADDSUB231PD m256 ymm ymm +// VFMADDSUB231PD xmm xmm xmm +// VFMADDSUB231PD ymm ymm ymm +// VFMADDSUB231PD m128 xmm k xmm +// VFMADDSUB231PD m256 ymm k ymm +// VFMADDSUB231PD xmm xmm k xmm +// VFMADDSUB231PD ymm ymm k ymm +// VFMADDSUB231PD m512 zmm k zmm +// VFMADDSUB231PD m512 zmm zmm +// VFMADDSUB231PD zmm zmm k zmm +// VFMADDSUB231PD zmm zmm zmm +func VFMADDSUB231PD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB231PD.Forms(), sffxs{}, ops) +} + +// VFMADDSUB231PD_BCST: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADDSUB231PD.BCST m64 xmm k xmm +// VFMADDSUB231PD.BCST m64 xmm xmm +// VFMADDSUB231PD.BCST m64 ymm k ymm +// VFMADDSUB231PD.BCST m64 ymm ymm +// VFMADDSUB231PD.BCST m64 zmm k zmm +// VFMADDSUB231PD.BCST m64 zmm zmm +func VFMADDSUB231PD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB231PD.Forms(), sffxs{sffxBCST}, ops) +} + +// VFMADDSUB231PD_BCST_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PD.BCST.Z m64 xmm k xmm +// VFMADDSUB231PD.BCST.Z m64 ymm k ymm +// VFMADDSUB231PD.BCST.Z m64 zmm k zmm +func VFMADDSUB231PD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB231PD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFMADDSUB231PD_RD_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADDSUB231PD.RD_SAE zmm zmm k zmm +// VFMADDSUB231PD.RD_SAE zmm zmm zmm +func VFMADDSUB231PD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB231PD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMADDSUB231PD_RD_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PD.RD_SAE.Z zmm zmm k zmm +func VFMADDSUB231PD_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB231PD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADDSUB231PD_RN_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADDSUB231PD.RN_SAE zmm zmm k zmm +// VFMADDSUB231PD.RN_SAE zmm zmm zmm +func VFMADDSUB231PD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB231PD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMADDSUB231PD_RN_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PD.RN_SAE.Z zmm zmm k zmm +func VFMADDSUB231PD_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB231PD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADDSUB231PD_RU_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADDSUB231PD.RU_SAE zmm zmm k zmm +// VFMADDSUB231PD.RU_SAE zmm zmm zmm +func VFMADDSUB231PD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB231PD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMADDSUB231PD_RU_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PD.RU_SAE.Z zmm zmm k zmm +func VFMADDSUB231PD_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB231PD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADDSUB231PD_RZ_SAE: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADDSUB231PD.RZ_SAE zmm zmm k zmm +// VFMADDSUB231PD.RZ_SAE zmm zmm zmm +func VFMADDSUB231PD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB231PD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMADDSUB231PD_RZ_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PD.RZ_SAE.Z zmm zmm k zmm +func VFMADDSUB231PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB231PD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADDSUB231PD_Z: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PD.Z m128 xmm k xmm +// VFMADDSUB231PD.Z m256 ymm k ymm +// VFMADDSUB231PD.Z xmm xmm k xmm +// VFMADDSUB231PD.Z ymm ymm k ymm +// VFMADDSUB231PD.Z m512 zmm k zmm +// VFMADDSUB231PD.Z zmm zmm k zmm +func VFMADDSUB231PD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB231PD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFMADDSUB231PS: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMADDSUB231PS m128 xmm xmm +// VFMADDSUB231PS m256 ymm ymm +// VFMADDSUB231PS xmm xmm xmm +// VFMADDSUB231PS ymm ymm ymm +// VFMADDSUB231PS m128 xmm k xmm +// VFMADDSUB231PS m256 ymm k ymm +// VFMADDSUB231PS xmm xmm k xmm +// VFMADDSUB231PS ymm ymm k ymm +// VFMADDSUB231PS m512 zmm k zmm +// VFMADDSUB231PS m512 zmm zmm +// VFMADDSUB231PS zmm zmm k zmm +// VFMADDSUB231PS zmm zmm zmm +func VFMADDSUB231PS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB231PS.Forms(), sffxs{}, ops) +} + +// VFMADDSUB231PS_BCST: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMADDSUB231PS.BCST m32 xmm k xmm +// VFMADDSUB231PS.BCST m32 xmm xmm +// VFMADDSUB231PS.BCST m32 ymm k ymm +// VFMADDSUB231PS.BCST m32 ymm ymm +// VFMADDSUB231PS.BCST m32 zmm k zmm +// VFMADDSUB231PS.BCST m32 zmm zmm +func VFMADDSUB231PS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB231PS.Forms(), sffxs{sffxBCST}, ops) +} + +// VFMADDSUB231PS_BCST_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PS.BCST.Z m32 xmm k xmm +// VFMADDSUB231PS.BCST.Z m32 ymm k ymm +// VFMADDSUB231PS.BCST.Z m32 zmm k zmm +func VFMADDSUB231PS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB231PS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFMADDSUB231PS_RD_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMADDSUB231PS.RD_SAE zmm zmm k zmm +// VFMADDSUB231PS.RD_SAE zmm zmm zmm +func VFMADDSUB231PS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB231PS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMADDSUB231PS_RD_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PS.RD_SAE.Z zmm zmm k zmm +func VFMADDSUB231PS_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB231PS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADDSUB231PS_RN_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMADDSUB231PS.RN_SAE zmm zmm k zmm +// VFMADDSUB231PS.RN_SAE zmm zmm zmm +func VFMADDSUB231PS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB231PS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMADDSUB231PS_RN_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PS.RN_SAE.Z zmm zmm k zmm +func VFMADDSUB231PS_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB231PS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADDSUB231PS_RU_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMADDSUB231PS.RU_SAE zmm zmm k zmm +// VFMADDSUB231PS.RU_SAE zmm zmm zmm +func VFMADDSUB231PS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB231PS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMADDSUB231PS_RU_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PS.RU_SAE.Z zmm zmm k zmm +func VFMADDSUB231PS_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB231PS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADDSUB231PS_RZ_SAE: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMADDSUB231PS.RZ_SAE zmm zmm k zmm +// VFMADDSUB231PS.RZ_SAE zmm zmm zmm +func VFMADDSUB231PS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB231PS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMADDSUB231PS_RZ_SAE_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PS.RZ_SAE.Z zmm zmm k zmm +func VFMADDSUB231PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB231PS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMADDSUB231PS_Z: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMADDSUB231PS.Z m128 xmm k xmm +// VFMADDSUB231PS.Z m256 ymm k ymm +// VFMADDSUB231PS.Z xmm xmm k xmm +// VFMADDSUB231PS.Z ymm ymm k ymm +// VFMADDSUB231PS.Z m512 zmm k zmm +// VFMADDSUB231PS.Z zmm zmm k zmm +func VFMADDSUB231PS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMADDSUB231PS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFMSUB132PD: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB132PD m128 xmm xmm +// VFMSUB132PD m256 ymm ymm +// VFMSUB132PD xmm xmm xmm +// VFMSUB132PD ymm ymm ymm +// VFMSUB132PD m128 xmm k xmm +// VFMSUB132PD m256 ymm k ymm +// VFMSUB132PD xmm xmm k xmm +// VFMSUB132PD ymm ymm k ymm +// VFMSUB132PD m512 zmm k zmm +// VFMSUB132PD m512 zmm zmm +// VFMSUB132PD zmm zmm k zmm +// VFMSUB132PD zmm zmm zmm +func VFMSUB132PD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132PD.Forms(), sffxs{}, ops) +} + +// VFMSUB132PD_BCST: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUB132PD.BCST m64 xmm k xmm +// VFMSUB132PD.BCST m64 xmm xmm +// VFMSUB132PD.BCST m64 ymm k ymm +// VFMSUB132PD.BCST m64 ymm ymm +// VFMSUB132PD.BCST m64 zmm k zmm +// VFMSUB132PD.BCST m64 zmm zmm +func VFMSUB132PD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132PD.Forms(), sffxs{sffxBCST}, ops) +} + +// VFMSUB132PD_BCST_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUB132PD.BCST.Z m64 xmm k xmm +// VFMSUB132PD.BCST.Z m64 ymm k ymm +// VFMSUB132PD.BCST.Z m64 zmm k zmm +func VFMSUB132PD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132PD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFMSUB132PD_RD_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB132PD.RD_SAE zmm zmm k zmm +// VFMSUB132PD.RD_SAE zmm zmm zmm +func VFMSUB132PD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132PD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMSUB132PD_RD_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB132PD.RD_SAE.Z zmm zmm k zmm +func VFMSUB132PD_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132PD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUB132PD_RN_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB132PD.RN_SAE zmm zmm k zmm +// VFMSUB132PD.RN_SAE zmm zmm zmm +func VFMSUB132PD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132PD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMSUB132PD_RN_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB132PD.RN_SAE.Z zmm zmm k zmm +func VFMSUB132PD_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132PD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUB132PD_RU_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB132PD.RU_SAE zmm zmm k zmm +// VFMSUB132PD.RU_SAE zmm zmm zmm +func VFMSUB132PD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132PD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMSUB132PD_RU_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB132PD.RU_SAE.Z zmm zmm k zmm +func VFMSUB132PD_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132PD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUB132PD_RZ_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB132PD.RZ_SAE zmm zmm k zmm +// VFMSUB132PD.RZ_SAE zmm zmm zmm +func VFMSUB132PD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132PD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMSUB132PD_RZ_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB132PD.RZ_SAE.Z zmm zmm k zmm +func VFMSUB132PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132PD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUB132PD_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB132PD.Z m128 xmm k xmm +// VFMSUB132PD.Z m256 ymm k ymm +// VFMSUB132PD.Z xmm xmm k xmm +// VFMSUB132PD.Z ymm ymm k ymm +// VFMSUB132PD.Z m512 zmm k zmm +// VFMSUB132PD.Z zmm zmm k zmm +func VFMSUB132PD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132PD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFMSUB132PS: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB132PS m128 xmm xmm +// VFMSUB132PS m256 ymm ymm +// VFMSUB132PS xmm xmm xmm +// VFMSUB132PS ymm ymm ymm +// VFMSUB132PS m128 xmm k xmm +// VFMSUB132PS m256 ymm k ymm +// VFMSUB132PS xmm xmm k xmm +// VFMSUB132PS ymm ymm k ymm +// VFMSUB132PS m512 zmm k zmm +// VFMSUB132PS m512 zmm zmm +// VFMSUB132PS zmm zmm k zmm +// VFMSUB132PS zmm zmm zmm +func VFMSUB132PS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132PS.Forms(), sffxs{}, ops) +} + +// VFMSUB132PS_BCST: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUB132PS.BCST m32 xmm k xmm +// VFMSUB132PS.BCST m32 xmm xmm +// VFMSUB132PS.BCST m32 ymm k ymm +// VFMSUB132PS.BCST m32 ymm ymm +// VFMSUB132PS.BCST m32 zmm k zmm +// VFMSUB132PS.BCST m32 zmm zmm +func VFMSUB132PS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132PS.Forms(), sffxs{sffxBCST}, ops) +} + +// VFMSUB132PS_BCST_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUB132PS.BCST.Z m32 xmm k xmm +// VFMSUB132PS.BCST.Z m32 ymm k ymm +// VFMSUB132PS.BCST.Z m32 zmm k zmm +func VFMSUB132PS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132PS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFMSUB132PS_RD_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB132PS.RD_SAE zmm zmm k zmm +// VFMSUB132PS.RD_SAE zmm zmm zmm +func VFMSUB132PS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132PS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMSUB132PS_RD_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB132PS.RD_SAE.Z zmm zmm k zmm +func VFMSUB132PS_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132PS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUB132PS_RN_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB132PS.RN_SAE zmm zmm k zmm +// VFMSUB132PS.RN_SAE zmm zmm zmm +func VFMSUB132PS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132PS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMSUB132PS_RN_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB132PS.RN_SAE.Z zmm zmm k zmm +func VFMSUB132PS_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132PS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUB132PS_RU_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB132PS.RU_SAE zmm zmm k zmm +// VFMSUB132PS.RU_SAE zmm zmm zmm +func VFMSUB132PS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132PS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMSUB132PS_RU_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB132PS.RU_SAE.Z zmm zmm k zmm +func VFMSUB132PS_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132PS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUB132PS_RZ_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB132PS.RZ_SAE zmm zmm k zmm +// VFMSUB132PS.RZ_SAE zmm zmm zmm +func VFMSUB132PS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132PS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMSUB132PS_RZ_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB132PS.RZ_SAE.Z zmm zmm k zmm +func VFMSUB132PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132PS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUB132PS_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB132PS.Z m128 xmm k xmm +// VFMSUB132PS.Z m256 ymm k ymm +// VFMSUB132PS.Z xmm xmm k xmm +// VFMSUB132PS.Z ymm ymm k ymm +// VFMSUB132PS.Z m512 zmm k zmm +// VFMSUB132PS.Z zmm zmm k zmm +func VFMSUB132PS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132PS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFMSUB132SD: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB132SD m64 xmm xmm +// VFMSUB132SD xmm xmm xmm +// VFMSUB132SD m64 xmm k xmm +// VFMSUB132SD xmm xmm k xmm +func VFMSUB132SD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132SD.Forms(), sffxs{}, ops) +} + +// VFMSUB132SD_RD_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB132SD.RD_SAE xmm xmm k xmm +// VFMSUB132SD.RD_SAE xmm xmm xmm +func VFMSUB132SD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132SD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMSUB132SD_RD_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB132SD.RD_SAE.Z xmm xmm k xmm +func VFMSUB132SD_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132SD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMSUB132SD_RN_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB132SD.RN_SAE xmm xmm k xmm +// VFMSUB132SD.RN_SAE xmm xmm xmm +func VFMSUB132SD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132SD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMSUB132SD_RN_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB132SD.RN_SAE.Z xmm xmm k xmm +func VFMSUB132SD_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132SD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMSUB132SD_RU_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB132SD.RU_SAE xmm xmm k xmm +// VFMSUB132SD.RU_SAE xmm xmm xmm +func VFMSUB132SD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132SD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMSUB132SD_RU_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB132SD.RU_SAE.Z xmm xmm k xmm +func VFMSUB132SD_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132SD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMSUB132SD_RZ_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB132SD.RZ_SAE xmm xmm k xmm +// VFMSUB132SD.RZ_SAE xmm xmm xmm +func VFMSUB132SD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132SD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMSUB132SD_RZ_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB132SD.RZ_SAE.Z xmm xmm k xmm +func VFMSUB132SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132SD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMSUB132SD_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB132SD.Z m64 xmm k xmm +// VFMSUB132SD.Z xmm xmm k xmm +func VFMSUB132SD_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132SD.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VFMSUB132SS: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB132SS m32 xmm xmm +// VFMSUB132SS xmm xmm xmm +// VFMSUB132SS m32 xmm k xmm +// VFMSUB132SS xmm xmm k xmm +func VFMSUB132SS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132SS.Forms(), sffxs{}, ops) +} + +// VFMSUB132SS_RD_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB132SS.RD_SAE xmm xmm k xmm +// VFMSUB132SS.RD_SAE xmm xmm xmm +func VFMSUB132SS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132SS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMSUB132SS_RD_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB132SS.RD_SAE.Z xmm xmm k xmm +func VFMSUB132SS_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132SS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMSUB132SS_RN_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB132SS.RN_SAE xmm xmm k xmm +// VFMSUB132SS.RN_SAE xmm xmm xmm +func VFMSUB132SS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132SS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMSUB132SS_RN_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB132SS.RN_SAE.Z xmm xmm k xmm +func VFMSUB132SS_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132SS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMSUB132SS_RU_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB132SS.RU_SAE xmm xmm k xmm +// VFMSUB132SS.RU_SAE xmm xmm xmm +func VFMSUB132SS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132SS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMSUB132SS_RU_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB132SS.RU_SAE.Z xmm xmm k xmm +func VFMSUB132SS_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132SS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMSUB132SS_RZ_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB132SS.RZ_SAE xmm xmm k xmm +// VFMSUB132SS.RZ_SAE xmm xmm xmm +func VFMSUB132SS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132SS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMSUB132SS_RZ_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB132SS.RZ_SAE.Z xmm xmm k xmm +func VFMSUB132SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132SS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMSUB132SS_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB132SS.Z m32 xmm k xmm +// VFMSUB132SS.Z xmm xmm k xmm +func VFMSUB132SS_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB132SS.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VFMSUB213PD: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB213PD m128 xmm xmm +// VFMSUB213PD m256 ymm ymm +// VFMSUB213PD xmm xmm xmm +// VFMSUB213PD ymm ymm ymm +// VFMSUB213PD m128 xmm k xmm +// VFMSUB213PD m256 ymm k ymm +// VFMSUB213PD xmm xmm k xmm +// VFMSUB213PD ymm ymm k ymm +// VFMSUB213PD m512 zmm k zmm +// VFMSUB213PD m512 zmm zmm +// VFMSUB213PD zmm zmm k zmm +// VFMSUB213PD zmm zmm zmm +func VFMSUB213PD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213PD.Forms(), sffxs{}, ops) +} + +// VFMSUB213PD_BCST: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUB213PD.BCST m64 xmm k xmm +// VFMSUB213PD.BCST m64 xmm xmm +// VFMSUB213PD.BCST m64 ymm k ymm +// VFMSUB213PD.BCST m64 ymm ymm +// VFMSUB213PD.BCST m64 zmm k zmm +// VFMSUB213PD.BCST m64 zmm zmm +func VFMSUB213PD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213PD.Forms(), sffxs{sffxBCST}, ops) +} + +// VFMSUB213PD_BCST_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUB213PD.BCST.Z m64 xmm k xmm +// VFMSUB213PD.BCST.Z m64 ymm k ymm +// VFMSUB213PD.BCST.Z m64 zmm k zmm +func VFMSUB213PD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213PD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFMSUB213PD_RD_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB213PD.RD_SAE zmm zmm k zmm +// VFMSUB213PD.RD_SAE zmm zmm zmm +func VFMSUB213PD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213PD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMSUB213PD_RD_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB213PD.RD_SAE.Z zmm zmm k zmm +func VFMSUB213PD_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213PD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUB213PD_RN_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB213PD.RN_SAE zmm zmm k zmm +// VFMSUB213PD.RN_SAE zmm zmm zmm +func VFMSUB213PD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213PD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMSUB213PD_RN_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB213PD.RN_SAE.Z zmm zmm k zmm +func VFMSUB213PD_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213PD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUB213PD_RU_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB213PD.RU_SAE zmm zmm k zmm +// VFMSUB213PD.RU_SAE zmm zmm zmm +func VFMSUB213PD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213PD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMSUB213PD_RU_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB213PD.RU_SAE.Z zmm zmm k zmm +func VFMSUB213PD_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213PD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUB213PD_RZ_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB213PD.RZ_SAE zmm zmm k zmm +// VFMSUB213PD.RZ_SAE zmm zmm zmm +func VFMSUB213PD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213PD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMSUB213PD_RZ_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB213PD.RZ_SAE.Z zmm zmm k zmm +func VFMSUB213PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213PD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUB213PD_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB213PD.Z m128 xmm k xmm +// VFMSUB213PD.Z m256 ymm k ymm +// VFMSUB213PD.Z xmm xmm k xmm +// VFMSUB213PD.Z ymm ymm k ymm +// VFMSUB213PD.Z m512 zmm k zmm +// VFMSUB213PD.Z zmm zmm k zmm +func VFMSUB213PD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213PD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFMSUB213PS: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB213PS m128 xmm xmm +// VFMSUB213PS m256 ymm ymm +// VFMSUB213PS xmm xmm xmm +// VFMSUB213PS ymm ymm ymm +// VFMSUB213PS m128 xmm k xmm +// VFMSUB213PS m256 ymm k ymm +// VFMSUB213PS xmm xmm k xmm +// VFMSUB213PS ymm ymm k ymm +// VFMSUB213PS m512 zmm k zmm +// VFMSUB213PS m512 zmm zmm +// VFMSUB213PS zmm zmm k zmm +// VFMSUB213PS zmm zmm zmm +func VFMSUB213PS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213PS.Forms(), sffxs{}, ops) +} + +// VFMSUB213PS_BCST: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUB213PS.BCST m32 xmm k xmm +// VFMSUB213PS.BCST m32 xmm xmm +// VFMSUB213PS.BCST m32 ymm k ymm +// VFMSUB213PS.BCST m32 ymm ymm +// VFMSUB213PS.BCST m32 zmm k zmm +// VFMSUB213PS.BCST m32 zmm zmm +func VFMSUB213PS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213PS.Forms(), sffxs{sffxBCST}, ops) +} + +// VFMSUB213PS_BCST_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUB213PS.BCST.Z m32 xmm k xmm +// VFMSUB213PS.BCST.Z m32 ymm k ymm +// VFMSUB213PS.BCST.Z m32 zmm k zmm +func VFMSUB213PS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213PS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFMSUB213PS_RD_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB213PS.RD_SAE zmm zmm k zmm +// VFMSUB213PS.RD_SAE zmm zmm zmm +func VFMSUB213PS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213PS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMSUB213PS_RD_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB213PS.RD_SAE.Z zmm zmm k zmm +func VFMSUB213PS_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213PS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUB213PS_RN_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB213PS.RN_SAE zmm zmm k zmm +// VFMSUB213PS.RN_SAE zmm zmm zmm +func VFMSUB213PS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213PS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMSUB213PS_RN_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB213PS.RN_SAE.Z zmm zmm k zmm +func VFMSUB213PS_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213PS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUB213PS_RU_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB213PS.RU_SAE zmm zmm k zmm +// VFMSUB213PS.RU_SAE zmm zmm zmm +func VFMSUB213PS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213PS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMSUB213PS_RU_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB213PS.RU_SAE.Z zmm zmm k zmm +func VFMSUB213PS_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213PS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUB213PS_RZ_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB213PS.RZ_SAE zmm zmm k zmm +// VFMSUB213PS.RZ_SAE zmm zmm zmm +func VFMSUB213PS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213PS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMSUB213PS_RZ_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB213PS.RZ_SAE.Z zmm zmm k zmm +func VFMSUB213PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213PS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUB213PS_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB213PS.Z m128 xmm k xmm +// VFMSUB213PS.Z m256 ymm k ymm +// VFMSUB213PS.Z xmm xmm k xmm +// VFMSUB213PS.Z ymm ymm k ymm +// VFMSUB213PS.Z m512 zmm k zmm +// VFMSUB213PS.Z zmm zmm k zmm +func VFMSUB213PS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213PS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFMSUB213SD: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB213SD m64 xmm xmm +// VFMSUB213SD xmm xmm xmm +// VFMSUB213SD m64 xmm k xmm +// VFMSUB213SD xmm xmm k xmm +func VFMSUB213SD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213SD.Forms(), sffxs{}, ops) +} + +// VFMSUB213SD_RD_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB213SD.RD_SAE xmm xmm k xmm +// VFMSUB213SD.RD_SAE xmm xmm xmm +func VFMSUB213SD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213SD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMSUB213SD_RD_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB213SD.RD_SAE.Z xmm xmm k xmm +func VFMSUB213SD_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213SD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMSUB213SD_RN_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB213SD.RN_SAE xmm xmm k xmm +// VFMSUB213SD.RN_SAE xmm xmm xmm +func VFMSUB213SD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213SD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMSUB213SD_RN_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB213SD.RN_SAE.Z xmm xmm k xmm +func VFMSUB213SD_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213SD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMSUB213SD_RU_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB213SD.RU_SAE xmm xmm k xmm +// VFMSUB213SD.RU_SAE xmm xmm xmm +func VFMSUB213SD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213SD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMSUB213SD_RU_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB213SD.RU_SAE.Z xmm xmm k xmm +func VFMSUB213SD_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213SD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMSUB213SD_RZ_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB213SD.RZ_SAE xmm xmm k xmm +// VFMSUB213SD.RZ_SAE xmm xmm xmm +func VFMSUB213SD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213SD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMSUB213SD_RZ_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB213SD.RZ_SAE.Z xmm xmm k xmm +func VFMSUB213SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213SD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMSUB213SD_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB213SD.Z m64 xmm k xmm +// VFMSUB213SD.Z xmm xmm k xmm +func VFMSUB213SD_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213SD.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VFMSUB213SS: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB213SS m32 xmm xmm +// VFMSUB213SS xmm xmm xmm +// VFMSUB213SS m32 xmm k xmm +// VFMSUB213SS xmm xmm k xmm +func VFMSUB213SS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213SS.Forms(), sffxs{}, ops) +} + +// VFMSUB213SS_RD_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB213SS.RD_SAE xmm xmm k xmm +// VFMSUB213SS.RD_SAE xmm xmm xmm +func VFMSUB213SS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213SS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMSUB213SS_RD_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB213SS.RD_SAE.Z xmm xmm k xmm +func VFMSUB213SS_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213SS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMSUB213SS_RN_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB213SS.RN_SAE xmm xmm k xmm +// VFMSUB213SS.RN_SAE xmm xmm xmm +func VFMSUB213SS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213SS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMSUB213SS_RN_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB213SS.RN_SAE.Z xmm xmm k xmm +func VFMSUB213SS_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213SS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMSUB213SS_RU_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB213SS.RU_SAE xmm xmm k xmm +// VFMSUB213SS.RU_SAE xmm xmm xmm +func VFMSUB213SS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213SS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMSUB213SS_RU_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB213SS.RU_SAE.Z xmm xmm k xmm +func VFMSUB213SS_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213SS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMSUB213SS_RZ_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB213SS.RZ_SAE xmm xmm k xmm +// VFMSUB213SS.RZ_SAE xmm xmm xmm +func VFMSUB213SS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213SS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMSUB213SS_RZ_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB213SS.RZ_SAE.Z xmm xmm k xmm +func VFMSUB213SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213SS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMSUB213SS_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB213SS.Z m32 xmm k xmm +// VFMSUB213SS.Z xmm xmm k xmm +func VFMSUB213SS_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB213SS.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VFMSUB231PD: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB231PD m128 xmm xmm +// VFMSUB231PD m256 ymm ymm +// VFMSUB231PD xmm xmm xmm +// VFMSUB231PD ymm ymm ymm +// VFMSUB231PD m128 xmm k xmm +// VFMSUB231PD m256 ymm k ymm +// VFMSUB231PD xmm xmm k xmm +// VFMSUB231PD ymm ymm k ymm +// VFMSUB231PD m512 zmm k zmm +// VFMSUB231PD m512 zmm zmm +// VFMSUB231PD zmm zmm k zmm +// VFMSUB231PD zmm zmm zmm +func VFMSUB231PD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231PD.Forms(), sffxs{}, ops) +} + +// VFMSUB231PD_BCST: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUB231PD.BCST m64 xmm k xmm +// VFMSUB231PD.BCST m64 xmm xmm +// VFMSUB231PD.BCST m64 ymm k ymm +// VFMSUB231PD.BCST m64 ymm ymm +// VFMSUB231PD.BCST m64 zmm k zmm +// VFMSUB231PD.BCST m64 zmm zmm +func VFMSUB231PD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231PD.Forms(), sffxs{sffxBCST}, ops) +} + +// VFMSUB231PD_BCST_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUB231PD.BCST.Z m64 xmm k xmm +// VFMSUB231PD.BCST.Z m64 ymm k ymm +// VFMSUB231PD.BCST.Z m64 zmm k zmm +func VFMSUB231PD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231PD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFMSUB231PD_RD_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB231PD.RD_SAE zmm zmm k zmm +// VFMSUB231PD.RD_SAE zmm zmm zmm +func VFMSUB231PD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231PD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMSUB231PD_RD_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB231PD.RD_SAE.Z zmm zmm k zmm +func VFMSUB231PD_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231PD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUB231PD_RN_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB231PD.RN_SAE zmm zmm k zmm +// VFMSUB231PD.RN_SAE zmm zmm zmm +func VFMSUB231PD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231PD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMSUB231PD_RN_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB231PD.RN_SAE.Z zmm zmm k zmm +func VFMSUB231PD_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231PD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUB231PD_RU_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB231PD.RU_SAE zmm zmm k zmm +// VFMSUB231PD.RU_SAE zmm zmm zmm +func VFMSUB231PD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231PD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMSUB231PD_RU_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB231PD.RU_SAE.Z zmm zmm k zmm +func VFMSUB231PD_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231PD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUB231PD_RZ_SAE: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB231PD.RZ_SAE zmm zmm k zmm +// VFMSUB231PD.RZ_SAE zmm zmm zmm +func VFMSUB231PD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231PD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMSUB231PD_RZ_SAE_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB231PD.RZ_SAE.Z zmm zmm k zmm +func VFMSUB231PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231PD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUB231PD_Z: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB231PD.Z m128 xmm k xmm +// VFMSUB231PD.Z m256 ymm k ymm +// VFMSUB231PD.Z xmm xmm k xmm +// VFMSUB231PD.Z ymm ymm k ymm +// VFMSUB231PD.Z m512 zmm k zmm +// VFMSUB231PD.Z zmm zmm k zmm +func VFMSUB231PD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231PD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFMSUB231PS: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB231PS m128 xmm xmm +// VFMSUB231PS m256 ymm ymm +// VFMSUB231PS xmm xmm xmm +// VFMSUB231PS ymm ymm ymm +// VFMSUB231PS m128 xmm k xmm +// VFMSUB231PS m256 ymm k ymm +// VFMSUB231PS xmm xmm k xmm +// VFMSUB231PS ymm ymm k ymm +// VFMSUB231PS m512 zmm k zmm +// VFMSUB231PS m512 zmm zmm +// VFMSUB231PS zmm zmm k zmm +// VFMSUB231PS zmm zmm zmm +func VFMSUB231PS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231PS.Forms(), sffxs{}, ops) +} + +// VFMSUB231PS_BCST: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUB231PS.BCST m32 xmm k xmm +// VFMSUB231PS.BCST m32 xmm xmm +// VFMSUB231PS.BCST m32 ymm k ymm +// VFMSUB231PS.BCST m32 ymm ymm +// VFMSUB231PS.BCST m32 zmm k zmm +// VFMSUB231PS.BCST m32 zmm zmm +func VFMSUB231PS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231PS.Forms(), sffxs{sffxBCST}, ops) +} + +// VFMSUB231PS_BCST_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUB231PS.BCST.Z m32 xmm k xmm +// VFMSUB231PS.BCST.Z m32 ymm k ymm +// VFMSUB231PS.BCST.Z m32 zmm k zmm +func VFMSUB231PS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231PS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFMSUB231PS_RD_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB231PS.RD_SAE zmm zmm k zmm +// VFMSUB231PS.RD_SAE zmm zmm zmm +func VFMSUB231PS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231PS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMSUB231PS_RD_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB231PS.RD_SAE.Z zmm zmm k zmm +func VFMSUB231PS_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231PS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUB231PS_RN_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB231PS.RN_SAE zmm zmm k zmm +// VFMSUB231PS.RN_SAE zmm zmm zmm +func VFMSUB231PS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231PS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMSUB231PS_RN_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB231PS.RN_SAE.Z zmm zmm k zmm +func VFMSUB231PS_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231PS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUB231PS_RU_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB231PS.RU_SAE zmm zmm k zmm +// VFMSUB231PS.RU_SAE zmm zmm zmm +func VFMSUB231PS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231PS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMSUB231PS_RU_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB231PS.RU_SAE.Z zmm zmm k zmm +func VFMSUB231PS_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231PS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUB231PS_RZ_SAE: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB231PS.RZ_SAE zmm zmm k zmm +// VFMSUB231PS.RZ_SAE zmm zmm zmm +func VFMSUB231PS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231PS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMSUB231PS_RZ_SAE_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB231PS.RZ_SAE.Z zmm zmm k zmm +func VFMSUB231PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231PS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUB231PS_Z: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB231PS.Z m128 xmm k xmm +// VFMSUB231PS.Z m256 ymm k ymm +// VFMSUB231PS.Z xmm xmm k xmm +// VFMSUB231PS.Z ymm ymm k ymm +// VFMSUB231PS.Z m512 zmm k zmm +// VFMSUB231PS.Z zmm zmm k zmm +func VFMSUB231PS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231PS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFMSUB231SD: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB231SD m64 xmm xmm +// VFMSUB231SD xmm xmm xmm +// VFMSUB231SD m64 xmm k xmm +// VFMSUB231SD xmm xmm k xmm +func VFMSUB231SD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231SD.Forms(), sffxs{}, ops) +} + +// VFMSUB231SD_RD_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB231SD.RD_SAE xmm xmm k xmm +// VFMSUB231SD.RD_SAE xmm xmm xmm +func VFMSUB231SD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231SD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMSUB231SD_RD_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB231SD.RD_SAE.Z xmm xmm k xmm +func VFMSUB231SD_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231SD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMSUB231SD_RN_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB231SD.RN_SAE xmm xmm k xmm +// VFMSUB231SD.RN_SAE xmm xmm xmm +func VFMSUB231SD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231SD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMSUB231SD_RN_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB231SD.RN_SAE.Z xmm xmm k xmm +func VFMSUB231SD_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231SD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMSUB231SD_RU_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB231SD.RU_SAE xmm xmm k xmm +// VFMSUB231SD.RU_SAE xmm xmm xmm +func VFMSUB231SD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231SD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMSUB231SD_RU_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB231SD.RU_SAE.Z xmm xmm k xmm +func VFMSUB231SD_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231SD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMSUB231SD_RZ_SAE: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB231SD.RZ_SAE xmm xmm k xmm +// VFMSUB231SD.RZ_SAE xmm xmm xmm +func VFMSUB231SD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231SD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMSUB231SD_RZ_SAE_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB231SD.RZ_SAE.Z xmm xmm k xmm +func VFMSUB231SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231SD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMSUB231SD_Z: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB231SD.Z m64 xmm k xmm +// VFMSUB231SD.Z xmm xmm k xmm +func VFMSUB231SD_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231SD.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VFMSUB231SS: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUB231SS m32 xmm xmm +// VFMSUB231SS xmm xmm xmm +// VFMSUB231SS m32 xmm k xmm +// VFMSUB231SS xmm xmm k xmm +func VFMSUB231SS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231SS.Forms(), sffxs{}, ops) +} + +// VFMSUB231SS_RD_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUB231SS.RD_SAE xmm xmm k xmm +// VFMSUB231SS.RD_SAE xmm xmm xmm +func VFMSUB231SS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231SS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMSUB231SS_RD_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB231SS.RD_SAE.Z xmm xmm k xmm +func VFMSUB231SS_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231SS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMSUB231SS_RN_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUB231SS.RN_SAE xmm xmm k xmm +// VFMSUB231SS.RN_SAE xmm xmm xmm +func VFMSUB231SS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231SS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMSUB231SS_RN_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUB231SS.RN_SAE.Z xmm xmm k xmm +func VFMSUB231SS_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231SS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMSUB231SS_RU_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUB231SS.RU_SAE xmm xmm k xmm +// VFMSUB231SS.RU_SAE xmm xmm xmm +func VFMSUB231SS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231SS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMSUB231SS_RU_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUB231SS.RU_SAE.Z xmm xmm k xmm +func VFMSUB231SS_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231SS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMSUB231SS_RZ_SAE: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUB231SS.RZ_SAE xmm xmm k xmm +// VFMSUB231SS.RZ_SAE xmm xmm xmm +func VFMSUB231SS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231SS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMSUB231SS_RZ_SAE_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUB231SS.RZ_SAE.Z xmm xmm k xmm +func VFMSUB231SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231SS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFMSUB231SS_Z: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUB231SS.Z m32 xmm k xmm +// VFMSUB231SS.Z xmm xmm k xmm +func VFMSUB231SS_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUB231SS.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VFMSUBADD132PD: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUBADD132PD m128 xmm xmm +// VFMSUBADD132PD m256 ymm ymm +// VFMSUBADD132PD xmm xmm xmm +// VFMSUBADD132PD ymm ymm ymm +// VFMSUBADD132PD m128 xmm k xmm +// VFMSUBADD132PD m256 ymm k ymm +// VFMSUBADD132PD xmm xmm k xmm +// VFMSUBADD132PD ymm ymm k ymm +// VFMSUBADD132PD m512 zmm k zmm +// VFMSUBADD132PD m512 zmm zmm +// VFMSUBADD132PD zmm zmm k zmm +// VFMSUBADD132PD zmm zmm zmm +func VFMSUBADD132PD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD132PD.Forms(), sffxs{}, ops) +} + +// VFMSUBADD132PD_BCST: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUBADD132PD.BCST m64 xmm k xmm +// VFMSUBADD132PD.BCST m64 xmm xmm +// VFMSUBADD132PD.BCST m64 ymm k ymm +// VFMSUBADD132PD.BCST m64 ymm ymm +// VFMSUBADD132PD.BCST m64 zmm k zmm +// VFMSUBADD132PD.BCST m64 zmm zmm +func VFMSUBADD132PD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD132PD.Forms(), sffxs{sffxBCST}, ops) +} + +// VFMSUBADD132PD_BCST_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PD.BCST.Z m64 xmm k xmm +// VFMSUBADD132PD.BCST.Z m64 ymm k ymm +// VFMSUBADD132PD.BCST.Z m64 zmm k zmm +func VFMSUBADD132PD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD132PD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFMSUBADD132PD_RD_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUBADD132PD.RD_SAE zmm zmm k zmm +// VFMSUBADD132PD.RD_SAE zmm zmm zmm +func VFMSUBADD132PD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD132PD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMSUBADD132PD_RD_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PD.RD_SAE.Z zmm zmm k zmm +func VFMSUBADD132PD_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD132PD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUBADD132PD_RN_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUBADD132PD.RN_SAE zmm zmm k zmm +// VFMSUBADD132PD.RN_SAE zmm zmm zmm +func VFMSUBADD132PD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD132PD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMSUBADD132PD_RN_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PD.RN_SAE.Z zmm zmm k zmm +func VFMSUBADD132PD_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD132PD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUBADD132PD_RU_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUBADD132PD.RU_SAE zmm zmm k zmm +// VFMSUBADD132PD.RU_SAE zmm zmm zmm +func VFMSUBADD132PD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD132PD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMSUBADD132PD_RU_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PD.RU_SAE.Z zmm zmm k zmm +func VFMSUBADD132PD_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD132PD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUBADD132PD_RZ_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUBADD132PD.RZ_SAE zmm zmm k zmm +// VFMSUBADD132PD.RZ_SAE zmm zmm zmm +func VFMSUBADD132PD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD132PD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMSUBADD132PD_RZ_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PD.RZ_SAE.Z zmm zmm k zmm +func VFMSUBADD132PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD132PD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUBADD132PD_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PD.Z m128 xmm k xmm +// VFMSUBADD132PD.Z m256 ymm k ymm +// VFMSUBADD132PD.Z xmm xmm k xmm +// VFMSUBADD132PD.Z ymm ymm k ymm +// VFMSUBADD132PD.Z m512 zmm k zmm +// VFMSUBADD132PD.Z zmm zmm k zmm +func VFMSUBADD132PD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD132PD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFMSUBADD132PS: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUBADD132PS m128 xmm xmm +// VFMSUBADD132PS m256 ymm ymm +// VFMSUBADD132PS xmm xmm xmm +// VFMSUBADD132PS ymm ymm ymm +// VFMSUBADD132PS m128 xmm k xmm +// VFMSUBADD132PS m256 ymm k ymm +// VFMSUBADD132PS xmm xmm k xmm +// VFMSUBADD132PS ymm ymm k ymm +// VFMSUBADD132PS m512 zmm k zmm +// VFMSUBADD132PS m512 zmm zmm +// VFMSUBADD132PS zmm zmm k zmm +// VFMSUBADD132PS zmm zmm zmm +func VFMSUBADD132PS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD132PS.Forms(), sffxs{}, ops) +} + +// VFMSUBADD132PS_BCST: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUBADD132PS.BCST m32 xmm k xmm +// VFMSUBADD132PS.BCST m32 xmm xmm +// VFMSUBADD132PS.BCST m32 ymm k ymm +// VFMSUBADD132PS.BCST m32 ymm ymm +// VFMSUBADD132PS.BCST m32 zmm k zmm +// VFMSUBADD132PS.BCST m32 zmm zmm +func VFMSUBADD132PS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD132PS.Forms(), sffxs{sffxBCST}, ops) +} + +// VFMSUBADD132PS_BCST_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PS.BCST.Z m32 xmm k xmm +// VFMSUBADD132PS.BCST.Z m32 ymm k ymm +// VFMSUBADD132PS.BCST.Z m32 zmm k zmm +func VFMSUBADD132PS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD132PS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFMSUBADD132PS_RD_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUBADD132PS.RD_SAE zmm zmm k zmm +// VFMSUBADD132PS.RD_SAE zmm zmm zmm +func VFMSUBADD132PS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD132PS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMSUBADD132PS_RD_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PS.RD_SAE.Z zmm zmm k zmm +func VFMSUBADD132PS_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD132PS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUBADD132PS_RN_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUBADD132PS.RN_SAE zmm zmm k zmm +// VFMSUBADD132PS.RN_SAE zmm zmm zmm +func VFMSUBADD132PS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD132PS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMSUBADD132PS_RN_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PS.RN_SAE.Z zmm zmm k zmm +func VFMSUBADD132PS_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD132PS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUBADD132PS_RU_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUBADD132PS.RU_SAE zmm zmm k zmm +// VFMSUBADD132PS.RU_SAE zmm zmm zmm +func VFMSUBADD132PS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD132PS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMSUBADD132PS_RU_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PS.RU_SAE.Z zmm zmm k zmm +func VFMSUBADD132PS_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD132PS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUBADD132PS_RZ_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUBADD132PS.RZ_SAE zmm zmm k zmm +// VFMSUBADD132PS.RZ_SAE zmm zmm zmm +func VFMSUBADD132PS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD132PS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMSUBADD132PS_RZ_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PS.RZ_SAE.Z zmm zmm k zmm +func VFMSUBADD132PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD132PS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUBADD132PS_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUBADD132PS.Z m128 xmm k xmm +// VFMSUBADD132PS.Z m256 ymm k ymm +// VFMSUBADD132PS.Z xmm xmm k xmm +// VFMSUBADD132PS.Z ymm ymm k ymm +// VFMSUBADD132PS.Z m512 zmm k zmm +// VFMSUBADD132PS.Z zmm zmm k zmm +func VFMSUBADD132PS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD132PS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFMSUBADD213PD: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUBADD213PD m128 xmm xmm +// VFMSUBADD213PD m256 ymm ymm +// VFMSUBADD213PD xmm xmm xmm +// VFMSUBADD213PD ymm ymm ymm +// VFMSUBADD213PD m128 xmm k xmm +// VFMSUBADD213PD m256 ymm k ymm +// VFMSUBADD213PD xmm xmm k xmm +// VFMSUBADD213PD ymm ymm k ymm +// VFMSUBADD213PD m512 zmm k zmm +// VFMSUBADD213PD m512 zmm zmm +// VFMSUBADD213PD zmm zmm k zmm +// VFMSUBADD213PD zmm zmm zmm +func VFMSUBADD213PD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD213PD.Forms(), sffxs{}, ops) +} + +// VFMSUBADD213PD_BCST: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUBADD213PD.BCST m64 xmm k xmm +// VFMSUBADD213PD.BCST m64 xmm xmm +// VFMSUBADD213PD.BCST m64 ymm k ymm +// VFMSUBADD213PD.BCST m64 ymm ymm +// VFMSUBADD213PD.BCST m64 zmm k zmm +// VFMSUBADD213PD.BCST m64 zmm zmm +func VFMSUBADD213PD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD213PD.Forms(), sffxs{sffxBCST}, ops) +} + +// VFMSUBADD213PD_BCST_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PD.BCST.Z m64 xmm k xmm +// VFMSUBADD213PD.BCST.Z m64 ymm k ymm +// VFMSUBADD213PD.BCST.Z m64 zmm k zmm +func VFMSUBADD213PD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD213PD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFMSUBADD213PD_RD_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUBADD213PD.RD_SAE zmm zmm k zmm +// VFMSUBADD213PD.RD_SAE zmm zmm zmm +func VFMSUBADD213PD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD213PD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMSUBADD213PD_RD_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PD.RD_SAE.Z zmm zmm k zmm +func VFMSUBADD213PD_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD213PD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUBADD213PD_RN_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUBADD213PD.RN_SAE zmm zmm k zmm +// VFMSUBADD213PD.RN_SAE zmm zmm zmm +func VFMSUBADD213PD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD213PD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMSUBADD213PD_RN_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PD.RN_SAE.Z zmm zmm k zmm +func VFMSUBADD213PD_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD213PD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUBADD213PD_RU_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUBADD213PD.RU_SAE zmm zmm k zmm +// VFMSUBADD213PD.RU_SAE zmm zmm zmm +func VFMSUBADD213PD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD213PD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMSUBADD213PD_RU_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PD.RU_SAE.Z zmm zmm k zmm +func VFMSUBADD213PD_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD213PD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUBADD213PD_RZ_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUBADD213PD.RZ_SAE zmm zmm k zmm +// VFMSUBADD213PD.RZ_SAE zmm zmm zmm +func VFMSUBADD213PD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD213PD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMSUBADD213PD_RZ_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PD.RZ_SAE.Z zmm zmm k zmm +func VFMSUBADD213PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD213PD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUBADD213PD_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PD.Z m128 xmm k xmm +// VFMSUBADD213PD.Z m256 ymm k ymm +// VFMSUBADD213PD.Z xmm xmm k xmm +// VFMSUBADD213PD.Z ymm ymm k ymm +// VFMSUBADD213PD.Z m512 zmm k zmm +// VFMSUBADD213PD.Z zmm zmm k zmm +func VFMSUBADD213PD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD213PD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFMSUBADD213PS: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUBADD213PS m128 xmm xmm +// VFMSUBADD213PS m256 ymm ymm +// VFMSUBADD213PS xmm xmm xmm +// VFMSUBADD213PS ymm ymm ymm +// VFMSUBADD213PS m128 xmm k xmm +// VFMSUBADD213PS m256 ymm k ymm +// VFMSUBADD213PS xmm xmm k xmm +// VFMSUBADD213PS ymm ymm k ymm +// VFMSUBADD213PS m512 zmm k zmm +// VFMSUBADD213PS m512 zmm zmm +// VFMSUBADD213PS zmm zmm k zmm +// VFMSUBADD213PS zmm zmm zmm +func VFMSUBADD213PS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD213PS.Forms(), sffxs{}, ops) +} + +// VFMSUBADD213PS_BCST: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUBADD213PS.BCST m32 xmm k xmm +// VFMSUBADD213PS.BCST m32 xmm xmm +// VFMSUBADD213PS.BCST m32 ymm k ymm +// VFMSUBADD213PS.BCST m32 ymm ymm +// VFMSUBADD213PS.BCST m32 zmm k zmm +// VFMSUBADD213PS.BCST m32 zmm zmm +func VFMSUBADD213PS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD213PS.Forms(), sffxs{sffxBCST}, ops) +} + +// VFMSUBADD213PS_BCST_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PS.BCST.Z m32 xmm k xmm +// VFMSUBADD213PS.BCST.Z m32 ymm k ymm +// VFMSUBADD213PS.BCST.Z m32 zmm k zmm +func VFMSUBADD213PS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD213PS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFMSUBADD213PS_RD_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUBADD213PS.RD_SAE zmm zmm k zmm +// VFMSUBADD213PS.RD_SAE zmm zmm zmm +func VFMSUBADD213PS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD213PS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMSUBADD213PS_RD_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PS.RD_SAE.Z zmm zmm k zmm +func VFMSUBADD213PS_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD213PS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUBADD213PS_RN_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUBADD213PS.RN_SAE zmm zmm k zmm +// VFMSUBADD213PS.RN_SAE zmm zmm zmm +func VFMSUBADD213PS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD213PS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMSUBADD213PS_RN_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PS.RN_SAE.Z zmm zmm k zmm +func VFMSUBADD213PS_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD213PS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUBADD213PS_RU_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUBADD213PS.RU_SAE zmm zmm k zmm +// VFMSUBADD213PS.RU_SAE zmm zmm zmm +func VFMSUBADD213PS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD213PS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMSUBADD213PS_RU_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PS.RU_SAE.Z zmm zmm k zmm +func VFMSUBADD213PS_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD213PS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUBADD213PS_RZ_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUBADD213PS.RZ_SAE zmm zmm k zmm +// VFMSUBADD213PS.RZ_SAE zmm zmm zmm +func VFMSUBADD213PS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD213PS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMSUBADD213PS_RZ_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PS.RZ_SAE.Z zmm zmm k zmm +func VFMSUBADD213PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD213PS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUBADD213PS_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUBADD213PS.Z m128 xmm k xmm +// VFMSUBADD213PS.Z m256 ymm k ymm +// VFMSUBADD213PS.Z xmm xmm k xmm +// VFMSUBADD213PS.Z ymm ymm k ymm +// VFMSUBADD213PS.Z m512 zmm k zmm +// VFMSUBADD213PS.Z zmm zmm k zmm +func VFMSUBADD213PS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD213PS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFMSUBADD231PD: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUBADD231PD m128 xmm xmm +// VFMSUBADD231PD m256 ymm ymm +// VFMSUBADD231PD xmm xmm xmm +// VFMSUBADD231PD ymm ymm ymm +// VFMSUBADD231PD m128 xmm k xmm +// VFMSUBADD231PD m256 ymm k ymm +// VFMSUBADD231PD xmm xmm k xmm +// VFMSUBADD231PD ymm ymm k ymm +// VFMSUBADD231PD m512 zmm k zmm +// VFMSUBADD231PD m512 zmm zmm +// VFMSUBADD231PD zmm zmm k zmm +// VFMSUBADD231PD zmm zmm zmm +func VFMSUBADD231PD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD231PD.Forms(), sffxs{}, ops) +} + +// VFMSUBADD231PD_BCST: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUBADD231PD.BCST m64 xmm k xmm +// VFMSUBADD231PD.BCST m64 xmm xmm +// VFMSUBADD231PD.BCST m64 ymm k ymm +// VFMSUBADD231PD.BCST m64 ymm ymm +// VFMSUBADD231PD.BCST m64 zmm k zmm +// VFMSUBADD231PD.BCST m64 zmm zmm +func VFMSUBADD231PD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD231PD.Forms(), sffxs{sffxBCST}, ops) +} + +// VFMSUBADD231PD_BCST_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PD.BCST.Z m64 xmm k xmm +// VFMSUBADD231PD.BCST.Z m64 ymm k ymm +// VFMSUBADD231PD.BCST.Z m64 zmm k zmm +func VFMSUBADD231PD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD231PD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFMSUBADD231PD_RD_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUBADD231PD.RD_SAE zmm zmm k zmm +// VFMSUBADD231PD.RD_SAE zmm zmm zmm +func VFMSUBADD231PD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD231PD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMSUBADD231PD_RD_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PD.RD_SAE.Z zmm zmm k zmm +func VFMSUBADD231PD_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD231PD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUBADD231PD_RN_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUBADD231PD.RN_SAE zmm zmm k zmm +// VFMSUBADD231PD.RN_SAE zmm zmm zmm +func VFMSUBADD231PD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD231PD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMSUBADD231PD_RN_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PD.RN_SAE.Z zmm zmm k zmm +func VFMSUBADD231PD_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD231PD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUBADD231PD_RU_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUBADD231PD.RU_SAE zmm zmm k zmm +// VFMSUBADD231PD.RU_SAE zmm zmm zmm +func VFMSUBADD231PD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD231PD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMSUBADD231PD_RU_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PD.RU_SAE.Z zmm zmm k zmm +func VFMSUBADD231PD_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD231PD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUBADD231PD_RZ_SAE: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUBADD231PD.RZ_SAE zmm zmm k zmm +// VFMSUBADD231PD.RZ_SAE zmm zmm zmm +func VFMSUBADD231PD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD231PD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMSUBADD231PD_RZ_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PD.RZ_SAE.Z zmm zmm k zmm +func VFMSUBADD231PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD231PD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUBADD231PD_Z: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PD.Z m128 xmm k xmm +// VFMSUBADD231PD.Z m256 ymm k ymm +// VFMSUBADD231PD.Z xmm xmm k xmm +// VFMSUBADD231PD.Z ymm ymm k ymm +// VFMSUBADD231PD.Z m512 zmm k zmm +// VFMSUBADD231PD.Z zmm zmm k zmm +func VFMSUBADD231PD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD231PD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFMSUBADD231PS: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFMSUBADD231PS m128 xmm xmm +// VFMSUBADD231PS m256 ymm ymm +// VFMSUBADD231PS xmm xmm xmm +// VFMSUBADD231PS ymm ymm ymm +// VFMSUBADD231PS m128 xmm k xmm +// VFMSUBADD231PS m256 ymm k ymm +// VFMSUBADD231PS xmm xmm k xmm +// VFMSUBADD231PS ymm ymm k ymm +// VFMSUBADD231PS m512 zmm k zmm +// VFMSUBADD231PS m512 zmm zmm +// VFMSUBADD231PS zmm zmm k zmm +// VFMSUBADD231PS zmm zmm zmm +func VFMSUBADD231PS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD231PS.Forms(), sffxs{}, ops) +} + +// VFMSUBADD231PS_BCST: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFMSUBADD231PS.BCST m32 xmm k xmm +// VFMSUBADD231PS.BCST m32 xmm xmm +// VFMSUBADD231PS.BCST m32 ymm k ymm +// VFMSUBADD231PS.BCST m32 ymm ymm +// VFMSUBADD231PS.BCST m32 zmm k zmm +// VFMSUBADD231PS.BCST m32 zmm zmm +func VFMSUBADD231PS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD231PS.Forms(), sffxs{sffxBCST}, ops) +} + +// VFMSUBADD231PS_BCST_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PS.BCST.Z m32 xmm k xmm +// VFMSUBADD231PS.BCST.Z m32 ymm k ymm +// VFMSUBADD231PS.BCST.Z m32 zmm k zmm +func VFMSUBADD231PS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD231PS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFMSUBADD231PS_RD_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFMSUBADD231PS.RD_SAE zmm zmm k zmm +// VFMSUBADD231PS.RD_SAE zmm zmm zmm +func VFMSUBADD231PS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD231PS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFMSUBADD231PS_RD_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PS.RD_SAE.Z zmm zmm k zmm +func VFMSUBADD231PS_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD231PS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUBADD231PS_RN_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFMSUBADD231PS.RN_SAE zmm zmm k zmm +// VFMSUBADD231PS.RN_SAE zmm zmm zmm +func VFMSUBADD231PS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD231PS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFMSUBADD231PS_RN_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PS.RN_SAE.Z zmm zmm k zmm +func VFMSUBADD231PS_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD231PS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUBADD231PS_RU_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFMSUBADD231PS.RU_SAE zmm zmm k zmm +// VFMSUBADD231PS.RU_SAE zmm zmm zmm +func VFMSUBADD231PS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD231PS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFMSUBADD231PS_RU_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PS.RU_SAE.Z zmm zmm k zmm +func VFMSUBADD231PS_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD231PS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUBADD231PS_RZ_SAE: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFMSUBADD231PS.RZ_SAE zmm zmm k zmm +// VFMSUBADD231PS.RZ_SAE zmm zmm zmm +func VFMSUBADD231PS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD231PS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFMSUBADD231PS_RZ_SAE_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PS.RZ_SAE.Z zmm zmm k zmm +func VFMSUBADD231PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD231PS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFMSUBADD231PS_Z: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFMSUBADD231PS.Z m128 xmm k xmm +// VFMSUBADD231PS.Z m256 ymm k ymm +// VFMSUBADD231PS.Z xmm xmm k xmm +// VFMSUBADD231PS.Z ymm ymm k ymm +// VFMSUBADD231PS.Z m512 zmm k zmm +// VFMSUBADD231PS.Z zmm zmm k zmm +func VFMSUBADD231PS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFMSUBADD231PS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFNMADD132PD: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD132PD m128 xmm xmm +// VFNMADD132PD m256 ymm ymm +// VFNMADD132PD xmm xmm xmm +// VFNMADD132PD ymm ymm ymm +// VFNMADD132PD m128 xmm k xmm +// VFNMADD132PD m256 ymm k ymm +// VFNMADD132PD xmm xmm k xmm +// VFNMADD132PD ymm ymm k ymm +// VFNMADD132PD m512 zmm k zmm +// VFNMADD132PD m512 zmm zmm +// VFNMADD132PD zmm zmm k zmm +// VFNMADD132PD zmm zmm zmm +func VFNMADD132PD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132PD.Forms(), sffxs{}, ops) +} + +// VFNMADD132PD_BCST: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMADD132PD.BCST m64 xmm k xmm +// VFNMADD132PD.BCST m64 xmm xmm +// VFNMADD132PD.BCST m64 ymm k ymm +// VFNMADD132PD.BCST m64 ymm ymm +// VFNMADD132PD.BCST m64 zmm k zmm +// VFNMADD132PD.BCST m64 zmm zmm +func VFNMADD132PD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132PD.Forms(), sffxs{sffxBCST}, ops) +} + +// VFNMADD132PD_BCST_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMADD132PD.BCST.Z m64 xmm k xmm +// VFNMADD132PD.BCST.Z m64 ymm k ymm +// VFNMADD132PD.BCST.Z m64 zmm k zmm +func VFNMADD132PD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132PD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFNMADD132PD_RD_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD132PD.RD_SAE zmm zmm k zmm +// VFNMADD132PD.RD_SAE zmm zmm zmm +func VFNMADD132PD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132PD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFNMADD132PD_RD_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD132PD.RD_SAE.Z zmm zmm k zmm +func VFNMADD132PD_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132PD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMADD132PD_RN_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD132PD.RN_SAE zmm zmm k zmm +// VFNMADD132PD.RN_SAE zmm zmm zmm +func VFNMADD132PD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132PD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFNMADD132PD_RN_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD132PD.RN_SAE.Z zmm zmm k zmm +func VFNMADD132PD_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132PD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMADD132PD_RU_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD132PD.RU_SAE zmm zmm k zmm +// VFNMADD132PD.RU_SAE zmm zmm zmm +func VFNMADD132PD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132PD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFNMADD132PD_RU_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD132PD.RU_SAE.Z zmm zmm k zmm +func VFNMADD132PD_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132PD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMADD132PD_RZ_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD132PD.RZ_SAE zmm zmm k zmm +// VFNMADD132PD.RZ_SAE zmm zmm zmm +func VFNMADD132PD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132PD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFNMADD132PD_RZ_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD132PD.RZ_SAE.Z zmm zmm k zmm +func VFNMADD132PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132PD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMADD132PD_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD132PD.Z m128 xmm k xmm +// VFNMADD132PD.Z m256 ymm k ymm +// VFNMADD132PD.Z xmm xmm k xmm +// VFNMADD132PD.Z ymm ymm k ymm +// VFNMADD132PD.Z m512 zmm k zmm +// VFNMADD132PD.Z zmm zmm k zmm +func VFNMADD132PD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132PD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFNMADD132PS: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD132PS m128 xmm xmm +// VFNMADD132PS m256 ymm ymm +// VFNMADD132PS xmm xmm xmm +// VFNMADD132PS ymm ymm ymm +// VFNMADD132PS m128 xmm k xmm +// VFNMADD132PS m256 ymm k ymm +// VFNMADD132PS xmm xmm k xmm +// VFNMADD132PS ymm ymm k ymm +// VFNMADD132PS m512 zmm k zmm +// VFNMADD132PS m512 zmm zmm +// VFNMADD132PS zmm zmm k zmm +// VFNMADD132PS zmm zmm zmm +func VFNMADD132PS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132PS.Forms(), sffxs{}, ops) +} + +// VFNMADD132PS_BCST: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMADD132PS.BCST m32 xmm k xmm +// VFNMADD132PS.BCST m32 xmm xmm +// VFNMADD132PS.BCST m32 ymm k ymm +// VFNMADD132PS.BCST m32 ymm ymm +// VFNMADD132PS.BCST m32 zmm k zmm +// VFNMADD132PS.BCST m32 zmm zmm +func VFNMADD132PS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132PS.Forms(), sffxs{sffxBCST}, ops) +} + +// VFNMADD132PS_BCST_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMADD132PS.BCST.Z m32 xmm k xmm +// VFNMADD132PS.BCST.Z m32 ymm k ymm +// VFNMADD132PS.BCST.Z m32 zmm k zmm +func VFNMADD132PS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132PS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFNMADD132PS_RD_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD132PS.RD_SAE zmm zmm k zmm +// VFNMADD132PS.RD_SAE zmm zmm zmm +func VFNMADD132PS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132PS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFNMADD132PS_RD_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD132PS.RD_SAE.Z zmm zmm k zmm +func VFNMADD132PS_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132PS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMADD132PS_RN_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD132PS.RN_SAE zmm zmm k zmm +// VFNMADD132PS.RN_SAE zmm zmm zmm +func VFNMADD132PS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132PS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFNMADD132PS_RN_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD132PS.RN_SAE.Z zmm zmm k zmm +func VFNMADD132PS_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132PS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMADD132PS_RU_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD132PS.RU_SAE zmm zmm k zmm +// VFNMADD132PS.RU_SAE zmm zmm zmm +func VFNMADD132PS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132PS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFNMADD132PS_RU_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD132PS.RU_SAE.Z zmm zmm k zmm +func VFNMADD132PS_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132PS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMADD132PS_RZ_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD132PS.RZ_SAE zmm zmm k zmm +// VFNMADD132PS.RZ_SAE zmm zmm zmm +func VFNMADD132PS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132PS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFNMADD132PS_RZ_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD132PS.RZ_SAE.Z zmm zmm k zmm +func VFNMADD132PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132PS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMADD132PS_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD132PS.Z m128 xmm k xmm +// VFNMADD132PS.Z m256 ymm k ymm +// VFNMADD132PS.Z xmm xmm k xmm +// VFNMADD132PS.Z ymm ymm k ymm +// VFNMADD132PS.Z m512 zmm k zmm +// VFNMADD132PS.Z zmm zmm k zmm +func VFNMADD132PS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132PS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFNMADD132SD: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD132SD m64 xmm xmm +// VFNMADD132SD xmm xmm xmm +// VFNMADD132SD m64 xmm k xmm +// VFNMADD132SD xmm xmm k xmm +func VFNMADD132SD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132SD.Forms(), sffxs{}, ops) +} + +// VFNMADD132SD_RD_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD132SD.RD_SAE xmm xmm k xmm +// VFNMADD132SD.RD_SAE xmm xmm xmm +func VFNMADD132SD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132SD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFNMADD132SD_RD_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD132SD.RD_SAE.Z xmm xmm k xmm +func VFNMADD132SD_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132SD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMADD132SD_RN_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD132SD.RN_SAE xmm xmm k xmm +// VFNMADD132SD.RN_SAE xmm xmm xmm +func VFNMADD132SD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132SD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFNMADD132SD_RN_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD132SD.RN_SAE.Z xmm xmm k xmm +func VFNMADD132SD_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132SD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMADD132SD_RU_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD132SD.RU_SAE xmm xmm k xmm +// VFNMADD132SD.RU_SAE xmm xmm xmm +func VFNMADD132SD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132SD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFNMADD132SD_RU_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD132SD.RU_SAE.Z xmm xmm k xmm +func VFNMADD132SD_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132SD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMADD132SD_RZ_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD132SD.RZ_SAE xmm xmm k xmm +// VFNMADD132SD.RZ_SAE xmm xmm xmm +func VFNMADD132SD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132SD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFNMADD132SD_RZ_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD132SD.RZ_SAE.Z xmm xmm k xmm +func VFNMADD132SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132SD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMADD132SD_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD132SD.Z m64 xmm k xmm +// VFNMADD132SD.Z xmm xmm k xmm +func VFNMADD132SD_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132SD.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VFNMADD132SS: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD132SS m32 xmm xmm +// VFNMADD132SS xmm xmm xmm +// VFNMADD132SS m32 xmm k xmm +// VFNMADD132SS xmm xmm k xmm +func VFNMADD132SS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132SS.Forms(), sffxs{}, ops) +} + +// VFNMADD132SS_RD_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD132SS.RD_SAE xmm xmm k xmm +// VFNMADD132SS.RD_SAE xmm xmm xmm +func VFNMADD132SS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132SS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFNMADD132SS_RD_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD132SS.RD_SAE.Z xmm xmm k xmm +func VFNMADD132SS_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132SS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMADD132SS_RN_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD132SS.RN_SAE xmm xmm k xmm +// VFNMADD132SS.RN_SAE xmm xmm xmm +func VFNMADD132SS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132SS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFNMADD132SS_RN_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD132SS.RN_SAE.Z xmm xmm k xmm +func VFNMADD132SS_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132SS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMADD132SS_RU_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD132SS.RU_SAE xmm xmm k xmm +// VFNMADD132SS.RU_SAE xmm xmm xmm +func VFNMADD132SS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132SS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFNMADD132SS_RU_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD132SS.RU_SAE.Z xmm xmm k xmm +func VFNMADD132SS_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132SS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMADD132SS_RZ_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD132SS.RZ_SAE xmm xmm k xmm +// VFNMADD132SS.RZ_SAE xmm xmm xmm +func VFNMADD132SS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132SS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFNMADD132SS_RZ_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD132SS.RZ_SAE.Z xmm xmm k xmm +func VFNMADD132SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132SS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMADD132SS_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD132SS.Z m32 xmm k xmm +// VFNMADD132SS.Z xmm xmm k xmm +func VFNMADD132SS_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD132SS.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VFNMADD213PD: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD213PD m128 xmm xmm +// VFNMADD213PD m256 ymm ymm +// VFNMADD213PD xmm xmm xmm +// VFNMADD213PD ymm ymm ymm +// VFNMADD213PD m128 xmm k xmm +// VFNMADD213PD m256 ymm k ymm +// VFNMADD213PD xmm xmm k xmm +// VFNMADD213PD ymm ymm k ymm +// VFNMADD213PD m512 zmm k zmm +// VFNMADD213PD m512 zmm zmm +// VFNMADD213PD zmm zmm k zmm +// VFNMADD213PD zmm zmm zmm +func VFNMADD213PD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213PD.Forms(), sffxs{}, ops) +} + +// VFNMADD213PD_BCST: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMADD213PD.BCST m64 xmm k xmm +// VFNMADD213PD.BCST m64 xmm xmm +// VFNMADD213PD.BCST m64 ymm k ymm +// VFNMADD213PD.BCST m64 ymm ymm +// VFNMADD213PD.BCST m64 zmm k zmm +// VFNMADD213PD.BCST m64 zmm zmm +func VFNMADD213PD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213PD.Forms(), sffxs{sffxBCST}, ops) +} + +// VFNMADD213PD_BCST_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMADD213PD.BCST.Z m64 xmm k xmm +// VFNMADD213PD.BCST.Z m64 ymm k ymm +// VFNMADD213PD.BCST.Z m64 zmm k zmm +func VFNMADD213PD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213PD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFNMADD213PD_RD_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD213PD.RD_SAE zmm zmm k zmm +// VFNMADD213PD.RD_SAE zmm zmm zmm +func VFNMADD213PD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213PD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFNMADD213PD_RD_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD213PD.RD_SAE.Z zmm zmm k zmm +func VFNMADD213PD_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213PD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMADD213PD_RN_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD213PD.RN_SAE zmm zmm k zmm +// VFNMADD213PD.RN_SAE zmm zmm zmm +func VFNMADD213PD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213PD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFNMADD213PD_RN_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD213PD.RN_SAE.Z zmm zmm k zmm +func VFNMADD213PD_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213PD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMADD213PD_RU_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD213PD.RU_SAE zmm zmm k zmm +// VFNMADD213PD.RU_SAE zmm zmm zmm +func VFNMADD213PD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213PD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFNMADD213PD_RU_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD213PD.RU_SAE.Z zmm zmm k zmm +func VFNMADD213PD_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213PD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMADD213PD_RZ_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD213PD.RZ_SAE zmm zmm k zmm +// VFNMADD213PD.RZ_SAE zmm zmm zmm +func VFNMADD213PD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213PD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFNMADD213PD_RZ_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD213PD.RZ_SAE.Z zmm zmm k zmm +func VFNMADD213PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213PD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMADD213PD_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD213PD.Z m128 xmm k xmm +// VFNMADD213PD.Z m256 ymm k ymm +// VFNMADD213PD.Z xmm xmm k xmm +// VFNMADD213PD.Z ymm ymm k ymm +// VFNMADD213PD.Z m512 zmm k zmm +// VFNMADD213PD.Z zmm zmm k zmm +func VFNMADD213PD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213PD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFNMADD213PS: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD213PS m128 xmm xmm +// VFNMADD213PS m256 ymm ymm +// VFNMADD213PS xmm xmm xmm +// VFNMADD213PS ymm ymm ymm +// VFNMADD213PS m128 xmm k xmm +// VFNMADD213PS m256 ymm k ymm +// VFNMADD213PS xmm xmm k xmm +// VFNMADD213PS ymm ymm k ymm +// VFNMADD213PS m512 zmm k zmm +// VFNMADD213PS m512 zmm zmm +// VFNMADD213PS zmm zmm k zmm +// VFNMADD213PS zmm zmm zmm +func VFNMADD213PS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213PS.Forms(), sffxs{}, ops) +} + +// VFNMADD213PS_BCST: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMADD213PS.BCST m32 xmm k xmm +// VFNMADD213PS.BCST m32 xmm xmm +// VFNMADD213PS.BCST m32 ymm k ymm +// VFNMADD213PS.BCST m32 ymm ymm +// VFNMADD213PS.BCST m32 zmm k zmm +// VFNMADD213PS.BCST m32 zmm zmm +func VFNMADD213PS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213PS.Forms(), sffxs{sffxBCST}, ops) +} + +// VFNMADD213PS_BCST_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMADD213PS.BCST.Z m32 xmm k xmm +// VFNMADD213PS.BCST.Z m32 ymm k ymm +// VFNMADD213PS.BCST.Z m32 zmm k zmm +func VFNMADD213PS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213PS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFNMADD213PS_RD_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD213PS.RD_SAE zmm zmm k zmm +// VFNMADD213PS.RD_SAE zmm zmm zmm +func VFNMADD213PS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213PS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFNMADD213PS_RD_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD213PS.RD_SAE.Z zmm zmm k zmm +func VFNMADD213PS_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213PS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMADD213PS_RN_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD213PS.RN_SAE zmm zmm k zmm +// VFNMADD213PS.RN_SAE zmm zmm zmm +func VFNMADD213PS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213PS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFNMADD213PS_RN_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD213PS.RN_SAE.Z zmm zmm k zmm +func VFNMADD213PS_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213PS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMADD213PS_RU_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD213PS.RU_SAE zmm zmm k zmm +// VFNMADD213PS.RU_SAE zmm zmm zmm +func VFNMADD213PS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213PS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFNMADD213PS_RU_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD213PS.RU_SAE.Z zmm zmm k zmm +func VFNMADD213PS_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213PS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMADD213PS_RZ_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD213PS.RZ_SAE zmm zmm k zmm +// VFNMADD213PS.RZ_SAE zmm zmm zmm +func VFNMADD213PS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213PS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFNMADD213PS_RZ_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD213PS.RZ_SAE.Z zmm zmm k zmm +func VFNMADD213PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213PS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMADD213PS_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD213PS.Z m128 xmm k xmm +// VFNMADD213PS.Z m256 ymm k ymm +// VFNMADD213PS.Z xmm xmm k xmm +// VFNMADD213PS.Z ymm ymm k ymm +// VFNMADD213PS.Z m512 zmm k zmm +// VFNMADD213PS.Z zmm zmm k zmm +func VFNMADD213PS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213PS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFNMADD213SD: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD213SD m64 xmm xmm +// VFNMADD213SD xmm xmm xmm +// VFNMADD213SD m64 xmm k xmm +// VFNMADD213SD xmm xmm k xmm +func VFNMADD213SD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213SD.Forms(), sffxs{}, ops) +} + +// VFNMADD213SD_RD_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD213SD.RD_SAE xmm xmm k xmm +// VFNMADD213SD.RD_SAE xmm xmm xmm +func VFNMADD213SD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213SD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFNMADD213SD_RD_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD213SD.RD_SAE.Z xmm xmm k xmm +func VFNMADD213SD_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213SD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMADD213SD_RN_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD213SD.RN_SAE xmm xmm k xmm +// VFNMADD213SD.RN_SAE xmm xmm xmm +func VFNMADD213SD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213SD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFNMADD213SD_RN_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD213SD.RN_SAE.Z xmm xmm k xmm +func VFNMADD213SD_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213SD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMADD213SD_RU_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD213SD.RU_SAE xmm xmm k xmm +// VFNMADD213SD.RU_SAE xmm xmm xmm +func VFNMADD213SD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213SD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFNMADD213SD_RU_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD213SD.RU_SAE.Z xmm xmm k xmm +func VFNMADD213SD_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213SD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMADD213SD_RZ_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD213SD.RZ_SAE xmm xmm k xmm +// VFNMADD213SD.RZ_SAE xmm xmm xmm +func VFNMADD213SD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213SD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFNMADD213SD_RZ_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD213SD.RZ_SAE.Z xmm xmm k xmm +func VFNMADD213SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213SD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMADD213SD_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD213SD.Z m64 xmm k xmm +// VFNMADD213SD.Z xmm xmm k xmm +func VFNMADD213SD_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213SD.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VFNMADD213SS: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD213SS m32 xmm xmm +// VFNMADD213SS xmm xmm xmm +// VFNMADD213SS m32 xmm k xmm +// VFNMADD213SS xmm xmm k xmm +func VFNMADD213SS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213SS.Forms(), sffxs{}, ops) +} + +// VFNMADD213SS_RD_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD213SS.RD_SAE xmm xmm k xmm +// VFNMADD213SS.RD_SAE xmm xmm xmm +func VFNMADD213SS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213SS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFNMADD213SS_RD_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD213SS.RD_SAE.Z xmm xmm k xmm +func VFNMADD213SS_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213SS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMADD213SS_RN_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD213SS.RN_SAE xmm xmm k xmm +// VFNMADD213SS.RN_SAE xmm xmm xmm +func VFNMADD213SS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213SS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFNMADD213SS_RN_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD213SS.RN_SAE.Z xmm xmm k xmm +func VFNMADD213SS_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213SS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMADD213SS_RU_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD213SS.RU_SAE xmm xmm k xmm +// VFNMADD213SS.RU_SAE xmm xmm xmm +func VFNMADD213SS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213SS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFNMADD213SS_RU_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD213SS.RU_SAE.Z xmm xmm k xmm +func VFNMADD213SS_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213SS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMADD213SS_RZ_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD213SS.RZ_SAE xmm xmm k xmm +// VFNMADD213SS.RZ_SAE xmm xmm xmm +func VFNMADD213SS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213SS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFNMADD213SS_RZ_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD213SS.RZ_SAE.Z xmm xmm k xmm +func VFNMADD213SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213SS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMADD213SS_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD213SS.Z m32 xmm k xmm +// VFNMADD213SS.Z xmm xmm k xmm +func VFNMADD213SS_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD213SS.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VFNMADD231PD: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD231PD m128 xmm xmm +// VFNMADD231PD m256 ymm ymm +// VFNMADD231PD xmm xmm xmm +// VFNMADD231PD ymm ymm ymm +// VFNMADD231PD m128 xmm k xmm +// VFNMADD231PD m256 ymm k ymm +// VFNMADD231PD xmm xmm k xmm +// VFNMADD231PD ymm ymm k ymm +// VFNMADD231PD m512 zmm k zmm +// VFNMADD231PD m512 zmm zmm +// VFNMADD231PD zmm zmm k zmm +// VFNMADD231PD zmm zmm zmm +func VFNMADD231PD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231PD.Forms(), sffxs{}, ops) +} + +// VFNMADD231PD_BCST: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMADD231PD.BCST m64 xmm k xmm +// VFNMADD231PD.BCST m64 xmm xmm +// VFNMADD231PD.BCST m64 ymm k ymm +// VFNMADD231PD.BCST m64 ymm ymm +// VFNMADD231PD.BCST m64 zmm k zmm +// VFNMADD231PD.BCST m64 zmm zmm +func VFNMADD231PD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231PD.Forms(), sffxs{sffxBCST}, ops) +} + +// VFNMADD231PD_BCST_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMADD231PD.BCST.Z m64 xmm k xmm +// VFNMADD231PD.BCST.Z m64 ymm k ymm +// VFNMADD231PD.BCST.Z m64 zmm k zmm +func VFNMADD231PD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231PD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFNMADD231PD_RD_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD231PD.RD_SAE zmm zmm k zmm +// VFNMADD231PD.RD_SAE zmm zmm zmm +func VFNMADD231PD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231PD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFNMADD231PD_RD_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD231PD.RD_SAE.Z zmm zmm k zmm +func VFNMADD231PD_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231PD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMADD231PD_RN_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD231PD.RN_SAE zmm zmm k zmm +// VFNMADD231PD.RN_SAE zmm zmm zmm +func VFNMADD231PD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231PD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFNMADD231PD_RN_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD231PD.RN_SAE.Z zmm zmm k zmm +func VFNMADD231PD_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231PD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMADD231PD_RU_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD231PD.RU_SAE zmm zmm k zmm +// VFNMADD231PD.RU_SAE zmm zmm zmm +func VFNMADD231PD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231PD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFNMADD231PD_RU_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD231PD.RU_SAE.Z zmm zmm k zmm +func VFNMADD231PD_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231PD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMADD231PD_RZ_SAE: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD231PD.RZ_SAE zmm zmm k zmm +// VFNMADD231PD.RZ_SAE zmm zmm zmm +func VFNMADD231PD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231PD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFNMADD231PD_RZ_SAE_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD231PD.RZ_SAE.Z zmm zmm k zmm +func VFNMADD231PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231PD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMADD231PD_Z: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD231PD.Z m128 xmm k xmm +// VFNMADD231PD.Z m256 ymm k ymm +// VFNMADD231PD.Z xmm xmm k xmm +// VFNMADD231PD.Z ymm ymm k ymm +// VFNMADD231PD.Z m512 zmm k zmm +// VFNMADD231PD.Z zmm zmm k zmm +func VFNMADD231PD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231PD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFNMADD231PS: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD231PS m128 xmm xmm +// VFNMADD231PS m256 ymm ymm +// VFNMADD231PS xmm xmm xmm +// VFNMADD231PS ymm ymm ymm +// VFNMADD231PS m128 xmm k xmm +// VFNMADD231PS m256 ymm k ymm +// VFNMADD231PS xmm xmm k xmm +// VFNMADD231PS ymm ymm k ymm +// VFNMADD231PS m512 zmm k zmm +// VFNMADD231PS m512 zmm zmm +// VFNMADD231PS zmm zmm k zmm +// VFNMADD231PS zmm zmm zmm +func VFNMADD231PS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231PS.Forms(), sffxs{}, ops) +} + +// VFNMADD231PS_BCST: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMADD231PS.BCST m32 xmm k xmm +// VFNMADD231PS.BCST m32 xmm xmm +// VFNMADD231PS.BCST m32 ymm k ymm +// VFNMADD231PS.BCST m32 ymm ymm +// VFNMADD231PS.BCST m32 zmm k zmm +// VFNMADD231PS.BCST m32 zmm zmm +func VFNMADD231PS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231PS.Forms(), sffxs{sffxBCST}, ops) +} + +// VFNMADD231PS_BCST_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMADD231PS.BCST.Z m32 xmm k xmm +// VFNMADD231PS.BCST.Z m32 ymm k ymm +// VFNMADD231PS.BCST.Z m32 zmm k zmm +func VFNMADD231PS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231PS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFNMADD231PS_RD_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD231PS.RD_SAE zmm zmm k zmm +// VFNMADD231PS.RD_SAE zmm zmm zmm +func VFNMADD231PS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231PS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFNMADD231PS_RD_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD231PS.RD_SAE.Z zmm zmm k zmm +func VFNMADD231PS_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231PS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMADD231PS_RN_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD231PS.RN_SAE zmm zmm k zmm +// VFNMADD231PS.RN_SAE zmm zmm zmm +func VFNMADD231PS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231PS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFNMADD231PS_RN_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD231PS.RN_SAE.Z zmm zmm k zmm +func VFNMADD231PS_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231PS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMADD231PS_RU_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD231PS.RU_SAE zmm zmm k zmm +// VFNMADD231PS.RU_SAE zmm zmm zmm +func VFNMADD231PS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231PS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFNMADD231PS_RU_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD231PS.RU_SAE.Z zmm zmm k zmm +func VFNMADD231PS_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231PS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMADD231PS_RZ_SAE: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD231PS.RZ_SAE zmm zmm k zmm +// VFNMADD231PS.RZ_SAE zmm zmm zmm +func VFNMADD231PS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231PS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFNMADD231PS_RZ_SAE_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD231PS.RZ_SAE.Z zmm zmm k zmm +func VFNMADD231PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231PS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMADD231PS_Z: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD231PS.Z m128 xmm k xmm +// VFNMADD231PS.Z m256 ymm k ymm +// VFNMADD231PS.Z xmm xmm k xmm +// VFNMADD231PS.Z ymm ymm k ymm +// VFNMADD231PS.Z m512 zmm k zmm +// VFNMADD231PS.Z zmm zmm k zmm +func VFNMADD231PS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231PS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFNMADD231SD: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD231SD m64 xmm xmm +// VFNMADD231SD xmm xmm xmm +// VFNMADD231SD m64 xmm k xmm +// VFNMADD231SD xmm xmm k xmm +func VFNMADD231SD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231SD.Forms(), sffxs{}, ops) +} + +// VFNMADD231SD_RD_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD231SD.RD_SAE xmm xmm k xmm +// VFNMADD231SD.RD_SAE xmm xmm xmm +func VFNMADD231SD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231SD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFNMADD231SD_RD_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD231SD.RD_SAE.Z xmm xmm k xmm +func VFNMADD231SD_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231SD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMADD231SD_RN_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD231SD.RN_SAE xmm xmm k xmm +// VFNMADD231SD.RN_SAE xmm xmm xmm +func VFNMADD231SD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231SD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFNMADD231SD_RN_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD231SD.RN_SAE.Z xmm xmm k xmm +func VFNMADD231SD_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231SD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMADD231SD_RU_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD231SD.RU_SAE xmm xmm k xmm +// VFNMADD231SD.RU_SAE xmm xmm xmm +func VFNMADD231SD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231SD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFNMADD231SD_RU_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD231SD.RU_SAE.Z xmm xmm k xmm +func VFNMADD231SD_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231SD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMADD231SD_RZ_SAE: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD231SD.RZ_SAE xmm xmm k xmm +// VFNMADD231SD.RZ_SAE xmm xmm xmm +func VFNMADD231SD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231SD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFNMADD231SD_RZ_SAE_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD231SD.RZ_SAE.Z xmm xmm k xmm +func VFNMADD231SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231SD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMADD231SD_Z: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD231SD.Z m64 xmm k xmm +// VFNMADD231SD.Z xmm xmm k xmm +func VFNMADD231SD_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231SD.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VFNMADD231SS: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMADD231SS m32 xmm xmm +// VFNMADD231SS xmm xmm xmm +// VFNMADD231SS m32 xmm k xmm +// VFNMADD231SS xmm xmm k xmm +func VFNMADD231SS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231SS.Forms(), sffxs{}, ops) +} + +// VFNMADD231SS_RD_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMADD231SS.RD_SAE xmm xmm k xmm +// VFNMADD231SS.RD_SAE xmm xmm xmm +func VFNMADD231SS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231SS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFNMADD231SS_RD_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD231SS.RD_SAE.Z xmm xmm k xmm +func VFNMADD231SS_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231SS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMADD231SS_RN_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMADD231SS.RN_SAE xmm xmm k xmm +// VFNMADD231SS.RN_SAE xmm xmm xmm +func VFNMADD231SS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231SS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFNMADD231SS_RN_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMADD231SS.RN_SAE.Z xmm xmm k xmm +func VFNMADD231SS_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231SS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMADD231SS_RU_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMADD231SS.RU_SAE xmm xmm k xmm +// VFNMADD231SS.RU_SAE xmm xmm xmm +func VFNMADD231SS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231SS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFNMADD231SS_RU_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMADD231SS.RU_SAE.Z xmm xmm k xmm +func VFNMADD231SS_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231SS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMADD231SS_RZ_SAE: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMADD231SS.RZ_SAE xmm xmm k xmm +// VFNMADD231SS.RZ_SAE xmm xmm xmm +func VFNMADD231SS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231SS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFNMADD231SS_RZ_SAE_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMADD231SS.RZ_SAE.Z xmm xmm k xmm +func VFNMADD231SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231SS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMADD231SS_Z: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMADD231SS.Z m32 xmm k xmm +// VFNMADD231SS.Z xmm xmm k xmm +func VFNMADD231SS_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMADD231SS.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VFNMSUB132PD: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB132PD m128 xmm xmm +// VFNMSUB132PD m256 ymm ymm +// VFNMSUB132PD xmm xmm xmm +// VFNMSUB132PD ymm ymm ymm +// VFNMSUB132PD m128 xmm k xmm +// VFNMSUB132PD m256 ymm k ymm +// VFNMSUB132PD xmm xmm k xmm +// VFNMSUB132PD ymm ymm k ymm +// VFNMSUB132PD m512 zmm k zmm +// VFNMSUB132PD m512 zmm zmm +// VFNMSUB132PD zmm zmm k zmm +// VFNMSUB132PD zmm zmm zmm +func VFNMSUB132PD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132PD.Forms(), sffxs{}, ops) +} + +// VFNMSUB132PD_BCST: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMSUB132PD.BCST m64 xmm k xmm +// VFNMSUB132PD.BCST m64 xmm xmm +// VFNMSUB132PD.BCST m64 ymm k ymm +// VFNMSUB132PD.BCST m64 ymm ymm +// VFNMSUB132PD.BCST m64 zmm k zmm +// VFNMSUB132PD.BCST m64 zmm zmm +func VFNMSUB132PD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132PD.Forms(), sffxs{sffxBCST}, ops) +} + +// VFNMSUB132PD_BCST_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PD.BCST.Z m64 xmm k xmm +// VFNMSUB132PD.BCST.Z m64 ymm k ymm +// VFNMSUB132PD.BCST.Z m64 zmm k zmm +func VFNMSUB132PD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132PD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFNMSUB132PD_RD_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB132PD.RD_SAE zmm zmm k zmm +// VFNMSUB132PD.RD_SAE zmm zmm zmm +func VFNMSUB132PD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132PD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFNMSUB132PD_RD_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PD.RD_SAE.Z zmm zmm k zmm +func VFNMSUB132PD_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132PD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMSUB132PD_RN_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB132PD.RN_SAE zmm zmm k zmm +// VFNMSUB132PD.RN_SAE zmm zmm zmm +func VFNMSUB132PD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132PD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFNMSUB132PD_RN_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PD.RN_SAE.Z zmm zmm k zmm +func VFNMSUB132PD_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132PD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMSUB132PD_RU_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB132PD.RU_SAE zmm zmm k zmm +// VFNMSUB132PD.RU_SAE zmm zmm zmm +func VFNMSUB132PD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132PD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFNMSUB132PD_RU_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PD.RU_SAE.Z zmm zmm k zmm +func VFNMSUB132PD_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132PD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMSUB132PD_RZ_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB132PD.RZ_SAE zmm zmm k zmm +// VFNMSUB132PD.RZ_SAE zmm zmm zmm +func VFNMSUB132PD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132PD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFNMSUB132PD_RZ_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PD.RZ_SAE.Z zmm zmm k zmm +func VFNMSUB132PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132PD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMSUB132PD_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PD.Z m128 xmm k xmm +// VFNMSUB132PD.Z m256 ymm k ymm +// VFNMSUB132PD.Z xmm xmm k xmm +// VFNMSUB132PD.Z ymm ymm k ymm +// VFNMSUB132PD.Z m512 zmm k zmm +// VFNMSUB132PD.Z zmm zmm k zmm +func VFNMSUB132PD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132PD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFNMSUB132PS: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB132PS m128 xmm xmm +// VFNMSUB132PS m256 ymm ymm +// VFNMSUB132PS xmm xmm xmm +// VFNMSUB132PS ymm ymm ymm +// VFNMSUB132PS m128 xmm k xmm +// VFNMSUB132PS m256 ymm k ymm +// VFNMSUB132PS xmm xmm k xmm +// VFNMSUB132PS ymm ymm k ymm +// VFNMSUB132PS m512 zmm k zmm +// VFNMSUB132PS m512 zmm zmm +// VFNMSUB132PS zmm zmm k zmm +// VFNMSUB132PS zmm zmm zmm +func VFNMSUB132PS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132PS.Forms(), sffxs{}, ops) +} + +// VFNMSUB132PS_BCST: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMSUB132PS.BCST m32 xmm k xmm +// VFNMSUB132PS.BCST m32 xmm xmm +// VFNMSUB132PS.BCST m32 ymm k ymm +// VFNMSUB132PS.BCST m32 ymm ymm +// VFNMSUB132PS.BCST m32 zmm k zmm +// VFNMSUB132PS.BCST m32 zmm zmm +func VFNMSUB132PS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132PS.Forms(), sffxs{sffxBCST}, ops) +} + +// VFNMSUB132PS_BCST_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PS.BCST.Z m32 xmm k xmm +// VFNMSUB132PS.BCST.Z m32 ymm k ymm +// VFNMSUB132PS.BCST.Z m32 zmm k zmm +func VFNMSUB132PS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132PS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFNMSUB132PS_RD_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB132PS.RD_SAE zmm zmm k zmm +// VFNMSUB132PS.RD_SAE zmm zmm zmm +func VFNMSUB132PS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132PS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFNMSUB132PS_RD_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PS.RD_SAE.Z zmm zmm k zmm +func VFNMSUB132PS_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132PS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMSUB132PS_RN_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB132PS.RN_SAE zmm zmm k zmm +// VFNMSUB132PS.RN_SAE zmm zmm zmm +func VFNMSUB132PS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132PS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFNMSUB132PS_RN_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PS.RN_SAE.Z zmm zmm k zmm +func VFNMSUB132PS_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132PS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMSUB132PS_RU_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB132PS.RU_SAE zmm zmm k zmm +// VFNMSUB132PS.RU_SAE zmm zmm zmm +func VFNMSUB132PS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132PS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFNMSUB132PS_RU_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PS.RU_SAE.Z zmm zmm k zmm +func VFNMSUB132PS_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132PS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMSUB132PS_RZ_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB132PS.RZ_SAE zmm zmm k zmm +// VFNMSUB132PS.RZ_SAE zmm zmm zmm +func VFNMSUB132PS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132PS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFNMSUB132PS_RZ_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PS.RZ_SAE.Z zmm zmm k zmm +func VFNMSUB132PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132PS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMSUB132PS_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB132PS.Z m128 xmm k xmm +// VFNMSUB132PS.Z m256 ymm k ymm +// VFNMSUB132PS.Z xmm xmm k xmm +// VFNMSUB132PS.Z ymm ymm k ymm +// VFNMSUB132PS.Z m512 zmm k zmm +// VFNMSUB132PS.Z zmm zmm k zmm +func VFNMSUB132PS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132PS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFNMSUB132SD: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB132SD m64 xmm xmm +// VFNMSUB132SD xmm xmm xmm +// VFNMSUB132SD m64 xmm k xmm +// VFNMSUB132SD xmm xmm k xmm +func VFNMSUB132SD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132SD.Forms(), sffxs{}, ops) +} + +// VFNMSUB132SD_RD_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB132SD.RD_SAE xmm xmm k xmm +// VFNMSUB132SD.RD_SAE xmm xmm xmm +func VFNMSUB132SD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132SD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFNMSUB132SD_RD_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132SD.RD_SAE.Z xmm xmm k xmm +func VFNMSUB132SD_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132SD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMSUB132SD_RN_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB132SD.RN_SAE xmm xmm k xmm +// VFNMSUB132SD.RN_SAE xmm xmm xmm +func VFNMSUB132SD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132SD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFNMSUB132SD_RN_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132SD.RN_SAE.Z xmm xmm k xmm +func VFNMSUB132SD_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132SD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMSUB132SD_RU_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB132SD.RU_SAE xmm xmm k xmm +// VFNMSUB132SD.RU_SAE xmm xmm xmm +func VFNMSUB132SD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132SD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFNMSUB132SD_RU_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132SD.RU_SAE.Z xmm xmm k xmm +func VFNMSUB132SD_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132SD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMSUB132SD_RZ_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB132SD.RZ_SAE xmm xmm k xmm +// VFNMSUB132SD.RZ_SAE xmm xmm xmm +func VFNMSUB132SD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132SD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFNMSUB132SD_RZ_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132SD.RZ_SAE.Z xmm xmm k xmm +func VFNMSUB132SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132SD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMSUB132SD_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB132SD.Z m64 xmm k xmm +// VFNMSUB132SD.Z xmm xmm k xmm +func VFNMSUB132SD_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132SD.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VFNMSUB132SS: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB132SS m32 xmm xmm +// VFNMSUB132SS xmm xmm xmm +// VFNMSUB132SS m32 xmm k xmm +// VFNMSUB132SS xmm xmm k xmm +func VFNMSUB132SS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132SS.Forms(), sffxs{}, ops) +} + +// VFNMSUB132SS_RD_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB132SS.RD_SAE xmm xmm k xmm +// VFNMSUB132SS.RD_SAE xmm xmm xmm +func VFNMSUB132SS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132SS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFNMSUB132SS_RD_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132SS.RD_SAE.Z xmm xmm k xmm +func VFNMSUB132SS_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132SS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMSUB132SS_RN_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB132SS.RN_SAE xmm xmm k xmm +// VFNMSUB132SS.RN_SAE xmm xmm xmm +func VFNMSUB132SS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132SS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFNMSUB132SS_RN_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132SS.RN_SAE.Z xmm xmm k xmm +func VFNMSUB132SS_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132SS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMSUB132SS_RU_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB132SS.RU_SAE xmm xmm k xmm +// VFNMSUB132SS.RU_SAE xmm xmm xmm +func VFNMSUB132SS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132SS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFNMSUB132SS_RU_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132SS.RU_SAE.Z xmm xmm k xmm +func VFNMSUB132SS_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132SS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMSUB132SS_RZ_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB132SS.RZ_SAE xmm xmm k xmm +// VFNMSUB132SS.RZ_SAE xmm xmm xmm +func VFNMSUB132SS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132SS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFNMSUB132SS_RZ_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB132SS.RZ_SAE.Z xmm xmm k xmm +func VFNMSUB132SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132SS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMSUB132SS_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB132SS.Z m32 xmm k xmm +// VFNMSUB132SS.Z xmm xmm k xmm +func VFNMSUB132SS_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB132SS.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VFNMSUB213PD: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB213PD m128 xmm xmm +// VFNMSUB213PD m256 ymm ymm +// VFNMSUB213PD xmm xmm xmm +// VFNMSUB213PD ymm ymm ymm +// VFNMSUB213PD m128 xmm k xmm +// VFNMSUB213PD m256 ymm k ymm +// VFNMSUB213PD xmm xmm k xmm +// VFNMSUB213PD ymm ymm k ymm +// VFNMSUB213PD m512 zmm k zmm +// VFNMSUB213PD m512 zmm zmm +// VFNMSUB213PD zmm zmm k zmm +// VFNMSUB213PD zmm zmm zmm +func VFNMSUB213PD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213PD.Forms(), sffxs{}, ops) +} + +// VFNMSUB213PD_BCST: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMSUB213PD.BCST m64 xmm k xmm +// VFNMSUB213PD.BCST m64 xmm xmm +// VFNMSUB213PD.BCST m64 ymm k ymm +// VFNMSUB213PD.BCST m64 ymm ymm +// VFNMSUB213PD.BCST m64 zmm k zmm +// VFNMSUB213PD.BCST m64 zmm zmm +func VFNMSUB213PD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213PD.Forms(), sffxs{sffxBCST}, ops) +} + +// VFNMSUB213PD_BCST_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PD.BCST.Z m64 xmm k xmm +// VFNMSUB213PD.BCST.Z m64 ymm k ymm +// VFNMSUB213PD.BCST.Z m64 zmm k zmm +func VFNMSUB213PD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213PD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFNMSUB213PD_RD_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB213PD.RD_SAE zmm zmm k zmm +// VFNMSUB213PD.RD_SAE zmm zmm zmm +func VFNMSUB213PD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213PD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFNMSUB213PD_RD_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PD.RD_SAE.Z zmm zmm k zmm +func VFNMSUB213PD_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213PD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMSUB213PD_RN_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB213PD.RN_SAE zmm zmm k zmm +// VFNMSUB213PD.RN_SAE zmm zmm zmm +func VFNMSUB213PD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213PD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFNMSUB213PD_RN_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PD.RN_SAE.Z zmm zmm k zmm +func VFNMSUB213PD_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213PD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMSUB213PD_RU_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB213PD.RU_SAE zmm zmm k zmm +// VFNMSUB213PD.RU_SAE zmm zmm zmm +func VFNMSUB213PD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213PD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFNMSUB213PD_RU_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PD.RU_SAE.Z zmm zmm k zmm +func VFNMSUB213PD_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213PD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMSUB213PD_RZ_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB213PD.RZ_SAE zmm zmm k zmm +// VFNMSUB213PD.RZ_SAE zmm zmm zmm +func VFNMSUB213PD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213PD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFNMSUB213PD_RZ_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PD.RZ_SAE.Z zmm zmm k zmm +func VFNMSUB213PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213PD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMSUB213PD_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PD.Z m128 xmm k xmm +// VFNMSUB213PD.Z m256 ymm k ymm +// VFNMSUB213PD.Z xmm xmm k xmm +// VFNMSUB213PD.Z ymm ymm k ymm +// VFNMSUB213PD.Z m512 zmm k zmm +// VFNMSUB213PD.Z zmm zmm k zmm +func VFNMSUB213PD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213PD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFNMSUB213PS: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB213PS m128 xmm xmm +// VFNMSUB213PS m256 ymm ymm +// VFNMSUB213PS xmm xmm xmm +// VFNMSUB213PS ymm ymm ymm +// VFNMSUB213PS m128 xmm k xmm +// VFNMSUB213PS m256 ymm k ymm +// VFNMSUB213PS xmm xmm k xmm +// VFNMSUB213PS ymm ymm k ymm +// VFNMSUB213PS m512 zmm k zmm +// VFNMSUB213PS m512 zmm zmm +// VFNMSUB213PS zmm zmm k zmm +// VFNMSUB213PS zmm zmm zmm +func VFNMSUB213PS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213PS.Forms(), sffxs{}, ops) +} + +// VFNMSUB213PS_BCST: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMSUB213PS.BCST m32 xmm k xmm +// VFNMSUB213PS.BCST m32 xmm xmm +// VFNMSUB213PS.BCST m32 ymm k ymm +// VFNMSUB213PS.BCST m32 ymm ymm +// VFNMSUB213PS.BCST m32 zmm k zmm +// VFNMSUB213PS.BCST m32 zmm zmm +func VFNMSUB213PS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213PS.Forms(), sffxs{sffxBCST}, ops) +} + +// VFNMSUB213PS_BCST_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PS.BCST.Z m32 xmm k xmm +// VFNMSUB213PS.BCST.Z m32 ymm k ymm +// VFNMSUB213PS.BCST.Z m32 zmm k zmm +func VFNMSUB213PS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213PS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFNMSUB213PS_RD_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB213PS.RD_SAE zmm zmm k zmm +// VFNMSUB213PS.RD_SAE zmm zmm zmm +func VFNMSUB213PS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213PS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFNMSUB213PS_RD_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PS.RD_SAE.Z zmm zmm k zmm +func VFNMSUB213PS_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213PS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMSUB213PS_RN_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB213PS.RN_SAE zmm zmm k zmm +// VFNMSUB213PS.RN_SAE zmm zmm zmm +func VFNMSUB213PS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213PS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFNMSUB213PS_RN_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PS.RN_SAE.Z zmm zmm k zmm +func VFNMSUB213PS_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213PS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMSUB213PS_RU_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB213PS.RU_SAE zmm zmm k zmm +// VFNMSUB213PS.RU_SAE zmm zmm zmm +func VFNMSUB213PS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213PS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFNMSUB213PS_RU_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PS.RU_SAE.Z zmm zmm k zmm +func VFNMSUB213PS_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213PS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMSUB213PS_RZ_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB213PS.RZ_SAE zmm zmm k zmm +// VFNMSUB213PS.RZ_SAE zmm zmm zmm +func VFNMSUB213PS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213PS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFNMSUB213PS_RZ_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PS.RZ_SAE.Z zmm zmm k zmm +func VFNMSUB213PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213PS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMSUB213PS_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB213PS.Z m128 xmm k xmm +// VFNMSUB213PS.Z m256 ymm k ymm +// VFNMSUB213PS.Z xmm xmm k xmm +// VFNMSUB213PS.Z ymm ymm k ymm +// VFNMSUB213PS.Z m512 zmm k zmm +// VFNMSUB213PS.Z zmm zmm k zmm +func VFNMSUB213PS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213PS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFNMSUB213SD: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB213SD m64 xmm xmm +// VFNMSUB213SD xmm xmm xmm +// VFNMSUB213SD m64 xmm k xmm +// VFNMSUB213SD xmm xmm k xmm +func VFNMSUB213SD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213SD.Forms(), sffxs{}, ops) +} + +// VFNMSUB213SD_RD_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB213SD.RD_SAE xmm xmm k xmm +// VFNMSUB213SD.RD_SAE xmm xmm xmm +func VFNMSUB213SD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213SD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFNMSUB213SD_RD_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213SD.RD_SAE.Z xmm xmm k xmm +func VFNMSUB213SD_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213SD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMSUB213SD_RN_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB213SD.RN_SAE xmm xmm k xmm +// VFNMSUB213SD.RN_SAE xmm xmm xmm +func VFNMSUB213SD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213SD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFNMSUB213SD_RN_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213SD.RN_SAE.Z xmm xmm k xmm +func VFNMSUB213SD_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213SD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMSUB213SD_RU_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB213SD.RU_SAE xmm xmm k xmm +// VFNMSUB213SD.RU_SAE xmm xmm xmm +func VFNMSUB213SD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213SD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFNMSUB213SD_RU_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213SD.RU_SAE.Z xmm xmm k xmm +func VFNMSUB213SD_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213SD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMSUB213SD_RZ_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB213SD.RZ_SAE xmm xmm k xmm +// VFNMSUB213SD.RZ_SAE xmm xmm xmm +func VFNMSUB213SD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213SD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFNMSUB213SD_RZ_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213SD.RZ_SAE.Z xmm xmm k xmm +func VFNMSUB213SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213SD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMSUB213SD_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB213SD.Z m64 xmm k xmm +// VFNMSUB213SD.Z xmm xmm k xmm +func VFNMSUB213SD_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213SD.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VFNMSUB213SS: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB213SS m32 xmm xmm +// VFNMSUB213SS xmm xmm xmm +// VFNMSUB213SS m32 xmm k xmm +// VFNMSUB213SS xmm xmm k xmm +func VFNMSUB213SS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213SS.Forms(), sffxs{}, ops) +} + +// VFNMSUB213SS_RD_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB213SS.RD_SAE xmm xmm k xmm +// VFNMSUB213SS.RD_SAE xmm xmm xmm +func VFNMSUB213SS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213SS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFNMSUB213SS_RD_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213SS.RD_SAE.Z xmm xmm k xmm +func VFNMSUB213SS_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213SS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMSUB213SS_RN_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB213SS.RN_SAE xmm xmm k xmm +// VFNMSUB213SS.RN_SAE xmm xmm xmm +func VFNMSUB213SS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213SS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFNMSUB213SS_RN_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213SS.RN_SAE.Z xmm xmm k xmm +func VFNMSUB213SS_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213SS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMSUB213SS_RU_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB213SS.RU_SAE xmm xmm k xmm +// VFNMSUB213SS.RU_SAE xmm xmm xmm +func VFNMSUB213SS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213SS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFNMSUB213SS_RU_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213SS.RU_SAE.Z xmm xmm k xmm +func VFNMSUB213SS_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213SS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMSUB213SS_RZ_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB213SS.RZ_SAE xmm xmm k xmm +// VFNMSUB213SS.RZ_SAE xmm xmm xmm +func VFNMSUB213SS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213SS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFNMSUB213SS_RZ_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB213SS.RZ_SAE.Z xmm xmm k xmm +func VFNMSUB213SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213SS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMSUB213SS_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB213SS.Z m32 xmm k xmm +// VFNMSUB213SS.Z xmm xmm k xmm +func VFNMSUB213SS_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB213SS.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VFNMSUB231PD: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB231PD m128 xmm xmm +// VFNMSUB231PD m256 ymm ymm +// VFNMSUB231PD xmm xmm xmm +// VFNMSUB231PD ymm ymm ymm +// VFNMSUB231PD m128 xmm k xmm +// VFNMSUB231PD m256 ymm k ymm +// VFNMSUB231PD xmm xmm k xmm +// VFNMSUB231PD ymm ymm k ymm +// VFNMSUB231PD m512 zmm k zmm +// VFNMSUB231PD m512 zmm zmm +// VFNMSUB231PD zmm zmm k zmm +// VFNMSUB231PD zmm zmm zmm +func VFNMSUB231PD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231PD.Forms(), sffxs{}, ops) +} + +// VFNMSUB231PD_BCST: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMSUB231PD.BCST m64 xmm k xmm +// VFNMSUB231PD.BCST m64 xmm xmm +// VFNMSUB231PD.BCST m64 ymm k ymm +// VFNMSUB231PD.BCST m64 ymm ymm +// VFNMSUB231PD.BCST m64 zmm k zmm +// VFNMSUB231PD.BCST m64 zmm zmm +func VFNMSUB231PD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231PD.Forms(), sffxs{sffxBCST}, ops) +} + +// VFNMSUB231PD_BCST_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PD.BCST.Z m64 xmm k xmm +// VFNMSUB231PD.BCST.Z m64 ymm k ymm +// VFNMSUB231PD.BCST.Z m64 zmm k zmm +func VFNMSUB231PD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231PD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFNMSUB231PD_RD_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB231PD.RD_SAE zmm zmm k zmm +// VFNMSUB231PD.RD_SAE zmm zmm zmm +func VFNMSUB231PD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231PD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFNMSUB231PD_RD_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PD.RD_SAE.Z zmm zmm k zmm +func VFNMSUB231PD_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231PD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMSUB231PD_RN_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB231PD.RN_SAE zmm zmm k zmm +// VFNMSUB231PD.RN_SAE zmm zmm zmm +func VFNMSUB231PD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231PD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFNMSUB231PD_RN_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PD.RN_SAE.Z zmm zmm k zmm +func VFNMSUB231PD_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231PD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMSUB231PD_RU_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB231PD.RU_SAE zmm zmm k zmm +// VFNMSUB231PD.RU_SAE zmm zmm zmm +func VFNMSUB231PD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231PD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFNMSUB231PD_RU_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PD.RU_SAE.Z zmm zmm k zmm +func VFNMSUB231PD_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231PD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMSUB231PD_RZ_SAE: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB231PD.RZ_SAE zmm zmm k zmm +// VFNMSUB231PD.RZ_SAE zmm zmm zmm +func VFNMSUB231PD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231PD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFNMSUB231PD_RZ_SAE_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PD.RZ_SAE.Z zmm zmm k zmm +func VFNMSUB231PD_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231PD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMSUB231PD_Z: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PD.Z m128 xmm k xmm +// VFNMSUB231PD.Z m256 ymm k ymm +// VFNMSUB231PD.Z xmm xmm k xmm +// VFNMSUB231PD.Z ymm ymm k ymm +// VFNMSUB231PD.Z m512 zmm k zmm +// VFNMSUB231PD.Z zmm zmm k zmm +func VFNMSUB231PD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231PD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFNMSUB231PS: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB231PS m128 xmm xmm +// VFNMSUB231PS m256 ymm ymm +// VFNMSUB231PS xmm xmm xmm +// VFNMSUB231PS ymm ymm ymm +// VFNMSUB231PS m128 xmm k xmm +// VFNMSUB231PS m256 ymm k ymm +// VFNMSUB231PS xmm xmm k xmm +// VFNMSUB231PS ymm ymm k ymm +// VFNMSUB231PS m512 zmm k zmm +// VFNMSUB231PS m512 zmm zmm +// VFNMSUB231PS zmm zmm k zmm +// VFNMSUB231PS zmm zmm zmm +func VFNMSUB231PS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231PS.Forms(), sffxs{}, ops) +} + +// VFNMSUB231PS_BCST: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFNMSUB231PS.BCST m32 xmm k xmm +// VFNMSUB231PS.BCST m32 xmm xmm +// VFNMSUB231PS.BCST m32 ymm k ymm +// VFNMSUB231PS.BCST m32 ymm ymm +// VFNMSUB231PS.BCST m32 zmm k zmm +// VFNMSUB231PS.BCST m32 zmm zmm +func VFNMSUB231PS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231PS.Forms(), sffxs{sffxBCST}, ops) +} + +// VFNMSUB231PS_BCST_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PS.BCST.Z m32 xmm k xmm +// VFNMSUB231PS.BCST.Z m32 ymm k ymm +// VFNMSUB231PS.BCST.Z m32 zmm k zmm +func VFNMSUB231PS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231PS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VFNMSUB231PS_RD_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB231PS.RD_SAE zmm zmm k zmm +// VFNMSUB231PS.RD_SAE zmm zmm zmm +func VFNMSUB231PS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231PS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFNMSUB231PS_RD_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PS.RD_SAE.Z zmm zmm k zmm +func VFNMSUB231PS_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231PS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMSUB231PS_RN_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB231PS.RN_SAE zmm zmm k zmm +// VFNMSUB231PS.RN_SAE zmm zmm zmm +func VFNMSUB231PS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231PS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFNMSUB231PS_RN_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PS.RN_SAE.Z zmm zmm k zmm +func VFNMSUB231PS_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231PS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMSUB231PS_RU_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB231PS.RU_SAE zmm zmm k zmm +// VFNMSUB231PS.RU_SAE zmm zmm zmm +func VFNMSUB231PS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231PS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFNMSUB231PS_RU_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PS.RU_SAE.Z zmm zmm k zmm +func VFNMSUB231PS_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231PS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMSUB231PS_RZ_SAE: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB231PS.RZ_SAE zmm zmm k zmm +// VFNMSUB231PS.RZ_SAE zmm zmm zmm +func VFNMSUB231PS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231PS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFNMSUB231PS_RZ_SAE_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PS.RZ_SAE.Z zmm zmm k zmm +func VFNMSUB231PS_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231PS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VFNMSUB231PS_Z: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB231PS.Z m128 xmm k xmm +// VFNMSUB231PS.Z m256 ymm k ymm +// VFNMSUB231PS.Z xmm xmm k xmm +// VFNMSUB231PS.Z ymm ymm k ymm +// VFNMSUB231PS.Z m512 zmm k zmm +// VFNMSUB231PS.Z zmm zmm k zmm +func VFNMSUB231PS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231PS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VFNMSUB231SD: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB231SD m64 xmm xmm +// VFNMSUB231SD xmm xmm xmm +// VFNMSUB231SD m64 xmm k xmm +// VFNMSUB231SD xmm xmm k xmm +func VFNMSUB231SD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231SD.Forms(), sffxs{}, ops) +} + +// VFNMSUB231SD_RD_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB231SD.RD_SAE xmm xmm k xmm +// VFNMSUB231SD.RD_SAE xmm xmm xmm +func VFNMSUB231SD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231SD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFNMSUB231SD_RD_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231SD.RD_SAE.Z xmm xmm k xmm +func VFNMSUB231SD_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231SD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMSUB231SD_RN_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB231SD.RN_SAE xmm xmm k xmm +// VFNMSUB231SD.RN_SAE xmm xmm xmm +func VFNMSUB231SD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231SD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFNMSUB231SD_RN_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231SD.RN_SAE.Z xmm xmm k xmm +func VFNMSUB231SD_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231SD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMSUB231SD_RU_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB231SD.RU_SAE xmm xmm k xmm +// VFNMSUB231SD.RU_SAE xmm xmm xmm +func VFNMSUB231SD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231SD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFNMSUB231SD_RU_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231SD.RU_SAE.Z xmm xmm k xmm +func VFNMSUB231SD_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231SD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMSUB231SD_RZ_SAE: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB231SD.RZ_SAE xmm xmm k xmm +// VFNMSUB231SD.RZ_SAE xmm xmm xmm +func VFNMSUB231SD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231SD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFNMSUB231SD_RZ_SAE_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231SD.RZ_SAE.Z xmm xmm k xmm +func VFNMSUB231SD_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231SD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMSUB231SD_Z: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB231SD.Z m64 xmm k xmm +// VFNMSUB231SD.Z xmm xmm k xmm +func VFNMSUB231SD_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231SD.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VFNMSUB231SS: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VFNMSUB231SS m32 xmm xmm +// VFNMSUB231SS xmm xmm xmm +// VFNMSUB231SS m32 xmm k xmm +// VFNMSUB231SS xmm xmm k xmm +func VFNMSUB231SS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231SS.Forms(), sffxs{}, ops) +} + +// VFNMSUB231SS_RD_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VFNMSUB231SS.RD_SAE xmm xmm k xmm +// VFNMSUB231SS.RD_SAE xmm xmm xmm +func VFNMSUB231SS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231SS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VFNMSUB231SS_RD_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231SS.RD_SAE.Z xmm xmm k xmm +func VFNMSUB231SS_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231SS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMSUB231SS_RN_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VFNMSUB231SS.RN_SAE xmm xmm k xmm +// VFNMSUB231SS.RN_SAE xmm xmm xmm +func VFNMSUB231SS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231SS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VFNMSUB231SS_RN_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231SS.RN_SAE.Z xmm xmm k xmm +func VFNMSUB231SS_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231SS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMSUB231SS_RU_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VFNMSUB231SS.RU_SAE xmm xmm k xmm +// VFNMSUB231SS.RU_SAE xmm xmm xmm +func VFNMSUB231SS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231SS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VFNMSUB231SS_RU_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231SS.RU_SAE.Z xmm xmm k xmm +func VFNMSUB231SS_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231SS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMSUB231SS_RZ_SAE: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VFNMSUB231SS.RZ_SAE xmm xmm k xmm +// VFNMSUB231SS.RZ_SAE xmm xmm xmm +func VFNMSUB231SS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231SS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VFNMSUB231SS_RZ_SAE_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VFNMSUB231SS.RZ_SAE.Z xmm xmm k xmm +func VFNMSUB231SS_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231SS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VFNMSUB231SS_Z: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VFNMSUB231SS.Z m32 xmm k xmm +// VFNMSUB231SS.Z xmm xmm k xmm +func VFNMSUB231SS_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVFNMSUB231SS.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VFPCLASSPDX: Test Class of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFPCLASSPDX imm8 m128 k k +// VFPCLASSPDX imm8 m128 k +// VFPCLASSPDX imm8 xmm k k +// VFPCLASSPDX imm8 xmm k +func VFPCLASSPDX(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFPCLASSPDX.Forms(), sffxs{}, ops) +} + +// VFPCLASSPDX_BCST: Test Class of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFPCLASSPDX.BCST imm8 m64 k k +// VFPCLASSPDX.BCST imm8 m64 k +func VFPCLASSPDX_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFPCLASSPDX.Forms(), sffxs{sffxBCST}, ops) +} + +// VFPCLASSPDY: Test Class of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFPCLASSPDY imm8 m256 k k +// VFPCLASSPDY imm8 m256 k +// VFPCLASSPDY imm8 ymm k k +// VFPCLASSPDY imm8 ymm k +func VFPCLASSPDY(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFPCLASSPDY.Forms(), sffxs{}, ops) +} + +// VFPCLASSPDY_BCST: Test Class of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFPCLASSPDY.BCST imm8 m64 k k +// VFPCLASSPDY.BCST imm8 m64 k +func VFPCLASSPDY_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFPCLASSPDY.Forms(), sffxs{sffxBCST}, ops) +} + +// VFPCLASSPDZ: Test Class of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VFPCLASSPDZ imm8 m512 k k +// VFPCLASSPDZ imm8 m512 k +// VFPCLASSPDZ imm8 zmm k k +// VFPCLASSPDZ imm8 zmm k +func VFPCLASSPDZ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFPCLASSPDZ.Forms(), sffxs{}, ops) +} + +// VFPCLASSPDZ_BCST: Test Class of Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFPCLASSPDZ.BCST imm8 m64 k k +// VFPCLASSPDZ.BCST imm8 m64 k +func VFPCLASSPDZ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFPCLASSPDZ.Forms(), sffxs{sffxBCST}, ops) +} + +// VFPCLASSPSX: Test Class of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFPCLASSPSX imm8 m128 k k +// VFPCLASSPSX imm8 m128 k +// VFPCLASSPSX imm8 xmm k k +// VFPCLASSPSX imm8 xmm k +func VFPCLASSPSX(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFPCLASSPSX.Forms(), sffxs{}, ops) +} + +// VFPCLASSPSX_BCST: Test Class of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFPCLASSPSX.BCST imm8 m32 k k +// VFPCLASSPSX.BCST imm8 m32 k +func VFPCLASSPSX_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFPCLASSPSX.Forms(), sffxs{sffxBCST}, ops) +} + +// VFPCLASSPSY: Test Class of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFPCLASSPSY imm8 m256 k k +// VFPCLASSPSY imm8 m256 k +// VFPCLASSPSY imm8 ymm k k +// VFPCLASSPSY imm8 ymm k +func VFPCLASSPSY(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFPCLASSPSY.Forms(), sffxs{}, ops) +} + +// VFPCLASSPSY_BCST: Test Class of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFPCLASSPSY.BCST imm8 m32 k k +// VFPCLASSPSY.BCST imm8 m32 k +func VFPCLASSPSY_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFPCLASSPSY.Forms(), sffxs{sffxBCST}, ops) +} + +// VFPCLASSPSZ: Test Class of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VFPCLASSPSZ imm8 m512 k k +// VFPCLASSPSZ imm8 m512 k +// VFPCLASSPSZ imm8 zmm k k +// VFPCLASSPSZ imm8 zmm k +func VFPCLASSPSZ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFPCLASSPSZ.Forms(), sffxs{}, ops) +} + +// VFPCLASSPSZ_BCST: Test Class of Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VFPCLASSPSZ.BCST imm8 m32 k k +// VFPCLASSPSZ.BCST imm8 m32 k +func VFPCLASSPSZ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFPCLASSPSZ.Forms(), sffxs{sffxBCST}, ops) +} + +// VFPCLASSSD: Test Class of Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// VFPCLASSSD imm8 m64 k k +// VFPCLASSSD imm8 m64 k +// VFPCLASSSD imm8 xmm k k +// VFPCLASSSD imm8 xmm k +func VFPCLASSSD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFPCLASSSD.Forms(), sffxs{}, ops) +} + +// VFPCLASSSS: Test Class of Scalar Single-Precision Floating-Point Value. +// +// Forms: +// +// VFPCLASSSS imm8 m32 k k +// VFPCLASSSS imm8 m32 k +// VFPCLASSSS imm8 xmm k k +// VFPCLASSSS imm8 xmm k +func VFPCLASSSS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVFPCLASSSS.Forms(), sffxs{}, ops) +} + +// VGATHERDPD: Gather Packed Double-Precision Floating-Point Values Using Signed Doubleword Indices. +// +// Forms: +// +// VGATHERDPD xmm vm32x xmm +// VGATHERDPD ymm vm32x ymm +// VGATHERDPD vm32x k xmm +// VGATHERDPD vm32x k ymm +// VGATHERDPD vm32y k zmm +func VGATHERDPD(vxy, kv, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVGATHERDPD.Forms(), sffxs{}, []operand.Op{vxy, kv, xyz}) +} + +// VGATHERDPS: Gather Packed Single-Precision Floating-Point Values Using Signed Doubleword Indices. +// +// Forms: +// +// VGATHERDPS xmm vm32x xmm +// VGATHERDPS ymm vm32y ymm +// VGATHERDPS vm32x k xmm +// VGATHERDPS vm32y k ymm +// VGATHERDPS vm32z k zmm +func VGATHERDPS(vxy, kv, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVGATHERDPS.Forms(), sffxs{}, []operand.Op{vxy, kv, xyz}) +} + +// VGATHERQPD: Gather Packed Double-Precision Floating-Point Values Using Signed Quadword Indices. +// +// Forms: +// +// VGATHERQPD xmm vm64x xmm +// VGATHERQPD ymm vm64y ymm +// VGATHERQPD vm64x k xmm +// VGATHERQPD vm64y k ymm +// VGATHERQPD vm64z k zmm +func VGATHERQPD(vxy, kv, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVGATHERQPD.Forms(), sffxs{}, []operand.Op{vxy, kv, xyz}) +} + +// VGATHERQPS: Gather Packed Single-Precision Floating-Point Values Using Signed Quadword Indices. +// +// Forms: +// +// VGATHERQPS xmm vm64x xmm +// VGATHERQPS xmm vm64y xmm +// VGATHERQPS vm64x k xmm +// VGATHERQPS vm64y k xmm +// VGATHERQPS vm64z k ymm +func VGATHERQPS(vx, kv, xy operand.Op) (*intrep.Instruction, error) { + return build(opcVGATHERQPS.Forms(), sffxs{}, []operand.Op{vx, kv, xy}) +} + +// VGETEXPPD: Extract Exponents of Packed Double-Precision Floating-Point Values as Double-Precision Floating-Point Values. +// +// Forms: +// +// VGETEXPPD m128 k xmm +// VGETEXPPD m128 xmm +// VGETEXPPD m256 k ymm +// VGETEXPPD m256 ymm +// VGETEXPPD xmm k xmm +// VGETEXPPD xmm xmm +// VGETEXPPD ymm k ymm +// VGETEXPPD ymm ymm +// VGETEXPPD m512 k zmm +// VGETEXPPD m512 zmm +// VGETEXPPD zmm k zmm +// VGETEXPPD zmm zmm +func VGETEXPPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVGETEXPPD.Forms(), sffxs{}, ops) +} + +// VGETEXPPD_BCST: Extract Exponents of Packed Double-Precision Floating-Point Values as Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VGETEXPPD.BCST m64 k xmm +// VGETEXPPD.BCST m64 k ymm +// VGETEXPPD.BCST m64 xmm +// VGETEXPPD.BCST m64 ymm +// VGETEXPPD.BCST m64 k zmm +// VGETEXPPD.BCST m64 zmm +func VGETEXPPD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVGETEXPPD.Forms(), sffxs{sffxBCST}, ops) +} + +// VGETEXPPD_BCST_Z: Extract Exponents of Packed Double-Precision Floating-Point Values as Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VGETEXPPD.BCST.Z m64 k xmm +// VGETEXPPD.BCST.Z m64 k ymm +// VGETEXPPD.BCST.Z m64 k zmm +func VGETEXPPD_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVGETEXPPD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) +} + +// VGETEXPPD_SAE: Extract Exponents of Packed Double-Precision Floating-Point Values as Double-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VGETEXPPD.SAE zmm k zmm +// VGETEXPPD.SAE zmm zmm +func VGETEXPPD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVGETEXPPD.Forms(), sffxs{sffxSAE}, ops) +} + +// VGETEXPPD_SAE_Z: Extract Exponents of Packed Double-Precision Floating-Point Values as Double-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VGETEXPPD.SAE.Z zmm k zmm +func VGETEXPPD_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVGETEXPPD.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VGETEXPPD_Z: Extract Exponents of Packed Double-Precision Floating-Point Values as Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VGETEXPPD.Z m128 k xmm +// VGETEXPPD.Z m256 k ymm +// VGETEXPPD.Z xmm k xmm +// VGETEXPPD.Z ymm k ymm +// VGETEXPPD.Z m512 k zmm +// VGETEXPPD.Z zmm k zmm +func VGETEXPPD_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVGETEXPPD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) +} + +// VGETEXPPS: Extract Exponents of Packed Single-Precision Floating-Point Values as Single-Precision Floating-Point Values. +// +// Forms: +// +// VGETEXPPS m128 k xmm +// VGETEXPPS m128 xmm +// VGETEXPPS m256 k ymm +// VGETEXPPS m256 ymm +// VGETEXPPS xmm k xmm +// VGETEXPPS xmm xmm +// VGETEXPPS ymm k ymm +// VGETEXPPS ymm ymm +// VGETEXPPS m512 k zmm +// VGETEXPPS m512 zmm +// VGETEXPPS zmm k zmm +// VGETEXPPS zmm zmm +func VGETEXPPS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVGETEXPPS.Forms(), sffxs{}, ops) +} + +// VGETEXPPS_BCST: Extract Exponents of Packed Single-Precision Floating-Point Values as Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VGETEXPPS.BCST m32 k xmm +// VGETEXPPS.BCST m32 k ymm +// VGETEXPPS.BCST m32 xmm +// VGETEXPPS.BCST m32 ymm +// VGETEXPPS.BCST m32 k zmm +// VGETEXPPS.BCST m32 zmm +func VGETEXPPS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVGETEXPPS.Forms(), sffxs{sffxBCST}, ops) +} + +// VGETEXPPS_BCST_Z: Extract Exponents of Packed Single-Precision Floating-Point Values as Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VGETEXPPS.BCST.Z m32 k xmm +// VGETEXPPS.BCST.Z m32 k ymm +// VGETEXPPS.BCST.Z m32 k zmm +func VGETEXPPS_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVGETEXPPS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) +} + +// VGETEXPPS_SAE: Extract Exponents of Packed Single-Precision Floating-Point Values as Single-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VGETEXPPS.SAE zmm k zmm +// VGETEXPPS.SAE zmm zmm +func VGETEXPPS_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVGETEXPPS.Forms(), sffxs{sffxSAE}, ops) +} + +// VGETEXPPS_SAE_Z: Extract Exponents of Packed Single-Precision Floating-Point Values as Single-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VGETEXPPS.SAE.Z zmm k zmm +func VGETEXPPS_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVGETEXPPS.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{z, k, z1}) +} + +// VGETEXPPS_Z: Extract Exponents of Packed Single-Precision Floating-Point Values as Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VGETEXPPS.Z m128 k xmm +// VGETEXPPS.Z m256 k ymm +// VGETEXPPS.Z xmm k xmm +// VGETEXPPS.Z ymm k ymm +// VGETEXPPS.Z m512 k zmm +// VGETEXPPS.Z zmm k zmm +func VGETEXPPS_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVGETEXPPS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) +} + +// VGETEXPSD: Extract Exponent of Scalar Double-Precision Floating-Point Value as Double-Precision Floating-Point Value. +// +// Forms: +// +// VGETEXPSD m64 xmm k xmm +// VGETEXPSD m64 xmm xmm +// VGETEXPSD xmm xmm k xmm +// VGETEXPSD xmm xmm xmm +func VGETEXPSD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVGETEXPSD.Forms(), sffxs{}, ops) +} + +// VGETEXPSD_SAE: Extract Exponent of Scalar Double-Precision Floating-Point Value as Double-Precision Floating-Point Value (Suppress All Exceptions). +// +// Forms: +// +// VGETEXPSD.SAE xmm xmm k xmm +// VGETEXPSD.SAE xmm xmm xmm +func VGETEXPSD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVGETEXPSD.Forms(), sffxs{sffxSAE}, ops) +} + +// VGETEXPSD_SAE_Z: Extract Exponent of Scalar Double-Precision Floating-Point Value as Double-Precision Floating-Point Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VGETEXPSD.SAE.Z xmm xmm k xmm +func VGETEXPSD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVGETEXPSD.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VGETEXPSD_Z: Extract Exponent of Scalar Double-Precision Floating-Point Value as Double-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VGETEXPSD.Z m64 xmm k xmm +// VGETEXPSD.Z xmm xmm k xmm +func VGETEXPSD_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVGETEXPSD.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VGETEXPSS: Extract Exponent of Scalar Single-Precision Floating-Point Value as Single-Precision Floating-Point Value. +// +// Forms: +// +// VGETEXPSS m32 xmm k xmm +// VGETEXPSS m32 xmm xmm +// VGETEXPSS xmm xmm k xmm +// VGETEXPSS xmm xmm xmm +func VGETEXPSS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVGETEXPSS.Forms(), sffxs{}, ops) +} + +// VGETEXPSS_SAE: Extract Exponent of Scalar Single-Precision Floating-Point Value as Single-Precision Floating-Point Value (Suppress All Exceptions). +// +// Forms: +// +// VGETEXPSS.SAE xmm xmm k xmm +// VGETEXPSS.SAE xmm xmm xmm +func VGETEXPSS_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVGETEXPSS.Forms(), sffxs{sffxSAE}, ops) +} + +// VGETEXPSS_SAE_Z: Extract Exponent of Scalar Single-Precision Floating-Point Value as Single-Precision Floating-Point Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VGETEXPSS.SAE.Z xmm xmm k xmm +func VGETEXPSS_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVGETEXPSS.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VGETEXPSS_Z: Extract Exponent of Scalar Single-Precision Floating-Point Value as Single-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VGETEXPSS.Z m32 xmm k xmm +// VGETEXPSS.Z xmm xmm k xmm +func VGETEXPSS_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVGETEXPSS.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VGETMANTPD: Extract Normalized Mantissas from Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VGETMANTPD imm8 m128 k xmm +// VGETMANTPD imm8 m128 xmm +// VGETMANTPD imm8 m256 k ymm +// VGETMANTPD imm8 m256 ymm +// VGETMANTPD imm8 xmm k xmm +// VGETMANTPD imm8 xmm xmm +// VGETMANTPD imm8 ymm k ymm +// VGETMANTPD imm8 ymm ymm +// VGETMANTPD imm8 m512 k zmm +// VGETMANTPD imm8 m512 zmm +// VGETMANTPD imm8 zmm k zmm +// VGETMANTPD imm8 zmm zmm +func VGETMANTPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVGETMANTPD.Forms(), sffxs{}, ops) +} + +// VGETMANTPD_BCST: Extract Normalized Mantissas from Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VGETMANTPD.BCST imm8 m64 k xmm +// VGETMANTPD.BCST imm8 m64 k ymm +// VGETMANTPD.BCST imm8 m64 xmm +// VGETMANTPD.BCST imm8 m64 ymm +// VGETMANTPD.BCST imm8 m64 k zmm +// VGETMANTPD.BCST imm8 m64 zmm +func VGETMANTPD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVGETMANTPD.Forms(), sffxs{sffxBCST}, ops) +} + +// VGETMANTPD_BCST_Z: Extract Normalized Mantissas from Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VGETMANTPD.BCST.Z imm8 m64 k xmm +// VGETMANTPD.BCST.Z imm8 m64 k ymm +// VGETMANTPD.BCST.Z imm8 m64 k zmm +func VGETMANTPD_BCST_Z(i, m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVGETMANTPD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{i, m, k, xyz}) +} + +// VGETMANTPD_SAE: Extract Normalized Mantissas from Packed Double-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VGETMANTPD.SAE imm8 zmm k zmm +// VGETMANTPD.SAE imm8 zmm zmm +func VGETMANTPD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVGETMANTPD.Forms(), sffxs{sffxSAE}, ops) +} + +// VGETMANTPD_SAE_Z: Extract Normalized Mantissas from Packed Double-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VGETMANTPD.SAE.Z imm8 zmm k zmm +func VGETMANTPD_SAE_Z(i, z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVGETMANTPD.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{i, z, k, z1}) +} + +// VGETMANTPD_Z: Extract Normalized Mantissas from Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VGETMANTPD.Z imm8 m128 k xmm +// VGETMANTPD.Z imm8 m256 k ymm +// VGETMANTPD.Z imm8 xmm k xmm +// VGETMANTPD.Z imm8 ymm k ymm +// VGETMANTPD.Z imm8 m512 k zmm +// VGETMANTPD.Z imm8 zmm k zmm +func VGETMANTPD_Z(i, mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVGETMANTPD.Forms(), sffxs{sffxZ}, []operand.Op{i, mxyz, k, xyz}) +} + +// VGETMANTPS: Extract Normalized Mantissas from Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VGETMANTPS imm8 m128 k xmm +// VGETMANTPS imm8 m128 xmm +// VGETMANTPS imm8 m256 k ymm +// VGETMANTPS imm8 m256 ymm +// VGETMANTPS imm8 xmm k xmm +// VGETMANTPS imm8 xmm xmm +// VGETMANTPS imm8 ymm k ymm +// VGETMANTPS imm8 ymm ymm +// VGETMANTPS imm8 m512 k zmm +// VGETMANTPS imm8 m512 zmm +// VGETMANTPS imm8 zmm k zmm +// VGETMANTPS imm8 zmm zmm +func VGETMANTPS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVGETMANTPS.Forms(), sffxs{}, ops) +} + +// VGETMANTPS_BCST: Extract Normalized Mantissas from Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VGETMANTPS.BCST imm8 m32 k xmm +// VGETMANTPS.BCST imm8 m32 k ymm +// VGETMANTPS.BCST imm8 m32 xmm +// VGETMANTPS.BCST imm8 m32 ymm +// VGETMANTPS.BCST imm8 m32 k zmm +// VGETMANTPS.BCST imm8 m32 zmm +func VGETMANTPS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVGETMANTPS.Forms(), sffxs{sffxBCST}, ops) +} + +// VGETMANTPS_BCST_Z: Extract Normalized Mantissas from Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VGETMANTPS.BCST.Z imm8 m32 k xmm +// VGETMANTPS.BCST.Z imm8 m32 k ymm +// VGETMANTPS.BCST.Z imm8 m32 k zmm +func VGETMANTPS_BCST_Z(i, m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVGETMANTPS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{i, m, k, xyz}) +} + +// VGETMANTPS_SAE: Extract Normalized Mantissas from Packed Single-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VGETMANTPS.SAE imm8 zmm k zmm +// VGETMANTPS.SAE imm8 zmm zmm +func VGETMANTPS_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVGETMANTPS.Forms(), sffxs{sffxSAE}, ops) +} + +// VGETMANTPS_SAE_Z: Extract Normalized Mantissas from Packed Single-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VGETMANTPS.SAE.Z imm8 zmm k zmm +func VGETMANTPS_SAE_Z(i, z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVGETMANTPS.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{i, z, k, z1}) +} + +// VGETMANTPS_Z: Extract Normalized Mantissas from Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VGETMANTPS.Z imm8 m128 k xmm +// VGETMANTPS.Z imm8 m256 k ymm +// VGETMANTPS.Z imm8 xmm k xmm +// VGETMANTPS.Z imm8 ymm k ymm +// VGETMANTPS.Z imm8 m512 k zmm +// VGETMANTPS.Z imm8 zmm k zmm +func VGETMANTPS_Z(i, mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVGETMANTPS.Forms(), sffxs{sffxZ}, []operand.Op{i, mxyz, k, xyz}) +} + +// VGETMANTSD: Extract Normalized Mantissa from Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// VGETMANTSD imm8 m64 xmm k xmm +// VGETMANTSD imm8 m64 xmm xmm +// VGETMANTSD imm8 xmm xmm k xmm +// VGETMANTSD imm8 xmm xmm xmm +func VGETMANTSD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVGETMANTSD.Forms(), sffxs{}, ops) +} + +// VGETMANTSD_SAE: Extract Normalized Mantissa from Scalar Double-Precision Floating-Point Value (Suppress All Exceptions). +// +// Forms: +// +// VGETMANTSD.SAE imm8 xmm xmm k xmm +// VGETMANTSD.SAE imm8 xmm xmm xmm +func VGETMANTSD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVGETMANTSD.Forms(), sffxs{sffxSAE}, ops) +} + +// VGETMANTSD_SAE_Z: Extract Normalized Mantissa from Scalar Double-Precision Floating-Point Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VGETMANTSD.SAE.Z imm8 xmm xmm k xmm +func VGETMANTSD_SAE_Z(i, x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVGETMANTSD.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{i, x, x1, k, x2}) +} + +// VGETMANTSD_Z: Extract Normalized Mantissa from Scalar Double-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VGETMANTSD.Z imm8 m64 xmm k xmm +// VGETMANTSD.Z imm8 xmm xmm k xmm +func VGETMANTSD_Z(i, mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVGETMANTSD.Forms(), sffxs{sffxZ}, []operand.Op{i, mx, x, k, x1}) +} + +// VGETMANTSS: Extract Normalized Mantissa from Scalar Single-Precision Floating-Point Value. +// +// Forms: +// +// VGETMANTSS imm8 m32 xmm k xmm +// VGETMANTSS imm8 m32 xmm xmm +// VGETMANTSS imm8 xmm xmm k xmm +// VGETMANTSS imm8 xmm xmm xmm +func VGETMANTSS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVGETMANTSS.Forms(), sffxs{}, ops) +} + +// VGETMANTSS_SAE: Extract Normalized Mantissa from Scalar Single-Precision Floating-Point Value (Suppress All Exceptions). +// +// Forms: +// +// VGETMANTSS.SAE imm8 xmm xmm k xmm +// VGETMANTSS.SAE imm8 xmm xmm xmm +func VGETMANTSS_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVGETMANTSS.Forms(), sffxs{sffxSAE}, ops) +} + +// VGETMANTSS_SAE_Z: Extract Normalized Mantissa from Scalar Single-Precision Floating-Point Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VGETMANTSS.SAE.Z imm8 xmm xmm k xmm +func VGETMANTSS_SAE_Z(i, x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVGETMANTSS.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{i, x, x1, k, x2}) +} + +// VGETMANTSS_Z: Extract Normalized Mantissa from Scalar Single-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VGETMANTSS.Z imm8 m32 xmm k xmm +// VGETMANTSS.Z imm8 xmm xmm k xmm +func VGETMANTSS_Z(i, mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVGETMANTSS.Forms(), sffxs{sffxZ}, []operand.Op{i, mx, x, k, x1}) +} + +// VHADDPD: Packed Double-FP Horizontal Add. +// +// Forms: +// +// VHADDPD m128 xmm xmm +// VHADDPD m256 ymm ymm +// VHADDPD xmm xmm xmm +// VHADDPD ymm ymm ymm +func VHADDPD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { + return build(opcVHADDPD.Forms(), sffxs{}, []operand.Op{mxy, xy, xy1}) +} + +// VHADDPS: Packed Single-FP Horizontal Add. +// +// Forms: +// +// VHADDPS m128 xmm xmm +// VHADDPS m256 ymm ymm +// VHADDPS xmm xmm xmm +// VHADDPS ymm ymm ymm +func VHADDPS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { + return build(opcVHADDPS.Forms(), sffxs{}, []operand.Op{mxy, xy, xy1}) +} + +// VHSUBPD: Packed Double-FP Horizontal Subtract. +// +// Forms: +// +// VHSUBPD m128 xmm xmm +// VHSUBPD m256 ymm ymm +// VHSUBPD xmm xmm xmm +// VHSUBPD ymm ymm ymm +func VHSUBPD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { + return build(opcVHSUBPD.Forms(), sffxs{}, []operand.Op{mxy, xy, xy1}) +} + +// VHSUBPS: Packed Single-FP Horizontal Subtract. +// +// Forms: +// +// VHSUBPS m128 xmm xmm +// VHSUBPS m256 ymm ymm +// VHSUBPS xmm xmm xmm +// VHSUBPS ymm ymm ymm +func VHSUBPS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { + return build(opcVHSUBPS.Forms(), sffxs{}, []operand.Op{mxy, xy, xy1}) +} + +// VINSERTF128: Insert Packed Floating-Point Values. +// +// Forms: +// +// VINSERTF128 imm8 m128 ymm ymm +// VINSERTF128 imm8 xmm ymm ymm +func VINSERTF128(i, mx, y, y1 operand.Op) (*intrep.Instruction, error) { + return build(opcVINSERTF128.Forms(), sffxs{}, []operand.Op{i, mx, y, y1}) +} + +// VINSERTF32X4: Insert 128 Bits of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VINSERTF32X4 imm8 m128 ymm k ymm +// VINSERTF32X4 imm8 m128 ymm ymm +// VINSERTF32X4 imm8 xmm ymm k ymm +// VINSERTF32X4 imm8 xmm ymm ymm +// VINSERTF32X4 imm8 m128 zmm k zmm +// VINSERTF32X4 imm8 m128 zmm zmm +// VINSERTF32X4 imm8 xmm zmm k zmm +// VINSERTF32X4 imm8 xmm zmm zmm +func VINSERTF32X4(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVINSERTF32X4.Forms(), sffxs{}, ops) +} + +// VINSERTF32X4_Z: Insert 128 Bits of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VINSERTF32X4.Z imm8 m128 ymm k ymm +// VINSERTF32X4.Z imm8 xmm ymm k ymm +// VINSERTF32X4.Z imm8 m128 zmm k zmm +// VINSERTF32X4.Z imm8 xmm zmm k zmm +func VINSERTF32X4_Z(i, mx, yz, k, yz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVINSERTF32X4.Forms(), sffxs{sffxZ}, []operand.Op{i, mx, yz, k, yz1}) +} + +// VINSERTF32X8: Insert 256 Bits of Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VINSERTF32X8 imm8 m256 zmm k zmm +// VINSERTF32X8 imm8 m256 zmm zmm +// VINSERTF32X8 imm8 ymm zmm k zmm +// VINSERTF32X8 imm8 ymm zmm zmm +func VINSERTF32X8(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVINSERTF32X8.Forms(), sffxs{}, ops) +} + +// VINSERTF32X8_Z: Insert 256 Bits of Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VINSERTF32X8.Z imm8 m256 zmm k zmm +// VINSERTF32X8.Z imm8 ymm zmm k zmm +func VINSERTF32X8_Z(i, my, z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVINSERTF32X8.Forms(), sffxs{sffxZ}, []operand.Op{i, my, z, k, z1}) +} + +// VINSERTF64X2: Insert 128 Bits of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VINSERTF64X2 imm8 m128 ymm k ymm +// VINSERTF64X2 imm8 m128 ymm ymm +// VINSERTF64X2 imm8 xmm ymm k ymm +// VINSERTF64X2 imm8 xmm ymm ymm +// VINSERTF64X2 imm8 m128 zmm k zmm +// VINSERTF64X2 imm8 m128 zmm zmm +// VINSERTF64X2 imm8 xmm zmm k zmm +// VINSERTF64X2 imm8 xmm zmm zmm +func VINSERTF64X2(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVINSERTF64X2.Forms(), sffxs{}, ops) +} + +// VINSERTF64X2_Z: Insert 128 Bits of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VINSERTF64X2.Z imm8 m128 ymm k ymm +// VINSERTF64X2.Z imm8 xmm ymm k ymm +// VINSERTF64X2.Z imm8 m128 zmm k zmm +// VINSERTF64X2.Z imm8 xmm zmm k zmm +func VINSERTF64X2_Z(i, mx, yz, k, yz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVINSERTF64X2.Forms(), sffxs{sffxZ}, []operand.Op{i, mx, yz, k, yz1}) +} + +// VINSERTF64X4: Insert 256 Bits of Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VINSERTF64X4 imm8 m256 zmm k zmm +// VINSERTF64X4 imm8 m256 zmm zmm +// VINSERTF64X4 imm8 ymm zmm k zmm +// VINSERTF64X4 imm8 ymm zmm zmm +func VINSERTF64X4(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVINSERTF64X4.Forms(), sffxs{}, ops) +} + +// VINSERTF64X4_Z: Insert 256 Bits of Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VINSERTF64X4.Z imm8 m256 zmm k zmm +// VINSERTF64X4.Z imm8 ymm zmm k zmm +func VINSERTF64X4_Z(i, my, z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVINSERTF64X4.Forms(), sffxs{sffxZ}, []operand.Op{i, my, z, k, z1}) +} + +// VINSERTI128: Insert Packed Integer Values. +// +// Forms: +// +// VINSERTI128 imm8 m128 ymm ymm +// VINSERTI128 imm8 xmm ymm ymm +func VINSERTI128(i, mx, y, y1 operand.Op) (*intrep.Instruction, error) { + return build(opcVINSERTI128.Forms(), sffxs{}, []operand.Op{i, mx, y, y1}) +} + +// VINSERTI32X4: Insert 128 Bits of Packed Doubleword Integer Values. +// +// Forms: +// +// VINSERTI32X4 imm8 m128 ymm k ymm +// VINSERTI32X4 imm8 m128 ymm ymm +// VINSERTI32X4 imm8 xmm ymm k ymm +// VINSERTI32X4 imm8 xmm ymm ymm +// VINSERTI32X4 imm8 m128 zmm k zmm +// VINSERTI32X4 imm8 m128 zmm zmm +// VINSERTI32X4 imm8 xmm zmm k zmm +// VINSERTI32X4 imm8 xmm zmm zmm +func VINSERTI32X4(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVINSERTI32X4.Forms(), sffxs{}, ops) +} + +// VINSERTI32X4_Z: Insert 128 Bits of Packed Doubleword Integer Values (Zeroing Masking). +// +// Forms: +// +// VINSERTI32X4.Z imm8 m128 ymm k ymm +// VINSERTI32X4.Z imm8 xmm ymm k ymm +// VINSERTI32X4.Z imm8 m128 zmm k zmm +// VINSERTI32X4.Z imm8 xmm zmm k zmm +func VINSERTI32X4_Z(i, mx, yz, k, yz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVINSERTI32X4.Forms(), sffxs{sffxZ}, []operand.Op{i, mx, yz, k, yz1}) +} + +// VINSERTI32X8: Insert 256 Bits of Packed Doubleword Integer Values. +// +// Forms: +// +// VINSERTI32X8 imm8 m256 zmm k zmm +// VINSERTI32X8 imm8 m256 zmm zmm +// VINSERTI32X8 imm8 ymm zmm k zmm +// VINSERTI32X8 imm8 ymm zmm zmm +func VINSERTI32X8(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVINSERTI32X8.Forms(), sffxs{}, ops) +} + +// VINSERTI32X8_Z: Insert 256 Bits of Packed Doubleword Integer Values (Zeroing Masking). +// +// Forms: +// +// VINSERTI32X8.Z imm8 m256 zmm k zmm +// VINSERTI32X8.Z imm8 ymm zmm k zmm +func VINSERTI32X8_Z(i, my, z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVINSERTI32X8.Forms(), sffxs{sffxZ}, []operand.Op{i, my, z, k, z1}) +} + +// VINSERTI64X2: Insert 128 Bits of Packed Quadword Integer Values. +// +// Forms: +// +// VINSERTI64X2 imm8 m128 ymm k ymm +// VINSERTI64X2 imm8 m128 ymm ymm +// VINSERTI64X2 imm8 xmm ymm k ymm +// VINSERTI64X2 imm8 xmm ymm ymm +// VINSERTI64X2 imm8 m128 zmm k zmm +// VINSERTI64X2 imm8 m128 zmm zmm +// VINSERTI64X2 imm8 xmm zmm k zmm +// VINSERTI64X2 imm8 xmm zmm zmm +func VINSERTI64X2(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVINSERTI64X2.Forms(), sffxs{}, ops) +} + +// VINSERTI64X2_Z: Insert 128 Bits of Packed Quadword Integer Values (Zeroing Masking). +// +// Forms: +// +// VINSERTI64X2.Z imm8 m128 ymm k ymm +// VINSERTI64X2.Z imm8 xmm ymm k ymm +// VINSERTI64X2.Z imm8 m128 zmm k zmm +// VINSERTI64X2.Z imm8 xmm zmm k zmm +func VINSERTI64X2_Z(i, mx, yz, k, yz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVINSERTI64X2.Forms(), sffxs{sffxZ}, []operand.Op{i, mx, yz, k, yz1}) +} + +// VINSERTI64X4: Insert 256 Bits of Packed Quadword Integer Values. +// +// Forms: +// +// VINSERTI64X4 imm8 m256 zmm k zmm +// VINSERTI64X4 imm8 m256 zmm zmm +// VINSERTI64X4 imm8 ymm zmm k zmm +// VINSERTI64X4 imm8 ymm zmm zmm +func VINSERTI64X4(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVINSERTI64X4.Forms(), sffxs{}, ops) +} + +// VINSERTI64X4_Z: Insert 256 Bits of Packed Quadword Integer Values (Zeroing Masking). +// +// Forms: +// +// VINSERTI64X4.Z imm8 m256 zmm k zmm +// VINSERTI64X4.Z imm8 ymm zmm k zmm +func VINSERTI64X4_Z(i, my, z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVINSERTI64X4.Forms(), sffxs{sffxZ}, []operand.Op{i, my, z, k, z1}) +} + +// VINSERTPS: Insert Packed Single Precision Floating-Point Value. +// +// Forms: +// +// VINSERTPS imm8 m32 xmm xmm +// VINSERTPS imm8 xmm xmm xmm +func VINSERTPS(i, mx, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVINSERTPS.Forms(), sffxs{}, []operand.Op{i, mx, x, x1}) +} + +// VLDDQU: Load Unaligned Integer 128 Bits. +// +// Forms: +// +// VLDDQU m128 xmm +// VLDDQU m256 ymm +func VLDDQU(m, xy operand.Op) (*intrep.Instruction, error) { + return build(opcVLDDQU.Forms(), sffxs{}, []operand.Op{m, xy}) +} + +// VLDMXCSR: Load MXCSR Register. +// +// Forms: +// +// VLDMXCSR m32 +func VLDMXCSR(m operand.Op) (*intrep.Instruction, error) { + return build(opcVLDMXCSR.Forms(), sffxs{}, []operand.Op{m}) +} + +// VMASKMOVDQU: Store Selected Bytes of Double Quadword. +// +// Forms: +// +// VMASKMOVDQU xmm xmm +func VMASKMOVDQU(x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMASKMOVDQU.Forms(), sffxs{}, []operand.Op{x, x1}) +} + +// VMASKMOVPD: Conditional Move Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VMASKMOVPD m128 xmm xmm +// VMASKMOVPD m256 ymm ymm +// VMASKMOVPD xmm xmm m128 +// VMASKMOVPD ymm ymm m256 +func VMASKMOVPD(mxy, xy, mxy1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMASKMOVPD.Forms(), sffxs{}, []operand.Op{mxy, xy, mxy1}) +} + +// VMASKMOVPS: Conditional Move Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VMASKMOVPS m128 xmm xmm +// VMASKMOVPS m256 ymm ymm +// VMASKMOVPS xmm xmm m128 +// VMASKMOVPS ymm ymm m256 +func VMASKMOVPS(mxy, xy, mxy1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMASKMOVPS.Forms(), sffxs{}, []operand.Op{mxy, xy, mxy1}) +} + +// VMAXPD: Return Maximum Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VMAXPD m128 xmm xmm +// VMAXPD m256 ymm ymm +// VMAXPD xmm xmm xmm +// VMAXPD ymm ymm ymm +// VMAXPD m128 xmm k xmm +// VMAXPD m256 ymm k ymm +// VMAXPD xmm xmm k xmm +// VMAXPD ymm ymm k ymm +// VMAXPD m512 zmm k zmm +// VMAXPD m512 zmm zmm +// VMAXPD zmm zmm k zmm +// VMAXPD zmm zmm zmm +func VMAXPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMAXPD.Forms(), sffxs{}, ops) +} + +// VMAXPD_BCST: Return Maximum Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VMAXPD.BCST m64 xmm k xmm +// VMAXPD.BCST m64 xmm xmm +// VMAXPD.BCST m64 ymm k ymm +// VMAXPD.BCST m64 ymm ymm +// VMAXPD.BCST m64 zmm k zmm +// VMAXPD.BCST m64 zmm zmm +func VMAXPD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMAXPD.Forms(), sffxs{sffxBCST}, ops) +} + +// VMAXPD_BCST_Z: Return Maximum Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VMAXPD.BCST.Z m64 xmm k xmm +// VMAXPD.BCST.Z m64 ymm k ymm +// VMAXPD.BCST.Z m64 zmm k zmm +func VMAXPD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMAXPD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VMAXPD_SAE: Return Maximum Packed Double-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VMAXPD.SAE zmm zmm k zmm +// VMAXPD.SAE zmm zmm zmm +func VMAXPD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMAXPD.Forms(), sffxs{sffxSAE}, ops) +} + +// VMAXPD_SAE_Z: Return Maximum Packed Double-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VMAXPD.SAE.Z zmm zmm k zmm +func VMAXPD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVMAXPD.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VMAXPD_Z: Return Maximum Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMAXPD.Z m128 xmm k xmm +// VMAXPD.Z m256 ymm k ymm +// VMAXPD.Z xmm xmm k xmm +// VMAXPD.Z ymm ymm k ymm +// VMAXPD.Z m512 zmm k zmm +// VMAXPD.Z zmm zmm k zmm +func VMAXPD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMAXPD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VMAXPS: Return Maximum Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VMAXPS m128 xmm xmm +// VMAXPS m256 ymm ymm +// VMAXPS xmm xmm xmm +// VMAXPS ymm ymm ymm +// VMAXPS m128 xmm k xmm +// VMAXPS m256 ymm k ymm +// VMAXPS xmm xmm k xmm +// VMAXPS ymm ymm k ymm +// VMAXPS m512 zmm k zmm +// VMAXPS m512 zmm zmm +// VMAXPS zmm zmm k zmm +// VMAXPS zmm zmm zmm +func VMAXPS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMAXPS.Forms(), sffxs{}, ops) +} + +// VMAXPS_BCST: Return Maximum Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VMAXPS.BCST m32 xmm k xmm +// VMAXPS.BCST m32 xmm xmm +// VMAXPS.BCST m32 ymm k ymm +// VMAXPS.BCST m32 ymm ymm +// VMAXPS.BCST m32 zmm k zmm +// VMAXPS.BCST m32 zmm zmm +func VMAXPS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMAXPS.Forms(), sffxs{sffxBCST}, ops) +} + +// VMAXPS_BCST_Z: Return Maximum Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VMAXPS.BCST.Z m32 xmm k xmm +// VMAXPS.BCST.Z m32 ymm k ymm +// VMAXPS.BCST.Z m32 zmm k zmm +func VMAXPS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMAXPS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VMAXPS_SAE: Return Maximum Packed Single-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VMAXPS.SAE zmm zmm k zmm +// VMAXPS.SAE zmm zmm zmm +func VMAXPS_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMAXPS.Forms(), sffxs{sffxSAE}, ops) +} + +// VMAXPS_SAE_Z: Return Maximum Packed Single-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VMAXPS.SAE.Z zmm zmm k zmm +func VMAXPS_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVMAXPS.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VMAXPS_Z: Return Maximum Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMAXPS.Z m128 xmm k xmm +// VMAXPS.Z m256 ymm k ymm +// VMAXPS.Z xmm xmm k xmm +// VMAXPS.Z ymm ymm k ymm +// VMAXPS.Z m512 zmm k zmm +// VMAXPS.Z zmm zmm k zmm +func VMAXPS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMAXPS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VMAXSD: Return Maximum Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// VMAXSD m64 xmm xmm +// VMAXSD xmm xmm xmm +// VMAXSD m64 xmm k xmm +// VMAXSD xmm xmm k xmm +func VMAXSD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMAXSD.Forms(), sffxs{}, ops) +} + +// VMAXSD_SAE: Return Maximum Scalar Double-Precision Floating-Point Value (Suppress All Exceptions). +// +// Forms: +// +// VMAXSD.SAE xmm xmm k xmm +// VMAXSD.SAE xmm xmm xmm +func VMAXSD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMAXSD.Forms(), sffxs{sffxSAE}, ops) +} + +// VMAXSD_SAE_Z: Return Maximum Scalar Double-Precision Floating-Point Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VMAXSD.SAE.Z xmm xmm k xmm +func VMAXSD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVMAXSD.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VMAXSD_Z: Return Maximum Scalar Double-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VMAXSD.Z m64 xmm k xmm +// VMAXSD.Z xmm xmm k xmm +func VMAXSD_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMAXSD.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VMAXSS: Return Maximum Scalar Single-Precision Floating-Point Value. +// +// Forms: +// +// VMAXSS m32 xmm xmm +// VMAXSS xmm xmm xmm +// VMAXSS m32 xmm k xmm +// VMAXSS xmm xmm k xmm +func VMAXSS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMAXSS.Forms(), sffxs{}, ops) +} + +// VMAXSS_SAE: Return Maximum Scalar Single-Precision Floating-Point Value (Suppress All Exceptions). +// +// Forms: +// +// VMAXSS.SAE xmm xmm k xmm +// VMAXSS.SAE xmm xmm xmm +func VMAXSS_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMAXSS.Forms(), sffxs{sffxSAE}, ops) +} + +// VMAXSS_SAE_Z: Return Maximum Scalar Single-Precision Floating-Point Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VMAXSS.SAE.Z xmm xmm k xmm +func VMAXSS_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVMAXSS.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VMAXSS_Z: Return Maximum Scalar Single-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VMAXSS.Z m32 xmm k xmm +// VMAXSS.Z xmm xmm k xmm +func VMAXSS_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMAXSS.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VMINPD: Return Minimum Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VMINPD m128 xmm xmm +// VMINPD m256 ymm ymm +// VMINPD xmm xmm xmm +// VMINPD ymm ymm ymm +// VMINPD m128 xmm k xmm +// VMINPD m256 ymm k ymm +// VMINPD xmm xmm k xmm +// VMINPD ymm ymm k ymm +// VMINPD m512 zmm k zmm +// VMINPD m512 zmm zmm +// VMINPD zmm zmm k zmm +// VMINPD zmm zmm zmm +func VMINPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMINPD.Forms(), sffxs{}, ops) +} + +// VMINPD_BCST: Return Minimum Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VMINPD.BCST m64 xmm k xmm +// VMINPD.BCST m64 xmm xmm +// VMINPD.BCST m64 ymm k ymm +// VMINPD.BCST m64 ymm ymm +// VMINPD.BCST m64 zmm k zmm +// VMINPD.BCST m64 zmm zmm +func VMINPD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMINPD.Forms(), sffxs{sffxBCST}, ops) +} + +// VMINPD_BCST_Z: Return Minimum Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VMINPD.BCST.Z m64 xmm k xmm +// VMINPD.BCST.Z m64 ymm k ymm +// VMINPD.BCST.Z m64 zmm k zmm +func VMINPD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMINPD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VMINPD_SAE: Return Minimum Packed Double-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VMINPD.SAE zmm zmm k zmm +// VMINPD.SAE zmm zmm zmm +func VMINPD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMINPD.Forms(), sffxs{sffxSAE}, ops) +} + +// VMINPD_SAE_Z: Return Minimum Packed Double-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VMINPD.SAE.Z zmm zmm k zmm +func VMINPD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVMINPD.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VMINPD_Z: Return Minimum Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMINPD.Z m128 xmm k xmm +// VMINPD.Z m256 ymm k ymm +// VMINPD.Z xmm xmm k xmm +// VMINPD.Z ymm ymm k ymm +// VMINPD.Z m512 zmm k zmm +// VMINPD.Z zmm zmm k zmm +func VMINPD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMINPD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VMINPS: Return Minimum Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VMINPS m128 xmm xmm +// VMINPS m256 ymm ymm +// VMINPS xmm xmm xmm +// VMINPS ymm ymm ymm +// VMINPS m128 xmm k xmm +// VMINPS m256 ymm k ymm +// VMINPS xmm xmm k xmm +// VMINPS ymm ymm k ymm +// VMINPS m512 zmm k zmm +// VMINPS m512 zmm zmm +// VMINPS zmm zmm k zmm +// VMINPS zmm zmm zmm +func VMINPS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMINPS.Forms(), sffxs{}, ops) +} + +// VMINPS_BCST: Return Minimum Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VMINPS.BCST m32 xmm k xmm +// VMINPS.BCST m32 xmm xmm +// VMINPS.BCST m32 ymm k ymm +// VMINPS.BCST m32 ymm ymm +// VMINPS.BCST m32 zmm k zmm +// VMINPS.BCST m32 zmm zmm +func VMINPS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMINPS.Forms(), sffxs{sffxBCST}, ops) +} + +// VMINPS_BCST_Z: Return Minimum Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VMINPS.BCST.Z m32 xmm k xmm +// VMINPS.BCST.Z m32 ymm k ymm +// VMINPS.BCST.Z m32 zmm k zmm +func VMINPS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMINPS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VMINPS_SAE: Return Minimum Packed Single-Precision Floating-Point Values (Suppress All Exceptions). +// +// Forms: +// +// VMINPS.SAE zmm zmm k zmm +// VMINPS.SAE zmm zmm zmm +func VMINPS_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMINPS.Forms(), sffxs{sffxSAE}, ops) +} + +// VMINPS_SAE_Z: Return Minimum Packed Single-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VMINPS.SAE.Z zmm zmm k zmm +func VMINPS_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVMINPS.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VMINPS_Z: Return Minimum Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMINPS.Z m128 xmm k xmm +// VMINPS.Z m256 ymm k ymm +// VMINPS.Z xmm xmm k xmm +// VMINPS.Z ymm ymm k ymm +// VMINPS.Z m512 zmm k zmm +// VMINPS.Z zmm zmm k zmm +func VMINPS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMINPS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VMINSD: Return Minimum Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// VMINSD m64 xmm xmm +// VMINSD xmm xmm xmm +// VMINSD m64 xmm k xmm +// VMINSD xmm xmm k xmm +func VMINSD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMINSD.Forms(), sffxs{}, ops) +} + +// VMINSD_SAE: Return Minimum Scalar Double-Precision Floating-Point Value (Suppress All Exceptions). +// +// Forms: +// +// VMINSD.SAE xmm xmm k xmm +// VMINSD.SAE xmm xmm xmm +func VMINSD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMINSD.Forms(), sffxs{sffxSAE}, ops) +} + +// VMINSD_SAE_Z: Return Minimum Scalar Double-Precision Floating-Point Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VMINSD.SAE.Z xmm xmm k xmm +func VMINSD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVMINSD.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VMINSD_Z: Return Minimum Scalar Double-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VMINSD.Z m64 xmm k xmm +// VMINSD.Z xmm xmm k xmm +func VMINSD_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMINSD.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VMINSS: Return Minimum Scalar Single-Precision Floating-Point Value. +// +// Forms: +// +// VMINSS m32 xmm xmm +// VMINSS xmm xmm xmm +// VMINSS m32 xmm k xmm +// VMINSS xmm xmm k xmm +func VMINSS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMINSS.Forms(), sffxs{}, ops) +} + +// VMINSS_SAE: Return Minimum Scalar Single-Precision Floating-Point Value (Suppress All Exceptions). +// +// Forms: +// +// VMINSS.SAE xmm xmm k xmm +// VMINSS.SAE xmm xmm xmm +func VMINSS_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMINSS.Forms(), sffxs{sffxSAE}, ops) +} + +// VMINSS_SAE_Z: Return Minimum Scalar Single-Precision Floating-Point Value (Suppress All Exceptions, Zeroing Masking). +// +// Forms: +// +// VMINSS.SAE.Z xmm xmm k xmm +func VMINSS_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVMINSS.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VMINSS_Z: Return Minimum Scalar Single-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VMINSS.Z m32 xmm k xmm +// VMINSS.Z xmm xmm k xmm +func VMINSS_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMINSS.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VMOVAPD: Move Aligned Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VMOVAPD m128 xmm +// VMOVAPD m256 ymm +// VMOVAPD xmm m128 +// VMOVAPD xmm xmm +// VMOVAPD ymm m256 +// VMOVAPD ymm ymm +// VMOVAPD m128 k xmm +// VMOVAPD m256 k ymm +// VMOVAPD xmm k m128 +// VMOVAPD xmm k xmm +// VMOVAPD ymm k m256 +// VMOVAPD ymm k ymm +// VMOVAPD m512 k zmm +// VMOVAPD m512 zmm +// VMOVAPD zmm k m512 +// VMOVAPD zmm k zmm +// VMOVAPD zmm m512 +// VMOVAPD zmm zmm +func VMOVAPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVAPD.Forms(), sffxs{}, ops) +} + +// VMOVAPD_Z: Move Aligned Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMOVAPD.Z m128 k xmm +// VMOVAPD.Z m256 k ymm +// VMOVAPD.Z xmm k m128 +// VMOVAPD.Z xmm k xmm +// VMOVAPD.Z ymm k m256 +// VMOVAPD.Z ymm k ymm +// VMOVAPD.Z m512 k zmm +// VMOVAPD.Z zmm k m512 +// VMOVAPD.Z zmm k zmm +func VMOVAPD_Z(mxyz, k, mxyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVAPD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, mxyz1}) +} + +// VMOVAPS: Move Aligned Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VMOVAPS m128 xmm +// VMOVAPS m256 ymm +// VMOVAPS xmm m128 +// VMOVAPS xmm xmm +// VMOVAPS ymm m256 +// VMOVAPS ymm ymm +// VMOVAPS m128 k xmm +// VMOVAPS m256 k ymm +// VMOVAPS xmm k m128 +// VMOVAPS xmm k xmm +// VMOVAPS ymm k m256 +// VMOVAPS ymm k ymm +// VMOVAPS m512 k zmm +// VMOVAPS m512 zmm +// VMOVAPS zmm k m512 +// VMOVAPS zmm k zmm +// VMOVAPS zmm m512 +// VMOVAPS zmm zmm +func VMOVAPS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVAPS.Forms(), sffxs{}, ops) +} + +// VMOVAPS_Z: Move Aligned Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMOVAPS.Z m128 k xmm +// VMOVAPS.Z m256 k ymm +// VMOVAPS.Z xmm k m128 +// VMOVAPS.Z xmm k xmm +// VMOVAPS.Z ymm k m256 +// VMOVAPS.Z ymm k ymm +// VMOVAPS.Z m512 k zmm +// VMOVAPS.Z zmm k m512 +// VMOVAPS.Z zmm k zmm +func VMOVAPS_Z(mxyz, k, mxyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVAPS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, mxyz1}) +} + +// VMOVD: Move Doubleword. +// +// Forms: +// +// VMOVD m32 xmm +// VMOVD r32 xmm +// VMOVD xmm m32 +// VMOVD xmm r32 +func VMOVD(mrx, mrx1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVD.Forms(), sffxs{}, []operand.Op{mrx, mrx1}) +} + +// VMOVDDUP: Move One Double-FP and Duplicate. +// +// Forms: +// +// VMOVDDUP m256 ymm +// VMOVDDUP m64 xmm +// VMOVDDUP xmm xmm +// VMOVDDUP ymm ymm +// VMOVDDUP m256 k ymm +// VMOVDDUP m64 k xmm +// VMOVDDUP xmm k xmm +// VMOVDDUP ymm k ymm +// VMOVDDUP m512 k zmm +// VMOVDDUP m512 zmm +// VMOVDDUP zmm k zmm +// VMOVDDUP zmm zmm +func VMOVDDUP(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVDDUP.Forms(), sffxs{}, ops) +} + +// VMOVDDUP_Z: Move One Double-FP and Duplicate (Zeroing Masking). +// +// Forms: +// +// VMOVDDUP.Z m256 k ymm +// VMOVDDUP.Z m64 k xmm +// VMOVDDUP.Z xmm k xmm +// VMOVDDUP.Z ymm k ymm +// VMOVDDUP.Z m512 k zmm +// VMOVDDUP.Z zmm k zmm +func VMOVDDUP_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVDDUP.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) +} + +// VMOVDQA: Move Aligned Double Quadword. +// +// Forms: +// +// VMOVDQA m128 xmm +// VMOVDQA m256 ymm +// VMOVDQA xmm m128 +// VMOVDQA xmm xmm +// VMOVDQA ymm m256 +// VMOVDQA ymm ymm +func VMOVDQA(mxy, mxy1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVDQA.Forms(), sffxs{}, []operand.Op{mxy, mxy1}) +} + +// VMOVDQA32: Move Aligned Doubleword Values. +// +// Forms: +// +// VMOVDQA32 m128 k xmm +// VMOVDQA32 m128 xmm +// VMOVDQA32 m256 k ymm +// VMOVDQA32 m256 ymm +// VMOVDQA32 xmm k m128 +// VMOVDQA32 xmm k xmm +// VMOVDQA32 xmm m128 +// VMOVDQA32 xmm xmm +// VMOVDQA32 ymm k m256 +// VMOVDQA32 ymm k ymm +// VMOVDQA32 ymm m256 +// VMOVDQA32 ymm ymm +// VMOVDQA32 m512 k zmm +// VMOVDQA32 m512 zmm +// VMOVDQA32 zmm k m512 +// VMOVDQA32 zmm k zmm +// VMOVDQA32 zmm m512 +// VMOVDQA32 zmm zmm +func VMOVDQA32(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVDQA32.Forms(), sffxs{}, ops) +} + +// VMOVDQA32_Z: Move Aligned Doubleword Values (Zeroing Masking). +// +// Forms: +// +// VMOVDQA32.Z m128 k xmm +// VMOVDQA32.Z m256 k ymm +// VMOVDQA32.Z xmm k m128 +// VMOVDQA32.Z xmm k xmm +// VMOVDQA32.Z ymm k m256 +// VMOVDQA32.Z ymm k ymm +// VMOVDQA32.Z m512 k zmm +// VMOVDQA32.Z zmm k m512 +// VMOVDQA32.Z zmm k zmm +func VMOVDQA32_Z(mxyz, k, mxyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVDQA32.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, mxyz1}) +} + +// VMOVDQA64: Move Aligned Quadword Values. +// +// Forms: +// +// VMOVDQA64 m128 k xmm +// VMOVDQA64 m128 xmm +// VMOVDQA64 m256 k ymm +// VMOVDQA64 m256 ymm +// VMOVDQA64 xmm k m128 +// VMOVDQA64 xmm k xmm +// VMOVDQA64 xmm m128 +// VMOVDQA64 xmm xmm +// VMOVDQA64 ymm k m256 +// VMOVDQA64 ymm k ymm +// VMOVDQA64 ymm m256 +// VMOVDQA64 ymm ymm +// VMOVDQA64 m512 k zmm +// VMOVDQA64 m512 zmm +// VMOVDQA64 zmm k m512 +// VMOVDQA64 zmm k zmm +// VMOVDQA64 zmm m512 +// VMOVDQA64 zmm zmm +func VMOVDQA64(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVDQA64.Forms(), sffxs{}, ops) +} + +// VMOVDQA64_Z: Move Aligned Quadword Values (Zeroing Masking). +// +// Forms: +// +// VMOVDQA64.Z m128 k xmm +// VMOVDQA64.Z m256 k ymm +// VMOVDQA64.Z xmm k m128 +// VMOVDQA64.Z xmm k xmm +// VMOVDQA64.Z ymm k m256 +// VMOVDQA64.Z ymm k ymm +// VMOVDQA64.Z m512 k zmm +// VMOVDQA64.Z zmm k m512 +// VMOVDQA64.Z zmm k zmm +func VMOVDQA64_Z(mxyz, k, mxyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVDQA64.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, mxyz1}) +} + +// VMOVDQU: Move Unaligned Double Quadword. +// +// Forms: +// +// VMOVDQU m128 xmm +// VMOVDQU m256 ymm +// VMOVDQU xmm m128 +// VMOVDQU xmm xmm +// VMOVDQU ymm m256 +// VMOVDQU ymm ymm +func VMOVDQU(mxy, mxy1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVDQU.Forms(), sffxs{}, []operand.Op{mxy, mxy1}) +} + +// VMOVDQU16: Move Unaligned Word Values. +// +// Forms: +// +// VMOVDQU16 m128 k xmm +// VMOVDQU16 m128 xmm +// VMOVDQU16 m256 k ymm +// VMOVDQU16 m256 ymm +// VMOVDQU16 xmm k m128 +// VMOVDQU16 xmm k xmm +// VMOVDQU16 xmm m128 +// VMOVDQU16 xmm xmm +// VMOVDQU16 ymm k m256 +// VMOVDQU16 ymm k ymm +// VMOVDQU16 ymm m256 +// VMOVDQU16 ymm ymm +// VMOVDQU16 m512 k zmm +// VMOVDQU16 m512 zmm +// VMOVDQU16 zmm k m512 +// VMOVDQU16 zmm k zmm +// VMOVDQU16 zmm m512 +// VMOVDQU16 zmm zmm +func VMOVDQU16(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVDQU16.Forms(), sffxs{}, ops) +} + +// VMOVDQU16_Z: Move Unaligned Word Values (Zeroing Masking). +// +// Forms: +// +// VMOVDQU16.Z m128 k xmm +// VMOVDQU16.Z m256 k ymm +// VMOVDQU16.Z xmm k m128 +// VMOVDQU16.Z xmm k xmm +// VMOVDQU16.Z ymm k m256 +// VMOVDQU16.Z ymm k ymm +// VMOVDQU16.Z m512 k zmm +// VMOVDQU16.Z zmm k m512 +// VMOVDQU16.Z zmm k zmm +func VMOVDQU16_Z(mxyz, k, mxyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVDQU16.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, mxyz1}) +} + +// VMOVDQU32: Move Unaligned Doubleword Values. +// +// Forms: +// +// VMOVDQU32 m128 k xmm +// VMOVDQU32 m128 xmm +// VMOVDQU32 m256 k ymm +// VMOVDQU32 m256 ymm +// VMOVDQU32 xmm k m128 +// VMOVDQU32 xmm k xmm +// VMOVDQU32 xmm m128 +// VMOVDQU32 xmm xmm +// VMOVDQU32 ymm k m256 +// VMOVDQU32 ymm k ymm +// VMOVDQU32 ymm m256 +// VMOVDQU32 ymm ymm +// VMOVDQU32 m512 k zmm +// VMOVDQU32 m512 zmm +// VMOVDQU32 zmm k m512 +// VMOVDQU32 zmm k zmm +// VMOVDQU32 zmm m512 +// VMOVDQU32 zmm zmm +func VMOVDQU32(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVDQU32.Forms(), sffxs{}, ops) +} + +// VMOVDQU32_Z: Move Unaligned Doubleword Values (Zeroing Masking). +// +// Forms: +// +// VMOVDQU32.Z m128 k xmm +// VMOVDQU32.Z m256 k ymm +// VMOVDQU32.Z xmm k m128 +// VMOVDQU32.Z xmm k xmm +// VMOVDQU32.Z ymm k m256 +// VMOVDQU32.Z ymm k ymm +// VMOVDQU32.Z m512 k zmm +// VMOVDQU32.Z zmm k m512 +// VMOVDQU32.Z zmm k zmm +func VMOVDQU32_Z(mxyz, k, mxyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVDQU32.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, mxyz1}) +} + +// VMOVDQU64: Move Unaligned Quadword Values. +// +// Forms: +// +// VMOVDQU64 m128 k xmm +// VMOVDQU64 m128 xmm +// VMOVDQU64 m256 k ymm +// VMOVDQU64 m256 ymm +// VMOVDQU64 xmm k m128 +// VMOVDQU64 xmm k xmm +// VMOVDQU64 xmm m128 +// VMOVDQU64 xmm xmm +// VMOVDQU64 ymm k m256 +// VMOVDQU64 ymm k ymm +// VMOVDQU64 ymm m256 +// VMOVDQU64 ymm ymm +// VMOVDQU64 m512 k zmm +// VMOVDQU64 m512 zmm +// VMOVDQU64 zmm k m512 +// VMOVDQU64 zmm k zmm +// VMOVDQU64 zmm m512 +// VMOVDQU64 zmm zmm +func VMOVDQU64(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVDQU64.Forms(), sffxs{}, ops) +} + +// VMOVDQU64_Z: Move Unaligned Quadword Values (Zeroing Masking). +// +// Forms: +// +// VMOVDQU64.Z m128 k xmm +// VMOVDQU64.Z m256 k ymm +// VMOVDQU64.Z xmm k m128 +// VMOVDQU64.Z xmm k xmm +// VMOVDQU64.Z ymm k m256 +// VMOVDQU64.Z ymm k ymm +// VMOVDQU64.Z m512 k zmm +// VMOVDQU64.Z zmm k m512 +// VMOVDQU64.Z zmm k zmm +func VMOVDQU64_Z(mxyz, k, mxyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVDQU64.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, mxyz1}) +} + +// VMOVDQU8: Move Unaligned Byte Values. +// +// Forms: +// +// VMOVDQU8 m128 k xmm +// VMOVDQU8 m128 xmm +// VMOVDQU8 m256 k ymm +// VMOVDQU8 m256 ymm +// VMOVDQU8 xmm k m128 +// VMOVDQU8 xmm k xmm +// VMOVDQU8 xmm m128 +// VMOVDQU8 xmm xmm +// VMOVDQU8 ymm k m256 +// VMOVDQU8 ymm k ymm +// VMOVDQU8 ymm m256 +// VMOVDQU8 ymm ymm +// VMOVDQU8 m512 k zmm +// VMOVDQU8 m512 zmm +// VMOVDQU8 zmm k m512 +// VMOVDQU8 zmm k zmm +// VMOVDQU8 zmm m512 +// VMOVDQU8 zmm zmm +func VMOVDQU8(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVDQU8.Forms(), sffxs{}, ops) +} + +// VMOVDQU8_Z: Move Unaligned Byte Values (Zeroing Masking). +// +// Forms: +// +// VMOVDQU8.Z m128 k xmm +// VMOVDQU8.Z m256 k ymm +// VMOVDQU8.Z xmm k m128 +// VMOVDQU8.Z xmm k xmm +// VMOVDQU8.Z ymm k m256 +// VMOVDQU8.Z ymm k ymm +// VMOVDQU8.Z m512 k zmm +// VMOVDQU8.Z zmm k m512 +// VMOVDQU8.Z zmm k zmm +func VMOVDQU8_Z(mxyz, k, mxyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVDQU8.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, mxyz1}) +} + +// VMOVHLPS: Move Packed Single-Precision Floating-Point Values High to Low. +// +// Forms: +// +// VMOVHLPS xmm xmm xmm +func VMOVHLPS(x, x1, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVHLPS.Forms(), sffxs{}, []operand.Op{x, x1, x2}) +} + +// VMOVHPD: Move High Packed Double-Precision Floating-Point Value. +// +// Forms: +// +// VMOVHPD m64 xmm xmm +// VMOVHPD xmm m64 +func VMOVHPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVHPD.Forms(), sffxs{}, ops) +} + +// VMOVHPS: Move High Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VMOVHPS m64 xmm xmm +// VMOVHPS xmm m64 +func VMOVHPS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVHPS.Forms(), sffxs{}, ops) +} + +// VMOVLHPS: Move Packed Single-Precision Floating-Point Values Low to High. +// +// Forms: +// +// VMOVLHPS xmm xmm xmm +func VMOVLHPS(x, x1, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVLHPS.Forms(), sffxs{}, []operand.Op{x, x1, x2}) +} + +// VMOVLPD: Move Low Packed Double-Precision Floating-Point Value. +// +// Forms: +// +// VMOVLPD m64 xmm xmm +// VMOVLPD xmm m64 +func VMOVLPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVLPD.Forms(), sffxs{}, ops) +} + +// VMOVLPS: Move Low Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VMOVLPS m64 xmm xmm +// VMOVLPS xmm m64 +func VMOVLPS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVLPS.Forms(), sffxs{}, ops) +} + +// VMOVMSKPD: Extract Packed Double-Precision Floating-Point Sign Mask. +// +// Forms: +// +// VMOVMSKPD xmm r32 +// VMOVMSKPD ymm r32 +func VMOVMSKPD(xy, r operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVMSKPD.Forms(), sffxs{}, []operand.Op{xy, r}) +} + +// VMOVMSKPS: Extract Packed Single-Precision Floating-Point Sign Mask. +// +// Forms: +// +// VMOVMSKPS xmm r32 +// VMOVMSKPS ymm r32 +func VMOVMSKPS(xy, r operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVMSKPS.Forms(), sffxs{}, []operand.Op{xy, r}) +} + +// VMOVNTDQ: Store Double Quadword Using Non-Temporal Hint. +// +// Forms: +// +// VMOVNTDQ xmm m128 +// VMOVNTDQ ymm m256 +// VMOVNTDQ zmm m512 +func VMOVNTDQ(xyz, m operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVNTDQ.Forms(), sffxs{}, []operand.Op{xyz, m}) +} + +// VMOVNTDQA: Load Double Quadword Non-Temporal Aligned Hint. +// +// Forms: +// +// VMOVNTDQA m256 ymm +// VMOVNTDQA m128 xmm +// VMOVNTDQA m512 zmm +func VMOVNTDQA(m, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVNTDQA.Forms(), sffxs{}, []operand.Op{m, xyz}) +} + +// VMOVNTPD: Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint. +// +// Forms: +// +// VMOVNTPD xmm m128 +// VMOVNTPD ymm m256 +// VMOVNTPD zmm m512 +func VMOVNTPD(xyz, m operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVNTPD.Forms(), sffxs{}, []operand.Op{xyz, m}) +} + +// VMOVNTPS: Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint. +// +// Forms: +// +// VMOVNTPS xmm m128 +// VMOVNTPS ymm m256 +// VMOVNTPS zmm m512 +func VMOVNTPS(xyz, m operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVNTPS.Forms(), sffxs{}, []operand.Op{xyz, m}) +} + +// VMOVQ: Move Quadword. +// +// Forms: +// +// VMOVQ m64 xmm +// VMOVQ r64 xmm +// VMOVQ xmm m64 +// VMOVQ xmm r64 +// VMOVQ xmm xmm +func VMOVQ(mrx, mrx1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVQ.Forms(), sffxs{}, []operand.Op{mrx, mrx1}) +} + +// VMOVSD: Move Scalar Double-Precision Floating-Point Value. +// +// Forms: +// +// VMOVSD m64 xmm +// VMOVSD xmm m64 +// VMOVSD xmm xmm xmm +// VMOVSD m64 k xmm +// VMOVSD xmm k m64 +// VMOVSD xmm xmm k xmm +func VMOVSD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVSD.Forms(), sffxs{}, ops) +} + +// VMOVSD_Z: Move Scalar Double-Precision Floating-Point Value (Zeroing Masking). +// +// Forms: +// +// VMOVSD.Z m64 k xmm +// VMOVSD.Z xmm xmm k xmm +func VMOVSD_Z(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVSD.Forms(), sffxs{sffxZ}, ops) +} + +// VMOVSHDUP: Move Packed Single-FP High and Duplicate. +// +// Forms: +// +// VMOVSHDUP m128 xmm +// VMOVSHDUP m256 ymm +// VMOVSHDUP xmm xmm +// VMOVSHDUP ymm ymm +// VMOVSHDUP m128 k xmm +// VMOVSHDUP m256 k ymm +// VMOVSHDUP xmm k xmm +// VMOVSHDUP ymm k ymm +// VMOVSHDUP m512 k zmm +// VMOVSHDUP m512 zmm +// VMOVSHDUP zmm k zmm +// VMOVSHDUP zmm zmm +func VMOVSHDUP(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVSHDUP.Forms(), sffxs{}, ops) +} + +// VMOVSHDUP_Z: Move Packed Single-FP High and Duplicate (Zeroing Masking). +// +// Forms: +// +// VMOVSHDUP.Z m128 k xmm +// VMOVSHDUP.Z m256 k ymm +// VMOVSHDUP.Z xmm k xmm +// VMOVSHDUP.Z ymm k ymm +// VMOVSHDUP.Z m512 k zmm +// VMOVSHDUP.Z zmm k zmm +func VMOVSHDUP_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVSHDUP.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) +} + +// VMOVSLDUP: Move Packed Single-FP Low and Duplicate. +// +// Forms: +// +// VMOVSLDUP m128 xmm +// VMOVSLDUP m256 ymm +// VMOVSLDUP xmm xmm +// VMOVSLDUP ymm ymm +// VMOVSLDUP m128 k xmm +// VMOVSLDUP m256 k ymm +// VMOVSLDUP xmm k xmm +// VMOVSLDUP ymm k ymm +// VMOVSLDUP m512 k zmm +// VMOVSLDUP m512 zmm +// VMOVSLDUP zmm k zmm +// VMOVSLDUP zmm zmm +func VMOVSLDUP(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVSLDUP.Forms(), sffxs{}, ops) +} + +// VMOVSLDUP_Z: Move Packed Single-FP Low and Duplicate (Zeroing Masking). +// +// Forms: +// +// VMOVSLDUP.Z m128 k xmm +// VMOVSLDUP.Z m256 k ymm +// VMOVSLDUP.Z xmm k xmm +// VMOVSLDUP.Z ymm k ymm +// VMOVSLDUP.Z m512 k zmm +// VMOVSLDUP.Z zmm k zmm +func VMOVSLDUP_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVSLDUP.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) +} + +// VMOVSS: Move Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VMOVSS m32 xmm +// VMOVSS xmm m32 +// VMOVSS xmm xmm xmm +// VMOVSS m32 k xmm +// VMOVSS xmm k m32 +// VMOVSS xmm xmm k xmm +func VMOVSS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVSS.Forms(), sffxs{}, ops) +} + +// VMOVSS_Z: Move Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMOVSS.Z m32 k xmm +// VMOVSS.Z xmm xmm k xmm +func VMOVSS_Z(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVSS.Forms(), sffxs{sffxZ}, ops) +} + +// VMOVUPD: Move Unaligned Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VMOVUPD m128 xmm +// VMOVUPD m256 ymm +// VMOVUPD xmm m128 +// VMOVUPD xmm xmm +// VMOVUPD ymm m256 +// VMOVUPD ymm ymm +// VMOVUPD m128 k xmm +// VMOVUPD m256 k ymm +// VMOVUPD xmm k m128 +// VMOVUPD xmm k xmm +// VMOVUPD ymm k m256 +// VMOVUPD ymm k ymm +// VMOVUPD m512 k zmm +// VMOVUPD m512 zmm +// VMOVUPD zmm k m512 +// VMOVUPD zmm k zmm +// VMOVUPD zmm m512 +// VMOVUPD zmm zmm +func VMOVUPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVUPD.Forms(), sffxs{}, ops) +} + +// VMOVUPD_Z: Move Unaligned Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMOVUPD.Z m128 k xmm +// VMOVUPD.Z m256 k ymm +// VMOVUPD.Z xmm k m128 +// VMOVUPD.Z xmm k xmm +// VMOVUPD.Z ymm k m256 +// VMOVUPD.Z ymm k ymm +// VMOVUPD.Z m512 k zmm +// VMOVUPD.Z zmm k m512 +// VMOVUPD.Z zmm k zmm +func VMOVUPD_Z(mxyz, k, mxyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVUPD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, mxyz1}) +} + +// VMOVUPS: Move Unaligned Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VMOVUPS m128 xmm +// VMOVUPS m256 ymm +// VMOVUPS xmm m128 +// VMOVUPS xmm xmm +// VMOVUPS ymm m256 +// VMOVUPS ymm ymm +// VMOVUPS m128 k xmm +// VMOVUPS m256 k ymm +// VMOVUPS xmm k m128 +// VMOVUPS xmm k xmm +// VMOVUPS ymm k m256 +// VMOVUPS ymm k ymm +// VMOVUPS m512 k zmm +// VMOVUPS m512 zmm +// VMOVUPS zmm k m512 +// VMOVUPS zmm k zmm +// VMOVUPS zmm m512 +// VMOVUPS zmm zmm +func VMOVUPS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVUPS.Forms(), sffxs{}, ops) +} + +// VMOVUPS_Z: Move Unaligned Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMOVUPS.Z m128 k xmm +// VMOVUPS.Z m256 k ymm +// VMOVUPS.Z xmm k m128 +// VMOVUPS.Z xmm k xmm +// VMOVUPS.Z ymm k m256 +// VMOVUPS.Z ymm k ymm +// VMOVUPS.Z m512 k zmm +// VMOVUPS.Z zmm k m512 +// VMOVUPS.Z zmm k zmm +func VMOVUPS_Z(mxyz, k, mxyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMOVUPS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, mxyz1}) +} + +// VMPSADBW: Compute Multiple Packed Sums of Absolute Difference. +// +// Forms: +// +// VMPSADBW imm8 m256 ymm ymm +// VMPSADBW imm8 ymm ymm ymm +// VMPSADBW imm8 m128 xmm xmm +// VMPSADBW imm8 xmm xmm xmm +func VMPSADBW(i, mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMPSADBW.Forms(), sffxs{}, []operand.Op{i, mxy, xy, xy1}) +} + +// VMULPD: Multiply Packed Double-Precision Floating-Point Values. +// +// Forms: +// +// VMULPD m128 xmm xmm +// VMULPD m256 ymm ymm +// VMULPD xmm xmm xmm +// VMULPD ymm ymm ymm +// VMULPD m128 xmm k xmm +// VMULPD m256 ymm k ymm +// VMULPD xmm xmm k xmm +// VMULPD ymm ymm k ymm +// VMULPD m512 zmm k zmm +// VMULPD m512 zmm zmm +// VMULPD zmm zmm k zmm +// VMULPD zmm zmm zmm +func VMULPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMULPD.Forms(), sffxs{}, ops) +} + +// VMULPD_BCST: Multiply Packed Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VMULPD.BCST m64 xmm k xmm +// VMULPD.BCST m64 xmm xmm +// VMULPD.BCST m64 ymm k ymm +// VMULPD.BCST m64 ymm ymm +// VMULPD.BCST m64 zmm k zmm +// VMULPD.BCST m64 zmm zmm +func VMULPD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMULPD.Forms(), sffxs{sffxBCST}, ops) +} + +// VMULPD_BCST_Z: Multiply Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VMULPD.BCST.Z m64 xmm k xmm +// VMULPD.BCST.Z m64 ymm k ymm +// VMULPD.BCST.Z m64 zmm k zmm +func VMULPD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMULPD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VMULPD_RD_SAE: Multiply Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VMULPD.RD_SAE zmm zmm k zmm +// VMULPD.RD_SAE zmm zmm zmm +func VMULPD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMULPD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VMULPD_RD_SAE_Z: Multiply Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VMULPD.RD_SAE.Z zmm zmm k zmm +func VMULPD_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVMULPD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VMULPD_RN_SAE: Multiply Packed Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VMULPD.RN_SAE zmm zmm k zmm +// VMULPD.RN_SAE zmm zmm zmm +func VMULPD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMULPD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VMULPD_RN_SAE_Z: Multiply Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VMULPD.RN_SAE.Z zmm zmm k zmm +func VMULPD_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVMULPD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VMULPD_RU_SAE: Multiply Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VMULPD.RU_SAE zmm zmm k zmm +// VMULPD.RU_SAE zmm zmm zmm +func VMULPD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMULPD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VMULPD_RU_SAE_Z: Multiply Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VMULPD.RU_SAE.Z zmm zmm k zmm +func VMULPD_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVMULPD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VMULPD_RZ_SAE: Multiply Packed Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VMULPD.RZ_SAE zmm zmm k zmm +// VMULPD.RZ_SAE zmm zmm zmm +func VMULPD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMULPD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VMULPD_RZ_SAE_Z: Multiply Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VMULPD.RZ_SAE.Z zmm zmm k zmm +func VMULPD_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVMULPD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VMULPD_Z: Multiply Packed Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMULPD.Z m128 xmm k xmm +// VMULPD.Z m256 ymm k ymm +// VMULPD.Z xmm xmm k xmm +// VMULPD.Z ymm ymm k ymm +// VMULPD.Z m512 zmm k zmm +// VMULPD.Z zmm zmm k zmm +func VMULPD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMULPD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VMULPS: Multiply Packed Single-Precision Floating-Point Values. +// +// Forms: +// +// VMULPS m128 xmm xmm +// VMULPS m256 ymm ymm +// VMULPS xmm xmm xmm +// VMULPS ymm ymm ymm +// VMULPS m128 xmm k xmm +// VMULPS m256 ymm k ymm +// VMULPS xmm xmm k xmm +// VMULPS ymm ymm k ymm +// VMULPS m512 zmm k zmm +// VMULPS m512 zmm zmm +// VMULPS zmm zmm k zmm +// VMULPS zmm zmm zmm +func VMULPS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMULPS.Forms(), sffxs{}, ops) +} + +// VMULPS_BCST: Multiply Packed Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VMULPS.BCST m32 xmm k xmm +// VMULPS.BCST m32 xmm xmm +// VMULPS.BCST m32 ymm k ymm +// VMULPS.BCST m32 ymm ymm +// VMULPS.BCST m32 zmm k zmm +// VMULPS.BCST m32 zmm zmm +func VMULPS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMULPS.Forms(), sffxs{sffxBCST}, ops) +} + +// VMULPS_BCST_Z: Multiply Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VMULPS.BCST.Z m32 xmm k xmm +// VMULPS.BCST.Z m32 ymm k ymm +// VMULPS.BCST.Z m32 zmm k zmm +func VMULPS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMULPS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VMULPS_RD_SAE: Multiply Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VMULPS.RD_SAE zmm zmm k zmm +// VMULPS.RD_SAE zmm zmm zmm +func VMULPS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMULPS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VMULPS_RD_SAE_Z: Multiply Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VMULPS.RD_SAE.Z zmm zmm k zmm +func VMULPS_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVMULPS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VMULPS_RN_SAE: Multiply Packed Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VMULPS.RN_SAE zmm zmm k zmm +// VMULPS.RN_SAE zmm zmm zmm +func VMULPS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMULPS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VMULPS_RN_SAE_Z: Multiply Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VMULPS.RN_SAE.Z zmm zmm k zmm +func VMULPS_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVMULPS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VMULPS_RU_SAE: Multiply Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VMULPS.RU_SAE zmm zmm k zmm +// VMULPS.RU_SAE zmm zmm zmm +func VMULPS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMULPS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VMULPS_RU_SAE_Z: Multiply Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VMULPS.RU_SAE.Z zmm zmm k zmm +func VMULPS_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVMULPS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VMULPS_RZ_SAE: Multiply Packed Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VMULPS.RZ_SAE zmm zmm k zmm +// VMULPS.RZ_SAE zmm zmm zmm +func VMULPS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMULPS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VMULPS_RZ_SAE_Z: Multiply Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VMULPS.RZ_SAE.Z zmm zmm k zmm +func VMULPS_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVMULPS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) +} + +// VMULPS_Z: Multiply Packed Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMULPS.Z m128 xmm k xmm +// VMULPS.Z m256 ymm k ymm +// VMULPS.Z xmm xmm k xmm +// VMULPS.Z ymm ymm k ymm +// VMULPS.Z m512 zmm k zmm +// VMULPS.Z zmm zmm k zmm +func VMULPS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMULPS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VMULSD: Multiply Scalar Double-Precision Floating-Point Values. +// +// Forms: +// +// VMULSD m64 xmm xmm +// VMULSD xmm xmm xmm +// VMULSD m64 xmm k xmm +// VMULSD xmm xmm k xmm +func VMULSD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMULSD.Forms(), sffxs{}, ops) +} + +// VMULSD_RD_SAE: Multiply Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VMULSD.RD_SAE xmm xmm k xmm +// VMULSD.RD_SAE xmm xmm xmm +func VMULSD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMULSD.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VMULSD_RD_SAE_Z: Multiply Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VMULSD.RD_SAE.Z xmm xmm k xmm +func VMULSD_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVMULSD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VMULSD_RN_SAE: Multiply Scalar Double-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VMULSD.RN_SAE xmm xmm k xmm +// VMULSD.RN_SAE xmm xmm xmm +func VMULSD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMULSD.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VMULSD_RN_SAE_Z: Multiply Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VMULSD.RN_SAE.Z xmm xmm k xmm +func VMULSD_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVMULSD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VMULSD_RU_SAE: Multiply Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VMULSD.RU_SAE xmm xmm k xmm +// VMULSD.RU_SAE xmm xmm xmm +func VMULSD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMULSD.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VMULSD_RU_SAE_Z: Multiply Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VMULSD.RU_SAE.Z xmm xmm k xmm +func VMULSD_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVMULSD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VMULSD_RZ_SAE: Multiply Scalar Double-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VMULSD.RZ_SAE xmm xmm k xmm +// VMULSD.RZ_SAE xmm xmm xmm +func VMULSD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMULSD.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VMULSD_RZ_SAE_Z: Multiply Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VMULSD.RZ_SAE.Z xmm xmm k xmm +func VMULSD_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVMULSD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VMULSD_Z: Multiply Scalar Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMULSD.Z m64 xmm k xmm +// VMULSD.Z xmm xmm k xmm +func VMULSD_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMULSD.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VMULSS: Multiply Scalar Single-Precision Floating-Point Values. +// +// Forms: +// +// VMULSS m32 xmm xmm +// VMULSS xmm xmm xmm +// VMULSS m32 xmm k xmm +// VMULSS xmm xmm k xmm +func VMULSS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMULSS.Forms(), sffxs{}, ops) +} + +// VMULSS_RD_SAE: Multiply Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). +// +// Forms: +// +// VMULSS.RD_SAE xmm xmm k xmm +// VMULSS.RD_SAE xmm xmm xmm +func VMULSS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMULSS.Forms(), sffxs{sffxRD_SAE}, ops) +} + +// VMULSS_RD_SAE_Z: Multiply Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). +// +// Forms: +// +// VMULSS.RD_SAE.Z xmm xmm k xmm +func VMULSS_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVMULSS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VMULSS_RN_SAE: Multiply Scalar Single-Precision Floating-Point Values (Round Towards Nearest). +// +// Forms: +// +// VMULSS.RN_SAE xmm xmm k xmm +// VMULSS.RN_SAE xmm xmm xmm +func VMULSS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMULSS.Forms(), sffxs{sffxRN_SAE}, ops) +} + +// VMULSS_RN_SAE_Z: Multiply Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). +// +// Forms: +// +// VMULSS.RN_SAE.Z xmm xmm k xmm +func VMULSS_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVMULSS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VMULSS_RU_SAE: Multiply Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). +// +// Forms: +// +// VMULSS.RU_SAE xmm xmm k xmm +// VMULSS.RU_SAE xmm xmm xmm +func VMULSS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMULSS.Forms(), sffxs{sffxRU_SAE}, ops) +} + +// VMULSS_RU_SAE_Z: Multiply Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). +// +// Forms: +// +// VMULSS.RU_SAE.Z xmm xmm k xmm +func VMULSS_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVMULSS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VMULSS_RZ_SAE: Multiply Scalar Single-Precision Floating-Point Values (Round Towards Zero). +// +// Forms: +// +// VMULSS.RZ_SAE xmm xmm k xmm +// VMULSS.RZ_SAE xmm xmm xmm +func VMULSS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVMULSS.Forms(), sffxs{sffxRZ_SAE}, ops) +} + +// VMULSS_RZ_SAE_Z: Multiply Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). +// +// Forms: +// +// VMULSS.RZ_SAE.Z xmm xmm k xmm +func VMULSS_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVMULSS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) +} + +// VMULSS_Z: Multiply Scalar Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VMULSS.Z m32 xmm k xmm +// VMULSS.Z xmm xmm k xmm +func VMULSS_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVMULSS.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) +} + +// VORPD: Bitwise Logical OR of Double-Precision Floating-Point Values. +// +// Forms: +// +// VORPD m128 xmm xmm +// VORPD m256 ymm ymm +// VORPD xmm xmm xmm +// VORPD ymm ymm ymm +// VORPD m128 xmm k xmm +// VORPD m256 ymm k ymm +// VORPD xmm xmm k xmm +// VORPD ymm ymm k ymm +// VORPD m512 zmm k zmm +// VORPD m512 zmm zmm +// VORPD zmm zmm k zmm +// VORPD zmm zmm zmm +func VORPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVORPD.Forms(), sffxs{}, ops) +} + +// VORPD_BCST: Bitwise Logical OR of Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VORPD.BCST m64 xmm k xmm +// VORPD.BCST m64 xmm xmm +// VORPD.BCST m64 ymm k ymm +// VORPD.BCST m64 ymm ymm +// VORPD.BCST m64 zmm k zmm +// VORPD.BCST m64 zmm zmm +func VORPD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVORPD.Forms(), sffxs{sffxBCST}, ops) +} + +// VORPD_BCST_Z: Bitwise Logical OR of Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VORPD.BCST.Z m64 xmm k xmm +// VORPD.BCST.Z m64 ymm k ymm +// VORPD.BCST.Z m64 zmm k zmm +func VORPD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVORPD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VORPD_Z: Bitwise Logical OR of Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VORPD.Z m128 xmm k xmm +// VORPD.Z m256 ymm k ymm +// VORPD.Z xmm xmm k xmm +// VORPD.Z ymm ymm k ymm +// VORPD.Z m512 zmm k zmm +// VORPD.Z zmm zmm k zmm +func VORPD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVORPD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VORPS: Bitwise Logical OR of Single-Precision Floating-Point Values. +// +// Forms: +// +// VORPS m128 xmm xmm +// VORPS m256 ymm ymm +// VORPS xmm xmm xmm +// VORPS ymm ymm ymm +// VORPS m128 xmm k xmm +// VORPS m256 ymm k ymm +// VORPS xmm xmm k xmm +// VORPS ymm ymm k ymm +// VORPS m512 zmm k zmm +// VORPS m512 zmm zmm +// VORPS zmm zmm k zmm +// VORPS zmm zmm zmm +func VORPS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVORPS.Forms(), sffxs{}, ops) +} + +// VORPS_BCST: Bitwise Logical OR of Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VORPS.BCST m32 xmm k xmm +// VORPS.BCST m32 xmm xmm +// VORPS.BCST m32 ymm k ymm +// VORPS.BCST m32 ymm ymm +// VORPS.BCST m32 zmm k zmm +// VORPS.BCST m32 zmm zmm +func VORPS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVORPS.Forms(), sffxs{sffxBCST}, ops) +} + +// VORPS_BCST_Z: Bitwise Logical OR of Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VORPS.BCST.Z m32 xmm k xmm +// VORPS.BCST.Z m32 ymm k ymm +// VORPS.BCST.Z m32 zmm k zmm +func VORPS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVORPS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VORPS_Z: Bitwise Logical OR of Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VORPS.Z m128 xmm k xmm +// VORPS.Z m256 ymm k ymm +// VORPS.Z xmm xmm k xmm +// VORPS.Z ymm ymm k ymm +// VORPS.Z m512 zmm k zmm +// VORPS.Z zmm zmm k zmm +func VORPS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVORPS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPABSB: Packed Absolute Value of Byte Integers. +// +// Forms: +// +// VPABSB m256 ymm +// VPABSB ymm ymm +// VPABSB m128 xmm +// VPABSB xmm xmm +// VPABSB m128 k xmm +// VPABSB m256 k ymm +// VPABSB xmm k xmm +// VPABSB ymm k ymm +// VPABSB m512 k zmm +// VPABSB m512 zmm +// VPABSB zmm k zmm +// VPABSB zmm zmm +func VPABSB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPABSB.Forms(), sffxs{}, ops) +} + +// VPABSB_Z: Packed Absolute Value of Byte Integers (Zeroing Masking). +// +// Forms: +// +// VPABSB.Z m128 k xmm +// VPABSB.Z m256 k ymm +// VPABSB.Z xmm k xmm +// VPABSB.Z ymm k ymm +// VPABSB.Z m512 k zmm +// VPABSB.Z zmm k zmm +func VPABSB_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPABSB.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) +} + +// VPABSD: Packed Absolute Value of Doubleword Integers. +// +// Forms: +// +// VPABSD m256 ymm +// VPABSD ymm ymm +// VPABSD m128 xmm +// VPABSD xmm xmm +// VPABSD m128 k xmm +// VPABSD m256 k ymm +// VPABSD xmm k xmm +// VPABSD ymm k ymm +// VPABSD m512 k zmm +// VPABSD m512 zmm +// VPABSD zmm k zmm +// VPABSD zmm zmm +func VPABSD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPABSD.Forms(), sffxs{}, ops) +} + +// VPABSD_BCST: Packed Absolute Value of Doubleword Integers (Broadcast). +// +// Forms: +// +// VPABSD.BCST m32 k xmm +// VPABSD.BCST m32 k ymm +// VPABSD.BCST m32 xmm +// VPABSD.BCST m32 ymm +// VPABSD.BCST m32 k zmm +// VPABSD.BCST m32 zmm +func VPABSD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPABSD.Forms(), sffxs{sffxBCST}, ops) +} + +// VPABSD_BCST_Z: Packed Absolute Value of Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPABSD.BCST.Z m32 k xmm +// VPABSD.BCST.Z m32 k ymm +// VPABSD.BCST.Z m32 k zmm +func VPABSD_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPABSD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) +} + +// VPABSD_Z: Packed Absolute Value of Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VPABSD.Z m128 k xmm +// VPABSD.Z m256 k ymm +// VPABSD.Z xmm k xmm +// VPABSD.Z ymm k ymm +// VPABSD.Z m512 k zmm +// VPABSD.Z zmm k zmm +func VPABSD_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPABSD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) +} + +// VPABSQ: Packed Absolute Value of Quadword Integers. +// +// Forms: +// +// VPABSQ m128 k xmm +// VPABSQ m128 xmm +// VPABSQ m256 k ymm +// VPABSQ m256 ymm +// VPABSQ xmm k xmm +// VPABSQ xmm xmm +// VPABSQ ymm k ymm +// VPABSQ ymm ymm +// VPABSQ m512 k zmm +// VPABSQ m512 zmm +// VPABSQ zmm k zmm +// VPABSQ zmm zmm +func VPABSQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPABSQ.Forms(), sffxs{}, ops) +} + +// VPABSQ_BCST: Packed Absolute Value of Quadword Integers (Broadcast). +// +// Forms: +// +// VPABSQ.BCST m64 k xmm +// VPABSQ.BCST m64 k ymm +// VPABSQ.BCST m64 xmm +// VPABSQ.BCST m64 ymm +// VPABSQ.BCST m64 k zmm +// VPABSQ.BCST m64 zmm +func VPABSQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPABSQ.Forms(), sffxs{sffxBCST}, ops) +} + +// VPABSQ_BCST_Z: Packed Absolute Value of Quadword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPABSQ.BCST.Z m64 k xmm +// VPABSQ.BCST.Z m64 k ymm +// VPABSQ.BCST.Z m64 k zmm +func VPABSQ_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPABSQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) +} + +// VPABSQ_Z: Packed Absolute Value of Quadword Integers (Zeroing Masking). +// +// Forms: +// +// VPABSQ.Z m128 k xmm +// VPABSQ.Z m256 k ymm +// VPABSQ.Z xmm k xmm +// VPABSQ.Z ymm k ymm +// VPABSQ.Z m512 k zmm +// VPABSQ.Z zmm k zmm +func VPABSQ_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPABSQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) +} + +// VPABSW: Packed Absolute Value of Word Integers. +// +// Forms: +// +// VPABSW m256 ymm +// VPABSW ymm ymm +// VPABSW m128 xmm +// VPABSW xmm xmm +// VPABSW m128 k xmm +// VPABSW m256 k ymm +// VPABSW xmm k xmm +// VPABSW ymm k ymm +// VPABSW m512 k zmm +// VPABSW m512 zmm +// VPABSW zmm k zmm +// VPABSW zmm zmm +func VPABSW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPABSW.Forms(), sffxs{}, ops) +} + +// VPABSW_Z: Packed Absolute Value of Word Integers (Zeroing Masking). +// +// Forms: +// +// VPABSW.Z m128 k xmm +// VPABSW.Z m256 k ymm +// VPABSW.Z xmm k xmm +// VPABSW.Z ymm k ymm +// VPABSW.Z m512 k zmm +// VPABSW.Z zmm k zmm +func VPABSW_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPABSW.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) +} + +// VPACKSSDW: Pack Doublewords into Words with Signed Saturation. +// +// Forms: +// +// VPACKSSDW m256 ymm ymm +// VPACKSSDW ymm ymm ymm +// VPACKSSDW m128 xmm xmm +// VPACKSSDW xmm xmm xmm +// VPACKSSDW m128 xmm k xmm +// VPACKSSDW m256 ymm k ymm +// VPACKSSDW xmm xmm k xmm +// VPACKSSDW ymm ymm k ymm +// VPACKSSDW m512 zmm k zmm +// VPACKSSDW m512 zmm zmm +// VPACKSSDW zmm zmm k zmm +// VPACKSSDW zmm zmm zmm +func VPACKSSDW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPACKSSDW.Forms(), sffxs{}, ops) +} + +// VPACKSSDW_BCST: Pack Doublewords into Words with Signed Saturation (Broadcast). +// +// Forms: +// +// VPACKSSDW.BCST m32 xmm k xmm +// VPACKSSDW.BCST m32 xmm xmm +// VPACKSSDW.BCST m32 ymm k ymm +// VPACKSSDW.BCST m32 ymm ymm +// VPACKSSDW.BCST m32 zmm k zmm +// VPACKSSDW.BCST m32 zmm zmm +func VPACKSSDW_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPACKSSDW.Forms(), sffxs{sffxBCST}, ops) +} + +// VPACKSSDW_BCST_Z: Pack Doublewords into Words with Signed Saturation (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPACKSSDW.BCST.Z m32 xmm k xmm +// VPACKSSDW.BCST.Z m32 ymm k ymm +// VPACKSSDW.BCST.Z m32 zmm k zmm +func VPACKSSDW_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPACKSSDW.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VPACKSSDW_Z: Pack Doublewords into Words with Signed Saturation (Zeroing Masking). +// +// Forms: +// +// VPACKSSDW.Z m128 xmm k xmm +// VPACKSSDW.Z m256 ymm k ymm +// VPACKSSDW.Z xmm xmm k xmm +// VPACKSSDW.Z ymm ymm k ymm +// VPACKSSDW.Z m512 zmm k zmm +// VPACKSSDW.Z zmm zmm k zmm +func VPACKSSDW_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPACKSSDW.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPACKSSWB: Pack Words into Bytes with Signed Saturation. +// +// Forms: +// +// VPACKSSWB m256 ymm ymm +// VPACKSSWB ymm ymm ymm +// VPACKSSWB m128 xmm xmm +// VPACKSSWB xmm xmm xmm +// VPACKSSWB m128 xmm k xmm +// VPACKSSWB m256 ymm k ymm +// VPACKSSWB xmm xmm k xmm +// VPACKSSWB ymm ymm k ymm +// VPACKSSWB m512 zmm k zmm +// VPACKSSWB m512 zmm zmm +// VPACKSSWB zmm zmm k zmm +// VPACKSSWB zmm zmm zmm +func VPACKSSWB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPACKSSWB.Forms(), sffxs{}, ops) +} + +// VPACKSSWB_Z: Pack Words into Bytes with Signed Saturation (Zeroing Masking). +// +// Forms: +// +// VPACKSSWB.Z m128 xmm k xmm +// VPACKSSWB.Z m256 ymm k ymm +// VPACKSSWB.Z xmm xmm k xmm +// VPACKSSWB.Z ymm ymm k ymm +// VPACKSSWB.Z m512 zmm k zmm +// VPACKSSWB.Z zmm zmm k zmm +func VPACKSSWB_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPACKSSWB.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPACKUSDW: Pack Doublewords into Words with Unsigned Saturation. +// +// Forms: +// +// VPACKUSDW m256 ymm ymm +// VPACKUSDW ymm ymm ymm +// VPACKUSDW m128 xmm xmm +// VPACKUSDW xmm xmm xmm +// VPACKUSDW m128 xmm k xmm +// VPACKUSDW m256 ymm k ymm +// VPACKUSDW xmm xmm k xmm +// VPACKUSDW ymm ymm k ymm +// VPACKUSDW m512 zmm k zmm +// VPACKUSDW m512 zmm zmm +// VPACKUSDW zmm zmm k zmm +// VPACKUSDW zmm zmm zmm +func VPACKUSDW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPACKUSDW.Forms(), sffxs{}, ops) +} + +// VPACKUSDW_BCST: Pack Doublewords into Words with Unsigned Saturation (Broadcast). +// +// Forms: +// +// VPACKUSDW.BCST m32 xmm k xmm +// VPACKUSDW.BCST m32 xmm xmm +// VPACKUSDW.BCST m32 ymm k ymm +// VPACKUSDW.BCST m32 ymm ymm +// VPACKUSDW.BCST m32 zmm k zmm +// VPACKUSDW.BCST m32 zmm zmm +func VPACKUSDW_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPACKUSDW.Forms(), sffxs{sffxBCST}, ops) +} + +// VPACKUSDW_BCST_Z: Pack Doublewords into Words with Unsigned Saturation (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPACKUSDW.BCST.Z m32 xmm k xmm +// VPACKUSDW.BCST.Z m32 ymm k ymm +// VPACKUSDW.BCST.Z m32 zmm k zmm +func VPACKUSDW_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPACKUSDW.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VPACKUSDW_Z: Pack Doublewords into Words with Unsigned Saturation (Zeroing Masking). +// +// Forms: +// +// VPACKUSDW.Z m128 xmm k xmm +// VPACKUSDW.Z m256 ymm k ymm +// VPACKUSDW.Z xmm xmm k xmm +// VPACKUSDW.Z ymm ymm k ymm +// VPACKUSDW.Z m512 zmm k zmm +// VPACKUSDW.Z zmm zmm k zmm +func VPACKUSDW_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPACKUSDW.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPACKUSWB: Pack Words into Bytes with Unsigned Saturation. +// +// Forms: +// +// VPACKUSWB m256 ymm ymm +// VPACKUSWB ymm ymm ymm +// VPACKUSWB m128 xmm xmm +// VPACKUSWB xmm xmm xmm +// VPACKUSWB m128 xmm k xmm +// VPACKUSWB m256 ymm k ymm +// VPACKUSWB xmm xmm k xmm +// VPACKUSWB ymm ymm k ymm +// VPACKUSWB m512 zmm k zmm +// VPACKUSWB m512 zmm zmm +// VPACKUSWB zmm zmm k zmm +// VPACKUSWB zmm zmm zmm +func VPACKUSWB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPACKUSWB.Forms(), sffxs{}, ops) +} + +// VPACKUSWB_Z: Pack Words into Bytes with Unsigned Saturation (Zeroing Masking). +// +// Forms: +// +// VPACKUSWB.Z m128 xmm k xmm +// VPACKUSWB.Z m256 ymm k ymm +// VPACKUSWB.Z xmm xmm k xmm +// VPACKUSWB.Z ymm ymm k ymm +// VPACKUSWB.Z m512 zmm k zmm +// VPACKUSWB.Z zmm zmm k zmm +func VPACKUSWB_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPACKUSWB.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPADDB: Add Packed Byte Integers. +// +// Forms: +// +// VPADDB m256 ymm ymm +// VPADDB ymm ymm ymm +// VPADDB m128 xmm xmm +// VPADDB xmm xmm xmm +// VPADDB m128 xmm k xmm +// VPADDB m256 ymm k ymm +// VPADDB xmm xmm k xmm +// VPADDB ymm ymm k ymm +// VPADDB m512 zmm k zmm +// VPADDB m512 zmm zmm +// VPADDB zmm zmm k zmm +// VPADDB zmm zmm zmm +func VPADDB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPADDB.Forms(), sffxs{}, ops) +} + +// VPADDB_Z: Add Packed Byte Integers (Zeroing Masking). +// +// Forms: +// +// VPADDB.Z m128 xmm k xmm +// VPADDB.Z m256 ymm k ymm +// VPADDB.Z xmm xmm k xmm +// VPADDB.Z ymm ymm k ymm +// VPADDB.Z m512 zmm k zmm +// VPADDB.Z zmm zmm k zmm +func VPADDB_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPADDB.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPADDD: Add Packed Doubleword Integers. +// +// Forms: +// +// VPADDD m256 ymm ymm +// VPADDD ymm ymm ymm +// VPADDD m128 xmm xmm +// VPADDD xmm xmm xmm +// VPADDD m128 xmm k xmm +// VPADDD m256 ymm k ymm +// VPADDD xmm xmm k xmm +// VPADDD ymm ymm k ymm +// VPADDD m512 zmm k zmm +// VPADDD m512 zmm zmm +// VPADDD zmm zmm k zmm +// VPADDD zmm zmm zmm +func VPADDD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPADDD.Forms(), sffxs{}, ops) +} + +// VPADDD_BCST: Add Packed Doubleword Integers (Broadcast). +// +// Forms: +// +// VPADDD.BCST m32 xmm k xmm +// VPADDD.BCST m32 xmm xmm +// VPADDD.BCST m32 ymm k ymm +// VPADDD.BCST m32 ymm ymm +// VPADDD.BCST m32 zmm k zmm +// VPADDD.BCST m32 zmm zmm +func VPADDD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPADDD.Forms(), sffxs{sffxBCST}, ops) +} + +// VPADDD_BCST_Z: Add Packed Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPADDD.BCST.Z m32 xmm k xmm +// VPADDD.BCST.Z m32 ymm k ymm +// VPADDD.BCST.Z m32 zmm k zmm +func VPADDD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPADDD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VPADDD_Z: Add Packed Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VPADDD.Z m128 xmm k xmm +// VPADDD.Z m256 ymm k ymm +// VPADDD.Z xmm xmm k xmm +// VPADDD.Z ymm ymm k ymm +// VPADDD.Z m512 zmm k zmm +// VPADDD.Z zmm zmm k zmm +func VPADDD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPADDD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPADDQ: Add Packed Quadword Integers. +// +// Forms: +// +// VPADDQ m256 ymm ymm +// VPADDQ ymm ymm ymm +// VPADDQ m128 xmm xmm +// VPADDQ xmm xmm xmm +// VPADDQ m128 xmm k xmm +// VPADDQ m256 ymm k ymm +// VPADDQ xmm xmm k xmm +// VPADDQ ymm ymm k ymm +// VPADDQ m512 zmm k zmm +// VPADDQ m512 zmm zmm +// VPADDQ zmm zmm k zmm +// VPADDQ zmm zmm zmm +func VPADDQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPADDQ.Forms(), sffxs{}, ops) +} + +// VPADDQ_BCST: Add Packed Quadword Integers (Broadcast). +// +// Forms: +// +// VPADDQ.BCST m64 xmm k xmm +// VPADDQ.BCST m64 xmm xmm +// VPADDQ.BCST m64 ymm k ymm +// VPADDQ.BCST m64 ymm ymm +// VPADDQ.BCST m64 zmm k zmm +// VPADDQ.BCST m64 zmm zmm +func VPADDQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPADDQ.Forms(), sffxs{sffxBCST}, ops) +} + +// VPADDQ_BCST_Z: Add Packed Quadword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPADDQ.BCST.Z m64 xmm k xmm +// VPADDQ.BCST.Z m64 ymm k ymm +// VPADDQ.BCST.Z m64 zmm k zmm +func VPADDQ_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPADDQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VPADDQ_Z: Add Packed Quadword Integers (Zeroing Masking). +// +// Forms: +// +// VPADDQ.Z m128 xmm k xmm +// VPADDQ.Z m256 ymm k ymm +// VPADDQ.Z xmm xmm k xmm +// VPADDQ.Z ymm ymm k ymm +// VPADDQ.Z m512 zmm k zmm +// VPADDQ.Z zmm zmm k zmm +func VPADDQ_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPADDQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPADDSB: Add Packed Signed Byte Integers with Signed Saturation. +// +// Forms: +// +// VPADDSB m256 ymm ymm +// VPADDSB ymm ymm ymm +// VPADDSB m128 xmm xmm +// VPADDSB xmm xmm xmm +// VPADDSB m128 xmm k xmm +// VPADDSB m256 ymm k ymm +// VPADDSB xmm xmm k xmm +// VPADDSB ymm ymm k ymm +// VPADDSB m512 zmm k zmm +// VPADDSB m512 zmm zmm +// VPADDSB zmm zmm k zmm +// VPADDSB zmm zmm zmm +func VPADDSB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPADDSB.Forms(), sffxs{}, ops) +} + +// VPADDSB_Z: Add Packed Signed Byte Integers with Signed Saturation (Zeroing Masking). +// +// Forms: +// +// VPADDSB.Z m128 xmm k xmm +// VPADDSB.Z m256 ymm k ymm +// VPADDSB.Z xmm xmm k xmm +// VPADDSB.Z ymm ymm k ymm +// VPADDSB.Z m512 zmm k zmm +// VPADDSB.Z zmm zmm k zmm +func VPADDSB_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPADDSB.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPADDSW: Add Packed Signed Word Integers with Signed Saturation. +// +// Forms: +// +// VPADDSW m256 ymm ymm +// VPADDSW ymm ymm ymm +// VPADDSW m128 xmm xmm +// VPADDSW xmm xmm xmm +// VPADDSW m128 xmm k xmm +// VPADDSW m256 ymm k ymm +// VPADDSW xmm xmm k xmm +// VPADDSW ymm ymm k ymm +// VPADDSW m512 zmm k zmm +// VPADDSW m512 zmm zmm +// VPADDSW zmm zmm k zmm +// VPADDSW zmm zmm zmm +func VPADDSW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPADDSW.Forms(), sffxs{}, ops) +} + +// VPADDSW_Z: Add Packed Signed Word Integers with Signed Saturation (Zeroing Masking). +// +// Forms: +// +// VPADDSW.Z m128 xmm k xmm +// VPADDSW.Z m256 ymm k ymm +// VPADDSW.Z xmm xmm k xmm +// VPADDSW.Z ymm ymm k ymm +// VPADDSW.Z m512 zmm k zmm +// VPADDSW.Z zmm zmm k zmm +func VPADDSW_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPADDSW.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPADDUSB: Add Packed Unsigned Byte Integers with Unsigned Saturation. +// +// Forms: +// +// VPADDUSB m256 ymm ymm +// VPADDUSB ymm ymm ymm +// VPADDUSB m128 xmm xmm +// VPADDUSB xmm xmm xmm +// VPADDUSB m128 xmm k xmm +// VPADDUSB m256 ymm k ymm +// VPADDUSB xmm xmm k xmm +// VPADDUSB ymm ymm k ymm +// VPADDUSB m512 zmm k zmm +// VPADDUSB m512 zmm zmm +// VPADDUSB zmm zmm k zmm +// VPADDUSB zmm zmm zmm +func VPADDUSB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPADDUSB.Forms(), sffxs{}, ops) +} + +// VPADDUSB_Z: Add Packed Unsigned Byte Integers with Unsigned Saturation (Zeroing Masking). +// +// Forms: +// +// VPADDUSB.Z m128 xmm k xmm +// VPADDUSB.Z m256 ymm k ymm +// VPADDUSB.Z xmm xmm k xmm +// VPADDUSB.Z ymm ymm k ymm +// VPADDUSB.Z m512 zmm k zmm +// VPADDUSB.Z zmm zmm k zmm +func VPADDUSB_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPADDUSB.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPADDUSW: Add Packed Unsigned Word Integers with Unsigned Saturation. +// +// Forms: +// +// VPADDUSW m256 ymm ymm +// VPADDUSW ymm ymm ymm +// VPADDUSW m128 xmm xmm +// VPADDUSW xmm xmm xmm +// VPADDUSW m128 xmm k xmm +// VPADDUSW m256 ymm k ymm +// VPADDUSW xmm xmm k xmm +// VPADDUSW ymm ymm k ymm +// VPADDUSW m512 zmm k zmm +// VPADDUSW m512 zmm zmm +// VPADDUSW zmm zmm k zmm +// VPADDUSW zmm zmm zmm +func VPADDUSW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPADDUSW.Forms(), sffxs{}, ops) +} + +// VPADDUSW_Z: Add Packed Unsigned Word Integers with Unsigned Saturation (Zeroing Masking). +// +// Forms: +// +// VPADDUSW.Z m128 xmm k xmm +// VPADDUSW.Z m256 ymm k ymm +// VPADDUSW.Z xmm xmm k xmm +// VPADDUSW.Z ymm ymm k ymm +// VPADDUSW.Z m512 zmm k zmm +// VPADDUSW.Z zmm zmm k zmm +func VPADDUSW_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPADDUSW.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPADDW: Add Packed Word Integers. +// +// Forms: +// +// VPADDW m256 ymm ymm +// VPADDW ymm ymm ymm +// VPADDW m128 xmm xmm +// VPADDW xmm xmm xmm +// VPADDW m128 xmm k xmm +// VPADDW m256 ymm k ymm +// VPADDW xmm xmm k xmm +// VPADDW ymm ymm k ymm +// VPADDW m512 zmm k zmm +// VPADDW m512 zmm zmm +// VPADDW zmm zmm k zmm +// VPADDW zmm zmm zmm +func VPADDW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPADDW.Forms(), sffxs{}, ops) +} + +// VPADDW_Z: Add Packed Word Integers (Zeroing Masking). +// +// Forms: +// +// VPADDW.Z m128 xmm k xmm +// VPADDW.Z m256 ymm k ymm +// VPADDW.Z xmm xmm k xmm +// VPADDW.Z ymm ymm k ymm +// VPADDW.Z m512 zmm k zmm +// VPADDW.Z zmm zmm k zmm +func VPADDW_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPADDW.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPALIGNR: Packed Align Right. +// +// Forms: +// +// VPALIGNR imm8 m256 ymm ymm +// VPALIGNR imm8 ymm ymm ymm +// VPALIGNR imm8 m128 xmm xmm +// VPALIGNR imm8 xmm xmm xmm +// VPALIGNR imm8 m128 xmm k xmm +// VPALIGNR imm8 m256 ymm k ymm +// VPALIGNR imm8 xmm xmm k xmm +// VPALIGNR imm8 ymm ymm k ymm +// VPALIGNR imm8 m512 zmm k zmm +// VPALIGNR imm8 m512 zmm zmm +// VPALIGNR imm8 zmm zmm k zmm +// VPALIGNR imm8 zmm zmm zmm +func VPALIGNR(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPALIGNR.Forms(), sffxs{}, ops) +} + +// VPALIGNR_Z: Packed Align Right (Zeroing Masking). +// +// Forms: +// +// VPALIGNR.Z imm8 m128 xmm k xmm +// VPALIGNR.Z imm8 m256 ymm k ymm +// VPALIGNR.Z imm8 xmm xmm k xmm +// VPALIGNR.Z imm8 ymm ymm k ymm +// VPALIGNR.Z imm8 m512 zmm k zmm +// VPALIGNR.Z imm8 zmm zmm k zmm +func VPALIGNR_Z(i, mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPALIGNR.Forms(), sffxs{sffxZ}, []operand.Op{i, mxyz, xyz, k, xyz1}) +} + +// VPAND: Packed Bitwise Logical AND. +// +// Forms: +// +// VPAND m256 ymm ymm +// VPAND ymm ymm ymm +// VPAND m128 xmm xmm +// VPAND xmm xmm xmm +func VPAND(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPAND.Forms(), sffxs{}, []operand.Op{mxy, xy, xy1}) +} + +// VPANDD: Bitwise Logical AND of Packed Doubleword Integers. +// +// Forms: +// +// VPANDD m128 xmm k xmm +// VPANDD m128 xmm xmm +// VPANDD m256 ymm k ymm +// VPANDD m256 ymm ymm +// VPANDD xmm xmm k xmm +// VPANDD xmm xmm xmm +// VPANDD ymm ymm k ymm +// VPANDD ymm ymm ymm +// VPANDD m512 zmm k zmm +// VPANDD m512 zmm zmm +// VPANDD zmm zmm k zmm +// VPANDD zmm zmm zmm +func VPANDD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPANDD.Forms(), sffxs{}, ops) +} + +// VPANDD_BCST: Bitwise Logical AND of Packed Doubleword Integers (Broadcast). +// +// Forms: +// +// VPANDD.BCST m32 xmm k xmm +// VPANDD.BCST m32 xmm xmm +// VPANDD.BCST m32 ymm k ymm +// VPANDD.BCST m32 ymm ymm +// VPANDD.BCST m32 zmm k zmm +// VPANDD.BCST m32 zmm zmm +func VPANDD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPANDD.Forms(), sffxs{sffxBCST}, ops) +} + +// VPANDD_BCST_Z: Bitwise Logical AND of Packed Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPANDD.BCST.Z m32 xmm k xmm +// VPANDD.BCST.Z m32 ymm k ymm +// VPANDD.BCST.Z m32 zmm k zmm +func VPANDD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPANDD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VPANDD_Z: Bitwise Logical AND of Packed Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VPANDD.Z m128 xmm k xmm +// VPANDD.Z m256 ymm k ymm +// VPANDD.Z xmm xmm k xmm +// VPANDD.Z ymm ymm k ymm +// VPANDD.Z m512 zmm k zmm +// VPANDD.Z zmm zmm k zmm +func VPANDD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPANDD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPANDN: Packed Bitwise Logical AND NOT. +// +// Forms: +// +// VPANDN m256 ymm ymm +// VPANDN ymm ymm ymm +// VPANDN m128 xmm xmm +// VPANDN xmm xmm xmm +func VPANDN(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPANDN.Forms(), sffxs{}, []operand.Op{mxy, xy, xy1}) +} + +// VPANDND: Bitwise Logical AND NOT of Packed Doubleword Integers. +// +// Forms: +// +// VPANDND m128 xmm k xmm +// VPANDND m128 xmm xmm +// VPANDND m256 ymm k ymm +// VPANDND m256 ymm ymm +// VPANDND xmm xmm k xmm +// VPANDND xmm xmm xmm +// VPANDND ymm ymm k ymm +// VPANDND ymm ymm ymm +// VPANDND m512 zmm k zmm +// VPANDND m512 zmm zmm +// VPANDND zmm zmm k zmm +// VPANDND zmm zmm zmm +func VPANDND(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPANDND.Forms(), sffxs{}, ops) +} + +// VPANDND_BCST: Bitwise Logical AND NOT of Packed Doubleword Integers (Broadcast). +// +// Forms: +// +// VPANDND.BCST m32 xmm k xmm +// VPANDND.BCST m32 xmm xmm +// VPANDND.BCST m32 ymm k ymm +// VPANDND.BCST m32 ymm ymm +// VPANDND.BCST m32 zmm k zmm +// VPANDND.BCST m32 zmm zmm +func VPANDND_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPANDND.Forms(), sffxs{sffxBCST}, ops) +} + +// VPANDND_BCST_Z: Bitwise Logical AND NOT of Packed Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPANDND.BCST.Z m32 xmm k xmm +// VPANDND.BCST.Z m32 ymm k ymm +// VPANDND.BCST.Z m32 zmm k zmm +func VPANDND_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPANDND.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VPANDND_Z: Bitwise Logical AND NOT of Packed Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VPANDND.Z m128 xmm k xmm +// VPANDND.Z m256 ymm k ymm +// VPANDND.Z xmm xmm k xmm +// VPANDND.Z ymm ymm k ymm +// VPANDND.Z m512 zmm k zmm +// VPANDND.Z zmm zmm k zmm +func VPANDND_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPANDND.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPANDNQ: Bitwise Logical AND NOT of Packed Quadword Integers. +// +// Forms: +// +// VPANDNQ m128 xmm k xmm +// VPANDNQ m128 xmm xmm +// VPANDNQ m256 ymm k ymm +// VPANDNQ m256 ymm ymm +// VPANDNQ xmm xmm k xmm +// VPANDNQ xmm xmm xmm +// VPANDNQ ymm ymm k ymm +// VPANDNQ ymm ymm ymm +// VPANDNQ m512 zmm k zmm +// VPANDNQ m512 zmm zmm +// VPANDNQ zmm zmm k zmm +// VPANDNQ zmm zmm zmm +func VPANDNQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPANDNQ.Forms(), sffxs{}, ops) +} + +// VPANDNQ_BCST: Bitwise Logical AND NOT of Packed Quadword Integers (Broadcast). +// +// Forms: +// +// VPANDNQ.BCST m64 xmm k xmm +// VPANDNQ.BCST m64 xmm xmm +// VPANDNQ.BCST m64 ymm k ymm +// VPANDNQ.BCST m64 ymm ymm +// VPANDNQ.BCST m64 zmm k zmm +// VPANDNQ.BCST m64 zmm zmm +func VPANDNQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPANDNQ.Forms(), sffxs{sffxBCST}, ops) +} + +// VPANDNQ_BCST_Z: Bitwise Logical AND NOT of Packed Quadword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPANDNQ.BCST.Z m64 xmm k xmm +// VPANDNQ.BCST.Z m64 ymm k ymm +// VPANDNQ.BCST.Z m64 zmm k zmm +func VPANDNQ_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPANDNQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VPANDNQ_Z: Bitwise Logical AND NOT of Packed Quadword Integers (Zeroing Masking). +// +// Forms: +// +// VPANDNQ.Z m128 xmm k xmm +// VPANDNQ.Z m256 ymm k ymm +// VPANDNQ.Z xmm xmm k xmm +// VPANDNQ.Z ymm ymm k ymm +// VPANDNQ.Z m512 zmm k zmm +// VPANDNQ.Z zmm zmm k zmm +func VPANDNQ_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPANDNQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPANDQ: Bitwise Logical AND of Packed Quadword Integers. +// +// Forms: +// +// VPANDQ m128 xmm k xmm +// VPANDQ m128 xmm xmm +// VPANDQ m256 ymm k ymm +// VPANDQ m256 ymm ymm +// VPANDQ xmm xmm k xmm +// VPANDQ xmm xmm xmm +// VPANDQ ymm ymm k ymm +// VPANDQ ymm ymm ymm +// VPANDQ m512 zmm k zmm +// VPANDQ m512 zmm zmm +// VPANDQ zmm zmm k zmm +// VPANDQ zmm zmm zmm +func VPANDQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPANDQ.Forms(), sffxs{}, ops) +} + +// VPANDQ_BCST: Bitwise Logical AND of Packed Quadword Integers (Broadcast). +// +// Forms: +// +// VPANDQ.BCST m64 xmm k xmm +// VPANDQ.BCST m64 xmm xmm +// VPANDQ.BCST m64 ymm k ymm +// VPANDQ.BCST m64 ymm ymm +// VPANDQ.BCST m64 zmm k zmm +// VPANDQ.BCST m64 zmm zmm +func VPANDQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPANDQ.Forms(), sffxs{sffxBCST}, ops) +} + +// VPANDQ_BCST_Z: Bitwise Logical AND of Packed Quadword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPANDQ.BCST.Z m64 xmm k xmm +// VPANDQ.BCST.Z m64 ymm k ymm +// VPANDQ.BCST.Z m64 zmm k zmm +func VPANDQ_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPANDQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VPANDQ_Z: Bitwise Logical AND of Packed Quadword Integers (Zeroing Masking). +// +// Forms: +// +// VPANDQ.Z m128 xmm k xmm +// VPANDQ.Z m256 ymm k ymm +// VPANDQ.Z xmm xmm k xmm +// VPANDQ.Z ymm ymm k ymm +// VPANDQ.Z m512 zmm k zmm +// VPANDQ.Z zmm zmm k zmm +func VPANDQ_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPANDQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPAVGB: Average Packed Byte Integers. +// +// Forms: +// +// VPAVGB m256 ymm ymm +// VPAVGB ymm ymm ymm +// VPAVGB m128 xmm xmm +// VPAVGB xmm xmm xmm +// VPAVGB m128 xmm k xmm +// VPAVGB m256 ymm k ymm +// VPAVGB xmm xmm k xmm +// VPAVGB ymm ymm k ymm +// VPAVGB m512 zmm k zmm +// VPAVGB m512 zmm zmm +// VPAVGB zmm zmm k zmm +// VPAVGB zmm zmm zmm +func VPAVGB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPAVGB.Forms(), sffxs{}, ops) +} + +// VPAVGB_Z: Average Packed Byte Integers (Zeroing Masking). +// +// Forms: +// +// VPAVGB.Z m128 xmm k xmm +// VPAVGB.Z m256 ymm k ymm +// VPAVGB.Z xmm xmm k xmm +// VPAVGB.Z ymm ymm k ymm +// VPAVGB.Z m512 zmm k zmm +// VPAVGB.Z zmm zmm k zmm +func VPAVGB_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPAVGB.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPAVGW: Average Packed Word Integers. +// +// Forms: +// +// VPAVGW m256 ymm ymm +// VPAVGW ymm ymm ymm +// VPAVGW m128 xmm xmm +// VPAVGW xmm xmm xmm +// VPAVGW m128 xmm k xmm +// VPAVGW m256 ymm k ymm +// VPAVGW xmm xmm k xmm +// VPAVGW ymm ymm k ymm +// VPAVGW m512 zmm k zmm +// VPAVGW m512 zmm zmm +// VPAVGW zmm zmm k zmm +// VPAVGW zmm zmm zmm +func VPAVGW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPAVGW.Forms(), sffxs{}, ops) +} + +// VPAVGW_Z: Average Packed Word Integers (Zeroing Masking). +// +// Forms: +// +// VPAVGW.Z m128 xmm k xmm +// VPAVGW.Z m256 ymm k ymm +// VPAVGW.Z xmm xmm k xmm +// VPAVGW.Z ymm ymm k ymm +// VPAVGW.Z m512 zmm k zmm +// VPAVGW.Z zmm zmm k zmm +func VPAVGW_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPAVGW.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPBLENDD: Blend Packed Doublewords. +// +// Forms: +// +// VPBLENDD imm8 m128 xmm xmm +// VPBLENDD imm8 m256 ymm ymm +// VPBLENDD imm8 xmm xmm xmm +// VPBLENDD imm8 ymm ymm ymm +func VPBLENDD(i, mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPBLENDD.Forms(), sffxs{}, []operand.Op{i, mxy, xy, xy1}) +} + +// VPBLENDMB: Blend Byte Vectors Using an OpMask Control. +// +// Forms: +// +// VPBLENDMB m128 xmm k xmm +// VPBLENDMB m128 xmm xmm +// VPBLENDMB m256 ymm k ymm +// VPBLENDMB m256 ymm ymm +// VPBLENDMB xmm xmm k xmm +// VPBLENDMB xmm xmm xmm +// VPBLENDMB ymm ymm k ymm +// VPBLENDMB ymm ymm ymm +// VPBLENDMB m512 zmm k zmm +// VPBLENDMB m512 zmm zmm +// VPBLENDMB zmm zmm k zmm +// VPBLENDMB zmm zmm zmm +func VPBLENDMB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPBLENDMB.Forms(), sffxs{}, ops) +} + +// VPBLENDMB_Z: Blend Byte Vectors Using an OpMask Control (Zeroing Masking). +// +// Forms: +// +// VPBLENDMB.Z m128 xmm k xmm +// VPBLENDMB.Z m256 ymm k ymm +// VPBLENDMB.Z xmm xmm k xmm +// VPBLENDMB.Z ymm ymm k ymm +// VPBLENDMB.Z m512 zmm k zmm +// VPBLENDMB.Z zmm zmm k zmm +func VPBLENDMB_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPBLENDMB.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPBLENDMD: Blend Doubleword Vectors Using an OpMask Control. +// +// Forms: +// +// VPBLENDMD m128 xmm k xmm +// VPBLENDMD m128 xmm xmm +// VPBLENDMD m256 ymm k ymm +// VPBLENDMD m256 ymm ymm +// VPBLENDMD xmm xmm k xmm +// VPBLENDMD xmm xmm xmm +// VPBLENDMD ymm ymm k ymm +// VPBLENDMD ymm ymm ymm +// VPBLENDMD m512 zmm k zmm +// VPBLENDMD m512 zmm zmm +// VPBLENDMD zmm zmm k zmm +// VPBLENDMD zmm zmm zmm +func VPBLENDMD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPBLENDMD.Forms(), sffxs{}, ops) +} + +// VPBLENDMD_BCST: Blend Doubleword Vectors Using an OpMask Control (Broadcast). +// +// Forms: +// +// VPBLENDMD.BCST m32 xmm k xmm +// VPBLENDMD.BCST m32 xmm xmm +// VPBLENDMD.BCST m32 ymm k ymm +// VPBLENDMD.BCST m32 ymm ymm +// VPBLENDMD.BCST m32 zmm k zmm +// VPBLENDMD.BCST m32 zmm zmm +func VPBLENDMD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPBLENDMD.Forms(), sffxs{sffxBCST}, ops) +} + +// VPBLENDMD_BCST_Z: Blend Doubleword Vectors Using an OpMask Control (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPBLENDMD.BCST.Z m32 xmm k xmm +// VPBLENDMD.BCST.Z m32 ymm k ymm +// VPBLENDMD.BCST.Z m32 zmm k zmm +func VPBLENDMD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPBLENDMD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VPBLENDMD_Z: Blend Doubleword Vectors Using an OpMask Control (Zeroing Masking). +// +// Forms: +// +// VPBLENDMD.Z m128 xmm k xmm +// VPBLENDMD.Z m256 ymm k ymm +// VPBLENDMD.Z xmm xmm k xmm +// VPBLENDMD.Z ymm ymm k ymm +// VPBLENDMD.Z m512 zmm k zmm +// VPBLENDMD.Z zmm zmm k zmm +func VPBLENDMD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPBLENDMD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPBLENDMQ: Blend Quadword Vectors Using an OpMask Control. +// +// Forms: +// +// VPBLENDMQ m128 xmm k xmm +// VPBLENDMQ m128 xmm xmm +// VPBLENDMQ m256 ymm k ymm +// VPBLENDMQ m256 ymm ymm +// VPBLENDMQ xmm xmm k xmm +// VPBLENDMQ xmm xmm xmm +// VPBLENDMQ ymm ymm k ymm +// VPBLENDMQ ymm ymm ymm +// VPBLENDMQ m512 zmm k zmm +// VPBLENDMQ m512 zmm zmm +// VPBLENDMQ zmm zmm k zmm +// VPBLENDMQ zmm zmm zmm +func VPBLENDMQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPBLENDMQ.Forms(), sffxs{}, ops) +} + +// VPBLENDMQ_BCST: Blend Quadword Vectors Using an OpMask Control (Broadcast). +// +// Forms: +// +// VPBLENDMQ.BCST m64 xmm k xmm +// VPBLENDMQ.BCST m64 xmm xmm +// VPBLENDMQ.BCST m64 ymm k ymm +// VPBLENDMQ.BCST m64 ymm ymm +// VPBLENDMQ.BCST m64 zmm k zmm +// VPBLENDMQ.BCST m64 zmm zmm +func VPBLENDMQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPBLENDMQ.Forms(), sffxs{sffxBCST}, ops) +} + +// VPBLENDMQ_BCST_Z: Blend Quadword Vectors Using an OpMask Control (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPBLENDMQ.BCST.Z m64 xmm k xmm +// VPBLENDMQ.BCST.Z m64 ymm k ymm +// VPBLENDMQ.BCST.Z m64 zmm k zmm +func VPBLENDMQ_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPBLENDMQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VPBLENDMQ_Z: Blend Quadword Vectors Using an OpMask Control (Zeroing Masking). +// +// Forms: +// +// VPBLENDMQ.Z m128 xmm k xmm +// VPBLENDMQ.Z m256 ymm k ymm +// VPBLENDMQ.Z xmm xmm k xmm +// VPBLENDMQ.Z ymm ymm k ymm +// VPBLENDMQ.Z m512 zmm k zmm +// VPBLENDMQ.Z zmm zmm k zmm +func VPBLENDMQ_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPBLENDMQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPBLENDMW: Blend Word Vectors Using an OpMask Control. +// +// Forms: +// +// VPBLENDMW m128 xmm k xmm +// VPBLENDMW m128 xmm xmm +// VPBLENDMW m256 ymm k ymm +// VPBLENDMW m256 ymm ymm +// VPBLENDMW xmm xmm k xmm +// VPBLENDMW xmm xmm xmm +// VPBLENDMW ymm ymm k ymm +// VPBLENDMW ymm ymm ymm +// VPBLENDMW m512 zmm k zmm +// VPBLENDMW m512 zmm zmm +// VPBLENDMW zmm zmm k zmm +// VPBLENDMW zmm zmm zmm +func VPBLENDMW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPBLENDMW.Forms(), sffxs{}, ops) +} + +// VPBLENDMW_Z: Blend Word Vectors Using an OpMask Control (Zeroing Masking). +// +// Forms: +// +// VPBLENDMW.Z m128 xmm k xmm +// VPBLENDMW.Z m256 ymm k ymm +// VPBLENDMW.Z xmm xmm k xmm +// VPBLENDMW.Z ymm ymm k ymm +// VPBLENDMW.Z m512 zmm k zmm +// VPBLENDMW.Z zmm zmm k zmm +func VPBLENDMW_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPBLENDMW.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPBLENDVB: Variable Blend Packed Bytes. +// +// Forms: +// +// VPBLENDVB ymm m256 ymm ymm +// VPBLENDVB ymm ymm ymm ymm +// VPBLENDVB xmm m128 xmm xmm +// VPBLENDVB xmm xmm xmm xmm +func VPBLENDVB(xy, mxy, xy1, xy2 operand.Op) (*intrep.Instruction, error) { + return build(opcVPBLENDVB.Forms(), sffxs{}, []operand.Op{xy, mxy, xy1, xy2}) +} + +// VPBLENDW: Blend Packed Words. +// +// Forms: +// +// VPBLENDW imm8 m256 ymm ymm +// VPBLENDW imm8 ymm ymm ymm +// VPBLENDW imm8 m128 xmm xmm +// VPBLENDW imm8 xmm xmm xmm +func VPBLENDW(i, mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPBLENDW.Forms(), sffxs{}, []operand.Op{i, mxy, xy, xy1}) +} + +// VPBROADCASTB: Broadcast Byte Integer. +// +// Forms: +// +// VPBROADCASTB m8 xmm +// VPBROADCASTB m8 ymm +// VPBROADCASTB xmm xmm +// VPBROADCASTB xmm ymm +// VPBROADCASTB m8 k xmm +// VPBROADCASTB m8 k ymm +// VPBROADCASTB r32 k xmm +// VPBROADCASTB r32 k ymm +// VPBROADCASTB r32 xmm +// VPBROADCASTB r32 ymm +// VPBROADCASTB xmm k xmm +// VPBROADCASTB xmm k ymm +// VPBROADCASTB m8 k zmm +// VPBROADCASTB m8 zmm +// VPBROADCASTB r32 k zmm +// VPBROADCASTB r32 zmm +// VPBROADCASTB xmm k zmm +// VPBROADCASTB xmm zmm +func VPBROADCASTB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPBROADCASTB.Forms(), sffxs{}, ops) +} + +// VPBROADCASTB_Z: Broadcast Byte Integer (Zeroing Masking). +// +// Forms: +// +// VPBROADCASTB.Z m8 k xmm +// VPBROADCASTB.Z m8 k ymm +// VPBROADCASTB.Z r32 k xmm +// VPBROADCASTB.Z r32 k ymm +// VPBROADCASTB.Z xmm k xmm +// VPBROADCASTB.Z xmm k ymm +// VPBROADCASTB.Z m8 k zmm +// VPBROADCASTB.Z r32 k zmm +// VPBROADCASTB.Z xmm k zmm +func VPBROADCASTB_Z(mrx, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPBROADCASTB.Forms(), sffxs{sffxZ}, []operand.Op{mrx, k, xyz}) +} + +// VPBROADCASTD: Broadcast Doubleword Integer. +// +// Forms: +// +// VPBROADCASTD m32 xmm +// VPBROADCASTD m32 ymm +// VPBROADCASTD xmm xmm +// VPBROADCASTD xmm ymm +// VPBROADCASTD m32 k xmm +// VPBROADCASTD m32 k ymm +// VPBROADCASTD r32 k xmm +// VPBROADCASTD r32 k ymm +// VPBROADCASTD r32 xmm +// VPBROADCASTD r32 ymm +// VPBROADCASTD xmm k xmm +// VPBROADCASTD xmm k ymm +// VPBROADCASTD m32 k zmm +// VPBROADCASTD m32 zmm +// VPBROADCASTD r32 k zmm +// VPBROADCASTD r32 zmm +// VPBROADCASTD xmm k zmm +// VPBROADCASTD xmm zmm +func VPBROADCASTD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPBROADCASTD.Forms(), sffxs{}, ops) +} + +// VPBROADCASTD_Z: Broadcast Doubleword Integer (Zeroing Masking). +// +// Forms: +// +// VPBROADCASTD.Z m32 k xmm +// VPBROADCASTD.Z m32 k ymm +// VPBROADCASTD.Z r32 k xmm +// VPBROADCASTD.Z r32 k ymm +// VPBROADCASTD.Z xmm k xmm +// VPBROADCASTD.Z xmm k ymm +// VPBROADCASTD.Z m32 k zmm +// VPBROADCASTD.Z r32 k zmm +// VPBROADCASTD.Z xmm k zmm +func VPBROADCASTD_Z(mrx, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPBROADCASTD.Forms(), sffxs{sffxZ}, []operand.Op{mrx, k, xyz}) +} + +// VPBROADCASTMB2Q: Broadcast Low Byte of Mask Register to Packed Quadword Values. +// +// Forms: +// +// VPBROADCASTMB2Q k xmm +// VPBROADCASTMB2Q k ymm +// VPBROADCASTMB2Q k zmm +func VPBROADCASTMB2Q(k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPBROADCASTMB2Q.Forms(), sffxs{}, []operand.Op{k, xyz}) +} + +// VPBROADCASTMW2D: Broadcast Low Word of Mask Register to Packed Doubleword Values. +// +// Forms: +// +// VPBROADCASTMW2D k xmm +// VPBROADCASTMW2D k ymm +// VPBROADCASTMW2D k zmm +func VPBROADCASTMW2D(k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPBROADCASTMW2D.Forms(), sffxs{}, []operand.Op{k, xyz}) +} + +// VPBROADCASTQ: Broadcast Quadword Integer. +// +// Forms: +// +// VPBROADCASTQ m64 xmm +// VPBROADCASTQ m64 ymm +// VPBROADCASTQ xmm xmm +// VPBROADCASTQ xmm ymm +// VPBROADCASTQ m64 k xmm +// VPBROADCASTQ m64 k ymm +// VPBROADCASTQ r64 k xmm +// VPBROADCASTQ r64 k ymm +// VPBROADCASTQ r64 xmm +// VPBROADCASTQ r64 ymm +// VPBROADCASTQ xmm k xmm +// VPBROADCASTQ xmm k ymm +// VPBROADCASTQ m64 k zmm +// VPBROADCASTQ m64 zmm +// VPBROADCASTQ r64 k zmm +// VPBROADCASTQ r64 zmm +// VPBROADCASTQ xmm k zmm +// VPBROADCASTQ xmm zmm +func VPBROADCASTQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPBROADCASTQ.Forms(), sffxs{}, ops) +} + +// VPBROADCASTQ_Z: Broadcast Quadword Integer (Zeroing Masking). +// +// Forms: +// +// VPBROADCASTQ.Z m64 k xmm +// VPBROADCASTQ.Z m64 k ymm +// VPBROADCASTQ.Z r64 k xmm +// VPBROADCASTQ.Z r64 k ymm +// VPBROADCASTQ.Z xmm k xmm +// VPBROADCASTQ.Z xmm k ymm +// VPBROADCASTQ.Z m64 k zmm +// VPBROADCASTQ.Z r64 k zmm +// VPBROADCASTQ.Z xmm k zmm +func VPBROADCASTQ_Z(mrx, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPBROADCASTQ.Forms(), sffxs{sffxZ}, []operand.Op{mrx, k, xyz}) +} + +// VPBROADCASTW: Broadcast Word Integer. +// +// Forms: +// +// VPBROADCASTW m16 xmm +// VPBROADCASTW m16 ymm +// VPBROADCASTW xmm xmm +// VPBROADCASTW xmm ymm +// VPBROADCASTW m16 k xmm +// VPBROADCASTW m16 k ymm +// VPBROADCASTW r32 k xmm +// VPBROADCASTW r32 k ymm +// VPBROADCASTW r32 xmm +// VPBROADCASTW r32 ymm +// VPBROADCASTW xmm k xmm +// VPBROADCASTW xmm k ymm +// VPBROADCASTW m16 k zmm +// VPBROADCASTW m16 zmm +// VPBROADCASTW r32 k zmm +// VPBROADCASTW r32 zmm +// VPBROADCASTW xmm k zmm +// VPBROADCASTW xmm zmm +func VPBROADCASTW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPBROADCASTW.Forms(), sffxs{}, ops) +} + +// VPBROADCASTW_Z: Broadcast Word Integer (Zeroing Masking). +// +// Forms: +// +// VPBROADCASTW.Z m16 k xmm +// VPBROADCASTW.Z m16 k ymm +// VPBROADCASTW.Z r32 k xmm +// VPBROADCASTW.Z r32 k ymm +// VPBROADCASTW.Z xmm k xmm +// VPBROADCASTW.Z xmm k ymm +// VPBROADCASTW.Z m16 k zmm +// VPBROADCASTW.Z r32 k zmm +// VPBROADCASTW.Z xmm k zmm +func VPBROADCASTW_Z(mrx, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPBROADCASTW.Forms(), sffxs{sffxZ}, []operand.Op{mrx, k, xyz}) +} + +// VPCLMULQDQ: Carry-Less Quadword Multiplication. +// +// Forms: +// +// VPCLMULQDQ imm8 m128 xmm xmm +// VPCLMULQDQ imm8 xmm xmm xmm +func VPCLMULQDQ(i, mx, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPCLMULQDQ.Forms(), sffxs{}, []operand.Op{i, mx, x, x1}) +} + +// VPCMPB: Compare Packed Signed Byte Values. +// +// Forms: +// +// VPCMPB imm8 m128 xmm k k +// VPCMPB imm8 m128 xmm k +// VPCMPB imm8 m256 ymm k k +// VPCMPB imm8 m256 ymm k +// VPCMPB imm8 xmm xmm k k +// VPCMPB imm8 xmm xmm k +// VPCMPB imm8 ymm ymm k k +// VPCMPB imm8 ymm ymm k +// VPCMPB imm8 m512 zmm k k +// VPCMPB imm8 m512 zmm k +// VPCMPB imm8 zmm zmm k k +// VPCMPB imm8 zmm zmm k +func VPCMPB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPCMPB.Forms(), sffxs{}, ops) +} + +// VPCMPD: Compare Packed Signed Doubleword Values. +// +// Forms: +// +// VPCMPD imm8 m128 xmm k k +// VPCMPD imm8 m128 xmm k +// VPCMPD imm8 m256 ymm k k +// VPCMPD imm8 m256 ymm k +// VPCMPD imm8 xmm xmm k k +// VPCMPD imm8 xmm xmm k +// VPCMPD imm8 ymm ymm k k +// VPCMPD imm8 ymm ymm k +// VPCMPD imm8 m512 zmm k k +// VPCMPD imm8 m512 zmm k +// VPCMPD imm8 zmm zmm k k +// VPCMPD imm8 zmm zmm k +func VPCMPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPCMPD.Forms(), sffxs{}, ops) +} + +// VPCMPD_BCST: Compare Packed Signed Doubleword Values (Broadcast). +// +// Forms: +// +// VPCMPD.BCST imm8 m32 xmm k k +// VPCMPD.BCST imm8 m32 xmm k +// VPCMPD.BCST imm8 m32 ymm k k +// VPCMPD.BCST imm8 m32 ymm k +// VPCMPD.BCST imm8 m32 zmm k k +// VPCMPD.BCST imm8 m32 zmm k +func VPCMPD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPCMPD.Forms(), sffxs{sffxBCST}, ops) +} + +// VPCMPEQB: Compare Packed Byte Data for Equality. +// +// Forms: +// +// VPCMPEQB m256 ymm ymm +// VPCMPEQB ymm ymm ymm +// VPCMPEQB m128 xmm xmm +// VPCMPEQB xmm xmm xmm +// VPCMPEQB m128 xmm k k +// VPCMPEQB m128 xmm k +// VPCMPEQB m256 ymm k k +// VPCMPEQB m256 ymm k +// VPCMPEQB xmm xmm k k +// VPCMPEQB xmm xmm k +// VPCMPEQB ymm ymm k k +// VPCMPEQB ymm ymm k +// VPCMPEQB m512 zmm k k +// VPCMPEQB m512 zmm k +// VPCMPEQB zmm zmm k k +// VPCMPEQB zmm zmm k +func VPCMPEQB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPCMPEQB.Forms(), sffxs{}, ops) +} + +// VPCMPEQD: Compare Packed Doubleword Data for Equality. +// +// Forms: +// +// VPCMPEQD m256 ymm ymm +// VPCMPEQD ymm ymm ymm +// VPCMPEQD m128 xmm xmm +// VPCMPEQD xmm xmm xmm +// VPCMPEQD m128 xmm k k +// VPCMPEQD m128 xmm k +// VPCMPEQD m256 ymm k k +// VPCMPEQD m256 ymm k +// VPCMPEQD xmm xmm k k +// VPCMPEQD xmm xmm k +// VPCMPEQD ymm ymm k k +// VPCMPEQD ymm ymm k +// VPCMPEQD m512 zmm k k +// VPCMPEQD m512 zmm k +// VPCMPEQD zmm zmm k k +// VPCMPEQD zmm zmm k +func VPCMPEQD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPCMPEQD.Forms(), sffxs{}, ops) +} + +// VPCMPEQD_BCST: Compare Packed Doubleword Data for Equality (Broadcast). +// +// Forms: +// +// VPCMPEQD.BCST m32 xmm k k +// VPCMPEQD.BCST m32 xmm k +// VPCMPEQD.BCST m32 ymm k k +// VPCMPEQD.BCST m32 ymm k +// VPCMPEQD.BCST m32 zmm k k +// VPCMPEQD.BCST m32 zmm k +func VPCMPEQD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPCMPEQD.Forms(), sffxs{sffxBCST}, ops) +} + +// VPCMPEQQ: Compare Packed Quadword Data for Equality. +// +// Forms: +// +// VPCMPEQQ m256 ymm ymm +// VPCMPEQQ ymm ymm ymm +// VPCMPEQQ m128 xmm xmm +// VPCMPEQQ xmm xmm xmm +// VPCMPEQQ m128 xmm k k +// VPCMPEQQ m128 xmm k +// VPCMPEQQ m256 ymm k k +// VPCMPEQQ m256 ymm k +// VPCMPEQQ xmm xmm k k +// VPCMPEQQ xmm xmm k +// VPCMPEQQ ymm ymm k k +// VPCMPEQQ ymm ymm k +// VPCMPEQQ m512 zmm k k +// VPCMPEQQ m512 zmm k +// VPCMPEQQ zmm zmm k k +// VPCMPEQQ zmm zmm k +func VPCMPEQQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPCMPEQQ.Forms(), sffxs{}, ops) +} + +// VPCMPEQQ_BCST: Compare Packed Quadword Data for Equality (Broadcast). +// +// Forms: +// +// VPCMPEQQ.BCST m64 xmm k k +// VPCMPEQQ.BCST m64 xmm k +// VPCMPEQQ.BCST m64 ymm k k +// VPCMPEQQ.BCST m64 ymm k +// VPCMPEQQ.BCST m64 zmm k k +// VPCMPEQQ.BCST m64 zmm k +func VPCMPEQQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPCMPEQQ.Forms(), sffxs{sffxBCST}, ops) +} + +// VPCMPEQW: Compare Packed Word Data for Equality. +// +// Forms: +// +// VPCMPEQW m256 ymm ymm +// VPCMPEQW ymm ymm ymm +// VPCMPEQW m128 xmm xmm +// VPCMPEQW xmm xmm xmm +// VPCMPEQW m128 xmm k k +// VPCMPEQW m128 xmm k +// VPCMPEQW m256 ymm k k +// VPCMPEQW m256 ymm k +// VPCMPEQW xmm xmm k k +// VPCMPEQW xmm xmm k +// VPCMPEQW ymm ymm k k +// VPCMPEQW ymm ymm k +// VPCMPEQW m512 zmm k k +// VPCMPEQW m512 zmm k +// VPCMPEQW zmm zmm k k +// VPCMPEQW zmm zmm k +func VPCMPEQW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPCMPEQW.Forms(), sffxs{}, ops) +} + +// VPCMPESTRI: Packed Compare Explicit Length Strings, Return Index. +// +// Forms: +// +// VPCMPESTRI imm8 m128 xmm +// VPCMPESTRI imm8 xmm xmm +func VPCMPESTRI(i, mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcVPCMPESTRI.Forms(), sffxs{}, []operand.Op{i, mx, x}) +} + +// VPCMPESTRM: Packed Compare Explicit Length Strings, Return Mask. +// +// Forms: +// +// VPCMPESTRM imm8 m128 xmm +// VPCMPESTRM imm8 xmm xmm +func VPCMPESTRM(i, mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcVPCMPESTRM.Forms(), sffxs{}, []operand.Op{i, mx, x}) +} + +// VPCMPGTB: Compare Packed Signed Byte Integers for Greater Than. +// +// Forms: +// +// VPCMPGTB m256 ymm ymm +// VPCMPGTB ymm ymm ymm +// VPCMPGTB m128 xmm xmm +// VPCMPGTB xmm xmm xmm +// VPCMPGTB m128 xmm k k +// VPCMPGTB m128 xmm k +// VPCMPGTB m256 ymm k k +// VPCMPGTB m256 ymm k +// VPCMPGTB xmm xmm k k +// VPCMPGTB xmm xmm k +// VPCMPGTB ymm ymm k k +// VPCMPGTB ymm ymm k +// VPCMPGTB m512 zmm k k +// VPCMPGTB m512 zmm k +// VPCMPGTB zmm zmm k k +// VPCMPGTB zmm zmm k +func VPCMPGTB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPCMPGTB.Forms(), sffxs{}, ops) +} + +// VPCMPGTD: Compare Packed Signed Doubleword Integers for Greater Than. +// +// Forms: +// +// VPCMPGTD m256 ymm ymm +// VPCMPGTD ymm ymm ymm +// VPCMPGTD m128 xmm xmm +// VPCMPGTD xmm xmm xmm +// VPCMPGTD m128 xmm k k +// VPCMPGTD m128 xmm k +// VPCMPGTD m256 ymm k k +// VPCMPGTD m256 ymm k +// VPCMPGTD xmm xmm k k +// VPCMPGTD xmm xmm k +// VPCMPGTD ymm ymm k k +// VPCMPGTD ymm ymm k +// VPCMPGTD m512 zmm k k +// VPCMPGTD m512 zmm k +// VPCMPGTD zmm zmm k k +// VPCMPGTD zmm zmm k +func VPCMPGTD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPCMPGTD.Forms(), sffxs{}, ops) +} + +// VPCMPGTD_BCST: Compare Packed Signed Doubleword Integers for Greater Than (Broadcast). +// +// Forms: +// +// VPCMPGTD.BCST m32 xmm k k +// VPCMPGTD.BCST m32 xmm k +// VPCMPGTD.BCST m32 ymm k k +// VPCMPGTD.BCST m32 ymm k +// VPCMPGTD.BCST m32 zmm k k +// VPCMPGTD.BCST m32 zmm k +func VPCMPGTD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPCMPGTD.Forms(), sffxs{sffxBCST}, ops) +} + +// VPCMPGTQ: Compare Packed Data for Greater Than. +// +// Forms: +// +// VPCMPGTQ m256 ymm ymm +// VPCMPGTQ ymm ymm ymm +// VPCMPGTQ m128 xmm xmm +// VPCMPGTQ xmm xmm xmm +// VPCMPGTQ m128 xmm k k +// VPCMPGTQ m128 xmm k +// VPCMPGTQ m256 ymm k k +// VPCMPGTQ m256 ymm k +// VPCMPGTQ xmm xmm k k +// VPCMPGTQ xmm xmm k +// VPCMPGTQ ymm ymm k k +// VPCMPGTQ ymm ymm k +// VPCMPGTQ m512 zmm k k +// VPCMPGTQ m512 zmm k +// VPCMPGTQ zmm zmm k k +// VPCMPGTQ zmm zmm k +func VPCMPGTQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPCMPGTQ.Forms(), sffxs{}, ops) +} + +// VPCMPGTQ_BCST: Compare Packed Data for Greater Than (Broadcast). +// +// Forms: +// +// VPCMPGTQ.BCST m64 xmm k k +// VPCMPGTQ.BCST m64 xmm k +// VPCMPGTQ.BCST m64 ymm k k +// VPCMPGTQ.BCST m64 ymm k +// VPCMPGTQ.BCST m64 zmm k k +// VPCMPGTQ.BCST m64 zmm k +func VPCMPGTQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPCMPGTQ.Forms(), sffxs{sffxBCST}, ops) +} + +// VPCMPGTW: Compare Packed Signed Word Integers for Greater Than. +// +// Forms: +// +// VPCMPGTW m256 ymm ymm +// VPCMPGTW ymm ymm ymm +// VPCMPGTW m128 xmm xmm +// VPCMPGTW xmm xmm xmm +// VPCMPGTW m128 xmm k k +// VPCMPGTW m128 xmm k +// VPCMPGTW m256 ymm k k +// VPCMPGTW m256 ymm k +// VPCMPGTW xmm xmm k k +// VPCMPGTW xmm xmm k +// VPCMPGTW ymm ymm k k +// VPCMPGTW ymm ymm k +// VPCMPGTW m512 zmm k k +// VPCMPGTW m512 zmm k +// VPCMPGTW zmm zmm k k +// VPCMPGTW zmm zmm k +func VPCMPGTW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPCMPGTW.Forms(), sffxs{}, ops) +} + +// VPCMPISTRI: Packed Compare Implicit Length Strings, Return Index. +// +// Forms: +// +// VPCMPISTRI imm8 m128 xmm +// VPCMPISTRI imm8 xmm xmm +func VPCMPISTRI(i, mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcVPCMPISTRI.Forms(), sffxs{}, []operand.Op{i, mx, x}) +} + +// VPCMPISTRM: Packed Compare Implicit Length Strings, Return Mask. +// +// Forms: +// +// VPCMPISTRM imm8 m128 xmm +// VPCMPISTRM imm8 xmm xmm +func VPCMPISTRM(i, mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcVPCMPISTRM.Forms(), sffxs{}, []operand.Op{i, mx, x}) +} + +// VPCMPQ: Compare Packed Signed Quadword Values. +// +// Forms: +// +// VPCMPQ imm8 m128 xmm k k +// VPCMPQ imm8 m128 xmm k +// VPCMPQ imm8 m256 ymm k k +// VPCMPQ imm8 m256 ymm k +// VPCMPQ imm8 xmm xmm k k +// VPCMPQ imm8 xmm xmm k +// VPCMPQ imm8 ymm ymm k k +// VPCMPQ imm8 ymm ymm k +// VPCMPQ imm8 m512 zmm k k +// VPCMPQ imm8 m512 zmm k +// VPCMPQ imm8 zmm zmm k k +// VPCMPQ imm8 zmm zmm k +func VPCMPQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPCMPQ.Forms(), sffxs{}, ops) +} + +// VPCMPQ_BCST: Compare Packed Signed Quadword Values (Broadcast). +// +// Forms: +// +// VPCMPQ.BCST imm8 m64 xmm k k +// VPCMPQ.BCST imm8 m64 xmm k +// VPCMPQ.BCST imm8 m64 ymm k k +// VPCMPQ.BCST imm8 m64 ymm k +// VPCMPQ.BCST imm8 m64 zmm k k +// VPCMPQ.BCST imm8 m64 zmm k +func VPCMPQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPCMPQ.Forms(), sffxs{sffxBCST}, ops) +} + +// VPCMPUB: Compare Packed Unsigned Byte Values. +// +// Forms: +// +// VPCMPUB imm8 m128 xmm k k +// VPCMPUB imm8 m128 xmm k +// VPCMPUB imm8 m256 ymm k k +// VPCMPUB imm8 m256 ymm k +// VPCMPUB imm8 xmm xmm k k +// VPCMPUB imm8 xmm xmm k +// VPCMPUB imm8 ymm ymm k k +// VPCMPUB imm8 ymm ymm k +// VPCMPUB imm8 m512 zmm k k +// VPCMPUB imm8 m512 zmm k +// VPCMPUB imm8 zmm zmm k k +// VPCMPUB imm8 zmm zmm k +func VPCMPUB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPCMPUB.Forms(), sffxs{}, ops) +} + +// VPCMPUD: Compare Packed Unsigned Doubleword Values. +// +// Forms: +// +// VPCMPUD imm8 m128 xmm k k +// VPCMPUD imm8 m128 xmm k +// VPCMPUD imm8 m256 ymm k k +// VPCMPUD imm8 m256 ymm k +// VPCMPUD imm8 xmm xmm k k +// VPCMPUD imm8 xmm xmm k +// VPCMPUD imm8 ymm ymm k k +// VPCMPUD imm8 ymm ymm k +// VPCMPUD imm8 m512 zmm k k +// VPCMPUD imm8 m512 zmm k +// VPCMPUD imm8 zmm zmm k k +// VPCMPUD imm8 zmm zmm k +func VPCMPUD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPCMPUD.Forms(), sffxs{}, ops) +} + +// VPCMPUD_BCST: Compare Packed Unsigned Doubleword Values (Broadcast). +// +// Forms: +// +// VPCMPUD.BCST imm8 m32 xmm k k +// VPCMPUD.BCST imm8 m32 xmm k +// VPCMPUD.BCST imm8 m32 ymm k k +// VPCMPUD.BCST imm8 m32 ymm k +// VPCMPUD.BCST imm8 m32 zmm k k +// VPCMPUD.BCST imm8 m32 zmm k +func VPCMPUD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPCMPUD.Forms(), sffxs{sffxBCST}, ops) +} + +// VPCMPUQ: Compare Packed Unsigned Quadword Values. +// +// Forms: +// +// VPCMPUQ imm8 m128 xmm k k +// VPCMPUQ imm8 m128 xmm k +// VPCMPUQ imm8 m256 ymm k k +// VPCMPUQ imm8 m256 ymm k +// VPCMPUQ imm8 xmm xmm k k +// VPCMPUQ imm8 xmm xmm k +// VPCMPUQ imm8 ymm ymm k k +// VPCMPUQ imm8 ymm ymm k +// VPCMPUQ imm8 m512 zmm k k +// VPCMPUQ imm8 m512 zmm k +// VPCMPUQ imm8 zmm zmm k k +// VPCMPUQ imm8 zmm zmm k +func VPCMPUQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPCMPUQ.Forms(), sffxs{}, ops) +} + +// VPCMPUQ_BCST: Compare Packed Unsigned Quadword Values (Broadcast). +// +// Forms: +// +// VPCMPUQ.BCST imm8 m64 xmm k k +// VPCMPUQ.BCST imm8 m64 xmm k +// VPCMPUQ.BCST imm8 m64 ymm k k +// VPCMPUQ.BCST imm8 m64 ymm k +// VPCMPUQ.BCST imm8 m64 zmm k k +// VPCMPUQ.BCST imm8 m64 zmm k +func VPCMPUQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPCMPUQ.Forms(), sffxs{sffxBCST}, ops) +} + +// VPCMPUW: Compare Packed Unsigned Word Values. +// +// Forms: +// +// VPCMPUW imm8 m128 xmm k k +// VPCMPUW imm8 m128 xmm k +// VPCMPUW imm8 m256 ymm k k +// VPCMPUW imm8 m256 ymm k +// VPCMPUW imm8 xmm xmm k k +// VPCMPUW imm8 xmm xmm k +// VPCMPUW imm8 ymm ymm k k +// VPCMPUW imm8 ymm ymm k +// VPCMPUW imm8 m512 zmm k k +// VPCMPUW imm8 m512 zmm k +// VPCMPUW imm8 zmm zmm k k +// VPCMPUW imm8 zmm zmm k +func VPCMPUW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPCMPUW.Forms(), sffxs{}, ops) +} + +// VPCMPW: Compare Packed Signed Word Values. +// +// Forms: +// +// VPCMPW imm8 m128 xmm k k +// VPCMPW imm8 m128 xmm k +// VPCMPW imm8 m256 ymm k k +// VPCMPW imm8 m256 ymm k +// VPCMPW imm8 xmm xmm k k +// VPCMPW imm8 xmm xmm k +// VPCMPW imm8 ymm ymm k k +// VPCMPW imm8 ymm ymm k +// VPCMPW imm8 m512 zmm k k +// VPCMPW imm8 m512 zmm k +// VPCMPW imm8 zmm zmm k k +// VPCMPW imm8 zmm zmm k +func VPCMPW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPCMPW.Forms(), sffxs{}, ops) +} + +// VPCOMPRESSD: Store Sparse Packed Doubleword Integer Values into Dense Memory/Register. +// +// Forms: +// +// VPCOMPRESSD xmm k m128 +// VPCOMPRESSD xmm k xmm +// VPCOMPRESSD xmm m128 +// VPCOMPRESSD xmm xmm +// VPCOMPRESSD ymm k m256 +// VPCOMPRESSD ymm k ymm +// VPCOMPRESSD ymm m256 +// VPCOMPRESSD ymm ymm +// VPCOMPRESSD zmm k m512 +// VPCOMPRESSD zmm k zmm +// VPCOMPRESSD zmm m512 +// VPCOMPRESSD zmm zmm +func VPCOMPRESSD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPCOMPRESSD.Forms(), sffxs{}, ops) +} + +// VPCOMPRESSD_Z: Store Sparse Packed Doubleword Integer Values into Dense Memory/Register (Zeroing Masking). +// +// Forms: +// +// VPCOMPRESSD.Z xmm k m128 +// VPCOMPRESSD.Z xmm k xmm +// VPCOMPRESSD.Z ymm k m256 +// VPCOMPRESSD.Z ymm k ymm +// VPCOMPRESSD.Z zmm k m512 +// VPCOMPRESSD.Z zmm k zmm +func VPCOMPRESSD_Z(xyz, k, mxyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPCOMPRESSD.Forms(), sffxs{sffxZ}, []operand.Op{xyz, k, mxyz}) +} + +// VPCOMPRESSQ: Store Sparse Packed Quadword Integer Values into Dense Memory/Register. +// +// Forms: +// +// VPCOMPRESSQ xmm k m128 +// VPCOMPRESSQ xmm k xmm +// VPCOMPRESSQ xmm m128 +// VPCOMPRESSQ xmm xmm +// VPCOMPRESSQ ymm k m256 +// VPCOMPRESSQ ymm k ymm +// VPCOMPRESSQ ymm m256 +// VPCOMPRESSQ ymm ymm +// VPCOMPRESSQ zmm k m512 +// VPCOMPRESSQ zmm k zmm +// VPCOMPRESSQ zmm m512 +// VPCOMPRESSQ zmm zmm +func VPCOMPRESSQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPCOMPRESSQ.Forms(), sffxs{}, ops) +} + +// VPCOMPRESSQ_Z: Store Sparse Packed Quadword Integer Values into Dense Memory/Register (Zeroing Masking). +// +// Forms: +// +// VPCOMPRESSQ.Z xmm k m128 +// VPCOMPRESSQ.Z xmm k xmm +// VPCOMPRESSQ.Z ymm k m256 +// VPCOMPRESSQ.Z ymm k ymm +// VPCOMPRESSQ.Z zmm k m512 +// VPCOMPRESSQ.Z zmm k zmm +func VPCOMPRESSQ_Z(xyz, k, mxyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPCOMPRESSQ.Forms(), sffxs{sffxZ}, []operand.Op{xyz, k, mxyz}) +} + +// VPCONFLICTD: Detect Conflicts Within a Vector of Packed Doubleword Values into Dense Memory/Register. +// +// Forms: +// +// VPCONFLICTD m128 k xmm +// VPCONFLICTD m128 xmm +// VPCONFLICTD m256 k ymm +// VPCONFLICTD m256 ymm +// VPCONFLICTD xmm k xmm +// VPCONFLICTD xmm xmm +// VPCONFLICTD ymm k ymm +// VPCONFLICTD ymm ymm +// VPCONFLICTD m512 k zmm +// VPCONFLICTD m512 zmm +// VPCONFLICTD zmm k zmm +// VPCONFLICTD zmm zmm +func VPCONFLICTD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPCONFLICTD.Forms(), sffxs{}, ops) +} + +// VPCONFLICTD_BCST: Detect Conflicts Within a Vector of Packed Doubleword Values into Dense Memory/Register (Broadcast). +// +// Forms: +// +// VPCONFLICTD.BCST m32 k xmm +// VPCONFLICTD.BCST m32 k ymm +// VPCONFLICTD.BCST m32 xmm +// VPCONFLICTD.BCST m32 ymm +// VPCONFLICTD.BCST m32 k zmm +// VPCONFLICTD.BCST m32 zmm +func VPCONFLICTD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPCONFLICTD.Forms(), sffxs{sffxBCST}, ops) +} + +// VPCONFLICTD_BCST_Z: Detect Conflicts Within a Vector of Packed Doubleword Values into Dense Memory/Register (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPCONFLICTD.BCST.Z m32 k xmm +// VPCONFLICTD.BCST.Z m32 k ymm +// VPCONFLICTD.BCST.Z m32 k zmm +func VPCONFLICTD_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPCONFLICTD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) +} + +// VPCONFLICTD_Z: Detect Conflicts Within a Vector of Packed Doubleword Values into Dense Memory/Register (Zeroing Masking). +// +// Forms: +// +// VPCONFLICTD.Z m128 k xmm +// VPCONFLICTD.Z m256 k ymm +// VPCONFLICTD.Z xmm k xmm +// VPCONFLICTD.Z ymm k ymm +// VPCONFLICTD.Z m512 k zmm +// VPCONFLICTD.Z zmm k zmm +func VPCONFLICTD_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPCONFLICTD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) +} + +// VPCONFLICTQ: Detect Conflicts Within a Vector of Packed Quadword Values into Dense Memory/Register. +// +// Forms: +// +// VPCONFLICTQ m128 k xmm +// VPCONFLICTQ m128 xmm +// VPCONFLICTQ m256 k ymm +// VPCONFLICTQ m256 ymm +// VPCONFLICTQ xmm k xmm +// VPCONFLICTQ xmm xmm +// VPCONFLICTQ ymm k ymm +// VPCONFLICTQ ymm ymm +// VPCONFLICTQ m512 k zmm +// VPCONFLICTQ m512 zmm +// VPCONFLICTQ zmm k zmm +// VPCONFLICTQ zmm zmm +func VPCONFLICTQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPCONFLICTQ.Forms(), sffxs{}, ops) +} + +// VPCONFLICTQ_BCST: Detect Conflicts Within a Vector of Packed Quadword Values into Dense Memory/Register (Broadcast). +// +// Forms: +// +// VPCONFLICTQ.BCST m64 k xmm +// VPCONFLICTQ.BCST m64 k ymm +// VPCONFLICTQ.BCST m64 xmm +// VPCONFLICTQ.BCST m64 ymm +// VPCONFLICTQ.BCST m64 k zmm +// VPCONFLICTQ.BCST m64 zmm +func VPCONFLICTQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPCONFLICTQ.Forms(), sffxs{sffxBCST}, ops) +} + +// VPCONFLICTQ_BCST_Z: Detect Conflicts Within a Vector of Packed Quadword Values into Dense Memory/Register (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPCONFLICTQ.BCST.Z m64 k xmm +// VPCONFLICTQ.BCST.Z m64 k ymm +// VPCONFLICTQ.BCST.Z m64 k zmm +func VPCONFLICTQ_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPCONFLICTQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) +} + +// VPCONFLICTQ_Z: Detect Conflicts Within a Vector of Packed Quadword Values into Dense Memory/Register (Zeroing Masking). +// +// Forms: +// +// VPCONFLICTQ.Z m128 k xmm +// VPCONFLICTQ.Z m256 k ymm +// VPCONFLICTQ.Z xmm k xmm +// VPCONFLICTQ.Z ymm k ymm +// VPCONFLICTQ.Z m512 k zmm +// VPCONFLICTQ.Z zmm k zmm +func VPCONFLICTQ_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPCONFLICTQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) +} + +// VPERM2F128: Permute Floating-Point Values. +// +// Forms: +// +// VPERM2F128 imm8 m256 ymm ymm +// VPERM2F128 imm8 ymm ymm ymm +func VPERM2F128(i, my, y, y1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPERM2F128.Forms(), sffxs{}, []operand.Op{i, my, y, y1}) +} + +// VPERM2I128: Permute 128-Bit Integer Values. +// +// Forms: +// +// VPERM2I128 imm8 m256 ymm ymm +// VPERM2I128 imm8 ymm ymm ymm +func VPERM2I128(i, my, y, y1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPERM2I128.Forms(), sffxs{}, []operand.Op{i, my, y, y1}) +} + +// VPERMB: Permute Byte Integers. +// +// Forms: +// +// VPERMB m128 xmm k xmm +// VPERMB m128 xmm xmm +// VPERMB m256 ymm k ymm +// VPERMB m256 ymm ymm +// VPERMB xmm xmm k xmm +// VPERMB xmm xmm xmm +// VPERMB ymm ymm k ymm +// VPERMB ymm ymm ymm +// VPERMB m512 zmm k zmm +// VPERMB m512 zmm zmm +// VPERMB zmm zmm k zmm +// VPERMB zmm zmm zmm +func VPERMB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMB.Forms(), sffxs{}, ops) +} + +// VPERMB_Z: Permute Byte Integers (Zeroing Masking). +// +// Forms: +// +// VPERMB.Z m128 xmm k xmm +// VPERMB.Z m256 ymm k ymm +// VPERMB.Z xmm xmm k xmm +// VPERMB.Z ymm ymm k ymm +// VPERMB.Z m512 zmm k zmm +// VPERMB.Z zmm zmm k zmm +func VPERMB_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMB.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPERMD: Permute Doubleword Integers. +// +// Forms: +// +// VPERMD m256 ymm ymm +// VPERMD ymm ymm ymm +// VPERMD m256 ymm k ymm +// VPERMD ymm ymm k ymm +// VPERMD m512 zmm k zmm +// VPERMD m512 zmm zmm +// VPERMD zmm zmm k zmm +// VPERMD zmm zmm zmm +func VPERMD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMD.Forms(), sffxs{}, ops) +} + +// VPERMD_BCST: Permute Doubleword Integers (Broadcast). +// +// Forms: +// +// VPERMD.BCST m32 ymm k ymm +// VPERMD.BCST m32 ymm ymm +// VPERMD.BCST m32 zmm k zmm +// VPERMD.BCST m32 zmm zmm +func VPERMD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMD.Forms(), sffxs{sffxBCST}, ops) +} + +// VPERMD_BCST_Z: Permute Doubleword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMD.BCST.Z m32 ymm k ymm +// VPERMD.BCST.Z m32 zmm k zmm +func VPERMD_BCST_Z(m, yz, k, yz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, yz, k, yz1}) +} + +// VPERMD_Z: Permute Doubleword Integers (Zeroing Masking). +// +// Forms: +// +// VPERMD.Z m256 ymm k ymm +// VPERMD.Z ymm ymm k ymm +// VPERMD.Z m512 zmm k zmm +// VPERMD.Z zmm zmm k zmm +func VPERMD_Z(myz, yz, k, yz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMD.Forms(), sffxs{sffxZ}, []operand.Op{myz, yz, k, yz1}) +} + +// VPERMI2B: Full Permute of Bytes From Two Tables Overwriting the Index. +// +// Forms: +// +// VPERMI2B m128 xmm k xmm +// VPERMI2B m128 xmm xmm +// VPERMI2B m256 ymm k ymm +// VPERMI2B m256 ymm ymm +// VPERMI2B xmm xmm k xmm +// VPERMI2B xmm xmm xmm +// VPERMI2B ymm ymm k ymm +// VPERMI2B ymm ymm ymm +// VPERMI2B m512 zmm k zmm +// VPERMI2B m512 zmm zmm +// VPERMI2B zmm zmm k zmm +// VPERMI2B zmm zmm zmm +func VPERMI2B(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMI2B.Forms(), sffxs{}, ops) +} + +// VPERMI2B_Z: Full Permute of Bytes From Two Tables Overwriting the Index (Zeroing Masking). +// +// Forms: +// +// VPERMI2B.Z m128 xmm k xmm +// VPERMI2B.Z m256 ymm k ymm +// VPERMI2B.Z xmm xmm k xmm +// VPERMI2B.Z ymm ymm k ymm +// VPERMI2B.Z m512 zmm k zmm +// VPERMI2B.Z zmm zmm k zmm +func VPERMI2B_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMI2B.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPERMI2D: Full Permute of Doublewords From Two Tables Overwriting the Index. +// +// Forms: +// +// VPERMI2D m128 xmm k xmm +// VPERMI2D m128 xmm xmm +// VPERMI2D m256 ymm k ymm +// VPERMI2D m256 ymm ymm +// VPERMI2D xmm xmm k xmm +// VPERMI2D xmm xmm xmm +// VPERMI2D ymm ymm k ymm +// VPERMI2D ymm ymm ymm +// VPERMI2D m512 zmm k zmm +// VPERMI2D m512 zmm zmm +// VPERMI2D zmm zmm k zmm +// VPERMI2D zmm zmm zmm +func VPERMI2D(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMI2D.Forms(), sffxs{}, ops) +} + +// VPERMI2D_BCST: Full Permute of Doublewords From Two Tables Overwriting the Index (Broadcast). +// +// Forms: +// +// VPERMI2D.BCST m32 xmm k xmm +// VPERMI2D.BCST m32 xmm xmm +// VPERMI2D.BCST m32 ymm k ymm +// VPERMI2D.BCST m32 ymm ymm +// VPERMI2D.BCST m32 zmm k zmm +// VPERMI2D.BCST m32 zmm zmm +func VPERMI2D_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMI2D.Forms(), sffxs{sffxBCST}, ops) +} + +// VPERMI2D_BCST_Z: Full Permute of Doublewords From Two Tables Overwriting the Index (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMI2D.BCST.Z m32 xmm k xmm +// VPERMI2D.BCST.Z m32 ymm k ymm +// VPERMI2D.BCST.Z m32 zmm k zmm +func VPERMI2D_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMI2D.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VPERMI2D_Z: Full Permute of Doublewords From Two Tables Overwriting the Index (Zeroing Masking). +// +// Forms: +// +// VPERMI2D.Z m128 xmm k xmm +// VPERMI2D.Z m256 ymm k ymm +// VPERMI2D.Z xmm xmm k xmm +// VPERMI2D.Z ymm ymm k ymm +// VPERMI2D.Z m512 zmm k zmm +// VPERMI2D.Z zmm zmm k zmm +func VPERMI2D_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMI2D.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPERMI2PD: Full Permute of Double-Precision Floating-Point Values From Two Tables Overwriting the Index. +// +// Forms: +// +// VPERMI2PD m128 xmm k xmm +// VPERMI2PD m128 xmm xmm +// VPERMI2PD m256 ymm k ymm +// VPERMI2PD m256 ymm ymm +// VPERMI2PD xmm xmm k xmm +// VPERMI2PD xmm xmm xmm +// VPERMI2PD ymm ymm k ymm +// VPERMI2PD ymm ymm ymm +// VPERMI2PD m512 zmm k zmm +// VPERMI2PD m512 zmm zmm +// VPERMI2PD zmm zmm k zmm +// VPERMI2PD zmm zmm zmm +func VPERMI2PD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMI2PD.Forms(), sffxs{}, ops) +} + +// VPERMI2PD_BCST: Full Permute of Double-Precision Floating-Point Values From Two Tables Overwriting the Index (Broadcast). +// +// Forms: +// +// VPERMI2PD.BCST m64 xmm k xmm +// VPERMI2PD.BCST m64 xmm xmm +// VPERMI2PD.BCST m64 ymm k ymm +// VPERMI2PD.BCST m64 ymm ymm +// VPERMI2PD.BCST m64 zmm k zmm +// VPERMI2PD.BCST m64 zmm zmm +func VPERMI2PD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMI2PD.Forms(), sffxs{sffxBCST}, ops) +} + +// VPERMI2PD_BCST_Z: Full Permute of Double-Precision Floating-Point Values From Two Tables Overwriting the Index (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMI2PD.BCST.Z m64 xmm k xmm +// VPERMI2PD.BCST.Z m64 ymm k ymm +// VPERMI2PD.BCST.Z m64 zmm k zmm +func VPERMI2PD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMI2PD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VPERMI2PD_Z: Full Permute of Double-Precision Floating-Point Values From Two Tables Overwriting the Index (Zeroing Masking). +// +// Forms: +// +// VPERMI2PD.Z m128 xmm k xmm +// VPERMI2PD.Z m256 ymm k ymm +// VPERMI2PD.Z xmm xmm k xmm +// VPERMI2PD.Z ymm ymm k ymm +// VPERMI2PD.Z m512 zmm k zmm +// VPERMI2PD.Z zmm zmm k zmm +func VPERMI2PD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMI2PD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPERMI2PS: Full Permute of Single-Precision Floating-Point Values From Two Tables Overwriting the Index. +// +// Forms: +// +// VPERMI2PS m128 xmm k xmm +// VPERMI2PS m128 xmm xmm +// VPERMI2PS m256 ymm k ymm +// VPERMI2PS m256 ymm ymm +// VPERMI2PS xmm xmm k xmm +// VPERMI2PS xmm xmm xmm +// VPERMI2PS ymm ymm k ymm +// VPERMI2PS ymm ymm ymm +// VPERMI2PS m512 zmm k zmm +// VPERMI2PS m512 zmm zmm +// VPERMI2PS zmm zmm k zmm +// VPERMI2PS zmm zmm zmm +func VPERMI2PS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMI2PS.Forms(), sffxs{}, ops) +} + +// VPERMI2PS_BCST: Full Permute of Single-Precision Floating-Point Values From Two Tables Overwriting the Index (Broadcast). +// +// Forms: +// +// VPERMI2PS.BCST m32 xmm k xmm +// VPERMI2PS.BCST m32 xmm xmm +// VPERMI2PS.BCST m32 ymm k ymm +// VPERMI2PS.BCST m32 ymm ymm +// VPERMI2PS.BCST m32 zmm k zmm +// VPERMI2PS.BCST m32 zmm zmm +func VPERMI2PS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMI2PS.Forms(), sffxs{sffxBCST}, ops) +} + +// VPERMI2PS_BCST_Z: Full Permute of Single-Precision Floating-Point Values From Two Tables Overwriting the Index (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMI2PS.BCST.Z m32 xmm k xmm +// VPERMI2PS.BCST.Z m32 ymm k ymm +// VPERMI2PS.BCST.Z m32 zmm k zmm +func VPERMI2PS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMI2PS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VPERMI2PS_Z: Full Permute of Single-Precision Floating-Point Values From Two Tables Overwriting the Index (Zeroing Masking). +// +// Forms: +// +// VPERMI2PS.Z m128 xmm k xmm +// VPERMI2PS.Z m256 ymm k ymm +// VPERMI2PS.Z xmm xmm k xmm +// VPERMI2PS.Z ymm ymm k ymm +// VPERMI2PS.Z m512 zmm k zmm +// VPERMI2PS.Z zmm zmm k zmm +func VPERMI2PS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMI2PS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPERMI2Q: Full Permute of Quadwords From Two Tables Overwriting the Index. +// +// Forms: +// +// VPERMI2Q m128 xmm k xmm +// VPERMI2Q m128 xmm xmm +// VPERMI2Q m256 ymm k ymm +// VPERMI2Q m256 ymm ymm +// VPERMI2Q xmm xmm k xmm +// VPERMI2Q xmm xmm xmm +// VPERMI2Q ymm ymm k ymm +// VPERMI2Q ymm ymm ymm +// VPERMI2Q m512 zmm k zmm +// VPERMI2Q m512 zmm zmm +// VPERMI2Q zmm zmm k zmm +// VPERMI2Q zmm zmm zmm +func VPERMI2Q(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMI2Q.Forms(), sffxs{}, ops) +} + +// VPERMI2Q_BCST: Full Permute of Quadwords From Two Tables Overwriting the Index (Broadcast). +// +// Forms: +// +// VPERMI2Q.BCST m64 xmm k xmm +// VPERMI2Q.BCST m64 xmm xmm +// VPERMI2Q.BCST m64 ymm k ymm +// VPERMI2Q.BCST m64 ymm ymm +// VPERMI2Q.BCST m64 zmm k zmm +// VPERMI2Q.BCST m64 zmm zmm +func VPERMI2Q_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMI2Q.Forms(), sffxs{sffxBCST}, ops) +} + +// VPERMI2Q_BCST_Z: Full Permute of Quadwords From Two Tables Overwriting the Index (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMI2Q.BCST.Z m64 xmm k xmm +// VPERMI2Q.BCST.Z m64 ymm k ymm +// VPERMI2Q.BCST.Z m64 zmm k zmm +func VPERMI2Q_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMI2Q.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VPERMI2Q_Z: Full Permute of Quadwords From Two Tables Overwriting the Index (Zeroing Masking). +// +// Forms: +// +// VPERMI2Q.Z m128 xmm k xmm +// VPERMI2Q.Z m256 ymm k ymm +// VPERMI2Q.Z xmm xmm k xmm +// VPERMI2Q.Z ymm ymm k ymm +// VPERMI2Q.Z m512 zmm k zmm +// VPERMI2Q.Z zmm zmm k zmm +func VPERMI2Q_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMI2Q.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPERMI2W: Full Permute of Words From Two Tables Overwriting the Index. +// +// Forms: +// +// VPERMI2W m128 xmm k xmm +// VPERMI2W m128 xmm xmm +// VPERMI2W m256 ymm k ymm +// VPERMI2W m256 ymm ymm +// VPERMI2W xmm xmm k xmm +// VPERMI2W xmm xmm xmm +// VPERMI2W ymm ymm k ymm +// VPERMI2W ymm ymm ymm +// VPERMI2W m512 zmm k zmm +// VPERMI2W m512 zmm zmm +// VPERMI2W zmm zmm k zmm +// VPERMI2W zmm zmm zmm +func VPERMI2W(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMI2W.Forms(), sffxs{}, ops) +} + +// VPERMI2W_Z: Full Permute of Words From Two Tables Overwriting the Index (Zeroing Masking). +// +// Forms: +// +// VPERMI2W.Z m128 xmm k xmm +// VPERMI2W.Z m256 ymm k ymm +// VPERMI2W.Z xmm xmm k xmm +// VPERMI2W.Z ymm ymm k ymm +// VPERMI2W.Z m512 zmm k zmm +// VPERMI2W.Z zmm zmm k zmm +func VPERMI2W_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMI2W.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPERMILPD: Permute Double-Precision Floating-Point Values. +// +// Forms: +// +// VPERMILPD imm8 m128 xmm +// VPERMILPD imm8 m256 ymm +// VPERMILPD imm8 xmm xmm +// VPERMILPD imm8 ymm ymm +// VPERMILPD m128 xmm xmm +// VPERMILPD m256 ymm ymm +// VPERMILPD xmm xmm xmm +// VPERMILPD ymm ymm ymm +// VPERMILPD imm8 m128 k xmm +// VPERMILPD imm8 m256 k ymm +// VPERMILPD imm8 xmm k xmm +// VPERMILPD imm8 ymm k ymm +// VPERMILPD m128 xmm k xmm +// VPERMILPD m256 ymm k ymm +// VPERMILPD xmm xmm k xmm +// VPERMILPD ymm ymm k ymm +// VPERMILPD imm8 m512 k zmm +// VPERMILPD imm8 m512 zmm +// VPERMILPD imm8 zmm k zmm +// VPERMILPD imm8 zmm zmm +// VPERMILPD m512 zmm k zmm +// VPERMILPD m512 zmm zmm +// VPERMILPD zmm zmm k zmm +// VPERMILPD zmm zmm zmm +func VPERMILPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMILPD.Forms(), sffxs{}, ops) +} + +// VPERMILPD_BCST: Permute Double-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VPERMILPD.BCST imm8 m64 k xmm +// VPERMILPD.BCST imm8 m64 k ymm +// VPERMILPD.BCST imm8 m64 xmm +// VPERMILPD.BCST imm8 m64 ymm +// VPERMILPD.BCST m64 xmm k xmm +// VPERMILPD.BCST m64 xmm xmm +// VPERMILPD.BCST m64 ymm k ymm +// VPERMILPD.BCST m64 ymm ymm +// VPERMILPD.BCST imm8 m64 k zmm +// VPERMILPD.BCST imm8 m64 zmm +// VPERMILPD.BCST m64 zmm k zmm +// VPERMILPD.BCST m64 zmm zmm +func VPERMILPD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMILPD.Forms(), sffxs{sffxBCST}, ops) +} + +// VPERMILPD_BCST_Z: Permute Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMILPD.BCST.Z imm8 m64 k xmm +// VPERMILPD.BCST.Z imm8 m64 k ymm +// VPERMILPD.BCST.Z m64 xmm k xmm +// VPERMILPD.BCST.Z m64 ymm k ymm +// VPERMILPD.BCST.Z imm8 m64 k zmm +// VPERMILPD.BCST.Z m64 zmm k zmm +func VPERMILPD_BCST_Z(im, mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMILPD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{im, mxyz, k, xyz}) +} + +// VPERMILPD_Z: Permute Double-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VPERMILPD.Z imm8 m128 k xmm +// VPERMILPD.Z imm8 m256 k ymm +// VPERMILPD.Z imm8 xmm k xmm +// VPERMILPD.Z imm8 ymm k ymm +// VPERMILPD.Z m128 xmm k xmm +// VPERMILPD.Z m256 ymm k ymm +// VPERMILPD.Z xmm xmm k xmm +// VPERMILPD.Z ymm ymm k ymm +// VPERMILPD.Z imm8 m512 k zmm +// VPERMILPD.Z imm8 zmm k zmm +// VPERMILPD.Z m512 zmm k zmm +// VPERMILPD.Z zmm zmm k zmm +func VPERMILPD_Z(imxyz, mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMILPD.Forms(), sffxs{sffxZ}, []operand.Op{imxyz, mxyz, k, xyz}) +} + +// VPERMILPS: Permute Single-Precision Floating-Point Values. +// +// Forms: +// +// VPERMILPS imm8 m128 xmm +// VPERMILPS imm8 m256 ymm +// VPERMILPS imm8 xmm xmm +// VPERMILPS imm8 ymm ymm +// VPERMILPS m128 xmm xmm +// VPERMILPS m256 ymm ymm +// VPERMILPS xmm xmm xmm +// VPERMILPS ymm ymm ymm +// VPERMILPS imm8 m128 k xmm +// VPERMILPS imm8 m256 k ymm +// VPERMILPS imm8 xmm k xmm +// VPERMILPS imm8 ymm k ymm +// VPERMILPS m128 xmm k xmm +// VPERMILPS m256 ymm k ymm +// VPERMILPS xmm xmm k xmm +// VPERMILPS ymm ymm k ymm +// VPERMILPS imm8 m512 k zmm +// VPERMILPS imm8 m512 zmm +// VPERMILPS imm8 zmm k zmm +// VPERMILPS imm8 zmm zmm +// VPERMILPS m512 zmm k zmm +// VPERMILPS m512 zmm zmm +// VPERMILPS zmm zmm k zmm +// VPERMILPS zmm zmm zmm +func VPERMILPS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMILPS.Forms(), sffxs{}, ops) +} + +// VPERMILPS_BCST: Permute Single-Precision Floating-Point Values (Broadcast). +// +// Forms: +// +// VPERMILPS.BCST imm8 m32 k xmm +// VPERMILPS.BCST imm8 m32 k ymm +// VPERMILPS.BCST imm8 m32 xmm +// VPERMILPS.BCST imm8 m32 ymm +// VPERMILPS.BCST m32 xmm k xmm +// VPERMILPS.BCST m32 xmm xmm +// VPERMILPS.BCST m32 ymm k ymm +// VPERMILPS.BCST m32 ymm ymm +// VPERMILPS.BCST imm8 m32 k zmm +// VPERMILPS.BCST imm8 m32 zmm +// VPERMILPS.BCST m32 zmm k zmm +// VPERMILPS.BCST m32 zmm zmm +func VPERMILPS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMILPS.Forms(), sffxs{sffxBCST}, ops) +} + +// VPERMILPS_BCST_Z: Permute Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMILPS.BCST.Z imm8 m32 k xmm +// VPERMILPS.BCST.Z imm8 m32 k ymm +// VPERMILPS.BCST.Z m32 xmm k xmm +// VPERMILPS.BCST.Z m32 ymm k ymm +// VPERMILPS.BCST.Z imm8 m32 k zmm +// VPERMILPS.BCST.Z m32 zmm k zmm +func VPERMILPS_BCST_Z(im, mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMILPS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{im, mxyz, k, xyz}) +} + +// VPERMILPS_Z: Permute Single-Precision Floating-Point Values (Zeroing Masking). +// +// Forms: +// +// VPERMILPS.Z imm8 m128 k xmm +// VPERMILPS.Z imm8 m256 k ymm +// VPERMILPS.Z imm8 xmm k xmm +// VPERMILPS.Z imm8 ymm k ymm +// VPERMILPS.Z m128 xmm k xmm +// VPERMILPS.Z m256 ymm k ymm +// VPERMILPS.Z xmm xmm k xmm +// VPERMILPS.Z ymm ymm k ymm +// VPERMILPS.Z imm8 m512 k zmm +// VPERMILPS.Z imm8 zmm k zmm +// VPERMILPS.Z m512 zmm k zmm +// VPERMILPS.Z zmm zmm k zmm +func VPERMILPS_Z(imxyz, mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMILPS.Forms(), sffxs{sffxZ}, []operand.Op{imxyz, mxyz, k, xyz}) +} + +// VPERMPD: Permute Double-Precision Floating-Point Elements. +// +// Forms: +// +// VPERMPD imm8 m256 ymm +// VPERMPD imm8 ymm ymm +// VPERMPD imm8 m256 k ymm +// VPERMPD imm8 ymm k ymm +// VPERMPD m256 ymm k ymm +// VPERMPD m256 ymm ymm +// VPERMPD ymm ymm k ymm +// VPERMPD ymm ymm ymm +// VPERMPD imm8 m512 k zmm +// VPERMPD imm8 m512 zmm +// VPERMPD imm8 zmm k zmm +// VPERMPD imm8 zmm zmm +// VPERMPD m512 zmm k zmm +// VPERMPD m512 zmm zmm +// VPERMPD zmm zmm k zmm +// VPERMPD zmm zmm zmm +func VPERMPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMPD.Forms(), sffxs{}, ops) +} + +// VPERMPD_BCST: Permute Double-Precision Floating-Point Elements (Broadcast). +// +// Forms: +// +// VPERMPD.BCST imm8 m64 k ymm +// VPERMPD.BCST imm8 m64 ymm +// VPERMPD.BCST m64 ymm k ymm +// VPERMPD.BCST m64 ymm ymm +// VPERMPD.BCST imm8 m64 k zmm +// VPERMPD.BCST imm8 m64 zmm +// VPERMPD.BCST m64 zmm k zmm +// VPERMPD.BCST m64 zmm zmm +func VPERMPD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMPD.Forms(), sffxs{sffxBCST}, ops) +} + +// VPERMPD_BCST_Z: Permute Double-Precision Floating-Point Elements (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMPD.BCST.Z imm8 m64 k ymm +// VPERMPD.BCST.Z m64 ymm k ymm +// VPERMPD.BCST.Z imm8 m64 k zmm +// VPERMPD.BCST.Z m64 zmm k zmm +func VPERMPD_BCST_Z(im, myz, k, yz operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMPD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{im, myz, k, yz}) +} + +// VPERMPD_Z: Permute Double-Precision Floating-Point Elements (Zeroing Masking). +// +// Forms: +// +// VPERMPD.Z imm8 m256 k ymm +// VPERMPD.Z imm8 ymm k ymm +// VPERMPD.Z m256 ymm k ymm +// VPERMPD.Z ymm ymm k ymm +// VPERMPD.Z imm8 m512 k zmm +// VPERMPD.Z imm8 zmm k zmm +// VPERMPD.Z m512 zmm k zmm +// VPERMPD.Z zmm zmm k zmm +func VPERMPD_Z(imyz, myz, k, yz operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMPD.Forms(), sffxs{sffxZ}, []operand.Op{imyz, myz, k, yz}) +} + +// VPERMPS: Permute Single-Precision Floating-Point Elements. +// +// Forms: +// +// VPERMPS m256 ymm ymm +// VPERMPS ymm ymm ymm +// VPERMPS m256 ymm k ymm +// VPERMPS ymm ymm k ymm +// VPERMPS m512 zmm k zmm +// VPERMPS m512 zmm zmm +// VPERMPS zmm zmm k zmm +// VPERMPS zmm zmm zmm +func VPERMPS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMPS.Forms(), sffxs{}, ops) +} + +// VPERMPS_BCST: Permute Single-Precision Floating-Point Elements (Broadcast). +// +// Forms: +// +// VPERMPS.BCST m32 ymm k ymm +// VPERMPS.BCST m32 ymm ymm +// VPERMPS.BCST m32 zmm k zmm +// VPERMPS.BCST m32 zmm zmm +func VPERMPS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMPS.Forms(), sffxs{sffxBCST}, ops) +} + +// VPERMPS_BCST_Z: Permute Single-Precision Floating-Point Elements (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMPS.BCST.Z m32 ymm k ymm +// VPERMPS.BCST.Z m32 zmm k zmm +func VPERMPS_BCST_Z(m, yz, k, yz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMPS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, yz, k, yz1}) +} + +// VPERMPS_Z: Permute Single-Precision Floating-Point Elements (Zeroing Masking). +// +// Forms: +// +// VPERMPS.Z m256 ymm k ymm +// VPERMPS.Z ymm ymm k ymm +// VPERMPS.Z m512 zmm k zmm +// VPERMPS.Z zmm zmm k zmm +func VPERMPS_Z(myz, yz, k, yz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMPS.Forms(), sffxs{sffxZ}, []operand.Op{myz, yz, k, yz1}) +} + +// VPERMQ: Permute Quadword Integers. +// +// Forms: +// +// VPERMQ imm8 m256 ymm +// VPERMQ imm8 ymm ymm +// VPERMQ imm8 m256 k ymm +// VPERMQ imm8 ymm k ymm +// VPERMQ m256 ymm k ymm +// VPERMQ m256 ymm ymm +// VPERMQ ymm ymm k ymm +// VPERMQ ymm ymm ymm +// VPERMQ imm8 m512 k zmm +// VPERMQ imm8 m512 zmm +// VPERMQ imm8 zmm k zmm +// VPERMQ imm8 zmm zmm +// VPERMQ m512 zmm k zmm +// VPERMQ m512 zmm zmm +// VPERMQ zmm zmm k zmm +// VPERMQ zmm zmm zmm +func VPERMQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMQ.Forms(), sffxs{}, ops) +} + +// VPERMQ_BCST: Permute Quadword Integers (Broadcast). +// +// Forms: +// +// VPERMQ.BCST imm8 m64 k ymm +// VPERMQ.BCST imm8 m64 ymm +// VPERMQ.BCST m64 ymm k ymm +// VPERMQ.BCST m64 ymm ymm +// VPERMQ.BCST imm8 m64 k zmm +// VPERMQ.BCST imm8 m64 zmm +// VPERMQ.BCST m64 zmm k zmm +// VPERMQ.BCST m64 zmm zmm +func VPERMQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMQ.Forms(), sffxs{sffxBCST}, ops) +} + +// VPERMQ_BCST_Z: Permute Quadword Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMQ.BCST.Z imm8 m64 k ymm +// VPERMQ.BCST.Z m64 ymm k ymm +// VPERMQ.BCST.Z imm8 m64 k zmm +// VPERMQ.BCST.Z m64 zmm k zmm +func VPERMQ_BCST_Z(im, myz, k, yz operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{im, myz, k, yz}) +} + +// VPERMQ_Z: Permute Quadword Integers (Zeroing Masking). +// +// Forms: +// +// VPERMQ.Z imm8 m256 k ymm +// VPERMQ.Z imm8 ymm k ymm +// VPERMQ.Z m256 ymm k ymm +// VPERMQ.Z ymm ymm k ymm +// VPERMQ.Z imm8 m512 k zmm +// VPERMQ.Z imm8 zmm k zmm +// VPERMQ.Z m512 zmm k zmm +// VPERMQ.Z zmm zmm k zmm +func VPERMQ_Z(imyz, myz, k, yz operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMQ.Forms(), sffxs{sffxZ}, []operand.Op{imyz, myz, k, yz}) +} + +// VPERMT2B: Full Permute of Bytes From Two Tables Overwriting a Table. +// +// Forms: +// +// VPERMT2B m128 xmm k xmm +// VPERMT2B m128 xmm xmm +// VPERMT2B m256 ymm k ymm +// VPERMT2B m256 ymm ymm +// VPERMT2B xmm xmm k xmm +// VPERMT2B xmm xmm xmm +// VPERMT2B ymm ymm k ymm +// VPERMT2B ymm ymm ymm +// VPERMT2B m512 zmm k zmm +// VPERMT2B m512 zmm zmm +// VPERMT2B zmm zmm k zmm +// VPERMT2B zmm zmm zmm +func VPERMT2B(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMT2B.Forms(), sffxs{}, ops) +} + +// VPERMT2B_Z: Full Permute of Bytes From Two Tables Overwriting a Table (Zeroing Masking). +// +// Forms: +// +// VPERMT2B.Z m128 xmm k xmm +// VPERMT2B.Z m256 ymm k ymm +// VPERMT2B.Z xmm xmm k xmm +// VPERMT2B.Z ymm ymm k ymm +// VPERMT2B.Z m512 zmm k zmm +// VPERMT2B.Z zmm zmm k zmm +func VPERMT2B_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMT2B.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPERMT2D: Full Permute of Doublewords From Two Tables Overwriting a Table. +// +// Forms: +// +// VPERMT2D m128 xmm k xmm +// VPERMT2D m128 xmm xmm +// VPERMT2D m256 ymm k ymm +// VPERMT2D m256 ymm ymm +// VPERMT2D xmm xmm k xmm +// VPERMT2D xmm xmm xmm +// VPERMT2D ymm ymm k ymm +// VPERMT2D ymm ymm ymm +// VPERMT2D m512 zmm k zmm +// VPERMT2D m512 zmm zmm +// VPERMT2D zmm zmm k zmm +// VPERMT2D zmm zmm zmm +func VPERMT2D(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMT2D.Forms(), sffxs{}, ops) +} + +// VPERMT2D_BCST: Full Permute of Doublewords From Two Tables Overwriting a Table (Broadcast). +// +// Forms: +// +// VPERMT2D.BCST m32 xmm k xmm +// VPERMT2D.BCST m32 xmm xmm +// VPERMT2D.BCST m32 ymm k ymm +// VPERMT2D.BCST m32 ymm ymm +// VPERMT2D.BCST m32 zmm k zmm +// VPERMT2D.BCST m32 zmm zmm +func VPERMT2D_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMT2D.Forms(), sffxs{sffxBCST}, ops) +} + +// VPERMT2D_BCST_Z: Full Permute of Doublewords From Two Tables Overwriting a Table (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMT2D.BCST.Z m32 xmm k xmm +// VPERMT2D.BCST.Z m32 ymm k ymm +// VPERMT2D.BCST.Z m32 zmm k zmm +func VPERMT2D_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMT2D.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VPERMT2D_Z: Full Permute of Doublewords From Two Tables Overwriting a Table (Zeroing Masking). +// +// Forms: +// +// VPERMT2D.Z m128 xmm k xmm +// VPERMT2D.Z m256 ymm k ymm +// VPERMT2D.Z xmm xmm k xmm +// VPERMT2D.Z ymm ymm k ymm +// VPERMT2D.Z m512 zmm k zmm +// VPERMT2D.Z zmm zmm k zmm +func VPERMT2D_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMT2D.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPERMT2PD: Full Permute of Double-Precision Floating-Point Values From Two Tables Overwriting a Table. +// +// Forms: +// +// VPERMT2PD m128 xmm k xmm +// VPERMT2PD m128 xmm xmm +// VPERMT2PD m256 ymm k ymm +// VPERMT2PD m256 ymm ymm +// VPERMT2PD xmm xmm k xmm +// VPERMT2PD xmm xmm xmm +// VPERMT2PD ymm ymm k ymm +// VPERMT2PD ymm ymm ymm +// VPERMT2PD m512 zmm k zmm +// VPERMT2PD m512 zmm zmm +// VPERMT2PD zmm zmm k zmm +// VPERMT2PD zmm zmm zmm +func VPERMT2PD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMT2PD.Forms(), sffxs{}, ops) +} + +// VPERMT2PD_BCST: Full Permute of Double-Precision Floating-Point Values From Two Tables Overwriting a Table (Broadcast). +// +// Forms: +// +// VPERMT2PD.BCST m64 xmm k xmm +// VPERMT2PD.BCST m64 xmm xmm +// VPERMT2PD.BCST m64 ymm k ymm +// VPERMT2PD.BCST m64 ymm ymm +// VPERMT2PD.BCST m64 zmm k zmm +// VPERMT2PD.BCST m64 zmm zmm +func VPERMT2PD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMT2PD.Forms(), sffxs{sffxBCST}, ops) +} + +// VPERMT2PD_BCST_Z: Full Permute of Double-Precision Floating-Point Values From Two Tables Overwriting a Table (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMT2PD.BCST.Z m64 xmm k xmm +// VPERMT2PD.BCST.Z m64 ymm k ymm +// VPERMT2PD.BCST.Z m64 zmm k zmm +func VPERMT2PD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMT2PD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VPERMT2PD_Z: Full Permute of Double-Precision Floating-Point Values From Two Tables Overwriting a Table (Zeroing Masking). +// +// Forms: +// +// VPERMT2PD.Z m128 xmm k xmm +// VPERMT2PD.Z m256 ymm k ymm +// VPERMT2PD.Z xmm xmm k xmm +// VPERMT2PD.Z ymm ymm k ymm +// VPERMT2PD.Z m512 zmm k zmm +// VPERMT2PD.Z zmm zmm k zmm +func VPERMT2PD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMT2PD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPERMT2PS: Full Permute of Single-Precision Floating-Point Values From Two Tables Overwriting a Table. +// +// Forms: +// +// VPERMT2PS m128 xmm k xmm +// VPERMT2PS m128 xmm xmm +// VPERMT2PS m256 ymm k ymm +// VPERMT2PS m256 ymm ymm +// VPERMT2PS xmm xmm k xmm +// VPERMT2PS xmm xmm xmm +// VPERMT2PS ymm ymm k ymm +// VPERMT2PS ymm ymm ymm +// VPERMT2PS m512 zmm k zmm +// VPERMT2PS m512 zmm zmm +// VPERMT2PS zmm zmm k zmm +// VPERMT2PS zmm zmm zmm +func VPERMT2PS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMT2PS.Forms(), sffxs{}, ops) +} + +// VPERMT2PS_BCST: Full Permute of Single-Precision Floating-Point Values From Two Tables Overwriting a Table (Broadcast). +// +// Forms: +// +// VPERMT2PS.BCST m32 xmm k xmm +// VPERMT2PS.BCST m32 xmm xmm +// VPERMT2PS.BCST m32 ymm k ymm +// VPERMT2PS.BCST m32 ymm ymm +// VPERMT2PS.BCST m32 zmm k zmm +// VPERMT2PS.BCST m32 zmm zmm +func VPERMT2PS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMT2PS.Forms(), sffxs{sffxBCST}, ops) +} + +// VPERMT2PS_BCST_Z: Full Permute of Single-Precision Floating-Point Values From Two Tables Overwriting a Table (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMT2PS.BCST.Z m32 xmm k xmm +// VPERMT2PS.BCST.Z m32 ymm k ymm +// VPERMT2PS.BCST.Z m32 zmm k zmm +func VPERMT2PS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMT2PS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VPERMT2PS_Z: Full Permute of Single-Precision Floating-Point Values From Two Tables Overwriting a Table (Zeroing Masking). +// +// Forms: +// +// VPERMT2PS.Z m128 xmm k xmm +// VPERMT2PS.Z m256 ymm k ymm +// VPERMT2PS.Z xmm xmm k xmm +// VPERMT2PS.Z ymm ymm k ymm +// VPERMT2PS.Z m512 zmm k zmm +// VPERMT2PS.Z zmm zmm k zmm +func VPERMT2PS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMT2PS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPERMT2Q: Full Permute of Quadwords From Two Tables Overwriting a Table. +// +// Forms: +// +// VPERMT2Q m128 xmm k xmm +// VPERMT2Q m128 xmm xmm +// VPERMT2Q m256 ymm k ymm +// VPERMT2Q m256 ymm ymm +// VPERMT2Q xmm xmm k xmm +// VPERMT2Q xmm xmm xmm +// VPERMT2Q ymm ymm k ymm +// VPERMT2Q ymm ymm ymm +// VPERMT2Q m512 zmm k zmm +// VPERMT2Q m512 zmm zmm +// VPERMT2Q zmm zmm k zmm +// VPERMT2Q zmm zmm zmm +func VPERMT2Q(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMT2Q.Forms(), sffxs{}, ops) +} + +// VPERMT2Q_BCST: Full Permute of Quadwords From Two Tables Overwriting a Table (Broadcast). +// +// Forms: +// +// VPERMT2Q.BCST m64 xmm k xmm +// VPERMT2Q.BCST m64 xmm xmm +// VPERMT2Q.BCST m64 ymm k ymm +// VPERMT2Q.BCST m64 ymm ymm +// VPERMT2Q.BCST m64 zmm k zmm +// VPERMT2Q.BCST m64 zmm zmm +func VPERMT2Q_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMT2Q.Forms(), sffxs{sffxBCST}, ops) +} + +// VPERMT2Q_BCST_Z: Full Permute of Quadwords From Two Tables Overwriting a Table (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPERMT2Q.BCST.Z m64 xmm k xmm +// VPERMT2Q.BCST.Z m64 ymm k ymm +// VPERMT2Q.BCST.Z m64 zmm k zmm +func VPERMT2Q_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMT2Q.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VPERMT2Q_Z: Full Permute of Quadwords From Two Tables Overwriting a Table (Zeroing Masking). +// +// Forms: +// +// VPERMT2Q.Z m128 xmm k xmm +// VPERMT2Q.Z m256 ymm k ymm +// VPERMT2Q.Z xmm xmm k xmm +// VPERMT2Q.Z ymm ymm k ymm +// VPERMT2Q.Z m512 zmm k zmm +// VPERMT2Q.Z zmm zmm k zmm +func VPERMT2Q_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMT2Q.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// MOVHPD: Move High Packed Double-Precision Floating-Point Value. +// VPERMT2W: Full Permute of Words From Two Tables Overwriting a Table. // // Forms: // -// MOVHPD m64 xmm -// MOVHPD xmm m64 -func MOVHPD(mx, mx1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM64(mx) && operand.IsXMM(mx1): - return &intrep.Instruction{ - Opcode: "MOVHPD", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx, mx1}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsXMM(mx) && operand.IsM64(mx1): - return &intrep.Instruction{ - Opcode: "MOVHPD", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("MOVHPD: bad operands") +// VPERMT2W m128 xmm k xmm +// VPERMT2W m128 xmm xmm +// VPERMT2W m256 ymm k ymm +// VPERMT2W m256 ymm ymm +// VPERMT2W xmm xmm k xmm +// VPERMT2W xmm xmm xmm +// VPERMT2W ymm ymm k ymm +// VPERMT2W ymm ymm ymm +// VPERMT2W m512 zmm k zmm +// VPERMT2W m512 zmm zmm +// VPERMT2W zmm zmm k zmm +// VPERMT2W zmm zmm zmm +func VPERMT2W(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMT2W.Forms(), sffxs{}, ops) } -// MOVHPS: Move High Packed Single-Precision Floating-Point Values. +// VPERMT2W_Z: Full Permute of Words From Two Tables Overwriting a Table (Zeroing Masking). // // Forms: // -// MOVHPS m64 xmm -// MOVHPS xmm m64 -func MOVHPS(mx, mx1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM64(mx) && operand.IsXMM(mx1): - return &intrep.Instruction{ - Opcode: "MOVHPS", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx, mx1}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE"}, - }, nil - case operand.IsXMM(mx) && operand.IsM64(mx1): - return &intrep.Instruction{ - Opcode: "MOVHPS", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("MOVHPS: bad operands") +// VPERMT2W.Z m128 xmm k xmm +// VPERMT2W.Z m256 ymm k ymm +// VPERMT2W.Z xmm xmm k xmm +// VPERMT2W.Z ymm ymm k ymm +// VPERMT2W.Z m512 zmm k zmm +// VPERMT2W.Z zmm zmm k zmm +func VPERMT2W_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMT2W.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// MOVL: Move. +// VPERMW: Permute Word Integers. // // Forms: // -// MOVL imm32 r32 -// MOVL r32 r32 -// MOVL m32 r32 -// MOVL imm32 m32 -// MOVL r32 m32 -func MOVL(imr, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM32(imr) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "MOVL", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR32(imr) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "MOVL", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{imr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM32(imr) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "MOVL", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{imr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM32(imr) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "MOVL", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR32(imr) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "MOVL", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{imr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("MOVL: bad operands") +// VPERMW m128 xmm k xmm +// VPERMW m128 xmm xmm +// VPERMW m256 ymm k ymm +// VPERMW m256 ymm ymm +// VPERMW xmm xmm k xmm +// VPERMW xmm xmm xmm +// VPERMW ymm ymm k ymm +// VPERMW ymm ymm ymm +// VPERMW m512 zmm k zmm +// VPERMW m512 zmm zmm +// VPERMW zmm zmm k zmm +// VPERMW zmm zmm zmm +func VPERMW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMW.Forms(), sffxs{}, ops) } -// MOVLHPS: Move Packed Single-Precision Floating-Point Values Low to High. +// VPERMW_Z: Permute Word Integers (Zeroing Masking). // // Forms: // -// MOVLHPS xmm xmm -func MOVLHPS(x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "MOVLHPS", - Operands: []operand.Op{x, x1}, - Inputs: []operand.Op{x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("MOVLHPS: bad operands") +// VPERMW.Z m128 xmm k xmm +// VPERMW.Z m256 ymm k ymm +// VPERMW.Z xmm xmm k xmm +// VPERMW.Z ymm ymm k ymm +// VPERMW.Z m512 zmm k zmm +// VPERMW.Z zmm zmm k zmm +func VPERMW_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPERMW.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// MOVLPD: Move Low Packed Double-Precision Floating-Point Value. +// VPEXPANDD: Load Sparse Packed Doubleword Integer Values from Dense Memory/Register. // // Forms: // -// MOVLPD m64 xmm -// MOVLPD xmm m64 -func MOVLPD(mx, mx1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM64(mx) && operand.IsXMM(mx1): - return &intrep.Instruction{ - Opcode: "MOVLPD", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx, mx1}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsXMM(mx) && operand.IsM64(mx1): - return &intrep.Instruction{ - Opcode: "MOVLPD", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("MOVLPD: bad operands") +// VPEXPANDD m128 k xmm +// VPEXPANDD m128 xmm +// VPEXPANDD m256 k ymm +// VPEXPANDD m256 ymm +// VPEXPANDD xmm k xmm +// VPEXPANDD xmm xmm +// VPEXPANDD ymm k ymm +// VPEXPANDD ymm ymm +// VPEXPANDD m512 k zmm +// VPEXPANDD m512 zmm +// VPEXPANDD zmm k zmm +// VPEXPANDD zmm zmm +func VPEXPANDD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPEXPANDD.Forms(), sffxs{}, ops) } -// MOVLPS: Move Low Packed Single-Precision Floating-Point Values. +// VPEXPANDD_Z: Load Sparse Packed Doubleword Integer Values from Dense Memory/Register (Zeroing Masking). // // Forms: // -// MOVLPS m64 xmm -// MOVLPS xmm m64 -func MOVLPS(mx, mx1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM64(mx) && operand.IsXMM(mx1): - return &intrep.Instruction{ - Opcode: "MOVLPS", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx, mx1}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE"}, - }, nil - case operand.IsXMM(mx) && operand.IsM64(mx1): - return &intrep.Instruction{ - Opcode: "MOVLPS", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("MOVLPS: bad operands") +// VPEXPANDD.Z m128 k xmm +// VPEXPANDD.Z m256 k ymm +// VPEXPANDD.Z xmm k xmm +// VPEXPANDD.Z ymm k ymm +// VPEXPANDD.Z m512 k zmm +// VPEXPANDD.Z zmm k zmm +func VPEXPANDD_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPEXPANDD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) } -// MOVLQSX: Move Doubleword to Quadword with Sign-Extension. +// VPEXPANDQ: Load Sparse Packed Quadword Integer Values from Dense Memory/Register. +// +// Forms: +// +// VPEXPANDQ m128 k xmm +// VPEXPANDQ m128 xmm +// VPEXPANDQ m256 k ymm +// VPEXPANDQ m256 ymm +// VPEXPANDQ xmm k xmm +// VPEXPANDQ xmm xmm +// VPEXPANDQ ymm k ymm +// VPEXPANDQ ymm ymm +// VPEXPANDQ m512 k zmm +// VPEXPANDQ m512 zmm +// VPEXPANDQ zmm k zmm +// VPEXPANDQ zmm zmm +func VPEXPANDQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPEXPANDQ.Forms(), sffxs{}, ops) +} + +// VPEXPANDQ_Z: Load Sparse Packed Quadword Integer Values from Dense Memory/Register (Zeroing Masking). +// +// Forms: +// +// VPEXPANDQ.Z m128 k xmm +// VPEXPANDQ.Z m256 k ymm +// VPEXPANDQ.Z xmm k xmm +// VPEXPANDQ.Z ymm k ymm +// VPEXPANDQ.Z m512 k zmm +// VPEXPANDQ.Z zmm k zmm +func VPEXPANDQ_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPEXPANDQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) +} + +// VPEXTRB: Extract Byte. +// +// Forms: +// +// VPEXTRB imm8 xmm m8 +// VPEXTRB imm8 xmm r32 +func VPEXTRB(i, x, mr operand.Op) (*intrep.Instruction, error) { + return build(opcVPEXTRB.Forms(), sffxs{}, []operand.Op{i, x, mr}) +} + +// VPEXTRD: Extract Doubleword. +// +// Forms: +// +// VPEXTRD imm8 xmm m32 +// VPEXTRD imm8 xmm r32 +func VPEXTRD(i, x, mr operand.Op) (*intrep.Instruction, error) { + return build(opcVPEXTRD.Forms(), sffxs{}, []operand.Op{i, x, mr}) +} + +// VPEXTRQ: Extract Quadword. +// +// Forms: +// +// VPEXTRQ imm8 xmm m64 +// VPEXTRQ imm8 xmm r64 +func VPEXTRQ(i, x, mr operand.Op) (*intrep.Instruction, error) { + return build(opcVPEXTRQ.Forms(), sffxs{}, []operand.Op{i, x, mr}) +} + +// VPEXTRW: Extract Word. +// +// Forms: +// +// VPEXTRW imm8 xmm m16 +// VPEXTRW imm8 xmm r32 +func VPEXTRW(i, x, mr operand.Op) (*intrep.Instruction, error) { + return build(opcVPEXTRW.Forms(), sffxs{}, []operand.Op{i, x, mr}) +} + +// VPGATHERDD: Gather Packed Doubleword Values Using Signed Doubleword Indices. +// +// Forms: +// +// VPGATHERDD xmm vm32x xmm +// VPGATHERDD ymm vm32y ymm +// VPGATHERDD vm32x k xmm +// VPGATHERDD vm32y k ymm +// VPGATHERDD vm32z k zmm +func VPGATHERDD(vxy, kv, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPGATHERDD.Forms(), sffxs{}, []operand.Op{vxy, kv, xyz}) +} + +// VPGATHERDQ: Gather Packed Quadword Values Using Signed Doubleword Indices. +// +// Forms: +// +// VPGATHERDQ xmm vm32x xmm +// VPGATHERDQ ymm vm32x ymm +// VPGATHERDQ vm32x k xmm +// VPGATHERDQ vm32x k ymm +// VPGATHERDQ vm32y k zmm +func VPGATHERDQ(vxy, kv, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPGATHERDQ.Forms(), sffxs{}, []operand.Op{vxy, kv, xyz}) +} + +// VPGATHERQD: Gather Packed Doubleword Values Using Signed Quadword Indices. +// +// Forms: +// +// VPGATHERQD xmm vm64x xmm +// VPGATHERQD xmm vm64y xmm +// VPGATHERQD vm64x k xmm +// VPGATHERQD vm64y k xmm +// VPGATHERQD vm64z k ymm +func VPGATHERQD(vx, kv, xy operand.Op) (*intrep.Instruction, error) { + return build(opcVPGATHERQD.Forms(), sffxs{}, []operand.Op{vx, kv, xy}) +} + +// VPGATHERQQ: Gather Packed Quadword Values Using Signed Quadword Indices. +// +// Forms: +// +// VPGATHERQQ xmm vm64x xmm +// VPGATHERQQ ymm vm64y ymm +// VPGATHERQQ vm64x k xmm +// VPGATHERQQ vm64y k ymm +// VPGATHERQQ vm64z k zmm +func VPGATHERQQ(vxy, kv, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPGATHERQQ.Forms(), sffxs{}, []operand.Op{vxy, kv, xyz}) +} + +// VPHADDD: Packed Horizontal Add Doubleword Integer. +// +// Forms: +// +// VPHADDD m256 ymm ymm +// VPHADDD ymm ymm ymm +// VPHADDD m128 xmm xmm +// VPHADDD xmm xmm xmm +func VPHADDD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPHADDD.Forms(), sffxs{}, []operand.Op{mxy, xy, xy1}) +} + +// VPHADDSW: Packed Horizontal Add Signed Word Integers with Signed Saturation. +// +// Forms: +// +// VPHADDSW m256 ymm ymm +// VPHADDSW ymm ymm ymm +// VPHADDSW m128 xmm xmm +// VPHADDSW xmm xmm xmm +func VPHADDSW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPHADDSW.Forms(), sffxs{}, []operand.Op{mxy, xy, xy1}) +} + +// VPHADDW: Packed Horizontal Add Word Integers. +// +// Forms: +// +// VPHADDW m256 ymm ymm +// VPHADDW ymm ymm ymm +// VPHADDW m128 xmm xmm +// VPHADDW xmm xmm xmm +func VPHADDW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPHADDW.Forms(), sffxs{}, []operand.Op{mxy, xy, xy1}) +} + +// VPHMINPOSUW: Packed Horizontal Minimum of Unsigned Word Integers. +// +// Forms: +// +// VPHMINPOSUW m128 xmm +// VPHMINPOSUW xmm xmm +func VPHMINPOSUW(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcVPHMINPOSUW.Forms(), sffxs{}, []operand.Op{mx, x}) +} + +// VPHSUBD: Packed Horizontal Subtract Doubleword Integers. +// +// Forms: +// +// VPHSUBD m256 ymm ymm +// VPHSUBD ymm ymm ymm +// VPHSUBD m128 xmm xmm +// VPHSUBD xmm xmm xmm +func VPHSUBD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPHSUBD.Forms(), sffxs{}, []operand.Op{mxy, xy, xy1}) +} + +// VPHSUBSW: Packed Horizontal Subtract Signed Word Integers with Signed Saturation. +// +// Forms: +// +// VPHSUBSW m256 ymm ymm +// VPHSUBSW ymm ymm ymm +// VPHSUBSW m128 xmm xmm +// VPHSUBSW xmm xmm xmm +func VPHSUBSW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPHSUBSW.Forms(), sffxs{}, []operand.Op{mxy, xy, xy1}) +} + +// VPHSUBW: Packed Horizontal Subtract Word Integers. +// +// Forms: +// +// VPHSUBW m256 ymm ymm +// VPHSUBW ymm ymm ymm +// VPHSUBW m128 xmm xmm +// VPHSUBW xmm xmm xmm +func VPHSUBW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPHSUBW.Forms(), sffxs{}, []operand.Op{mxy, xy, xy1}) +} + +// VPINSRB: Insert Byte. +// +// Forms: +// +// VPINSRB imm8 m8 xmm xmm +// VPINSRB imm8 r32 xmm xmm +func VPINSRB(i, mr, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPINSRB.Forms(), sffxs{}, []operand.Op{i, mr, x, x1}) +} + +// VPINSRD: Insert Doubleword. +// +// Forms: +// +// VPINSRD imm8 m32 xmm xmm +// VPINSRD imm8 r32 xmm xmm +func VPINSRD(i, mr, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPINSRD.Forms(), sffxs{}, []operand.Op{i, mr, x, x1}) +} + +// VPINSRQ: Insert Quadword. +// +// Forms: +// +// VPINSRQ imm8 m64 xmm xmm +// VPINSRQ imm8 r64 xmm xmm +func VPINSRQ(i, mr, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPINSRQ.Forms(), sffxs{}, []operand.Op{i, mr, x, x1}) +} + +// VPINSRW: Insert Word. +// +// Forms: +// +// VPINSRW imm8 m16 xmm xmm +// VPINSRW imm8 r32 xmm xmm +func VPINSRW(i, mr, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPINSRW.Forms(), sffxs{}, []operand.Op{i, mr, x, x1}) +} + +// VPLZCNTD: Count the Number of Leading Zero Bits for Packed Doubleword Values. +// +// Forms: +// +// VPLZCNTD m128 k xmm +// VPLZCNTD m128 xmm +// VPLZCNTD m256 k ymm +// VPLZCNTD m256 ymm +// VPLZCNTD xmm k xmm +// VPLZCNTD xmm xmm +// VPLZCNTD ymm k ymm +// VPLZCNTD ymm ymm +// VPLZCNTD m512 k zmm +// VPLZCNTD m512 zmm +// VPLZCNTD zmm k zmm +// VPLZCNTD zmm zmm +func VPLZCNTD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPLZCNTD.Forms(), sffxs{}, ops) +} + +// VPLZCNTD_BCST: Count the Number of Leading Zero Bits for Packed Doubleword Values (Broadcast). +// +// Forms: +// +// VPLZCNTD.BCST m32 k xmm +// VPLZCNTD.BCST m32 k ymm +// VPLZCNTD.BCST m32 xmm +// VPLZCNTD.BCST m32 ymm +// VPLZCNTD.BCST m32 k zmm +// VPLZCNTD.BCST m32 zmm +func VPLZCNTD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPLZCNTD.Forms(), sffxs{sffxBCST}, ops) +} + +// VPLZCNTD_BCST_Z: Count the Number of Leading Zero Bits for Packed Doubleword Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPLZCNTD.BCST.Z m32 k xmm +// VPLZCNTD.BCST.Z m32 k ymm +// VPLZCNTD.BCST.Z m32 k zmm +func VPLZCNTD_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPLZCNTD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) +} + +// VPLZCNTD_Z: Count the Number of Leading Zero Bits for Packed Doubleword Values (Zeroing Masking). +// +// Forms: +// +// VPLZCNTD.Z m128 k xmm +// VPLZCNTD.Z m256 k ymm +// VPLZCNTD.Z xmm k xmm +// VPLZCNTD.Z ymm k ymm +// VPLZCNTD.Z m512 k zmm +// VPLZCNTD.Z zmm k zmm +func VPLZCNTD_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPLZCNTD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) +} + +// VPLZCNTQ: Count the Number of Leading Zero Bits for Packed Quadword Values. +// +// Forms: +// +// VPLZCNTQ m128 k xmm +// VPLZCNTQ m128 xmm +// VPLZCNTQ m256 k ymm +// VPLZCNTQ m256 ymm +// VPLZCNTQ xmm k xmm +// VPLZCNTQ xmm xmm +// VPLZCNTQ ymm k ymm +// VPLZCNTQ ymm ymm +// VPLZCNTQ m512 k zmm +// VPLZCNTQ m512 zmm +// VPLZCNTQ zmm k zmm +// VPLZCNTQ zmm zmm +func VPLZCNTQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPLZCNTQ.Forms(), sffxs{}, ops) +} + +// VPLZCNTQ_BCST: Count the Number of Leading Zero Bits for Packed Quadword Values (Broadcast). +// +// Forms: +// +// VPLZCNTQ.BCST m64 k xmm +// VPLZCNTQ.BCST m64 k ymm +// VPLZCNTQ.BCST m64 xmm +// VPLZCNTQ.BCST m64 ymm +// VPLZCNTQ.BCST m64 k zmm +// VPLZCNTQ.BCST m64 zmm +func VPLZCNTQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPLZCNTQ.Forms(), sffxs{sffxBCST}, ops) +} + +// VPLZCNTQ_BCST_Z: Count the Number of Leading Zero Bits for Packed Quadword Values (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPLZCNTQ.BCST.Z m64 k xmm +// VPLZCNTQ.BCST.Z m64 k ymm +// VPLZCNTQ.BCST.Z m64 k zmm +func VPLZCNTQ_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPLZCNTQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) +} + +// VPLZCNTQ_Z: Count the Number of Leading Zero Bits for Packed Quadword Values (Zeroing Masking). +// +// Forms: +// +// VPLZCNTQ.Z m128 k xmm +// VPLZCNTQ.Z m256 k ymm +// VPLZCNTQ.Z xmm k xmm +// VPLZCNTQ.Z ymm k ymm +// VPLZCNTQ.Z m512 k zmm +// VPLZCNTQ.Z zmm k zmm +func VPLZCNTQ_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPLZCNTQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) +} + +// VPMADD52HUQ: Packed Multiply of Unsigned 52-bit Unsigned Integers and Add High 52-bit Products to Quadword Accumulators. +// +// Forms: +// +// VPMADD52HUQ m128 xmm k xmm +// VPMADD52HUQ m128 xmm xmm +// VPMADD52HUQ m256 ymm k ymm +// VPMADD52HUQ m256 ymm ymm +// VPMADD52HUQ xmm xmm k xmm +// VPMADD52HUQ xmm xmm xmm +// VPMADD52HUQ ymm ymm k ymm +// VPMADD52HUQ ymm ymm ymm +// VPMADD52HUQ m512 zmm k zmm +// VPMADD52HUQ m512 zmm zmm +// VPMADD52HUQ zmm zmm k zmm +// VPMADD52HUQ zmm zmm zmm +func VPMADD52HUQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMADD52HUQ.Forms(), sffxs{}, ops) +} + +// VPMADD52HUQ_BCST: Packed Multiply of Unsigned 52-bit Unsigned Integers and Add High 52-bit Products to Quadword Accumulators (Broadcast). // // Forms: // -// MOVLQSX r32 r64 -// MOVLQSX m32 r64 -func MOVLQSX(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "MOVLQSX", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - case operand.IsM32(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "MOVLQSX", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - } - return nil, errors.New("MOVLQSX: bad operands") +// VPMADD52HUQ.BCST m64 xmm k xmm +// VPMADD52HUQ.BCST m64 xmm xmm +// VPMADD52HUQ.BCST m64 ymm k ymm +// VPMADD52HUQ.BCST m64 ymm ymm +// VPMADD52HUQ.BCST m64 zmm k zmm +// VPMADD52HUQ.BCST m64 zmm zmm +func VPMADD52HUQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMADD52HUQ.Forms(), sffxs{sffxBCST}, ops) } -// MOVLQZX: Move with Zero-Extend. +// VPMADD52HUQ_BCST_Z: Packed Multiply of Unsigned 52-bit Unsigned Integers and Add High 52-bit Products to Quadword Accumulators (Broadcast, Zeroing Masking). // // Forms: // -// MOVLQZX m32 r64 -func MOVLQZX(m, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM32(m) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "MOVLQZX", - Operands: []operand.Op{m, r}, - Inputs: []operand.Op{m}, - Outputs: []operand.Op{r}, - }, nil - } - return nil, errors.New("MOVLQZX: bad operands") +// VPMADD52HUQ.BCST.Z m64 xmm k xmm +// VPMADD52HUQ.BCST.Z m64 ymm k ymm +// VPMADD52HUQ.BCST.Z m64 zmm k zmm +func VPMADD52HUQ_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMADD52HUQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// MOVMSKPD: Extract Packed Double-Precision Floating-Point Sign Mask. +// VPMADD52HUQ_Z: Packed Multiply of Unsigned 52-bit Unsigned Integers and Add High 52-bit Products to Quadword Accumulators (Zeroing Masking). // // Forms: // -// MOVMSKPD xmm r32 -func MOVMSKPD(x, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(x) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "MOVMSKPD", - Operands: []operand.Op{x, r}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{r}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("MOVMSKPD: bad operands") +// VPMADD52HUQ.Z m128 xmm k xmm +// VPMADD52HUQ.Z m256 ymm k ymm +// VPMADD52HUQ.Z xmm xmm k xmm +// VPMADD52HUQ.Z ymm ymm k ymm +// VPMADD52HUQ.Z m512 zmm k zmm +// VPMADD52HUQ.Z zmm zmm k zmm +func VPMADD52HUQ_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMADD52HUQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// MOVMSKPS: Extract Packed Single-Precision Floating-Point Sign Mask. +// VPMADD52LUQ: Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit Products to Quadword Accumulators. // // Forms: // -// MOVMSKPS xmm r32 -func MOVMSKPS(x, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(x) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "MOVMSKPS", - Operands: []operand.Op{x, r}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{r}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("MOVMSKPS: bad operands") +// VPMADD52LUQ m128 xmm k xmm +// VPMADD52LUQ m128 xmm xmm +// VPMADD52LUQ m256 ymm k ymm +// VPMADD52LUQ m256 ymm ymm +// VPMADD52LUQ xmm xmm k xmm +// VPMADD52LUQ xmm xmm xmm +// VPMADD52LUQ ymm ymm k ymm +// VPMADD52LUQ ymm ymm ymm +// VPMADD52LUQ m512 zmm k zmm +// VPMADD52LUQ m512 zmm zmm +// VPMADD52LUQ zmm zmm k zmm +// VPMADD52LUQ zmm zmm zmm +func VPMADD52LUQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMADD52LUQ.Forms(), sffxs{}, ops) } -// MOVNTDQ: Store Double Quadword Using Non-Temporal Hint. +// VPMADD52LUQ_BCST: Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit Products to Quadword Accumulators (Broadcast). // // Forms: // -// MOVNTDQ xmm m128 -func MOVNTDQ(x, m operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(x) && operand.IsM128(m): - return &intrep.Instruction{ - Opcode: "MOVNTDQ", - Operands: []operand.Op{x, m}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{m}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("MOVNTDQ: bad operands") +// VPMADD52LUQ.BCST m64 xmm k xmm +// VPMADD52LUQ.BCST m64 xmm xmm +// VPMADD52LUQ.BCST m64 ymm k ymm +// VPMADD52LUQ.BCST m64 ymm ymm +// VPMADD52LUQ.BCST m64 zmm k zmm +// VPMADD52LUQ.BCST m64 zmm zmm +func VPMADD52LUQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMADD52LUQ.Forms(), sffxs{sffxBCST}, ops) } -// MOVNTDQA: Load Double Quadword Non-Temporal Aligned Hint. +// VPMADD52LUQ_BCST_Z: Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit Products to Quadword Accumulators (Broadcast, Zeroing Masking). // // Forms: // -// MOVNTDQA m128 xmm -func MOVNTDQA(m, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM128(m) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MOVNTDQA", - Operands: []operand.Op{m, x}, - Inputs: []operand.Op{m}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("MOVNTDQA: bad operands") +// VPMADD52LUQ.BCST.Z m64 xmm k xmm +// VPMADD52LUQ.BCST.Z m64 ymm k ymm +// VPMADD52LUQ.BCST.Z m64 zmm k zmm +func VPMADD52LUQ_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMADD52LUQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// MOVNTIL: Store Doubleword Using Non-Temporal Hint. +// VPMADD52LUQ_Z: Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit Products to Quadword Accumulators (Zeroing Masking). // // Forms: // -// MOVNTIL r32 m32 -func MOVNTIL(r, m operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(r) && operand.IsM32(m): - return &intrep.Instruction{ - Opcode: "MOVNTIL", - Operands: []operand.Op{r, m}, - Inputs: []operand.Op{r}, - Outputs: []operand.Op{m}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("MOVNTIL: bad operands") +// VPMADD52LUQ.Z m128 xmm k xmm +// VPMADD52LUQ.Z m256 ymm k ymm +// VPMADD52LUQ.Z xmm xmm k xmm +// VPMADD52LUQ.Z ymm ymm k ymm +// VPMADD52LUQ.Z m512 zmm k zmm +// VPMADD52LUQ.Z zmm zmm k zmm +func VPMADD52LUQ_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMADD52LUQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// MOVNTIQ: Store Doubleword Using Non-Temporal Hint. +// VPMADDUBSW: Multiply and Add Packed Signed and Unsigned Byte Integers. // // Forms: // -// MOVNTIQ r64 m64 -func MOVNTIQ(r, m operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(r) && operand.IsM64(m): - return &intrep.Instruction{ - Opcode: "MOVNTIQ", - Operands: []operand.Op{r, m}, - Inputs: []operand.Op{r}, - Outputs: []operand.Op{m}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("MOVNTIQ: bad operands") +// VPMADDUBSW m256 ymm ymm +// VPMADDUBSW ymm ymm ymm +// VPMADDUBSW m128 xmm xmm +// VPMADDUBSW xmm xmm xmm +// VPMADDUBSW m128 xmm k xmm +// VPMADDUBSW m256 ymm k ymm +// VPMADDUBSW xmm xmm k xmm +// VPMADDUBSW ymm ymm k ymm +// VPMADDUBSW m512 zmm k zmm +// VPMADDUBSW m512 zmm zmm +// VPMADDUBSW zmm zmm k zmm +// VPMADDUBSW zmm zmm zmm +func VPMADDUBSW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMADDUBSW.Forms(), sffxs{}, ops) } -// MOVNTO: Store Double Quadword Using Non-Temporal Hint. +// VPMADDUBSW_Z: Multiply and Add Packed Signed and Unsigned Byte Integers (Zeroing Masking). // // Forms: // -// MOVNTO xmm m128 -func MOVNTO(x, m operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(x) && operand.IsM128(m): - return &intrep.Instruction{ - Opcode: "MOVNTO", - Operands: []operand.Op{x, m}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{m}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("MOVNTO: bad operands") +// VPMADDUBSW.Z m128 xmm k xmm +// VPMADDUBSW.Z m256 ymm k ymm +// VPMADDUBSW.Z xmm xmm k xmm +// VPMADDUBSW.Z ymm ymm k ymm +// VPMADDUBSW.Z m512 zmm k zmm +// VPMADDUBSW.Z zmm zmm k zmm +func VPMADDUBSW_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMADDUBSW.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// MOVNTPD: Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint. +// VPMADDWD: Multiply and Add Packed Signed Word Integers. // // Forms: // -// MOVNTPD xmm m128 -func MOVNTPD(x, m operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(x) && operand.IsM128(m): - return &intrep.Instruction{ - Opcode: "MOVNTPD", - Operands: []operand.Op{x, m}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{m}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("MOVNTPD: bad operands") +// VPMADDWD m256 ymm ymm +// VPMADDWD ymm ymm ymm +// VPMADDWD m128 xmm xmm +// VPMADDWD xmm xmm xmm +// VPMADDWD m128 xmm k xmm +// VPMADDWD m256 ymm k ymm +// VPMADDWD xmm xmm k xmm +// VPMADDWD ymm ymm k ymm +// VPMADDWD m512 zmm k zmm +// VPMADDWD m512 zmm zmm +// VPMADDWD zmm zmm k zmm +// VPMADDWD zmm zmm zmm +func VPMADDWD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMADDWD.Forms(), sffxs{}, ops) } -// MOVNTPS: Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint. +// VPMADDWD_Z: Multiply and Add Packed Signed Word Integers (Zeroing Masking). // // Forms: // -// MOVNTPS xmm m128 -func MOVNTPS(x, m operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(x) && operand.IsM128(m): - return &intrep.Instruction{ - Opcode: "MOVNTPS", - Operands: []operand.Op{x, m}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{m}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("MOVNTPS: bad operands") +// VPMADDWD.Z m128 xmm k xmm +// VPMADDWD.Z m256 ymm k ymm +// VPMADDWD.Z xmm xmm k xmm +// VPMADDWD.Z ymm ymm k ymm +// VPMADDWD.Z m512 zmm k zmm +// VPMADDWD.Z zmm zmm k zmm +func VPMADDWD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMADDWD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// MOVO: Move Aligned Double Quadword. +// VPMASKMOVD: Conditional Move Packed Doubleword Integers. // // Forms: // -// MOVO xmm xmm -// MOVO m128 xmm -// MOVO xmm m128 -func MOVO(mx, mx1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(mx1): - return &intrep.Instruction{ - Opcode: "MOVO", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(mx1): - return &intrep.Instruction{ - Opcode: "MOVO", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsXMM(mx) && operand.IsM128(mx1): - return &intrep.Instruction{ - Opcode: "MOVO", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("MOVO: bad operands") +// VPMASKMOVD m128 xmm xmm +// VPMASKMOVD m256 ymm ymm +// VPMASKMOVD xmm xmm m128 +// VPMASKMOVD ymm ymm m256 +func VPMASKMOVD(mxy, xy, mxy1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMASKMOVD.Forms(), sffxs{}, []operand.Op{mxy, xy, mxy1}) } -// MOVOA: Move Aligned Double Quadword. +// VPMASKMOVQ: Conditional Move Packed Quadword Integers. // // Forms: // -// MOVOA xmm xmm -// MOVOA m128 xmm -// MOVOA xmm m128 -func MOVOA(mx, mx1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(mx1): - return &intrep.Instruction{ - Opcode: "MOVOA", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(mx1): - return &intrep.Instruction{ - Opcode: "MOVOA", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsXMM(mx) && operand.IsM128(mx1): - return &intrep.Instruction{ - Opcode: "MOVOA", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("MOVOA: bad operands") +// VPMASKMOVQ m128 xmm xmm +// VPMASKMOVQ m256 ymm ymm +// VPMASKMOVQ xmm xmm m128 +// VPMASKMOVQ ymm ymm m256 +func VPMASKMOVQ(mxy, xy, mxy1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMASKMOVQ.Forms(), sffxs{}, []operand.Op{mxy, xy, mxy1}) } -// MOVOU: Move Unaligned Double Quadword. +// VPMAXSB: Maximum of Packed Signed Byte Integers. // // Forms: // -// MOVOU xmm xmm -// MOVOU m128 xmm -// MOVOU xmm m128 -func MOVOU(mx, mx1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(mx1): - return &intrep.Instruction{ - Opcode: "MOVOU", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(mx1): - return &intrep.Instruction{ - Opcode: "MOVOU", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsXMM(mx) && operand.IsM128(mx1): - return &intrep.Instruction{ - Opcode: "MOVOU", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("MOVOU: bad operands") +// VPMAXSB m256 ymm ymm +// VPMAXSB ymm ymm ymm +// VPMAXSB m128 xmm xmm +// VPMAXSB xmm xmm xmm +// VPMAXSB m128 xmm k xmm +// VPMAXSB m256 ymm k ymm +// VPMAXSB xmm xmm k xmm +// VPMAXSB ymm ymm k ymm +// VPMAXSB m512 zmm k zmm +// VPMAXSB m512 zmm zmm +// VPMAXSB zmm zmm k zmm +// VPMAXSB zmm zmm zmm +func VPMAXSB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMAXSB.Forms(), sffxs{}, ops) } -// MOVQ: Move. +// VPMAXSB_Z: Maximum of Packed Signed Byte Integers (Zeroing Masking). // // Forms: // -// MOVQ imm32 r64 -// MOVQ imm64 r64 -// MOVQ r64 r64 -// MOVQ m64 r64 -// MOVQ imm32 m64 -// MOVQ r64 m64 -// MOVQ xmm r64 -// MOVQ r64 xmm -// MOVQ xmm xmm -// MOVQ m64 xmm -// MOVQ xmm m64 -// MOVQ xmm r32 -// MOVQ r32 xmm -// MOVQ m32 xmm -// MOVQ xmm m32 -func MOVQ(imrx, mrx operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM32(imrx) && operand.IsR64(mrx): - return &intrep.Instruction{ - Opcode: "MOVQ", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mrx}, - }, nil - case operand.IsIMM64(imrx) && operand.IsR64(mrx): - return &intrep.Instruction{ - Opcode: "MOVQ", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mrx}, - }, nil - case operand.IsR64(imrx) && operand.IsR64(mrx): - return &intrep.Instruction{ - Opcode: "MOVQ", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - }, nil - case operand.IsM64(imrx) && operand.IsR64(mrx): - return &intrep.Instruction{ - Opcode: "MOVQ", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - }, nil - case operand.IsIMM32(imrx) && operand.IsM64(mrx): - return &intrep.Instruction{ - Opcode: "MOVQ", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mrx}, - }, nil - case operand.IsR64(imrx) && operand.IsM64(mrx): - return &intrep.Instruction{ - Opcode: "MOVQ", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - }, nil - case operand.IsXMM(imrx) && operand.IsR64(mrx): - return &intrep.Instruction{ - Opcode: "MOVQ", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsR64(imrx) && operand.IsXMM(mrx): - return &intrep.Instruction{ - Opcode: "MOVQ", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsXMM(imrx) && operand.IsXMM(mrx): - return &intrep.Instruction{ - Opcode: "MOVQ", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM64(imrx) && operand.IsXMM(mrx): - return &intrep.Instruction{ - Opcode: "MOVQ", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsXMM(imrx) && operand.IsM64(mrx): - return &intrep.Instruction{ - Opcode: "MOVQ", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsXMM(imrx) && operand.IsR32(mrx): - return &intrep.Instruction{ - Opcode: "MOVQ", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsR32(imrx) && operand.IsXMM(mrx): - return &intrep.Instruction{ - Opcode: "MOVQ", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM32(imrx) && operand.IsXMM(mrx): - return &intrep.Instruction{ - Opcode: "MOVQ", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsXMM(imrx) && operand.IsM32(mrx): - return &intrep.Instruction{ - Opcode: "MOVQ", - Operands: []operand.Op{imrx, mrx}, - Inputs: []operand.Op{imrx}, - Outputs: []operand.Op{mrx}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("MOVQ: bad operands") +// VPMAXSB.Z m128 xmm k xmm +// VPMAXSB.Z m256 ymm k ymm +// VPMAXSB.Z xmm xmm k xmm +// VPMAXSB.Z ymm ymm k ymm +// VPMAXSB.Z m512 zmm k zmm +// VPMAXSB.Z zmm zmm k zmm +func VPMAXSB_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMAXSB.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// MOVSD: Move Scalar Double-Precision Floating-Point Value. +// VPMAXSD: Maximum of Packed Signed Doubleword Integers. // // Forms: // -// MOVSD xmm xmm -// MOVSD m64 xmm -// MOVSD xmm m64 -func MOVSD(mx, mx1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(mx1): - return &intrep.Instruction{ - Opcode: "MOVSD", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx, mx1}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(mx1): - return &intrep.Instruction{ - Opcode: "MOVSD", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsXMM(mx) && operand.IsM64(mx1): - return &intrep.Instruction{ - Opcode: "MOVSD", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("MOVSD: bad operands") +// VPMAXSD m256 ymm ymm +// VPMAXSD ymm ymm ymm +// VPMAXSD m128 xmm xmm +// VPMAXSD xmm xmm xmm +// VPMAXSD m128 xmm k xmm +// VPMAXSD m256 ymm k ymm +// VPMAXSD xmm xmm k xmm +// VPMAXSD ymm ymm k ymm +// VPMAXSD m512 zmm k zmm +// VPMAXSD m512 zmm zmm +// VPMAXSD zmm zmm k zmm +// VPMAXSD zmm zmm zmm +func VPMAXSD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMAXSD.Forms(), sffxs{}, ops) } -// MOVSHDUP: Move Packed Single-FP High and Duplicate. +// VPMAXSD_BCST: Maximum of Packed Signed Doubleword Integers (Broadcast). // // Forms: // -// MOVSHDUP xmm xmm -// MOVSHDUP m128 xmm -func MOVSHDUP(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MOVSHDUP", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE3"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MOVSHDUP", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE3"}, - }, nil - } - return nil, errors.New("MOVSHDUP: bad operands") +// VPMAXSD.BCST m32 xmm k xmm +// VPMAXSD.BCST m32 xmm xmm +// VPMAXSD.BCST m32 ymm k ymm +// VPMAXSD.BCST m32 ymm ymm +// VPMAXSD.BCST m32 zmm k zmm +// VPMAXSD.BCST m32 zmm zmm +func VPMAXSD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMAXSD.Forms(), sffxs{sffxBCST}, ops) } -// MOVSLDUP: Move Packed Single-FP Low and Duplicate. +// VPMAXSD_BCST_Z: Maximum of Packed Signed Doubleword Integers (Broadcast, Zeroing Masking). // // Forms: // -// MOVSLDUP xmm xmm -// MOVSLDUP m128 xmm -func MOVSLDUP(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MOVSLDUP", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE3"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MOVSLDUP", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE3"}, - }, nil - } - return nil, errors.New("MOVSLDUP: bad operands") +// VPMAXSD.BCST.Z m32 xmm k xmm +// VPMAXSD.BCST.Z m32 ymm k ymm +// VPMAXSD.BCST.Z m32 zmm k zmm +func VPMAXSD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMAXSD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// MOVSS: Move Scalar Single-Precision Floating-Point Values. +// VPMAXSD_Z: Maximum of Packed Signed Doubleword Integers (Zeroing Masking). // // Forms: // -// MOVSS xmm xmm -// MOVSS m32 xmm -// MOVSS xmm m32 -func MOVSS(mx, mx1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(mx1): - return &intrep.Instruction{ - Opcode: "MOVSS", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx, mx1}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(mx1): - return &intrep.Instruction{ - Opcode: "MOVSS", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE"}, - }, nil - case operand.IsXMM(mx) && operand.IsM32(mx1): - return &intrep.Instruction{ - Opcode: "MOVSS", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("MOVSS: bad operands") +// VPMAXSD.Z m128 xmm k xmm +// VPMAXSD.Z m256 ymm k ymm +// VPMAXSD.Z xmm xmm k xmm +// VPMAXSD.Z ymm ymm k ymm +// VPMAXSD.Z m512 zmm k zmm +// VPMAXSD.Z zmm zmm k zmm +func VPMAXSD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMAXSD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// MOVUPD: Move Unaligned Packed Double-Precision Floating-Point Values. +// VPMAXSQ: Maximum of Packed Signed Quadword Integers. // // Forms: // -// MOVUPD xmm xmm -// MOVUPD m128 xmm -// MOVUPD xmm m128 -func MOVUPD(mx, mx1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(mx1): - return &intrep.Instruction{ - Opcode: "MOVUPD", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(mx1): - return &intrep.Instruction{ - Opcode: "MOVUPD", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsXMM(mx) && operand.IsM128(mx1): - return &intrep.Instruction{ - Opcode: "MOVUPD", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("MOVUPD: bad operands") +// VPMAXSQ m128 xmm k xmm +// VPMAXSQ m128 xmm xmm +// VPMAXSQ m256 ymm k ymm +// VPMAXSQ m256 ymm ymm +// VPMAXSQ xmm xmm k xmm +// VPMAXSQ xmm xmm xmm +// VPMAXSQ ymm ymm k ymm +// VPMAXSQ ymm ymm ymm +// VPMAXSQ m512 zmm k zmm +// VPMAXSQ m512 zmm zmm +// VPMAXSQ zmm zmm k zmm +// VPMAXSQ zmm zmm zmm +func VPMAXSQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMAXSQ.Forms(), sffxs{}, ops) } -// MOVUPS: Move Unaligned Packed Single-Precision Floating-Point Values. +// VPMAXSQ_BCST: Maximum of Packed Signed Quadword Integers (Broadcast). // // Forms: // -// MOVUPS xmm xmm -// MOVUPS m128 xmm -// MOVUPS xmm m128 -func MOVUPS(mx, mx1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(mx1): - return &intrep.Instruction{ - Opcode: "MOVUPS", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(mx1): - return &intrep.Instruction{ - Opcode: "MOVUPS", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE"}, - }, nil - case operand.IsXMM(mx) && operand.IsM128(mx1): - return &intrep.Instruction{ - Opcode: "MOVUPS", - Operands: []operand.Op{mx, mx1}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{mx1}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("MOVUPS: bad operands") +// VPMAXSQ.BCST m64 xmm k xmm +// VPMAXSQ.BCST m64 xmm xmm +// VPMAXSQ.BCST m64 ymm k ymm +// VPMAXSQ.BCST m64 ymm ymm +// VPMAXSQ.BCST m64 zmm k zmm +// VPMAXSQ.BCST m64 zmm zmm +func VPMAXSQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMAXSQ.Forms(), sffxs{sffxBCST}, ops) } -// MOVW: Move. +// VPMAXSQ_BCST_Z: Maximum of Packed Signed Quadword Integers (Broadcast, Zeroing Masking). // // Forms: // -// MOVW imm16 r16 -// MOVW r16 r16 -// MOVW m16 r16 -// MOVW imm16 m16 -// MOVW r16 m16 -func MOVW(imr, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM16(imr) && operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "MOVW", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR16(imr) && operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "MOVW", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{imr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM16(imr) && operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "MOVW", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{imr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM16(imr) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "MOVW", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR16(imr) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "MOVW", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{imr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("MOVW: bad operands") +// VPMAXSQ.BCST.Z m64 xmm k xmm +// VPMAXSQ.BCST.Z m64 ymm k ymm +// VPMAXSQ.BCST.Z m64 zmm k zmm +func VPMAXSQ_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMAXSQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// MOVWLSX: Move with Sign-Extension. +// VPMAXSQ_Z: Maximum of Packed Signed Quadword Integers (Zeroing Masking). // // Forms: // -// MOVWLSX r16 r32 -// MOVWLSX m16 r32 -func MOVWLSX(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "MOVWLSX", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - case operand.IsM16(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "MOVWLSX", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - } - return nil, errors.New("MOVWLSX: bad operands") +// VPMAXSQ.Z m128 xmm k xmm +// VPMAXSQ.Z m256 ymm k ymm +// VPMAXSQ.Z xmm xmm k xmm +// VPMAXSQ.Z ymm ymm k ymm +// VPMAXSQ.Z m512 zmm k zmm +// VPMAXSQ.Z zmm zmm k zmm +func VPMAXSQ_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMAXSQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// MOVWLZX: Move with Zero-Extend. +// VPMAXSW: Maximum of Packed Signed Word Integers. // // Forms: // -// MOVWLZX r16 r32 -// MOVWLZX m16 r32 -func MOVWLZX(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "MOVWLZX", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - case operand.IsM16(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "MOVWLZX", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - } - return nil, errors.New("MOVWLZX: bad operands") +// VPMAXSW m256 ymm ymm +// VPMAXSW ymm ymm ymm +// VPMAXSW m128 xmm xmm +// VPMAXSW xmm xmm xmm +// VPMAXSW m128 xmm k xmm +// VPMAXSW m256 ymm k ymm +// VPMAXSW xmm xmm k xmm +// VPMAXSW ymm ymm k ymm +// VPMAXSW m512 zmm k zmm +// VPMAXSW m512 zmm zmm +// VPMAXSW zmm zmm k zmm +// VPMAXSW zmm zmm zmm +func VPMAXSW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMAXSW.Forms(), sffxs{}, ops) } -// MOVWQSX: Move with Sign-Extension. +// VPMAXSW_Z: Maximum of Packed Signed Word Integers (Zeroing Masking). // // Forms: // -// MOVWQSX r16 r64 -// MOVWQSX m16 r64 -func MOVWQSX(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "MOVWQSX", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - case operand.IsM16(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "MOVWQSX", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - } - return nil, errors.New("MOVWQSX: bad operands") +// VPMAXSW.Z m128 xmm k xmm +// VPMAXSW.Z m256 ymm k ymm +// VPMAXSW.Z xmm xmm k xmm +// VPMAXSW.Z ymm ymm k ymm +// VPMAXSW.Z m512 zmm k zmm +// VPMAXSW.Z zmm zmm k zmm +func VPMAXSW_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMAXSW.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// MOVWQZX: Move with Zero-Extend. +// VPMAXUB: Maximum of Packed Unsigned Byte Integers. // // Forms: // -// MOVWQZX r16 r64 -// MOVWQZX m16 r64 -func MOVWQZX(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "MOVWQZX", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - case operand.IsM16(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "MOVWQZX", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - }, nil - } - return nil, errors.New("MOVWQZX: bad operands") +// VPMAXUB m256 ymm ymm +// VPMAXUB ymm ymm ymm +// VPMAXUB m128 xmm xmm +// VPMAXUB xmm xmm xmm +// VPMAXUB m128 xmm k xmm +// VPMAXUB m256 ymm k ymm +// VPMAXUB xmm xmm k xmm +// VPMAXUB ymm ymm k ymm +// VPMAXUB m512 zmm k zmm +// VPMAXUB m512 zmm zmm +// VPMAXUB zmm zmm k zmm +// VPMAXUB zmm zmm zmm +func VPMAXUB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMAXUB.Forms(), sffxs{}, ops) } -// MPSADBW: Compute Multiple Packed Sums of Absolute Difference. +// VPMAXUB_Z: Maximum of Packed Unsigned Byte Integers (Zeroing Masking). // // Forms: // -// MPSADBW imm8 xmm xmm -// MPSADBW imm8 m128 xmm -func MPSADBW(i, mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MPSADBW", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MPSADBW", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("MPSADBW: bad operands") +// VPMAXUB.Z m128 xmm k xmm +// VPMAXUB.Z m256 ymm k ymm +// VPMAXUB.Z xmm xmm k xmm +// VPMAXUB.Z ymm ymm k ymm +// VPMAXUB.Z m512 zmm k zmm +// VPMAXUB.Z zmm zmm k zmm +func VPMAXUB_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMAXUB.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// MULB: Unsigned Multiply. +// VPMAXUD: Maximum of Packed Unsigned Doubleword Integers. // // Forms: // -// MULB r8 -// MULB m8 -func MULB(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "MULB", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr, reg.AL}, - Outputs: []operand.Op{reg.AX}, - }, nil - case operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "MULB", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr, reg.AL}, - Outputs: []operand.Op{reg.AX}, - }, nil - } - return nil, errors.New("MULB: bad operands") +// VPMAXUD m256 ymm ymm +// VPMAXUD ymm ymm ymm +// VPMAXUD m128 xmm xmm +// VPMAXUD xmm xmm xmm +// VPMAXUD m128 xmm k xmm +// VPMAXUD m256 ymm k ymm +// VPMAXUD xmm xmm k xmm +// VPMAXUD ymm ymm k ymm +// VPMAXUD m512 zmm k zmm +// VPMAXUD m512 zmm zmm +// VPMAXUD zmm zmm k zmm +// VPMAXUD zmm zmm zmm +func VPMAXUD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMAXUD.Forms(), sffxs{}, ops) } -// MULL: Unsigned Multiply. +// VPMAXUD_BCST: Maximum of Packed Unsigned Doubleword Integers (Broadcast). // // Forms: // -// MULL r32 -// MULL m32 -func MULL(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "MULL", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr, reg.EAX}, - Outputs: []operand.Op{reg.EAX, reg.EDX}, - }, nil - case operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "MULL", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr, reg.EAX}, - Outputs: []operand.Op{reg.EAX, reg.EDX}, - }, nil - } - return nil, errors.New("MULL: bad operands") +// VPMAXUD.BCST m32 xmm k xmm +// VPMAXUD.BCST m32 xmm xmm +// VPMAXUD.BCST m32 ymm k ymm +// VPMAXUD.BCST m32 ymm ymm +// VPMAXUD.BCST m32 zmm k zmm +// VPMAXUD.BCST m32 zmm zmm +func VPMAXUD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMAXUD.Forms(), sffxs{sffxBCST}, ops) } -// MULPD: Multiply Packed Double-Precision Floating-Point Values. +// VPMAXUD_BCST_Z: Maximum of Packed Unsigned Doubleword Integers (Broadcast, Zeroing Masking). // // Forms: // -// MULPD xmm xmm -// MULPD m128 xmm -func MULPD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MULPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MULPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("MULPD: bad operands") +// VPMAXUD.BCST.Z m32 xmm k xmm +// VPMAXUD.BCST.Z m32 ymm k ymm +// VPMAXUD.BCST.Z m32 zmm k zmm +func VPMAXUD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMAXUD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// MULPS: Multiply Packed Single-Precision Floating-Point Values. +// VPMAXUD_Z: Maximum of Packed Unsigned Doubleword Integers (Zeroing Masking). // // Forms: // -// MULPS xmm xmm -// MULPS m128 xmm -func MULPS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MULPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MULPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("MULPS: bad operands") +// VPMAXUD.Z m128 xmm k xmm +// VPMAXUD.Z m256 ymm k ymm +// VPMAXUD.Z xmm xmm k xmm +// VPMAXUD.Z ymm ymm k ymm +// VPMAXUD.Z m512 zmm k zmm +// VPMAXUD.Z zmm zmm k zmm +func VPMAXUD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMAXUD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// MULQ: Unsigned Multiply. +// VPMAXUQ: Maximum of Packed Unsigned Quadword Integers. // // Forms: // -// MULQ r64 -// MULQ m64 -func MULQ(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "MULQ", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr, reg.RAX}, - Outputs: []operand.Op{reg.RAX, reg.RDX}, - }, nil - case operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "MULQ", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr, reg.RAX}, - Outputs: []operand.Op{reg.RAX, reg.RDX}, - }, nil - } - return nil, errors.New("MULQ: bad operands") +// VPMAXUQ m128 xmm k xmm +// VPMAXUQ m128 xmm xmm +// VPMAXUQ m256 ymm k ymm +// VPMAXUQ m256 ymm ymm +// VPMAXUQ xmm xmm k xmm +// VPMAXUQ xmm xmm xmm +// VPMAXUQ ymm ymm k ymm +// VPMAXUQ ymm ymm ymm +// VPMAXUQ m512 zmm k zmm +// VPMAXUQ m512 zmm zmm +// VPMAXUQ zmm zmm k zmm +// VPMAXUQ zmm zmm zmm +func VPMAXUQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMAXUQ.Forms(), sffxs{}, ops) } -// MULSD: Multiply Scalar Double-Precision Floating-Point Values. +// VPMAXUQ_BCST: Maximum of Packed Unsigned Quadword Integers (Broadcast). // // Forms: // -// MULSD xmm xmm -// MULSD m64 xmm -func MULSD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MULSD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MULSD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("MULSD: bad operands") +// VPMAXUQ.BCST m64 xmm k xmm +// VPMAXUQ.BCST m64 xmm xmm +// VPMAXUQ.BCST m64 ymm k ymm +// VPMAXUQ.BCST m64 ymm ymm +// VPMAXUQ.BCST m64 zmm k zmm +// VPMAXUQ.BCST m64 zmm zmm +func VPMAXUQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMAXUQ.Forms(), sffxs{sffxBCST}, ops) } -// MULSS: Multiply Scalar Single-Precision Floating-Point Values. +// VPMAXUQ_BCST_Z: Maximum of Packed Unsigned Quadword Integers (Broadcast, Zeroing Masking). // // Forms: // -// MULSS xmm xmm -// MULSS m32 xmm -func MULSS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MULSS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "MULSS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("MULSS: bad operands") +// VPMAXUQ.BCST.Z m64 xmm k xmm +// VPMAXUQ.BCST.Z m64 ymm k ymm +// VPMAXUQ.BCST.Z m64 zmm k zmm +func VPMAXUQ_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMAXUQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// MULW: Unsigned Multiply. +// VPMAXUQ_Z: Maximum of Packed Unsigned Quadword Integers (Zeroing Masking). // // Forms: // -// MULW r16 -// MULW m16 -func MULW(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "MULW", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr, reg.AX}, - Outputs: []operand.Op{reg.AX, reg.DX}, - }, nil - case operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "MULW", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr, reg.AX}, - Outputs: []operand.Op{reg.AX, reg.DX}, - }, nil - } - return nil, errors.New("MULW: bad operands") +// VPMAXUQ.Z m128 xmm k xmm +// VPMAXUQ.Z m256 ymm k ymm +// VPMAXUQ.Z xmm xmm k xmm +// VPMAXUQ.Z ymm ymm k ymm +// VPMAXUQ.Z m512 zmm k zmm +// VPMAXUQ.Z zmm zmm k zmm +func VPMAXUQ_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMAXUQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// MULXL: Unsigned Multiply Without Affecting Flags. +// VPMAXUW: Maximum of Packed Unsigned Word Integers. // // Forms: // -// MULXL r32 r32 r32 -// MULXL m32 r32 r32 -func MULXL(mr, r, r1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR32(r) && operand.IsR32(r1): - return &intrep.Instruction{ - Opcode: "MULXL", - Operands: []operand.Op{mr, r, r1}, - Inputs: []operand.Op{mr, reg.EDX}, - Outputs: []operand.Op{r, r1}, - ISA: []string{"BMI2"}, - }, nil - case operand.IsM32(mr) && operand.IsR32(r) && operand.IsR32(r1): - return &intrep.Instruction{ - Opcode: "MULXL", - Operands: []operand.Op{mr, r, r1}, - Inputs: []operand.Op{mr, reg.EDX}, - Outputs: []operand.Op{r, r1}, - ISA: []string{"BMI2"}, - }, nil - } - return nil, errors.New("MULXL: bad operands") +// VPMAXUW m256 ymm ymm +// VPMAXUW ymm ymm ymm +// VPMAXUW m128 xmm xmm +// VPMAXUW xmm xmm xmm +// VPMAXUW m128 xmm k xmm +// VPMAXUW m256 ymm k ymm +// VPMAXUW xmm xmm k xmm +// VPMAXUW ymm ymm k ymm +// VPMAXUW m512 zmm k zmm +// VPMAXUW m512 zmm zmm +// VPMAXUW zmm zmm k zmm +// VPMAXUW zmm zmm zmm +func VPMAXUW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMAXUW.Forms(), sffxs{}, ops) } -// MULXQ: Unsigned Multiply Without Affecting Flags. +// VPMAXUW_Z: Maximum of Packed Unsigned Word Integers (Zeroing Masking). // // Forms: // -// MULXQ r64 r64 r64 -// MULXQ m64 r64 r64 -func MULXQ(mr, r, r1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsR64(r) && operand.IsR64(r1): - return &intrep.Instruction{ - Opcode: "MULXQ", - Operands: []operand.Op{mr, r, r1}, - Inputs: []operand.Op{mr, reg.RDX}, - Outputs: []operand.Op{r, r1}, - ISA: []string{"BMI2"}, - }, nil - case operand.IsM64(mr) && operand.IsR64(r) && operand.IsR64(r1): - return &intrep.Instruction{ - Opcode: "MULXQ", - Operands: []operand.Op{mr, r, r1}, - Inputs: []operand.Op{mr, reg.RDX}, - Outputs: []operand.Op{r, r1}, - ISA: []string{"BMI2"}, - }, nil - } - return nil, errors.New("MULXQ: bad operands") +// VPMAXUW.Z m128 xmm k xmm +// VPMAXUW.Z m256 ymm k ymm +// VPMAXUW.Z xmm xmm k xmm +// VPMAXUW.Z ymm ymm k ymm +// VPMAXUW.Z m512 zmm k zmm +// VPMAXUW.Z zmm zmm k zmm +func VPMAXUW_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMAXUW.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// MWAIT: Monitor Wait. +// VPMINSB: Minimum of Packed Signed Byte Integers. // // Forms: // -// MWAIT -func MWAIT() (*intrep.Instruction, error) { - return &intrep.Instruction{ - Opcode: "MWAIT", - Operands: nil, - Inputs: []operand.Op{reg.EAX, reg.ECX}, - Outputs: []operand.Op{}, - ISA: []string{"MONITOR"}, - }, nil +// VPMINSB m256 ymm ymm +// VPMINSB ymm ymm ymm +// VPMINSB m128 xmm xmm +// VPMINSB xmm xmm xmm +// VPMINSB m128 xmm k xmm +// VPMINSB m256 ymm k ymm +// VPMINSB xmm xmm k xmm +// VPMINSB ymm ymm k ymm +// VPMINSB m512 zmm k zmm +// VPMINSB m512 zmm zmm +// VPMINSB zmm zmm k zmm +// VPMINSB zmm zmm zmm +func VPMINSB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMINSB.Forms(), sffxs{}, ops) } -// NEGB: Two's Complement Negation. +// VPMINSB_Z: Minimum of Packed Signed Byte Integers (Zeroing Masking). // // Forms: // -// NEGB r8 -// NEGB m8 -func NEGB(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "NEGB", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "NEGB", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("NEGB: bad operands") +// VPMINSB.Z m128 xmm k xmm +// VPMINSB.Z m256 ymm k ymm +// VPMINSB.Z xmm xmm k xmm +// VPMINSB.Z ymm ymm k ymm +// VPMINSB.Z m512 zmm k zmm +// VPMINSB.Z zmm zmm k zmm +func VPMINSB_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMINSB.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// NEGL: Two's Complement Negation. +// VPMINSD: Minimum of Packed Signed Doubleword Integers. // // Forms: // -// NEGL r32 -// NEGL m32 -func NEGL(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "NEGL", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "NEGL", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("NEGL: bad operands") +// VPMINSD m256 ymm ymm +// VPMINSD ymm ymm ymm +// VPMINSD m128 xmm xmm +// VPMINSD xmm xmm xmm +// VPMINSD m128 xmm k xmm +// VPMINSD m256 ymm k ymm +// VPMINSD xmm xmm k xmm +// VPMINSD ymm ymm k ymm +// VPMINSD m512 zmm k zmm +// VPMINSD m512 zmm zmm +// VPMINSD zmm zmm k zmm +// VPMINSD zmm zmm zmm +func VPMINSD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMINSD.Forms(), sffxs{}, ops) } -// NEGQ: Two's Complement Negation. +// VPMINSD_BCST: Minimum of Packed Signed Doubleword Integers (Broadcast). // // Forms: // -// NEGQ r64 -// NEGQ m64 -func NEGQ(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "NEGQ", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "NEGQ", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("NEGQ: bad operands") +// VPMINSD.BCST m32 xmm k xmm +// VPMINSD.BCST m32 xmm xmm +// VPMINSD.BCST m32 ymm k ymm +// VPMINSD.BCST m32 ymm ymm +// VPMINSD.BCST m32 zmm k zmm +// VPMINSD.BCST m32 zmm zmm +func VPMINSD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMINSD.Forms(), sffxs{sffxBCST}, ops) } -// NEGW: Two's Complement Negation. +// VPMINSD_BCST_Z: Minimum of Packed Signed Doubleword Integers (Broadcast, Zeroing Masking). // // Forms: // -// NEGW r16 -// NEGW m16 -func NEGW(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "NEGW", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "NEGW", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("NEGW: bad operands") +// VPMINSD.BCST.Z m32 xmm k xmm +// VPMINSD.BCST.Z m32 ymm k ymm +// VPMINSD.BCST.Z m32 zmm k zmm +func VPMINSD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMINSD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// NOP: No Operation. +// VPMINSD_Z: Minimum of Packed Signed Doubleword Integers (Zeroing Masking). // // Forms: // -// NOP -func NOP() (*intrep.Instruction, error) { - return &intrep.Instruction{ - Opcode: "NOP", - Operands: nil, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - }, nil +// VPMINSD.Z m128 xmm k xmm +// VPMINSD.Z m256 ymm k ymm +// VPMINSD.Z xmm xmm k xmm +// VPMINSD.Z ymm ymm k ymm +// VPMINSD.Z m512 zmm k zmm +// VPMINSD.Z zmm zmm k zmm +func VPMINSD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMINSD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// NOTB: One's Complement Negation. +// VPMINSQ: Minimum of Packed Signed Quadword Integers. // // Forms: // -// NOTB r8 -// NOTB m8 -func NOTB(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "NOTB", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "NOTB", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("NOTB: bad operands") +// VPMINSQ m128 xmm k xmm +// VPMINSQ m128 xmm xmm +// VPMINSQ m256 ymm k ymm +// VPMINSQ m256 ymm ymm +// VPMINSQ xmm xmm k xmm +// VPMINSQ xmm xmm xmm +// VPMINSQ ymm ymm k ymm +// VPMINSQ ymm ymm ymm +// VPMINSQ m512 zmm k zmm +// VPMINSQ m512 zmm zmm +// VPMINSQ zmm zmm k zmm +// VPMINSQ zmm zmm zmm +func VPMINSQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMINSQ.Forms(), sffxs{}, ops) } -// NOTL: One's Complement Negation. +// VPMINSQ_BCST: Minimum of Packed Signed Quadword Integers (Broadcast). // // Forms: // -// NOTL r32 -// NOTL m32 -func NOTL(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "NOTL", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "NOTL", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("NOTL: bad operands") +// VPMINSQ.BCST m64 xmm k xmm +// VPMINSQ.BCST m64 xmm xmm +// VPMINSQ.BCST m64 ymm k ymm +// VPMINSQ.BCST m64 ymm ymm +// VPMINSQ.BCST m64 zmm k zmm +// VPMINSQ.BCST m64 zmm zmm +func VPMINSQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMINSQ.Forms(), sffxs{sffxBCST}, ops) } -// NOTQ: One's Complement Negation. +// VPMINSQ_BCST_Z: Minimum of Packed Signed Quadword Integers (Broadcast, Zeroing Masking). // // Forms: // -// NOTQ r64 -// NOTQ m64 -func NOTQ(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "NOTQ", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "NOTQ", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("NOTQ: bad operands") +// VPMINSQ.BCST.Z m64 xmm k xmm +// VPMINSQ.BCST.Z m64 ymm k ymm +// VPMINSQ.BCST.Z m64 zmm k zmm +func VPMINSQ_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMINSQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// NOTW: One's Complement Negation. +// VPMINSQ_Z: Minimum of Packed Signed Quadword Integers (Zeroing Masking). // // Forms: // -// NOTW r16 -// NOTW m16 -func NOTW(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "NOTW", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "NOTW", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("NOTW: bad operands") +// VPMINSQ.Z m128 xmm k xmm +// VPMINSQ.Z m256 ymm k ymm +// VPMINSQ.Z xmm xmm k xmm +// VPMINSQ.Z ymm ymm k ymm +// VPMINSQ.Z m512 zmm k zmm +// VPMINSQ.Z zmm zmm k zmm +func VPMINSQ_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMINSQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// ORB: Logical Inclusive OR. +// VPMINSW: Minimum of Packed Signed Word Integers. // // Forms: // -// ORB imm8 al -// ORB imm8 r8 -// ORB r8 r8 -// ORB m8 r8 -// ORB imm8 m8 -// ORB r8 m8 -func ORB(imr, amr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(imr) && operand.IsAL(amr): - return &intrep.Instruction{ - Opcode: "ORB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM8(imr) && operand.IsR8(amr): - return &intrep.Instruction{ - Opcode: "ORB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsR8(imr) && operand.IsR8(amr): - return &intrep.Instruction{ - Opcode: "ORB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsM8(imr) && operand.IsR8(amr): - return &intrep.Instruction{ - Opcode: "ORB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM8(imr) && operand.IsM8(amr): - return &intrep.Instruction{ - Opcode: "ORB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsR8(imr) && operand.IsM8(amr): - return &intrep.Instruction{ - Opcode: "ORB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - } - return nil, errors.New("ORB: bad operands") +// VPMINSW m256 ymm ymm +// VPMINSW ymm ymm ymm +// VPMINSW m128 xmm xmm +// VPMINSW xmm xmm xmm +// VPMINSW m128 xmm k xmm +// VPMINSW m256 ymm k ymm +// VPMINSW xmm xmm k xmm +// VPMINSW ymm ymm k ymm +// VPMINSW m512 zmm k zmm +// VPMINSW m512 zmm zmm +// VPMINSW zmm zmm k zmm +// VPMINSW zmm zmm zmm +func VPMINSW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMINSW.Forms(), sffxs{}, ops) } -// ORL: Logical Inclusive OR. +// VPMINSW_Z: Minimum of Packed Signed Word Integers (Zeroing Masking). // // Forms: // -// ORL imm32 eax -// ORL imm8 r32 -// ORL imm32 r32 -// ORL r32 r32 -// ORL m32 r32 -// ORL imm8 m32 -// ORL imm32 m32 -// ORL r32 m32 -func ORL(imr, emr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM32(imr) && operand.IsEAX(emr): - return &intrep.Instruction{ - Opcode: "ORL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsIMM8(imr) && operand.IsR32(emr): - return &intrep.Instruction{ - Opcode: "ORL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsIMM32(imr) && operand.IsR32(emr): - return &intrep.Instruction{ - Opcode: "ORL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsR32(imr) && operand.IsR32(emr): - return &intrep.Instruction{ - Opcode: "ORL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{imr, emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsM32(imr) && operand.IsR32(emr): - return &intrep.Instruction{ - Opcode: "ORL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{imr, emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsIMM8(imr) && operand.IsM32(emr): - return &intrep.Instruction{ - Opcode: "ORL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsIMM32(imr) && operand.IsM32(emr): - return &intrep.Instruction{ - Opcode: "ORL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsR32(imr) && operand.IsM32(emr): - return &intrep.Instruction{ - Opcode: "ORL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{imr, emr}, - Outputs: []operand.Op{emr}, - }, nil - } - return nil, errors.New("ORL: bad operands") +// VPMINSW.Z m128 xmm k xmm +// VPMINSW.Z m256 ymm k ymm +// VPMINSW.Z xmm xmm k xmm +// VPMINSW.Z ymm ymm k ymm +// VPMINSW.Z m512 zmm k zmm +// VPMINSW.Z zmm zmm k zmm +func VPMINSW_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMINSW.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// ORPD: Bitwise Logical OR of Double-Precision Floating-Point Values. +// VPMINUB: Minimum of Packed Unsigned Byte Integers. // // Forms: // -// ORPD xmm xmm -// ORPD m128 xmm -func ORPD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ORPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ORPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("ORPD: bad operands") +// VPMINUB m256 ymm ymm +// VPMINUB ymm ymm ymm +// VPMINUB m128 xmm xmm +// VPMINUB xmm xmm xmm +// VPMINUB m128 xmm k xmm +// VPMINUB m256 ymm k ymm +// VPMINUB xmm xmm k xmm +// VPMINUB ymm ymm k ymm +// VPMINUB m512 zmm k zmm +// VPMINUB m512 zmm zmm +// VPMINUB zmm zmm k zmm +// VPMINUB zmm zmm zmm +func VPMINUB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMINUB.Forms(), sffxs{}, ops) } -// ORPS: Bitwise Logical OR of Single-Precision Floating-Point Values. +// VPMINUB_Z: Minimum of Packed Unsigned Byte Integers (Zeroing Masking). // // Forms: // -// ORPS xmm xmm -// ORPS m128 xmm -func ORPS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ORPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ORPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("ORPS: bad operands") +// VPMINUB.Z m128 xmm k xmm +// VPMINUB.Z m256 ymm k ymm +// VPMINUB.Z xmm xmm k xmm +// VPMINUB.Z ymm ymm k ymm +// VPMINUB.Z m512 zmm k zmm +// VPMINUB.Z zmm zmm k zmm +func VPMINUB_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMINUB.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// ORQ: Logical Inclusive OR. +// VPMINUD: Minimum of Packed Unsigned Doubleword Integers. // // Forms: // -// ORQ imm32 rax -// ORQ imm8 r64 -// ORQ imm32 r64 -// ORQ r64 r64 -// ORQ m64 r64 -// ORQ imm8 m64 -// ORQ imm32 m64 -// ORQ r64 m64 -func ORQ(imr, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM32(imr) && operand.IsRAX(mr): - return &intrep.Instruction{ - Opcode: "ORQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(imr) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "ORQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM32(imr) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "ORQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR64(imr) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "ORQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{imr, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM64(imr) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "ORQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{imr, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(imr) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "ORQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM32(imr) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "ORQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR64(imr) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "ORQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{imr, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("ORQ: bad operands") +// VPMINUD m256 ymm ymm +// VPMINUD ymm ymm ymm +// VPMINUD m128 xmm xmm +// VPMINUD xmm xmm xmm +// VPMINUD m128 xmm k xmm +// VPMINUD m256 ymm k ymm +// VPMINUD xmm xmm k xmm +// VPMINUD ymm ymm k ymm +// VPMINUD m512 zmm k zmm +// VPMINUD m512 zmm zmm +// VPMINUD zmm zmm k zmm +// VPMINUD zmm zmm zmm +func VPMINUD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMINUD.Forms(), sffxs{}, ops) } -// ORW: Logical Inclusive OR. +// VPMINUD_BCST: Minimum of Packed Unsigned Doubleword Integers (Broadcast). // // Forms: // -// ORW imm16 ax -// ORW imm8 r16 -// ORW imm16 r16 -// ORW r16 r16 -// ORW m16 r16 -// ORW imm8 m16 -// ORW imm16 m16 -// ORW r16 m16 -func ORW(imr, amr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM16(imr) && operand.IsAX(amr): - return &intrep.Instruction{ - Opcode: "ORW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM8(imr) && operand.IsR16(amr): - return &intrep.Instruction{ - Opcode: "ORW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM16(imr) && operand.IsR16(amr): - return &intrep.Instruction{ - Opcode: "ORW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsR16(imr) && operand.IsR16(amr): - return &intrep.Instruction{ - Opcode: "ORW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsM16(imr) && operand.IsR16(amr): - return &intrep.Instruction{ - Opcode: "ORW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM8(imr) && operand.IsM16(amr): - return &intrep.Instruction{ - Opcode: "ORW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM16(imr) && operand.IsM16(amr): - return &intrep.Instruction{ - Opcode: "ORW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsR16(imr) && operand.IsM16(amr): - return &intrep.Instruction{ - Opcode: "ORW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - } - return nil, errors.New("ORW: bad operands") +// VPMINUD.BCST m32 xmm k xmm +// VPMINUD.BCST m32 xmm xmm +// VPMINUD.BCST m32 ymm k ymm +// VPMINUD.BCST m32 ymm ymm +// VPMINUD.BCST m32 zmm k zmm +// VPMINUD.BCST m32 zmm zmm +func VPMINUD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMINUD.Forms(), sffxs{sffxBCST}, ops) } -// PABSB: Packed Absolute Value of Byte Integers. +// VPMINUD_BCST_Z: Minimum of Packed Unsigned Doubleword Integers (Broadcast, Zeroing Masking). // // Forms: // -// PABSB xmm xmm -// PABSB m128 xmm -func PABSB(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PABSB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PABSB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - }, nil - } - return nil, errors.New("PABSB: bad operands") +// VPMINUD.BCST.Z m32 xmm k xmm +// VPMINUD.BCST.Z m32 ymm k ymm +// VPMINUD.BCST.Z m32 zmm k zmm +func VPMINUD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMINUD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// PABSD: Packed Absolute Value of Doubleword Integers. +// VPMINUD_Z: Minimum of Packed Unsigned Doubleword Integers (Zeroing Masking). // // Forms: // -// PABSD xmm xmm -// PABSD m128 xmm -func PABSD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PABSD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PABSD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - }, nil - } - return nil, errors.New("PABSD: bad operands") +// VPMINUD.Z m128 xmm k xmm +// VPMINUD.Z m256 ymm k ymm +// VPMINUD.Z xmm xmm k xmm +// VPMINUD.Z ymm ymm k ymm +// VPMINUD.Z m512 zmm k zmm +// VPMINUD.Z zmm zmm k zmm +func VPMINUD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMINUD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// PABSW: Packed Absolute Value of Word Integers. +// VPMINUQ: Minimum of Packed Unsigned Quadword Integers. // // Forms: // -// PABSW xmm xmm -// PABSW m128 xmm -func PABSW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PABSW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PABSW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - }, nil - } - return nil, errors.New("PABSW: bad operands") +// VPMINUQ m128 xmm k xmm +// VPMINUQ m128 xmm xmm +// VPMINUQ m256 ymm k ymm +// VPMINUQ m256 ymm ymm +// VPMINUQ xmm xmm k xmm +// VPMINUQ xmm xmm xmm +// VPMINUQ ymm ymm k ymm +// VPMINUQ ymm ymm ymm +// VPMINUQ m512 zmm k zmm +// VPMINUQ m512 zmm zmm +// VPMINUQ zmm zmm k zmm +// VPMINUQ zmm zmm zmm +func VPMINUQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMINUQ.Forms(), sffxs{}, ops) } -// PACKSSLW: Pack Doublewords into Words with Signed Saturation. +// VPMINUQ_BCST: Minimum of Packed Unsigned Quadword Integers (Broadcast). // // Forms: // -// PACKSSLW xmm xmm -// PACKSSLW m128 xmm -func PACKSSLW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PACKSSLW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PACKSSLW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PACKSSLW: bad operands") +// VPMINUQ.BCST m64 xmm k xmm +// VPMINUQ.BCST m64 xmm xmm +// VPMINUQ.BCST m64 ymm k ymm +// VPMINUQ.BCST m64 ymm ymm +// VPMINUQ.BCST m64 zmm k zmm +// VPMINUQ.BCST m64 zmm zmm +func VPMINUQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMINUQ.Forms(), sffxs{sffxBCST}, ops) } -// PACKSSWB: Pack Words into Bytes with Signed Saturation. +// VPMINUQ_BCST_Z: Minimum of Packed Unsigned Quadword Integers (Broadcast, Zeroing Masking). // // Forms: // -// PACKSSWB xmm xmm -// PACKSSWB m128 xmm -func PACKSSWB(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PACKSSWB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PACKSSWB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PACKSSWB: bad operands") +// VPMINUQ.BCST.Z m64 xmm k xmm +// VPMINUQ.BCST.Z m64 ymm k ymm +// VPMINUQ.BCST.Z m64 zmm k zmm +func VPMINUQ_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMINUQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// PACKUSDW: Pack Doublewords into Words with Unsigned Saturation. +// VPMINUQ_Z: Minimum of Packed Unsigned Quadword Integers (Zeroing Masking). // // Forms: // -// PACKUSDW xmm xmm -// PACKUSDW m128 xmm -func PACKUSDW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PACKUSDW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PACKUSDW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PACKUSDW: bad operands") +// VPMINUQ.Z m128 xmm k xmm +// VPMINUQ.Z m256 ymm k ymm +// VPMINUQ.Z xmm xmm k xmm +// VPMINUQ.Z ymm ymm k ymm +// VPMINUQ.Z m512 zmm k zmm +// VPMINUQ.Z zmm zmm k zmm +func VPMINUQ_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMINUQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// PACKUSWB: Pack Words into Bytes with Unsigned Saturation. +// VPMINUW: Minimum of Packed Unsigned Word Integers. // // Forms: // -// PACKUSWB xmm xmm -// PACKUSWB m128 xmm -func PACKUSWB(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PACKUSWB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PACKUSWB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PACKUSWB: bad operands") +// VPMINUW m256 ymm ymm +// VPMINUW ymm ymm ymm +// VPMINUW m128 xmm xmm +// VPMINUW xmm xmm xmm +// VPMINUW m128 xmm k xmm +// VPMINUW m256 ymm k ymm +// VPMINUW xmm xmm k xmm +// VPMINUW ymm ymm k ymm +// VPMINUW m512 zmm k zmm +// VPMINUW m512 zmm zmm +// VPMINUW zmm zmm k zmm +// VPMINUW zmm zmm zmm +func VPMINUW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMINUW.Forms(), sffxs{}, ops) } -// PADDB: Add Packed Byte Integers. +// VPMINUW_Z: Minimum of Packed Unsigned Word Integers (Zeroing Masking). // // Forms: // -// PADDB xmm xmm -// PADDB m128 xmm -func PADDB(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PADDB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PADDB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PADDB: bad operands") +// VPMINUW.Z m128 xmm k xmm +// VPMINUW.Z m256 ymm k ymm +// VPMINUW.Z xmm xmm k xmm +// VPMINUW.Z ymm ymm k ymm +// VPMINUW.Z m512 zmm k zmm +// VPMINUW.Z zmm zmm k zmm +func VPMINUW_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMINUW.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// PADDD: Add Packed Doubleword Integers. +// VPMOVB2M: Move Signs of Packed Byte Integers to Mask Register. // // Forms: // -// PADDD xmm xmm -// PADDD m128 xmm -func PADDD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PADDD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PADDD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PADDD: bad operands") +// VPMOVB2M xmm k +// VPMOVB2M ymm k +// VPMOVB2M zmm k +func VPMOVB2M(xyz, k operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVB2M.Forms(), sffxs{}, []operand.Op{xyz, k}) } -// PADDL: Add Packed Doubleword Integers. +// VPMOVD2M: Move Signs of Packed Doubleword Integers to Mask Register. // // Forms: // -// PADDL xmm xmm -// PADDL m128 xmm -func PADDL(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PADDL", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PADDL", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PADDL: bad operands") +// VPMOVD2M xmm k +// VPMOVD2M ymm k +// VPMOVD2M zmm k +func VPMOVD2M(xyz, k operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVD2M.Forms(), sffxs{}, []operand.Op{xyz, k}) } -// PADDQ: Add Packed Quadword Integers. +// VPMOVDB: Down Convert Packed Doubleword Values to Byte Values with Truncation. // // Forms: // -// PADDQ xmm xmm -// PADDQ m128 xmm -func PADDQ(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PADDQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PADDQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PADDQ: bad operands") +// VPMOVDB xmm k m32 +// VPMOVDB xmm k xmm +// VPMOVDB xmm m32 +// VPMOVDB xmm xmm +// VPMOVDB ymm k m64 +// VPMOVDB ymm k xmm +// VPMOVDB ymm m64 +// VPMOVDB ymm xmm +// VPMOVDB zmm k m128 +// VPMOVDB zmm k xmm +// VPMOVDB zmm m128 +// VPMOVDB zmm xmm +func VPMOVDB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVDB.Forms(), sffxs{}, ops) } -// PADDSB: Add Packed Signed Byte Integers with Signed Saturation. +// VPMOVDB_Z: Down Convert Packed Doubleword Values to Byte Values with Truncation (Zeroing Masking). // // Forms: // -// PADDSB xmm xmm -// PADDSB m128 xmm -func PADDSB(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PADDSB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PADDSB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PADDSB: bad operands") +// VPMOVDB.Z xmm k m32 +// VPMOVDB.Z xmm k xmm +// VPMOVDB.Z ymm k m64 +// VPMOVDB.Z ymm k xmm +// VPMOVDB.Z zmm k m128 +// VPMOVDB.Z zmm k xmm +func VPMOVDB_Z(xyz, k, mx operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVDB.Forms(), sffxs{sffxZ}, []operand.Op{xyz, k, mx}) } -// PADDSW: Add Packed Signed Word Integers with Signed Saturation. +// VPMOVDW: Down Convert Packed Doubleword Values to Word Values with Truncation. // // Forms: // -// PADDSW xmm xmm -// PADDSW m128 xmm -func PADDSW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PADDSW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PADDSW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PADDSW: bad operands") +// VPMOVDW xmm k m64 +// VPMOVDW xmm k xmm +// VPMOVDW xmm m64 +// VPMOVDW xmm xmm +// VPMOVDW ymm k m128 +// VPMOVDW ymm k xmm +// VPMOVDW ymm m128 +// VPMOVDW ymm xmm +// VPMOVDW zmm k m256 +// VPMOVDW zmm k ymm +// VPMOVDW zmm m256 +// VPMOVDW zmm ymm +func VPMOVDW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVDW.Forms(), sffxs{}, ops) } -// PADDUSB: Add Packed Unsigned Byte Integers with Unsigned Saturation. +// VPMOVDW_Z: Down Convert Packed Doubleword Values to Word Values with Truncation (Zeroing Masking). // // Forms: // -// PADDUSB xmm xmm -// PADDUSB m128 xmm -func PADDUSB(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PADDUSB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PADDUSB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PADDUSB: bad operands") +// VPMOVDW.Z xmm k m64 +// VPMOVDW.Z xmm k xmm +// VPMOVDW.Z ymm k m128 +// VPMOVDW.Z ymm k xmm +// VPMOVDW.Z zmm k m256 +// VPMOVDW.Z zmm k ymm +func VPMOVDW_Z(xyz, k, mxy operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVDW.Forms(), sffxs{sffxZ}, []operand.Op{xyz, k, mxy}) } -// PADDUSW: Add Packed Unsigned Word Integers with Unsigned Saturation. +// VPMOVM2B: Expand Bits of Mask Register to Packed Byte Integers. // // Forms: // -// PADDUSW xmm xmm -// PADDUSW m128 xmm -func PADDUSW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PADDUSW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PADDUSW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PADDUSW: bad operands") +// VPMOVM2B k xmm +// VPMOVM2B k ymm +// VPMOVM2B k zmm +func VPMOVM2B(k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVM2B.Forms(), sffxs{}, []operand.Op{k, xyz}) } -// PADDW: Add Packed Word Integers. +// VPMOVM2D: Expand Bits of Mask Register to Packed Doubleword Integers. // // Forms: // -// PADDW xmm xmm -// PADDW m128 xmm -func PADDW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PADDW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PADDW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PADDW: bad operands") +// VPMOVM2D k xmm +// VPMOVM2D k ymm +// VPMOVM2D k zmm +func VPMOVM2D(k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVM2D.Forms(), sffxs{}, []operand.Op{k, xyz}) } -// PALIGNR: Packed Align Right. +// VPMOVM2Q: Expand Bits of Mask Register to Packed Quadword Integers. // // Forms: // -// PALIGNR imm8 xmm xmm -// PALIGNR imm8 m128 xmm -func PALIGNR(i, mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PALIGNR", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PALIGNR", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - }, nil - } - return nil, errors.New("PALIGNR: bad operands") +// VPMOVM2Q k xmm +// VPMOVM2Q k ymm +// VPMOVM2Q k zmm +func VPMOVM2Q(k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVM2Q.Forms(), sffxs{}, []operand.Op{k, xyz}) } -// PAND: Packed Bitwise Logical AND. +// VPMOVM2W: Expand Bits of Mask Register to Packed Word Integers. // // Forms: // -// PAND xmm xmm -// PAND m128 xmm -func PAND(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PAND", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PAND", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PAND: bad operands") +// VPMOVM2W k xmm +// VPMOVM2W k ymm +// VPMOVM2W k zmm +func VPMOVM2W(k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVM2W.Forms(), sffxs{}, []operand.Op{k, xyz}) } -// PANDN: Packed Bitwise Logical AND NOT. +// VPMOVMSKB: Move Byte Mask. // // Forms: // -// PANDN xmm xmm -// PANDN m128 xmm -func PANDN(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PANDN", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PANDN", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PANDN: bad operands") +// VPMOVMSKB ymm r32 +// VPMOVMSKB xmm r32 +func VPMOVMSKB(xy, r operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVMSKB.Forms(), sffxs{}, []operand.Op{xy, r}) } -// PAUSE: Spin Loop Hint. +// VPMOVQ2M: Move Signs of Packed Quadword Integers to Mask Register. // // Forms: // -// PAUSE -func PAUSE() (*intrep.Instruction, error) { - return &intrep.Instruction{ - Opcode: "PAUSE", - Operands: nil, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - }, nil +// VPMOVQ2M xmm k +// VPMOVQ2M ymm k +// VPMOVQ2M zmm k +func VPMOVQ2M(xyz, k operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVQ2M.Forms(), sffxs{}, []operand.Op{xyz, k}) } -// PAVGB: Average Packed Byte Integers. +// VPMOVQB: Down Convert Packed Quadword Values to Byte Values with Truncation. // // Forms: // -// PAVGB xmm xmm -// PAVGB m128 xmm -func PAVGB(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PAVGB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PAVGB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PAVGB: bad operands") +// VPMOVQB xmm k m16 +// VPMOVQB xmm k xmm +// VPMOVQB xmm m16 +// VPMOVQB xmm xmm +// VPMOVQB ymm k m32 +// VPMOVQB ymm k xmm +// VPMOVQB ymm m32 +// VPMOVQB ymm xmm +// VPMOVQB zmm k m64 +// VPMOVQB zmm k xmm +// VPMOVQB zmm m64 +// VPMOVQB zmm xmm +func VPMOVQB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVQB.Forms(), sffxs{}, ops) } -// PAVGW: Average Packed Word Integers. +// VPMOVQB_Z: Down Convert Packed Quadword Values to Byte Values with Truncation (Zeroing Masking). // // Forms: // -// PAVGW xmm xmm -// PAVGW m128 xmm -func PAVGW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PAVGW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PAVGW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PAVGW: bad operands") +// VPMOVQB.Z xmm k m16 +// VPMOVQB.Z xmm k xmm +// VPMOVQB.Z ymm k m32 +// VPMOVQB.Z ymm k xmm +// VPMOVQB.Z zmm k m64 +// VPMOVQB.Z zmm k xmm +func VPMOVQB_Z(xyz, k, mx operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVQB.Forms(), sffxs{sffxZ}, []operand.Op{xyz, k, mx}) } -// PBLENDVB: Variable Blend Packed Bytes. +// VPMOVQD: Down Convert Packed Quadword Values to Doubleword Values with Truncation. // // Forms: // -// PBLENDVB xmm0 xmm xmm -// PBLENDVB xmm0 m128 xmm -func PBLENDVB(x, mx, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM0(x) && operand.IsXMM(mx) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "PBLENDVB", - Operands: []operand.Op{x, mx, x1}, - Inputs: []operand.Op{x, mx, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsXMM0(x) && operand.IsM128(mx) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "PBLENDVB", - Operands: []operand.Op{x, mx, x1}, - Inputs: []operand.Op{x, mx, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PBLENDVB: bad operands") +// VPMOVQD xmm k m64 +// VPMOVQD xmm k xmm +// VPMOVQD xmm m64 +// VPMOVQD xmm xmm +// VPMOVQD ymm k m128 +// VPMOVQD ymm k xmm +// VPMOVQD ymm m128 +// VPMOVQD ymm xmm +// VPMOVQD zmm k m256 +// VPMOVQD zmm k ymm +// VPMOVQD zmm m256 +// VPMOVQD zmm ymm +func VPMOVQD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVQD.Forms(), sffxs{}, ops) } -// PBLENDW: Blend Packed Words. +// VPMOVQD_Z: Down Convert Packed Quadword Values to Doubleword Values with Truncation (Zeroing Masking). // // Forms: // -// PBLENDW imm8 xmm xmm -// PBLENDW imm8 m128 xmm -func PBLENDW(i, mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PBLENDW", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PBLENDW", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PBLENDW: bad operands") +// VPMOVQD.Z xmm k m64 +// VPMOVQD.Z xmm k xmm +// VPMOVQD.Z ymm k m128 +// VPMOVQD.Z ymm k xmm +// VPMOVQD.Z zmm k m256 +// VPMOVQD.Z zmm k ymm +func VPMOVQD_Z(xyz, k, mxy operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVQD.Forms(), sffxs{sffxZ}, []operand.Op{xyz, k, mxy}) } -// PCLMULQDQ: Carry-Less Quadword Multiplication. +// VPMOVQW: Down Convert Packed Quadword Values to Word Values with Truncation. // // Forms: // -// PCLMULQDQ imm8 xmm xmm -// PCLMULQDQ imm8 m128 xmm -func PCLMULQDQ(i, mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PCLMULQDQ", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"PCLMULQDQ"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PCLMULQDQ", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"PCLMULQDQ"}, - }, nil - } - return nil, errors.New("PCLMULQDQ: bad operands") +// VPMOVQW xmm k m32 +// VPMOVQW xmm k xmm +// VPMOVQW xmm m32 +// VPMOVQW xmm xmm +// VPMOVQW ymm k m64 +// VPMOVQW ymm k xmm +// VPMOVQW ymm m64 +// VPMOVQW ymm xmm +// VPMOVQW zmm k m128 +// VPMOVQW zmm k xmm +// VPMOVQW zmm m128 +// VPMOVQW zmm xmm +func VPMOVQW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVQW.Forms(), sffxs{}, ops) } -// PCMPEQB: Compare Packed Byte Data for Equality. +// VPMOVQW_Z: Down Convert Packed Quadword Values to Word Values with Truncation (Zeroing Masking). // // Forms: // -// PCMPEQB xmm xmm -// PCMPEQB m128 xmm -func PCMPEQB(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PCMPEQB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PCMPEQB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PCMPEQB: bad operands") +// VPMOVQW.Z xmm k m32 +// VPMOVQW.Z xmm k xmm +// VPMOVQW.Z ymm k m64 +// VPMOVQW.Z ymm k xmm +// VPMOVQW.Z zmm k m128 +// VPMOVQW.Z zmm k xmm +func VPMOVQW_Z(xyz, k, mx operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVQW.Forms(), sffxs{sffxZ}, []operand.Op{xyz, k, mx}) } -// PCMPEQL: Compare Packed Doubleword Data for Equality. +// VPMOVSDB: Down Convert Packed Doubleword Values to Byte Values with Signed Saturation. // // Forms: // -// PCMPEQL xmm xmm -// PCMPEQL m128 xmm -func PCMPEQL(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PCMPEQL", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PCMPEQL", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PCMPEQL: bad operands") +// VPMOVSDB xmm k m32 +// VPMOVSDB xmm k xmm +// VPMOVSDB xmm m32 +// VPMOVSDB xmm xmm +// VPMOVSDB ymm k m64 +// VPMOVSDB ymm k xmm +// VPMOVSDB ymm m64 +// VPMOVSDB ymm xmm +// VPMOVSDB zmm k m128 +// VPMOVSDB zmm k xmm +// VPMOVSDB zmm m128 +// VPMOVSDB zmm xmm +func VPMOVSDB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVSDB.Forms(), sffxs{}, ops) } -// PCMPEQQ: Compare Packed Quadword Data for Equality. +// VPMOVSDB_Z: Down Convert Packed Doubleword Values to Byte Values with Signed Saturation (Zeroing Masking). // // Forms: // -// PCMPEQQ xmm xmm -// PCMPEQQ m128 xmm -func PCMPEQQ(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PCMPEQQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PCMPEQQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PCMPEQQ: bad operands") +// VPMOVSDB.Z xmm k m32 +// VPMOVSDB.Z xmm k xmm +// VPMOVSDB.Z ymm k m64 +// VPMOVSDB.Z ymm k xmm +// VPMOVSDB.Z zmm k m128 +// VPMOVSDB.Z zmm k xmm +func VPMOVSDB_Z(xyz, k, mx operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVSDB.Forms(), sffxs{sffxZ}, []operand.Op{xyz, k, mx}) } -// PCMPEQW: Compare Packed Word Data for Equality. +// VPMOVSDW: Down Convert Packed Doubleword Values to Word Values with Signed Saturation. // // Forms: // -// PCMPEQW xmm xmm -// PCMPEQW m128 xmm -func PCMPEQW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PCMPEQW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PCMPEQW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PCMPEQW: bad operands") +// VPMOVSDW xmm k m64 +// VPMOVSDW xmm k xmm +// VPMOVSDW xmm m64 +// VPMOVSDW xmm xmm +// VPMOVSDW ymm k m128 +// VPMOVSDW ymm k xmm +// VPMOVSDW ymm m128 +// VPMOVSDW ymm xmm +// VPMOVSDW zmm k m256 +// VPMOVSDW zmm k ymm +// VPMOVSDW zmm m256 +// VPMOVSDW zmm ymm +func VPMOVSDW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVSDW.Forms(), sffxs{}, ops) } -// PCMPESTRI: Packed Compare Explicit Length Strings, Return Index. +// VPMOVSDW_Z: Down Convert Packed Doubleword Values to Word Values with Signed Saturation (Zeroing Masking). // // Forms: // -// PCMPESTRI imm8 xmm xmm -// PCMPESTRI imm8 m128 xmm -func PCMPESTRI(i, mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PCMPESTRI", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x, reg.EAX, reg.EDX}, - Outputs: []operand.Op{reg.ECX}, - ISA: []string{"SSE4.2"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PCMPESTRI", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x, reg.EAX, reg.EDX}, - Outputs: []operand.Op{reg.ECX}, - ISA: []string{"SSE4.2"}, - }, nil - } - return nil, errors.New("PCMPESTRI: bad operands") +// VPMOVSDW.Z xmm k m64 +// VPMOVSDW.Z xmm k xmm +// VPMOVSDW.Z ymm k m128 +// VPMOVSDW.Z ymm k xmm +// VPMOVSDW.Z zmm k m256 +// VPMOVSDW.Z zmm k ymm +func VPMOVSDW_Z(xyz, k, mxy operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVSDW.Forms(), sffxs{sffxZ}, []operand.Op{xyz, k, mxy}) } -// PCMPESTRM: Packed Compare Explicit Length Strings, Return Mask. +// VPMOVSQB: Down Convert Packed Quadword Values to Byte Values with Signed Saturation. // // Forms: // -// PCMPESTRM imm8 xmm xmm -// PCMPESTRM imm8 m128 xmm -func PCMPESTRM(i, mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PCMPESTRM", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x, reg.EAX, reg.EDX}, - Outputs: []operand.Op{reg.X0}, - ISA: []string{"SSE4.2"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PCMPESTRM", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x, reg.EAX, reg.EDX}, - Outputs: []operand.Op{reg.X0}, - ISA: []string{"SSE4.2"}, - }, nil - } - return nil, errors.New("PCMPESTRM: bad operands") +// VPMOVSQB xmm k m16 +// VPMOVSQB xmm k xmm +// VPMOVSQB xmm m16 +// VPMOVSQB xmm xmm +// VPMOVSQB ymm k m32 +// VPMOVSQB ymm k xmm +// VPMOVSQB ymm m32 +// VPMOVSQB ymm xmm +// VPMOVSQB zmm k m64 +// VPMOVSQB zmm k xmm +// VPMOVSQB zmm m64 +// VPMOVSQB zmm xmm +func VPMOVSQB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVSQB.Forms(), sffxs{}, ops) } -// PCMPGTB: Compare Packed Signed Byte Integers for Greater Than. +// VPMOVSQB_Z: Down Convert Packed Quadword Values to Byte Values with Signed Saturation (Zeroing Masking). // // Forms: // -// PCMPGTB xmm xmm -// PCMPGTB m128 xmm -func PCMPGTB(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PCMPGTB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PCMPGTB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PCMPGTB: bad operands") +// VPMOVSQB.Z xmm k m16 +// VPMOVSQB.Z xmm k xmm +// VPMOVSQB.Z ymm k m32 +// VPMOVSQB.Z ymm k xmm +// VPMOVSQB.Z zmm k m64 +// VPMOVSQB.Z zmm k xmm +func VPMOVSQB_Z(xyz, k, mx operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVSQB.Forms(), sffxs{sffxZ}, []operand.Op{xyz, k, mx}) } -// PCMPGTL: Compare Packed Signed Doubleword Integers for Greater Than. +// VPMOVSQD: Down Convert Packed Quadword Values to Doubleword Values with Signed Saturation. // // Forms: // -// PCMPGTL xmm xmm -// PCMPGTL m128 xmm -func PCMPGTL(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PCMPGTL", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PCMPGTL", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PCMPGTL: bad operands") +// VPMOVSQD xmm k m64 +// VPMOVSQD xmm k xmm +// VPMOVSQD xmm m64 +// VPMOVSQD xmm xmm +// VPMOVSQD ymm k m128 +// VPMOVSQD ymm k xmm +// VPMOVSQD ymm m128 +// VPMOVSQD ymm xmm +// VPMOVSQD zmm k m256 +// VPMOVSQD zmm k ymm +// VPMOVSQD zmm m256 +// VPMOVSQD zmm ymm +func VPMOVSQD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVSQD.Forms(), sffxs{}, ops) } -// PCMPGTQ: Compare Packed Data for Greater Than. +// VPMOVSQD_Z: Down Convert Packed Quadword Values to Doubleword Values with Signed Saturation (Zeroing Masking). // // Forms: // -// PCMPGTQ xmm xmm -// PCMPGTQ m128 xmm -func PCMPGTQ(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PCMPGTQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.2"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PCMPGTQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.2"}, - }, nil - } - return nil, errors.New("PCMPGTQ: bad operands") +// VPMOVSQD.Z xmm k m64 +// VPMOVSQD.Z xmm k xmm +// VPMOVSQD.Z ymm k m128 +// VPMOVSQD.Z ymm k xmm +// VPMOVSQD.Z zmm k m256 +// VPMOVSQD.Z zmm k ymm +func VPMOVSQD_Z(xyz, k, mxy operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVSQD.Forms(), sffxs{sffxZ}, []operand.Op{xyz, k, mxy}) } -// PCMPGTW: Compare Packed Signed Word Integers for Greater Than. +// VPMOVSQW: Down Convert Packed Quadword Values to Word Values with Signed Saturation. // // Forms: // -// PCMPGTW xmm xmm -// PCMPGTW m128 xmm -func PCMPGTW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PCMPGTW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PCMPGTW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PCMPGTW: bad operands") +// VPMOVSQW xmm k m32 +// VPMOVSQW xmm k xmm +// VPMOVSQW xmm m32 +// VPMOVSQW xmm xmm +// VPMOVSQW ymm k m64 +// VPMOVSQW ymm k xmm +// VPMOVSQW ymm m64 +// VPMOVSQW ymm xmm +// VPMOVSQW zmm k m128 +// VPMOVSQW zmm k xmm +// VPMOVSQW zmm m128 +// VPMOVSQW zmm xmm +func VPMOVSQW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVSQW.Forms(), sffxs{}, ops) } -// PCMPISTRI: Packed Compare Implicit Length Strings, Return Index. +// VPMOVSQW_Z: Down Convert Packed Quadword Values to Word Values with Signed Saturation (Zeroing Masking). // // Forms: // -// PCMPISTRI imm8 xmm xmm -// PCMPISTRI imm8 m128 xmm -func PCMPISTRI(i, mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PCMPISTRI", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{reg.ECX}, - ISA: []string{"SSE4.2"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PCMPISTRI", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{reg.ECX}, - ISA: []string{"SSE4.2"}, - }, nil - } - return nil, errors.New("PCMPISTRI: bad operands") +// VPMOVSQW.Z xmm k m32 +// VPMOVSQW.Z xmm k xmm +// VPMOVSQW.Z ymm k m64 +// VPMOVSQW.Z ymm k xmm +// VPMOVSQW.Z zmm k m128 +// VPMOVSQW.Z zmm k xmm +func VPMOVSQW_Z(xyz, k, mx operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVSQW.Forms(), sffxs{sffxZ}, []operand.Op{xyz, k, mx}) } -// PCMPISTRM: Packed Compare Implicit Length Strings, Return Mask. +// VPMOVSWB: Down Convert Packed Word Values to Byte Values with Signed Saturation. // // Forms: // -// PCMPISTRM imm8 xmm xmm -// PCMPISTRM imm8 m128 xmm -func PCMPISTRM(i, mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PCMPISTRM", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{reg.X0}, - ISA: []string{"SSE4.2"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PCMPISTRM", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{reg.X0}, - ISA: []string{"SSE4.2"}, - }, nil - } - return nil, errors.New("PCMPISTRM: bad operands") +// VPMOVSWB xmm k m64 +// VPMOVSWB xmm k xmm +// VPMOVSWB xmm m64 +// VPMOVSWB xmm xmm +// VPMOVSWB ymm k m128 +// VPMOVSWB ymm k xmm +// VPMOVSWB ymm m128 +// VPMOVSWB ymm xmm +// VPMOVSWB zmm k m256 +// VPMOVSWB zmm k ymm +// VPMOVSWB zmm m256 +// VPMOVSWB zmm ymm +func VPMOVSWB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVSWB.Forms(), sffxs{}, ops) } -// PDEPL: Parallel Bits Deposit. +// VPMOVSWB_Z: Down Convert Packed Word Values to Byte Values with Signed Saturation (Zeroing Masking). // // Forms: // -// PDEPL r32 r32 r32 -// PDEPL m32 r32 r32 -func PDEPL(mr, r, r1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR32(r) && operand.IsR32(r1): - return &intrep.Instruction{ - Opcode: "PDEPL", - Operands: []operand.Op{mr, r, r1}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI2"}, - }, nil - case operand.IsM32(mr) && operand.IsR32(r) && operand.IsR32(r1): - return &intrep.Instruction{ - Opcode: "PDEPL", - Operands: []operand.Op{mr, r, r1}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI2"}, - }, nil - } - return nil, errors.New("PDEPL: bad operands") +// VPMOVSWB.Z xmm k m64 +// VPMOVSWB.Z xmm k xmm +// VPMOVSWB.Z ymm k m128 +// VPMOVSWB.Z ymm k xmm +// VPMOVSWB.Z zmm k m256 +// VPMOVSWB.Z zmm k ymm +func VPMOVSWB_Z(xyz, k, mxy operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVSWB.Forms(), sffxs{sffxZ}, []operand.Op{xyz, k, mxy}) } -// PDEPQ: Parallel Bits Deposit. +// VPMOVSXBD: Move Packed Byte Integers to Doubleword Integers with Sign Extension. // // Forms: // -// PDEPQ r64 r64 r64 -// PDEPQ m64 r64 r64 -func PDEPQ(mr, r, r1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsR64(r) && operand.IsR64(r1): - return &intrep.Instruction{ - Opcode: "PDEPQ", - Operands: []operand.Op{mr, r, r1}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI2"}, - }, nil - case operand.IsM64(mr) && operand.IsR64(r) && operand.IsR64(r1): - return &intrep.Instruction{ - Opcode: "PDEPQ", - Operands: []operand.Op{mr, r, r1}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI2"}, - }, nil - } - return nil, errors.New("PDEPQ: bad operands") +// VPMOVSXBD m64 ymm +// VPMOVSXBD xmm ymm +// VPMOVSXBD m32 xmm +// VPMOVSXBD xmm xmm +// VPMOVSXBD m32 k xmm +// VPMOVSXBD m64 k ymm +// VPMOVSXBD xmm k xmm +// VPMOVSXBD xmm k ymm +// VPMOVSXBD m128 k zmm +// VPMOVSXBD m128 zmm +// VPMOVSXBD xmm k zmm +// VPMOVSXBD xmm zmm +func VPMOVSXBD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVSXBD.Forms(), sffxs{}, ops) } -// PEXTL: Parallel Bits Extract. +// VPMOVSXBD_Z: Move Packed Byte Integers to Doubleword Integers with Sign Extension (Zeroing Masking). // // Forms: // -// PEXTL r32 r32 r32 -// PEXTL m32 r32 r32 -func PEXTL(mr, r, r1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR32(r) && operand.IsR32(r1): - return &intrep.Instruction{ - Opcode: "PEXTL", - Operands: []operand.Op{mr, r, r1}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI2"}, - }, nil - case operand.IsM32(mr) && operand.IsR32(r) && operand.IsR32(r1): - return &intrep.Instruction{ - Opcode: "PEXTL", - Operands: []operand.Op{mr, r, r1}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI2"}, - }, nil - } - return nil, errors.New("PEXTL: bad operands") +// VPMOVSXBD.Z m32 k xmm +// VPMOVSXBD.Z m64 k ymm +// VPMOVSXBD.Z xmm k xmm +// VPMOVSXBD.Z xmm k ymm +// VPMOVSXBD.Z m128 k zmm +// VPMOVSXBD.Z xmm k zmm +func VPMOVSXBD_Z(mx, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVSXBD.Forms(), sffxs{sffxZ}, []operand.Op{mx, k, xyz}) } -// PEXTQ: Parallel Bits Extract. +// VPMOVSXBQ: Move Packed Byte Integers to Quadword Integers with Sign Extension. // // Forms: // -// PEXTQ r64 r64 r64 -// PEXTQ m64 r64 r64 -func PEXTQ(mr, r, r1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsR64(r) && operand.IsR64(r1): - return &intrep.Instruction{ - Opcode: "PEXTQ", - Operands: []operand.Op{mr, r, r1}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI2"}, - }, nil - case operand.IsM64(mr) && operand.IsR64(r) && operand.IsR64(r1): - return &intrep.Instruction{ - Opcode: "PEXTQ", - Operands: []operand.Op{mr, r, r1}, - Inputs: []operand.Op{mr, r}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI2"}, - }, nil - } - return nil, errors.New("PEXTQ: bad operands") +// VPMOVSXBQ m32 ymm +// VPMOVSXBQ xmm ymm +// VPMOVSXBQ m16 xmm +// VPMOVSXBQ xmm xmm +// VPMOVSXBQ m16 k xmm +// VPMOVSXBQ m32 k ymm +// VPMOVSXBQ xmm k xmm +// VPMOVSXBQ xmm k ymm +// VPMOVSXBQ m64 k zmm +// VPMOVSXBQ m64 zmm +// VPMOVSXBQ xmm k zmm +// VPMOVSXBQ xmm zmm +func VPMOVSXBQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVSXBQ.Forms(), sffxs{}, ops) } -// PEXTRB: Extract Byte. +// VPMOVSXBQ_Z: Move Packed Byte Integers to Quadword Integers with Sign Extension (Zeroing Masking). // // Forms: // -// PEXTRB imm8 xmm r32 -// PEXTRB imm8 xmm m8 -func PEXTRB(i, x, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(x) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "PEXTRB", - Operands: []operand.Op{i, x, mr}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{mr}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsIMM8(i) && operand.IsXMM(x) && operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "PEXTRB", - Operands: []operand.Op{i, x, mr}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{mr}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PEXTRB: bad operands") +// VPMOVSXBQ.Z m16 k xmm +// VPMOVSXBQ.Z m32 k ymm +// VPMOVSXBQ.Z xmm k xmm +// VPMOVSXBQ.Z xmm k ymm +// VPMOVSXBQ.Z m64 k zmm +// VPMOVSXBQ.Z xmm k zmm +func VPMOVSXBQ_Z(mx, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVSXBQ.Forms(), sffxs{sffxZ}, []operand.Op{mx, k, xyz}) } -// PEXTRD: Extract Doubleword. +// VPMOVSXBW: Move Packed Byte Integers to Word Integers with Sign Extension. // // Forms: // -// PEXTRD imm8 xmm r32 -// PEXTRD imm8 xmm m32 -func PEXTRD(i, x, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(x) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "PEXTRD", - Operands: []operand.Op{i, x, mr}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{mr}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsIMM8(i) && operand.IsXMM(x) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "PEXTRD", - Operands: []operand.Op{i, x, mr}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{mr}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PEXTRD: bad operands") +// VPMOVSXBW m128 ymm +// VPMOVSXBW xmm ymm +// VPMOVSXBW m64 xmm +// VPMOVSXBW xmm xmm +// VPMOVSXBW m128 k ymm +// VPMOVSXBW m64 k xmm +// VPMOVSXBW xmm k xmm +// VPMOVSXBW xmm k ymm +// VPMOVSXBW m256 k zmm +// VPMOVSXBW m256 zmm +// VPMOVSXBW ymm k zmm +// VPMOVSXBW ymm zmm +func VPMOVSXBW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVSXBW.Forms(), sffxs{}, ops) } -// PEXTRQ: Extract Quadword. +// VPMOVSXBW_Z: Move Packed Byte Integers to Word Integers with Sign Extension (Zeroing Masking). // // Forms: // -// PEXTRQ imm8 xmm r64 -// PEXTRQ imm8 xmm m64 -func PEXTRQ(i, x, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(x) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "PEXTRQ", - Operands: []operand.Op{i, x, mr}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{mr}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsIMM8(i) && operand.IsXMM(x) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "PEXTRQ", - Operands: []operand.Op{i, x, mr}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{mr}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PEXTRQ: bad operands") +// VPMOVSXBW.Z m128 k ymm +// VPMOVSXBW.Z m64 k xmm +// VPMOVSXBW.Z xmm k xmm +// VPMOVSXBW.Z xmm k ymm +// VPMOVSXBW.Z m256 k zmm +// VPMOVSXBW.Z ymm k zmm +func VPMOVSXBW_Z(mxy, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVSXBW.Forms(), sffxs{sffxZ}, []operand.Op{mxy, k, xyz}) } -// PEXTRW: Extract Word. +// VPMOVSXDQ: Move Packed Doubleword Integers to Quadword Integers with Sign Extension. // // Forms: // -// PEXTRW imm8 xmm r32 -// PEXTRW imm8 xmm m16 -func PEXTRW(i, x, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(x) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "PEXTRW", - Operands: []operand.Op{i, x, mr}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{mr}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsIMM8(i) && operand.IsXMM(x) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "PEXTRW", - Operands: []operand.Op{i, x, mr}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{mr}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PEXTRW: bad operands") +// VPMOVSXDQ m128 ymm +// VPMOVSXDQ xmm ymm +// VPMOVSXDQ m64 xmm +// VPMOVSXDQ xmm xmm +// VPMOVSXDQ m128 k ymm +// VPMOVSXDQ m64 k xmm +// VPMOVSXDQ xmm k xmm +// VPMOVSXDQ xmm k ymm +// VPMOVSXDQ m256 k zmm +// VPMOVSXDQ m256 zmm +// VPMOVSXDQ ymm k zmm +// VPMOVSXDQ ymm zmm +func VPMOVSXDQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVSXDQ.Forms(), sffxs{}, ops) } -// PHADDD: Packed Horizontal Add Doubleword Integer. +// VPMOVSXDQ_Z: Move Packed Doubleword Integers to Quadword Integers with Sign Extension (Zeroing Masking). // // Forms: // -// PHADDD xmm xmm -// PHADDD m128 xmm -func PHADDD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PHADDD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PHADDD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - }, nil - } - return nil, errors.New("PHADDD: bad operands") +// VPMOVSXDQ.Z m128 k ymm +// VPMOVSXDQ.Z m64 k xmm +// VPMOVSXDQ.Z xmm k xmm +// VPMOVSXDQ.Z xmm k ymm +// VPMOVSXDQ.Z m256 k zmm +// VPMOVSXDQ.Z ymm k zmm +func VPMOVSXDQ_Z(mxy, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVSXDQ.Forms(), sffxs{sffxZ}, []operand.Op{mxy, k, xyz}) } -// PHADDSW: Packed Horizontal Add Signed Word Integers with Signed Saturation. +// VPMOVSXWD: Move Packed Word Integers to Doubleword Integers with Sign Extension. // // Forms: // -// PHADDSW xmm xmm -// PHADDSW m128 xmm -func PHADDSW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PHADDSW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PHADDSW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - }, nil - } - return nil, errors.New("PHADDSW: bad operands") +// VPMOVSXWD m128 ymm +// VPMOVSXWD xmm ymm +// VPMOVSXWD m64 xmm +// VPMOVSXWD xmm xmm +// VPMOVSXWD m128 k ymm +// VPMOVSXWD m64 k xmm +// VPMOVSXWD xmm k xmm +// VPMOVSXWD xmm k ymm +// VPMOVSXWD m256 k zmm +// VPMOVSXWD m256 zmm +// VPMOVSXWD ymm k zmm +// VPMOVSXWD ymm zmm +func VPMOVSXWD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVSXWD.Forms(), sffxs{}, ops) } -// PHADDW: Packed Horizontal Add Word Integers. +// VPMOVSXWD_Z: Move Packed Word Integers to Doubleword Integers with Sign Extension (Zeroing Masking). // // Forms: // -// PHADDW xmm xmm -// PHADDW m128 xmm -func PHADDW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PHADDW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PHADDW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - }, nil - } - return nil, errors.New("PHADDW: bad operands") +// VPMOVSXWD.Z m128 k ymm +// VPMOVSXWD.Z m64 k xmm +// VPMOVSXWD.Z xmm k xmm +// VPMOVSXWD.Z xmm k ymm +// VPMOVSXWD.Z m256 k zmm +// VPMOVSXWD.Z ymm k zmm +func VPMOVSXWD_Z(mxy, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVSXWD.Forms(), sffxs{sffxZ}, []operand.Op{mxy, k, xyz}) } -// PHMINPOSUW: Packed Horizontal Minimum of Unsigned Word Integers. +// VPMOVSXWQ: Move Packed Word Integers to Quadword Integers with Sign Extension. // // Forms: // -// PHMINPOSUW xmm xmm -// PHMINPOSUW m128 xmm -func PHMINPOSUW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PHMINPOSUW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PHMINPOSUW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PHMINPOSUW: bad operands") +// VPMOVSXWQ m64 ymm +// VPMOVSXWQ xmm ymm +// VPMOVSXWQ m32 xmm +// VPMOVSXWQ xmm xmm +// VPMOVSXWQ m32 k xmm +// VPMOVSXWQ m64 k ymm +// VPMOVSXWQ xmm k xmm +// VPMOVSXWQ xmm k ymm +// VPMOVSXWQ m128 k zmm +// VPMOVSXWQ m128 zmm +// VPMOVSXWQ xmm k zmm +// VPMOVSXWQ xmm zmm +func VPMOVSXWQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVSXWQ.Forms(), sffxs{}, ops) } -// PHSUBD: Packed Horizontal Subtract Doubleword Integers. +// VPMOVSXWQ_Z: Move Packed Word Integers to Quadword Integers with Sign Extension (Zeroing Masking). // // Forms: // -// PHSUBD xmm xmm -// PHSUBD m128 xmm -func PHSUBD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PHSUBD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PHSUBD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - }, nil - } - return nil, errors.New("PHSUBD: bad operands") +// VPMOVSXWQ.Z m32 k xmm +// VPMOVSXWQ.Z m64 k ymm +// VPMOVSXWQ.Z xmm k xmm +// VPMOVSXWQ.Z xmm k ymm +// VPMOVSXWQ.Z m128 k zmm +// VPMOVSXWQ.Z xmm k zmm +func VPMOVSXWQ_Z(mx, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVSXWQ.Forms(), sffxs{sffxZ}, []operand.Op{mx, k, xyz}) } -// PHSUBSW: Packed Horizontal Subtract Signed Word Integers with Signed Saturation. +// VPMOVUSDB: Down Convert Packed Doubleword Values to Byte Values with Unsigned Saturation. // // Forms: // -// PHSUBSW xmm xmm -// PHSUBSW m128 xmm -func PHSUBSW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PHSUBSW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PHSUBSW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - }, nil - } - return nil, errors.New("PHSUBSW: bad operands") +// VPMOVUSDB xmm k m32 +// VPMOVUSDB xmm k xmm +// VPMOVUSDB xmm m32 +// VPMOVUSDB xmm xmm +// VPMOVUSDB ymm k m64 +// VPMOVUSDB ymm k xmm +// VPMOVUSDB ymm m64 +// VPMOVUSDB ymm xmm +// VPMOVUSDB zmm k m128 +// VPMOVUSDB zmm k xmm +// VPMOVUSDB zmm m128 +// VPMOVUSDB zmm xmm +func VPMOVUSDB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVUSDB.Forms(), sffxs{}, ops) } -// PHSUBW: Packed Horizontal Subtract Word Integers. +// VPMOVUSDB_Z: Down Convert Packed Doubleword Values to Byte Values with Unsigned Saturation (Zeroing Masking). // // Forms: // -// PHSUBW xmm xmm -// PHSUBW m128 xmm -func PHSUBW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PHSUBW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PHSUBW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - }, nil - } - return nil, errors.New("PHSUBW: bad operands") +// VPMOVUSDB.Z xmm k m32 +// VPMOVUSDB.Z xmm k xmm +// VPMOVUSDB.Z ymm k m64 +// VPMOVUSDB.Z ymm k xmm +// VPMOVUSDB.Z zmm k m128 +// VPMOVUSDB.Z zmm k xmm +func VPMOVUSDB_Z(xyz, k, mx operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVUSDB.Forms(), sffxs{sffxZ}, []operand.Op{xyz, k, mx}) } -// PINSRB: Insert Byte. +// VPMOVUSDW: Down Convert Packed Doubleword Values to Word Values with Unsigned Saturation. // // Forms: // -// PINSRB imm8 r32 xmm -// PINSRB imm8 m8 xmm -func PINSRB(i, mr, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsR32(mr) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PINSRB", - Operands: []operand.Op{i, mr, x}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsIMM8(i) && operand.IsM8(mr) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PINSRB", - Operands: []operand.Op{i, mr, x}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PINSRB: bad operands") +// VPMOVUSDW xmm k m64 +// VPMOVUSDW xmm k xmm +// VPMOVUSDW xmm m64 +// VPMOVUSDW xmm xmm +// VPMOVUSDW ymm k m128 +// VPMOVUSDW ymm k xmm +// VPMOVUSDW ymm m128 +// VPMOVUSDW ymm xmm +// VPMOVUSDW zmm k m256 +// VPMOVUSDW zmm k ymm +// VPMOVUSDW zmm m256 +// VPMOVUSDW zmm ymm +func VPMOVUSDW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVUSDW.Forms(), sffxs{}, ops) } -// PINSRD: Insert Doubleword. +// VPMOVUSDW_Z: Down Convert Packed Doubleword Values to Word Values with Unsigned Saturation (Zeroing Masking). // // Forms: // -// PINSRD imm8 r32 xmm -// PINSRD imm8 m32 xmm -func PINSRD(i, mr, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsR32(mr) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PINSRD", - Operands: []operand.Op{i, mr, x}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsIMM8(i) && operand.IsM32(mr) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PINSRD", - Operands: []operand.Op{i, mr, x}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PINSRD: bad operands") +// VPMOVUSDW.Z xmm k m64 +// VPMOVUSDW.Z xmm k xmm +// VPMOVUSDW.Z ymm k m128 +// VPMOVUSDW.Z ymm k xmm +// VPMOVUSDW.Z zmm k m256 +// VPMOVUSDW.Z zmm k ymm +func VPMOVUSDW_Z(xyz, k, mxy operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVUSDW.Forms(), sffxs{sffxZ}, []operand.Op{xyz, k, mxy}) } -// PINSRQ: Insert Quadword. +// VPMOVUSQB: Down Convert Packed Quadword Values to Byte Values with Unsigned Saturation. // // Forms: // -// PINSRQ imm8 r64 xmm -// PINSRQ imm8 m64 xmm -func PINSRQ(i, mr, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsR64(mr) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PINSRQ", - Operands: []operand.Op{i, mr, x}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsIMM8(i) && operand.IsM64(mr) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PINSRQ", - Operands: []operand.Op{i, mr, x}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PINSRQ: bad operands") +// VPMOVUSQB xmm k m16 +// VPMOVUSQB xmm k xmm +// VPMOVUSQB xmm m16 +// VPMOVUSQB xmm xmm +// VPMOVUSQB ymm k m32 +// VPMOVUSQB ymm k xmm +// VPMOVUSQB ymm m32 +// VPMOVUSQB ymm xmm +// VPMOVUSQB zmm k m64 +// VPMOVUSQB zmm k xmm +// VPMOVUSQB zmm m64 +// VPMOVUSQB zmm xmm +func VPMOVUSQB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVUSQB.Forms(), sffxs{}, ops) } -// PINSRW: Insert Word. +// VPMOVUSQB_Z: Down Convert Packed Quadword Values to Byte Values with Unsigned Saturation (Zeroing Masking). // // Forms: // -// PINSRW imm8 r32 xmm -// PINSRW imm8 m16 xmm -func PINSRW(i, mr, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsR32(mr) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PINSRW", - Operands: []operand.Op{i, mr, x}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsIMM8(i) && operand.IsM16(mr) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PINSRW", - Operands: []operand.Op{i, mr, x}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PINSRW: bad operands") +// VPMOVUSQB.Z xmm k m16 +// VPMOVUSQB.Z xmm k xmm +// VPMOVUSQB.Z ymm k m32 +// VPMOVUSQB.Z ymm k xmm +// VPMOVUSQB.Z zmm k m64 +// VPMOVUSQB.Z zmm k xmm +func VPMOVUSQB_Z(xyz, k, mx operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVUSQB.Forms(), sffxs{sffxZ}, []operand.Op{xyz, k, mx}) } -// PMADDUBSW: Multiply and Add Packed Signed and Unsigned Byte Integers. +// VPMOVUSQD: Down Convert Packed Quadword Values to Doubleword Values with Unsigned Saturation. // // Forms: // -// PMADDUBSW xmm xmm -// PMADDUBSW m128 xmm -func PMADDUBSW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMADDUBSW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMADDUBSW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - }, nil - } - return nil, errors.New("PMADDUBSW: bad operands") +// VPMOVUSQD xmm k m64 +// VPMOVUSQD xmm k xmm +// VPMOVUSQD xmm m64 +// VPMOVUSQD xmm xmm +// VPMOVUSQD ymm k m128 +// VPMOVUSQD ymm k xmm +// VPMOVUSQD ymm m128 +// VPMOVUSQD ymm xmm +// VPMOVUSQD zmm k m256 +// VPMOVUSQD zmm k ymm +// VPMOVUSQD zmm m256 +// VPMOVUSQD zmm ymm +func VPMOVUSQD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVUSQD.Forms(), sffxs{}, ops) } -// PMADDWL: Multiply and Add Packed Signed Word Integers. +// VPMOVUSQD_Z: Down Convert Packed Quadword Values to Doubleword Values with Unsigned Saturation (Zeroing Masking). // // Forms: // -// PMADDWL xmm xmm -// PMADDWL m128 xmm -func PMADDWL(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMADDWL", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMADDWL", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PMADDWL: bad operands") +// VPMOVUSQD.Z xmm k m64 +// VPMOVUSQD.Z xmm k xmm +// VPMOVUSQD.Z ymm k m128 +// VPMOVUSQD.Z ymm k xmm +// VPMOVUSQD.Z zmm k m256 +// VPMOVUSQD.Z zmm k ymm +func VPMOVUSQD_Z(xyz, k, mxy operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVUSQD.Forms(), sffxs{sffxZ}, []operand.Op{xyz, k, mxy}) } -// PMAXSB: Maximum of Packed Signed Byte Integers. +// VPMOVUSQW: Down Convert Packed Quadword Values to Word Values with Unsigned Saturation. // // Forms: // -// PMAXSB xmm xmm -// PMAXSB m128 xmm -func PMAXSB(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMAXSB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMAXSB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PMAXSB: bad operands") +// VPMOVUSQW xmm k m32 +// VPMOVUSQW xmm k xmm +// VPMOVUSQW xmm m32 +// VPMOVUSQW xmm xmm +// VPMOVUSQW ymm k m64 +// VPMOVUSQW ymm k xmm +// VPMOVUSQW ymm m64 +// VPMOVUSQW ymm xmm +// VPMOVUSQW zmm k m128 +// VPMOVUSQW zmm k xmm +// VPMOVUSQW zmm m128 +// VPMOVUSQW zmm xmm +func VPMOVUSQW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVUSQW.Forms(), sffxs{}, ops) } -// PMAXSD: Maximum of Packed Signed Doubleword Integers. +// VPMOVUSQW_Z: Down Convert Packed Quadword Values to Word Values with Unsigned Saturation (Zeroing Masking). // // Forms: // -// PMAXSD xmm xmm -// PMAXSD m128 xmm -func PMAXSD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMAXSD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMAXSD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PMAXSD: bad operands") +// VPMOVUSQW.Z xmm k m32 +// VPMOVUSQW.Z xmm k xmm +// VPMOVUSQW.Z ymm k m64 +// VPMOVUSQW.Z ymm k xmm +// VPMOVUSQW.Z zmm k m128 +// VPMOVUSQW.Z zmm k xmm +func VPMOVUSQW_Z(xyz, k, mx operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVUSQW.Forms(), sffxs{sffxZ}, []operand.Op{xyz, k, mx}) } -// PMAXSW: Maximum of Packed Signed Word Integers. +// VPMOVUSWB: Down Convert Packed Word Values to Byte Values with Unsigned Saturation. // // Forms: // -// PMAXSW xmm xmm -// PMAXSW m128 xmm -func PMAXSW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMAXSW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMAXSW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PMAXSW: bad operands") +// VPMOVUSWB xmm k m64 +// VPMOVUSWB xmm k xmm +// VPMOVUSWB xmm m64 +// VPMOVUSWB xmm xmm +// VPMOVUSWB ymm k m128 +// VPMOVUSWB ymm k xmm +// VPMOVUSWB ymm m128 +// VPMOVUSWB ymm xmm +// VPMOVUSWB zmm k m256 +// VPMOVUSWB zmm k ymm +// VPMOVUSWB zmm m256 +// VPMOVUSWB zmm ymm +func VPMOVUSWB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVUSWB.Forms(), sffxs{}, ops) } -// PMAXUB: Maximum of Packed Unsigned Byte Integers. +// VPMOVUSWB_Z: Down Convert Packed Word Values to Byte Values with Unsigned Saturation (Zeroing Masking). // // Forms: // -// PMAXUB xmm xmm -// PMAXUB m128 xmm -func PMAXUB(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMAXUB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMAXUB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PMAXUB: bad operands") +// VPMOVUSWB.Z xmm k m64 +// VPMOVUSWB.Z xmm k xmm +// VPMOVUSWB.Z ymm k m128 +// VPMOVUSWB.Z ymm k xmm +// VPMOVUSWB.Z zmm k m256 +// VPMOVUSWB.Z zmm k ymm +func VPMOVUSWB_Z(xyz, k, mxy operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVUSWB.Forms(), sffxs{sffxZ}, []operand.Op{xyz, k, mxy}) } -// PMAXUD: Maximum of Packed Unsigned Doubleword Integers. +// VPMOVW2M: Move Signs of Packed Word Integers to Mask Register. // // Forms: // -// PMAXUD xmm xmm -// PMAXUD m128 xmm -func PMAXUD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMAXUD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMAXUD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PMAXUD: bad operands") +// VPMOVW2M xmm k +// VPMOVW2M ymm k +// VPMOVW2M zmm k +func VPMOVW2M(xyz, k operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVW2M.Forms(), sffxs{}, []operand.Op{xyz, k}) } -// PMAXUW: Maximum of Packed Unsigned Word Integers. +// VPMOVWB: Down Convert Packed Word Values to Byte Values with Truncation. // // Forms: // -// PMAXUW xmm xmm -// PMAXUW m128 xmm -func PMAXUW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMAXUW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMAXUW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PMAXUW: bad operands") +// VPMOVWB xmm k m64 +// VPMOVWB xmm k xmm +// VPMOVWB xmm m64 +// VPMOVWB xmm xmm +// VPMOVWB ymm k m128 +// VPMOVWB ymm k xmm +// VPMOVWB ymm m128 +// VPMOVWB ymm xmm +// VPMOVWB zmm k m256 +// VPMOVWB zmm k ymm +// VPMOVWB zmm m256 +// VPMOVWB zmm ymm +func VPMOVWB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVWB.Forms(), sffxs{}, ops) } -// PMINSB: Minimum of Packed Signed Byte Integers. +// VPMOVWB_Z: Down Convert Packed Word Values to Byte Values with Truncation (Zeroing Masking). // // Forms: // -// PMINSB xmm xmm -// PMINSB m128 xmm -func PMINSB(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMINSB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMINSB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PMINSB: bad operands") +// VPMOVWB.Z xmm k m64 +// VPMOVWB.Z xmm k xmm +// VPMOVWB.Z ymm k m128 +// VPMOVWB.Z ymm k xmm +// VPMOVWB.Z zmm k m256 +// VPMOVWB.Z zmm k ymm +func VPMOVWB_Z(xyz, k, mxy operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVWB.Forms(), sffxs{sffxZ}, []operand.Op{xyz, k, mxy}) } -// PMINSD: Minimum of Packed Signed Doubleword Integers. +// VPMOVZXBD: Move Packed Byte Integers to Doubleword Integers with Zero Extension. // // Forms: // -// PMINSD xmm xmm -// PMINSD m128 xmm -func PMINSD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMINSD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMINSD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PMINSD: bad operands") +// VPMOVZXBD m64 ymm +// VPMOVZXBD xmm ymm +// VPMOVZXBD m32 xmm +// VPMOVZXBD xmm xmm +// VPMOVZXBD m32 k xmm +// VPMOVZXBD m64 k ymm +// VPMOVZXBD xmm k xmm +// VPMOVZXBD xmm k ymm +// VPMOVZXBD m128 k zmm +// VPMOVZXBD m128 zmm +// VPMOVZXBD xmm k zmm +// VPMOVZXBD xmm zmm +func VPMOVZXBD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVZXBD.Forms(), sffxs{}, ops) } -// PMINSW: Minimum of Packed Signed Word Integers. +// VPMOVZXBD_Z: Move Packed Byte Integers to Doubleword Integers with Zero Extension (Zeroing Masking). // // Forms: // -// PMINSW xmm xmm -// PMINSW m128 xmm -func PMINSW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMINSW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMINSW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PMINSW: bad operands") +// VPMOVZXBD.Z m32 k xmm +// VPMOVZXBD.Z m64 k ymm +// VPMOVZXBD.Z xmm k xmm +// VPMOVZXBD.Z xmm k ymm +// VPMOVZXBD.Z m128 k zmm +// VPMOVZXBD.Z xmm k zmm +func VPMOVZXBD_Z(mx, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVZXBD.Forms(), sffxs{sffxZ}, []operand.Op{mx, k, xyz}) } -// PMINUB: Minimum of Packed Unsigned Byte Integers. +// VPMOVZXBQ: Move Packed Byte Integers to Quadword Integers with Zero Extension. // // Forms: // -// PMINUB xmm xmm -// PMINUB m128 xmm -func PMINUB(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMINUB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMINUB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PMINUB: bad operands") +// VPMOVZXBQ m32 ymm +// VPMOVZXBQ xmm ymm +// VPMOVZXBQ m16 xmm +// VPMOVZXBQ xmm xmm +// VPMOVZXBQ m16 k xmm +// VPMOVZXBQ m32 k ymm +// VPMOVZXBQ xmm k xmm +// VPMOVZXBQ xmm k ymm +// VPMOVZXBQ m64 k zmm +// VPMOVZXBQ m64 zmm +// VPMOVZXBQ xmm k zmm +// VPMOVZXBQ xmm zmm +func VPMOVZXBQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVZXBQ.Forms(), sffxs{}, ops) } -// PMINUD: Minimum of Packed Unsigned Doubleword Integers. +// VPMOVZXBQ_Z: Move Packed Byte Integers to Quadword Integers with Zero Extension (Zeroing Masking). // // Forms: // -// PMINUD xmm xmm -// PMINUD m128 xmm -func PMINUD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMINUD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMINUD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PMINUD: bad operands") +// VPMOVZXBQ.Z m16 k xmm +// VPMOVZXBQ.Z m32 k ymm +// VPMOVZXBQ.Z xmm k xmm +// VPMOVZXBQ.Z xmm k ymm +// VPMOVZXBQ.Z m64 k zmm +// VPMOVZXBQ.Z xmm k zmm +func VPMOVZXBQ_Z(mx, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVZXBQ.Forms(), sffxs{sffxZ}, []operand.Op{mx, k, xyz}) } -// PMINUW: Minimum of Packed Unsigned Word Integers. +// VPMOVZXBW: Move Packed Byte Integers to Word Integers with Zero Extension. // // Forms: // -// PMINUW xmm xmm -// PMINUW m128 xmm -func PMINUW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMINUW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMINUW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PMINUW: bad operands") +// VPMOVZXBW m128 ymm +// VPMOVZXBW xmm ymm +// VPMOVZXBW m64 xmm +// VPMOVZXBW xmm xmm +// VPMOVZXBW m128 k ymm +// VPMOVZXBW m64 k xmm +// VPMOVZXBW xmm k xmm +// VPMOVZXBW xmm k ymm +// VPMOVZXBW m256 k zmm +// VPMOVZXBW m256 zmm +// VPMOVZXBW ymm k zmm +// VPMOVZXBW ymm zmm +func VPMOVZXBW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVZXBW.Forms(), sffxs{}, ops) } -// PMOVMSKB: Move Byte Mask. +// VPMOVZXBW_Z: Move Packed Byte Integers to Word Integers with Zero Extension (Zeroing Masking). // // Forms: // -// PMOVMSKB xmm r32 -func PMOVMSKB(x, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(x) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "PMOVMSKB", - Operands: []operand.Op{x, r}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{r}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PMOVMSKB: bad operands") +// VPMOVZXBW.Z m128 k ymm +// VPMOVZXBW.Z m64 k xmm +// VPMOVZXBW.Z xmm k xmm +// VPMOVZXBW.Z xmm k ymm +// VPMOVZXBW.Z m256 k zmm +// VPMOVZXBW.Z ymm k zmm +func VPMOVZXBW_Z(mxy, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVZXBW.Forms(), sffxs{sffxZ}, []operand.Op{mxy, k, xyz}) } -// PMOVSXBD: Move Packed Byte Integers to Doubleword Integers with Sign Extension. +// VPMOVZXDQ: Move Packed Doubleword Integers to Quadword Integers with Zero Extension. // // Forms: // -// PMOVSXBD xmm xmm -// PMOVSXBD m32 xmm -func PMOVSXBD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMOVSXBD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMOVSXBD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PMOVSXBD: bad operands") +// VPMOVZXDQ m128 ymm +// VPMOVZXDQ xmm ymm +// VPMOVZXDQ m64 xmm +// VPMOVZXDQ xmm xmm +// VPMOVZXDQ m128 k ymm +// VPMOVZXDQ m64 k xmm +// VPMOVZXDQ xmm k xmm +// VPMOVZXDQ xmm k ymm +// VPMOVZXDQ m256 k zmm +// VPMOVZXDQ m256 zmm +// VPMOVZXDQ ymm k zmm +// VPMOVZXDQ ymm zmm +func VPMOVZXDQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVZXDQ.Forms(), sffxs{}, ops) } -// PMOVSXBQ: Move Packed Byte Integers to Quadword Integers with Sign Extension. +// VPMOVZXDQ_Z: Move Packed Doubleword Integers to Quadword Integers with Zero Extension (Zeroing Masking). // // Forms: // -// PMOVSXBQ xmm xmm -// PMOVSXBQ m16 xmm -func PMOVSXBQ(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMOVSXBQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsM16(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMOVSXBQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PMOVSXBQ: bad operands") +// VPMOVZXDQ.Z m128 k ymm +// VPMOVZXDQ.Z m64 k xmm +// VPMOVZXDQ.Z xmm k xmm +// VPMOVZXDQ.Z xmm k ymm +// VPMOVZXDQ.Z m256 k zmm +// VPMOVZXDQ.Z ymm k zmm +func VPMOVZXDQ_Z(mxy, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVZXDQ.Forms(), sffxs{sffxZ}, []operand.Op{mxy, k, xyz}) } -// PMOVSXBW: Move Packed Byte Integers to Word Integers with Sign Extension. +// VPMOVZXWD: Move Packed Word Integers to Doubleword Integers with Zero Extension. // // Forms: // -// PMOVSXBW xmm xmm -// PMOVSXBW m64 xmm -func PMOVSXBW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMOVSXBW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMOVSXBW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PMOVSXBW: bad operands") +// VPMOVZXWD m128 ymm +// VPMOVZXWD xmm ymm +// VPMOVZXWD m64 xmm +// VPMOVZXWD xmm xmm +// VPMOVZXWD m128 k ymm +// VPMOVZXWD m64 k xmm +// VPMOVZXWD xmm k xmm +// VPMOVZXWD xmm k ymm +// VPMOVZXWD m256 k zmm +// VPMOVZXWD m256 zmm +// VPMOVZXWD ymm k zmm +// VPMOVZXWD ymm zmm +func VPMOVZXWD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVZXWD.Forms(), sffxs{}, ops) } -// PMOVSXDQ: Move Packed Doubleword Integers to Quadword Integers with Sign Extension. +// VPMOVZXWD_Z: Move Packed Word Integers to Doubleword Integers with Zero Extension (Zeroing Masking). // // Forms: // -// PMOVSXDQ xmm xmm -// PMOVSXDQ m64 xmm -func PMOVSXDQ(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMOVSXDQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMOVSXDQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PMOVSXDQ: bad operands") +// VPMOVZXWD.Z m128 k ymm +// VPMOVZXWD.Z m64 k xmm +// VPMOVZXWD.Z xmm k xmm +// VPMOVZXWD.Z xmm k ymm +// VPMOVZXWD.Z m256 k zmm +// VPMOVZXWD.Z ymm k zmm +func VPMOVZXWD_Z(mxy, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVZXWD.Forms(), sffxs{sffxZ}, []operand.Op{mxy, k, xyz}) } -// PMOVSXWD: Move Packed Word Integers to Doubleword Integers with Sign Extension. +// VPMOVZXWQ: Move Packed Word Integers to Quadword Integers with Zero Extension. // // Forms: // -// PMOVSXWD xmm xmm -// PMOVSXWD m64 xmm -func PMOVSXWD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMOVSXWD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMOVSXWD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PMOVSXWD: bad operands") +// VPMOVZXWQ m64 ymm +// VPMOVZXWQ xmm ymm +// VPMOVZXWQ m32 xmm +// VPMOVZXWQ xmm xmm +// VPMOVZXWQ m32 k xmm +// VPMOVZXWQ m64 k ymm +// VPMOVZXWQ xmm k xmm +// VPMOVZXWQ xmm k ymm +// VPMOVZXWQ m128 k zmm +// VPMOVZXWQ m128 zmm +// VPMOVZXWQ xmm k zmm +// VPMOVZXWQ xmm zmm +func VPMOVZXWQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVZXWQ.Forms(), sffxs{}, ops) } -// PMOVSXWQ: Move Packed Word Integers to Quadword Integers with Sign Extension. +// VPMOVZXWQ_Z: Move Packed Word Integers to Quadword Integers with Zero Extension (Zeroing Masking). // // Forms: // -// PMOVSXWQ xmm xmm -// PMOVSXWQ m32 xmm -func PMOVSXWQ(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMOVSXWQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMOVSXWQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PMOVSXWQ: bad operands") +// VPMOVZXWQ.Z m32 k xmm +// VPMOVZXWQ.Z m64 k ymm +// VPMOVZXWQ.Z xmm k xmm +// VPMOVZXWQ.Z xmm k ymm +// VPMOVZXWQ.Z m128 k zmm +// VPMOVZXWQ.Z xmm k zmm +func VPMOVZXWQ_Z(mx, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPMOVZXWQ.Forms(), sffxs{sffxZ}, []operand.Op{mx, k, xyz}) } -// PMOVZXBD: Move Packed Byte Integers to Doubleword Integers with Zero Extension. +// VPMULDQ: Multiply Packed Signed Doubleword Integers and Store Quadword Result. // // Forms: // -// PMOVZXBD xmm xmm -// PMOVZXBD m32 xmm -func PMOVZXBD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMOVZXBD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMOVZXBD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PMOVZXBD: bad operands") +// VPMULDQ m256 ymm ymm +// VPMULDQ ymm ymm ymm +// VPMULDQ m128 xmm xmm +// VPMULDQ xmm xmm xmm +// VPMULDQ m128 xmm k xmm +// VPMULDQ m256 ymm k ymm +// VPMULDQ xmm xmm k xmm +// VPMULDQ ymm ymm k ymm +// VPMULDQ m512 zmm k zmm +// VPMULDQ m512 zmm zmm +// VPMULDQ zmm zmm k zmm +// VPMULDQ zmm zmm zmm +func VPMULDQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMULDQ.Forms(), sffxs{}, ops) } -// PMOVZXBQ: Move Packed Byte Integers to Quadword Integers with Zero Extension. +// VPMULDQ_BCST: Multiply Packed Signed Doubleword Integers and Store Quadword Result (Broadcast). // // Forms: // -// PMOVZXBQ xmm xmm -// PMOVZXBQ m16 xmm -func PMOVZXBQ(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMOVZXBQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsM16(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMOVZXBQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PMOVZXBQ: bad operands") +// VPMULDQ.BCST m64 xmm k xmm +// VPMULDQ.BCST m64 xmm xmm +// VPMULDQ.BCST m64 ymm k ymm +// VPMULDQ.BCST m64 ymm ymm +// VPMULDQ.BCST m64 zmm k zmm +// VPMULDQ.BCST m64 zmm zmm +func VPMULDQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMULDQ.Forms(), sffxs{sffxBCST}, ops) } -// PMOVZXBW: Move Packed Byte Integers to Word Integers with Zero Extension. +// VPMULDQ_BCST_Z: Multiply Packed Signed Doubleword Integers and Store Quadword Result (Broadcast, Zeroing Masking). // // Forms: // -// PMOVZXBW xmm xmm -// PMOVZXBW m64 xmm -func PMOVZXBW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMOVZXBW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMOVZXBW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PMOVZXBW: bad operands") +// VPMULDQ.BCST.Z m64 xmm k xmm +// VPMULDQ.BCST.Z m64 ymm k ymm +// VPMULDQ.BCST.Z m64 zmm k zmm +func VPMULDQ_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMULDQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// PMOVZXDQ: Move Packed Doubleword Integers to Quadword Integers with Zero Extension. +// VPMULDQ_Z: Multiply Packed Signed Doubleword Integers and Store Quadword Result (Zeroing Masking). // // Forms: // -// PMOVZXDQ xmm xmm -// PMOVZXDQ m64 xmm -func PMOVZXDQ(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMOVZXDQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMOVZXDQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PMOVZXDQ: bad operands") +// VPMULDQ.Z m128 xmm k xmm +// VPMULDQ.Z m256 ymm k ymm +// VPMULDQ.Z xmm xmm k xmm +// VPMULDQ.Z ymm ymm k ymm +// VPMULDQ.Z m512 zmm k zmm +// VPMULDQ.Z zmm zmm k zmm +func VPMULDQ_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMULDQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// PMOVZXWD: Move Packed Word Integers to Doubleword Integers with Zero Extension. +// VPMULHRSW: Packed Multiply Signed Word Integers and Store High Result with Round and Scale. // // Forms: // -// PMOVZXWD xmm xmm -// PMOVZXWD m64 xmm -func PMOVZXWD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMOVZXWD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMOVZXWD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PMOVZXWD: bad operands") +// VPMULHRSW m256 ymm ymm +// VPMULHRSW ymm ymm ymm +// VPMULHRSW m128 xmm xmm +// VPMULHRSW xmm xmm xmm +// VPMULHRSW m128 xmm k xmm +// VPMULHRSW m256 ymm k ymm +// VPMULHRSW xmm xmm k xmm +// VPMULHRSW ymm ymm k ymm +// VPMULHRSW m512 zmm k zmm +// VPMULHRSW m512 zmm zmm +// VPMULHRSW zmm zmm k zmm +// VPMULHRSW zmm zmm zmm +func VPMULHRSW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMULHRSW.Forms(), sffxs{}, ops) } -// PMOVZXWQ: Move Packed Word Integers to Quadword Integers with Zero Extension. +// VPMULHRSW_Z: Packed Multiply Signed Word Integers and Store High Result with Round and Scale (Zeroing Masking). // // Forms: // -// PMOVZXWQ xmm xmm -// PMOVZXWQ m32 xmm -func PMOVZXWQ(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMOVZXWQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMOVZXWQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PMOVZXWQ: bad operands") +// VPMULHRSW.Z m128 xmm k xmm +// VPMULHRSW.Z m256 ymm k ymm +// VPMULHRSW.Z xmm xmm k xmm +// VPMULHRSW.Z ymm ymm k ymm +// VPMULHRSW.Z m512 zmm k zmm +// VPMULHRSW.Z zmm zmm k zmm +func VPMULHRSW_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMULHRSW.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// PMULDQ: Multiply Packed Signed Doubleword Integers and Store Quadword Result. +// VPMULHUW: Multiply Packed Unsigned Word Integers and Store High Result. // // Forms: // -// PMULDQ xmm xmm -// PMULDQ m128 xmm -func PMULDQ(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMULDQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMULDQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PMULDQ: bad operands") +// VPMULHUW m256 ymm ymm +// VPMULHUW ymm ymm ymm +// VPMULHUW m128 xmm xmm +// VPMULHUW xmm xmm xmm +// VPMULHUW m128 xmm k xmm +// VPMULHUW m256 ymm k ymm +// VPMULHUW xmm xmm k xmm +// VPMULHUW ymm ymm k ymm +// VPMULHUW m512 zmm k zmm +// VPMULHUW m512 zmm zmm +// VPMULHUW zmm zmm k zmm +// VPMULHUW zmm zmm zmm +func VPMULHUW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMULHUW.Forms(), sffxs{}, ops) } -// PMULHRSW: Packed Multiply Signed Word Integers and Store High Result with Round and Scale. +// VPMULHUW_Z: Multiply Packed Unsigned Word Integers and Store High Result (Zeroing Masking). // // Forms: // -// PMULHRSW xmm xmm -// PMULHRSW m128 xmm -func PMULHRSW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMULHRSW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMULHRSW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - }, nil - } - return nil, errors.New("PMULHRSW: bad operands") +// VPMULHUW.Z m128 xmm k xmm +// VPMULHUW.Z m256 ymm k ymm +// VPMULHUW.Z xmm xmm k xmm +// VPMULHUW.Z ymm ymm k ymm +// VPMULHUW.Z m512 zmm k zmm +// VPMULHUW.Z zmm zmm k zmm +func VPMULHUW_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMULHUW.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// PMULHUW: Multiply Packed Unsigned Word Integers and Store High Result. +// VPMULHW: Multiply Packed Signed Word Integers and Store High Result. // // Forms: // -// PMULHUW xmm xmm -// PMULHUW m128 xmm -func PMULHUW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMULHUW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMULHUW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PMULHUW: bad operands") +// VPMULHW m256 ymm ymm +// VPMULHW ymm ymm ymm +// VPMULHW m128 xmm xmm +// VPMULHW xmm xmm xmm +// VPMULHW m128 xmm k xmm +// VPMULHW m256 ymm k ymm +// VPMULHW xmm xmm k xmm +// VPMULHW ymm ymm k ymm +// VPMULHW m512 zmm k zmm +// VPMULHW m512 zmm zmm +// VPMULHW zmm zmm k zmm +// VPMULHW zmm zmm zmm +func VPMULHW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMULHW.Forms(), sffxs{}, ops) } -// PMULHW: Multiply Packed Signed Word Integers and Store High Result. +// VPMULHW_Z: Multiply Packed Signed Word Integers and Store High Result (Zeroing Masking). // // Forms: // -// PMULHW xmm xmm -// PMULHW m128 xmm -func PMULHW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMULHW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMULHW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PMULHW: bad operands") +// VPMULHW.Z m128 xmm k xmm +// VPMULHW.Z m256 ymm k ymm +// VPMULHW.Z xmm xmm k xmm +// VPMULHW.Z ymm ymm k ymm +// VPMULHW.Z m512 zmm k zmm +// VPMULHW.Z zmm zmm k zmm +func VPMULHW_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMULHW.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// PMULLD: Multiply Packed Signed Doubleword Integers and Store Low Result. +// VPMULLD: Multiply Packed Signed Doubleword Integers and Store Low Result. // // Forms: // -// PMULLD xmm xmm -// PMULLD m128 xmm -func PMULLD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMULLD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMULLD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PMULLD: bad operands") +// VPMULLD m256 ymm ymm +// VPMULLD ymm ymm ymm +// VPMULLD m128 xmm xmm +// VPMULLD xmm xmm xmm +// VPMULLD m128 xmm k xmm +// VPMULLD m256 ymm k ymm +// VPMULLD xmm xmm k xmm +// VPMULLD ymm ymm k ymm +// VPMULLD m512 zmm k zmm +// VPMULLD m512 zmm zmm +// VPMULLD zmm zmm k zmm +// VPMULLD zmm zmm zmm +func VPMULLD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMULLD.Forms(), sffxs{}, ops) } -// PMULLW: Multiply Packed Signed Word Integers and Store Low Result. +// VPMULLD_BCST: Multiply Packed Signed Doubleword Integers and Store Low Result (Broadcast). // // Forms: // -// PMULLW xmm xmm -// PMULLW m128 xmm -func PMULLW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMULLW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMULLW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PMULLW: bad operands") +// VPMULLD.BCST m32 xmm k xmm +// VPMULLD.BCST m32 xmm xmm +// VPMULLD.BCST m32 ymm k ymm +// VPMULLD.BCST m32 ymm ymm +// VPMULLD.BCST m32 zmm k zmm +// VPMULLD.BCST m32 zmm zmm +func VPMULLD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMULLD.Forms(), sffxs{sffxBCST}, ops) } -// PMULULQ: Multiply Packed Unsigned Doubleword Integers. +// VPMULLD_BCST_Z: Multiply Packed Signed Doubleword Integers and Store Low Result (Broadcast, Zeroing Masking). // // Forms: // -// PMULULQ xmm xmm -// PMULULQ m128 xmm -func PMULULQ(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMULULQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PMULULQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PMULULQ: bad operands") +// VPMULLD.BCST.Z m32 xmm k xmm +// VPMULLD.BCST.Z m32 ymm k ymm +// VPMULLD.BCST.Z m32 zmm k zmm +func VPMULLD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMULLD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// POPCNTL: Count of Number of Bits Set to 1. +// VPMULLD_Z: Multiply Packed Signed Doubleword Integers and Store Low Result (Zeroing Masking). // // Forms: // -// POPCNTL r32 r32 -// POPCNTL m32 r32 -func POPCNTL(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "POPCNTL", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"POPCNT"}, - }, nil - case operand.IsM32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "POPCNTL", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"POPCNT"}, - }, nil - } - return nil, errors.New("POPCNTL: bad operands") +// VPMULLD.Z m128 xmm k xmm +// VPMULLD.Z m256 ymm k ymm +// VPMULLD.Z xmm xmm k xmm +// VPMULLD.Z ymm ymm k ymm +// VPMULLD.Z m512 zmm k zmm +// VPMULLD.Z zmm zmm k zmm +func VPMULLD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMULLD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// POPCNTQ: Count of Number of Bits Set to 1. +// VPMULLQ: Multiply Packed Signed Quadword Integers and Store Low Result. // // Forms: // -// POPCNTQ r64 r64 -// POPCNTQ m64 r64 -func POPCNTQ(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "POPCNTQ", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"POPCNT"}, - }, nil - case operand.IsM64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "POPCNTQ", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"POPCNT"}, - }, nil - } - return nil, errors.New("POPCNTQ: bad operands") +// VPMULLQ m128 xmm k xmm +// VPMULLQ m128 xmm xmm +// VPMULLQ m256 ymm k ymm +// VPMULLQ m256 ymm ymm +// VPMULLQ xmm xmm k xmm +// VPMULLQ xmm xmm xmm +// VPMULLQ ymm ymm k ymm +// VPMULLQ ymm ymm ymm +// VPMULLQ m512 zmm k zmm +// VPMULLQ m512 zmm zmm +// VPMULLQ zmm zmm k zmm +// VPMULLQ zmm zmm zmm +func VPMULLQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMULLQ.Forms(), sffxs{}, ops) +} + +// VPMULLQ_BCST: Multiply Packed Signed Quadword Integers and Store Low Result (Broadcast). +// +// Forms: +// +// VPMULLQ.BCST m64 xmm k xmm +// VPMULLQ.BCST m64 xmm xmm +// VPMULLQ.BCST m64 ymm k ymm +// VPMULLQ.BCST m64 ymm ymm +// VPMULLQ.BCST m64 zmm k zmm +// VPMULLQ.BCST m64 zmm zmm +func VPMULLQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMULLQ.Forms(), sffxs{sffxBCST}, ops) } -// POPCNTW: Count of Number of Bits Set to 1. +// VPMULLQ_BCST_Z: Multiply Packed Signed Quadword Integers and Store Low Result (Broadcast, Zeroing Masking). // // Forms: // -// POPCNTW r16 r16 -// POPCNTW m16 r16 -func POPCNTW(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "POPCNTW", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"POPCNT"}, - }, nil - case operand.IsM16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "POPCNTW", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"POPCNT"}, - }, nil - } - return nil, errors.New("POPCNTW: bad operands") +// VPMULLQ.BCST.Z m64 xmm k xmm +// VPMULLQ.BCST.Z m64 ymm k ymm +// VPMULLQ.BCST.Z m64 zmm k zmm +func VPMULLQ_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMULLQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// POPQ: Pop a Value from the Stack. +// VPMULLQ_Z: Multiply Packed Signed Quadword Integers and Store Low Result (Zeroing Masking). // // Forms: // -// POPQ r64 -// POPQ m64 -func POPQ(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "POPQ", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "POPQ", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("POPQ: bad operands") +// VPMULLQ.Z m128 xmm k xmm +// VPMULLQ.Z m256 ymm k ymm +// VPMULLQ.Z xmm xmm k xmm +// VPMULLQ.Z ymm ymm k ymm +// VPMULLQ.Z m512 zmm k zmm +// VPMULLQ.Z zmm zmm k zmm +func VPMULLQ_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMULLQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// POPW: Pop a Value from the Stack. +// VPMULLW: Multiply Packed Signed Word Integers and Store Low Result. // // Forms: // -// POPW r16 -// POPW m16 -func POPW(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "POPW", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "POPW", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("POPW: bad operands") +// VPMULLW m256 ymm ymm +// VPMULLW ymm ymm ymm +// VPMULLW m128 xmm xmm +// VPMULLW xmm xmm xmm +// VPMULLW m128 xmm k xmm +// VPMULLW m256 ymm k ymm +// VPMULLW xmm xmm k xmm +// VPMULLW ymm ymm k ymm +// VPMULLW m512 zmm k zmm +// VPMULLW m512 zmm zmm +// VPMULLW zmm zmm k zmm +// VPMULLW zmm zmm zmm +func VPMULLW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMULLW.Forms(), sffxs{}, ops) } -// POR: Packed Bitwise Logical OR. +// VPMULLW_Z: Multiply Packed Signed Word Integers and Store Low Result (Zeroing Masking). // // Forms: // -// POR xmm xmm -// POR m128 xmm -func POR(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "POR", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "POR", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("POR: bad operands") +// VPMULLW.Z m128 xmm k xmm +// VPMULLW.Z m256 ymm k ymm +// VPMULLW.Z xmm xmm k xmm +// VPMULLW.Z ymm ymm k ymm +// VPMULLW.Z m512 zmm k zmm +// VPMULLW.Z zmm zmm k zmm +func VPMULLW_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMULLW.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// PREFETCHNTA: Prefetch Data Into Caches using NTA Hint. +// VPMULTISHIFTQB: Select Packed Unaligned Bytes from Quadword Sources. // // Forms: // -// PREFETCHNTA m8 -func PREFETCHNTA(m operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM8(m): - return &intrep.Instruction{ - Opcode: "PREFETCHNTA", - Operands: []operand.Op{m}, - Inputs: []operand.Op{m}, - Outputs: []operand.Op{}, - ISA: []string{"MMX+"}, - }, nil - } - return nil, errors.New("PREFETCHNTA: bad operands") +// VPMULTISHIFTQB m128 xmm k xmm +// VPMULTISHIFTQB m128 xmm xmm +// VPMULTISHIFTQB m256 ymm k ymm +// VPMULTISHIFTQB m256 ymm ymm +// VPMULTISHIFTQB xmm xmm k xmm +// VPMULTISHIFTQB xmm xmm xmm +// VPMULTISHIFTQB ymm ymm k ymm +// VPMULTISHIFTQB ymm ymm ymm +// VPMULTISHIFTQB m512 zmm k zmm +// VPMULTISHIFTQB m512 zmm zmm +// VPMULTISHIFTQB zmm zmm k zmm +// VPMULTISHIFTQB zmm zmm zmm +func VPMULTISHIFTQB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMULTISHIFTQB.Forms(), sffxs{}, ops) } -// PREFETCHT0: Prefetch Data Into Caches using T0 Hint. +// VPMULTISHIFTQB_BCST: Select Packed Unaligned Bytes from Quadword Sources (Broadcast). // // Forms: // -// PREFETCHT0 m8 -func PREFETCHT0(m operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM8(m): - return &intrep.Instruction{ - Opcode: "PREFETCHT0", - Operands: []operand.Op{m}, - Inputs: []operand.Op{m}, - Outputs: []operand.Op{}, - ISA: []string{"MMX+"}, - }, nil - } - return nil, errors.New("PREFETCHT0: bad operands") +// VPMULTISHIFTQB.BCST m64 xmm k xmm +// VPMULTISHIFTQB.BCST m64 xmm xmm +// VPMULTISHIFTQB.BCST m64 ymm k ymm +// VPMULTISHIFTQB.BCST m64 ymm ymm +// VPMULTISHIFTQB.BCST m64 zmm k zmm +// VPMULTISHIFTQB.BCST m64 zmm zmm +func VPMULTISHIFTQB_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMULTISHIFTQB.Forms(), sffxs{sffxBCST}, ops) } -// PREFETCHT1: Prefetch Data Into Caches using T1 Hint. +// VPMULTISHIFTQB_BCST_Z: Select Packed Unaligned Bytes from Quadword Sources (Broadcast, Zeroing Masking). // // Forms: // -// PREFETCHT1 m8 -func PREFETCHT1(m operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM8(m): - return &intrep.Instruction{ - Opcode: "PREFETCHT1", - Operands: []operand.Op{m}, - Inputs: []operand.Op{m}, - Outputs: []operand.Op{}, - ISA: []string{"MMX+"}, - }, nil - } - return nil, errors.New("PREFETCHT1: bad operands") +// VPMULTISHIFTQB.BCST.Z m64 xmm k xmm +// VPMULTISHIFTQB.BCST.Z m64 ymm k ymm +// VPMULTISHIFTQB.BCST.Z m64 zmm k zmm +func VPMULTISHIFTQB_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMULTISHIFTQB.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// PREFETCHT2: Prefetch Data Into Caches using T2 Hint. +// VPMULTISHIFTQB_Z: Select Packed Unaligned Bytes from Quadword Sources (Zeroing Masking). // // Forms: // -// PREFETCHT2 m8 -func PREFETCHT2(m operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM8(m): - return &intrep.Instruction{ - Opcode: "PREFETCHT2", - Operands: []operand.Op{m}, - Inputs: []operand.Op{m}, - Outputs: []operand.Op{}, - ISA: []string{"MMX+"}, - }, nil - } - return nil, errors.New("PREFETCHT2: bad operands") +// VPMULTISHIFTQB.Z m128 xmm k xmm +// VPMULTISHIFTQB.Z m256 ymm k ymm +// VPMULTISHIFTQB.Z xmm xmm k xmm +// VPMULTISHIFTQB.Z ymm ymm k ymm +// VPMULTISHIFTQB.Z m512 zmm k zmm +// VPMULTISHIFTQB.Z zmm zmm k zmm +func VPMULTISHIFTQB_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMULTISHIFTQB.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// PSADBW: Compute Sum of Absolute Differences. +// VPMULUDQ: Multiply Packed Unsigned Doubleword Integers. // // Forms: // -// PSADBW xmm xmm -// PSADBW m128 xmm -func PSADBW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSADBW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSADBW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PSADBW: bad operands") +// VPMULUDQ m256 ymm ymm +// VPMULUDQ ymm ymm ymm +// VPMULUDQ m128 xmm xmm +// VPMULUDQ xmm xmm xmm +// VPMULUDQ m128 xmm k xmm +// VPMULUDQ m256 ymm k ymm +// VPMULUDQ xmm xmm k xmm +// VPMULUDQ ymm ymm k ymm +// VPMULUDQ m512 zmm k zmm +// VPMULUDQ m512 zmm zmm +// VPMULUDQ zmm zmm k zmm +// VPMULUDQ zmm zmm zmm +func VPMULUDQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMULUDQ.Forms(), sffxs{}, ops) } -// PSHUFB: Packed Shuffle Bytes. +// VPMULUDQ_BCST: Multiply Packed Unsigned Doubleword Integers (Broadcast). // // Forms: // -// PSHUFB xmm xmm -// PSHUFB m128 xmm -func PSHUFB(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSHUFB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSHUFB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - }, nil - } - return nil, errors.New("PSHUFB: bad operands") +// VPMULUDQ.BCST m64 xmm k xmm +// VPMULUDQ.BCST m64 xmm xmm +// VPMULUDQ.BCST m64 ymm k ymm +// VPMULUDQ.BCST m64 ymm ymm +// VPMULUDQ.BCST m64 zmm k zmm +// VPMULUDQ.BCST m64 zmm zmm +func VPMULUDQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPMULUDQ.Forms(), sffxs{sffxBCST}, ops) } -// PSHUFD: Shuffle Packed Doublewords. +// VPMULUDQ_BCST_Z: Multiply Packed Unsigned Doubleword Integers (Broadcast, Zeroing Masking). // // Forms: // -// PSHUFD imm8 xmm xmm -// PSHUFD imm8 m128 xmm -func PSHUFD(i, mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSHUFD", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSHUFD", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PSHUFD: bad operands") +// VPMULUDQ.BCST.Z m64 xmm k xmm +// VPMULUDQ.BCST.Z m64 ymm k ymm +// VPMULUDQ.BCST.Z m64 zmm k zmm +func VPMULUDQ_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMULUDQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// PSHUFHW: Shuffle Packed High Words. +// VPMULUDQ_Z: Multiply Packed Unsigned Doubleword Integers (Zeroing Masking). // // Forms: // -// PSHUFHW imm8 xmm xmm -// PSHUFHW imm8 m128 xmm -func PSHUFHW(i, mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSHUFHW", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSHUFHW", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PSHUFHW: bad operands") +// VPMULUDQ.Z m128 xmm k xmm +// VPMULUDQ.Z m256 ymm k ymm +// VPMULUDQ.Z xmm xmm k xmm +// VPMULUDQ.Z ymm ymm k ymm +// VPMULUDQ.Z m512 zmm k zmm +// VPMULUDQ.Z zmm zmm k zmm +func VPMULUDQ_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPMULUDQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// PSHUFL: Shuffle Packed Doublewords. +// VPOPCNTD: Packed Population Count for Doubleword Integers. // // Forms: // -// PSHUFL imm8 xmm xmm -// PSHUFL imm8 m128 xmm -func PSHUFL(i, mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSHUFL", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSHUFL", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PSHUFL: bad operands") +// VPOPCNTD m512 k zmm +// VPOPCNTD m512 zmm +// VPOPCNTD zmm k zmm +// VPOPCNTD zmm zmm +func VPOPCNTD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPOPCNTD.Forms(), sffxs{}, ops) } -// PSHUFLW: Shuffle Packed Low Words. +// VPOPCNTD_BCST: Packed Population Count for Doubleword Integers (Broadcast). // // Forms: // -// PSHUFLW imm8 xmm xmm -// PSHUFLW imm8 m128 xmm -func PSHUFLW(i, mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSHUFLW", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSHUFLW", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PSHUFLW: bad operands") +// VPOPCNTD.BCST m32 k zmm +// VPOPCNTD.BCST m32 zmm +func VPOPCNTD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPOPCNTD.Forms(), sffxs{sffxBCST}, ops) } -// PSIGNB: Packed Sign of Byte Integers. +// VPOPCNTD_BCST_Z: Packed Population Count for Doubleword Integers (Broadcast, Zeroing Masking). // // Forms: // -// PSIGNB xmm xmm -// PSIGNB m128 xmm -func PSIGNB(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSIGNB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSIGNB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - }, nil - } - return nil, errors.New("PSIGNB: bad operands") +// VPOPCNTD.BCST.Z m32 k zmm +func VPOPCNTD_BCST_Z(m, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVPOPCNTD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, z}) } -// PSIGND: Packed Sign of Doubleword Integers. +// VPOPCNTD_Z: Packed Population Count for Doubleword Integers (Zeroing Masking). // // Forms: // -// PSIGND xmm xmm -// PSIGND m128 xmm -func PSIGND(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSIGND", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSIGND", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - }, nil - } - return nil, errors.New("PSIGND: bad operands") +// VPOPCNTD.Z m512 k zmm +// VPOPCNTD.Z zmm k zmm +func VPOPCNTD_Z(mz, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVPOPCNTD.Forms(), sffxs{sffxZ}, []operand.Op{mz, k, z}) } -// PSIGNW: Packed Sign of Word Integers. +// VPOPCNTQ: Packed Population Count for Quadword Integers. // // Forms: // -// PSIGNW xmm xmm -// PSIGNW m128 xmm -func PSIGNW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSIGNW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSIGNW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSSE3"}, - }, nil - } - return nil, errors.New("PSIGNW: bad operands") +// VPOPCNTQ m512 k zmm +// VPOPCNTQ m512 zmm +// VPOPCNTQ zmm k zmm +// VPOPCNTQ zmm zmm +func VPOPCNTQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPOPCNTQ.Forms(), sffxs{}, ops) } -// PSLLDQ: Shift Packed Double Quadword Left Logical. +// VPOPCNTQ_BCST: Packed Population Count for Quadword Integers (Broadcast). // // Forms: // -// PSLLDQ imm8 xmm -func PSLLDQ(i, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSLLDQ", - Operands: []operand.Op{i, x}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PSLLDQ: bad operands") +// VPOPCNTQ.BCST m64 k zmm +// VPOPCNTQ.BCST m64 zmm +func VPOPCNTQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPOPCNTQ.Forms(), sffxs{sffxBCST}, ops) } -// PSLLL: Shift Packed Doubleword Data Left Logical. +// VPOPCNTQ_BCST_Z: Packed Population Count for Quadword Integers (Broadcast, Zeroing Masking). // // Forms: // -// PSLLL imm8 xmm -// PSLLL xmm xmm -// PSLLL m128 xmm -func PSLLL(imx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(imx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSLLL", - Operands: []operand.Op{imx, x}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsXMM(imx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSLLL", - Operands: []operand.Op{imx, x}, - Inputs: []operand.Op{imx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(imx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSLLL", - Operands: []operand.Op{imx, x}, - Inputs: []operand.Op{imx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PSLLL: bad operands") +// VPOPCNTQ.BCST.Z m64 k zmm +func VPOPCNTQ_BCST_Z(m, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVPOPCNTQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, z}) } -// PSLLO: Shift Packed Double Quadword Left Logical. +// VPOPCNTQ_Z: Packed Population Count for Quadword Integers (Zeroing Masking). // // Forms: // -// PSLLO imm8 xmm -func PSLLO(i, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSLLO", - Operands: []operand.Op{i, x}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PSLLO: bad operands") +// VPOPCNTQ.Z m512 k zmm +// VPOPCNTQ.Z zmm k zmm +func VPOPCNTQ_Z(mz, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVPOPCNTQ.Forms(), sffxs{sffxZ}, []operand.Op{mz, k, z}) } -// PSLLQ: Shift Packed Quadword Data Left Logical. +// VPOR: Packed Bitwise Logical OR. // // Forms: // -// PSLLQ imm8 xmm -// PSLLQ xmm xmm -// PSLLQ m128 xmm -func PSLLQ(imx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(imx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSLLQ", - Operands: []operand.Op{imx, x}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsXMM(imx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSLLQ", - Operands: []operand.Op{imx, x}, - Inputs: []operand.Op{imx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(imx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSLLQ", - Operands: []operand.Op{imx, x}, - Inputs: []operand.Op{imx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PSLLQ: bad operands") +// VPOR m256 ymm ymm +// VPOR ymm ymm ymm +// VPOR m128 xmm xmm +// VPOR xmm xmm xmm +func VPOR(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPOR.Forms(), sffxs{}, []operand.Op{mxy, xy, xy1}) } -// PSLLW: Shift Packed Word Data Left Logical. +// VPORD: Bitwise Logical OR of Packed Doubleword Integers. // // Forms: // -// PSLLW imm8 xmm -// PSLLW xmm xmm -// PSLLW m128 xmm -func PSLLW(imx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(imx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSLLW", - Operands: []operand.Op{imx, x}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsXMM(imx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSLLW", - Operands: []operand.Op{imx, x}, - Inputs: []operand.Op{imx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(imx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSLLW", - Operands: []operand.Op{imx, x}, - Inputs: []operand.Op{imx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PSLLW: bad operands") +// VPORD m128 xmm k xmm +// VPORD m128 xmm xmm +// VPORD m256 ymm k ymm +// VPORD m256 ymm ymm +// VPORD xmm xmm k xmm +// VPORD xmm xmm xmm +// VPORD ymm ymm k ymm +// VPORD ymm ymm ymm +// VPORD m512 zmm k zmm +// VPORD m512 zmm zmm +// VPORD zmm zmm k zmm +// VPORD zmm zmm zmm +func VPORD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPORD.Forms(), sffxs{}, ops) } -// PSRAL: Shift Packed Doubleword Data Right Arithmetic. +// VPORD_BCST: Bitwise Logical OR of Packed Doubleword Integers (Broadcast). // // Forms: // -// PSRAL imm8 xmm -// PSRAL xmm xmm -// PSRAL m128 xmm -func PSRAL(imx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(imx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSRAL", - Operands: []operand.Op{imx, x}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsXMM(imx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSRAL", - Operands: []operand.Op{imx, x}, - Inputs: []operand.Op{imx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(imx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSRAL", - Operands: []operand.Op{imx, x}, - Inputs: []operand.Op{imx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PSRAL: bad operands") +// VPORD.BCST m32 xmm k xmm +// VPORD.BCST m32 xmm xmm +// VPORD.BCST m32 ymm k ymm +// VPORD.BCST m32 ymm ymm +// VPORD.BCST m32 zmm k zmm +// VPORD.BCST m32 zmm zmm +func VPORD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPORD.Forms(), sffxs{sffxBCST}, ops) } -// PSRAW: Shift Packed Word Data Right Arithmetic. +// VPORD_BCST_Z: Bitwise Logical OR of Packed Doubleword Integers (Broadcast, Zeroing Masking). // // Forms: // -// PSRAW imm8 xmm -// PSRAW xmm xmm -// PSRAW m128 xmm -func PSRAW(imx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(imx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSRAW", - Operands: []operand.Op{imx, x}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsXMM(imx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSRAW", - Operands: []operand.Op{imx, x}, - Inputs: []operand.Op{imx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(imx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSRAW", - Operands: []operand.Op{imx, x}, - Inputs: []operand.Op{imx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PSRAW: bad operands") +// VPORD.BCST.Z m32 xmm k xmm +// VPORD.BCST.Z m32 ymm k ymm +// VPORD.BCST.Z m32 zmm k zmm +func VPORD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPORD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// PSRLDQ: Shift Packed Double Quadword Right Logical. +// VPORD_Z: Bitwise Logical OR of Packed Doubleword Integers (Zeroing Masking). // // Forms: // -// PSRLDQ imm8 xmm -func PSRLDQ(i, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSRLDQ", - Operands: []operand.Op{i, x}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PSRLDQ: bad operands") +// VPORD.Z m128 xmm k xmm +// VPORD.Z m256 ymm k ymm +// VPORD.Z xmm xmm k xmm +// VPORD.Z ymm ymm k ymm +// VPORD.Z m512 zmm k zmm +// VPORD.Z zmm zmm k zmm +func VPORD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPORD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// PSRLL: Shift Packed Doubleword Data Right Logical. +// VPORQ: Bitwise Logical OR of Packed Quadword Integers. // // Forms: // -// PSRLL imm8 xmm -// PSRLL xmm xmm -// PSRLL m128 xmm -func PSRLL(imx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(imx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSRLL", - Operands: []operand.Op{imx, x}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsXMM(imx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSRLL", - Operands: []operand.Op{imx, x}, - Inputs: []operand.Op{imx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(imx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSRLL", - Operands: []operand.Op{imx, x}, - Inputs: []operand.Op{imx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PSRLL: bad operands") +// VPORQ m128 xmm k xmm +// VPORQ m128 xmm xmm +// VPORQ m256 ymm k ymm +// VPORQ m256 ymm ymm +// VPORQ xmm xmm k xmm +// VPORQ xmm xmm xmm +// VPORQ ymm ymm k ymm +// VPORQ ymm ymm ymm +// VPORQ m512 zmm k zmm +// VPORQ m512 zmm zmm +// VPORQ zmm zmm k zmm +// VPORQ zmm zmm zmm +func VPORQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPORQ.Forms(), sffxs{}, ops) } -// PSRLO: Shift Packed Double Quadword Right Logical. +// VPORQ_BCST: Bitwise Logical OR of Packed Quadword Integers (Broadcast). // // Forms: // -// PSRLO imm8 xmm -func PSRLO(i, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSRLO", - Operands: []operand.Op{i, x}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PSRLO: bad operands") +// VPORQ.BCST m64 xmm k xmm +// VPORQ.BCST m64 xmm xmm +// VPORQ.BCST m64 ymm k ymm +// VPORQ.BCST m64 ymm ymm +// VPORQ.BCST m64 zmm k zmm +// VPORQ.BCST m64 zmm zmm +func VPORQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPORQ.Forms(), sffxs{sffxBCST}, ops) } -// PSRLQ: Shift Packed Quadword Data Right Logical. +// VPORQ_BCST_Z: Bitwise Logical OR of Packed Quadword Integers (Broadcast, Zeroing Masking). // // Forms: // -// PSRLQ imm8 xmm -// PSRLQ xmm xmm -// PSRLQ m128 xmm -func PSRLQ(imx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(imx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSRLQ", - Operands: []operand.Op{imx, x}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsXMM(imx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSRLQ", - Operands: []operand.Op{imx, x}, - Inputs: []operand.Op{imx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(imx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSRLQ", - Operands: []operand.Op{imx, x}, - Inputs: []operand.Op{imx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PSRLQ: bad operands") +// VPORQ.BCST.Z m64 xmm k xmm +// VPORQ.BCST.Z m64 ymm k ymm +// VPORQ.BCST.Z m64 zmm k zmm +func VPORQ_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPORQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// PSRLW: Shift Packed Word Data Right Logical. +// VPORQ_Z: Bitwise Logical OR of Packed Quadword Integers (Zeroing Masking). // // Forms: // -// PSRLW imm8 xmm -// PSRLW xmm xmm -// PSRLW m128 xmm -func PSRLW(imx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(imx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSRLW", - Operands: []operand.Op{imx, x}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsXMM(imx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSRLW", - Operands: []operand.Op{imx, x}, - Inputs: []operand.Op{imx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(imx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSRLW", - Operands: []operand.Op{imx, x}, - Inputs: []operand.Op{imx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PSRLW: bad operands") +// VPORQ.Z m128 xmm k xmm +// VPORQ.Z m256 ymm k ymm +// VPORQ.Z xmm xmm k xmm +// VPORQ.Z ymm ymm k ymm +// VPORQ.Z m512 zmm k zmm +// VPORQ.Z zmm zmm k zmm +func VPORQ_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPORQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// PSUBB: Subtract Packed Byte Integers. +// VPROLD: Rotate Packed Doubleword Left. // // Forms: // -// PSUBB xmm xmm -// PSUBB m128 xmm -func PSUBB(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSUBB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSUBB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PSUBB: bad operands") +// VPROLD imm8 m128 k xmm +// VPROLD imm8 m128 xmm +// VPROLD imm8 m256 k ymm +// VPROLD imm8 m256 ymm +// VPROLD imm8 xmm k xmm +// VPROLD imm8 xmm xmm +// VPROLD imm8 ymm k ymm +// VPROLD imm8 ymm ymm +// VPROLD imm8 m512 k zmm +// VPROLD imm8 m512 zmm +// VPROLD imm8 zmm k zmm +// VPROLD imm8 zmm zmm +func VPROLD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPROLD.Forms(), sffxs{}, ops) } -// PSUBL: Subtract Packed Doubleword Integers. +// VPROLD_BCST: Rotate Packed Doubleword Left (Broadcast). // // Forms: // -// PSUBL xmm xmm -// PSUBL m128 xmm -func PSUBL(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSUBL", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSUBL", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PSUBL: bad operands") +// VPROLD.BCST imm8 m32 k xmm +// VPROLD.BCST imm8 m32 k ymm +// VPROLD.BCST imm8 m32 xmm +// VPROLD.BCST imm8 m32 ymm +// VPROLD.BCST imm8 m32 k zmm +// VPROLD.BCST imm8 m32 zmm +func VPROLD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPROLD.Forms(), sffxs{sffxBCST}, ops) } -// PSUBQ: Subtract Packed Quadword Integers. +// VPROLD_BCST_Z: Rotate Packed Doubleword Left (Broadcast, Zeroing Masking). // // Forms: // -// PSUBQ xmm xmm -// PSUBQ m128 xmm -func PSUBQ(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSUBQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSUBQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PSUBQ: bad operands") +// VPROLD.BCST.Z imm8 m32 k xmm +// VPROLD.BCST.Z imm8 m32 k ymm +// VPROLD.BCST.Z imm8 m32 k zmm +func VPROLD_BCST_Z(i, m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPROLD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{i, m, k, xyz}) } -// PSUBSB: Subtract Packed Signed Byte Integers with Signed Saturation. +// VPROLD_Z: Rotate Packed Doubleword Left (Zeroing Masking). // // Forms: // -// PSUBSB xmm xmm -// PSUBSB m128 xmm -func PSUBSB(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSUBSB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSUBSB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PSUBSB: bad operands") +// VPROLD.Z imm8 m128 k xmm +// VPROLD.Z imm8 m256 k ymm +// VPROLD.Z imm8 xmm k xmm +// VPROLD.Z imm8 ymm k ymm +// VPROLD.Z imm8 m512 k zmm +// VPROLD.Z imm8 zmm k zmm +func VPROLD_Z(i, mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPROLD.Forms(), sffxs{sffxZ}, []operand.Op{i, mxyz, k, xyz}) } -// PSUBSW: Subtract Packed Signed Word Integers with Signed Saturation. +// VPROLQ: Rotate Packed Quadword Left. // // Forms: // -// PSUBSW xmm xmm -// PSUBSW m128 xmm -func PSUBSW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSUBSW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSUBSW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PSUBSW: bad operands") +// VPROLQ imm8 m128 k xmm +// VPROLQ imm8 m128 xmm +// VPROLQ imm8 m256 k ymm +// VPROLQ imm8 m256 ymm +// VPROLQ imm8 xmm k xmm +// VPROLQ imm8 xmm xmm +// VPROLQ imm8 ymm k ymm +// VPROLQ imm8 ymm ymm +// VPROLQ imm8 m512 k zmm +// VPROLQ imm8 m512 zmm +// VPROLQ imm8 zmm k zmm +// VPROLQ imm8 zmm zmm +func VPROLQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPROLQ.Forms(), sffxs{}, ops) } -// PSUBUSB: Subtract Packed Unsigned Byte Integers with Unsigned Saturation. +// VPROLQ_BCST: Rotate Packed Quadword Left (Broadcast). // // Forms: // -// PSUBUSB xmm xmm -// PSUBUSB m128 xmm -func PSUBUSB(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSUBUSB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSUBUSB", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PSUBUSB: bad operands") +// VPROLQ.BCST imm8 m64 k xmm +// VPROLQ.BCST imm8 m64 k ymm +// VPROLQ.BCST imm8 m64 xmm +// VPROLQ.BCST imm8 m64 ymm +// VPROLQ.BCST imm8 m64 k zmm +// VPROLQ.BCST imm8 m64 zmm +func VPROLQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPROLQ.Forms(), sffxs{sffxBCST}, ops) } -// PSUBUSW: Subtract Packed Unsigned Word Integers with Unsigned Saturation. +// VPROLQ_BCST_Z: Rotate Packed Quadword Left (Broadcast, Zeroing Masking). // // Forms: // -// PSUBUSW xmm xmm -// PSUBUSW m128 xmm -func PSUBUSW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSUBUSW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSUBUSW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PSUBUSW: bad operands") +// VPROLQ.BCST.Z imm8 m64 k xmm +// VPROLQ.BCST.Z imm8 m64 k ymm +// VPROLQ.BCST.Z imm8 m64 k zmm +func VPROLQ_BCST_Z(i, m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPROLQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{i, m, k, xyz}) } -// PSUBW: Subtract Packed Word Integers. +// VPROLQ_Z: Rotate Packed Quadword Left (Zeroing Masking). // // Forms: // -// PSUBW xmm xmm -// PSUBW m128 xmm -func PSUBW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSUBW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PSUBW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PSUBW: bad operands") +// VPROLQ.Z imm8 m128 k xmm +// VPROLQ.Z imm8 m256 k ymm +// VPROLQ.Z imm8 xmm k xmm +// VPROLQ.Z imm8 ymm k ymm +// VPROLQ.Z imm8 m512 k zmm +// VPROLQ.Z imm8 zmm k zmm +func VPROLQ_Z(i, mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPROLQ.Forms(), sffxs{sffxZ}, []operand.Op{i, mxyz, k, xyz}) } -// PTEST: Packed Logical Compare. +// VPROLVD: Variable Rotate Packed Doubleword Left. // // Forms: // -// PTEST xmm xmm -// PTEST m128 xmm -func PTEST(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PTEST", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PTEST", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("PTEST: bad operands") +// VPROLVD m128 xmm k xmm +// VPROLVD m128 xmm xmm +// VPROLVD m256 ymm k ymm +// VPROLVD m256 ymm ymm +// VPROLVD xmm xmm k xmm +// VPROLVD xmm xmm xmm +// VPROLVD ymm ymm k ymm +// VPROLVD ymm ymm ymm +// VPROLVD m512 zmm k zmm +// VPROLVD m512 zmm zmm +// VPROLVD zmm zmm k zmm +// VPROLVD zmm zmm zmm +func VPROLVD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPROLVD.Forms(), sffxs{}, ops) } -// PUNPCKHBW: Unpack and Interleave High-Order Bytes into Words. +// VPROLVD_BCST: Variable Rotate Packed Doubleword Left (Broadcast). // // Forms: // -// PUNPCKHBW xmm xmm -// PUNPCKHBW m128 xmm -func PUNPCKHBW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PUNPCKHBW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PUNPCKHBW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PUNPCKHBW: bad operands") +// VPROLVD.BCST m32 xmm k xmm +// VPROLVD.BCST m32 xmm xmm +// VPROLVD.BCST m32 ymm k ymm +// VPROLVD.BCST m32 ymm ymm +// VPROLVD.BCST m32 zmm k zmm +// VPROLVD.BCST m32 zmm zmm +func VPROLVD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPROLVD.Forms(), sffxs{sffxBCST}, ops) } -// PUNPCKHLQ: Unpack and Interleave High-Order Doublewords into Quadwords. +// VPROLVD_BCST_Z: Variable Rotate Packed Doubleword Left (Broadcast, Zeroing Masking). // // Forms: // -// PUNPCKHLQ xmm xmm -// PUNPCKHLQ m128 xmm -func PUNPCKHLQ(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PUNPCKHLQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PUNPCKHLQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PUNPCKHLQ: bad operands") +// VPROLVD.BCST.Z m32 xmm k xmm +// VPROLVD.BCST.Z m32 ymm k ymm +// VPROLVD.BCST.Z m32 zmm k zmm +func VPROLVD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPROLVD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// PUNPCKHQDQ: Unpack and Interleave High-Order Quadwords into Double Quadwords. +// VPROLVD_Z: Variable Rotate Packed Doubleword Left (Zeroing Masking). // // Forms: // -// PUNPCKHQDQ xmm xmm -// PUNPCKHQDQ m128 xmm -func PUNPCKHQDQ(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PUNPCKHQDQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PUNPCKHQDQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PUNPCKHQDQ: bad operands") +// VPROLVD.Z m128 xmm k xmm +// VPROLVD.Z m256 ymm k ymm +// VPROLVD.Z xmm xmm k xmm +// VPROLVD.Z ymm ymm k ymm +// VPROLVD.Z m512 zmm k zmm +// VPROLVD.Z zmm zmm k zmm +func VPROLVD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPROLVD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// PUNPCKHWL: Unpack and Interleave High-Order Words into Doublewords. +// VPROLVQ: Variable Rotate Packed Quadword Left. // // Forms: // -// PUNPCKHWL xmm xmm -// PUNPCKHWL m128 xmm -func PUNPCKHWL(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PUNPCKHWL", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PUNPCKHWL", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PUNPCKHWL: bad operands") +// VPROLVQ m128 xmm k xmm +// VPROLVQ m128 xmm xmm +// VPROLVQ m256 ymm k ymm +// VPROLVQ m256 ymm ymm +// VPROLVQ xmm xmm k xmm +// VPROLVQ xmm xmm xmm +// VPROLVQ ymm ymm k ymm +// VPROLVQ ymm ymm ymm +// VPROLVQ m512 zmm k zmm +// VPROLVQ m512 zmm zmm +// VPROLVQ zmm zmm k zmm +// VPROLVQ zmm zmm zmm +func VPROLVQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPROLVQ.Forms(), sffxs{}, ops) } -// PUNPCKLBW: Unpack and Interleave Low-Order Bytes into Words. +// VPROLVQ_BCST: Variable Rotate Packed Quadword Left (Broadcast). // // Forms: // -// PUNPCKLBW xmm xmm -// PUNPCKLBW m128 xmm -func PUNPCKLBW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PUNPCKLBW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PUNPCKLBW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PUNPCKLBW: bad operands") +// VPROLVQ.BCST m64 xmm k xmm +// VPROLVQ.BCST m64 xmm xmm +// VPROLVQ.BCST m64 ymm k ymm +// VPROLVQ.BCST m64 ymm ymm +// VPROLVQ.BCST m64 zmm k zmm +// VPROLVQ.BCST m64 zmm zmm +func VPROLVQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPROLVQ.Forms(), sffxs{sffxBCST}, ops) } -// PUNPCKLLQ: Unpack and Interleave Low-Order Doublewords into Quadwords. +// VPROLVQ_BCST_Z: Variable Rotate Packed Quadword Left (Broadcast, Zeroing Masking). // // Forms: // -// PUNPCKLLQ xmm xmm -// PUNPCKLLQ m128 xmm -func PUNPCKLLQ(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PUNPCKLLQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PUNPCKLLQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PUNPCKLLQ: bad operands") +// VPROLVQ.BCST.Z m64 xmm k xmm +// VPROLVQ.BCST.Z m64 ymm k ymm +// VPROLVQ.BCST.Z m64 zmm k zmm +func VPROLVQ_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPROLVQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// PUNPCKLQDQ: Unpack and Interleave Low-Order Quadwords into Double Quadwords. +// VPROLVQ_Z: Variable Rotate Packed Quadword Left (Zeroing Masking). // // Forms: // -// PUNPCKLQDQ xmm xmm -// PUNPCKLQDQ m128 xmm -func PUNPCKLQDQ(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PUNPCKLQDQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PUNPCKLQDQ", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PUNPCKLQDQ: bad operands") +// VPROLVQ.Z m128 xmm k xmm +// VPROLVQ.Z m256 ymm k ymm +// VPROLVQ.Z xmm xmm k xmm +// VPROLVQ.Z ymm ymm k ymm +// VPROLVQ.Z m512 zmm k zmm +// VPROLVQ.Z zmm zmm k zmm +func VPROLVQ_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPROLVQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// PUNPCKLWL: Unpack and Interleave Low-Order Words into Doublewords. +// VPRORD: Rotate Packed Doubleword Right. // // Forms: // -// PUNPCKLWL xmm xmm -// PUNPCKLWL m128 xmm -func PUNPCKLWL(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PUNPCKLWL", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PUNPCKLWL", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PUNPCKLWL: bad operands") +// VPRORD imm8 m128 k xmm +// VPRORD imm8 m128 xmm +// VPRORD imm8 m256 k ymm +// VPRORD imm8 m256 ymm +// VPRORD imm8 xmm k xmm +// VPRORD imm8 xmm xmm +// VPRORD imm8 ymm k ymm +// VPRORD imm8 ymm ymm +// VPRORD imm8 m512 k zmm +// VPRORD imm8 m512 zmm +// VPRORD imm8 zmm k zmm +// VPRORD imm8 zmm zmm +func VPRORD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPRORD.Forms(), sffxs{}, ops) } -// PUSHQ: Push Value Onto the Stack. +// VPRORD_BCST: Rotate Packed Doubleword Right (Broadcast). // // Forms: // -// PUSHQ imm8 -// PUSHQ imm32 -// PUSHQ r64 -// PUSHQ m64 -func PUSHQ(imr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(imr): - return &intrep.Instruction{ - Opcode: "PUSHQ", - Operands: []operand.Op{imr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - }, nil - case operand.IsIMM32(imr): - return &intrep.Instruction{ - Opcode: "PUSHQ", - Operands: []operand.Op{imr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - }, nil - case operand.IsR64(imr): - return &intrep.Instruction{ - Opcode: "PUSHQ", - Operands: []operand.Op{imr}, - Inputs: []operand.Op{imr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsM64(imr): - return &intrep.Instruction{ - Opcode: "PUSHQ", - Operands: []operand.Op{imr}, - Inputs: []operand.Op{imr}, - Outputs: []operand.Op{}, - }, nil - } - return nil, errors.New("PUSHQ: bad operands") +// VPRORD.BCST imm8 m32 k xmm +// VPRORD.BCST imm8 m32 k ymm +// VPRORD.BCST imm8 m32 xmm +// VPRORD.BCST imm8 m32 ymm +// VPRORD.BCST imm8 m32 k zmm +// VPRORD.BCST imm8 m32 zmm +func VPRORD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPRORD.Forms(), sffxs{sffxBCST}, ops) } -// PUSHW: Push Value Onto the Stack. +// VPRORD_BCST_Z: Rotate Packed Doubleword Right (Broadcast, Zeroing Masking). // // Forms: // -// PUSHW r16 -// PUSHW m16 -func PUSHW(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "PUSHW", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "PUSHW", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{}, - }, nil - } - return nil, errors.New("PUSHW: bad operands") +// VPRORD.BCST.Z imm8 m32 k xmm +// VPRORD.BCST.Z imm8 m32 k ymm +// VPRORD.BCST.Z imm8 m32 k zmm +func VPRORD_BCST_Z(i, m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPRORD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{i, m, k, xyz}) } -// PXOR: Packed Bitwise Logical Exclusive OR. +// VPRORD_Z: Rotate Packed Doubleword Right (Zeroing Masking). // // Forms: // -// PXOR xmm xmm -// PXOR m128 xmm -func PXOR(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PXOR", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "PXOR", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("PXOR: bad operands") +// VPRORD.Z imm8 m128 k xmm +// VPRORD.Z imm8 m256 k ymm +// VPRORD.Z imm8 xmm k xmm +// VPRORD.Z imm8 ymm k ymm +// VPRORD.Z imm8 m512 k zmm +// VPRORD.Z imm8 zmm k zmm +func VPRORD_Z(i, mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPRORD.Forms(), sffxs{sffxZ}, []operand.Op{i, mxyz, k, xyz}) } -// RCLB: Rotate Left through Carry Flag. +// VPRORQ: Rotate Packed Quadword Right. // // Forms: // -// RCLB 1 r8 -// RCLB imm8 r8 -// RCLB cl r8 -// RCLB 1 m8 -// RCLB imm8 m8 -// RCLB cl m8 -func RCLB(ci, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.Is1(ci) && operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "RCLB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "RCLB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "RCLB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.Is1(ci) && operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "RCLB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "RCLB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "RCLB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("RCLB: bad operands") +// VPRORQ imm8 m128 k xmm +// VPRORQ imm8 m128 xmm +// VPRORQ imm8 m256 k ymm +// VPRORQ imm8 m256 ymm +// VPRORQ imm8 xmm k xmm +// VPRORQ imm8 xmm xmm +// VPRORQ imm8 ymm k ymm +// VPRORQ imm8 ymm ymm +// VPRORQ imm8 m512 k zmm +// VPRORQ imm8 m512 zmm +// VPRORQ imm8 zmm k zmm +// VPRORQ imm8 zmm zmm +func VPRORQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPRORQ.Forms(), sffxs{}, ops) } -// RCLL: Rotate Left through Carry Flag. +// VPRORQ_BCST: Rotate Packed Quadword Right (Broadcast). // // Forms: // -// RCLL 1 r32 -// RCLL imm8 r32 -// RCLL cl r32 -// RCLL 1 m32 -// RCLL imm8 m32 -// RCLL cl m32 -func RCLL(ci, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.Is1(ci) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "RCLL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "RCLL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "RCLL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.Is1(ci) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "RCLL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "RCLL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "RCLL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("RCLL: bad operands") +// VPRORQ.BCST imm8 m64 k xmm +// VPRORQ.BCST imm8 m64 k ymm +// VPRORQ.BCST imm8 m64 xmm +// VPRORQ.BCST imm8 m64 ymm +// VPRORQ.BCST imm8 m64 k zmm +// VPRORQ.BCST imm8 m64 zmm +func VPRORQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPRORQ.Forms(), sffxs{sffxBCST}, ops) } -// RCLQ: Rotate Left through Carry Flag. +// VPRORQ_BCST_Z: Rotate Packed Quadword Right (Broadcast, Zeroing Masking). // // Forms: // -// RCLQ 1 r64 -// RCLQ imm8 r64 -// RCLQ cl r64 -// RCLQ 1 m64 -// RCLQ imm8 m64 -// RCLQ cl m64 -func RCLQ(ci, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.Is1(ci) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "RCLQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "RCLQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "RCLQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.Is1(ci) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "RCLQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "RCLQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "RCLQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("RCLQ: bad operands") +// VPRORQ.BCST.Z imm8 m64 k xmm +// VPRORQ.BCST.Z imm8 m64 k ymm +// VPRORQ.BCST.Z imm8 m64 k zmm +func VPRORQ_BCST_Z(i, m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPRORQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{i, m, k, xyz}) } -// RCLW: Rotate Left through Carry Flag. +// VPRORQ_Z: Rotate Packed Quadword Right (Zeroing Masking). // // Forms: // -// RCLW 1 r16 -// RCLW imm8 r16 -// RCLW cl r16 -// RCLW 1 m16 -// RCLW imm8 m16 -// RCLW cl m16 -func RCLW(ci, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.Is1(ci) && operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "RCLW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "RCLW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "RCLW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.Is1(ci) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "RCLW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "RCLW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "RCLW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("RCLW: bad operands") +// VPRORQ.Z imm8 m128 k xmm +// VPRORQ.Z imm8 m256 k ymm +// VPRORQ.Z imm8 xmm k xmm +// VPRORQ.Z imm8 ymm k ymm +// VPRORQ.Z imm8 m512 k zmm +// VPRORQ.Z imm8 zmm k zmm +func VPRORQ_Z(i, mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPRORQ.Forms(), sffxs{sffxZ}, []operand.Op{i, mxyz, k, xyz}) } -// RCPPS: Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values. +// VPRORVD: Variable Rotate Packed Doubleword Right. // // Forms: // -// RCPPS xmm xmm -// RCPPS m128 xmm -func RCPPS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "RCPPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "RCPPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("RCPPS: bad operands") +// VPRORVD m128 xmm k xmm +// VPRORVD m128 xmm xmm +// VPRORVD m256 ymm k ymm +// VPRORVD m256 ymm ymm +// VPRORVD xmm xmm k xmm +// VPRORVD xmm xmm xmm +// VPRORVD ymm ymm k ymm +// VPRORVD ymm ymm ymm +// VPRORVD m512 zmm k zmm +// VPRORVD m512 zmm zmm +// VPRORVD zmm zmm k zmm +// VPRORVD zmm zmm zmm +func VPRORVD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPRORVD.Forms(), sffxs{}, ops) } -// RCPSS: Compute Approximate Reciprocal of Scalar Single-Precision Floating-Point Values. +// VPRORVD_BCST: Variable Rotate Packed Doubleword Right (Broadcast). // // Forms: // -// RCPSS xmm xmm -// RCPSS m32 xmm -func RCPSS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "RCPSS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "RCPSS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("RCPSS: bad operands") +// VPRORVD.BCST m32 xmm k xmm +// VPRORVD.BCST m32 xmm xmm +// VPRORVD.BCST m32 ymm k ymm +// VPRORVD.BCST m32 ymm ymm +// VPRORVD.BCST m32 zmm k zmm +// VPRORVD.BCST m32 zmm zmm +func VPRORVD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPRORVD.Forms(), sffxs{sffxBCST}, ops) } -// RCRB: Rotate Right through Carry Flag. +// VPRORVD_BCST_Z: Variable Rotate Packed Doubleword Right (Broadcast, Zeroing Masking). // // Forms: // -// RCRB 1 r8 -// RCRB imm8 r8 -// RCRB cl r8 -// RCRB 1 m8 -// RCRB imm8 m8 -// RCRB cl m8 -func RCRB(ci, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.Is1(ci) && operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "RCRB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "RCRB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "RCRB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.Is1(ci) && operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "RCRB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "RCRB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "RCRB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("RCRB: bad operands") +// VPRORVD.BCST.Z m32 xmm k xmm +// VPRORVD.BCST.Z m32 ymm k ymm +// VPRORVD.BCST.Z m32 zmm k zmm +func VPRORVD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPRORVD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// RCRL: Rotate Right through Carry Flag. +// VPRORVD_Z: Variable Rotate Packed Doubleword Right (Zeroing Masking). // // Forms: // -// RCRL 1 r32 -// RCRL imm8 r32 -// RCRL cl r32 -// RCRL 1 m32 -// RCRL imm8 m32 -// RCRL cl m32 -func RCRL(ci, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.Is1(ci) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "RCRL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "RCRL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "RCRL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.Is1(ci) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "RCRL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "RCRL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "RCRL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("RCRL: bad operands") +// VPRORVD.Z m128 xmm k xmm +// VPRORVD.Z m256 ymm k ymm +// VPRORVD.Z xmm xmm k xmm +// VPRORVD.Z ymm ymm k ymm +// VPRORVD.Z m512 zmm k zmm +// VPRORVD.Z zmm zmm k zmm +func VPRORVD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPRORVD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// RCRQ: Rotate Right through Carry Flag. +// VPRORVQ: Variable Rotate Packed Quadword Right. // // Forms: // -// RCRQ 1 r64 -// RCRQ imm8 r64 -// RCRQ cl r64 -// RCRQ 1 m64 -// RCRQ imm8 m64 -// RCRQ cl m64 -func RCRQ(ci, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.Is1(ci) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "RCRQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "RCRQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "RCRQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.Is1(ci) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "RCRQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "RCRQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "RCRQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("RCRQ: bad operands") +// VPRORVQ m128 xmm k xmm +// VPRORVQ m128 xmm xmm +// VPRORVQ m256 ymm k ymm +// VPRORVQ m256 ymm ymm +// VPRORVQ xmm xmm k xmm +// VPRORVQ xmm xmm xmm +// VPRORVQ ymm ymm k ymm +// VPRORVQ ymm ymm ymm +// VPRORVQ m512 zmm k zmm +// VPRORVQ m512 zmm zmm +// VPRORVQ zmm zmm k zmm +// VPRORVQ zmm zmm zmm +func VPRORVQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPRORVQ.Forms(), sffxs{}, ops) } -// RCRW: Rotate Right through Carry Flag. +// VPRORVQ_BCST: Variable Rotate Packed Quadword Right (Broadcast). // // Forms: // -// RCRW 1 r16 -// RCRW imm8 r16 -// RCRW cl r16 -// RCRW 1 m16 -// RCRW imm8 m16 -// RCRW cl m16 -func RCRW(ci, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.Is1(ci) && operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "RCRW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "RCRW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "RCRW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.Is1(ci) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "RCRW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "RCRW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "RCRW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("RCRW: bad operands") +// VPRORVQ.BCST m64 xmm k xmm +// VPRORVQ.BCST m64 xmm xmm +// VPRORVQ.BCST m64 ymm k ymm +// VPRORVQ.BCST m64 ymm ymm +// VPRORVQ.BCST m64 zmm k zmm +// VPRORVQ.BCST m64 zmm zmm +func VPRORVQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPRORVQ.Forms(), sffxs{sffxBCST}, ops) } -// RDRANDL: Read Random Number. +// VPRORVQ_BCST_Z: Variable Rotate Packed Quadword Right (Broadcast, Zeroing Masking). // // Forms: // -// RDRANDL r32 -func RDRANDL(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "RDRANDL", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{r}, - ISA: []string{"RDRAND"}, - }, nil - } - return nil, errors.New("RDRANDL: bad operands") +// VPRORVQ.BCST.Z m64 xmm k xmm +// VPRORVQ.BCST.Z m64 ymm k ymm +// VPRORVQ.BCST.Z m64 zmm k zmm +func VPRORVQ_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPRORVQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// RDRANDQ: Read Random Number. +// VPRORVQ_Z: Variable Rotate Packed Quadword Right (Zeroing Masking). // // Forms: // -// RDRANDQ r64 -func RDRANDQ(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "RDRANDQ", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{r}, - ISA: []string{"RDRAND"}, - }, nil - } - return nil, errors.New("RDRANDQ: bad operands") +// VPRORVQ.Z m128 xmm k xmm +// VPRORVQ.Z m256 ymm k ymm +// VPRORVQ.Z xmm xmm k xmm +// VPRORVQ.Z ymm ymm k ymm +// VPRORVQ.Z m512 zmm k zmm +// VPRORVQ.Z zmm zmm k zmm +func VPRORVQ_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPRORVQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// RDRANDW: Read Random Number. +// VPSADBW: Compute Sum of Absolute Differences. // // Forms: // -// RDRANDW r16 -func RDRANDW(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "RDRANDW", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{r}, - ISA: []string{"RDRAND"}, - }, nil - } - return nil, errors.New("RDRANDW: bad operands") +// VPSADBW m256 ymm ymm +// VPSADBW ymm ymm ymm +// VPSADBW m128 xmm xmm +// VPSADBW xmm xmm xmm +// VPSADBW m512 zmm zmm +// VPSADBW zmm zmm zmm +func VPSADBW(mxyz, xyz, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPSADBW.Forms(), sffxs{}, []operand.Op{mxyz, xyz, xyz1}) } -// RDSEEDL: Read Random SEED. +// VPSCATTERDD: Scatter Packed Doubleword Values with Signed Doubleword Indices. // // Forms: // -// RDSEEDL r32 -func RDSEEDL(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "RDSEEDL", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{r}, - ISA: []string{"RDSEED"}, - }, nil - } - return nil, errors.New("RDSEEDL: bad operands") +// VPSCATTERDD xmm k vm32x +// VPSCATTERDD ymm k vm32y +// VPSCATTERDD zmm k vm32z +func VPSCATTERDD(xyz, k, v operand.Op) (*intrep.Instruction, error) { + return build(opcVPSCATTERDD.Forms(), sffxs{}, []operand.Op{xyz, k, v}) } -// RDSEEDQ: Read Random SEED. +// VPSCATTERDQ: Scatter Packed Quadword Values with Signed Doubleword Indices. // // Forms: // -// RDSEEDQ r64 -func RDSEEDQ(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "RDSEEDQ", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{r}, - ISA: []string{"RDSEED"}, - }, nil - } - return nil, errors.New("RDSEEDQ: bad operands") +// VPSCATTERDQ xmm k vm32x +// VPSCATTERDQ ymm k vm32x +// VPSCATTERDQ zmm k vm32y +func VPSCATTERDQ(xyz, k, v operand.Op) (*intrep.Instruction, error) { + return build(opcVPSCATTERDQ.Forms(), sffxs{}, []operand.Op{xyz, k, v}) } -// RDSEEDW: Read Random SEED. +// VPSCATTERQD: Scatter Packed Doubleword Values with Signed Quadword Indices. // // Forms: // -// RDSEEDW r16 -func RDSEEDW(r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "RDSEEDW", - Operands: []operand.Op{r}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{r}, - ISA: []string{"RDSEED"}, - }, nil - } - return nil, errors.New("RDSEEDW: bad operands") +// VPSCATTERQD xmm k vm64x +// VPSCATTERQD xmm k vm64y +// VPSCATTERQD ymm k vm64z +func VPSCATTERQD(xy, k, v operand.Op) (*intrep.Instruction, error) { + return build(opcVPSCATTERQD.Forms(), sffxs{}, []operand.Op{xy, k, v}) } -// RDTSC: Read Time-Stamp Counter. +// VPSCATTERQQ: Scatter Packed Quadword Values with Signed Quadword Indices. // // Forms: // -// RDTSC -func RDTSC() (*intrep.Instruction, error) { - return &intrep.Instruction{ - Opcode: "RDTSC", - Operands: nil, - Inputs: []operand.Op{}, - Outputs: []operand.Op{reg.EAX, reg.EDX}, - ISA: []string{"RDTSC"}, - }, nil +// VPSCATTERQQ xmm k vm64x +// VPSCATTERQQ ymm k vm64y +// VPSCATTERQQ zmm k vm64z +func VPSCATTERQQ(xyz, k, v operand.Op) (*intrep.Instruction, error) { + return build(opcVPSCATTERQQ.Forms(), sffxs{}, []operand.Op{xyz, k, v}) } -// RDTSCP: Read Time-Stamp Counter and Processor ID. +// VPSHUFB: Packed Shuffle Bytes. // // Forms: // -// RDTSCP -func RDTSCP() (*intrep.Instruction, error) { - return &intrep.Instruction{ - Opcode: "RDTSCP", - Operands: nil, - Inputs: []operand.Op{}, - Outputs: []operand.Op{reg.EAX, reg.ECX, reg.EDX}, - ISA: []string{"RDTSCP"}, - }, nil +// VPSHUFB m256 ymm ymm +// VPSHUFB ymm ymm ymm +// VPSHUFB m128 xmm xmm +// VPSHUFB xmm xmm xmm +// VPSHUFB m128 xmm k xmm +// VPSHUFB m256 ymm k ymm +// VPSHUFB xmm xmm k xmm +// VPSHUFB ymm ymm k ymm +// VPSHUFB m512 zmm k zmm +// VPSHUFB m512 zmm zmm +// VPSHUFB zmm zmm k zmm +// VPSHUFB zmm zmm zmm +func VPSHUFB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSHUFB.Forms(), sffxs{}, ops) } -// RET: Return from Procedure. +// VPSHUFB_Z: Packed Shuffle Bytes (Zeroing Masking). // // Forms: // -// RET -func RET() (*intrep.Instruction, error) { - return &intrep.Instruction{ - Opcode: "RET", - Operands: nil, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - IsTerminal: true, - }, nil +// VPSHUFB.Z m128 xmm k xmm +// VPSHUFB.Z m256 ymm k ymm +// VPSHUFB.Z xmm xmm k xmm +// VPSHUFB.Z ymm ymm k ymm +// VPSHUFB.Z m512 zmm k zmm +// VPSHUFB.Z zmm zmm k zmm +func VPSHUFB_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPSHUFB.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// RETFL: Return from Procedure. +// VPSHUFD: Shuffle Packed Doublewords. // // Forms: // -// RETFL imm16 -func RETFL(i operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM16(i): - return &intrep.Instruction{ - Opcode: "RETFL", - Operands: []operand.Op{i}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - }, nil - } - return nil, errors.New("RETFL: bad operands") +// VPSHUFD imm8 m256 ymm +// VPSHUFD imm8 ymm ymm +// VPSHUFD imm8 m128 xmm +// VPSHUFD imm8 xmm xmm +// VPSHUFD imm8 m128 k xmm +// VPSHUFD imm8 m256 k ymm +// VPSHUFD imm8 xmm k xmm +// VPSHUFD imm8 ymm k ymm +// VPSHUFD imm8 m512 k zmm +// VPSHUFD imm8 m512 zmm +// VPSHUFD imm8 zmm k zmm +// VPSHUFD imm8 zmm zmm +func VPSHUFD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSHUFD.Forms(), sffxs{}, ops) } -// RETFQ: Return from Procedure. +// VPSHUFD_BCST: Shuffle Packed Doublewords (Broadcast). // // Forms: // -// RETFQ imm16 -func RETFQ(i operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM16(i): - return &intrep.Instruction{ - Opcode: "RETFQ", - Operands: []operand.Op{i}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - }, nil - } - return nil, errors.New("RETFQ: bad operands") +// VPSHUFD.BCST imm8 m32 k xmm +// VPSHUFD.BCST imm8 m32 k ymm +// VPSHUFD.BCST imm8 m32 xmm +// VPSHUFD.BCST imm8 m32 ymm +// VPSHUFD.BCST imm8 m32 k zmm +// VPSHUFD.BCST imm8 m32 zmm +func VPSHUFD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSHUFD.Forms(), sffxs{sffxBCST}, ops) } -// RETFW: Return from Procedure. +// VPSHUFD_BCST_Z: Shuffle Packed Doublewords (Broadcast, Zeroing Masking). // // Forms: // -// RETFW imm16 -func RETFW(i operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM16(i): - return &intrep.Instruction{ - Opcode: "RETFW", - Operands: []operand.Op{i}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - }, nil - } - return nil, errors.New("RETFW: bad operands") +// VPSHUFD.BCST.Z imm8 m32 k xmm +// VPSHUFD.BCST.Z imm8 m32 k ymm +// VPSHUFD.BCST.Z imm8 m32 k zmm +func VPSHUFD_BCST_Z(i, m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPSHUFD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{i, m, k, xyz}) } -// ROLB: Rotate Left. +// VPSHUFD_Z: Shuffle Packed Doublewords (Zeroing Masking). // // Forms: // -// ROLB 1 r8 -// ROLB imm8 r8 -// ROLB cl r8 -// ROLB 1 m8 -// ROLB imm8 m8 -// ROLB cl m8 -func ROLB(ci, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.Is1(ci) && operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "ROLB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "ROLB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "ROLB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.Is1(ci) && operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "ROLB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "ROLB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "ROLB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("ROLB: bad operands") +// VPSHUFD.Z imm8 m128 k xmm +// VPSHUFD.Z imm8 m256 k ymm +// VPSHUFD.Z imm8 xmm k xmm +// VPSHUFD.Z imm8 ymm k ymm +// VPSHUFD.Z imm8 m512 k zmm +// VPSHUFD.Z imm8 zmm k zmm +func VPSHUFD_Z(i, mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPSHUFD.Forms(), sffxs{sffxZ}, []operand.Op{i, mxyz, k, xyz}) } -// ROLL: Rotate Left. +// VPSHUFHW: Shuffle Packed High Words. // // Forms: // -// ROLL 1 r32 -// ROLL imm8 r32 -// ROLL cl r32 -// ROLL 1 m32 -// ROLL imm8 m32 -// ROLL cl m32 -func ROLL(ci, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.Is1(ci) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "ROLL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "ROLL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "ROLL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.Is1(ci) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "ROLL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "ROLL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "ROLL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("ROLL: bad operands") +// VPSHUFHW imm8 m256 ymm +// VPSHUFHW imm8 ymm ymm +// VPSHUFHW imm8 m128 xmm +// VPSHUFHW imm8 xmm xmm +// VPSHUFHW imm8 m128 k xmm +// VPSHUFHW imm8 m256 k ymm +// VPSHUFHW imm8 xmm k xmm +// VPSHUFHW imm8 ymm k ymm +// VPSHUFHW imm8 m512 k zmm +// VPSHUFHW imm8 m512 zmm +// VPSHUFHW imm8 zmm k zmm +// VPSHUFHW imm8 zmm zmm +func VPSHUFHW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSHUFHW.Forms(), sffxs{}, ops) } -// ROLQ: Rotate Left. +// VPSHUFHW_Z: Shuffle Packed High Words (Zeroing Masking). // // Forms: // -// ROLQ 1 r64 -// ROLQ imm8 r64 -// ROLQ cl r64 -// ROLQ 1 m64 -// ROLQ imm8 m64 -// ROLQ cl m64 -func ROLQ(ci, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.Is1(ci) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "ROLQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "ROLQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "ROLQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.Is1(ci) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "ROLQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "ROLQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "ROLQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("ROLQ: bad operands") +// VPSHUFHW.Z imm8 m128 k xmm +// VPSHUFHW.Z imm8 m256 k ymm +// VPSHUFHW.Z imm8 xmm k xmm +// VPSHUFHW.Z imm8 ymm k ymm +// VPSHUFHW.Z imm8 m512 k zmm +// VPSHUFHW.Z imm8 zmm k zmm +func VPSHUFHW_Z(i, mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPSHUFHW.Forms(), sffxs{sffxZ}, []operand.Op{i, mxyz, k, xyz}) } -// ROLW: Rotate Left. +// VPSHUFLW: Shuffle Packed Low Words. // // Forms: // -// ROLW 1 r16 -// ROLW imm8 r16 -// ROLW cl r16 -// ROLW 1 m16 -// ROLW imm8 m16 -// ROLW cl m16 -func ROLW(ci, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.Is1(ci) && operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "ROLW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "ROLW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "ROLW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.Is1(ci) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "ROLW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "ROLW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "ROLW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("ROLW: bad operands") +// VPSHUFLW imm8 m256 ymm +// VPSHUFLW imm8 ymm ymm +// VPSHUFLW imm8 m128 xmm +// VPSHUFLW imm8 xmm xmm +// VPSHUFLW imm8 m128 k xmm +// VPSHUFLW imm8 m256 k ymm +// VPSHUFLW imm8 xmm k xmm +// VPSHUFLW imm8 ymm k ymm +// VPSHUFLW imm8 m512 k zmm +// VPSHUFLW imm8 m512 zmm +// VPSHUFLW imm8 zmm k zmm +// VPSHUFLW imm8 zmm zmm +func VPSHUFLW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSHUFLW.Forms(), sffxs{}, ops) } -// RORB: Rotate Right. +// VPSHUFLW_Z: Shuffle Packed Low Words (Zeroing Masking). // // Forms: // -// RORB 1 r8 -// RORB imm8 r8 -// RORB cl r8 -// RORB 1 m8 -// RORB imm8 m8 -// RORB cl m8 -func RORB(ci, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.Is1(ci) && operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "RORB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "RORB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "RORB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.Is1(ci) && operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "RORB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "RORB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "RORB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("RORB: bad operands") +// VPSHUFLW.Z imm8 m128 k xmm +// VPSHUFLW.Z imm8 m256 k ymm +// VPSHUFLW.Z imm8 xmm k xmm +// VPSHUFLW.Z imm8 ymm k ymm +// VPSHUFLW.Z imm8 m512 k zmm +// VPSHUFLW.Z imm8 zmm k zmm +func VPSHUFLW_Z(i, mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPSHUFLW.Forms(), sffxs{sffxZ}, []operand.Op{i, mxyz, k, xyz}) } -// RORL: Rotate Right. +// VPSIGNB: Packed Sign of Byte Integers. // // Forms: // -// RORL 1 r32 -// RORL imm8 r32 -// RORL cl r32 -// RORL 1 m32 -// RORL imm8 m32 -// RORL cl m32 -func RORL(ci, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.Is1(ci) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "RORL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "RORL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "RORL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.Is1(ci) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "RORL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "RORL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "RORL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("RORL: bad operands") +// VPSIGNB m256 ymm ymm +// VPSIGNB ymm ymm ymm +// VPSIGNB m128 xmm xmm +// VPSIGNB xmm xmm xmm +func VPSIGNB(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPSIGNB.Forms(), sffxs{}, []operand.Op{mxy, xy, xy1}) } -// RORQ: Rotate Right. +// VPSIGND: Packed Sign of Doubleword Integers. // // Forms: // -// RORQ 1 r64 -// RORQ imm8 r64 -// RORQ cl r64 -// RORQ 1 m64 -// RORQ imm8 m64 -// RORQ cl m64 -func RORQ(ci, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.Is1(ci) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "RORQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "RORQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "RORQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.Is1(ci) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "RORQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "RORQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "RORQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("RORQ: bad operands") +// VPSIGND m256 ymm ymm +// VPSIGND ymm ymm ymm +// VPSIGND m128 xmm xmm +// VPSIGND xmm xmm xmm +func VPSIGND(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPSIGND.Forms(), sffxs{}, []operand.Op{mxy, xy, xy1}) } -// RORW: Rotate Right. +// VPSIGNW: Packed Sign of Word Integers. // // Forms: // -// RORW 1 r16 -// RORW imm8 r16 -// RORW cl r16 -// RORW 1 m16 -// RORW imm8 m16 -// RORW cl m16 -func RORW(ci, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.Is1(ci) && operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "RORW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "RORW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "RORW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.Is1(ci) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "RORW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "RORW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "RORW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("RORW: bad operands") +// VPSIGNW m256 ymm ymm +// VPSIGNW ymm ymm ymm +// VPSIGNW m128 xmm xmm +// VPSIGNW xmm xmm xmm +func VPSIGNW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPSIGNW.Forms(), sffxs{}, []operand.Op{mxy, xy, xy1}) } -// RORXL: Rotate Right Logical Without Affecting Flags. +// VPSLLD: Shift Packed Doubleword Data Left Logical. // // Forms: // -// RORXL imm8 r32 r32 -// RORXL imm8 m32 r32 -func RORXL(i, mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsR32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "RORXL", - Operands: []operand.Op{i, mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"BMI2"}, - }, nil - case operand.IsIMM8(i) && operand.IsM32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "RORXL", - Operands: []operand.Op{i, mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"BMI2"}, - }, nil - } - return nil, errors.New("RORXL: bad operands") +// VPSLLD imm8 ymm ymm +// VPSLLD m128 ymm ymm +// VPSLLD xmm ymm ymm +// VPSLLD imm8 xmm xmm +// VPSLLD m128 xmm xmm +// VPSLLD xmm xmm xmm +// VPSLLD imm8 m128 k xmm +// VPSLLD imm8 m128 xmm +// VPSLLD imm8 m256 k ymm +// VPSLLD imm8 m256 ymm +// VPSLLD imm8 xmm k xmm +// VPSLLD imm8 ymm k ymm +// VPSLLD m128 xmm k xmm +// VPSLLD m128 ymm k ymm +// VPSLLD xmm xmm k xmm +// VPSLLD xmm ymm k ymm +// VPSLLD imm8 m512 k zmm +// VPSLLD imm8 m512 zmm +// VPSLLD imm8 zmm k zmm +// VPSLLD imm8 zmm zmm +// VPSLLD m128 zmm k zmm +// VPSLLD m128 zmm zmm +// VPSLLD xmm zmm k zmm +// VPSLLD xmm zmm zmm +func VPSLLD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSLLD.Forms(), sffxs{}, ops) } -// RORXQ: Rotate Right Logical Without Affecting Flags. +// VPSLLDQ: Shift Packed Double Quadword Left Logical. // // Forms: // -// RORXQ imm8 r64 r64 -// RORXQ imm8 m64 r64 -func RORXQ(i, mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsR64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "RORXQ", - Operands: []operand.Op{i, mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"BMI2"}, - }, nil - case operand.IsIMM8(i) && operand.IsM64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "RORXQ", - Operands: []operand.Op{i, mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"BMI2"}, - }, nil - } - return nil, errors.New("RORXQ: bad operands") +// VPSLLDQ imm8 ymm ymm +// VPSLLDQ imm8 xmm xmm +// VPSLLDQ imm8 m128 xmm +// VPSLLDQ imm8 m256 ymm +// VPSLLDQ imm8 m512 zmm +// VPSLLDQ imm8 zmm zmm +func VPSLLDQ(i, mxyz, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPSLLDQ.Forms(), sffxs{}, []operand.Op{i, mxyz, xyz}) } -// ROUNDPD: Round Packed Double Precision Floating-Point Values. +// VPSLLD_BCST: Shift Packed Doubleword Data Left Logical (Broadcast). // // Forms: // -// ROUNDPD imm8 xmm xmm -// ROUNDPD imm8 m128 xmm -func ROUNDPD(i, mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ROUNDPD", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ROUNDPD", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("ROUNDPD: bad operands") +// VPSLLD.BCST imm8 m32 k xmm +// VPSLLD.BCST imm8 m32 k ymm +// VPSLLD.BCST imm8 m32 xmm +// VPSLLD.BCST imm8 m32 ymm +// VPSLLD.BCST imm8 m32 k zmm +// VPSLLD.BCST imm8 m32 zmm +func VPSLLD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSLLD.Forms(), sffxs{sffxBCST}, ops) } -// ROUNDPS: Round Packed Single Precision Floating-Point Values. +// VPSLLD_BCST_Z: Shift Packed Doubleword Data Left Logical (Broadcast, Zeroing Masking). // // Forms: // -// ROUNDPS imm8 xmm xmm -// ROUNDPS imm8 m128 xmm -func ROUNDPS(i, mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ROUNDPS", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ROUNDPS", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("ROUNDPS: bad operands") +// VPSLLD.BCST.Z imm8 m32 k xmm +// VPSLLD.BCST.Z imm8 m32 k ymm +// VPSLLD.BCST.Z imm8 m32 k zmm +func VPSLLD_BCST_Z(i, m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPSLLD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{i, m, k, xyz}) } -// ROUNDSD: Round Scalar Double Precision Floating-Point Values. +// VPSLLD_Z: Shift Packed Doubleword Data Left Logical (Zeroing Masking). // // Forms: // -// ROUNDSD imm8 xmm xmm -// ROUNDSD imm8 m64 xmm -func ROUNDSD(i, mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ROUNDSD", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsIMM8(i) && operand.IsM64(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ROUNDSD", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("ROUNDSD: bad operands") +// VPSLLD.Z imm8 m128 k xmm +// VPSLLD.Z imm8 m256 k ymm +// VPSLLD.Z imm8 xmm k xmm +// VPSLLD.Z imm8 ymm k ymm +// VPSLLD.Z m128 xmm k xmm +// VPSLLD.Z m128 ymm k ymm +// VPSLLD.Z xmm xmm k xmm +// VPSLLD.Z xmm ymm k ymm +// VPSLLD.Z imm8 m512 k zmm +// VPSLLD.Z imm8 zmm k zmm +// VPSLLD.Z m128 zmm k zmm +// VPSLLD.Z xmm zmm k zmm +func VPSLLD_Z(imx, mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPSLLD.Forms(), sffxs{sffxZ}, []operand.Op{imx, mxyz, k, xyz}) } -// ROUNDSS: Round Scalar Single Precision Floating-Point Values. +// VPSLLQ: Shift Packed Quadword Data Left Logical. // // Forms: // -// ROUNDSS imm8 xmm xmm -// ROUNDSS imm8 m32 xmm -func ROUNDSS(i, mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ROUNDSS", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - case operand.IsIMM8(i) && operand.IsM32(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "ROUNDSS", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE4.1"}, - }, nil - } - return nil, errors.New("ROUNDSS: bad operands") +// VPSLLQ imm8 ymm ymm +// VPSLLQ m128 ymm ymm +// VPSLLQ xmm ymm ymm +// VPSLLQ imm8 xmm xmm +// VPSLLQ m128 xmm xmm +// VPSLLQ xmm xmm xmm +// VPSLLQ imm8 m128 k xmm +// VPSLLQ imm8 m128 xmm +// VPSLLQ imm8 m256 k ymm +// VPSLLQ imm8 m256 ymm +// VPSLLQ imm8 xmm k xmm +// VPSLLQ imm8 ymm k ymm +// VPSLLQ m128 xmm k xmm +// VPSLLQ m128 ymm k ymm +// VPSLLQ xmm xmm k xmm +// VPSLLQ xmm ymm k ymm +// VPSLLQ imm8 m512 k zmm +// VPSLLQ imm8 m512 zmm +// VPSLLQ imm8 zmm k zmm +// VPSLLQ imm8 zmm zmm +// VPSLLQ m128 zmm k zmm +// VPSLLQ m128 zmm zmm +// VPSLLQ xmm zmm k zmm +// VPSLLQ xmm zmm zmm +func VPSLLQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSLLQ.Forms(), sffxs{}, ops) } -// RSQRTPS: Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values. +// VPSLLQ_BCST: Shift Packed Quadword Data Left Logical (Broadcast). // // Forms: // -// RSQRTPS xmm xmm -// RSQRTPS m128 xmm -func RSQRTPS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "RSQRTPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "RSQRTPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("RSQRTPS: bad operands") +// VPSLLQ.BCST imm8 m64 k xmm +// VPSLLQ.BCST imm8 m64 k ymm +// VPSLLQ.BCST imm8 m64 xmm +// VPSLLQ.BCST imm8 m64 ymm +// VPSLLQ.BCST imm8 m64 k zmm +// VPSLLQ.BCST imm8 m64 zmm +func VPSLLQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSLLQ.Forms(), sffxs{sffxBCST}, ops) } -// RSQRTSS: Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value. +// VPSLLQ_BCST_Z: Shift Packed Quadword Data Left Logical (Broadcast, Zeroing Masking). // // Forms: // -// RSQRTSS xmm xmm -// RSQRTSS m32 xmm -func RSQRTSS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "RSQRTSS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "RSQRTSS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("RSQRTSS: bad operands") +// VPSLLQ.BCST.Z imm8 m64 k xmm +// VPSLLQ.BCST.Z imm8 m64 k ymm +// VPSLLQ.BCST.Z imm8 m64 k zmm +func VPSLLQ_BCST_Z(i, m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPSLLQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{i, m, k, xyz}) } -// SALB: Arithmetic Shift Left. +// VPSLLQ_Z: Shift Packed Quadword Data Left Logical (Zeroing Masking). // // Forms: // -// SALB 1 r8 -// SALB imm8 r8 -// SALB cl r8 -// SALB 1 m8 -// SALB imm8 m8 -// SALB cl m8 -func SALB(ci, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.Is1(ci) && operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "SALB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "SALB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "SALB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.Is1(ci) && operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "SALB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "SALB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "SALB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("SALB: bad operands") +// VPSLLQ.Z imm8 m128 k xmm +// VPSLLQ.Z imm8 m256 k ymm +// VPSLLQ.Z imm8 xmm k xmm +// VPSLLQ.Z imm8 ymm k ymm +// VPSLLQ.Z m128 xmm k xmm +// VPSLLQ.Z m128 ymm k ymm +// VPSLLQ.Z xmm xmm k xmm +// VPSLLQ.Z xmm ymm k ymm +// VPSLLQ.Z imm8 m512 k zmm +// VPSLLQ.Z imm8 zmm k zmm +// VPSLLQ.Z m128 zmm k zmm +// VPSLLQ.Z xmm zmm k zmm +func VPSLLQ_Z(imx, mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPSLLQ.Forms(), sffxs{sffxZ}, []operand.Op{imx, mxyz, k, xyz}) } -// SALL: Arithmetic Shift Left. +// VPSLLVD: Variable Shift Packed Doubleword Data Left Logical. // // Forms: // -// SALL 1 r32 -// SALL imm8 r32 -// SALL cl r32 -// SALL 1 m32 -// SALL imm8 m32 -// SALL cl m32 -func SALL(ci, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.Is1(ci) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "SALL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "SALL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "SALL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.Is1(ci) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "SALL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "SALL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "SALL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("SALL: bad operands") +// VPSLLVD m128 xmm xmm +// VPSLLVD m256 ymm ymm +// VPSLLVD xmm xmm xmm +// VPSLLVD ymm ymm ymm +// VPSLLVD m128 xmm k xmm +// VPSLLVD m256 ymm k ymm +// VPSLLVD xmm xmm k xmm +// VPSLLVD ymm ymm k ymm +// VPSLLVD m512 zmm k zmm +// VPSLLVD m512 zmm zmm +// VPSLLVD zmm zmm k zmm +// VPSLLVD zmm zmm zmm +func VPSLLVD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSLLVD.Forms(), sffxs{}, ops) } -// SALQ: Arithmetic Shift Left. +// VPSLLVD_BCST: Variable Shift Packed Doubleword Data Left Logical (Broadcast). // // Forms: // -// SALQ 1 r64 -// SALQ imm8 r64 -// SALQ cl r64 -// SALQ 1 m64 -// SALQ imm8 m64 -// SALQ cl m64 -func SALQ(ci, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.Is1(ci) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "SALQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "SALQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "SALQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.Is1(ci) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "SALQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "SALQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "SALQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("SALQ: bad operands") +// VPSLLVD.BCST m32 xmm k xmm +// VPSLLVD.BCST m32 xmm xmm +// VPSLLVD.BCST m32 ymm k ymm +// VPSLLVD.BCST m32 ymm ymm +// VPSLLVD.BCST m32 zmm k zmm +// VPSLLVD.BCST m32 zmm zmm +func VPSLLVD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSLLVD.Forms(), sffxs{sffxBCST}, ops) } -// SALW: Arithmetic Shift Left. +// VPSLLVD_BCST_Z: Variable Shift Packed Doubleword Data Left Logical (Broadcast, Zeroing Masking). // // Forms: // -// SALW 1 r16 -// SALW imm8 r16 -// SALW cl r16 -// SALW 1 m16 -// SALW imm8 m16 -// SALW cl m16 -func SALW(ci, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.Is1(ci) && operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "SALW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "SALW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "SALW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.Is1(ci) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "SALW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "SALW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "SALW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("SALW: bad operands") +// VPSLLVD.BCST.Z m32 xmm k xmm +// VPSLLVD.BCST.Z m32 ymm k ymm +// VPSLLVD.BCST.Z m32 zmm k zmm +func VPSLLVD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPSLLVD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// SARB: Arithmetic Shift Right. +// VPSLLVD_Z: Variable Shift Packed Doubleword Data Left Logical (Zeroing Masking). // // Forms: // -// SARB 1 r8 -// SARB imm8 r8 -// SARB cl r8 -// SARB 1 m8 -// SARB imm8 m8 -// SARB cl m8 -func SARB(ci, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.Is1(ci) && operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "SARB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "SARB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "SARB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.Is1(ci) && operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "SARB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "SARB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "SARB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("SARB: bad operands") +// VPSLLVD.Z m128 xmm k xmm +// VPSLLVD.Z m256 ymm k ymm +// VPSLLVD.Z xmm xmm k xmm +// VPSLLVD.Z ymm ymm k ymm +// VPSLLVD.Z m512 zmm k zmm +// VPSLLVD.Z zmm zmm k zmm +func VPSLLVD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPSLLVD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// SARL: Arithmetic Shift Right. +// VPSLLVQ: Variable Shift Packed Quadword Data Left Logical. // // Forms: // -// SARL 1 r32 -// SARL imm8 r32 -// SARL cl r32 -// SARL 1 m32 -// SARL imm8 m32 -// SARL cl m32 -func SARL(ci, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.Is1(ci) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "SARL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "SARL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "SARL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.Is1(ci) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "SARL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "SARL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "SARL", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("SARL: bad operands") +// VPSLLVQ m128 xmm xmm +// VPSLLVQ m256 ymm ymm +// VPSLLVQ xmm xmm xmm +// VPSLLVQ ymm ymm ymm +// VPSLLVQ m128 xmm k xmm +// VPSLLVQ m256 ymm k ymm +// VPSLLVQ xmm xmm k xmm +// VPSLLVQ ymm ymm k ymm +// VPSLLVQ m512 zmm k zmm +// VPSLLVQ m512 zmm zmm +// VPSLLVQ zmm zmm k zmm +// VPSLLVQ zmm zmm zmm +func VPSLLVQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSLLVQ.Forms(), sffxs{}, ops) } -// SARQ: Arithmetic Shift Right. +// VPSLLVQ_BCST: Variable Shift Packed Quadword Data Left Logical (Broadcast). // // Forms: // -// SARQ 1 r64 -// SARQ imm8 r64 -// SARQ cl r64 -// SARQ 1 m64 -// SARQ imm8 m64 -// SARQ cl m64 -func SARQ(ci, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.Is1(ci) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "SARQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "SARQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "SARQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.Is1(ci) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "SARQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "SARQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "SARQ", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("SARQ: bad operands") +// VPSLLVQ.BCST m64 xmm k xmm +// VPSLLVQ.BCST m64 xmm xmm +// VPSLLVQ.BCST m64 ymm k ymm +// VPSLLVQ.BCST m64 ymm ymm +// VPSLLVQ.BCST m64 zmm k zmm +// VPSLLVQ.BCST m64 zmm zmm +func VPSLLVQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSLLVQ.Forms(), sffxs{sffxBCST}, ops) } -// SARW: Arithmetic Shift Right. +// VPSLLVQ_BCST_Z: Variable Shift Packed Quadword Data Left Logical (Broadcast, Zeroing Masking). // // Forms: // -// SARW 1 r16 -// SARW imm8 r16 -// SARW cl r16 -// SARW 1 m16 -// SARW imm8 m16 -// SARW cl m16 -func SARW(ci, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.Is1(ci) && operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "SARW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "SARW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "SARW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.Is1(ci) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "SARW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "SARW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "SARW", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("SARW: bad operands") +// VPSLLVQ.BCST.Z m64 xmm k xmm +// VPSLLVQ.BCST.Z m64 ymm k ymm +// VPSLLVQ.BCST.Z m64 zmm k zmm +func VPSLLVQ_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPSLLVQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// SARXL: Arithmetic Shift Right Without Affecting Flags. +// VPSLLVQ_Z: Variable Shift Packed Quadword Data Left Logical (Zeroing Masking). // // Forms: // -// SARXL r32 r32 r32 -// SARXL r32 m32 r32 -func SARXL(r, mr, r1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(r) && operand.IsR32(mr) && operand.IsR32(r1): - return &intrep.Instruction{ - Opcode: "SARXL", - Operands: []operand.Op{r, mr, r1}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI2"}, - }, nil - case operand.IsR32(r) && operand.IsM32(mr) && operand.IsR32(r1): - return &intrep.Instruction{ - Opcode: "SARXL", - Operands: []operand.Op{r, mr, r1}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI2"}, - }, nil - } - return nil, errors.New("SARXL: bad operands") +// VPSLLVQ.Z m128 xmm k xmm +// VPSLLVQ.Z m256 ymm k ymm +// VPSLLVQ.Z xmm xmm k xmm +// VPSLLVQ.Z ymm ymm k ymm +// VPSLLVQ.Z m512 zmm k zmm +// VPSLLVQ.Z zmm zmm k zmm +func VPSLLVQ_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPSLLVQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// SARXQ: Arithmetic Shift Right Without Affecting Flags. +// VPSLLVW: Variable Shift Packed Word Data Left Logical. // // Forms: // -// SARXQ r64 r64 r64 -// SARXQ r64 m64 r64 -func SARXQ(r, mr, r1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(r) && operand.IsR64(mr) && operand.IsR64(r1): - return &intrep.Instruction{ - Opcode: "SARXQ", - Operands: []operand.Op{r, mr, r1}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI2"}, - }, nil - case operand.IsR64(r) && operand.IsM64(mr) && operand.IsR64(r1): - return &intrep.Instruction{ - Opcode: "SARXQ", - Operands: []operand.Op{r, mr, r1}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI2"}, - }, nil - } - return nil, errors.New("SARXQ: bad operands") +// VPSLLVW m128 xmm k xmm +// VPSLLVW m128 xmm xmm +// VPSLLVW m256 ymm k ymm +// VPSLLVW m256 ymm ymm +// VPSLLVW xmm xmm k xmm +// VPSLLVW xmm xmm xmm +// VPSLLVW ymm ymm k ymm +// VPSLLVW ymm ymm ymm +// VPSLLVW m512 zmm k zmm +// VPSLLVW m512 zmm zmm +// VPSLLVW zmm zmm k zmm +// VPSLLVW zmm zmm zmm +func VPSLLVW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSLLVW.Forms(), sffxs{}, ops) } -// SBBB: Subtract with Borrow. +// VPSLLVW_Z: Variable Shift Packed Word Data Left Logical (Zeroing Masking). // // Forms: // -// SBBB imm8 al -// SBBB imm8 r8 -// SBBB r8 r8 -// SBBB m8 r8 -// SBBB imm8 m8 -// SBBB r8 m8 -func SBBB(imr, amr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(imr) && operand.IsAL(amr): - return &intrep.Instruction{ - Opcode: "SBBB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM8(imr) && operand.IsR8(amr): - return &intrep.Instruction{ - Opcode: "SBBB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsR8(imr) && operand.IsR8(amr): - return &intrep.Instruction{ - Opcode: "SBBB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - CancellingInputs: true, - }, nil - case operand.IsM8(imr) && operand.IsR8(amr): - return &intrep.Instruction{ - Opcode: "SBBB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM8(imr) && operand.IsM8(amr): - return &intrep.Instruction{ - Opcode: "SBBB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsR8(imr) && operand.IsM8(amr): - return &intrep.Instruction{ - Opcode: "SBBB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - } - return nil, errors.New("SBBB: bad operands") +// VPSLLVW.Z m128 xmm k xmm +// VPSLLVW.Z m256 ymm k ymm +// VPSLLVW.Z xmm xmm k xmm +// VPSLLVW.Z ymm ymm k ymm +// VPSLLVW.Z m512 zmm k zmm +// VPSLLVW.Z zmm zmm k zmm +func VPSLLVW_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPSLLVW.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// SBBL: Subtract with Borrow. +// VPSLLW: Shift Packed Word Data Left Logical. // // Forms: // -// SBBL imm32 eax -// SBBL imm8 r32 -// SBBL imm32 r32 -// SBBL r32 r32 -// SBBL m32 r32 -// SBBL imm8 m32 -// SBBL imm32 m32 -// SBBL r32 m32 -func SBBL(imr, emr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM32(imr) && operand.IsEAX(emr): - return &intrep.Instruction{ - Opcode: "SBBL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsIMM8(imr) && operand.IsR32(emr): - return &intrep.Instruction{ - Opcode: "SBBL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsIMM32(imr) && operand.IsR32(emr): - return &intrep.Instruction{ - Opcode: "SBBL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsR32(imr) && operand.IsR32(emr): - return &intrep.Instruction{ - Opcode: "SBBL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{imr, emr}, - Outputs: []operand.Op{emr}, - CancellingInputs: true, - }, nil - case operand.IsM32(imr) && operand.IsR32(emr): - return &intrep.Instruction{ - Opcode: "SBBL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{imr, emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsIMM8(imr) && operand.IsM32(emr): - return &intrep.Instruction{ - Opcode: "SBBL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsIMM32(imr) && operand.IsM32(emr): - return &intrep.Instruction{ - Opcode: "SBBL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsR32(imr) && operand.IsM32(emr): - return &intrep.Instruction{ - Opcode: "SBBL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{imr, emr}, - Outputs: []operand.Op{emr}, - }, nil - } - return nil, errors.New("SBBL: bad operands") +// VPSLLW imm8 ymm ymm +// VPSLLW m128 ymm ymm +// VPSLLW xmm ymm ymm +// VPSLLW imm8 xmm xmm +// VPSLLW m128 xmm xmm +// VPSLLW xmm xmm xmm +// VPSLLW imm8 m128 k xmm +// VPSLLW imm8 m128 xmm +// VPSLLW imm8 m256 k ymm +// VPSLLW imm8 m256 ymm +// VPSLLW imm8 xmm k xmm +// VPSLLW imm8 ymm k ymm +// VPSLLW m128 xmm k xmm +// VPSLLW m128 ymm k ymm +// VPSLLW xmm xmm k xmm +// VPSLLW xmm ymm k ymm +// VPSLLW imm8 m512 k zmm +// VPSLLW imm8 m512 zmm +// VPSLLW imm8 zmm k zmm +// VPSLLW imm8 zmm zmm +// VPSLLW m128 zmm k zmm +// VPSLLW m128 zmm zmm +// VPSLLW xmm zmm k zmm +// VPSLLW xmm zmm zmm +func VPSLLW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSLLW.Forms(), sffxs{}, ops) +} + +// VPSLLW_Z: Shift Packed Word Data Left Logical (Zeroing Masking). +// +// Forms: +// +// VPSLLW.Z imm8 m128 k xmm +// VPSLLW.Z imm8 m256 k ymm +// VPSLLW.Z imm8 xmm k xmm +// VPSLLW.Z imm8 ymm k ymm +// VPSLLW.Z m128 xmm k xmm +// VPSLLW.Z m128 ymm k ymm +// VPSLLW.Z xmm xmm k xmm +// VPSLLW.Z xmm ymm k ymm +// VPSLLW.Z imm8 m512 k zmm +// VPSLLW.Z imm8 zmm k zmm +// VPSLLW.Z m128 zmm k zmm +// VPSLLW.Z xmm zmm k zmm +func VPSLLW_Z(imx, mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPSLLW.Forms(), sffxs{sffxZ}, []operand.Op{imx, mxyz, k, xyz}) } -// SBBQ: Subtract with Borrow. +// VPSRAD: Shift Packed Doubleword Data Right Arithmetic. // // Forms: // -// SBBQ imm32 rax -// SBBQ imm8 r64 -// SBBQ imm32 r64 -// SBBQ r64 r64 -// SBBQ m64 r64 -// SBBQ imm8 m64 -// SBBQ imm32 m64 -// SBBQ r64 m64 -func SBBQ(imr, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM32(imr) && operand.IsRAX(mr): - return &intrep.Instruction{ - Opcode: "SBBQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(imr) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "SBBQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM32(imr) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "SBBQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR64(imr) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "SBBQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{imr, mr}, - Outputs: []operand.Op{mr}, - CancellingInputs: true, - }, nil - case operand.IsM64(imr) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "SBBQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{imr, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(imr) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "SBBQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM32(imr) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "SBBQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR64(imr) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "SBBQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{imr, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("SBBQ: bad operands") +// VPSRAD imm8 ymm ymm +// VPSRAD m128 ymm ymm +// VPSRAD xmm ymm ymm +// VPSRAD imm8 xmm xmm +// VPSRAD m128 xmm xmm +// VPSRAD xmm xmm xmm +// VPSRAD imm8 m128 k xmm +// VPSRAD imm8 m128 xmm +// VPSRAD imm8 m256 k ymm +// VPSRAD imm8 m256 ymm +// VPSRAD imm8 xmm k xmm +// VPSRAD imm8 ymm k ymm +// VPSRAD m128 xmm k xmm +// VPSRAD m128 ymm k ymm +// VPSRAD xmm xmm k xmm +// VPSRAD xmm ymm k ymm +// VPSRAD imm8 m512 k zmm +// VPSRAD imm8 m512 zmm +// VPSRAD imm8 zmm k zmm +// VPSRAD imm8 zmm zmm +// VPSRAD m128 zmm k zmm +// VPSRAD m128 zmm zmm +// VPSRAD xmm zmm k zmm +// VPSRAD xmm zmm zmm +func VPSRAD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRAD.Forms(), sffxs{}, ops) } -// SBBW: Subtract with Borrow. +// VPSRAD_BCST: Shift Packed Doubleword Data Right Arithmetic (Broadcast). // // Forms: // -// SBBW imm16 ax -// SBBW imm8 r16 -// SBBW imm16 r16 -// SBBW r16 r16 -// SBBW m16 r16 -// SBBW imm8 m16 -// SBBW imm16 m16 -// SBBW r16 m16 -func SBBW(imr, amr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM16(imr) && operand.IsAX(amr): - return &intrep.Instruction{ - Opcode: "SBBW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM8(imr) && operand.IsR16(amr): - return &intrep.Instruction{ - Opcode: "SBBW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM16(imr) && operand.IsR16(amr): - return &intrep.Instruction{ - Opcode: "SBBW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsR16(imr) && operand.IsR16(amr): - return &intrep.Instruction{ - Opcode: "SBBW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - CancellingInputs: true, - }, nil - case operand.IsM16(imr) && operand.IsR16(amr): - return &intrep.Instruction{ - Opcode: "SBBW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM8(imr) && operand.IsM16(amr): - return &intrep.Instruction{ - Opcode: "SBBW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM16(imr) && operand.IsM16(amr): - return &intrep.Instruction{ - Opcode: "SBBW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsR16(imr) && operand.IsM16(amr): - return &intrep.Instruction{ - Opcode: "SBBW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - } - return nil, errors.New("SBBW: bad operands") +// VPSRAD.BCST imm8 m32 k xmm +// VPSRAD.BCST imm8 m32 k ymm +// VPSRAD.BCST imm8 m32 xmm +// VPSRAD.BCST imm8 m32 ymm +// VPSRAD.BCST imm8 m32 k zmm +// VPSRAD.BCST imm8 m32 zmm +func VPSRAD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRAD.Forms(), sffxs{sffxBCST}, ops) } -// SETCC: Set byte if above or equal (CF == 0). +// VPSRAD_BCST_Z: Shift Packed Doubleword Data Right Arithmetic (Broadcast, Zeroing Masking). // // Forms: // -// SETCC r8 -// SETCC m8 -func SETCC(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "SETCC", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "SETCC", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("SETCC: bad operands") +// VPSRAD.BCST.Z imm8 m32 k xmm +// VPSRAD.BCST.Z imm8 m32 k ymm +// VPSRAD.BCST.Z imm8 m32 k zmm +func VPSRAD_BCST_Z(i, m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRAD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{i, m, k, xyz}) } -// SETCS: Set byte if below (CF == 1). +// VPSRAD_Z: Shift Packed Doubleword Data Right Arithmetic (Zeroing Masking). // // Forms: // -// SETCS r8 -// SETCS m8 -func SETCS(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "SETCS", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "SETCS", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("SETCS: bad operands") +// VPSRAD.Z imm8 m128 k xmm +// VPSRAD.Z imm8 m256 k ymm +// VPSRAD.Z imm8 xmm k xmm +// VPSRAD.Z imm8 ymm k ymm +// VPSRAD.Z m128 xmm k xmm +// VPSRAD.Z m128 ymm k ymm +// VPSRAD.Z xmm xmm k xmm +// VPSRAD.Z xmm ymm k ymm +// VPSRAD.Z imm8 m512 k zmm +// VPSRAD.Z imm8 zmm k zmm +// VPSRAD.Z m128 zmm k zmm +// VPSRAD.Z xmm zmm k zmm +func VPSRAD_Z(imx, mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRAD.Forms(), sffxs{sffxZ}, []operand.Op{imx, mxyz, k, xyz}) } -// SETEQ: Set byte if equal (ZF == 1). +// VPSRAQ: Shift Packed Quadword Data Right Arithmetic. // // Forms: // -// SETEQ r8 -// SETEQ m8 -func SETEQ(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "SETEQ", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "SETEQ", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("SETEQ: bad operands") +// VPSRAQ imm8 m128 k xmm +// VPSRAQ imm8 m128 xmm +// VPSRAQ imm8 m256 k ymm +// VPSRAQ imm8 m256 ymm +// VPSRAQ imm8 xmm k xmm +// VPSRAQ imm8 xmm xmm +// VPSRAQ imm8 ymm k ymm +// VPSRAQ imm8 ymm ymm +// VPSRAQ m128 xmm k xmm +// VPSRAQ m128 xmm xmm +// VPSRAQ m128 ymm k ymm +// VPSRAQ m128 ymm ymm +// VPSRAQ xmm xmm k xmm +// VPSRAQ xmm xmm xmm +// VPSRAQ xmm ymm k ymm +// VPSRAQ xmm ymm ymm +// VPSRAQ imm8 m512 k zmm +// VPSRAQ imm8 m512 zmm +// VPSRAQ imm8 zmm k zmm +// VPSRAQ imm8 zmm zmm +// VPSRAQ m128 zmm k zmm +// VPSRAQ m128 zmm zmm +// VPSRAQ xmm zmm k zmm +// VPSRAQ xmm zmm zmm +func VPSRAQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRAQ.Forms(), sffxs{}, ops) } -// SETGE: Set byte if greater or equal (SF == OF). +// VPSRAQ_BCST: Shift Packed Quadword Data Right Arithmetic (Broadcast). // // Forms: // -// SETGE r8 -// SETGE m8 -func SETGE(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "SETGE", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "SETGE", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("SETGE: bad operands") +// VPSRAQ.BCST imm8 m64 k xmm +// VPSRAQ.BCST imm8 m64 k ymm +// VPSRAQ.BCST imm8 m64 xmm +// VPSRAQ.BCST imm8 m64 ymm +// VPSRAQ.BCST imm8 m64 k zmm +// VPSRAQ.BCST imm8 m64 zmm +func VPSRAQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRAQ.Forms(), sffxs{sffxBCST}, ops) } -// SETGT: Set byte if greater (ZF == 0 and SF == OF). +// VPSRAQ_BCST_Z: Shift Packed Quadword Data Right Arithmetic (Broadcast, Zeroing Masking). // // Forms: // -// SETGT r8 -// SETGT m8 -func SETGT(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "SETGT", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "SETGT", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("SETGT: bad operands") +// VPSRAQ.BCST.Z imm8 m64 k xmm +// VPSRAQ.BCST.Z imm8 m64 k ymm +// VPSRAQ.BCST.Z imm8 m64 k zmm +func VPSRAQ_BCST_Z(i, m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRAQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{i, m, k, xyz}) } -// SETHI: Set byte if above (CF == 0 and ZF == 0). +// VPSRAQ_Z: Shift Packed Quadword Data Right Arithmetic (Zeroing Masking). // // Forms: // -// SETHI r8 -// SETHI m8 -func SETHI(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "SETHI", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "SETHI", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("SETHI: bad operands") +// VPSRAQ.Z imm8 m128 k xmm +// VPSRAQ.Z imm8 m256 k ymm +// VPSRAQ.Z imm8 xmm k xmm +// VPSRAQ.Z imm8 ymm k ymm +// VPSRAQ.Z m128 xmm k xmm +// VPSRAQ.Z m128 ymm k ymm +// VPSRAQ.Z xmm xmm k xmm +// VPSRAQ.Z xmm ymm k ymm +// VPSRAQ.Z imm8 m512 k zmm +// VPSRAQ.Z imm8 zmm k zmm +// VPSRAQ.Z m128 zmm k zmm +// VPSRAQ.Z xmm zmm k zmm +func VPSRAQ_Z(imx, mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRAQ.Forms(), sffxs{sffxZ}, []operand.Op{imx, mxyz, k, xyz}) } -// SETLE: Set byte if less or equal (ZF == 1 or SF != OF). +// VPSRAVD: Variable Shift Packed Doubleword Data Right Arithmetic. // // Forms: // -// SETLE r8 -// SETLE m8 -func SETLE(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "SETLE", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "SETLE", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("SETLE: bad operands") +// VPSRAVD m128 xmm xmm +// VPSRAVD m256 ymm ymm +// VPSRAVD xmm xmm xmm +// VPSRAVD ymm ymm ymm +// VPSRAVD m128 xmm k xmm +// VPSRAVD m256 ymm k ymm +// VPSRAVD xmm xmm k xmm +// VPSRAVD ymm ymm k ymm +// VPSRAVD m512 zmm k zmm +// VPSRAVD m512 zmm zmm +// VPSRAVD zmm zmm k zmm +// VPSRAVD zmm zmm zmm +func VPSRAVD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRAVD.Forms(), sffxs{}, ops) } -// SETLS: Set byte if below or equal (CF == 1 or ZF == 1). +// VPSRAVD_BCST: Variable Shift Packed Doubleword Data Right Arithmetic (Broadcast). // // Forms: // -// SETLS r8 -// SETLS m8 -func SETLS(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "SETLS", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "SETLS", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("SETLS: bad operands") +// VPSRAVD.BCST m32 xmm k xmm +// VPSRAVD.BCST m32 xmm xmm +// VPSRAVD.BCST m32 ymm k ymm +// VPSRAVD.BCST m32 ymm ymm +// VPSRAVD.BCST m32 zmm k zmm +// VPSRAVD.BCST m32 zmm zmm +func VPSRAVD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRAVD.Forms(), sffxs{sffxBCST}, ops) } -// SETLT: Set byte if less (SF != OF). +// VPSRAVD_BCST_Z: Variable Shift Packed Doubleword Data Right Arithmetic (Broadcast, Zeroing Masking). // // Forms: // -// SETLT r8 -// SETLT m8 -func SETLT(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "SETLT", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "SETLT", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("SETLT: bad operands") +// VPSRAVD.BCST.Z m32 xmm k xmm +// VPSRAVD.BCST.Z m32 ymm k ymm +// VPSRAVD.BCST.Z m32 zmm k zmm +func VPSRAVD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRAVD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// SETMI: Set byte if sign (SF == 1). +// VPSRAVD_Z: Variable Shift Packed Doubleword Data Right Arithmetic (Zeroing Masking). // // Forms: // -// SETMI r8 -// SETMI m8 -func SETMI(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "SETMI", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "SETMI", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("SETMI: bad operands") +// VPSRAVD.Z m128 xmm k xmm +// VPSRAVD.Z m256 ymm k ymm +// VPSRAVD.Z xmm xmm k xmm +// VPSRAVD.Z ymm ymm k ymm +// VPSRAVD.Z m512 zmm k zmm +// VPSRAVD.Z zmm zmm k zmm +func VPSRAVD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRAVD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// SETNE: Set byte if not equal (ZF == 0). +// VPSRAVQ: Variable Shift Packed Quadword Data Right Arithmetic. // // Forms: // -// SETNE r8 -// SETNE m8 -func SETNE(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "SETNE", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "SETNE", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("SETNE: bad operands") +// VPSRAVQ m128 xmm k xmm +// VPSRAVQ m128 xmm xmm +// VPSRAVQ m256 ymm k ymm +// VPSRAVQ m256 ymm ymm +// VPSRAVQ xmm xmm k xmm +// VPSRAVQ xmm xmm xmm +// VPSRAVQ ymm ymm k ymm +// VPSRAVQ ymm ymm ymm +// VPSRAVQ m512 zmm k zmm +// VPSRAVQ m512 zmm zmm +// VPSRAVQ zmm zmm k zmm +// VPSRAVQ zmm zmm zmm +func VPSRAVQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRAVQ.Forms(), sffxs{}, ops) } -// SETOC: Set byte if not overflow (OF == 0). +// VPSRAVQ_BCST: Variable Shift Packed Quadword Data Right Arithmetic (Broadcast). // // Forms: // -// SETOC r8 -// SETOC m8 -func SETOC(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "SETOC", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "SETOC", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("SETOC: bad operands") +// VPSRAVQ.BCST m64 xmm k xmm +// VPSRAVQ.BCST m64 xmm xmm +// VPSRAVQ.BCST m64 ymm k ymm +// VPSRAVQ.BCST m64 ymm ymm +// VPSRAVQ.BCST m64 zmm k zmm +// VPSRAVQ.BCST m64 zmm zmm +func VPSRAVQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRAVQ.Forms(), sffxs{sffxBCST}, ops) } -// SETOS: Set byte if overflow (OF == 1). +// VPSRAVQ_BCST_Z: Variable Shift Packed Quadword Data Right Arithmetic (Broadcast, Zeroing Masking). // // Forms: // -// SETOS r8 -// SETOS m8 -func SETOS(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "SETOS", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "SETOS", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("SETOS: bad operands") +// VPSRAVQ.BCST.Z m64 xmm k xmm +// VPSRAVQ.BCST.Z m64 ymm k ymm +// VPSRAVQ.BCST.Z m64 zmm k zmm +func VPSRAVQ_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRAVQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// SETPC: Set byte if not parity (PF == 0). +// VPSRAVQ_Z: Variable Shift Packed Quadword Data Right Arithmetic (Zeroing Masking). // // Forms: // -// SETPC r8 -// SETPC m8 -func SETPC(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "SETPC", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "SETPC", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("SETPC: bad operands") +// VPSRAVQ.Z m128 xmm k xmm +// VPSRAVQ.Z m256 ymm k ymm +// VPSRAVQ.Z xmm xmm k xmm +// VPSRAVQ.Z ymm ymm k ymm +// VPSRAVQ.Z m512 zmm k zmm +// VPSRAVQ.Z zmm zmm k zmm +func VPSRAVQ_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRAVQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// SETPL: Set byte if not sign (SF == 0). +// VPSRAVW: Variable Shift Packed Word Data Right Arithmetic. // // Forms: // -// SETPL r8 -// SETPL m8 -func SETPL(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "SETPL", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "SETPL", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("SETPL: bad operands") +// VPSRAVW m128 xmm k xmm +// VPSRAVW m128 xmm xmm +// VPSRAVW m256 ymm k ymm +// VPSRAVW m256 ymm ymm +// VPSRAVW xmm xmm k xmm +// VPSRAVW xmm xmm xmm +// VPSRAVW ymm ymm k ymm +// VPSRAVW ymm ymm ymm +// VPSRAVW m512 zmm k zmm +// VPSRAVW m512 zmm zmm +// VPSRAVW zmm zmm k zmm +// VPSRAVW zmm zmm zmm +func VPSRAVW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRAVW.Forms(), sffxs{}, ops) } -// SETPS: Set byte if parity (PF == 1). +// VPSRAVW_Z: Variable Shift Packed Word Data Right Arithmetic (Zeroing Masking). // // Forms: // -// SETPS r8 -// SETPS m8 -func SETPS(mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "SETPS", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "SETPS", - Operands: []operand.Op{mr}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("SETPS: bad operands") +// VPSRAVW.Z m128 xmm k xmm +// VPSRAVW.Z m256 ymm k ymm +// VPSRAVW.Z xmm xmm k xmm +// VPSRAVW.Z ymm ymm k ymm +// VPSRAVW.Z m512 zmm k zmm +// VPSRAVW.Z zmm zmm k zmm +func VPSRAVW_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRAVW.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// SFENCE: Store Fence. +// VPSRAW: Shift Packed Word Data Right Arithmetic. // // Forms: // -// SFENCE -func SFENCE() (*intrep.Instruction, error) { - return &intrep.Instruction{ - Opcode: "SFENCE", - Operands: nil, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - ISA: []string{"MMX+"}, - }, nil +// VPSRAW imm8 ymm ymm +// VPSRAW m128 ymm ymm +// VPSRAW xmm ymm ymm +// VPSRAW imm8 xmm xmm +// VPSRAW m128 xmm xmm +// VPSRAW xmm xmm xmm +// VPSRAW imm8 m128 k xmm +// VPSRAW imm8 m128 xmm +// VPSRAW imm8 m256 k ymm +// VPSRAW imm8 m256 ymm +// VPSRAW imm8 xmm k xmm +// VPSRAW imm8 ymm k ymm +// VPSRAW m128 xmm k xmm +// VPSRAW m128 ymm k ymm +// VPSRAW xmm xmm k xmm +// VPSRAW xmm ymm k ymm +// VPSRAW imm8 m512 k zmm +// VPSRAW imm8 m512 zmm +// VPSRAW imm8 zmm k zmm +// VPSRAW imm8 zmm zmm +// VPSRAW m128 zmm k zmm +// VPSRAW m128 zmm zmm +// VPSRAW xmm zmm k zmm +// VPSRAW xmm zmm zmm +func VPSRAW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRAW.Forms(), sffxs{}, ops) +} + +// VPSRAW_Z: Shift Packed Word Data Right Arithmetic (Zeroing Masking). +// +// Forms: +// +// VPSRAW.Z imm8 m128 k xmm +// VPSRAW.Z imm8 m256 k ymm +// VPSRAW.Z imm8 xmm k xmm +// VPSRAW.Z imm8 ymm k ymm +// VPSRAW.Z m128 xmm k xmm +// VPSRAW.Z m128 ymm k ymm +// VPSRAW.Z xmm xmm k xmm +// VPSRAW.Z xmm ymm k ymm +// VPSRAW.Z imm8 m512 k zmm +// VPSRAW.Z imm8 zmm k zmm +// VPSRAW.Z m128 zmm k zmm +// VPSRAW.Z xmm zmm k zmm +func VPSRAW_Z(imx, mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRAW.Forms(), sffxs{sffxZ}, []operand.Op{imx, mxyz, k, xyz}) } -// SHA1MSG1: Perform an Intermediate Calculation for the Next Four SHA1 Message Doublewords. +// VPSRLD: Shift Packed Doubleword Data Right Logical. // // Forms: // -// SHA1MSG1 xmm xmm -// SHA1MSG1 m128 xmm -func SHA1MSG1(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SHA1MSG1", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SHA"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SHA1MSG1", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SHA"}, - }, nil - } - return nil, errors.New("SHA1MSG1: bad operands") +// VPSRLD imm8 ymm ymm +// VPSRLD m128 ymm ymm +// VPSRLD xmm ymm ymm +// VPSRLD imm8 xmm xmm +// VPSRLD m128 xmm xmm +// VPSRLD xmm xmm xmm +// VPSRLD imm8 m128 k xmm +// VPSRLD imm8 m128 xmm +// VPSRLD imm8 m256 k ymm +// VPSRLD imm8 m256 ymm +// VPSRLD imm8 xmm k xmm +// VPSRLD imm8 ymm k ymm +// VPSRLD m128 xmm k xmm +// VPSRLD m128 ymm k ymm +// VPSRLD xmm xmm k xmm +// VPSRLD xmm ymm k ymm +// VPSRLD imm8 m512 k zmm +// VPSRLD imm8 m512 zmm +// VPSRLD imm8 zmm k zmm +// VPSRLD imm8 zmm zmm +// VPSRLD m128 zmm k zmm +// VPSRLD m128 zmm zmm +// VPSRLD xmm zmm k zmm +// VPSRLD xmm zmm zmm +func VPSRLD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRLD.Forms(), sffxs{}, ops) } -// SHA1MSG2: Perform a Final Calculation for the Next Four SHA1 Message Doublewords. +// VPSRLDQ: Shift Packed Double Quadword Right Logical. // // Forms: // -// SHA1MSG2 xmm xmm -// SHA1MSG2 m128 xmm -func SHA1MSG2(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SHA1MSG2", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SHA"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SHA1MSG2", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SHA"}, - }, nil - } - return nil, errors.New("SHA1MSG2: bad operands") +// VPSRLDQ imm8 ymm ymm +// VPSRLDQ imm8 xmm xmm +// VPSRLDQ imm8 m128 xmm +// VPSRLDQ imm8 m256 ymm +// VPSRLDQ imm8 m512 zmm +// VPSRLDQ imm8 zmm zmm +func VPSRLDQ(i, mxyz, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRLDQ.Forms(), sffxs{}, []operand.Op{i, mxyz, xyz}) } -// SHA1NEXTE: Calculate SHA1 State Variable E after Four Rounds. +// VPSRLD_BCST: Shift Packed Doubleword Data Right Logical (Broadcast). // // Forms: // -// SHA1NEXTE xmm xmm -// SHA1NEXTE m128 xmm -func SHA1NEXTE(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SHA1NEXTE", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SHA"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SHA1NEXTE", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SHA"}, - }, nil - } - return nil, errors.New("SHA1NEXTE: bad operands") +// VPSRLD.BCST imm8 m32 k xmm +// VPSRLD.BCST imm8 m32 k ymm +// VPSRLD.BCST imm8 m32 xmm +// VPSRLD.BCST imm8 m32 ymm +// VPSRLD.BCST imm8 m32 k zmm +// VPSRLD.BCST imm8 m32 zmm +func VPSRLD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRLD.Forms(), sffxs{sffxBCST}, ops) } -// SHA1RNDS4: Perform Four Rounds of SHA1 Operation. +// VPSRLD_BCST_Z: Shift Packed Doubleword Data Right Logical (Broadcast, Zeroing Masking). // // Forms: // -// SHA1RNDS4 imm2u xmm xmm -// SHA1RNDS4 imm2u m128 xmm -func SHA1RNDS4(i, mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM2U(i) && operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SHA1RNDS4", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SHA"}, - }, nil - case operand.IsIMM2U(i) && operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SHA1RNDS4", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SHA"}, - }, nil - } - return nil, errors.New("SHA1RNDS4: bad operands") +// VPSRLD.BCST.Z imm8 m32 k xmm +// VPSRLD.BCST.Z imm8 m32 k ymm +// VPSRLD.BCST.Z imm8 m32 k zmm +func VPSRLD_BCST_Z(i, m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRLD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{i, m, k, xyz}) } -// SHA256MSG1: Perform an Intermediate Calculation for the Next Four SHA256 Message Doublewords. +// VPSRLD_Z: Shift Packed Doubleword Data Right Logical (Zeroing Masking). // // Forms: // -// SHA256MSG1 xmm xmm -// SHA256MSG1 m128 xmm -func SHA256MSG1(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SHA256MSG1", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SHA"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SHA256MSG1", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SHA"}, - }, nil - } - return nil, errors.New("SHA256MSG1: bad operands") +// VPSRLD.Z imm8 m128 k xmm +// VPSRLD.Z imm8 m256 k ymm +// VPSRLD.Z imm8 xmm k xmm +// VPSRLD.Z imm8 ymm k ymm +// VPSRLD.Z m128 xmm k xmm +// VPSRLD.Z m128 ymm k ymm +// VPSRLD.Z xmm xmm k xmm +// VPSRLD.Z xmm ymm k ymm +// VPSRLD.Z imm8 m512 k zmm +// VPSRLD.Z imm8 zmm k zmm +// VPSRLD.Z m128 zmm k zmm +// VPSRLD.Z xmm zmm k zmm +func VPSRLD_Z(imx, mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRLD.Forms(), sffxs{sffxZ}, []operand.Op{imx, mxyz, k, xyz}) } -// SHA256MSG2: Perform a Final Calculation for the Next Four SHA256 Message Doublewords. +// VPSRLQ: Shift Packed Quadword Data Right Logical. // // Forms: // -// SHA256MSG2 xmm xmm -// SHA256MSG2 m128 xmm -func SHA256MSG2(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SHA256MSG2", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SHA"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SHA256MSG2", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SHA"}, - }, nil - } - return nil, errors.New("SHA256MSG2: bad operands") +// VPSRLQ imm8 ymm ymm +// VPSRLQ m128 ymm ymm +// VPSRLQ xmm ymm ymm +// VPSRLQ imm8 xmm xmm +// VPSRLQ m128 xmm xmm +// VPSRLQ xmm xmm xmm +// VPSRLQ imm8 m128 k xmm +// VPSRLQ imm8 m128 xmm +// VPSRLQ imm8 m256 k ymm +// VPSRLQ imm8 m256 ymm +// VPSRLQ imm8 xmm k xmm +// VPSRLQ imm8 ymm k ymm +// VPSRLQ m128 xmm k xmm +// VPSRLQ m128 ymm k ymm +// VPSRLQ xmm xmm k xmm +// VPSRLQ xmm ymm k ymm +// VPSRLQ imm8 m512 k zmm +// VPSRLQ imm8 m512 zmm +// VPSRLQ imm8 zmm k zmm +// VPSRLQ imm8 zmm zmm +// VPSRLQ m128 zmm k zmm +// VPSRLQ m128 zmm zmm +// VPSRLQ xmm zmm k zmm +// VPSRLQ xmm zmm zmm +func VPSRLQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRLQ.Forms(), sffxs{}, ops) } -// SHA256RNDS2: Perform Two Rounds of SHA256 Operation. +// VPSRLQ_BCST: Shift Packed Quadword Data Right Logical (Broadcast). // // Forms: // -// SHA256RNDS2 xmm0 xmm xmm -// SHA256RNDS2 xmm0 m128 xmm -func SHA256RNDS2(x, mx, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM0(x) && operand.IsXMM(mx) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "SHA256RNDS2", - Operands: []operand.Op{x, mx, x1}, - Inputs: []operand.Op{x, mx, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"SHA"}, - }, nil - case operand.IsXMM0(x) && operand.IsM128(mx) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "SHA256RNDS2", - Operands: []operand.Op{x, mx, x1}, - Inputs: []operand.Op{x, mx, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"SHA"}, - }, nil - } - return nil, errors.New("SHA256RNDS2: bad operands") +// VPSRLQ.BCST imm8 m64 k xmm +// VPSRLQ.BCST imm8 m64 k ymm +// VPSRLQ.BCST imm8 m64 xmm +// VPSRLQ.BCST imm8 m64 ymm +// VPSRLQ.BCST imm8 m64 k zmm +// VPSRLQ.BCST imm8 m64 zmm +func VPSRLQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRLQ.Forms(), sffxs{sffxBCST}, ops) } -// SHLB: Logical Shift Left. +// VPSRLQ_BCST_Z: Shift Packed Quadword Data Right Logical (Broadcast, Zeroing Masking). // // Forms: // -// SHLB 1 r8 -// SHLB imm8 r8 -// SHLB cl r8 -// SHLB 1 m8 -// SHLB imm8 m8 -// SHLB cl m8 -func SHLB(ci, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.Is1(ci) && operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "SHLB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "SHLB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "SHLB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.Is1(ci) && operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "SHLB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "SHLB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "SHLB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("SHLB: bad operands") +// VPSRLQ.BCST.Z imm8 m64 k xmm +// VPSRLQ.BCST.Z imm8 m64 k ymm +// VPSRLQ.BCST.Z imm8 m64 k zmm +func VPSRLQ_BCST_Z(i, m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRLQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{i, m, k, xyz}) } -// SHLL: Logical Shift Left. +// VPSRLQ_Z: Shift Packed Quadword Data Right Logical (Zeroing Masking). // // Forms: // -// SHLL 1 r32 -// SHLL imm8 r32 -// SHLL cl r32 -// SHLL 1 m32 -// SHLL imm8 m32 -// SHLL cl m32 -// SHLL imm8 r32 r32 -// SHLL cl r32 r32 -// SHLL imm8 r32 m32 -// SHLL cl r32 m32 -func SHLL(ops ...operand.Op) (*intrep.Instruction, error) { - switch { - case len(ops) == 2 && operand.Is1(ops[0]) && operand.IsR32(ops[1]): - return &intrep.Instruction{ - Opcode: "SHLL", - Operands: ops, - Inputs: []operand.Op{ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.IsIMM8(ops[0]) && operand.IsR32(ops[1]): - return &intrep.Instruction{ - Opcode: "SHLL", - Operands: ops, - Inputs: []operand.Op{ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.IsCL(ops[0]) && operand.IsR32(ops[1]): - return &intrep.Instruction{ - Opcode: "SHLL", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.Is1(ops[0]) && operand.IsM32(ops[1]): - return &intrep.Instruction{ - Opcode: "SHLL", - Operands: ops, - Inputs: []operand.Op{ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.IsIMM8(ops[0]) && operand.IsM32(ops[1]): - return &intrep.Instruction{ - Opcode: "SHLL", - Operands: ops, - Inputs: []operand.Op{ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.IsCL(ops[0]) && operand.IsM32(ops[1]): - return &intrep.Instruction{ - Opcode: "SHLL", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 3 && operand.IsIMM8(ops[0]) && operand.IsR32(ops[1]) && operand.IsR32(ops[2]): - return &intrep.Instruction{ - Opcode: "SHLL", - Operands: ops, - Inputs: []operand.Op{ops[1], ops[2]}, - Outputs: []operand.Op{ops[2]}, - }, nil - case len(ops) == 3 && operand.IsCL(ops[0]) && operand.IsR32(ops[1]) && operand.IsR32(ops[2]): - return &intrep.Instruction{ - Opcode: "SHLL", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1], ops[2]}, - Outputs: []operand.Op{ops[2]}, - }, nil - case len(ops) == 3 && operand.IsIMM8(ops[0]) && operand.IsR32(ops[1]) && operand.IsM32(ops[2]): - return &intrep.Instruction{ - Opcode: "SHLL", - Operands: ops, - Inputs: []operand.Op{ops[1], ops[2]}, - Outputs: []operand.Op{ops[2]}, - }, nil - case len(ops) == 3 && operand.IsCL(ops[0]) && operand.IsR32(ops[1]) && operand.IsM32(ops[2]): - return &intrep.Instruction{ - Opcode: "SHLL", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1], ops[2]}, - Outputs: []operand.Op{ops[2]}, - }, nil - } - return nil, errors.New("SHLL: bad operands") +// VPSRLQ.Z imm8 m128 k xmm +// VPSRLQ.Z imm8 m256 k ymm +// VPSRLQ.Z imm8 xmm k xmm +// VPSRLQ.Z imm8 ymm k ymm +// VPSRLQ.Z m128 xmm k xmm +// VPSRLQ.Z m128 ymm k ymm +// VPSRLQ.Z xmm xmm k xmm +// VPSRLQ.Z xmm ymm k ymm +// VPSRLQ.Z imm8 m512 k zmm +// VPSRLQ.Z imm8 zmm k zmm +// VPSRLQ.Z m128 zmm k zmm +// VPSRLQ.Z xmm zmm k zmm +func VPSRLQ_Z(imx, mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRLQ.Forms(), sffxs{sffxZ}, []operand.Op{imx, mxyz, k, xyz}) } -// SHLQ: Logical Shift Left. +// VPSRLVD: Variable Shift Packed Doubleword Data Right Logical. // // Forms: // -// SHLQ 1 r64 -// SHLQ imm8 r64 -// SHLQ cl r64 -// SHLQ 1 m64 -// SHLQ imm8 m64 -// SHLQ cl m64 -// SHLQ imm8 r64 r64 -// SHLQ cl r64 r64 -// SHLQ imm8 r64 m64 -// SHLQ cl r64 m64 -func SHLQ(ops ...operand.Op) (*intrep.Instruction, error) { - switch { - case len(ops) == 2 && operand.Is1(ops[0]) && operand.IsR64(ops[1]): - return &intrep.Instruction{ - Opcode: "SHLQ", - Operands: ops, - Inputs: []operand.Op{ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.IsIMM8(ops[0]) && operand.IsR64(ops[1]): - return &intrep.Instruction{ - Opcode: "SHLQ", - Operands: ops, - Inputs: []operand.Op{ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.IsCL(ops[0]) && operand.IsR64(ops[1]): - return &intrep.Instruction{ - Opcode: "SHLQ", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.Is1(ops[0]) && operand.IsM64(ops[1]): - return &intrep.Instruction{ - Opcode: "SHLQ", - Operands: ops, - Inputs: []operand.Op{ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.IsIMM8(ops[0]) && operand.IsM64(ops[1]): - return &intrep.Instruction{ - Opcode: "SHLQ", - Operands: ops, - Inputs: []operand.Op{ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.IsCL(ops[0]) && operand.IsM64(ops[1]): - return &intrep.Instruction{ - Opcode: "SHLQ", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 3 && operand.IsIMM8(ops[0]) && operand.IsR64(ops[1]) && operand.IsR64(ops[2]): - return &intrep.Instruction{ - Opcode: "SHLQ", - Operands: ops, - Inputs: []operand.Op{ops[1], ops[2]}, - Outputs: []operand.Op{ops[2]}, - }, nil - case len(ops) == 3 && operand.IsCL(ops[0]) && operand.IsR64(ops[1]) && operand.IsR64(ops[2]): - return &intrep.Instruction{ - Opcode: "SHLQ", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1], ops[2]}, - Outputs: []operand.Op{ops[2]}, - }, nil - case len(ops) == 3 && operand.IsIMM8(ops[0]) && operand.IsR64(ops[1]) && operand.IsM64(ops[2]): - return &intrep.Instruction{ - Opcode: "SHLQ", - Operands: ops, - Inputs: []operand.Op{ops[1], ops[2]}, - Outputs: []operand.Op{ops[2]}, - }, nil - case len(ops) == 3 && operand.IsCL(ops[0]) && operand.IsR64(ops[1]) && operand.IsM64(ops[2]): - return &intrep.Instruction{ - Opcode: "SHLQ", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1], ops[2]}, - Outputs: []operand.Op{ops[2]}, - }, nil - } - return nil, errors.New("SHLQ: bad operands") +// VPSRLVD m128 xmm xmm +// VPSRLVD m256 ymm ymm +// VPSRLVD xmm xmm xmm +// VPSRLVD ymm ymm ymm +// VPSRLVD m128 xmm k xmm +// VPSRLVD m256 ymm k ymm +// VPSRLVD xmm xmm k xmm +// VPSRLVD ymm ymm k ymm +// VPSRLVD m512 zmm k zmm +// VPSRLVD m512 zmm zmm +// VPSRLVD zmm zmm k zmm +// VPSRLVD zmm zmm zmm +func VPSRLVD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRLVD.Forms(), sffxs{}, ops) } -// SHLW: Logical Shift Left. +// VPSRLVD_BCST: Variable Shift Packed Doubleword Data Right Logical (Broadcast). // // Forms: // -// SHLW 1 r16 -// SHLW imm8 r16 -// SHLW cl r16 -// SHLW 1 m16 -// SHLW imm8 m16 -// SHLW cl m16 -// SHLW imm8 r16 r16 -// SHLW cl r16 r16 -// SHLW imm8 r16 m16 -// SHLW cl r16 m16 -func SHLW(ops ...operand.Op) (*intrep.Instruction, error) { - switch { - case len(ops) == 2 && operand.Is1(ops[0]) && operand.IsR16(ops[1]): - return &intrep.Instruction{ - Opcode: "SHLW", - Operands: ops, - Inputs: []operand.Op{ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.IsIMM8(ops[0]) && operand.IsR16(ops[1]): - return &intrep.Instruction{ - Opcode: "SHLW", - Operands: ops, - Inputs: []operand.Op{ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.IsCL(ops[0]) && operand.IsR16(ops[1]): - return &intrep.Instruction{ - Opcode: "SHLW", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.Is1(ops[0]) && operand.IsM16(ops[1]): - return &intrep.Instruction{ - Opcode: "SHLW", - Operands: ops, - Inputs: []operand.Op{ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.IsIMM8(ops[0]) && operand.IsM16(ops[1]): - return &intrep.Instruction{ - Opcode: "SHLW", - Operands: ops, - Inputs: []operand.Op{ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.IsCL(ops[0]) && operand.IsM16(ops[1]): - return &intrep.Instruction{ - Opcode: "SHLW", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 3 && operand.IsIMM8(ops[0]) && operand.IsR16(ops[1]) && operand.IsR16(ops[2]): - return &intrep.Instruction{ - Opcode: "SHLW", - Operands: ops, - Inputs: []operand.Op{ops[1], ops[2]}, - Outputs: []operand.Op{ops[2]}, - }, nil - case len(ops) == 3 && operand.IsCL(ops[0]) && operand.IsR16(ops[1]) && operand.IsR16(ops[2]): - return &intrep.Instruction{ - Opcode: "SHLW", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1], ops[2]}, - Outputs: []operand.Op{ops[2]}, - }, nil - case len(ops) == 3 && operand.IsIMM8(ops[0]) && operand.IsR16(ops[1]) && operand.IsM16(ops[2]): - return &intrep.Instruction{ - Opcode: "SHLW", - Operands: ops, - Inputs: []operand.Op{ops[1], ops[2]}, - Outputs: []operand.Op{ops[2]}, - }, nil - case len(ops) == 3 && operand.IsCL(ops[0]) && operand.IsR16(ops[1]) && operand.IsM16(ops[2]): - return &intrep.Instruction{ - Opcode: "SHLW", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1], ops[2]}, - Outputs: []operand.Op{ops[2]}, - }, nil - } - return nil, errors.New("SHLW: bad operands") +// VPSRLVD.BCST m32 xmm k xmm +// VPSRLVD.BCST m32 xmm xmm +// VPSRLVD.BCST m32 ymm k ymm +// VPSRLVD.BCST m32 ymm ymm +// VPSRLVD.BCST m32 zmm k zmm +// VPSRLVD.BCST m32 zmm zmm +func VPSRLVD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRLVD.Forms(), sffxs{sffxBCST}, ops) } -// SHLXL: Logical Shift Left Without Affecting Flags. +// VPSRLVD_BCST_Z: Variable Shift Packed Doubleword Data Right Logical (Broadcast, Zeroing Masking). // // Forms: // -// SHLXL r32 r32 r32 -// SHLXL r32 m32 r32 -func SHLXL(r, mr, r1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(r) && operand.IsR32(mr) && operand.IsR32(r1): - return &intrep.Instruction{ - Opcode: "SHLXL", - Operands: []operand.Op{r, mr, r1}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI2"}, - }, nil - case operand.IsR32(r) && operand.IsM32(mr) && operand.IsR32(r1): - return &intrep.Instruction{ - Opcode: "SHLXL", - Operands: []operand.Op{r, mr, r1}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI2"}, - }, nil - } - return nil, errors.New("SHLXL: bad operands") +// VPSRLVD.BCST.Z m32 xmm k xmm +// VPSRLVD.BCST.Z m32 ymm k ymm +// VPSRLVD.BCST.Z m32 zmm k zmm +func VPSRLVD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRLVD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// SHLXQ: Logical Shift Left Without Affecting Flags. +// VPSRLVD_Z: Variable Shift Packed Doubleword Data Right Logical (Zeroing Masking). // // Forms: // -// SHLXQ r64 r64 r64 -// SHLXQ r64 m64 r64 -func SHLXQ(r, mr, r1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(r) && operand.IsR64(mr) && operand.IsR64(r1): - return &intrep.Instruction{ - Opcode: "SHLXQ", - Operands: []operand.Op{r, mr, r1}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI2"}, - }, nil - case operand.IsR64(r) && operand.IsM64(mr) && operand.IsR64(r1): - return &intrep.Instruction{ - Opcode: "SHLXQ", - Operands: []operand.Op{r, mr, r1}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI2"}, - }, nil - } - return nil, errors.New("SHLXQ: bad operands") +// VPSRLVD.Z m128 xmm k xmm +// VPSRLVD.Z m256 ymm k ymm +// VPSRLVD.Z xmm xmm k xmm +// VPSRLVD.Z ymm ymm k ymm +// VPSRLVD.Z m512 zmm k zmm +// VPSRLVD.Z zmm zmm k zmm +func VPSRLVD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRLVD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// SHRB: Logical Shift Right. +// VPSRLVQ: Variable Shift Packed Quadword Data Right Logical. // // Forms: // -// SHRB 1 r8 -// SHRB imm8 r8 -// SHRB cl r8 -// SHRB 1 m8 -// SHRB imm8 m8 -// SHRB cl m8 -func SHRB(ci, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.Is1(ci) && operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "SHRB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "SHRB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "SHRB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.Is1(ci) && operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "SHRB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(ci) && operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "SHRB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsCL(ci) && operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "SHRB", - Operands: []operand.Op{ci, mr}, - Inputs: []operand.Op{ci, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("SHRB: bad operands") +// VPSRLVQ m128 xmm xmm +// VPSRLVQ m256 ymm ymm +// VPSRLVQ xmm xmm xmm +// VPSRLVQ ymm ymm ymm +// VPSRLVQ m128 xmm k xmm +// VPSRLVQ m256 ymm k ymm +// VPSRLVQ xmm xmm k xmm +// VPSRLVQ ymm ymm k ymm +// VPSRLVQ m512 zmm k zmm +// VPSRLVQ m512 zmm zmm +// VPSRLVQ zmm zmm k zmm +// VPSRLVQ zmm zmm zmm +func VPSRLVQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRLVQ.Forms(), sffxs{}, ops) } -// SHRL: Logical Shift Right. +// VPSRLVQ_BCST: Variable Shift Packed Quadword Data Right Logical (Broadcast). // // Forms: // -// SHRL 1 r32 -// SHRL imm8 r32 -// SHRL cl r32 -// SHRL 1 m32 -// SHRL imm8 m32 -// SHRL cl m32 -// SHRL imm8 r32 r32 -// SHRL cl r32 r32 -// SHRL imm8 r32 m32 -// SHRL cl r32 m32 -func SHRL(ops ...operand.Op) (*intrep.Instruction, error) { - switch { - case len(ops) == 2 && operand.Is1(ops[0]) && operand.IsR32(ops[1]): - return &intrep.Instruction{ - Opcode: "SHRL", - Operands: ops, - Inputs: []operand.Op{ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.IsIMM8(ops[0]) && operand.IsR32(ops[1]): - return &intrep.Instruction{ - Opcode: "SHRL", - Operands: ops, - Inputs: []operand.Op{ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.IsCL(ops[0]) && operand.IsR32(ops[1]): - return &intrep.Instruction{ - Opcode: "SHRL", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.Is1(ops[0]) && operand.IsM32(ops[1]): - return &intrep.Instruction{ - Opcode: "SHRL", - Operands: ops, - Inputs: []operand.Op{ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.IsIMM8(ops[0]) && operand.IsM32(ops[1]): - return &intrep.Instruction{ - Opcode: "SHRL", - Operands: ops, - Inputs: []operand.Op{ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.IsCL(ops[0]) && operand.IsM32(ops[1]): - return &intrep.Instruction{ - Opcode: "SHRL", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 3 && operand.IsIMM8(ops[0]) && operand.IsR32(ops[1]) && operand.IsR32(ops[2]): - return &intrep.Instruction{ - Opcode: "SHRL", - Operands: ops, - Inputs: []operand.Op{ops[1], ops[2]}, - Outputs: []operand.Op{ops[2]}, - }, nil - case len(ops) == 3 && operand.IsCL(ops[0]) && operand.IsR32(ops[1]) && operand.IsR32(ops[2]): - return &intrep.Instruction{ - Opcode: "SHRL", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1], ops[2]}, - Outputs: []operand.Op{ops[2]}, - }, nil - case len(ops) == 3 && operand.IsIMM8(ops[0]) && operand.IsR32(ops[1]) && operand.IsM32(ops[2]): - return &intrep.Instruction{ - Opcode: "SHRL", - Operands: ops, - Inputs: []operand.Op{ops[1], ops[2]}, - Outputs: []operand.Op{ops[2]}, - }, nil - case len(ops) == 3 && operand.IsCL(ops[0]) && operand.IsR32(ops[1]) && operand.IsM32(ops[2]): - return &intrep.Instruction{ - Opcode: "SHRL", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1], ops[2]}, - Outputs: []operand.Op{ops[2]}, - }, nil - } - return nil, errors.New("SHRL: bad operands") +// VPSRLVQ.BCST m64 xmm k xmm +// VPSRLVQ.BCST m64 xmm xmm +// VPSRLVQ.BCST m64 ymm k ymm +// VPSRLVQ.BCST m64 ymm ymm +// VPSRLVQ.BCST m64 zmm k zmm +// VPSRLVQ.BCST m64 zmm zmm +func VPSRLVQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRLVQ.Forms(), sffxs{sffxBCST}, ops) +} + +// VPSRLVQ_BCST_Z: Variable Shift Packed Quadword Data Right Logical (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPSRLVQ.BCST.Z m64 xmm k xmm +// VPSRLVQ.BCST.Z m64 ymm k ymm +// VPSRLVQ.BCST.Z m64 zmm k zmm +func VPSRLVQ_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRLVQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VPSRLVQ_Z: Variable Shift Packed Quadword Data Right Logical (Zeroing Masking). +// +// Forms: +// +// VPSRLVQ.Z m128 xmm k xmm +// VPSRLVQ.Z m256 ymm k ymm +// VPSRLVQ.Z xmm xmm k xmm +// VPSRLVQ.Z ymm ymm k ymm +// VPSRLVQ.Z m512 zmm k zmm +// VPSRLVQ.Z zmm zmm k zmm +func VPSRLVQ_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRLVQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// SHRQ: Logical Shift Right. +// VPSRLVW: Variable Shift Packed Word Data Right Logical. // // Forms: // -// SHRQ 1 r64 -// SHRQ imm8 r64 -// SHRQ cl r64 -// SHRQ 1 m64 -// SHRQ imm8 m64 -// SHRQ cl m64 -// SHRQ imm8 r64 r64 -// SHRQ cl r64 r64 -// SHRQ imm8 r64 m64 -// SHRQ cl r64 m64 -func SHRQ(ops ...operand.Op) (*intrep.Instruction, error) { - switch { - case len(ops) == 2 && operand.Is1(ops[0]) && operand.IsR64(ops[1]): - return &intrep.Instruction{ - Opcode: "SHRQ", - Operands: ops, - Inputs: []operand.Op{ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.IsIMM8(ops[0]) && operand.IsR64(ops[1]): - return &intrep.Instruction{ - Opcode: "SHRQ", - Operands: ops, - Inputs: []operand.Op{ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.IsCL(ops[0]) && operand.IsR64(ops[1]): - return &intrep.Instruction{ - Opcode: "SHRQ", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.Is1(ops[0]) && operand.IsM64(ops[1]): - return &intrep.Instruction{ - Opcode: "SHRQ", - Operands: ops, - Inputs: []operand.Op{ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.IsIMM8(ops[0]) && operand.IsM64(ops[1]): - return &intrep.Instruction{ - Opcode: "SHRQ", - Operands: ops, - Inputs: []operand.Op{ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.IsCL(ops[0]) && operand.IsM64(ops[1]): - return &intrep.Instruction{ - Opcode: "SHRQ", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 3 && operand.IsIMM8(ops[0]) && operand.IsR64(ops[1]) && operand.IsR64(ops[2]): - return &intrep.Instruction{ - Opcode: "SHRQ", - Operands: ops, - Inputs: []operand.Op{ops[1], ops[2]}, - Outputs: []operand.Op{ops[2]}, - }, nil - case len(ops) == 3 && operand.IsCL(ops[0]) && operand.IsR64(ops[1]) && operand.IsR64(ops[2]): - return &intrep.Instruction{ - Opcode: "SHRQ", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1], ops[2]}, - Outputs: []operand.Op{ops[2]}, - }, nil - case len(ops) == 3 && operand.IsIMM8(ops[0]) && operand.IsR64(ops[1]) && operand.IsM64(ops[2]): - return &intrep.Instruction{ - Opcode: "SHRQ", - Operands: ops, - Inputs: []operand.Op{ops[1], ops[2]}, - Outputs: []operand.Op{ops[2]}, - }, nil - case len(ops) == 3 && operand.IsCL(ops[0]) && operand.IsR64(ops[1]) && operand.IsM64(ops[2]): - return &intrep.Instruction{ - Opcode: "SHRQ", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1], ops[2]}, - Outputs: []operand.Op{ops[2]}, - }, nil - } - return nil, errors.New("SHRQ: bad operands") +// VPSRLVW m128 xmm k xmm +// VPSRLVW m128 xmm xmm +// VPSRLVW m256 ymm k ymm +// VPSRLVW m256 ymm ymm +// VPSRLVW xmm xmm k xmm +// VPSRLVW xmm xmm xmm +// VPSRLVW ymm ymm k ymm +// VPSRLVW ymm ymm ymm +// VPSRLVW m512 zmm k zmm +// VPSRLVW m512 zmm zmm +// VPSRLVW zmm zmm k zmm +// VPSRLVW zmm zmm zmm +func VPSRLVW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRLVW.Forms(), sffxs{}, ops) } -// SHRW: Logical Shift Right. +// VPSRLVW_Z: Variable Shift Packed Word Data Right Logical (Zeroing Masking). // // Forms: // -// SHRW 1 r16 -// SHRW imm8 r16 -// SHRW cl r16 -// SHRW 1 m16 -// SHRW imm8 m16 -// SHRW cl m16 -// SHRW imm8 r16 r16 -// SHRW cl r16 r16 -// SHRW imm8 r16 m16 -// SHRW cl r16 m16 -func SHRW(ops ...operand.Op) (*intrep.Instruction, error) { - switch { - case len(ops) == 2 && operand.Is1(ops[0]) && operand.IsR16(ops[1]): - return &intrep.Instruction{ - Opcode: "SHRW", - Operands: ops, - Inputs: []operand.Op{ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.IsIMM8(ops[0]) && operand.IsR16(ops[1]): - return &intrep.Instruction{ - Opcode: "SHRW", - Operands: ops, - Inputs: []operand.Op{ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.IsCL(ops[0]) && operand.IsR16(ops[1]): - return &intrep.Instruction{ - Opcode: "SHRW", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.Is1(ops[0]) && operand.IsM16(ops[1]): - return &intrep.Instruction{ - Opcode: "SHRW", - Operands: ops, - Inputs: []operand.Op{ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.IsIMM8(ops[0]) && operand.IsM16(ops[1]): - return &intrep.Instruction{ - Opcode: "SHRW", - Operands: ops, - Inputs: []operand.Op{ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 2 && operand.IsCL(ops[0]) && operand.IsM16(ops[1]): - return &intrep.Instruction{ - Opcode: "SHRW", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1]}, - Outputs: []operand.Op{ops[1]}, - }, nil - case len(ops) == 3 && operand.IsIMM8(ops[0]) && operand.IsR16(ops[1]) && operand.IsR16(ops[2]): - return &intrep.Instruction{ - Opcode: "SHRW", - Operands: ops, - Inputs: []operand.Op{ops[1], ops[2]}, - Outputs: []operand.Op{ops[2]}, - }, nil - case len(ops) == 3 && operand.IsCL(ops[0]) && operand.IsR16(ops[1]) && operand.IsR16(ops[2]): - return &intrep.Instruction{ - Opcode: "SHRW", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1], ops[2]}, - Outputs: []operand.Op{ops[2]}, - }, nil - case len(ops) == 3 && operand.IsIMM8(ops[0]) && operand.IsR16(ops[1]) && operand.IsM16(ops[2]): - return &intrep.Instruction{ - Opcode: "SHRW", - Operands: ops, - Inputs: []operand.Op{ops[1], ops[2]}, - Outputs: []operand.Op{ops[2]}, - }, nil - case len(ops) == 3 && operand.IsCL(ops[0]) && operand.IsR16(ops[1]) && operand.IsM16(ops[2]): - return &intrep.Instruction{ - Opcode: "SHRW", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1], ops[2]}, - Outputs: []operand.Op{ops[2]}, - }, nil - } - return nil, errors.New("SHRW: bad operands") +// VPSRLVW.Z m128 xmm k xmm +// VPSRLVW.Z m256 ymm k ymm +// VPSRLVW.Z xmm xmm k xmm +// VPSRLVW.Z ymm ymm k ymm +// VPSRLVW.Z m512 zmm k zmm +// VPSRLVW.Z zmm zmm k zmm +func VPSRLVW_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRLVW.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// SHRXL: Logical Shift Right Without Affecting Flags. +// VPSRLW: Shift Packed Word Data Right Logical. // // Forms: // -// SHRXL r32 r32 r32 -// SHRXL r32 m32 r32 -func SHRXL(r, mr, r1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(r) && operand.IsR32(mr) && operand.IsR32(r1): - return &intrep.Instruction{ - Opcode: "SHRXL", - Operands: []operand.Op{r, mr, r1}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI2"}, - }, nil - case operand.IsR32(r) && operand.IsM32(mr) && operand.IsR32(r1): - return &intrep.Instruction{ - Opcode: "SHRXL", - Operands: []operand.Op{r, mr, r1}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI2"}, - }, nil - } - return nil, errors.New("SHRXL: bad operands") +// VPSRLW imm8 ymm ymm +// VPSRLW m128 ymm ymm +// VPSRLW xmm ymm ymm +// VPSRLW imm8 xmm xmm +// VPSRLW m128 xmm xmm +// VPSRLW xmm xmm xmm +// VPSRLW imm8 m128 k xmm +// VPSRLW imm8 m128 xmm +// VPSRLW imm8 m256 k ymm +// VPSRLW imm8 m256 ymm +// VPSRLW imm8 xmm k xmm +// VPSRLW imm8 ymm k ymm +// VPSRLW m128 xmm k xmm +// VPSRLW m128 ymm k ymm +// VPSRLW xmm xmm k xmm +// VPSRLW xmm ymm k ymm +// VPSRLW imm8 m512 k zmm +// VPSRLW imm8 m512 zmm +// VPSRLW imm8 zmm k zmm +// VPSRLW imm8 zmm zmm +// VPSRLW m128 zmm k zmm +// VPSRLW m128 zmm zmm +// VPSRLW xmm zmm k zmm +// VPSRLW xmm zmm zmm +func VPSRLW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRLW.Forms(), sffxs{}, ops) +} + +// VPSRLW_Z: Shift Packed Word Data Right Logical (Zeroing Masking). +// +// Forms: +// +// VPSRLW.Z imm8 m128 k xmm +// VPSRLW.Z imm8 m256 k ymm +// VPSRLW.Z imm8 xmm k xmm +// VPSRLW.Z imm8 ymm k ymm +// VPSRLW.Z m128 xmm k xmm +// VPSRLW.Z m128 ymm k ymm +// VPSRLW.Z xmm xmm k xmm +// VPSRLW.Z xmm ymm k ymm +// VPSRLW.Z imm8 m512 k zmm +// VPSRLW.Z imm8 zmm k zmm +// VPSRLW.Z m128 zmm k zmm +// VPSRLW.Z xmm zmm k zmm +func VPSRLW_Z(imx, mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPSRLW.Forms(), sffxs{sffxZ}, []operand.Op{imx, mxyz, k, xyz}) } -// SHRXQ: Logical Shift Right Without Affecting Flags. +// VPSUBB: Subtract Packed Byte Integers. // // Forms: // -// SHRXQ r64 r64 r64 -// SHRXQ r64 m64 r64 -func SHRXQ(r, mr, r1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(r) && operand.IsR64(mr) && operand.IsR64(r1): - return &intrep.Instruction{ - Opcode: "SHRXQ", - Operands: []operand.Op{r, mr, r1}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI2"}, - }, nil - case operand.IsR64(r) && operand.IsM64(mr) && operand.IsR64(r1): - return &intrep.Instruction{ - Opcode: "SHRXQ", - Operands: []operand.Op{r, mr, r1}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{r1}, - ISA: []string{"BMI2"}, - }, nil - } - return nil, errors.New("SHRXQ: bad operands") +// VPSUBB m256 ymm ymm +// VPSUBB ymm ymm ymm +// VPSUBB m128 xmm xmm +// VPSUBB xmm xmm xmm +// VPSUBB m128 xmm k xmm +// VPSUBB m256 ymm k ymm +// VPSUBB xmm xmm k xmm +// VPSUBB ymm ymm k ymm +// VPSUBB m512 zmm k zmm +// VPSUBB m512 zmm zmm +// VPSUBB zmm zmm k zmm +// VPSUBB zmm zmm zmm +func VPSUBB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSUBB.Forms(), sffxs{}, ops) } -// SHUFPD: Shuffle Packed Double-Precision Floating-Point Values. +// VPSUBB_Z: Subtract Packed Byte Integers (Zeroing Masking). // // Forms: // -// SHUFPD imm8 xmm xmm -// SHUFPD imm8 m128 xmm -func SHUFPD(i, mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SHUFPD", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SHUFPD", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("SHUFPD: bad operands") +// VPSUBB.Z m128 xmm k xmm +// VPSUBB.Z m256 ymm k ymm +// VPSUBB.Z xmm xmm k xmm +// VPSUBB.Z ymm ymm k ymm +// VPSUBB.Z m512 zmm k zmm +// VPSUBB.Z zmm zmm k zmm +func VPSUBB_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPSUBB.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// SHUFPS: Shuffle Packed Single-Precision Floating-Point Values. +// VPSUBD: Subtract Packed Doubleword Integers. // // Forms: // -// SHUFPS imm8 xmm xmm -// SHUFPS imm8 m128 xmm -func SHUFPS(i, mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SHUFPS", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SHUFPS", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("SHUFPS: bad operands") +// VPSUBD m256 ymm ymm +// VPSUBD ymm ymm ymm +// VPSUBD m128 xmm xmm +// VPSUBD xmm xmm xmm +// VPSUBD m128 xmm k xmm +// VPSUBD m256 ymm k ymm +// VPSUBD xmm xmm k xmm +// VPSUBD ymm ymm k ymm +// VPSUBD m512 zmm k zmm +// VPSUBD m512 zmm zmm +// VPSUBD zmm zmm k zmm +// VPSUBD zmm zmm zmm +func VPSUBD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSUBD.Forms(), sffxs{}, ops) } -// SQRTPD: Compute Square Roots of Packed Double-Precision Floating-Point Values. +// VPSUBD_BCST: Subtract Packed Doubleword Integers (Broadcast). // // Forms: // -// SQRTPD xmm xmm -// SQRTPD m128 xmm -func SQRTPD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SQRTPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SQRTPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("SQRTPD: bad operands") +// VPSUBD.BCST m32 xmm k xmm +// VPSUBD.BCST m32 xmm xmm +// VPSUBD.BCST m32 ymm k ymm +// VPSUBD.BCST m32 ymm ymm +// VPSUBD.BCST m32 zmm k zmm +// VPSUBD.BCST m32 zmm zmm +func VPSUBD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSUBD.Forms(), sffxs{sffxBCST}, ops) } -// SQRTPS: Compute Square Roots of Packed Single-Precision Floating-Point Values. +// VPSUBD_BCST_Z: Subtract Packed Doubleword Integers (Broadcast, Zeroing Masking). // // Forms: // -// SQRTPS xmm xmm -// SQRTPS m128 xmm -func SQRTPS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SQRTPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SQRTPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("SQRTPS: bad operands") +// VPSUBD.BCST.Z m32 xmm k xmm +// VPSUBD.BCST.Z m32 ymm k ymm +// VPSUBD.BCST.Z m32 zmm k zmm +func VPSUBD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPSUBD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// SQRTSD: Compute Square Root of Scalar Double-Precision Floating-Point Value. +// VPSUBD_Z: Subtract Packed Doubleword Integers (Zeroing Masking). // // Forms: // -// SQRTSD xmm xmm -// SQRTSD m64 xmm -func SQRTSD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SQRTSD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SQRTSD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("SQRTSD: bad operands") +// VPSUBD.Z m128 xmm k xmm +// VPSUBD.Z m256 ymm k ymm +// VPSUBD.Z xmm xmm k xmm +// VPSUBD.Z ymm ymm k ymm +// VPSUBD.Z m512 zmm k zmm +// VPSUBD.Z zmm zmm k zmm +func VPSUBD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPSUBD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// SQRTSS: Compute Square Root of Scalar Single-Precision Floating-Point Value. +// VPSUBQ: Subtract Packed Quadword Integers. // // Forms: // -// SQRTSS xmm xmm -// SQRTSS m32 xmm -func SQRTSS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SQRTSS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SQRTSS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("SQRTSS: bad operands") +// VPSUBQ m256 ymm ymm +// VPSUBQ ymm ymm ymm +// VPSUBQ m128 xmm xmm +// VPSUBQ xmm xmm xmm +// VPSUBQ m128 xmm k xmm +// VPSUBQ m256 ymm k ymm +// VPSUBQ xmm xmm k xmm +// VPSUBQ ymm ymm k ymm +// VPSUBQ m512 zmm k zmm +// VPSUBQ m512 zmm zmm +// VPSUBQ zmm zmm k zmm +// VPSUBQ zmm zmm zmm +func VPSUBQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSUBQ.Forms(), sffxs{}, ops) } -// STC: Set Carry Flag. +// VPSUBQ_BCST: Subtract Packed Quadword Integers (Broadcast). // // Forms: // -// STC -func STC() (*intrep.Instruction, error) { - return &intrep.Instruction{ - Opcode: "STC", - Operands: nil, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - }, nil +// VPSUBQ.BCST m64 xmm k xmm +// VPSUBQ.BCST m64 xmm xmm +// VPSUBQ.BCST m64 ymm k ymm +// VPSUBQ.BCST m64 ymm ymm +// VPSUBQ.BCST m64 zmm k zmm +// VPSUBQ.BCST m64 zmm zmm +func VPSUBQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSUBQ.Forms(), sffxs{sffxBCST}, ops) } -// STD: Set Direction Flag. +// VPSUBQ_BCST_Z: Subtract Packed Quadword Integers (Broadcast, Zeroing Masking). // // Forms: // -// STD -func STD() (*intrep.Instruction, error) { - return &intrep.Instruction{ - Opcode: "STD", - Operands: nil, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - }, nil +// VPSUBQ.BCST.Z m64 xmm k xmm +// VPSUBQ.BCST.Z m64 ymm k ymm +// VPSUBQ.BCST.Z m64 zmm k zmm +func VPSUBQ_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPSUBQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// STMXCSR: Store MXCSR Register State. +// VPSUBQ_Z: Subtract Packed Quadword Integers (Zeroing Masking). // // Forms: // -// STMXCSR m32 -func STMXCSR(m operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM32(m): - return &intrep.Instruction{ - Opcode: "STMXCSR", - Operands: []operand.Op{m}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{m}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("STMXCSR: bad operands") +// VPSUBQ.Z m128 xmm k xmm +// VPSUBQ.Z m256 ymm k ymm +// VPSUBQ.Z xmm xmm k xmm +// VPSUBQ.Z ymm ymm k ymm +// VPSUBQ.Z m512 zmm k zmm +// VPSUBQ.Z zmm zmm k zmm +func VPSUBQ_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPSUBQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// SUBB: Subtract. +// VPSUBSB: Subtract Packed Signed Byte Integers with Signed Saturation. // // Forms: // -// SUBB imm8 al -// SUBB imm8 r8 -// SUBB r8 r8 -// SUBB m8 r8 -// SUBB imm8 m8 -// SUBB r8 m8 -func SUBB(imr, amr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(imr) && operand.IsAL(amr): - return &intrep.Instruction{ - Opcode: "SUBB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM8(imr) && operand.IsR8(amr): - return &intrep.Instruction{ - Opcode: "SUBB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsR8(imr) && operand.IsR8(amr): - return &intrep.Instruction{ - Opcode: "SUBB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - CancellingInputs: true, - }, nil - case operand.IsM8(imr) && operand.IsR8(amr): - return &intrep.Instruction{ - Opcode: "SUBB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM8(imr) && operand.IsM8(amr): - return &intrep.Instruction{ - Opcode: "SUBB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsR8(imr) && operand.IsM8(amr): - return &intrep.Instruction{ - Opcode: "SUBB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - } - return nil, errors.New("SUBB: bad operands") +// VPSUBSB m256 ymm ymm +// VPSUBSB ymm ymm ymm +// VPSUBSB m128 xmm xmm +// VPSUBSB xmm xmm xmm +// VPSUBSB m128 xmm k xmm +// VPSUBSB m256 ymm k ymm +// VPSUBSB xmm xmm k xmm +// VPSUBSB ymm ymm k ymm +// VPSUBSB m512 zmm k zmm +// VPSUBSB m512 zmm zmm +// VPSUBSB zmm zmm k zmm +// VPSUBSB zmm zmm zmm +func VPSUBSB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSUBSB.Forms(), sffxs{}, ops) } -// SUBL: Subtract. +// VPSUBSB_Z: Subtract Packed Signed Byte Integers with Signed Saturation (Zeroing Masking). // // Forms: // -// SUBL imm32 eax -// SUBL imm8 r32 -// SUBL imm32 r32 -// SUBL r32 r32 -// SUBL m32 r32 -// SUBL imm8 m32 -// SUBL imm32 m32 -// SUBL r32 m32 -func SUBL(imr, emr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM32(imr) && operand.IsEAX(emr): - return &intrep.Instruction{ - Opcode: "SUBL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsIMM8(imr) && operand.IsR32(emr): - return &intrep.Instruction{ - Opcode: "SUBL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsIMM32(imr) && operand.IsR32(emr): - return &intrep.Instruction{ - Opcode: "SUBL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsR32(imr) && operand.IsR32(emr): - return &intrep.Instruction{ - Opcode: "SUBL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{imr, emr}, - Outputs: []operand.Op{emr}, - CancellingInputs: true, - }, nil - case operand.IsM32(imr) && operand.IsR32(emr): - return &intrep.Instruction{ - Opcode: "SUBL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{imr, emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsIMM8(imr) && operand.IsM32(emr): - return &intrep.Instruction{ - Opcode: "SUBL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsIMM32(imr) && operand.IsM32(emr): - return &intrep.Instruction{ - Opcode: "SUBL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsR32(imr) && operand.IsM32(emr): - return &intrep.Instruction{ - Opcode: "SUBL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{imr, emr}, - Outputs: []operand.Op{emr}, - }, nil - } - return nil, errors.New("SUBL: bad operands") +// VPSUBSB.Z m128 xmm k xmm +// VPSUBSB.Z m256 ymm k ymm +// VPSUBSB.Z xmm xmm k xmm +// VPSUBSB.Z ymm ymm k ymm +// VPSUBSB.Z m512 zmm k zmm +// VPSUBSB.Z zmm zmm k zmm +func VPSUBSB_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPSUBSB.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// SUBPD: Subtract Packed Double-Precision Floating-Point Values. +// VPSUBSW: Subtract Packed Signed Word Integers with Signed Saturation. // // Forms: // -// SUBPD xmm xmm -// SUBPD m128 xmm -func SUBPD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SUBPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SUBPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("SUBPD: bad operands") +// VPSUBSW m256 ymm ymm +// VPSUBSW ymm ymm ymm +// VPSUBSW m128 xmm xmm +// VPSUBSW xmm xmm xmm +// VPSUBSW m128 xmm k xmm +// VPSUBSW m256 ymm k ymm +// VPSUBSW xmm xmm k xmm +// VPSUBSW ymm ymm k ymm +// VPSUBSW m512 zmm k zmm +// VPSUBSW m512 zmm zmm +// VPSUBSW zmm zmm k zmm +// VPSUBSW zmm zmm zmm +func VPSUBSW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSUBSW.Forms(), sffxs{}, ops) } -// SUBPS: Subtract Packed Single-Precision Floating-Point Values. +// VPSUBSW_Z: Subtract Packed Signed Word Integers with Signed Saturation (Zeroing Masking). // // Forms: // -// SUBPS xmm xmm -// SUBPS m128 xmm -func SUBPS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SUBPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SUBPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("SUBPS: bad operands") +// VPSUBSW.Z m128 xmm k xmm +// VPSUBSW.Z m256 ymm k ymm +// VPSUBSW.Z xmm xmm k xmm +// VPSUBSW.Z ymm ymm k ymm +// VPSUBSW.Z m512 zmm k zmm +// VPSUBSW.Z zmm zmm k zmm +func VPSUBSW_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPSUBSW.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// SUBQ: Subtract. +// VPSUBUSB: Subtract Packed Unsigned Byte Integers with Unsigned Saturation. // // Forms: // -// SUBQ imm32 rax -// SUBQ imm8 r64 -// SUBQ imm32 r64 -// SUBQ r64 r64 -// SUBQ m64 r64 -// SUBQ imm8 m64 -// SUBQ imm32 m64 -// SUBQ r64 m64 -func SUBQ(imr, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM32(imr) && operand.IsRAX(mr): - return &intrep.Instruction{ - Opcode: "SUBQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(imr) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "SUBQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM32(imr) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "SUBQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR64(imr) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "SUBQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{imr, mr}, - Outputs: []operand.Op{mr}, - CancellingInputs: true, - }, nil - case operand.IsM64(imr) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "SUBQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{imr, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(imr) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "SUBQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM32(imr) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "SUBQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR64(imr) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "SUBQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{imr, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("SUBQ: bad operands") +// VPSUBUSB m256 ymm ymm +// VPSUBUSB ymm ymm ymm +// VPSUBUSB m128 xmm xmm +// VPSUBUSB xmm xmm xmm +// VPSUBUSB m128 xmm k xmm +// VPSUBUSB m256 ymm k ymm +// VPSUBUSB xmm xmm k xmm +// VPSUBUSB ymm ymm k ymm +// VPSUBUSB m512 zmm k zmm +// VPSUBUSB m512 zmm zmm +// VPSUBUSB zmm zmm k zmm +// VPSUBUSB zmm zmm zmm +func VPSUBUSB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSUBUSB.Forms(), sffxs{}, ops) } -// SUBSD: Subtract Scalar Double-Precision Floating-Point Values. +// VPSUBUSB_Z: Subtract Packed Unsigned Byte Integers with Unsigned Saturation (Zeroing Masking). // // Forms: // -// SUBSD xmm xmm -// SUBSD m64 xmm -func SUBSD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SUBSD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SUBSD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("SUBSD: bad operands") +// VPSUBUSB.Z m128 xmm k xmm +// VPSUBUSB.Z m256 ymm k ymm +// VPSUBUSB.Z xmm xmm k xmm +// VPSUBUSB.Z ymm ymm k ymm +// VPSUBUSB.Z m512 zmm k zmm +// VPSUBUSB.Z zmm zmm k zmm +func VPSUBUSB_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPSUBUSB.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// SUBSS: Subtract Scalar Single-Precision Floating-Point Values. +// VPSUBUSW: Subtract Packed Unsigned Word Integers with Unsigned Saturation. // // Forms: // -// SUBSS xmm xmm -// SUBSS m32 xmm -func SUBSS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SUBSS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "SUBSS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("SUBSS: bad operands") +// VPSUBUSW m256 ymm ymm +// VPSUBUSW ymm ymm ymm +// VPSUBUSW m128 xmm xmm +// VPSUBUSW xmm xmm xmm +// VPSUBUSW m128 xmm k xmm +// VPSUBUSW m256 ymm k ymm +// VPSUBUSW xmm xmm k xmm +// VPSUBUSW ymm ymm k ymm +// VPSUBUSW m512 zmm k zmm +// VPSUBUSW m512 zmm zmm +// VPSUBUSW zmm zmm k zmm +// VPSUBUSW zmm zmm zmm +func VPSUBUSW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSUBUSW.Forms(), sffxs{}, ops) } -// SUBW: Subtract. +// VPSUBUSW_Z: Subtract Packed Unsigned Word Integers with Unsigned Saturation (Zeroing Masking). // // Forms: // -// SUBW imm16 ax -// SUBW imm8 r16 -// SUBW imm16 r16 -// SUBW r16 r16 -// SUBW m16 r16 -// SUBW imm8 m16 -// SUBW imm16 m16 -// SUBW r16 m16 -func SUBW(imr, amr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM16(imr) && operand.IsAX(amr): - return &intrep.Instruction{ - Opcode: "SUBW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM8(imr) && operand.IsR16(amr): - return &intrep.Instruction{ - Opcode: "SUBW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM16(imr) && operand.IsR16(amr): - return &intrep.Instruction{ - Opcode: "SUBW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsR16(imr) && operand.IsR16(amr): - return &intrep.Instruction{ - Opcode: "SUBW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - CancellingInputs: true, - }, nil - case operand.IsM16(imr) && operand.IsR16(amr): - return &intrep.Instruction{ - Opcode: "SUBW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM8(imr) && operand.IsM16(amr): - return &intrep.Instruction{ - Opcode: "SUBW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM16(imr) && operand.IsM16(amr): - return &intrep.Instruction{ - Opcode: "SUBW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsR16(imr) && operand.IsM16(amr): - return &intrep.Instruction{ - Opcode: "SUBW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - } - return nil, errors.New("SUBW: bad operands") +// VPSUBUSW.Z m128 xmm k xmm +// VPSUBUSW.Z m256 ymm k ymm +// VPSUBUSW.Z xmm xmm k xmm +// VPSUBUSW.Z ymm ymm k ymm +// VPSUBUSW.Z m512 zmm k zmm +// VPSUBUSW.Z zmm zmm k zmm +func VPSUBUSW_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPSUBUSW.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// SYSCALL: Fast System Call. +// VPSUBW: Subtract Packed Word Integers. // // Forms: // -// SYSCALL -func SYSCALL() (*intrep.Instruction, error) { - return &intrep.Instruction{ - Opcode: "SYSCALL", - Operands: nil, - Inputs: []operand.Op{}, - Outputs: []operand.Op{reg.R11, reg.RCX}, - }, nil +// VPSUBW m256 ymm ymm +// VPSUBW ymm ymm ymm +// VPSUBW m128 xmm xmm +// VPSUBW xmm xmm xmm +// VPSUBW m128 xmm k xmm +// VPSUBW m256 ymm k ymm +// VPSUBW xmm xmm k xmm +// VPSUBW ymm ymm k ymm +// VPSUBW m512 zmm k zmm +// VPSUBW m512 zmm zmm +// VPSUBW zmm zmm k zmm +// VPSUBW zmm zmm zmm +func VPSUBW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSUBW.Forms(), sffxs{}, ops) } -// TESTB: Logical Compare. +// VPSUBW_Z: Subtract Packed Word Integers (Zeroing Masking). // // Forms: // -// TESTB imm8 al -// TESTB imm8 r8 -// TESTB r8 r8 -// TESTB imm8 m8 -// TESTB r8 m8 -func TESTB(ir, amr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(ir) && operand.IsAL(amr): - return &intrep.Instruction{ - Opcode: "TESTB", - Operands: []operand.Op{ir, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsIMM8(ir) && operand.IsR8(amr): - return &intrep.Instruction{ - Opcode: "TESTB", - Operands: []operand.Op{ir, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsR8(ir) && operand.IsR8(amr): - return &intrep.Instruction{ - Opcode: "TESTB", - Operands: []operand.Op{ir, amr}, - Inputs: []operand.Op{ir, amr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsIMM8(ir) && operand.IsM8(amr): - return &intrep.Instruction{ - Opcode: "TESTB", - Operands: []operand.Op{ir, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsR8(ir) && operand.IsM8(amr): - return &intrep.Instruction{ - Opcode: "TESTB", - Operands: []operand.Op{ir, amr}, - Inputs: []operand.Op{ir, amr}, - Outputs: []operand.Op{}, - }, nil - } - return nil, errors.New("TESTB: bad operands") +// VPSUBW.Z m128 xmm k xmm +// VPSUBW.Z m256 ymm k ymm +// VPSUBW.Z xmm xmm k xmm +// VPSUBW.Z ymm ymm k ymm +// VPSUBW.Z m512 zmm k zmm +// VPSUBW.Z zmm zmm k zmm +func VPSUBW_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPSUBW.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// TESTL: Logical Compare. +// VPTERNLOGD: Bitwise Ternary Logical Operation on Doubleword Values. // // Forms: // -// TESTL imm32 eax -// TESTL imm32 r32 -// TESTL r32 r32 -// TESTL imm32 m32 -// TESTL r32 m32 -func TESTL(ir, emr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM32(ir) && operand.IsEAX(emr): - return &intrep.Instruction{ - Opcode: "TESTL", - Operands: []operand.Op{ir, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsIMM32(ir) && operand.IsR32(emr): - return &intrep.Instruction{ - Opcode: "TESTL", - Operands: []operand.Op{ir, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsR32(ir) && operand.IsR32(emr): - return &intrep.Instruction{ - Opcode: "TESTL", - Operands: []operand.Op{ir, emr}, - Inputs: []operand.Op{ir, emr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsIMM32(ir) && operand.IsM32(emr): - return &intrep.Instruction{ - Opcode: "TESTL", - Operands: []operand.Op{ir, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsR32(ir) && operand.IsM32(emr): - return &intrep.Instruction{ - Opcode: "TESTL", - Operands: []operand.Op{ir, emr}, - Inputs: []operand.Op{ir, emr}, - Outputs: []operand.Op{}, - }, nil - } - return nil, errors.New("TESTL: bad operands") +// VPTERNLOGD imm8 m128 xmm k xmm +// VPTERNLOGD imm8 m128 xmm xmm +// VPTERNLOGD imm8 m256 ymm k ymm +// VPTERNLOGD imm8 m256 ymm ymm +// VPTERNLOGD imm8 xmm xmm k xmm +// VPTERNLOGD imm8 xmm xmm xmm +// VPTERNLOGD imm8 ymm ymm k ymm +// VPTERNLOGD imm8 ymm ymm ymm +// VPTERNLOGD imm8 m512 zmm k zmm +// VPTERNLOGD imm8 m512 zmm zmm +// VPTERNLOGD imm8 zmm zmm k zmm +// VPTERNLOGD imm8 zmm zmm zmm +func VPTERNLOGD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPTERNLOGD.Forms(), sffxs{}, ops) } -// TESTQ: Logical Compare. +// VPTERNLOGD_BCST: Bitwise Ternary Logical Operation on Doubleword Values (Broadcast). // // Forms: // -// TESTQ imm32 rax -// TESTQ imm32 r64 -// TESTQ r64 r64 -// TESTQ imm32 m64 -// TESTQ r64 m64 -func TESTQ(ir, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM32(ir) && operand.IsRAX(mr): - return &intrep.Instruction{ - Opcode: "TESTQ", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsIMM32(ir) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "TESTQ", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsR64(ir) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "TESTQ", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{ir, mr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsIMM32(ir) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "TESTQ", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsR64(ir) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "TESTQ", - Operands: []operand.Op{ir, mr}, - Inputs: []operand.Op{ir, mr}, - Outputs: []operand.Op{}, - }, nil - } - return nil, errors.New("TESTQ: bad operands") +// VPTERNLOGD.BCST imm8 m32 xmm k xmm +// VPTERNLOGD.BCST imm8 m32 xmm xmm +// VPTERNLOGD.BCST imm8 m32 ymm k ymm +// VPTERNLOGD.BCST imm8 m32 ymm ymm +// VPTERNLOGD.BCST imm8 m32 zmm k zmm +// VPTERNLOGD.BCST imm8 m32 zmm zmm +func VPTERNLOGD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPTERNLOGD.Forms(), sffxs{sffxBCST}, ops) } -// TESTW: Logical Compare. +// VPTERNLOGD_BCST_Z: Bitwise Ternary Logical Operation on Doubleword Values (Broadcast, Zeroing Masking). // // Forms: // -// TESTW imm16 ax -// TESTW imm16 r16 -// TESTW r16 r16 -// TESTW imm16 m16 -// TESTW r16 m16 -func TESTW(ir, amr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM16(ir) && operand.IsAX(amr): - return &intrep.Instruction{ - Opcode: "TESTW", - Operands: []operand.Op{ir, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsIMM16(ir) && operand.IsR16(amr): - return &intrep.Instruction{ - Opcode: "TESTW", - Operands: []operand.Op{ir, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsR16(ir) && operand.IsR16(amr): - return &intrep.Instruction{ - Opcode: "TESTW", - Operands: []operand.Op{ir, amr}, - Inputs: []operand.Op{ir, amr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsIMM16(ir) && operand.IsM16(amr): - return &intrep.Instruction{ - Opcode: "TESTW", - Operands: []operand.Op{ir, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{}, - }, nil - case operand.IsR16(ir) && operand.IsM16(amr): - return &intrep.Instruction{ - Opcode: "TESTW", - Operands: []operand.Op{ir, amr}, - Inputs: []operand.Op{ir, amr}, - Outputs: []operand.Op{}, - }, nil - } - return nil, errors.New("TESTW: bad operands") +// VPTERNLOGD.BCST.Z imm8 m32 xmm k xmm +// VPTERNLOGD.BCST.Z imm8 m32 ymm k ymm +// VPTERNLOGD.BCST.Z imm8 m32 zmm k zmm +func VPTERNLOGD_BCST_Z(i, m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPTERNLOGD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{i, m, xyz, k, xyz1}) } -// TZCNTL: Count the Number of Trailing Zero Bits. +// VPTERNLOGD_Z: Bitwise Ternary Logical Operation on Doubleword Values (Zeroing Masking). // // Forms: // -// TZCNTL r32 r32 -// TZCNTL m32 r32 -func TZCNTL(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "TZCNTL", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"BMI"}, - }, nil - case operand.IsM32(mr) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "TZCNTL", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"BMI"}, - }, nil - } - return nil, errors.New("TZCNTL: bad operands") +// VPTERNLOGD.Z imm8 m128 xmm k xmm +// VPTERNLOGD.Z imm8 m256 ymm k ymm +// VPTERNLOGD.Z imm8 xmm xmm k xmm +// VPTERNLOGD.Z imm8 ymm ymm k ymm +// VPTERNLOGD.Z imm8 m512 zmm k zmm +// VPTERNLOGD.Z imm8 zmm zmm k zmm +func VPTERNLOGD_Z(i, mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPTERNLOGD.Forms(), sffxs{sffxZ}, []operand.Op{i, mxyz, xyz, k, xyz1}) } -// TZCNTQ: Count the Number of Trailing Zero Bits. +// VPTERNLOGQ: Bitwise Ternary Logical Operation on Quadword Values. // // Forms: // -// TZCNTQ r64 r64 -// TZCNTQ m64 r64 -func TZCNTQ(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "TZCNTQ", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"BMI"}, - }, nil - case operand.IsM64(mr) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "TZCNTQ", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"BMI"}, - }, nil - } - return nil, errors.New("TZCNTQ: bad operands") +// VPTERNLOGQ imm8 m128 xmm k xmm +// VPTERNLOGQ imm8 m128 xmm xmm +// VPTERNLOGQ imm8 m256 ymm k ymm +// VPTERNLOGQ imm8 m256 ymm ymm +// VPTERNLOGQ imm8 xmm xmm k xmm +// VPTERNLOGQ imm8 xmm xmm xmm +// VPTERNLOGQ imm8 ymm ymm k ymm +// VPTERNLOGQ imm8 ymm ymm ymm +// VPTERNLOGQ imm8 m512 zmm k zmm +// VPTERNLOGQ imm8 m512 zmm zmm +// VPTERNLOGQ imm8 zmm zmm k zmm +// VPTERNLOGQ imm8 zmm zmm zmm +func VPTERNLOGQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPTERNLOGQ.Forms(), sffxs{}, ops) } -// TZCNTW: Count the Number of Trailing Zero Bits. +// VPTERNLOGQ_BCST: Bitwise Ternary Logical Operation on Quadword Values (Broadcast). // // Forms: // -// TZCNTW r16 r16 -// TZCNTW m16 r16 -func TZCNTW(mr, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "TZCNTW", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"BMI"}, - }, nil - case operand.IsM16(mr) && operand.IsR16(r): - return &intrep.Instruction{ - Opcode: "TZCNTW", - Operands: []operand.Op{mr, r}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{r}, - ISA: []string{"BMI"}, - }, nil - } - return nil, errors.New("TZCNTW: bad operands") +// VPTERNLOGQ.BCST imm8 m64 xmm k xmm +// VPTERNLOGQ.BCST imm8 m64 xmm xmm +// VPTERNLOGQ.BCST imm8 m64 ymm k ymm +// VPTERNLOGQ.BCST imm8 m64 ymm ymm +// VPTERNLOGQ.BCST imm8 m64 zmm k zmm +// VPTERNLOGQ.BCST imm8 m64 zmm zmm +func VPTERNLOGQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPTERNLOGQ.Forms(), sffxs{sffxBCST}, ops) } -// UCOMISD: Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS. +// VPTERNLOGQ_BCST_Z: Bitwise Ternary Logical Operation on Quadword Values (Broadcast, Zeroing Masking). // // Forms: // -// UCOMISD xmm xmm -// UCOMISD m64 xmm -func UCOMISD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "UCOMISD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "UCOMISD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("UCOMISD: bad operands") +// VPTERNLOGQ.BCST.Z imm8 m64 xmm k xmm +// VPTERNLOGQ.BCST.Z imm8 m64 ymm k ymm +// VPTERNLOGQ.BCST.Z imm8 m64 zmm k zmm +func VPTERNLOGQ_BCST_Z(i, m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPTERNLOGQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{i, m, xyz, k, xyz1}) } -// UCOMISS: Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS. +// VPTERNLOGQ_Z: Bitwise Ternary Logical Operation on Quadword Values (Zeroing Masking). // // Forms: // -// UCOMISS xmm xmm -// UCOMISS m32 xmm -func UCOMISS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "UCOMISS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "UCOMISS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("UCOMISS: bad operands") +// VPTERNLOGQ.Z imm8 m128 xmm k xmm +// VPTERNLOGQ.Z imm8 m256 ymm k ymm +// VPTERNLOGQ.Z imm8 xmm xmm k xmm +// VPTERNLOGQ.Z imm8 ymm ymm k ymm +// VPTERNLOGQ.Z imm8 m512 zmm k zmm +// VPTERNLOGQ.Z imm8 zmm zmm k zmm +func VPTERNLOGQ_Z(i, mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPTERNLOGQ.Forms(), sffxs{sffxZ}, []operand.Op{i, mxyz, xyz, k, xyz1}) } -// UD2: Undefined Instruction. +// VPTEST: Packed Logical Compare. // // Forms: // -// UD2 -func UD2() (*intrep.Instruction, error) { - return &intrep.Instruction{ - Opcode: "UD2", - Operands: nil, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - }, nil +// VPTEST m128 xmm +// VPTEST m256 ymm +// VPTEST xmm xmm +// VPTEST ymm ymm +func VPTEST(mxy, xy operand.Op) (*intrep.Instruction, error) { + return build(opcVPTEST.Forms(), sffxs{}, []operand.Op{mxy, xy}) } -// UNPCKHPD: Unpack and Interleave High Packed Double-Precision Floating-Point Values. +// VPTESTMB: Logical AND of Packed Byte Integer Values and Set Mask. // // Forms: // -// UNPCKHPD xmm xmm -// UNPCKHPD m128 xmm -func UNPCKHPD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "UNPCKHPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "UNPCKHPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("UNPCKHPD: bad operands") +// VPTESTMB m128 xmm k k +// VPTESTMB m128 xmm k +// VPTESTMB m256 ymm k k +// VPTESTMB m256 ymm k +// VPTESTMB xmm xmm k k +// VPTESTMB xmm xmm k +// VPTESTMB ymm ymm k k +// VPTESTMB ymm ymm k +// VPTESTMB m512 zmm k k +// VPTESTMB m512 zmm k +// VPTESTMB zmm zmm k k +// VPTESTMB zmm zmm k +func VPTESTMB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPTESTMB.Forms(), sffxs{}, ops) } -// UNPCKHPS: Unpack and Interleave High Packed Single-Precision Floating-Point Values. +// VPTESTMD: Logical AND of Packed Doubleword Integer Values and Set Mask. // // Forms: // -// UNPCKHPS xmm xmm -// UNPCKHPS m128 xmm -func UNPCKHPS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "UNPCKHPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "UNPCKHPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("UNPCKHPS: bad operands") +// VPTESTMD m128 xmm k k +// VPTESTMD m128 xmm k +// VPTESTMD m256 ymm k k +// VPTESTMD m256 ymm k +// VPTESTMD xmm xmm k k +// VPTESTMD xmm xmm k +// VPTESTMD ymm ymm k k +// VPTESTMD ymm ymm k +// VPTESTMD m512 zmm k k +// VPTESTMD m512 zmm k +// VPTESTMD zmm zmm k k +// VPTESTMD zmm zmm k +func VPTESTMD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPTESTMD.Forms(), sffxs{}, ops) } -// UNPCKLPD: Unpack and Interleave Low Packed Double-Precision Floating-Point Values. +// VPTESTMD_BCST: Logical AND of Packed Doubleword Integer Values and Set Mask (Broadcast). // // Forms: // -// UNPCKLPD xmm xmm -// UNPCKLPD m128 xmm -func UNPCKLPD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "UNPCKLPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "UNPCKLPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("UNPCKLPD: bad operands") +// VPTESTMD.BCST m32 xmm k k +// VPTESTMD.BCST m32 xmm k +// VPTESTMD.BCST m32 ymm k k +// VPTESTMD.BCST m32 ymm k +// VPTESTMD.BCST m32 zmm k k +// VPTESTMD.BCST m32 zmm k +func VPTESTMD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPTESTMD.Forms(), sffxs{sffxBCST}, ops) } -// UNPCKLPS: Unpack and Interleave Low Packed Single-Precision Floating-Point Values. +// VPTESTMQ: Logical AND of Packed Quadword Integer Values and Set Mask. // // Forms: // -// UNPCKLPS xmm xmm -// UNPCKLPS m128 xmm -func UNPCKLPS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "UNPCKLPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "UNPCKLPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("UNPCKLPS: bad operands") +// VPTESTMQ m128 xmm k k +// VPTESTMQ m128 xmm k +// VPTESTMQ m256 ymm k k +// VPTESTMQ m256 ymm k +// VPTESTMQ xmm xmm k k +// VPTESTMQ xmm xmm k +// VPTESTMQ ymm ymm k k +// VPTESTMQ ymm ymm k +// VPTESTMQ m512 zmm k k +// VPTESTMQ m512 zmm k +// VPTESTMQ zmm zmm k k +// VPTESTMQ zmm zmm k +func VPTESTMQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPTESTMQ.Forms(), sffxs{}, ops) } -// VADDPD: Add Packed Double-Precision Floating-Point Values. +// VPTESTMQ_BCST: Logical AND of Packed Quadword Integer Values and Set Mask (Broadcast). // // Forms: // -// VADDPD xmm xmm xmm -// VADDPD m128 xmm xmm -// VADDPD ymm ymm ymm -// VADDPD m256 ymm ymm -func VADDPD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VADDPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VADDPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VADDPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VADDPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VADDPD: bad operands") +// VPTESTMQ.BCST m64 xmm k k +// VPTESTMQ.BCST m64 xmm k +// VPTESTMQ.BCST m64 ymm k k +// VPTESTMQ.BCST m64 ymm k +// VPTESTMQ.BCST m64 zmm k k +// VPTESTMQ.BCST m64 zmm k +func VPTESTMQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPTESTMQ.Forms(), sffxs{sffxBCST}, ops) } -// VADDPS: Add Packed Single-Precision Floating-Point Values. +// VPTESTMW: Logical AND of Packed Word Integer Values and Set Mask. // // Forms: // -// VADDPS xmm xmm xmm -// VADDPS m128 xmm xmm -// VADDPS ymm ymm ymm -// VADDPS m256 ymm ymm -func VADDPS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VADDPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VADDPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VADDPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VADDPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VADDPS: bad operands") +// VPTESTMW m128 xmm k k +// VPTESTMW m128 xmm k +// VPTESTMW m256 ymm k k +// VPTESTMW m256 ymm k +// VPTESTMW xmm xmm k k +// VPTESTMW xmm xmm k +// VPTESTMW ymm ymm k k +// VPTESTMW ymm ymm k +// VPTESTMW m512 zmm k k +// VPTESTMW m512 zmm k +// VPTESTMW zmm zmm k k +// VPTESTMW zmm zmm k +func VPTESTMW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPTESTMW.Forms(), sffxs{}, ops) } -// VADDSD: Add Scalar Double-Precision Floating-Point Values. +// VPTESTNMB: Logical NAND of Packed Byte Integer Values and Set Mask. // // Forms: // -// VADDSD xmm xmm xmm -// VADDSD m64 xmm xmm -func VADDSD(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VADDSD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VADDSD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VADDSD: bad operands") +// VPTESTNMB m512 zmm k k +// VPTESTNMB m512 zmm k +// VPTESTNMB zmm zmm k k +// VPTESTNMB zmm zmm k +// VPTESTNMB m128 xmm k k +// VPTESTNMB m128 xmm k +// VPTESTNMB m256 ymm k k +// VPTESTNMB m256 ymm k +// VPTESTNMB xmm xmm k k +// VPTESTNMB xmm xmm k +// VPTESTNMB ymm ymm k k +// VPTESTNMB ymm ymm k +func VPTESTNMB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPTESTNMB.Forms(), sffxs{}, ops) } -// VADDSS: Add Scalar Single-Precision Floating-Point Values. +// VPTESTNMD: Logical NAND of Packed Doubleword Integer Values and Set Mask. // // Forms: // -// VADDSS xmm xmm xmm -// VADDSS m32 xmm xmm -func VADDSS(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VADDSS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VADDSS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VADDSS: bad operands") +// VPTESTNMD m128 xmm k k +// VPTESTNMD m128 xmm k +// VPTESTNMD m256 ymm k k +// VPTESTNMD m256 ymm k +// VPTESTNMD xmm xmm k k +// VPTESTNMD xmm xmm k +// VPTESTNMD ymm ymm k k +// VPTESTNMD ymm ymm k +// VPTESTNMD m512 zmm k k +// VPTESTNMD m512 zmm k +// VPTESTNMD zmm zmm k k +// VPTESTNMD zmm zmm k +func VPTESTNMD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPTESTNMD.Forms(), sffxs{}, ops) } -// VADDSUBPD: Packed Double-FP Add/Subtract. +// VPTESTNMD_BCST: Logical NAND of Packed Doubleword Integer Values and Set Mask (Broadcast). // // Forms: // -// VADDSUBPD xmm xmm xmm -// VADDSUBPD m128 xmm xmm -// VADDSUBPD ymm ymm ymm -// VADDSUBPD m256 ymm ymm -func VADDSUBPD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VADDSUBPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VADDSUBPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VADDSUBPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VADDSUBPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VADDSUBPD: bad operands") +// VPTESTNMD.BCST m32 xmm k k +// VPTESTNMD.BCST m32 xmm k +// VPTESTNMD.BCST m32 ymm k k +// VPTESTNMD.BCST m32 ymm k +// VPTESTNMD.BCST m32 zmm k k +// VPTESTNMD.BCST m32 zmm k +func VPTESTNMD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPTESTNMD.Forms(), sffxs{sffxBCST}, ops) } -// VADDSUBPS: Packed Single-FP Add/Subtract. +// VPTESTNMQ: Logical NAND of Packed Quadword Integer Values and Set Mask. // // Forms: // -// VADDSUBPS xmm xmm xmm -// VADDSUBPS m128 xmm xmm -// VADDSUBPS ymm ymm ymm -// VADDSUBPS m256 ymm ymm -func VADDSUBPS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VADDSUBPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VADDSUBPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VADDSUBPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VADDSUBPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VADDSUBPS: bad operands") +// VPTESTNMQ m128 xmm k k +// VPTESTNMQ m128 xmm k +// VPTESTNMQ m256 ymm k k +// VPTESTNMQ m256 ymm k +// VPTESTNMQ xmm xmm k k +// VPTESTNMQ xmm xmm k +// VPTESTNMQ ymm ymm k k +// VPTESTNMQ ymm ymm k +// VPTESTNMQ m512 zmm k k +// VPTESTNMQ m512 zmm k +// VPTESTNMQ zmm zmm k k +// VPTESTNMQ zmm zmm k +func VPTESTNMQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPTESTNMQ.Forms(), sffxs{}, ops) } -// VAESDEC: Perform One Round of an AES Decryption Flow. +// VPTESTNMQ_BCST: Logical NAND of Packed Quadword Integer Values and Set Mask (Broadcast). // // Forms: // -// VAESDEC xmm xmm xmm -// VAESDEC m128 xmm xmm -func VAESDEC(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VAESDEC", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX", "AES"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VAESDEC", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX", "AES"}, - }, nil - } - return nil, errors.New("VAESDEC: bad operands") +// VPTESTNMQ.BCST m64 xmm k k +// VPTESTNMQ.BCST m64 xmm k +// VPTESTNMQ.BCST m64 ymm k k +// VPTESTNMQ.BCST m64 ymm k +// VPTESTNMQ.BCST m64 zmm k k +// VPTESTNMQ.BCST m64 zmm k +func VPTESTNMQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPTESTNMQ.Forms(), sffxs{sffxBCST}, ops) } -// VAESDECLAST: Perform Last Round of an AES Decryption Flow. +// VPTESTNMW: Logical NAND of Packed Word Integer Values and Set Mask. // // Forms: // -// VAESDECLAST xmm xmm xmm -// VAESDECLAST m128 xmm xmm -func VAESDECLAST(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VAESDECLAST", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX", "AES"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VAESDECLAST", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX", "AES"}, - }, nil - } - return nil, errors.New("VAESDECLAST: bad operands") +// VPTESTNMW m512 zmm k k +// VPTESTNMW m512 zmm k +// VPTESTNMW zmm zmm k k +// VPTESTNMW zmm zmm k +// VPTESTNMW m128 xmm k k +// VPTESTNMW m128 xmm k +// VPTESTNMW m256 ymm k k +// VPTESTNMW m256 ymm k +// VPTESTNMW xmm xmm k k +// VPTESTNMW xmm xmm k +// VPTESTNMW ymm ymm k k +// VPTESTNMW ymm ymm k +func VPTESTNMW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPTESTNMW.Forms(), sffxs{}, ops) } -// VAESENC: Perform One Round of an AES Encryption Flow. +// VPUNPCKHBW: Unpack and Interleave High-Order Bytes into Words. // // Forms: // -// VAESENC xmm xmm xmm -// VAESENC m128 xmm xmm -func VAESENC(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VAESENC", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX", "AES"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VAESENC", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX", "AES"}, - }, nil - } - return nil, errors.New("VAESENC: bad operands") +// VPUNPCKHBW m256 ymm ymm +// VPUNPCKHBW ymm ymm ymm +// VPUNPCKHBW m128 xmm xmm +// VPUNPCKHBW xmm xmm xmm +// VPUNPCKHBW m128 xmm k xmm +// VPUNPCKHBW m256 ymm k ymm +// VPUNPCKHBW xmm xmm k xmm +// VPUNPCKHBW ymm ymm k ymm +// VPUNPCKHBW m512 zmm k zmm +// VPUNPCKHBW m512 zmm zmm +// VPUNPCKHBW zmm zmm k zmm +// VPUNPCKHBW zmm zmm zmm +func VPUNPCKHBW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPUNPCKHBW.Forms(), sffxs{}, ops) } -// VAESENCLAST: Perform Last Round of an AES Encryption Flow. +// VPUNPCKHBW_Z: Unpack and Interleave High-Order Bytes into Words (Zeroing Masking). // // Forms: // -// VAESENCLAST xmm xmm xmm -// VAESENCLAST m128 xmm xmm -func VAESENCLAST(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VAESENCLAST", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX", "AES"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VAESENCLAST", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX", "AES"}, - }, nil - } - return nil, errors.New("VAESENCLAST: bad operands") +// VPUNPCKHBW.Z m128 xmm k xmm +// VPUNPCKHBW.Z m256 ymm k ymm +// VPUNPCKHBW.Z xmm xmm k xmm +// VPUNPCKHBW.Z ymm ymm k ymm +// VPUNPCKHBW.Z m512 zmm k zmm +// VPUNPCKHBW.Z zmm zmm k zmm +func VPUNPCKHBW_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPUNPCKHBW.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// VAESIMC: Perform the AES InvMixColumn Transformation. +// VPUNPCKHDQ: Unpack and Interleave High-Order Doublewords into Quadwords. // // Forms: // -// VAESIMC xmm xmm -// VAESIMC m128 xmm -func VAESIMC(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VAESIMC", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"AVX", "AES"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VAESIMC", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"AVX", "AES"}, - }, nil - } - return nil, errors.New("VAESIMC: bad operands") +// VPUNPCKHDQ m256 ymm ymm +// VPUNPCKHDQ ymm ymm ymm +// VPUNPCKHDQ m128 xmm xmm +// VPUNPCKHDQ xmm xmm xmm +// VPUNPCKHDQ m128 xmm k xmm +// VPUNPCKHDQ m256 ymm k ymm +// VPUNPCKHDQ xmm xmm k xmm +// VPUNPCKHDQ ymm ymm k ymm +// VPUNPCKHDQ m512 zmm k zmm +// VPUNPCKHDQ m512 zmm zmm +// VPUNPCKHDQ zmm zmm k zmm +// VPUNPCKHDQ zmm zmm zmm +func VPUNPCKHDQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPUNPCKHDQ.Forms(), sffxs{}, ops) } -// VAESKEYGENASSIST: AES Round Key Generation Assist. +// VPUNPCKHDQ_BCST: Unpack and Interleave High-Order Doublewords into Quadwords (Broadcast). // // Forms: // -// VAESKEYGENASSIST imm8 xmm xmm -// VAESKEYGENASSIST imm8 m128 xmm -func VAESKEYGENASSIST(i, mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VAESKEYGENASSIST", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"AVX", "AES"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VAESKEYGENASSIST", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"AVX", "AES"}, - }, nil - } - return nil, errors.New("VAESKEYGENASSIST: bad operands") +// VPUNPCKHDQ.BCST m32 xmm k xmm +// VPUNPCKHDQ.BCST m32 xmm xmm +// VPUNPCKHDQ.BCST m32 ymm k ymm +// VPUNPCKHDQ.BCST m32 ymm ymm +// VPUNPCKHDQ.BCST m32 zmm k zmm +// VPUNPCKHDQ.BCST m32 zmm zmm +func VPUNPCKHDQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPUNPCKHDQ.Forms(), sffxs{sffxBCST}, ops) } -// VANDNPD: Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values. +// VPUNPCKHDQ_BCST_Z: Unpack and Interleave High-Order Doublewords into Quadwords (Broadcast, Zeroing Masking). // // Forms: // -// VANDNPD xmm xmm xmm -// VANDNPD m128 xmm xmm -// VANDNPD ymm ymm ymm -// VANDNPD m256 ymm ymm -func VANDNPD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VANDNPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VANDNPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VANDNPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - CancellingInputs: true, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VANDNPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VANDNPD: bad operands") +// VPUNPCKHDQ.BCST.Z m32 xmm k xmm +// VPUNPCKHDQ.BCST.Z m32 ymm k ymm +// VPUNPCKHDQ.BCST.Z m32 zmm k zmm +func VPUNPCKHDQ_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPUNPCKHDQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// VANDNPS: Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values. +// VPUNPCKHDQ_Z: Unpack and Interleave High-Order Doublewords into Quadwords (Zeroing Masking). // // Forms: // -// VANDNPS xmm xmm xmm -// VANDNPS m128 xmm xmm -// VANDNPS ymm ymm ymm -// VANDNPS m256 ymm ymm -func VANDNPS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VANDNPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VANDNPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VANDNPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - CancellingInputs: true, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VANDNPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VANDNPS: bad operands") +// VPUNPCKHDQ.Z m128 xmm k xmm +// VPUNPCKHDQ.Z m256 ymm k ymm +// VPUNPCKHDQ.Z xmm xmm k xmm +// VPUNPCKHDQ.Z ymm ymm k ymm +// VPUNPCKHDQ.Z m512 zmm k zmm +// VPUNPCKHDQ.Z zmm zmm k zmm +func VPUNPCKHDQ_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPUNPCKHDQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// VANDPD: Bitwise Logical AND of Packed Double-Precision Floating-Point Values. +// VPUNPCKHQDQ: Unpack and Interleave High-Order Quadwords into Double Quadwords. // // Forms: // -// VANDPD xmm xmm xmm -// VANDPD m128 xmm xmm -// VANDPD ymm ymm ymm -// VANDPD m256 ymm ymm -func VANDPD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VANDPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VANDPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VANDPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VANDPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VANDPD: bad operands") +// VPUNPCKHQDQ m256 ymm ymm +// VPUNPCKHQDQ ymm ymm ymm +// VPUNPCKHQDQ m128 xmm xmm +// VPUNPCKHQDQ xmm xmm xmm +// VPUNPCKHQDQ m128 xmm k xmm +// VPUNPCKHQDQ m256 ymm k ymm +// VPUNPCKHQDQ xmm xmm k xmm +// VPUNPCKHQDQ ymm ymm k ymm +// VPUNPCKHQDQ m512 zmm k zmm +// VPUNPCKHQDQ m512 zmm zmm +// VPUNPCKHQDQ zmm zmm k zmm +// VPUNPCKHQDQ zmm zmm zmm +func VPUNPCKHQDQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPUNPCKHQDQ.Forms(), sffxs{}, ops) } -// VANDPS: Bitwise Logical AND of Packed Single-Precision Floating-Point Values. +// VPUNPCKHQDQ_BCST: Unpack and Interleave High-Order Quadwords into Double Quadwords (Broadcast). // // Forms: // -// VANDPS xmm xmm xmm -// VANDPS m128 xmm xmm -// VANDPS ymm ymm ymm -// VANDPS m256 ymm ymm -func VANDPS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VANDPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VANDPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VANDPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VANDPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VANDPS: bad operands") +// VPUNPCKHQDQ.BCST m64 xmm k xmm +// VPUNPCKHQDQ.BCST m64 xmm xmm +// VPUNPCKHQDQ.BCST m64 ymm k ymm +// VPUNPCKHQDQ.BCST m64 ymm ymm +// VPUNPCKHQDQ.BCST m64 zmm k zmm +// VPUNPCKHQDQ.BCST m64 zmm zmm +func VPUNPCKHQDQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPUNPCKHQDQ.Forms(), sffxs{sffxBCST}, ops) } -// VBLENDPD: Blend Packed Double Precision Floating-Point Values. +// VPUNPCKHQDQ_BCST_Z: Unpack and Interleave High-Order Quadwords into Double Quadwords (Broadcast, Zeroing Masking). // // Forms: // -// VBLENDPD imm8 xmm xmm xmm -// VBLENDPD imm8 m128 xmm xmm -// VBLENDPD imm8 ymm ymm ymm -// VBLENDPD imm8 m256 ymm ymm -func VBLENDPD(i, mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VBLENDPD", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VBLENDPD", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VBLENDPD", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VBLENDPD", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VBLENDPD: bad operands") +// VPUNPCKHQDQ.BCST.Z m64 xmm k xmm +// VPUNPCKHQDQ.BCST.Z m64 ymm k ymm +// VPUNPCKHQDQ.BCST.Z m64 zmm k zmm +func VPUNPCKHQDQ_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPUNPCKHQDQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// VBLENDPS: Blend Packed Single Precision Floating-Point Values. +// VPUNPCKHQDQ_Z: Unpack and Interleave High-Order Quadwords into Double Quadwords (Zeroing Masking). // // Forms: // -// VBLENDPS imm8 xmm xmm xmm -// VBLENDPS imm8 m128 xmm xmm -// VBLENDPS imm8 ymm ymm ymm -// VBLENDPS imm8 m256 ymm ymm -func VBLENDPS(i, mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VBLENDPS", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VBLENDPS", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VBLENDPS", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VBLENDPS", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VBLENDPS: bad operands") +// VPUNPCKHQDQ.Z m128 xmm k xmm +// VPUNPCKHQDQ.Z m256 ymm k ymm +// VPUNPCKHQDQ.Z xmm xmm k xmm +// VPUNPCKHQDQ.Z ymm ymm k ymm +// VPUNPCKHQDQ.Z m512 zmm k zmm +// VPUNPCKHQDQ.Z zmm zmm k zmm +func VPUNPCKHQDQ_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPUNPCKHQDQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// VBLENDVPD: Variable Blend Packed Double Precision Floating-Point Values. +// VPUNPCKHWD: Unpack and Interleave High-Order Words into Doublewords. // // Forms: // -// VBLENDVPD xmm xmm xmm xmm -// VBLENDVPD xmm m128 xmm xmm -// VBLENDVPD ymm ymm ymm ymm -// VBLENDVPD ymm m256 ymm ymm -func VBLENDVPD(xy, mxy, xy1, xy2 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(xy) && operand.IsXMM(mxy) && operand.IsXMM(xy1) && operand.IsXMM(xy2): - return &intrep.Instruction{ - Opcode: "VBLENDVPD", - Operands: []operand.Op{xy, mxy, xy1, xy2}, - Inputs: []operand.Op{xy, mxy, xy1}, - Outputs: []operand.Op{xy2}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(xy) && operand.IsM128(mxy) && operand.IsXMM(xy1) && operand.IsXMM(xy2): - return &intrep.Instruction{ - Opcode: "VBLENDVPD", - Operands: []operand.Op{xy, mxy, xy1, xy2}, - Inputs: []operand.Op{xy, mxy, xy1}, - Outputs: []operand.Op{xy2}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(xy) && operand.IsYMM(mxy) && operand.IsYMM(xy1) && operand.IsYMM(xy2): - return &intrep.Instruction{ - Opcode: "VBLENDVPD", - Operands: []operand.Op{xy, mxy, xy1, xy2}, - Inputs: []operand.Op{xy, mxy, xy1}, - Outputs: []operand.Op{xy2}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(xy) && operand.IsM256(mxy) && operand.IsYMM(xy1) && operand.IsYMM(xy2): - return &intrep.Instruction{ - Opcode: "VBLENDVPD", - Operands: []operand.Op{xy, mxy, xy1, xy2}, - Inputs: []operand.Op{xy, mxy, xy1}, - Outputs: []operand.Op{xy2}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VBLENDVPD: bad operands") +// VPUNPCKHWD m256 ymm ymm +// VPUNPCKHWD ymm ymm ymm +// VPUNPCKHWD m128 xmm xmm +// VPUNPCKHWD xmm xmm xmm +// VPUNPCKHWD m128 xmm k xmm +// VPUNPCKHWD m256 ymm k ymm +// VPUNPCKHWD xmm xmm k xmm +// VPUNPCKHWD ymm ymm k ymm +// VPUNPCKHWD m512 zmm k zmm +// VPUNPCKHWD m512 zmm zmm +// VPUNPCKHWD zmm zmm k zmm +// VPUNPCKHWD zmm zmm zmm +func VPUNPCKHWD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPUNPCKHWD.Forms(), sffxs{}, ops) } -// VBLENDVPS: Variable Blend Packed Single Precision Floating-Point Values. +// VPUNPCKHWD_Z: Unpack and Interleave High-Order Words into Doublewords (Zeroing Masking). // // Forms: // -// VBLENDVPS xmm xmm xmm xmm -// VBLENDVPS xmm m128 xmm xmm -// VBLENDVPS ymm ymm ymm ymm -// VBLENDVPS ymm m256 ymm ymm -func VBLENDVPS(xy, mxy, xy1, xy2 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(xy) && operand.IsXMM(mxy) && operand.IsXMM(xy1) && operand.IsXMM(xy2): - return &intrep.Instruction{ - Opcode: "VBLENDVPS", - Operands: []operand.Op{xy, mxy, xy1, xy2}, - Inputs: []operand.Op{xy, mxy, xy1}, - Outputs: []operand.Op{xy2}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(xy) && operand.IsM128(mxy) && operand.IsXMM(xy1) && operand.IsXMM(xy2): - return &intrep.Instruction{ - Opcode: "VBLENDVPS", - Operands: []operand.Op{xy, mxy, xy1, xy2}, - Inputs: []operand.Op{xy, mxy, xy1}, - Outputs: []operand.Op{xy2}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(xy) && operand.IsYMM(mxy) && operand.IsYMM(xy1) && operand.IsYMM(xy2): - return &intrep.Instruction{ - Opcode: "VBLENDVPS", - Operands: []operand.Op{xy, mxy, xy1, xy2}, - Inputs: []operand.Op{xy, mxy, xy1}, - Outputs: []operand.Op{xy2}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(xy) && operand.IsM256(mxy) && operand.IsYMM(xy1) && operand.IsYMM(xy2): - return &intrep.Instruction{ - Opcode: "VBLENDVPS", - Operands: []operand.Op{xy, mxy, xy1, xy2}, - Inputs: []operand.Op{xy, mxy, xy1}, - Outputs: []operand.Op{xy2}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VBLENDVPS: bad operands") +// VPUNPCKHWD.Z m128 xmm k xmm +// VPUNPCKHWD.Z m256 ymm k ymm +// VPUNPCKHWD.Z xmm xmm k xmm +// VPUNPCKHWD.Z ymm ymm k ymm +// VPUNPCKHWD.Z m512 zmm k zmm +// VPUNPCKHWD.Z zmm zmm k zmm +func VPUNPCKHWD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPUNPCKHWD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// VBROADCASTF128: Broadcast 128 Bit of Floating-Point Data. +// VPUNPCKLBW: Unpack and Interleave Low-Order Bytes into Words. // // Forms: // -// VBROADCASTF128 m128 ymm -func VBROADCASTF128(m, y operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM128(m) && operand.IsYMM(y): - return &intrep.Instruction{ - Opcode: "VBROADCASTF128", - Operands: []operand.Op{m, y}, - Inputs: []operand.Op{m}, - Outputs: []operand.Op{y}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VBROADCASTF128: bad operands") +// VPUNPCKLBW m256 ymm ymm +// VPUNPCKLBW ymm ymm ymm +// VPUNPCKLBW m128 xmm xmm +// VPUNPCKLBW xmm xmm xmm +// VPUNPCKLBW m128 xmm k xmm +// VPUNPCKLBW m256 ymm k ymm +// VPUNPCKLBW xmm xmm k xmm +// VPUNPCKLBW ymm ymm k ymm +// VPUNPCKLBW m512 zmm k zmm +// VPUNPCKLBW m512 zmm zmm +// VPUNPCKLBW zmm zmm k zmm +// VPUNPCKLBW zmm zmm zmm +func VPUNPCKLBW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPUNPCKLBW.Forms(), sffxs{}, ops) } -// VBROADCASTI128: Broadcast 128 Bits of Integer Data. +// VPUNPCKLBW_Z: Unpack and Interleave Low-Order Bytes into Words (Zeroing Masking). // // Forms: // -// VBROADCASTI128 m128 ymm -func VBROADCASTI128(m, y operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM128(m) && operand.IsYMM(y): - return &intrep.Instruction{ - Opcode: "VBROADCASTI128", - Operands: []operand.Op{m, y}, - Inputs: []operand.Op{m}, - Outputs: []operand.Op{y}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VBROADCASTI128: bad operands") +// VPUNPCKLBW.Z m128 xmm k xmm +// VPUNPCKLBW.Z m256 ymm k ymm +// VPUNPCKLBW.Z xmm xmm k xmm +// VPUNPCKLBW.Z ymm ymm k ymm +// VPUNPCKLBW.Z m512 zmm k zmm +// VPUNPCKLBW.Z zmm zmm k zmm +func VPUNPCKLBW_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPUNPCKLBW.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// VBROADCASTSD: Broadcast Double-Precision Floating-Point Element. +// VPUNPCKLDQ: Unpack and Interleave Low-Order Doublewords into Quadwords. // // Forms: // -// VBROADCASTSD xmm ymm -// VBROADCASTSD m64 ymm -func VBROADCASTSD(mx, y operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsYMM(y): - return &intrep.Instruction{ - Opcode: "VBROADCASTSD", - Operands: []operand.Op{mx, y}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{y}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM64(mx) && operand.IsYMM(y): - return &intrep.Instruction{ - Opcode: "VBROADCASTSD", - Operands: []operand.Op{mx, y}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{y}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VBROADCASTSD: bad operands") +// VPUNPCKLDQ m256 ymm ymm +// VPUNPCKLDQ ymm ymm ymm +// VPUNPCKLDQ m128 xmm xmm +// VPUNPCKLDQ xmm xmm xmm +// VPUNPCKLDQ m128 xmm k xmm +// VPUNPCKLDQ m256 ymm k ymm +// VPUNPCKLDQ xmm xmm k xmm +// VPUNPCKLDQ ymm ymm k ymm +// VPUNPCKLDQ m512 zmm k zmm +// VPUNPCKLDQ m512 zmm zmm +// VPUNPCKLDQ zmm zmm k zmm +// VPUNPCKLDQ zmm zmm zmm +func VPUNPCKLDQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPUNPCKLDQ.Forms(), sffxs{}, ops) } -// VBROADCASTSS: Broadcast Single-Precision Floating-Point Element. +// VPUNPCKLDQ_BCST: Unpack and Interleave Low-Order Doublewords into Quadwords (Broadcast). // // Forms: // -// VBROADCASTSS xmm xmm -// VBROADCASTSS m32 xmm -// VBROADCASTSS xmm ymm -// VBROADCASTSS m32 ymm -func VBROADCASTSS(mx, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VBROADCASTSS", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VBROADCASTSS", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VBROADCASTSS", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM32(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VBROADCASTSS", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VBROADCASTSS: bad operands") +// VPUNPCKLDQ.BCST m32 xmm k xmm +// VPUNPCKLDQ.BCST m32 xmm xmm +// VPUNPCKLDQ.BCST m32 ymm k ymm +// VPUNPCKLDQ.BCST m32 ymm ymm +// VPUNPCKLDQ.BCST m32 zmm k zmm +// VPUNPCKLDQ.BCST m32 zmm zmm +func VPUNPCKLDQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPUNPCKLDQ.Forms(), sffxs{sffxBCST}, ops) } -// VCMPPD: Compare Packed Double-Precision Floating-Point Values. +// VPUNPCKLDQ_BCST_Z: Unpack and Interleave Low-Order Doublewords into Quadwords (Broadcast, Zeroing Masking). // // Forms: // -// VCMPPD imm8 xmm xmm xmm -// VCMPPD imm8 m128 xmm xmm -// VCMPPD imm8 ymm ymm ymm -// VCMPPD imm8 m256 ymm ymm -func VCMPPD(i, mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VCMPPD", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VCMPPD", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VCMPPD", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VCMPPD", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VCMPPD: bad operands") +// VPUNPCKLDQ.BCST.Z m32 xmm k xmm +// VPUNPCKLDQ.BCST.Z m32 ymm k ymm +// VPUNPCKLDQ.BCST.Z m32 zmm k zmm +func VPUNPCKLDQ_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPUNPCKLDQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// VCMPPS: Compare Packed Single-Precision Floating-Point Values. +// VPUNPCKLDQ_Z: Unpack and Interleave Low-Order Doublewords into Quadwords (Zeroing Masking). // // Forms: // -// VCMPPS imm8 xmm xmm xmm -// VCMPPS imm8 m128 xmm xmm -// VCMPPS imm8 ymm ymm ymm -// VCMPPS imm8 m256 ymm ymm -func VCMPPS(i, mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VCMPPS", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VCMPPS", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VCMPPS", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VCMPPS", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VCMPPS: bad operands") +// VPUNPCKLDQ.Z m128 xmm k xmm +// VPUNPCKLDQ.Z m256 ymm k ymm +// VPUNPCKLDQ.Z xmm xmm k xmm +// VPUNPCKLDQ.Z ymm ymm k ymm +// VPUNPCKLDQ.Z m512 zmm k zmm +// VPUNPCKLDQ.Z zmm zmm k zmm +func VPUNPCKLDQ_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPUNPCKLDQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// VCMPSD: Compare Scalar Double-Precision Floating-Point Values. +// VPUNPCKLQDQ: Unpack and Interleave Low-Order Quadwords into Double Quadwords. // // Forms: // -// VCMPSD imm8 xmm xmm xmm -// VCMPSD imm8 m64 xmm xmm -func VCMPSD(i, mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VCMPSD", - Operands: []operand.Op{i, mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM64(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VCMPSD", - Operands: []operand.Op{i, mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VCMPSD: bad operands") +// VPUNPCKLQDQ m256 ymm ymm +// VPUNPCKLQDQ ymm ymm ymm +// VPUNPCKLQDQ m128 xmm xmm +// VPUNPCKLQDQ xmm xmm xmm +// VPUNPCKLQDQ m128 xmm k xmm +// VPUNPCKLQDQ m256 ymm k ymm +// VPUNPCKLQDQ xmm xmm k xmm +// VPUNPCKLQDQ ymm ymm k ymm +// VPUNPCKLQDQ m512 zmm k zmm +// VPUNPCKLQDQ m512 zmm zmm +// VPUNPCKLQDQ zmm zmm k zmm +// VPUNPCKLQDQ zmm zmm zmm +func VPUNPCKLQDQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPUNPCKLQDQ.Forms(), sffxs{}, ops) } -// VCMPSS: Compare Scalar Single-Precision Floating-Point Values. +// VPUNPCKLQDQ_BCST: Unpack and Interleave Low-Order Quadwords into Double Quadwords (Broadcast). // // Forms: // -// VCMPSS imm8 xmm xmm xmm -// VCMPSS imm8 m32 xmm xmm -func VCMPSS(i, mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VCMPSS", - Operands: []operand.Op{i, mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM32(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VCMPSS", - Operands: []operand.Op{i, mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VCMPSS: bad operands") +// VPUNPCKLQDQ.BCST m64 xmm k xmm +// VPUNPCKLQDQ.BCST m64 xmm xmm +// VPUNPCKLQDQ.BCST m64 ymm k ymm +// VPUNPCKLQDQ.BCST m64 ymm ymm +// VPUNPCKLQDQ.BCST m64 zmm k zmm +// VPUNPCKLQDQ.BCST m64 zmm zmm +func VPUNPCKLQDQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPUNPCKLQDQ.Forms(), sffxs{sffxBCST}, ops) } -// VCOMISD: Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS. +// VPUNPCKLQDQ_BCST_Z: Unpack and Interleave Low-Order Quadwords into Double Quadwords (Broadcast, Zeroing Masking). // // Forms: // -// VCOMISD xmm xmm -// VCOMISD m64 xmm -func VCOMISD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VCOMISD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VCOMISD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VCOMISD: bad operands") +// VPUNPCKLQDQ.BCST.Z m64 xmm k xmm +// VPUNPCKLQDQ.BCST.Z m64 ymm k ymm +// VPUNPCKLQDQ.BCST.Z m64 zmm k zmm +func VPUNPCKLQDQ_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPUNPCKLQDQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// VCOMISS: Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS. +// VPUNPCKLQDQ_Z: Unpack and Interleave Low-Order Quadwords into Double Quadwords (Zeroing Masking). // // Forms: // -// VCOMISS xmm xmm -// VCOMISS m32 xmm -func VCOMISS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VCOMISS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VCOMISS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VCOMISS: bad operands") +// VPUNPCKLQDQ.Z m128 xmm k xmm +// VPUNPCKLQDQ.Z m256 ymm k ymm +// VPUNPCKLQDQ.Z xmm xmm k xmm +// VPUNPCKLQDQ.Z ymm ymm k ymm +// VPUNPCKLQDQ.Z m512 zmm k zmm +// VPUNPCKLQDQ.Z zmm zmm k zmm +func VPUNPCKLQDQ_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPUNPCKLQDQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// VCVTDQ2PD: Convert Packed Dword Integers to Packed Double-Precision FP Values. +// VPUNPCKLWD: Unpack and Interleave Low-Order Words into Doublewords. // // Forms: // -// VCVTDQ2PD xmm xmm -// VCVTDQ2PD m64 xmm -// VCVTDQ2PD xmm ymm -// VCVTDQ2PD m128 ymm -func VCVTDQ2PD(mx, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VCVTDQ2PD", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VCVTDQ2PD", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VCVTDQ2PD", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VCVTDQ2PD", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VCVTDQ2PD: bad operands") +// VPUNPCKLWD m256 ymm ymm +// VPUNPCKLWD ymm ymm ymm +// VPUNPCKLWD m128 xmm xmm +// VPUNPCKLWD xmm xmm xmm +// VPUNPCKLWD m128 xmm k xmm +// VPUNPCKLWD m256 ymm k ymm +// VPUNPCKLWD xmm xmm k xmm +// VPUNPCKLWD ymm ymm k ymm +// VPUNPCKLWD m512 zmm k zmm +// VPUNPCKLWD m512 zmm zmm +// VPUNPCKLWD zmm zmm k zmm +// VPUNPCKLWD zmm zmm zmm +func VPUNPCKLWD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPUNPCKLWD.Forms(), sffxs{}, ops) } -// VCVTDQ2PS: Convert Packed Dword Integers to Packed Single-Precision FP Values. +// VPUNPCKLWD_Z: Unpack and Interleave Low-Order Words into Doublewords (Zeroing Masking). // // Forms: // -// VCVTDQ2PS xmm xmm -// VCVTDQ2PS m128 xmm -// VCVTDQ2PS ymm ymm -// VCVTDQ2PS m256 ymm -func VCVTDQ2PS(mxy, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VCVTDQ2PS", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VCVTDQ2PS", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VCVTDQ2PS", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VCVTDQ2PS", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VCVTDQ2PS: bad operands") +// VPUNPCKLWD.Z m128 xmm k xmm +// VPUNPCKLWD.Z m256 ymm k ymm +// VPUNPCKLWD.Z xmm xmm k xmm +// VPUNPCKLWD.Z ymm ymm k ymm +// VPUNPCKLWD.Z m512 zmm k zmm +// VPUNPCKLWD.Z zmm zmm k zmm +func VPUNPCKLWD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPUNPCKLWD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// VCVTPD2DQX: Convert Packed Double-Precision FP Values to Packed Dword Integers. +// VPXOR: Packed Bitwise Logical Exclusive OR. // // Forms: // -// VCVTPD2DQX xmm xmm -// VCVTPD2DQX m128 xmm -func VCVTPD2DQX(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VCVTPD2DQX", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VCVTPD2DQX", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VCVTPD2DQX: bad operands") +// VPXOR m256 ymm ymm +// VPXOR ymm ymm ymm +// VPXOR m128 xmm xmm +// VPXOR xmm xmm xmm +func VPXOR(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPXOR.Forms(), sffxs{}, []operand.Op{mxy, xy, xy1}) } -// VCVTPD2DQY: Convert Packed Double-Precision FP Values to Packed Dword Integers. +// VPXORD: Bitwise Logical Exclusive OR of Packed Doubleword Integers. // // Forms: // -// VCVTPD2DQY ymm xmm -// VCVTPD2DQY m256 xmm -func VCVTPD2DQY(my, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsYMM(my) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VCVTPD2DQY", - Operands: []operand.Op{my, x}, - Inputs: []operand.Op{my}, - Outputs: []operand.Op{x}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(my) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VCVTPD2DQY", - Operands: []operand.Op{my, x}, - Inputs: []operand.Op{my}, - Outputs: []operand.Op{x}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VCVTPD2DQY: bad operands") +// VPXORD m128 xmm k xmm +// VPXORD m128 xmm xmm +// VPXORD m256 ymm k ymm +// VPXORD m256 ymm ymm +// VPXORD xmm xmm k xmm +// VPXORD xmm xmm xmm +// VPXORD ymm ymm k ymm +// VPXORD ymm ymm ymm +// VPXORD m512 zmm k zmm +// VPXORD m512 zmm zmm +// VPXORD zmm zmm k zmm +// VPXORD zmm zmm zmm +func VPXORD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPXORD.Forms(), sffxs{}, ops) } -// VCVTPD2PSX: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values. +// VPXORD_BCST: Bitwise Logical Exclusive OR of Packed Doubleword Integers (Broadcast). // // Forms: // -// VCVTPD2PSX xmm xmm -// VCVTPD2PSX m128 xmm -func VCVTPD2PSX(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VCVTPD2PSX", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VCVTPD2PSX", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VCVTPD2PSX: bad operands") +// VPXORD.BCST m32 xmm k xmm +// VPXORD.BCST m32 xmm xmm +// VPXORD.BCST m32 ymm k ymm +// VPXORD.BCST m32 ymm ymm +// VPXORD.BCST m32 zmm k zmm +// VPXORD.BCST m32 zmm zmm +func VPXORD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPXORD.Forms(), sffxs{sffxBCST}, ops) } -// VCVTPD2PSY: Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values. +// VPXORD_BCST_Z: Bitwise Logical Exclusive OR of Packed Doubleword Integers (Broadcast, Zeroing Masking). // // Forms: // -// VCVTPD2PSY ymm xmm -// VCVTPD2PSY m256 xmm -func VCVTPD2PSY(my, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsYMM(my) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VCVTPD2PSY", - Operands: []operand.Op{my, x}, - Inputs: []operand.Op{my}, - Outputs: []operand.Op{x}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(my) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VCVTPD2PSY", - Operands: []operand.Op{my, x}, - Inputs: []operand.Op{my}, - Outputs: []operand.Op{x}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VCVTPD2PSY: bad operands") +// VPXORD.BCST.Z m32 xmm k xmm +// VPXORD.BCST.Z m32 ymm k ymm +// VPXORD.BCST.Z m32 zmm k zmm +func VPXORD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPXORD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// VCVTPH2PS: Convert Half-Precision FP Values to Single-Precision FP Values. +// VPXORD_Z: Bitwise Logical Exclusive OR of Packed Doubleword Integers (Zeroing Masking). // // Forms: // -// VCVTPH2PS xmm xmm -// VCVTPH2PS m64 xmm -// VCVTPH2PS xmm ymm -// VCVTPH2PS m128 ymm -func VCVTPH2PS(mx, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VCVTPH2PS", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"F16C"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VCVTPH2PS", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"F16C"}, - }, nil - case operand.IsXMM(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VCVTPH2PS", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"F16C"}, - }, nil - case operand.IsM128(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VCVTPH2PS", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"F16C"}, - }, nil - } - return nil, errors.New("VCVTPH2PS: bad operands") +// VPXORD.Z m128 xmm k xmm +// VPXORD.Z m256 ymm k ymm +// VPXORD.Z xmm xmm k xmm +// VPXORD.Z ymm ymm k ymm +// VPXORD.Z m512 zmm k zmm +// VPXORD.Z zmm zmm k zmm +func VPXORD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPXORD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// VCVTPS2DQ: Convert Packed Single-Precision FP Values to Packed Dword Integers. +// VPXORQ: Bitwise Logical Exclusive OR of Packed Quadword Integers. // // Forms: // -// VCVTPS2DQ xmm xmm -// VCVTPS2DQ m128 xmm -// VCVTPS2DQ ymm ymm -// VCVTPS2DQ m256 ymm -func VCVTPS2DQ(mxy, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VCVTPS2DQ", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VCVTPS2DQ", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VCVTPS2DQ", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VCVTPS2DQ", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VCVTPS2DQ: bad operands") +// VPXORQ m128 xmm k xmm +// VPXORQ m128 xmm xmm +// VPXORQ m256 ymm k ymm +// VPXORQ m256 ymm ymm +// VPXORQ xmm xmm k xmm +// VPXORQ xmm xmm xmm +// VPXORQ ymm ymm k ymm +// VPXORQ ymm ymm ymm +// VPXORQ m512 zmm k zmm +// VPXORQ m512 zmm zmm +// VPXORQ zmm zmm k zmm +// VPXORQ zmm zmm zmm +func VPXORQ(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPXORQ.Forms(), sffxs{}, ops) } -// VCVTPS2PD: Convert Packed Single-Precision FP Values to Packed Double-Precision FP Values. +// VPXORQ_BCST: Bitwise Logical Exclusive OR of Packed Quadword Integers (Broadcast). // // Forms: // -// VCVTPS2PD xmm xmm -// VCVTPS2PD m64 xmm -// VCVTPS2PD xmm ymm -// VCVTPS2PD m128 ymm -func VCVTPS2PD(mx, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VCVTPS2PD", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VCVTPS2PD", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VCVTPS2PD", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VCVTPS2PD", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VCVTPS2PD: bad operands") +// VPXORQ.BCST m64 xmm k xmm +// VPXORQ.BCST m64 xmm xmm +// VPXORQ.BCST m64 ymm k ymm +// VPXORQ.BCST m64 ymm ymm +// VPXORQ.BCST m64 zmm k zmm +// VPXORQ.BCST m64 zmm zmm +func VPXORQ_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPXORQ.Forms(), sffxs{sffxBCST}, ops) } -// VCVTPS2PH: Convert Single-Precision FP value to Half-Precision FP value. +// VPXORQ_BCST_Z: Bitwise Logical Exclusive OR of Packed Quadword Integers (Broadcast, Zeroing Masking). // // Forms: // -// VCVTPS2PH imm8 xmm xmm -// VCVTPS2PH imm8 ymm xmm -// VCVTPS2PH imm8 xmm m64 -// VCVTPS2PH imm8 ymm m128 -func VCVTPS2PH(i, xy, mx operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(xy) && operand.IsXMM(mx): - return &intrep.Instruction{ - Opcode: "VCVTPS2PH", - Operands: []operand.Op{i, xy, mx}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{mx}, - ISA: []string{"F16C"}, - }, nil - case operand.IsIMM8(i) && operand.IsYMM(xy) && operand.IsXMM(mx): - return &intrep.Instruction{ - Opcode: "VCVTPS2PH", - Operands: []operand.Op{i, xy, mx}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{mx}, - ISA: []string{"F16C"}, - }, nil - case operand.IsIMM8(i) && operand.IsXMM(xy) && operand.IsM64(mx): - return &intrep.Instruction{ - Opcode: "VCVTPS2PH", - Operands: []operand.Op{i, xy, mx}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{mx}, - ISA: []string{"F16C"}, - }, nil - case operand.IsIMM8(i) && operand.IsYMM(xy) && operand.IsM128(mx): - return &intrep.Instruction{ - Opcode: "VCVTPS2PH", - Operands: []operand.Op{i, xy, mx}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{mx}, - ISA: []string{"F16C"}, - }, nil - } - return nil, errors.New("VCVTPS2PH: bad operands") +// VPXORQ.BCST.Z m64 xmm k xmm +// VPXORQ.BCST.Z m64 ymm k ymm +// VPXORQ.BCST.Z m64 zmm k zmm +func VPXORQ_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPXORQ.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// VCVTSD2SI: Convert Scalar Double-Precision FP Value to Integer. +// VPXORQ_Z: Bitwise Logical Exclusive OR of Packed Quadword Integers (Zeroing Masking). // // Forms: // -// VCVTSD2SI xmm r32 -// VCVTSD2SI m64 r32 -func VCVTSD2SI(mx, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "VCVTSD2SI", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM64(mx) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "VCVTSD2SI", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VCVTSD2SI: bad operands") +// VPXORQ.Z m128 xmm k xmm +// VPXORQ.Z m256 ymm k ymm +// VPXORQ.Z xmm xmm k xmm +// VPXORQ.Z ymm ymm k ymm +// VPXORQ.Z m512 zmm k zmm +// VPXORQ.Z zmm zmm k zmm +func VPXORQ_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPXORQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// VCVTSD2SIQ: Convert Scalar Double-Precision FP Value to Integer. +// VRANGEPD: Range Restriction Calculation For Packed Pairs of Double-Precision Floating-Point Values. // // Forms: // -// VCVTSD2SIQ xmm r64 -// VCVTSD2SIQ m64 r64 -func VCVTSD2SIQ(mx, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "VCVTSD2SIQ", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM64(mx) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "VCVTSD2SIQ", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VCVTSD2SIQ: bad operands") +// VRANGEPD imm8 m128 xmm k xmm +// VRANGEPD imm8 m128 xmm xmm +// VRANGEPD imm8 m256 ymm k ymm +// VRANGEPD imm8 m256 ymm ymm +// VRANGEPD imm8 xmm xmm k xmm +// VRANGEPD imm8 xmm xmm xmm +// VRANGEPD imm8 ymm ymm k ymm +// VRANGEPD imm8 ymm ymm ymm +// VRANGEPD imm8 m512 zmm k zmm +// VRANGEPD imm8 m512 zmm zmm +// VRANGEPD imm8 zmm zmm k zmm +// VRANGEPD imm8 zmm zmm zmm +func VRANGEPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRANGEPD.Forms(), sffxs{}, ops) } -// VCVTSD2SS: Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value. +// VRANGEPD_BCST: Range Restriction Calculation For Packed Pairs of Double-Precision Floating-Point Values (Broadcast). // // Forms: // -// VCVTSD2SS xmm xmm xmm -// VCVTSD2SS m64 xmm xmm -func VCVTSD2SS(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VCVTSD2SS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VCVTSD2SS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VCVTSD2SS: bad operands") +// VRANGEPD.BCST imm8 m64 xmm k xmm +// VRANGEPD.BCST imm8 m64 xmm xmm +// VRANGEPD.BCST imm8 m64 ymm k ymm +// VRANGEPD.BCST imm8 m64 ymm ymm +// VRANGEPD.BCST imm8 m64 zmm k zmm +// VRANGEPD.BCST imm8 m64 zmm zmm +func VRANGEPD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRANGEPD.Forms(), sffxs{sffxBCST}, ops) } -// VCVTSI2SDL: Convert Dword Integer to Scalar Double-Precision FP Value. +// VRANGEPD_BCST_Z: Range Restriction Calculation For Packed Pairs of Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VCVTSI2SDL r32 xmm xmm -// VCVTSI2SDL m32 xmm xmm -func VCVTSI2SDL(mr, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VCVTSI2SDL", - Operands: []operand.Op{mr, x, x1}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM32(mr) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VCVTSI2SDL", - Operands: []operand.Op{mr, x, x1}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VCVTSI2SDL: bad operands") +// VRANGEPD.BCST.Z imm8 m64 xmm k xmm +// VRANGEPD.BCST.Z imm8 m64 ymm k ymm +// VRANGEPD.BCST.Z imm8 m64 zmm k zmm +func VRANGEPD_BCST_Z(i, m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVRANGEPD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{i, m, xyz, k, xyz1}) } -// VCVTSI2SDQ: Convert Dword Integer to Scalar Double-Precision FP Value. +// VRANGEPD_SAE: Range Restriction Calculation For Packed Pairs of Double-Precision Floating-Point Values (Suppress All Exceptions). // // Forms: // -// VCVTSI2SDQ r64 xmm xmm -// VCVTSI2SDQ m64 xmm xmm -func VCVTSI2SDQ(mr, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VCVTSI2SDQ", - Operands: []operand.Op{mr, x, x1}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM64(mr) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VCVTSI2SDQ", - Operands: []operand.Op{mr, x, x1}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VCVTSI2SDQ: bad operands") +// VRANGEPD.SAE imm8 zmm zmm k zmm +// VRANGEPD.SAE imm8 zmm zmm zmm +func VRANGEPD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRANGEPD.Forms(), sffxs{sffxSAE}, ops) } -// VCVTSI2SSL: Convert Dword Integer to Scalar Single-Precision FP Value. +// VRANGEPD_SAE_Z: Range Restriction Calculation For Packed Pairs of Double-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VCVTSI2SSL r32 xmm xmm -// VCVTSI2SSL m32 xmm xmm -func VCVTSI2SSL(mr, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(mr) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VCVTSI2SSL", - Operands: []operand.Op{mr, x, x1}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM32(mr) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VCVTSI2SSL", - Operands: []operand.Op{mr, x, x1}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VCVTSI2SSL: bad operands") +// VRANGEPD.SAE.Z imm8 zmm zmm k zmm +func VRANGEPD_SAE_Z(i, z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVRANGEPD.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{i, z, z1, k, z2}) } -// VCVTSI2SSQ: Convert Dword Integer to Scalar Single-Precision FP Value. +// VRANGEPD_Z: Range Restriction Calculation For Packed Pairs of Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VCVTSI2SSQ r64 xmm xmm -// VCVTSI2SSQ m64 xmm xmm -func VCVTSI2SSQ(mr, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VCVTSI2SSQ", - Operands: []operand.Op{mr, x, x1}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM64(mr) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VCVTSI2SSQ", - Operands: []operand.Op{mr, x, x1}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VCVTSI2SSQ: bad operands") +// VRANGEPD.Z imm8 m128 xmm k xmm +// VRANGEPD.Z imm8 m256 ymm k ymm +// VRANGEPD.Z imm8 xmm xmm k xmm +// VRANGEPD.Z imm8 ymm ymm k ymm +// VRANGEPD.Z imm8 m512 zmm k zmm +// VRANGEPD.Z imm8 zmm zmm k zmm +func VRANGEPD_Z(i, mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVRANGEPD.Forms(), sffxs{sffxZ}, []operand.Op{i, mxyz, xyz, k, xyz1}) } -// VCVTSS2SD: Convert Scalar Single-Precision FP Value to Scalar Double-Precision FP Value. +// VRANGEPS: Range Restriction Calculation For Packed Pairs of Single-Precision Floating-Point Values. // // Forms: // -// VCVTSS2SD xmm xmm xmm -// VCVTSS2SD m32 xmm xmm -func VCVTSS2SD(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VCVTSS2SD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VCVTSS2SD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VCVTSS2SD: bad operands") +// VRANGEPS imm8 m128 xmm k xmm +// VRANGEPS imm8 m128 xmm xmm +// VRANGEPS imm8 m256 ymm k ymm +// VRANGEPS imm8 m256 ymm ymm +// VRANGEPS imm8 xmm xmm k xmm +// VRANGEPS imm8 xmm xmm xmm +// VRANGEPS imm8 ymm ymm k ymm +// VRANGEPS imm8 ymm ymm ymm +// VRANGEPS imm8 m512 zmm k zmm +// VRANGEPS imm8 m512 zmm zmm +// VRANGEPS imm8 zmm zmm k zmm +// VRANGEPS imm8 zmm zmm zmm +func VRANGEPS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRANGEPS.Forms(), sffxs{}, ops) } -// VCVTSS2SI: Convert Scalar Single-Precision FP Value to Dword Integer. +// VRANGEPS_BCST: Range Restriction Calculation For Packed Pairs of Single-Precision Floating-Point Values (Broadcast). // // Forms: // -// VCVTSS2SI xmm r32 -// VCVTSS2SI m32 r32 -func VCVTSS2SI(mx, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "VCVTSS2SI", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM32(mx) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "VCVTSS2SI", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VCVTSS2SI: bad operands") +// VRANGEPS.BCST imm8 m32 xmm k xmm +// VRANGEPS.BCST imm8 m32 xmm xmm +// VRANGEPS.BCST imm8 m32 ymm k ymm +// VRANGEPS.BCST imm8 m32 ymm ymm +// VRANGEPS.BCST imm8 m32 zmm k zmm +// VRANGEPS.BCST imm8 m32 zmm zmm +func VRANGEPS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRANGEPS.Forms(), sffxs{sffxBCST}, ops) } -// VCVTSS2SIQ: Convert Scalar Single-Precision FP Value to Dword Integer. +// VRANGEPS_BCST_Z: Range Restriction Calculation For Packed Pairs of Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VCVTSS2SIQ xmm r64 -// VCVTSS2SIQ m32 r64 -func VCVTSS2SIQ(mx, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "VCVTSS2SIQ", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM32(mx) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "VCVTSS2SIQ", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VCVTSS2SIQ: bad operands") +// VRANGEPS.BCST.Z imm8 m32 xmm k xmm +// VRANGEPS.BCST.Z imm8 m32 ymm k ymm +// VRANGEPS.BCST.Z imm8 m32 zmm k zmm +func VRANGEPS_BCST_Z(i, m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVRANGEPS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{i, m, xyz, k, xyz1}) } -// VCVTTPD2DQX: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers. +// VRANGEPS_SAE: Range Restriction Calculation For Packed Pairs of Single-Precision Floating-Point Values (Suppress All Exceptions). // // Forms: // -// VCVTTPD2DQX xmm xmm -// VCVTTPD2DQX m128 xmm -func VCVTTPD2DQX(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VCVTTPD2DQX", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VCVTTPD2DQX", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VCVTTPD2DQX: bad operands") +// VRANGEPS.SAE imm8 zmm zmm k zmm +// VRANGEPS.SAE imm8 zmm zmm zmm +func VRANGEPS_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRANGEPS.Forms(), sffxs{sffxSAE}, ops) } -// VCVTTPD2DQY: Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers. +// VRANGEPS_SAE_Z: Range Restriction Calculation For Packed Pairs of Single-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VCVTTPD2DQY ymm xmm -// VCVTTPD2DQY m256 xmm -func VCVTTPD2DQY(my, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsYMM(my) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VCVTTPD2DQY", - Operands: []operand.Op{my, x}, - Inputs: []operand.Op{my}, - Outputs: []operand.Op{x}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(my) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VCVTTPD2DQY", - Operands: []operand.Op{my, x}, - Inputs: []operand.Op{my}, - Outputs: []operand.Op{x}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VCVTTPD2DQY: bad operands") +// VRANGEPS.SAE.Z imm8 zmm zmm k zmm +func VRANGEPS_SAE_Z(i, z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVRANGEPS.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{i, z, z1, k, z2}) } -// VCVTTPS2DQ: Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers. +// VRANGEPS_Z: Range Restriction Calculation For Packed Pairs of Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VCVTTPS2DQ xmm xmm -// VCVTTPS2DQ m128 xmm -// VCVTTPS2DQ ymm ymm -// VCVTTPS2DQ m256 ymm -func VCVTTPS2DQ(mxy, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VCVTTPS2DQ", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VCVTTPS2DQ", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VCVTTPS2DQ", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VCVTTPS2DQ", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VCVTTPS2DQ: bad operands") +// VRANGEPS.Z imm8 m128 xmm k xmm +// VRANGEPS.Z imm8 m256 ymm k ymm +// VRANGEPS.Z imm8 xmm xmm k xmm +// VRANGEPS.Z imm8 ymm ymm k ymm +// VRANGEPS.Z imm8 m512 zmm k zmm +// VRANGEPS.Z imm8 zmm zmm k zmm +func VRANGEPS_Z(i, mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVRANGEPS.Forms(), sffxs{sffxZ}, []operand.Op{i, mxyz, xyz, k, xyz1}) } -// VCVTTSD2SI: Convert with Truncation Scalar Double-Precision FP Value to Signed Integer. +// VRANGESD: Range Restriction Calculation For a pair of Scalar Double-Precision Floating-Point Values. // // Forms: // -// VCVTTSD2SI xmm r32 -// VCVTTSD2SI m64 r32 -func VCVTTSD2SI(mx, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "VCVTTSD2SI", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM64(mx) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "VCVTTSD2SI", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VCVTTSD2SI: bad operands") +// VRANGESD imm8 m64 xmm k xmm +// VRANGESD imm8 m64 xmm xmm +// VRANGESD imm8 xmm xmm k xmm +// VRANGESD imm8 xmm xmm xmm +func VRANGESD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRANGESD.Forms(), sffxs{}, ops) } -// VCVTTSD2SIQ: Convert with Truncation Scalar Double-Precision FP Value to Signed Integer. +// VRANGESD_SAE: Range Restriction Calculation For a pair of Scalar Double-Precision Floating-Point Values (Suppress All Exceptions). // // Forms: // -// VCVTTSD2SIQ xmm r64 -// VCVTTSD2SIQ m64 r64 -func VCVTTSD2SIQ(mx, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "VCVTTSD2SIQ", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM64(mx) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "VCVTTSD2SIQ", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VCVTTSD2SIQ: bad operands") +// VRANGESD.SAE imm8 xmm xmm k xmm +// VRANGESD.SAE imm8 xmm xmm xmm +func VRANGESD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRANGESD.Forms(), sffxs{sffxSAE}, ops) } -// VCVTTSS2SI: Convert with Truncation Scalar Single-Precision FP Value to Dword Integer. +// VRANGESD_SAE_Z: Range Restriction Calculation For a pair of Scalar Double-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VCVTTSS2SI xmm r32 -// VCVTTSS2SI m32 r32 -func VCVTTSS2SI(mx, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "VCVTTSS2SI", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM32(mx) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "VCVTTSS2SI", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VCVTTSS2SI: bad operands") +// VRANGESD.SAE.Z imm8 xmm xmm k xmm +func VRANGESD_SAE_Z(i, x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVRANGESD.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{i, x, x1, k, x2}) } -// VCVTTSS2SIQ: Convert with Truncation Scalar Single-Precision FP Value to Dword Integer. +// VRANGESD_Z: Range Restriction Calculation For a pair of Scalar Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VCVTTSS2SIQ xmm r64 -// VCVTTSS2SIQ m32 r64 -func VCVTTSS2SIQ(mx, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "VCVTTSS2SIQ", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM32(mx) && operand.IsR64(r): - return &intrep.Instruction{ - Opcode: "VCVTTSS2SIQ", - Operands: []operand.Op{mx, r}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{r}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VCVTTSS2SIQ: bad operands") +// VRANGESD.Z imm8 m64 xmm k xmm +// VRANGESD.Z imm8 xmm xmm k xmm +func VRANGESD_Z(i, mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVRANGESD.Forms(), sffxs{sffxZ}, []operand.Op{i, mx, x, k, x1}) } -// VDIVPD: Divide Packed Double-Precision Floating-Point Values. +// VRANGESS: Range Restriction Calculation For a pair of Scalar Single-Precision Floating-Point Values. // // Forms: // -// VDIVPD xmm xmm xmm -// VDIVPD m128 xmm xmm -// VDIVPD ymm ymm ymm -// VDIVPD m256 ymm ymm -func VDIVPD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VDIVPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VDIVPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VDIVPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VDIVPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VDIVPD: bad operands") +// VRANGESS imm8 m32 xmm k xmm +// VRANGESS imm8 m32 xmm xmm +// VRANGESS imm8 xmm xmm k xmm +// VRANGESS imm8 xmm xmm xmm +func VRANGESS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRANGESS.Forms(), sffxs{}, ops) } -// VDIVPS: Divide Packed Single-Precision Floating-Point Values. +// VRANGESS_SAE: Range Restriction Calculation For a pair of Scalar Single-Precision Floating-Point Values (Suppress All Exceptions). // // Forms: // -// VDIVPS xmm xmm xmm -// VDIVPS m128 xmm xmm -// VDIVPS ymm ymm ymm -// VDIVPS m256 ymm ymm -func VDIVPS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VDIVPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VDIVPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VDIVPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VDIVPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VDIVPS: bad operands") +// VRANGESS.SAE imm8 xmm xmm k xmm +// VRANGESS.SAE imm8 xmm xmm xmm +func VRANGESS_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRANGESS.Forms(), sffxs{sffxSAE}, ops) } -// VDIVSD: Divide Scalar Double-Precision Floating-Point Values. +// VRANGESS_SAE_Z: Range Restriction Calculation For a pair of Scalar Single-Precision Floating-Point Values (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VDIVSD xmm xmm xmm -// VDIVSD m64 xmm xmm -func VDIVSD(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VDIVSD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VDIVSD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VDIVSD: bad operands") +// VRANGESS.SAE.Z imm8 xmm xmm k xmm +func VRANGESS_SAE_Z(i, x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVRANGESS.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{i, x, x1, k, x2}) } -// VDIVSS: Divide Scalar Single-Precision Floating-Point Values. +// VRANGESS_Z: Range Restriction Calculation For a pair of Scalar Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VDIVSS xmm xmm xmm -// VDIVSS m32 xmm xmm -func VDIVSS(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VDIVSS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VDIVSS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VDIVSS: bad operands") +// VRANGESS.Z imm8 m32 xmm k xmm +// VRANGESS.Z imm8 xmm xmm k xmm +func VRANGESS_Z(i, mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVRANGESS.Forms(), sffxs{sffxZ}, []operand.Op{i, mx, x, k, x1}) } -// VDPPD: Dot Product of Packed Double Precision Floating-Point Values. +// VRCP14PD: Compute Approximate Reciprocals of Packed Double-Precision Floating-Point Values. // // Forms: // -// VDPPD imm8 xmm xmm xmm -// VDPPD imm8 m128 xmm xmm -func VDPPD(i, mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VDPPD", - Operands: []operand.Op{i, mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VDPPD", - Operands: []operand.Op{i, mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VDPPD: bad operands") +// VRCP14PD m128 k xmm +// VRCP14PD m128 xmm +// VRCP14PD m256 k ymm +// VRCP14PD m256 ymm +// VRCP14PD xmm k xmm +// VRCP14PD xmm xmm +// VRCP14PD ymm k ymm +// VRCP14PD ymm ymm +// VRCP14PD m512 k zmm +// VRCP14PD m512 zmm +// VRCP14PD zmm k zmm +// VRCP14PD zmm zmm +func VRCP14PD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP14PD.Forms(), sffxs{}, ops) } -// VDPPS: Dot Product of Packed Single Precision Floating-Point Values. +// VRCP14PD_BCST: Compute Approximate Reciprocals of Packed Double-Precision Floating-Point Values (Broadcast). // // Forms: // -// VDPPS imm8 xmm xmm xmm -// VDPPS imm8 m128 xmm xmm -// VDPPS imm8 ymm ymm ymm -// VDPPS imm8 m256 ymm ymm -func VDPPS(i, mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VDPPS", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VDPPS", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VDPPS", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VDPPS", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VDPPS: bad operands") +// VRCP14PD.BCST m64 k xmm +// VRCP14PD.BCST m64 k ymm +// VRCP14PD.BCST m64 xmm +// VRCP14PD.BCST m64 ymm +// VRCP14PD.BCST m64 k zmm +// VRCP14PD.BCST m64 zmm +func VRCP14PD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP14PD.Forms(), sffxs{sffxBCST}, ops) } -// VEXTRACTF128: Extract Packed Floating-Point Values. +// VRCP14PD_BCST_Z: Compute Approximate Reciprocals of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VEXTRACTF128 imm8 ymm xmm -// VEXTRACTF128 imm8 ymm m128 -func VEXTRACTF128(i, y, mx operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsYMM(y) && operand.IsXMM(mx): - return &intrep.Instruction{ - Opcode: "VEXTRACTF128", - Operands: []operand.Op{i, y, mx}, - Inputs: []operand.Op{y}, - Outputs: []operand.Op{mx}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsYMM(y) && operand.IsM128(mx): - return &intrep.Instruction{ - Opcode: "VEXTRACTF128", - Operands: []operand.Op{i, y, mx}, - Inputs: []operand.Op{y}, - Outputs: []operand.Op{mx}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VEXTRACTF128: bad operands") +// VRCP14PD.BCST.Z m64 k xmm +// VRCP14PD.BCST.Z m64 k ymm +// VRCP14PD.BCST.Z m64 k zmm +func VRCP14PD_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP14PD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) } -// VEXTRACTI128: Extract Packed Integer Values. +// VRCP14PD_Z: Compute Approximate Reciprocals of Packed Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VEXTRACTI128 imm8 ymm xmm -// VEXTRACTI128 imm8 ymm m128 -func VEXTRACTI128(i, y, mx operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsYMM(y) && operand.IsXMM(mx): - return &intrep.Instruction{ - Opcode: "VEXTRACTI128", - Operands: []operand.Op{i, y, mx}, - Inputs: []operand.Op{y}, - Outputs: []operand.Op{mx}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsIMM8(i) && operand.IsYMM(y) && operand.IsM128(mx): - return &intrep.Instruction{ - Opcode: "VEXTRACTI128", - Operands: []operand.Op{i, y, mx}, - Inputs: []operand.Op{y}, - Outputs: []operand.Op{mx}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VEXTRACTI128: bad operands") +// VRCP14PD.Z m128 k xmm +// VRCP14PD.Z m256 k ymm +// VRCP14PD.Z xmm k xmm +// VRCP14PD.Z ymm k ymm +// VRCP14PD.Z m512 k zmm +// VRCP14PD.Z zmm k zmm +func VRCP14PD_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP14PD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) } -// VEXTRACTPS: Extract Packed Single Precision Floating-Point Value. +// VRCP14PS: Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values. // // Forms: // -// VEXTRACTPS imm8 xmm r32 -// VEXTRACTPS imm8 xmm m32 -func VEXTRACTPS(i, x, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(x) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "VEXTRACTPS", - Operands: []operand.Op{i, x, mr}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{mr}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsXMM(x) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "VEXTRACTPS", - Operands: []operand.Op{i, x, mr}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{mr}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VEXTRACTPS: bad operands") +// VRCP14PS m128 k xmm +// VRCP14PS m128 xmm +// VRCP14PS m256 k ymm +// VRCP14PS m256 ymm +// VRCP14PS xmm k xmm +// VRCP14PS xmm xmm +// VRCP14PS ymm k ymm +// VRCP14PS ymm ymm +// VRCP14PS m512 k zmm +// VRCP14PS m512 zmm +// VRCP14PS zmm k zmm +// VRCP14PS zmm zmm +func VRCP14PS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP14PS.Forms(), sffxs{}, ops) } -// VFMADD132PD: Fused Multiply-Add of Packed Double-Precision Floating-Point Values. +// VRCP14PS_BCST: Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values (Broadcast). // // Forms: // -// VFMADD132PD xmm xmm xmm -// VFMADD132PD m128 xmm xmm -// VFMADD132PD ymm ymm ymm -// VFMADD132PD m256 ymm ymm -func VFMADD132PD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADD132PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADD132PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADD132PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADD132PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMADD132PD: bad operands") +// VRCP14PS.BCST m32 k xmm +// VRCP14PS.BCST m32 k ymm +// VRCP14PS.BCST m32 xmm +// VRCP14PS.BCST m32 ymm +// VRCP14PS.BCST m32 k zmm +// VRCP14PS.BCST m32 zmm +func VRCP14PS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP14PS.Forms(), sffxs{sffxBCST}, ops) } -// VFMADD132PS: Fused Multiply-Add of Packed Single-Precision Floating-Point Values. +// VRCP14PS_BCST_Z: Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VFMADD132PS xmm xmm xmm -// VFMADD132PS m128 xmm xmm -// VFMADD132PS ymm ymm ymm -// VFMADD132PS m256 ymm ymm -func VFMADD132PS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADD132PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADD132PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADD132PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADD132PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMADD132PS: bad operands") +// VRCP14PS.BCST.Z m32 k xmm +// VRCP14PS.BCST.Z m32 k ymm +// VRCP14PS.BCST.Z m32 k zmm +func VRCP14PS_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP14PS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) } -// VFMADD132SD: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values. +// VRCP14PS_Z: Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VFMADD132SD xmm xmm xmm -// VFMADD132SD m64 xmm xmm -func VFMADD132SD(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFMADD132SD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFMADD132SD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMADD132SD: bad operands") +// VRCP14PS.Z m128 k xmm +// VRCP14PS.Z m256 k ymm +// VRCP14PS.Z xmm k xmm +// VRCP14PS.Z ymm k ymm +// VRCP14PS.Z m512 k zmm +// VRCP14PS.Z zmm k zmm +func VRCP14PS_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP14PS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) } -// VFMADD132SS: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values. +// VRCP14SD: Compute Approximate Reciprocal of a Scalar Double-Precision Floating-Point Value. // // Forms: // -// VFMADD132SS xmm xmm xmm -// VFMADD132SS m32 xmm xmm -func VFMADD132SS(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFMADD132SS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFMADD132SS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMADD132SS: bad operands") +// VRCP14SD m64 xmm k xmm +// VRCP14SD m64 xmm xmm +// VRCP14SD xmm xmm k xmm +// VRCP14SD xmm xmm xmm +func VRCP14SD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP14SD.Forms(), sffxs{}, ops) } -// VFMADD213PD: Fused Multiply-Add of Packed Double-Precision Floating-Point Values. +// VRCP14SD_Z: Compute Approximate Reciprocal of a Scalar Double-Precision Floating-Point Value (Zeroing Masking). // // Forms: // -// VFMADD213PD xmm xmm xmm -// VFMADD213PD m128 xmm xmm -// VFMADD213PD ymm ymm ymm -// VFMADD213PD m256 ymm ymm -func VFMADD213PD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADD213PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADD213PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADD213PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADD213PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMADD213PD: bad operands") +// VRCP14SD.Z m64 xmm k xmm +// VRCP14SD.Z xmm xmm k xmm +func VRCP14SD_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP14SD.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) } -// VFMADD213PS: Fused Multiply-Add of Packed Single-Precision Floating-Point Values. +// VRCP14SS: Compute Approximate Reciprocal of a Scalar Single-Precision Floating-Point Value. // // Forms: // -// VFMADD213PS xmm xmm xmm -// VFMADD213PS m128 xmm xmm -// VFMADD213PS ymm ymm ymm -// VFMADD213PS m256 ymm ymm -func VFMADD213PS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADD213PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADD213PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADD213PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADD213PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMADD213PS: bad operands") +// VRCP14SS m32 xmm k xmm +// VRCP14SS m32 xmm xmm +// VRCP14SS xmm xmm k xmm +// VRCP14SS xmm xmm xmm +func VRCP14SS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP14SS.Forms(), sffxs{}, ops) } -// VFMADD213SD: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values. +// VRCP14SS_Z: Compute Approximate Reciprocal of a Scalar Single-Precision Floating-Point Value (Zeroing Masking). // // Forms: // -// VFMADD213SD xmm xmm xmm -// VFMADD213SD m64 xmm xmm -func VFMADD213SD(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFMADD213SD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFMADD213SD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMADD213SD: bad operands") +// VRCP14SS.Z m32 xmm k xmm +// VRCP14SS.Z xmm xmm k xmm +func VRCP14SS_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP14SS.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) } -// VFMADD213SS: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values. +// VRCP28PD: Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error. // // Forms: // -// VFMADD213SS xmm xmm xmm -// VFMADD213SS m32 xmm xmm -func VFMADD213SS(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFMADD213SS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFMADD213SS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMADD213SS: bad operands") +// VRCP28PD m512 k zmm +// VRCP28PD m512 zmm +// VRCP28PD zmm k zmm +// VRCP28PD zmm zmm +func VRCP28PD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP28PD.Forms(), sffxs{}, ops) } -// VFMADD231PD: Fused Multiply-Add of Packed Double-Precision Floating-Point Values. +// VRCP28PD_BCST: Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Broadcast). // // Forms: // -// VFMADD231PD xmm xmm xmm -// VFMADD231PD m128 xmm xmm -// VFMADD231PD ymm ymm ymm -// VFMADD231PD m256 ymm ymm -func VFMADD231PD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADD231PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADD231PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADD231PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADD231PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMADD231PD: bad operands") +// VRCP28PD.BCST m64 k zmm +// VRCP28PD.BCST m64 zmm +func VRCP28PD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP28PD.Forms(), sffxs{sffxBCST}, ops) } -// VFMADD231PS: Fused Multiply-Add of Packed Single-Precision Floating-Point Values. +// VRCP28PD_BCST_Z: Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Broadcast, Zeroing Masking). // // Forms: // -// VFMADD231PS xmm xmm xmm -// VFMADD231PS m128 xmm xmm -// VFMADD231PS ymm ymm ymm -// VFMADD231PS m256 ymm ymm -func VFMADD231PS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADD231PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADD231PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADD231PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADD231PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMADD231PS: bad operands") +// VRCP28PD.BCST.Z m64 k zmm +func VRCP28PD_BCST_Z(m, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP28PD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, z}) } -// VFMADD231SD: Fused Multiply-Add of Scalar Double-Precision Floating-Point Values. +// VRCP28PD_SAE: Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Suppress All Exceptions). // // Forms: // -// VFMADD231SD xmm xmm xmm -// VFMADD231SD m64 xmm xmm -func VFMADD231SD(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFMADD231SD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFMADD231SD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMADD231SD: bad operands") +// VRCP28PD.SAE zmm k zmm +// VRCP28PD.SAE zmm zmm +func VRCP28PD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP28PD.Forms(), sffxs{sffxSAE}, ops) } -// VFMADD231SS: Fused Multiply-Add of Scalar Single-Precision Floating-Point Values. +// VRCP28PD_SAE_Z: Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VFMADD231SS xmm xmm xmm -// VFMADD231SS m32 xmm xmm -func VFMADD231SS(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFMADD231SS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFMADD231SS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMADD231SS: bad operands") +// VRCP28PD.SAE.Z zmm k zmm +func VRCP28PD_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP28PD.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{z, k, z1}) } -// VFMADDSUB132PD: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values. +// VRCP28PD_Z: Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Zeroing Masking). // // Forms: // -// VFMADDSUB132PD xmm xmm xmm -// VFMADDSUB132PD m128 xmm xmm -// VFMADDSUB132PD ymm ymm ymm -// VFMADDSUB132PD m256 ymm ymm -func VFMADDSUB132PD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADDSUB132PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADDSUB132PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADDSUB132PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADDSUB132PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMADDSUB132PD: bad operands") +// VRCP28PD.Z m512 k zmm +// VRCP28PD.Z zmm k zmm +func VRCP28PD_Z(mz, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP28PD.Forms(), sffxs{sffxZ}, []operand.Op{mz, k, z}) } -// VFMADDSUB132PS: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values. +// VRCP28PS: Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error. // // Forms: // -// VFMADDSUB132PS xmm xmm xmm -// VFMADDSUB132PS m128 xmm xmm -// VFMADDSUB132PS ymm ymm ymm -// VFMADDSUB132PS m256 ymm ymm -func VFMADDSUB132PS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADDSUB132PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADDSUB132PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADDSUB132PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADDSUB132PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMADDSUB132PS: bad operands") +// VRCP28PS m512 k zmm +// VRCP28PS m512 zmm +// VRCP28PS zmm k zmm +// VRCP28PS zmm zmm +func VRCP28PS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP28PS.Forms(), sffxs{}, ops) } -// VFMADDSUB213PD: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values. +// VRCP28PS_BCST: Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Broadcast). // // Forms: // -// VFMADDSUB213PD xmm xmm xmm -// VFMADDSUB213PD m128 xmm xmm -// VFMADDSUB213PD ymm ymm ymm -// VFMADDSUB213PD m256 ymm ymm -func VFMADDSUB213PD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADDSUB213PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADDSUB213PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADDSUB213PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADDSUB213PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMADDSUB213PD: bad operands") +// VRCP28PS.BCST m32 k zmm +// VRCP28PS.BCST m32 zmm +func VRCP28PS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP28PS.Forms(), sffxs{sffxBCST}, ops) } -// VFMADDSUB213PS: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values. +// VRCP28PS_BCST_Z: Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Broadcast, Zeroing Masking). // // Forms: // -// VFMADDSUB213PS xmm xmm xmm -// VFMADDSUB213PS m128 xmm xmm -// VFMADDSUB213PS ymm ymm ymm -// VFMADDSUB213PS m256 ymm ymm -func VFMADDSUB213PS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADDSUB213PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADDSUB213PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADDSUB213PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADDSUB213PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMADDSUB213PS: bad operands") +// VRCP28PS.BCST.Z m32 k zmm +func VRCP28PS_BCST_Z(m, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP28PS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, z}) } -// VFMADDSUB231PD: Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values. +// VRCP28PS_SAE: Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Suppress All Exceptions). // // Forms: // -// VFMADDSUB231PD xmm xmm xmm -// VFMADDSUB231PD m128 xmm xmm -// VFMADDSUB231PD ymm ymm ymm -// VFMADDSUB231PD m256 ymm ymm -func VFMADDSUB231PD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADDSUB231PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADDSUB231PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADDSUB231PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADDSUB231PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMADDSUB231PD: bad operands") +// VRCP28PS.SAE zmm k zmm +// VRCP28PS.SAE zmm zmm +func VRCP28PS_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP28PS.Forms(), sffxs{sffxSAE}, ops) } -// VFMADDSUB231PS: Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values. +// VRCP28PS_SAE_Z: Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VFMADDSUB231PS xmm xmm xmm -// VFMADDSUB231PS m128 xmm xmm -// VFMADDSUB231PS ymm ymm ymm -// VFMADDSUB231PS m256 ymm ymm -func VFMADDSUB231PS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADDSUB231PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADDSUB231PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADDSUB231PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMADDSUB231PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMADDSUB231PS: bad operands") +// VRCP28PS.SAE.Z zmm k zmm +func VRCP28PS_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP28PS.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{z, k, z1}) } -// VFMSUB132PD: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// VRCP28PS_Z: Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Zeroing Masking). // // Forms: // -// VFMSUB132PD xmm xmm xmm -// VFMSUB132PD m128 xmm xmm -// VFMSUB132PD ymm ymm ymm -// VFMSUB132PD m256 ymm ymm -func VFMSUB132PD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUB132PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUB132PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUB132PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUB132PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMSUB132PD: bad operands") +// VRCP28PS.Z m512 k zmm +// VRCP28PS.Z zmm k zmm +func VRCP28PS_Z(mz, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP28PS.Forms(), sffxs{sffxZ}, []operand.Op{mz, k, z}) } -// VFMSUB132PS: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// VRCP28SD: Approximation to the Reciprocal of a Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error. // // Forms: // -// VFMSUB132PS xmm xmm xmm -// VFMSUB132PS m128 xmm xmm -// VFMSUB132PS ymm ymm ymm -// VFMSUB132PS m256 ymm ymm -func VFMSUB132PS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUB132PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUB132PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUB132PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUB132PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMSUB132PS: bad operands") +// VRCP28SD m64 xmm k xmm +// VRCP28SD m64 xmm xmm +// VRCP28SD xmm xmm k xmm +// VRCP28SD xmm xmm xmm +func VRCP28SD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP28SD.Forms(), sffxs{}, ops) } -// VFMSUB132SD: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// VRCP28SD_SAE: Approximation to the Reciprocal of a Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Suppress All Exceptions). // // Forms: // -// VFMSUB132SD xmm xmm xmm -// VFMSUB132SD m64 xmm xmm -func VFMSUB132SD(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFMSUB132SD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFMSUB132SD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMSUB132SD: bad operands") +// VRCP28SD.SAE xmm xmm k xmm +// VRCP28SD.SAE xmm xmm xmm +func VRCP28SD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP28SD.Forms(), sffxs{sffxSAE}, ops) } -// VFMSUB132SS: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// VRCP28SD_SAE_Z: Approximation to the Reciprocal of a Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VFMSUB132SS xmm xmm xmm -// VFMSUB132SS m32 xmm xmm -func VFMSUB132SS(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFMSUB132SS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFMSUB132SS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMSUB132SS: bad operands") +// VRCP28SD.SAE.Z xmm xmm k xmm +func VRCP28SD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP28SD.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{x, x1, k, x2}) } -// VFMSUB213PD: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// VRCP28SD_Z: Approximation to the Reciprocal of a Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Zeroing Masking). // // Forms: // -// VFMSUB213PD xmm xmm xmm -// VFMSUB213PD m128 xmm xmm -// VFMSUB213PD ymm ymm ymm -// VFMSUB213PD m256 ymm ymm -func VFMSUB213PD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUB213PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUB213PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUB213PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUB213PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMSUB213PD: bad operands") +// VRCP28SD.Z m64 xmm k xmm +// VRCP28SD.Z xmm xmm k xmm +func VRCP28SD_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP28SD.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) } -// VFMSUB213PS: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// VRCP28SS: Approximation to the Reciprocal of a Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error. // // Forms: // -// VFMSUB213PS xmm xmm xmm -// VFMSUB213PS m128 xmm xmm -// VFMSUB213PS ymm ymm ymm -// VFMSUB213PS m256 ymm ymm -func VFMSUB213PS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUB213PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUB213PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUB213PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUB213PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMSUB213PS: bad operands") +// VRCP28SS m32 xmm k xmm +// VRCP28SS m32 xmm xmm +// VRCP28SS xmm xmm k xmm +// VRCP28SS xmm xmm xmm +func VRCP28SS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP28SS.Forms(), sffxs{}, ops) } -// VFMSUB213SD: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// VRCP28SS_SAE: Approximation to the Reciprocal of a Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Suppress All Exceptions). // // Forms: // -// VFMSUB213SD xmm xmm xmm -// VFMSUB213SD m64 xmm xmm -func VFMSUB213SD(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFMSUB213SD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFMSUB213SD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMSUB213SD: bad operands") +// VRCP28SS.SAE xmm xmm k xmm +// VRCP28SS.SAE xmm xmm xmm +func VRCP28SS_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP28SS.Forms(), sffxs{sffxSAE}, ops) } -// VFMSUB213SS: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// VRCP28SS_SAE_Z: Approximation to the Reciprocal of a Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VFMSUB213SS xmm xmm xmm -// VFMSUB213SS m32 xmm xmm -func VFMSUB213SS(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFMSUB213SS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFMSUB213SS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMSUB213SS: bad operands") +// VRCP28SS.SAE.Z xmm xmm k xmm +func VRCP28SS_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP28SS.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{x, x1, k, x2}) } -// VFMSUB231PD: Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// VRCP28SS_Z: Approximation to the Reciprocal of a Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Zeroing Masking). // // Forms: // -// VFMSUB231PD xmm xmm xmm -// VFMSUB231PD m128 xmm xmm -// VFMSUB231PD ymm ymm ymm -// VFMSUB231PD m256 ymm ymm -func VFMSUB231PD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUB231PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUB231PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUB231PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUB231PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMSUB231PD: bad operands") +// VRCP28SS.Z m32 xmm k xmm +// VRCP28SS.Z xmm xmm k xmm +func VRCP28SS_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVRCP28SS.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) } -// VFMSUB231PS: Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// VRCPPS: Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values. // // Forms: // -// VFMSUB231PS xmm xmm xmm -// VFMSUB231PS m128 xmm xmm -// VFMSUB231PS ymm ymm ymm -// VFMSUB231PS m256 ymm ymm -func VFMSUB231PS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUB231PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUB231PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUB231PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUB231PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMSUB231PS: bad operands") +// VRCPPS m128 xmm +// VRCPPS m256 ymm +// VRCPPS xmm xmm +// VRCPPS ymm ymm +func VRCPPS(mxy, xy operand.Op) (*intrep.Instruction, error) { + return build(opcVRCPPS.Forms(), sffxs{}, []operand.Op{mxy, xy}) } -// VFMSUB231SD: Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// VRCPSS: Compute Approximate Reciprocal of Scalar Single-Precision Floating-Point Values. // // Forms: // -// VFMSUB231SD xmm xmm xmm -// VFMSUB231SD m64 xmm xmm -func VFMSUB231SD(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFMSUB231SD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFMSUB231SD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMSUB231SD: bad operands") +// VRCPSS m32 xmm xmm +// VRCPSS xmm xmm xmm +func VRCPSS(mx, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVRCPSS.Forms(), sffxs{}, []operand.Op{mx, x, x1}) } -// VFMSUB231SS: Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// VREDUCEPD: Perform Reduction Transformation on Packed Double-Precision Floating-Point Values. // // Forms: // -// VFMSUB231SS xmm xmm xmm -// VFMSUB231SS m32 xmm xmm -func VFMSUB231SS(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFMSUB231SS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFMSUB231SS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMSUB231SS: bad operands") +// VREDUCEPD imm8 m128 k xmm +// VREDUCEPD imm8 m128 xmm +// VREDUCEPD imm8 m256 k ymm +// VREDUCEPD imm8 m256 ymm +// VREDUCEPD imm8 xmm k xmm +// VREDUCEPD imm8 xmm xmm +// VREDUCEPD imm8 ymm k ymm +// VREDUCEPD imm8 ymm ymm +// VREDUCEPD imm8 m512 k zmm +// VREDUCEPD imm8 m512 zmm +// VREDUCEPD imm8 zmm k zmm +// VREDUCEPD imm8 zmm zmm +func VREDUCEPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVREDUCEPD.Forms(), sffxs{}, ops) } -// VFMSUBADD132PD: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values. +// VREDUCEPD_BCST: Perform Reduction Transformation on Packed Double-Precision Floating-Point Values (Broadcast). // // Forms: // -// VFMSUBADD132PD xmm xmm xmm -// VFMSUBADD132PD m128 xmm xmm -// VFMSUBADD132PD ymm ymm ymm -// VFMSUBADD132PD m256 ymm ymm -func VFMSUBADD132PD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUBADD132PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUBADD132PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUBADD132PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUBADD132PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMSUBADD132PD: bad operands") +// VREDUCEPD.BCST imm8 m64 k xmm +// VREDUCEPD.BCST imm8 m64 k ymm +// VREDUCEPD.BCST imm8 m64 xmm +// VREDUCEPD.BCST imm8 m64 ymm +// VREDUCEPD.BCST imm8 m64 k zmm +// VREDUCEPD.BCST imm8 m64 zmm +func VREDUCEPD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVREDUCEPD.Forms(), sffxs{sffxBCST}, ops) } -// VFMSUBADD132PS: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values. +// VREDUCEPD_BCST_Z: Perform Reduction Transformation on Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VFMSUBADD132PS xmm xmm xmm -// VFMSUBADD132PS m128 xmm xmm -// VFMSUBADD132PS ymm ymm ymm -// VFMSUBADD132PS m256 ymm ymm -func VFMSUBADD132PS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUBADD132PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUBADD132PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUBADD132PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUBADD132PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMSUBADD132PS: bad operands") +// VREDUCEPD.BCST.Z imm8 m64 k xmm +// VREDUCEPD.BCST.Z imm8 m64 k ymm +// VREDUCEPD.BCST.Z imm8 m64 k zmm +func VREDUCEPD_BCST_Z(i, m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVREDUCEPD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{i, m, k, xyz}) } -// VFMSUBADD213PD: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values. +// VREDUCEPD_Z: Perform Reduction Transformation on Packed Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VFMSUBADD213PD xmm xmm xmm -// VFMSUBADD213PD m128 xmm xmm -// VFMSUBADD213PD ymm ymm ymm -// VFMSUBADD213PD m256 ymm ymm -func VFMSUBADD213PD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUBADD213PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUBADD213PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUBADD213PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUBADD213PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMSUBADD213PD: bad operands") +// VREDUCEPD.Z imm8 m128 k xmm +// VREDUCEPD.Z imm8 m256 k ymm +// VREDUCEPD.Z imm8 xmm k xmm +// VREDUCEPD.Z imm8 ymm k ymm +// VREDUCEPD.Z imm8 m512 k zmm +// VREDUCEPD.Z imm8 zmm k zmm +func VREDUCEPD_Z(i, mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVREDUCEPD.Forms(), sffxs{sffxZ}, []operand.Op{i, mxyz, k, xyz}) } -// VFMSUBADD213PS: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values. +// VREDUCEPS: Perform Reduction Transformation on Packed Single-Precision Floating-Point Values. // // Forms: // -// VFMSUBADD213PS xmm xmm xmm -// VFMSUBADD213PS m128 xmm xmm -// VFMSUBADD213PS ymm ymm ymm -// VFMSUBADD213PS m256 ymm ymm -func VFMSUBADD213PS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUBADD213PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUBADD213PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUBADD213PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUBADD213PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMSUBADD213PS: bad operands") +// VREDUCEPS imm8 m128 k xmm +// VREDUCEPS imm8 m128 xmm +// VREDUCEPS imm8 m256 k ymm +// VREDUCEPS imm8 m256 ymm +// VREDUCEPS imm8 xmm k xmm +// VREDUCEPS imm8 xmm xmm +// VREDUCEPS imm8 ymm k ymm +// VREDUCEPS imm8 ymm ymm +// VREDUCEPS imm8 m512 k zmm +// VREDUCEPS imm8 m512 zmm +// VREDUCEPS imm8 zmm k zmm +// VREDUCEPS imm8 zmm zmm +func VREDUCEPS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVREDUCEPS.Forms(), sffxs{}, ops) } -// VFMSUBADD231PD: Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values. +// VREDUCEPS_BCST: Perform Reduction Transformation on Packed Single-Precision Floating-Point Values (Broadcast). // // Forms: // -// VFMSUBADD231PD xmm xmm xmm -// VFMSUBADD231PD m128 xmm xmm -// VFMSUBADD231PD ymm ymm ymm -// VFMSUBADD231PD m256 ymm ymm -func VFMSUBADD231PD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUBADD231PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUBADD231PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUBADD231PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUBADD231PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMSUBADD231PD: bad operands") +// VREDUCEPS.BCST imm8 m32 k xmm +// VREDUCEPS.BCST imm8 m32 k ymm +// VREDUCEPS.BCST imm8 m32 xmm +// VREDUCEPS.BCST imm8 m32 ymm +// VREDUCEPS.BCST imm8 m32 k zmm +// VREDUCEPS.BCST imm8 m32 zmm +func VREDUCEPS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVREDUCEPS.Forms(), sffxs{sffxBCST}, ops) } -// VFMSUBADD231PS: Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values. +// VREDUCEPS_BCST_Z: Perform Reduction Transformation on Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VFMSUBADD231PS xmm xmm xmm -// VFMSUBADD231PS m128 xmm xmm -// VFMSUBADD231PS ymm ymm ymm -// VFMSUBADD231PS m256 ymm ymm -func VFMSUBADD231PS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUBADD231PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUBADD231PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUBADD231PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFMSUBADD231PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFMSUBADD231PS: bad operands") +// VREDUCEPS.BCST.Z imm8 m32 k xmm +// VREDUCEPS.BCST.Z imm8 m32 k ymm +// VREDUCEPS.BCST.Z imm8 m32 k zmm +func VREDUCEPS_BCST_Z(i, m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVREDUCEPS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{i, m, k, xyz}) } -// VFNMADD132PD: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values. +// VREDUCEPS_Z: Perform Reduction Transformation on Packed Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VFNMADD132PD xmm xmm xmm -// VFNMADD132PD m128 xmm xmm -// VFNMADD132PD ymm ymm ymm -// VFNMADD132PD m256 ymm ymm -func VFNMADD132PD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMADD132PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMADD132PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMADD132PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMADD132PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFNMADD132PD: bad operands") +// VREDUCEPS.Z imm8 m128 k xmm +// VREDUCEPS.Z imm8 m256 k ymm +// VREDUCEPS.Z imm8 xmm k xmm +// VREDUCEPS.Z imm8 ymm k ymm +// VREDUCEPS.Z imm8 m512 k zmm +// VREDUCEPS.Z imm8 zmm k zmm +func VREDUCEPS_Z(i, mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVREDUCEPS.Forms(), sffxs{sffxZ}, []operand.Op{i, mxyz, k, xyz}) } -// VFNMADD132PS: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values. +// VREDUCESD: Perform Reduction Transformation on a Scalar Double-Precision Floating-Point Value. // // Forms: // -// VFNMADD132PS xmm xmm xmm -// VFNMADD132PS m128 xmm xmm -// VFNMADD132PS ymm ymm ymm -// VFNMADD132PS m256 ymm ymm -func VFNMADD132PS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMADD132PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMADD132PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMADD132PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMADD132PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFNMADD132PS: bad operands") +// VREDUCESD imm8 m64 xmm k xmm +// VREDUCESD imm8 m64 xmm xmm +// VREDUCESD imm8 xmm xmm k xmm +// VREDUCESD imm8 xmm xmm xmm +func VREDUCESD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVREDUCESD.Forms(), sffxs{}, ops) } -// VFNMADD132SD: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values. +// VREDUCESD_Z: Perform Reduction Transformation on a Scalar Double-Precision Floating-Point Value (Zeroing Masking). // // Forms: // -// VFNMADD132SD xmm xmm xmm -// VFNMADD132SD m64 xmm xmm -func VFNMADD132SD(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFNMADD132SD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFNMADD132SD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFNMADD132SD: bad operands") +// VREDUCESD.Z imm8 m64 xmm k xmm +// VREDUCESD.Z imm8 xmm xmm k xmm +func VREDUCESD_Z(i, mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVREDUCESD.Forms(), sffxs{sffxZ}, []operand.Op{i, mx, x, k, x1}) } -// VFNMADD132SS: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values. +// VREDUCESS: Perform Reduction Transformation on a Scalar Single-Precision Floating-Point Value. // // Forms: // -// VFNMADD132SS xmm xmm xmm -// VFNMADD132SS m32 xmm xmm -func VFNMADD132SS(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFNMADD132SS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFNMADD132SS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFNMADD132SS: bad operands") +// VREDUCESS imm8 m32 xmm k xmm +// VREDUCESS imm8 m32 xmm xmm +// VREDUCESS imm8 xmm xmm k xmm +// VREDUCESS imm8 xmm xmm xmm +func VREDUCESS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVREDUCESS.Forms(), sffxs{}, ops) } -// VFNMADD213PD: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values. +// VREDUCESS_Z: Perform Reduction Transformation on a Scalar Single-Precision Floating-Point Value (Zeroing Masking). // // Forms: // -// VFNMADD213PD xmm xmm xmm -// VFNMADD213PD m128 xmm xmm -// VFNMADD213PD ymm ymm ymm -// VFNMADD213PD m256 ymm ymm -func VFNMADD213PD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMADD213PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMADD213PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMADD213PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMADD213PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFNMADD213PD: bad operands") +// VREDUCESS.Z imm8 m32 xmm k xmm +// VREDUCESS.Z imm8 xmm xmm k xmm +func VREDUCESS_Z(i, mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVREDUCESS.Forms(), sffxs{sffxZ}, []operand.Op{i, mx, x, k, x1}) } -// VFNMADD213PS: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values. +// VRNDSCALEPD: Round Packed Double-Precision Floating-Point Values To Include A Given Number Of Fraction Bits. // // Forms: // -// VFNMADD213PS xmm xmm xmm -// VFNMADD213PS m128 xmm xmm -// VFNMADD213PS ymm ymm ymm -// VFNMADD213PS m256 ymm ymm -func VFNMADD213PS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMADD213PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMADD213PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMADD213PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMADD213PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFNMADD213PS: bad operands") +// VRNDSCALEPD imm8 m128 k xmm +// VRNDSCALEPD imm8 m128 xmm +// VRNDSCALEPD imm8 m256 k ymm +// VRNDSCALEPD imm8 m256 ymm +// VRNDSCALEPD imm8 xmm k xmm +// VRNDSCALEPD imm8 xmm xmm +// VRNDSCALEPD imm8 ymm k ymm +// VRNDSCALEPD imm8 ymm ymm +// VRNDSCALEPD imm8 m512 k zmm +// VRNDSCALEPD imm8 m512 zmm +// VRNDSCALEPD imm8 zmm k zmm +// VRNDSCALEPD imm8 zmm zmm +func VRNDSCALEPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRNDSCALEPD.Forms(), sffxs{}, ops) } -// VFNMADD213SD: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values. +// VRNDSCALEPD_BCST: Round Packed Double-Precision Floating-Point Values To Include A Given Number Of Fraction Bits (Broadcast). // // Forms: // -// VFNMADD213SD xmm xmm xmm -// VFNMADD213SD m64 xmm xmm -func VFNMADD213SD(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFNMADD213SD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFNMADD213SD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFNMADD213SD: bad operands") +// VRNDSCALEPD.BCST imm8 m64 k xmm +// VRNDSCALEPD.BCST imm8 m64 k ymm +// VRNDSCALEPD.BCST imm8 m64 xmm +// VRNDSCALEPD.BCST imm8 m64 ymm +// VRNDSCALEPD.BCST imm8 m64 k zmm +// VRNDSCALEPD.BCST imm8 m64 zmm +func VRNDSCALEPD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRNDSCALEPD.Forms(), sffxs{sffxBCST}, ops) } -// VFNMADD213SS: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values. +// VRNDSCALEPD_BCST_Z: Round Packed Double-Precision Floating-Point Values To Include A Given Number Of Fraction Bits (Broadcast, Zeroing Masking). // // Forms: // -// VFNMADD213SS xmm xmm xmm -// VFNMADD213SS m32 xmm xmm -func VFNMADD213SS(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFNMADD213SS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFNMADD213SS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFNMADD213SS: bad operands") +// VRNDSCALEPD.BCST.Z imm8 m64 k xmm +// VRNDSCALEPD.BCST.Z imm8 m64 k ymm +// VRNDSCALEPD.BCST.Z imm8 m64 k zmm +func VRNDSCALEPD_BCST_Z(i, m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVRNDSCALEPD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{i, m, k, xyz}) } -// VFNMADD231PD: Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values. +// VRNDSCALEPD_SAE: Round Packed Double-Precision Floating-Point Values To Include A Given Number Of Fraction Bits (Suppress All Exceptions). // // Forms: // -// VFNMADD231PD xmm xmm xmm -// VFNMADD231PD m128 xmm xmm -// VFNMADD231PD ymm ymm ymm -// VFNMADD231PD m256 ymm ymm -func VFNMADD231PD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMADD231PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMADD231PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMADD231PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMADD231PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFNMADD231PD: bad operands") +// VRNDSCALEPD.SAE imm8 zmm k zmm +// VRNDSCALEPD.SAE imm8 zmm zmm +func VRNDSCALEPD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRNDSCALEPD.Forms(), sffxs{sffxSAE}, ops) } -// VFNMADD231PS: Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values. +// VRNDSCALEPD_SAE_Z: Round Packed Double-Precision Floating-Point Values To Include A Given Number Of Fraction Bits (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VFNMADD231PS xmm xmm xmm -// VFNMADD231PS m128 xmm xmm -// VFNMADD231PS ymm ymm ymm -// VFNMADD231PS m256 ymm ymm -func VFNMADD231PS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMADD231PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMADD231PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMADD231PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMADD231PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFNMADD231PS: bad operands") +// VRNDSCALEPD.SAE.Z imm8 zmm k zmm +func VRNDSCALEPD_SAE_Z(i, z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVRNDSCALEPD.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{i, z, k, z1}) } -// VFNMADD231SD: Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values. +// VRNDSCALEPD_Z: Round Packed Double-Precision Floating-Point Values To Include A Given Number Of Fraction Bits (Zeroing Masking). // // Forms: // -// VFNMADD231SD xmm xmm xmm -// VFNMADD231SD m64 xmm xmm -func VFNMADD231SD(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFNMADD231SD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFNMADD231SD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFNMADD231SD: bad operands") +// VRNDSCALEPD.Z imm8 m128 k xmm +// VRNDSCALEPD.Z imm8 m256 k ymm +// VRNDSCALEPD.Z imm8 xmm k xmm +// VRNDSCALEPD.Z imm8 ymm k ymm +// VRNDSCALEPD.Z imm8 m512 k zmm +// VRNDSCALEPD.Z imm8 zmm k zmm +func VRNDSCALEPD_Z(i, mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVRNDSCALEPD.Forms(), sffxs{sffxZ}, []operand.Op{i, mxyz, k, xyz}) } -// VFNMADD231SS: Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values. +// VRNDSCALEPS: Round Packed Single-Precision Floating-Point Values To Include A Given Number Of Fraction Bits. // // Forms: // -// VFNMADD231SS xmm xmm xmm -// VFNMADD231SS m32 xmm xmm -func VFNMADD231SS(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFNMADD231SS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFNMADD231SS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFNMADD231SS: bad operands") +// VRNDSCALEPS imm8 m128 k xmm +// VRNDSCALEPS imm8 m128 xmm +// VRNDSCALEPS imm8 m256 k ymm +// VRNDSCALEPS imm8 m256 ymm +// VRNDSCALEPS imm8 xmm k xmm +// VRNDSCALEPS imm8 xmm xmm +// VRNDSCALEPS imm8 ymm k ymm +// VRNDSCALEPS imm8 ymm ymm +// VRNDSCALEPS imm8 m512 k zmm +// VRNDSCALEPS imm8 m512 zmm +// VRNDSCALEPS imm8 zmm k zmm +// VRNDSCALEPS imm8 zmm zmm +func VRNDSCALEPS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRNDSCALEPS.Forms(), sffxs{}, ops) } -// VFNMSUB132PD: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// VRNDSCALEPS_BCST: Round Packed Single-Precision Floating-Point Values To Include A Given Number Of Fraction Bits (Broadcast). // // Forms: // -// VFNMSUB132PD xmm xmm xmm -// VFNMSUB132PD m128 xmm xmm -// VFNMSUB132PD ymm ymm ymm -// VFNMSUB132PD m256 ymm ymm -func VFNMSUB132PD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMSUB132PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMSUB132PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMSUB132PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMSUB132PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFNMSUB132PD: bad operands") +// VRNDSCALEPS.BCST imm8 m32 k xmm +// VRNDSCALEPS.BCST imm8 m32 k ymm +// VRNDSCALEPS.BCST imm8 m32 xmm +// VRNDSCALEPS.BCST imm8 m32 ymm +// VRNDSCALEPS.BCST imm8 m32 k zmm +// VRNDSCALEPS.BCST imm8 m32 zmm +func VRNDSCALEPS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRNDSCALEPS.Forms(), sffxs{sffxBCST}, ops) } -// VFNMSUB132PS: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// VRNDSCALEPS_BCST_Z: Round Packed Single-Precision Floating-Point Values To Include A Given Number Of Fraction Bits (Broadcast, Zeroing Masking). // // Forms: // -// VFNMSUB132PS xmm xmm xmm -// VFNMSUB132PS m128 xmm xmm -// VFNMSUB132PS ymm ymm ymm -// VFNMSUB132PS m256 ymm ymm -func VFNMSUB132PS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMSUB132PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMSUB132PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMSUB132PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMSUB132PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFNMSUB132PS: bad operands") +// VRNDSCALEPS.BCST.Z imm8 m32 k xmm +// VRNDSCALEPS.BCST.Z imm8 m32 k ymm +// VRNDSCALEPS.BCST.Z imm8 m32 k zmm +func VRNDSCALEPS_BCST_Z(i, m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVRNDSCALEPS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{i, m, k, xyz}) } -// VFNMSUB132SD: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// VRNDSCALEPS_SAE: Round Packed Single-Precision Floating-Point Values To Include A Given Number Of Fraction Bits (Suppress All Exceptions). // // Forms: // -// VFNMSUB132SD xmm xmm xmm -// VFNMSUB132SD m64 xmm xmm -func VFNMSUB132SD(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFNMSUB132SD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFNMSUB132SD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFNMSUB132SD: bad operands") +// VRNDSCALEPS.SAE imm8 zmm k zmm +// VRNDSCALEPS.SAE imm8 zmm zmm +func VRNDSCALEPS_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRNDSCALEPS.Forms(), sffxs{sffxSAE}, ops) } -// VFNMSUB132SS: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// VRNDSCALEPS_SAE_Z: Round Packed Single-Precision Floating-Point Values To Include A Given Number Of Fraction Bits (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VFNMSUB132SS xmm xmm xmm -// VFNMSUB132SS m32 xmm xmm -func VFNMSUB132SS(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFNMSUB132SS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFNMSUB132SS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFNMSUB132SS: bad operands") +// VRNDSCALEPS.SAE.Z imm8 zmm k zmm +func VRNDSCALEPS_SAE_Z(i, z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVRNDSCALEPS.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{i, z, k, z1}) } -// VFNMSUB213PD: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// VRNDSCALEPS_Z: Round Packed Single-Precision Floating-Point Values To Include A Given Number Of Fraction Bits (Zeroing Masking). // // Forms: // -// VFNMSUB213PD xmm xmm xmm -// VFNMSUB213PD m128 xmm xmm -// VFNMSUB213PD ymm ymm ymm -// VFNMSUB213PD m256 ymm ymm -func VFNMSUB213PD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMSUB213PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMSUB213PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMSUB213PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMSUB213PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFNMSUB213PD: bad operands") +// VRNDSCALEPS.Z imm8 m128 k xmm +// VRNDSCALEPS.Z imm8 m256 k ymm +// VRNDSCALEPS.Z imm8 xmm k xmm +// VRNDSCALEPS.Z imm8 ymm k ymm +// VRNDSCALEPS.Z imm8 m512 k zmm +// VRNDSCALEPS.Z imm8 zmm k zmm +func VRNDSCALEPS_Z(i, mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVRNDSCALEPS.Forms(), sffxs{sffxZ}, []operand.Op{i, mxyz, k, xyz}) } -// VFNMSUB213PS: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// VRNDSCALESD: Round Scalar Double-Precision Floating-Point Value To Include A Given Number Of Fraction Bits. // // Forms: // -// VFNMSUB213PS xmm xmm xmm -// VFNMSUB213PS m128 xmm xmm -// VFNMSUB213PS ymm ymm ymm -// VFNMSUB213PS m256 ymm ymm -func VFNMSUB213PS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMSUB213PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMSUB213PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMSUB213PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMSUB213PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFNMSUB213PS: bad operands") +// VRNDSCALESD imm8 m64 xmm k xmm +// VRNDSCALESD imm8 m64 xmm xmm +// VRNDSCALESD imm8 xmm xmm k xmm +// VRNDSCALESD imm8 xmm xmm xmm +func VRNDSCALESD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRNDSCALESD.Forms(), sffxs{}, ops) } -// VFNMSUB213SD: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// VRNDSCALESD_SAE: Round Scalar Double-Precision Floating-Point Value To Include A Given Number Of Fraction Bits (Suppress All Exceptions). // // Forms: // -// VFNMSUB213SD xmm xmm xmm -// VFNMSUB213SD m64 xmm xmm -func VFNMSUB213SD(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFNMSUB213SD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFNMSUB213SD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFNMSUB213SD: bad operands") +// VRNDSCALESD.SAE imm8 xmm xmm k xmm +// VRNDSCALESD.SAE imm8 xmm xmm xmm +func VRNDSCALESD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRNDSCALESD.Forms(), sffxs{sffxSAE}, ops) } -// VFNMSUB213SS: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// VRNDSCALESD_SAE_Z: Round Scalar Double-Precision Floating-Point Value To Include A Given Number Of Fraction Bits (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VFNMSUB213SS xmm xmm xmm -// VFNMSUB213SS m32 xmm xmm -func VFNMSUB213SS(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFNMSUB213SS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFNMSUB213SS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFNMSUB213SS: bad operands") +// VRNDSCALESD.SAE.Z imm8 xmm xmm k xmm +func VRNDSCALESD_SAE_Z(i, x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVRNDSCALESD.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{i, x, x1, k, x2}) } -// VFNMSUB231PD: Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values. +// VRNDSCALESD_Z: Round Scalar Double-Precision Floating-Point Value To Include A Given Number Of Fraction Bits (Zeroing Masking). // // Forms: // -// VFNMSUB231PD xmm xmm xmm -// VFNMSUB231PD m128 xmm xmm -// VFNMSUB231PD ymm ymm ymm -// VFNMSUB231PD m256 ymm ymm -func VFNMSUB231PD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMSUB231PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMSUB231PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMSUB231PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMSUB231PD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFNMSUB231PD: bad operands") +// VRNDSCALESD.Z imm8 m64 xmm k xmm +// VRNDSCALESD.Z imm8 xmm xmm k xmm +func VRNDSCALESD_Z(i, mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVRNDSCALESD.Forms(), sffxs{sffxZ}, []operand.Op{i, mx, x, k, x1}) } -// VFNMSUB231PS: Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values. +// VRNDSCALESS: Round Scalar Single-Precision Floating-Point Value To Include A Given Number Of Fraction Bits. // // Forms: // -// VFNMSUB231PS xmm xmm xmm -// VFNMSUB231PS m128 xmm xmm -// VFNMSUB231PS ymm ymm ymm -// VFNMSUB231PS m256 ymm ymm -func VFNMSUB231PS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMSUB231PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMSUB231PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMSUB231PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VFNMSUB231PS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy, xy1}, - Outputs: []operand.Op{xy1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFNMSUB231PS: bad operands") +// VRNDSCALESS imm8 m32 xmm k xmm +// VRNDSCALESS imm8 m32 xmm xmm +// VRNDSCALESS imm8 xmm xmm k xmm +// VRNDSCALESS imm8 xmm xmm xmm +func VRNDSCALESS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRNDSCALESS.Forms(), sffxs{}, ops) } -// VFNMSUB231SD: Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values. +// VRNDSCALESS_SAE: Round Scalar Single-Precision Floating-Point Value To Include A Given Number Of Fraction Bits (Suppress All Exceptions). // // Forms: // -// VFNMSUB231SD xmm xmm xmm -// VFNMSUB231SD m64 xmm xmm -func VFNMSUB231SD(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFNMSUB231SD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFNMSUB231SD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFNMSUB231SD: bad operands") +// VRNDSCALESS.SAE imm8 xmm xmm k xmm +// VRNDSCALESS.SAE imm8 xmm xmm xmm +func VRNDSCALESS_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRNDSCALESS.Forms(), sffxs{sffxSAE}, ops) } -// VFNMSUB231SS: Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values. +// VRNDSCALESS_SAE_Z: Round Scalar Single-Precision Floating-Point Value To Include A Given Number Of Fraction Bits (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VFNMSUB231SS xmm xmm xmm -// VFNMSUB231SS m32 xmm xmm -func VFNMSUB231SS(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFNMSUB231SS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VFNMSUB231SS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x, x1}, - Outputs: []operand.Op{x1}, - ISA: []string{"FMA3"}, - }, nil - } - return nil, errors.New("VFNMSUB231SS: bad operands") +// VRNDSCALESS.SAE.Z imm8 xmm xmm k xmm +func VRNDSCALESS_SAE_Z(i, x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVRNDSCALESS.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{i, x, x1, k, x2}) } -// VGATHERDPD: Gather Packed Double-Precision Floating-Point Values Using Signed Doubleword Indices. +// VRNDSCALESS_Z: Round Scalar Single-Precision Floating-Point Value To Include A Given Number Of Fraction Bits (Zeroing Masking). // // Forms: // -// VGATHERDPD xmm vm32x xmm -// VGATHERDPD ymm vm32x ymm -func VGATHERDPD(xy, v, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(xy) && operand.IsVM32X(v) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VGATHERDPD", - Operands: []operand.Op{xy, v, xy1}, - Inputs: []operand.Op{xy, v, xy1}, - Outputs: []operand.Op{xy, xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsYMM(xy) && operand.IsVM32X(v) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VGATHERDPD", - Operands: []operand.Op{xy, v, xy1}, - Inputs: []operand.Op{xy, v, xy1}, - Outputs: []operand.Op{xy, xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VGATHERDPD: bad operands") +// VRNDSCALESS.Z imm8 m32 xmm k xmm +// VRNDSCALESS.Z imm8 xmm xmm k xmm +func VRNDSCALESS_Z(i, mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVRNDSCALESS.Forms(), sffxs{sffxZ}, []operand.Op{i, mx, x, k, x1}) } -// VGATHERDPS: Gather Packed Single-Precision Floating-Point Values Using Signed Doubleword Indices. +// VROUNDPD: Round Packed Double Precision Floating-Point Values. // // Forms: // -// VGATHERDPS xmm vm32x xmm -// VGATHERDPS ymm vm32y ymm -func VGATHERDPS(xy, v, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(xy) && operand.IsVM32X(v) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VGATHERDPS", - Operands: []operand.Op{xy, v, xy1}, - Inputs: []operand.Op{xy, v, xy1}, - Outputs: []operand.Op{xy, xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsYMM(xy) && operand.IsVM32Y(v) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VGATHERDPS", - Operands: []operand.Op{xy, v, xy1}, - Inputs: []operand.Op{xy, v, xy1}, - Outputs: []operand.Op{xy, xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VGATHERDPS: bad operands") +// VROUNDPD imm8 m128 xmm +// VROUNDPD imm8 m256 ymm +// VROUNDPD imm8 xmm xmm +// VROUNDPD imm8 ymm ymm +func VROUNDPD(i, mxy, xy operand.Op) (*intrep.Instruction, error) { + return build(opcVROUNDPD.Forms(), sffxs{}, []operand.Op{i, mxy, xy}) } -// VGATHERQPD: Gather Packed Double-Precision Floating-Point Values Using Signed Quadword Indices. +// VROUNDPS: Round Packed Single Precision Floating-Point Values. // // Forms: // -// VGATHERQPD xmm vm64x xmm -// VGATHERQPD ymm vm64y ymm -func VGATHERQPD(xy, v, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(xy) && operand.IsVM64X(v) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VGATHERQPD", - Operands: []operand.Op{xy, v, xy1}, - Inputs: []operand.Op{xy, v, xy1}, - Outputs: []operand.Op{xy, xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsYMM(xy) && operand.IsVM64Y(v) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VGATHERQPD", - Operands: []operand.Op{xy, v, xy1}, - Inputs: []operand.Op{xy, v, xy1}, - Outputs: []operand.Op{xy, xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VGATHERQPD: bad operands") +// VROUNDPS imm8 m128 xmm +// VROUNDPS imm8 m256 ymm +// VROUNDPS imm8 xmm xmm +// VROUNDPS imm8 ymm ymm +func VROUNDPS(i, mxy, xy operand.Op) (*intrep.Instruction, error) { + return build(opcVROUNDPS.Forms(), sffxs{}, []operand.Op{i, mxy, xy}) } -// VGATHERQPS: Gather Packed Single-Precision Floating-Point Values Using Signed Quadword Indices. +// VROUNDSD: Round Scalar Double Precision Floating-Point Values. // // Forms: // -// VGATHERQPS xmm vm64x xmm -// VGATHERQPS xmm vm64y xmm -func VGATHERQPS(x, v, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(x) && operand.IsVM64X(v) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VGATHERQPS", - Operands: []operand.Op{x, v, x1}, - Inputs: []operand.Op{x, v, x1}, - Outputs: []operand.Op{x, x1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsXMM(x) && operand.IsVM64Y(v) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VGATHERQPS", - Operands: []operand.Op{x, v, x1}, - Inputs: []operand.Op{x, v, x1}, - Outputs: []operand.Op{x, x1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VGATHERQPS: bad operands") +// VROUNDSD imm8 m64 xmm xmm +// VROUNDSD imm8 xmm xmm xmm +func VROUNDSD(i, mx, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVROUNDSD.Forms(), sffxs{}, []operand.Op{i, mx, x, x1}) } -// VHADDPD: Packed Double-FP Horizontal Add. +// VROUNDSS: Round Scalar Single Precision Floating-Point Values. // // Forms: // -// VHADDPD xmm xmm xmm -// VHADDPD m128 xmm xmm -// VHADDPD ymm ymm ymm -// VHADDPD m256 ymm ymm -func VHADDPD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VHADDPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VHADDPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VHADDPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VHADDPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VHADDPD: bad operands") +// VROUNDSS imm8 m32 xmm xmm +// VROUNDSS imm8 xmm xmm xmm +func VROUNDSS(i, mx, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVROUNDSS.Forms(), sffxs{}, []operand.Op{i, mx, x, x1}) } -// VHADDPS: Packed Single-FP Horizontal Add. +// VRSQRT14PD: Compute Approximate Reciprocals of Square Roots of Packed Double-Precision Floating-Point Values. // // Forms: // -// VHADDPS xmm xmm xmm -// VHADDPS m128 xmm xmm -// VHADDPS ymm ymm ymm -// VHADDPS m256 ymm ymm -func VHADDPS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VHADDPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VHADDPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VHADDPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VHADDPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VHADDPS: bad operands") +// VRSQRT14PD m128 k xmm +// VRSQRT14PD m128 xmm +// VRSQRT14PD m256 k ymm +// VRSQRT14PD m256 ymm +// VRSQRT14PD xmm k xmm +// VRSQRT14PD xmm xmm +// VRSQRT14PD ymm k ymm +// VRSQRT14PD ymm ymm +// VRSQRT14PD m512 k zmm +// VRSQRT14PD m512 zmm +// VRSQRT14PD zmm k zmm +// VRSQRT14PD zmm zmm +func VRSQRT14PD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT14PD.Forms(), sffxs{}, ops) } -// VHSUBPD: Packed Double-FP Horizontal Subtract. +// VRSQRT14PD_BCST: Compute Approximate Reciprocals of Square Roots of Packed Double-Precision Floating-Point Values (Broadcast). // // Forms: // -// VHSUBPD xmm xmm xmm -// VHSUBPD m128 xmm xmm -// VHSUBPD ymm ymm ymm -// VHSUBPD m256 ymm ymm -func VHSUBPD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VHSUBPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VHSUBPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VHSUBPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VHSUBPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VHSUBPD: bad operands") +// VRSQRT14PD.BCST m64 k xmm +// VRSQRT14PD.BCST m64 k ymm +// VRSQRT14PD.BCST m64 xmm +// VRSQRT14PD.BCST m64 ymm +// VRSQRT14PD.BCST m64 k zmm +// VRSQRT14PD.BCST m64 zmm +func VRSQRT14PD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT14PD.Forms(), sffxs{sffxBCST}, ops) } -// VHSUBPS: Packed Single-FP Horizontal Subtract. +// VRSQRT14PD_BCST_Z: Compute Approximate Reciprocals of Square Roots of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VHSUBPS xmm xmm xmm -// VHSUBPS m128 xmm xmm -// VHSUBPS ymm ymm ymm -// VHSUBPS m256 ymm ymm -func VHSUBPS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VHSUBPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VHSUBPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VHSUBPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VHSUBPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VHSUBPS: bad operands") +// VRSQRT14PD.BCST.Z m64 k xmm +// VRSQRT14PD.BCST.Z m64 k ymm +// VRSQRT14PD.BCST.Z m64 k zmm +func VRSQRT14PD_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT14PD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) } -// VINSERTF128: Insert Packed Floating-Point Values. +// VRSQRT14PD_Z: Compute Approximate Reciprocals of Square Roots of Packed Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VINSERTF128 imm8 xmm ymm ymm -// VINSERTF128 imm8 m128 ymm ymm -func VINSERTF128(i, mx, y, y1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsYMM(y) && operand.IsYMM(y1): - return &intrep.Instruction{ - Opcode: "VINSERTF128", - Operands: []operand.Op{i, mx, y, y1}, - Inputs: []operand.Op{mx, y}, - Outputs: []operand.Op{y1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mx) && operand.IsYMM(y) && operand.IsYMM(y1): - return &intrep.Instruction{ - Opcode: "VINSERTF128", - Operands: []operand.Op{i, mx, y, y1}, - Inputs: []operand.Op{mx, y}, - Outputs: []operand.Op{y1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VINSERTF128: bad operands") +// VRSQRT14PD.Z m128 k xmm +// VRSQRT14PD.Z m256 k ymm +// VRSQRT14PD.Z xmm k xmm +// VRSQRT14PD.Z ymm k ymm +// VRSQRT14PD.Z m512 k zmm +// VRSQRT14PD.Z zmm k zmm +func VRSQRT14PD_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT14PD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) } -// VINSERTI128: Insert Packed Integer Values. +// VRSQRT14PS: Compute Approximate Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values. // // Forms: // -// VINSERTI128 imm8 xmm ymm ymm -// VINSERTI128 imm8 m128 ymm ymm -func VINSERTI128(i, mx, y, y1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsYMM(y) && operand.IsYMM(y1): - return &intrep.Instruction{ - Opcode: "VINSERTI128", - Operands: []operand.Op{i, mx, y, y1}, - Inputs: []operand.Op{mx, y}, - Outputs: []operand.Op{y1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mx) && operand.IsYMM(y) && operand.IsYMM(y1): - return &intrep.Instruction{ - Opcode: "VINSERTI128", - Operands: []operand.Op{i, mx, y, y1}, - Inputs: []operand.Op{mx, y}, - Outputs: []operand.Op{y1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VINSERTI128: bad operands") +// VRSQRT14PS m128 k xmm +// VRSQRT14PS m128 xmm +// VRSQRT14PS m256 k ymm +// VRSQRT14PS m256 ymm +// VRSQRT14PS xmm k xmm +// VRSQRT14PS xmm xmm +// VRSQRT14PS ymm k ymm +// VRSQRT14PS ymm ymm +// VRSQRT14PS m512 k zmm +// VRSQRT14PS m512 zmm +// VRSQRT14PS zmm k zmm +// VRSQRT14PS zmm zmm +func VRSQRT14PS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT14PS.Forms(), sffxs{}, ops) } -// VINSERTPS: Insert Packed Single Precision Floating-Point Value. +// VRSQRT14PS_BCST: Compute Approximate Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values (Broadcast). // // Forms: // -// VINSERTPS imm8 xmm xmm xmm -// VINSERTPS imm8 m32 xmm xmm -func VINSERTPS(i, mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VINSERTPS", - Operands: []operand.Op{i, mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM32(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VINSERTPS", - Operands: []operand.Op{i, mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VINSERTPS: bad operands") +// VRSQRT14PS.BCST m32 k xmm +// VRSQRT14PS.BCST m32 k ymm +// VRSQRT14PS.BCST m32 xmm +// VRSQRT14PS.BCST m32 ymm +// VRSQRT14PS.BCST m32 k zmm +// VRSQRT14PS.BCST m32 zmm +func VRSQRT14PS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT14PS.Forms(), sffxs{sffxBCST}, ops) } -// VLDDQU: Load Unaligned Integer 128 Bits. +// VRSQRT14PS_BCST_Z: Compute Approximate Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VLDDQU m128 xmm -// VLDDQU m256 ymm -func VLDDQU(m, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM128(m) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VLDDQU", - Operands: []operand.Op{m, xy}, - Inputs: []operand.Op{m}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(m) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VLDDQU", - Operands: []operand.Op{m, xy}, - Inputs: []operand.Op{m}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VLDDQU: bad operands") +// VRSQRT14PS.BCST.Z m32 k xmm +// VRSQRT14PS.BCST.Z m32 k ymm +// VRSQRT14PS.BCST.Z m32 k zmm +func VRSQRT14PS_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT14PS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) } -// VLDMXCSR: Load MXCSR Register. +// VRSQRT14PS_Z: Compute Approximate Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VLDMXCSR m32 -func VLDMXCSR(m operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM32(m): - return &intrep.Instruction{ - Opcode: "VLDMXCSR", - Operands: []operand.Op{m}, - Inputs: []operand.Op{m}, - Outputs: []operand.Op{}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VLDMXCSR: bad operands") +// VRSQRT14PS.Z m128 k xmm +// VRSQRT14PS.Z m256 k ymm +// VRSQRT14PS.Z xmm k xmm +// VRSQRT14PS.Z ymm k ymm +// VRSQRT14PS.Z m512 k zmm +// VRSQRT14PS.Z zmm k zmm +func VRSQRT14PS_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT14PS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) } -// VMASKMOVDQU: Store Selected Bytes of Double Quadword. +// VRSQRT14SD: Compute Approximate Reciprocal of a Square Root of a Scalar Double-Precision Floating-Point Value. // // Forms: // -// VMASKMOVDQU xmm xmm -func VMASKMOVDQU(x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VMASKMOVDQU", - Operands: []operand.Op{x, x1}, - Inputs: []operand.Op{x, x1, reg.RDI}, - Outputs: []operand.Op{}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMASKMOVDQU: bad operands") +// VRSQRT14SD m64 xmm k xmm +// VRSQRT14SD m64 xmm xmm +// VRSQRT14SD xmm xmm k xmm +// VRSQRT14SD xmm xmm xmm +func VRSQRT14SD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT14SD.Forms(), sffxs{}, ops) } -// VMASKMOVPD: Conditional Move Packed Double-Precision Floating-Point Values. +// VRSQRT14SD_Z: Compute Approximate Reciprocal of a Square Root of a Scalar Double-Precision Floating-Point Value (Zeroing Masking). // // Forms: // -// VMASKMOVPD m128 xmm xmm -// VMASKMOVPD m256 ymm ymm -// VMASKMOVPD xmm xmm m128 -// VMASKMOVPD ymm ymm m256 -func VMASKMOVPD(mxy, xy, mxy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(mxy1): - return &intrep.Instruction{ - Opcode: "VMASKMOVPD", - Operands: []operand.Op{mxy, xy, mxy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(mxy1): - return &intrep.Instruction{ - Opcode: "VMASKMOVPD", - Operands: []operand.Op{mxy, xy, mxy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsM128(mxy1): - return &intrep.Instruction{ - Opcode: "VMASKMOVPD", - Operands: []operand.Op{mxy, xy, mxy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsM256(mxy1): - return &intrep.Instruction{ - Opcode: "VMASKMOVPD", - Operands: []operand.Op{mxy, xy, mxy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMASKMOVPD: bad operands") +// VRSQRT14SD.Z m64 xmm k xmm +// VRSQRT14SD.Z xmm xmm k xmm +func VRSQRT14SD_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT14SD.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) } -// VMASKMOVPS: Conditional Move Packed Single-Precision Floating-Point Values. +// VRSQRT14SS: Compute Approximate Reciprocal of a Square Root of a Scalar Single-Precision Floating-Point Value. // // Forms: // -// VMASKMOVPS m128 xmm xmm -// VMASKMOVPS m256 ymm ymm -// VMASKMOVPS xmm xmm m128 -// VMASKMOVPS ymm ymm m256 -func VMASKMOVPS(mxy, xy, mxy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(mxy1): - return &intrep.Instruction{ - Opcode: "VMASKMOVPS", - Operands: []operand.Op{mxy, xy, mxy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(mxy1): - return &intrep.Instruction{ - Opcode: "VMASKMOVPS", - Operands: []operand.Op{mxy, xy, mxy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsM128(mxy1): - return &intrep.Instruction{ - Opcode: "VMASKMOVPS", - Operands: []operand.Op{mxy, xy, mxy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsM256(mxy1): - return &intrep.Instruction{ - Opcode: "VMASKMOVPS", - Operands: []operand.Op{mxy, xy, mxy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMASKMOVPS: bad operands") +// VRSQRT14SS m32 xmm k xmm +// VRSQRT14SS m32 xmm xmm +// VRSQRT14SS xmm xmm k xmm +// VRSQRT14SS xmm xmm xmm +func VRSQRT14SS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT14SS.Forms(), sffxs{}, ops) } -// VMAXPD: Return Maximum Packed Double-Precision Floating-Point Values. +// VRSQRT14SS_Z: Compute Approximate Reciprocal of a Square Root of a Scalar Single-Precision Floating-Point Value (Zeroing Masking). // // Forms: // -// VMAXPD xmm xmm xmm -// VMAXPD m128 xmm xmm -// VMAXPD ymm ymm ymm -// VMAXPD m256 ymm ymm -func VMAXPD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VMAXPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VMAXPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VMAXPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VMAXPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMAXPD: bad operands") +// VRSQRT14SS.Z m32 xmm k xmm +// VRSQRT14SS.Z xmm xmm k xmm +func VRSQRT14SS_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT14SS.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) } -// VMAXPS: Return Maximum Packed Single-Precision Floating-Point Values. +// VRSQRT28PD: Approximation to the Reciprocal Square Root of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error. // // Forms: // -// VMAXPS xmm xmm xmm -// VMAXPS m128 xmm xmm -// VMAXPS ymm ymm ymm -// VMAXPS m256 ymm ymm -func VMAXPS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VMAXPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VMAXPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VMAXPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VMAXPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMAXPS: bad operands") +// VRSQRT28PD m512 k zmm +// VRSQRT28PD m512 zmm +// VRSQRT28PD zmm k zmm +// VRSQRT28PD zmm zmm +func VRSQRT28PD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT28PD.Forms(), sffxs{}, ops) } -// VMAXSD: Return Maximum Scalar Double-Precision Floating-Point Value. +// VRSQRT28PD_BCST: Approximation to the Reciprocal Square Root of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Broadcast). // // Forms: // -// VMAXSD xmm xmm xmm -// VMAXSD m64 xmm xmm -func VMAXSD(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VMAXSD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VMAXSD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMAXSD: bad operands") +// VRSQRT28PD.BCST m64 k zmm +// VRSQRT28PD.BCST m64 zmm +func VRSQRT28PD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT28PD.Forms(), sffxs{sffxBCST}, ops) } -// VMAXSS: Return Maximum Scalar Single-Precision Floating-Point Value. +// VRSQRT28PD_BCST_Z: Approximation to the Reciprocal Square Root of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Broadcast, Zeroing Masking). // // Forms: // -// VMAXSS xmm xmm xmm -// VMAXSS m32 xmm xmm -func VMAXSS(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VMAXSS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VMAXSS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMAXSS: bad operands") +// VRSQRT28PD.BCST.Z m64 k zmm +func VRSQRT28PD_BCST_Z(m, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT28PD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, z}) } -// VMINPD: Return Minimum Packed Double-Precision Floating-Point Values. +// VRSQRT28PD_SAE: Approximation to the Reciprocal Square Root of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Suppress All Exceptions). // // Forms: // -// VMINPD xmm xmm xmm -// VMINPD m128 xmm xmm -// VMINPD ymm ymm ymm -// VMINPD m256 ymm ymm -func VMINPD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VMINPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VMINPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VMINPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VMINPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMINPD: bad operands") +// VRSQRT28PD.SAE zmm k zmm +// VRSQRT28PD.SAE zmm zmm +func VRSQRT28PD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT28PD.Forms(), sffxs{sffxSAE}, ops) } -// VMINPS: Return Minimum Packed Single-Precision Floating-Point Values. +// VRSQRT28PD_SAE_Z: Approximation to the Reciprocal Square Root of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VMINPS xmm xmm xmm -// VMINPS m128 xmm xmm -// VMINPS ymm ymm ymm -// VMINPS m256 ymm ymm -func VMINPS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VMINPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VMINPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VMINPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VMINPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMINPS: bad operands") +// VRSQRT28PD.SAE.Z zmm k zmm +func VRSQRT28PD_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT28PD.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{z, k, z1}) } -// VMINSD: Return Minimum Scalar Double-Precision Floating-Point Value. +// VRSQRT28PD_Z: Approximation to the Reciprocal Square Root of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Zeroing Masking). // // Forms: // -// VMINSD xmm xmm xmm -// VMINSD m64 xmm xmm -func VMINSD(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VMINSD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VMINSD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMINSD: bad operands") +// VRSQRT28PD.Z m512 k zmm +// VRSQRT28PD.Z zmm k zmm +func VRSQRT28PD_Z(mz, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT28PD.Forms(), sffxs{sffxZ}, []operand.Op{mz, k, z}) } -// VMINSS: Return Minimum Scalar Single-Precision Floating-Point Value. +// VRSQRT28PS: Approximation to the Reciprocal Square Root of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error. // // Forms: // -// VMINSS xmm xmm xmm -// VMINSS m32 xmm xmm -func VMINSS(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VMINSS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VMINSS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMINSS: bad operands") +// VRSQRT28PS m512 k zmm +// VRSQRT28PS m512 zmm +// VRSQRT28PS zmm k zmm +// VRSQRT28PS zmm zmm +func VRSQRT28PS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT28PS.Forms(), sffxs{}, ops) } -// VMOVAPD: Move Aligned Packed Double-Precision Floating-Point Values. +// VRSQRT28PS_BCST: Approximation to the Reciprocal Square Root of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Broadcast). // // Forms: // -// VMOVAPD xmm xmm -// VMOVAPD m128 xmm -// VMOVAPD ymm ymm -// VMOVAPD m256 ymm -// VMOVAPD xmm m128 -// VMOVAPD ymm m256 -func VMOVAPD(mxy, mxy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVAPD", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVAPD", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVAPD", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVAPD", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(mxy) && operand.IsM128(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVAPD", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsM256(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVAPD", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMOVAPD: bad operands") +// VRSQRT28PS.BCST m32 k zmm +// VRSQRT28PS.BCST m32 zmm +func VRSQRT28PS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT28PS.Forms(), sffxs{sffxBCST}, ops) } -// VMOVAPS: Move Aligned Packed Single-Precision Floating-Point Values. +// VRSQRT28PS_BCST_Z: Approximation to the Reciprocal Square Root of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Broadcast, Zeroing Masking). // // Forms: // -// VMOVAPS xmm xmm -// VMOVAPS m128 xmm -// VMOVAPS ymm ymm -// VMOVAPS m256 ymm -// VMOVAPS xmm m128 -// VMOVAPS ymm m256 -func VMOVAPS(mxy, mxy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVAPS", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVAPS", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVAPS", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVAPS", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(mxy) && operand.IsM128(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVAPS", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsM256(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVAPS", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMOVAPS: bad operands") +// VRSQRT28PS.BCST.Z m32 k zmm +func VRSQRT28PS_BCST_Z(m, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT28PS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, z}) } -// VMOVD: Move Doubleword. +// VRSQRT28PS_SAE: Approximation to the Reciprocal Square Root of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Suppress All Exceptions). // // Forms: // -// VMOVD xmm r32 -// VMOVD r32 xmm -// VMOVD m32 xmm -// VMOVD xmm m32 -func VMOVD(mrx, mrx1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mrx) && operand.IsR32(mrx1): - return &intrep.Instruction{ - Opcode: "VMOVD", - Operands: []operand.Op{mrx, mrx1}, - Inputs: []operand.Op{mrx}, - Outputs: []operand.Op{mrx1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsR32(mrx) && operand.IsXMM(mrx1): - return &intrep.Instruction{ - Opcode: "VMOVD", - Operands: []operand.Op{mrx, mrx1}, - Inputs: []operand.Op{mrx}, - Outputs: []operand.Op{mrx1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM32(mrx) && operand.IsXMM(mrx1): - return &intrep.Instruction{ - Opcode: "VMOVD", - Operands: []operand.Op{mrx, mrx1}, - Inputs: []operand.Op{mrx}, - Outputs: []operand.Op{mrx1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(mrx) && operand.IsM32(mrx1): - return &intrep.Instruction{ - Opcode: "VMOVD", - Operands: []operand.Op{mrx, mrx1}, - Inputs: []operand.Op{mrx}, - Outputs: []operand.Op{mrx1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMOVD: bad operands") +// VRSQRT28PS.SAE zmm k zmm +// VRSQRT28PS.SAE zmm zmm +func VRSQRT28PS_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT28PS.Forms(), sffxs{sffxSAE}, ops) } -// VMOVDDUP: Move One Double-FP and Duplicate. +// VRSQRT28PS_SAE_Z: Approximation to the Reciprocal Square Root of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VMOVDDUP xmm xmm -// VMOVDDUP m64 xmm -// VMOVDDUP ymm ymm -// VMOVDDUP m256 ymm -func VMOVDDUP(mxy, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VMOVDDUP", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM64(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VMOVDDUP", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VMOVDDUP", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VMOVDDUP", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMOVDDUP: bad operands") +// VRSQRT28PS.SAE.Z zmm k zmm +func VRSQRT28PS_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT28PS.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{z, k, z1}) } -// VMOVDQA: Move Aligned Double Quadword. +// VRSQRT28PS_Z: Approximation to the Reciprocal Square Root of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error (Zeroing Masking). // // Forms: // -// VMOVDQA xmm xmm -// VMOVDQA m128 xmm -// VMOVDQA ymm ymm -// VMOVDQA m256 ymm -// VMOVDQA xmm m128 -// VMOVDQA ymm m256 -func VMOVDQA(mxy, mxy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVDQA", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVDQA", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVDQA", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVDQA", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(mxy) && operand.IsM128(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVDQA", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsM256(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVDQA", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMOVDQA: bad operands") +// VRSQRT28PS.Z m512 k zmm +// VRSQRT28PS.Z zmm k zmm +func VRSQRT28PS_Z(mz, k, z operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT28PS.Forms(), sffxs{sffxZ}, []operand.Op{mz, k, z}) } -// VMOVDQU: Move Unaligned Double Quadword. +// VRSQRT28SD: Approximation to the Reciprocal Square Root of a Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error. // // Forms: // -// VMOVDQU xmm xmm -// VMOVDQU m128 xmm -// VMOVDQU ymm ymm -// VMOVDQU m256 ymm -// VMOVDQU xmm m128 -// VMOVDQU ymm m256 -func VMOVDQU(mxy, mxy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVDQU", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVDQU", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVDQU", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVDQU", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(mxy) && operand.IsM128(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVDQU", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsM256(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVDQU", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMOVDQU: bad operands") +// VRSQRT28SD m64 xmm k xmm +// VRSQRT28SD m64 xmm xmm +// VRSQRT28SD xmm xmm k xmm +// VRSQRT28SD xmm xmm xmm +func VRSQRT28SD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT28SD.Forms(), sffxs{}, ops) } -// VMOVHLPS: Move Packed Single-Precision Floating-Point Values High to Low. +// VRSQRT28SD_SAE: Approximation to the Reciprocal Square Root of a Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Suppress All Exceptions). // // Forms: // -// VMOVHLPS xmm xmm xmm -func VMOVHLPS(x, x1, x2 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(x) && operand.IsXMM(x1) && operand.IsXMM(x2): - return &intrep.Instruction{ - Opcode: "VMOVHLPS", - Operands: []operand.Op{x, x1, x2}, - Inputs: []operand.Op{x, x1}, - Outputs: []operand.Op{x2}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMOVHLPS: bad operands") +// VRSQRT28SD.SAE xmm xmm k xmm +// VRSQRT28SD.SAE xmm xmm xmm +func VRSQRT28SD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT28SD.Forms(), sffxs{sffxSAE}, ops) } -// VMOVHPD: Move High Packed Double-Precision Floating-Point Value. +// VRSQRT28SD_SAE_Z: Approximation to the Reciprocal Square Root of a Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VMOVHPD xmm m64 -// VMOVHPD m64 xmm xmm -func VMOVHPD(ops ...operand.Op) (*intrep.Instruction, error) { - switch { - case len(ops) == 2 && operand.IsXMM(ops[0]) && operand.IsM64(ops[1]): - return &intrep.Instruction{ - Opcode: "VMOVHPD", - Operands: ops, - Inputs: []operand.Op{ops[0]}, - Outputs: []operand.Op{ops[1]}, - ISA: []string{"AVX"}, - }, nil - case len(ops) == 3 && operand.IsM64(ops[0]) && operand.IsXMM(ops[1]) && operand.IsXMM(ops[2]): - return &intrep.Instruction{ - Opcode: "VMOVHPD", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1]}, - Outputs: []operand.Op{ops[2]}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMOVHPD: bad operands") +// VRSQRT28SD.SAE.Z xmm xmm k xmm +func VRSQRT28SD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT28SD.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{x, x1, k, x2}) } -// VMOVHPS: Move High Packed Single-Precision Floating-Point Values. +// VRSQRT28SD_Z: Approximation to the Reciprocal Square Root of a Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Zeroing Masking). // // Forms: // -// VMOVHPS xmm m64 -// VMOVHPS m64 xmm xmm -func VMOVHPS(ops ...operand.Op) (*intrep.Instruction, error) { - switch { - case len(ops) == 2 && operand.IsXMM(ops[0]) && operand.IsM64(ops[1]): - return &intrep.Instruction{ - Opcode: "VMOVHPS", - Operands: ops, - Inputs: []operand.Op{ops[0]}, - Outputs: []operand.Op{ops[1]}, - ISA: []string{"AVX"}, - }, nil - case len(ops) == 3 && operand.IsM64(ops[0]) && operand.IsXMM(ops[1]) && operand.IsXMM(ops[2]): - return &intrep.Instruction{ - Opcode: "VMOVHPS", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1]}, - Outputs: []operand.Op{ops[2]}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMOVHPS: bad operands") +// VRSQRT28SD.Z m64 xmm k xmm +// VRSQRT28SD.Z xmm xmm k xmm +func VRSQRT28SD_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT28SD.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) } -// VMOVLHPS: Move Packed Single-Precision Floating-Point Values Low to High. +// VRSQRT28SS: Approximation to the Reciprocal Square Root of a Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error. // // Forms: // -// VMOVLHPS xmm xmm xmm -func VMOVLHPS(x, x1, x2 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(x) && operand.IsXMM(x1) && operand.IsXMM(x2): - return &intrep.Instruction{ - Opcode: "VMOVLHPS", - Operands: []operand.Op{x, x1, x2}, - Inputs: []operand.Op{x, x1}, - Outputs: []operand.Op{x2}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMOVLHPS: bad operands") +// VRSQRT28SS m32 xmm k xmm +// VRSQRT28SS m32 xmm xmm +// VRSQRT28SS xmm xmm k xmm +// VRSQRT28SS xmm xmm xmm +func VRSQRT28SS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT28SS.Forms(), sffxs{}, ops) } -// VMOVLPD: Move Low Packed Double-Precision Floating-Point Value. +// VRSQRT28SS_SAE: Approximation to the Reciprocal Square Root of a Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Suppress All Exceptions). // // Forms: // -// VMOVLPD xmm m64 -// VMOVLPD m64 xmm xmm -func VMOVLPD(ops ...operand.Op) (*intrep.Instruction, error) { - switch { - case len(ops) == 2 && operand.IsXMM(ops[0]) && operand.IsM64(ops[1]): - return &intrep.Instruction{ - Opcode: "VMOVLPD", - Operands: ops, - Inputs: []operand.Op{ops[0]}, - Outputs: []operand.Op{ops[1]}, - ISA: []string{"AVX"}, - }, nil - case len(ops) == 3 && operand.IsM64(ops[0]) && operand.IsXMM(ops[1]) && operand.IsXMM(ops[2]): - return &intrep.Instruction{ - Opcode: "VMOVLPD", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1]}, - Outputs: []operand.Op{ops[2]}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMOVLPD: bad operands") +// VRSQRT28SS.SAE xmm xmm k xmm +// VRSQRT28SS.SAE xmm xmm xmm +func VRSQRT28SS_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT28SS.Forms(), sffxs{sffxSAE}, ops) } -// VMOVLPS: Move Low Packed Single-Precision Floating-Point Values. +// VRSQRT28SS_SAE_Z: Approximation to the Reciprocal Square Root of a Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Suppress All Exceptions, Zeroing Masking). // // Forms: // -// VMOVLPS xmm m64 -// VMOVLPS m64 xmm xmm -func VMOVLPS(ops ...operand.Op) (*intrep.Instruction, error) { - switch { - case len(ops) == 2 && operand.IsXMM(ops[0]) && operand.IsM64(ops[1]): - return &intrep.Instruction{ - Opcode: "VMOVLPS", - Operands: ops, - Inputs: []operand.Op{ops[0]}, - Outputs: []operand.Op{ops[1]}, - ISA: []string{"AVX"}, - }, nil - case len(ops) == 3 && operand.IsM64(ops[0]) && operand.IsXMM(ops[1]) && operand.IsXMM(ops[2]): - return &intrep.Instruction{ - Opcode: "VMOVLPS", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1]}, - Outputs: []operand.Op{ops[2]}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMOVLPS: bad operands") +// VRSQRT28SS.SAE.Z xmm xmm k xmm +func VRSQRT28SS_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT28SS.Forms(), sffxs{sffxSAE, sffxZ}, []operand.Op{x, x1, k, x2}) } -// VMOVMSKPD: Extract Packed Double-Precision Floating-Point Sign Mask. +// VRSQRT28SS_Z: Approximation to the Reciprocal Square Root of a Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error (Zeroing Masking). // // Forms: // -// VMOVMSKPD xmm r32 -// VMOVMSKPD ymm r32 -func VMOVMSKPD(xy, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(xy) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "VMOVMSKPD", - Operands: []operand.Op{xy, r}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{r}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(xy) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "VMOVMSKPD", - Operands: []operand.Op{xy, r}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{r}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMOVMSKPD: bad operands") +// VRSQRT28SS.Z m32 xmm k xmm +// VRSQRT28SS.Z xmm xmm k xmm +func VRSQRT28SS_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRT28SS.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) } -// VMOVMSKPS: Extract Packed Single-Precision Floating-Point Sign Mask. +// VRSQRTPS: Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values. // // Forms: // -// VMOVMSKPS xmm r32 -// VMOVMSKPS ymm r32 -func VMOVMSKPS(xy, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(xy) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "VMOVMSKPS", - Operands: []operand.Op{xy, r}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{r}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(xy) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "VMOVMSKPS", - Operands: []operand.Op{xy, r}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{r}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMOVMSKPS: bad operands") +// VRSQRTPS m128 xmm +// VRSQRTPS m256 ymm +// VRSQRTPS xmm xmm +// VRSQRTPS ymm ymm +func VRSQRTPS(mxy, xy operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRTPS.Forms(), sffxs{}, []operand.Op{mxy, xy}) } -// VMOVNTDQ: Store Double Quadword Using Non-Temporal Hint. +// VRSQRTSS: Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value. // // Forms: // -// VMOVNTDQ xmm m128 -// VMOVNTDQ ymm m256 -func VMOVNTDQ(xy, m operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(xy) && operand.IsM128(m): - return &intrep.Instruction{ - Opcode: "VMOVNTDQ", - Operands: []operand.Op{xy, m}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{m}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(xy) && operand.IsM256(m): - return &intrep.Instruction{ - Opcode: "VMOVNTDQ", - Operands: []operand.Op{xy, m}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{m}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMOVNTDQ: bad operands") +// VRSQRTSS m32 xmm xmm +// VRSQRTSS xmm xmm xmm +func VRSQRTSS(mx, x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVRSQRTSS.Forms(), sffxs{}, []operand.Op{mx, x, x1}) } -// VMOVNTDQA: Load Double Quadword Non-Temporal Aligned Hint. +// VSCALEFPD: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values. // // Forms: // -// VMOVNTDQA m128 xmm -// VMOVNTDQA m256 ymm -func VMOVNTDQA(m, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM128(m) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VMOVNTDQA", - Operands: []operand.Op{m, xy}, - Inputs: []operand.Op{m}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(m) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VMOVNTDQA", - Operands: []operand.Op{m, xy}, - Inputs: []operand.Op{m}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VMOVNTDQA: bad operands") +// VSCALEFPD m128 xmm k xmm +// VSCALEFPD m128 xmm xmm +// VSCALEFPD m256 ymm k ymm +// VSCALEFPD m256 ymm ymm +// VSCALEFPD xmm xmm k xmm +// VSCALEFPD xmm xmm xmm +// VSCALEFPD ymm ymm k ymm +// VSCALEFPD ymm ymm ymm +// VSCALEFPD m512 zmm k zmm +// VSCALEFPD m512 zmm zmm +// VSCALEFPD zmm zmm k zmm +// VSCALEFPD zmm zmm zmm +func VSCALEFPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFPD.Forms(), sffxs{}, ops) } -// VMOVNTPD: Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint. +// VSCALEFPD_BCST: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Broadcast). // // Forms: // -// VMOVNTPD xmm m128 -// VMOVNTPD ymm m256 -func VMOVNTPD(xy, m operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(xy) && operand.IsM128(m): - return &intrep.Instruction{ - Opcode: "VMOVNTPD", - Operands: []operand.Op{xy, m}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{m}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(xy) && operand.IsM256(m): - return &intrep.Instruction{ - Opcode: "VMOVNTPD", - Operands: []operand.Op{xy, m}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{m}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMOVNTPD: bad operands") +// VSCALEFPD.BCST m64 xmm k xmm +// VSCALEFPD.BCST m64 xmm xmm +// VSCALEFPD.BCST m64 ymm k ymm +// VSCALEFPD.BCST m64 ymm ymm +// VSCALEFPD.BCST m64 zmm k zmm +// VSCALEFPD.BCST m64 zmm zmm +func VSCALEFPD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFPD.Forms(), sffxs{sffxBCST}, ops) } -// VMOVNTPS: Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint. +// VSCALEFPD_BCST_Z: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VMOVNTPS xmm m128 -// VMOVNTPS ymm m256 -func VMOVNTPS(xy, m operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(xy) && operand.IsM128(m): - return &intrep.Instruction{ - Opcode: "VMOVNTPS", - Operands: []operand.Op{xy, m}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{m}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(xy) && operand.IsM256(m): - return &intrep.Instruction{ - Opcode: "VMOVNTPS", - Operands: []operand.Op{xy, m}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{m}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMOVNTPS: bad operands") +// VSCALEFPD.BCST.Z m64 xmm k xmm +// VSCALEFPD.BCST.Z m64 ymm k ymm +// VSCALEFPD.BCST.Z m64 zmm k zmm +func VSCALEFPD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFPD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// VMOVQ: Move Quadword. +// VSCALEFPD_RD_SAE: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Round Towards Negative Infinity). // // Forms: // -// VMOVQ xmm r64 -// VMOVQ r64 xmm -// VMOVQ xmm xmm -// VMOVQ m64 xmm -// VMOVQ xmm m64 -func VMOVQ(mrx, mrx1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mrx) && operand.IsR64(mrx1): - return &intrep.Instruction{ - Opcode: "VMOVQ", - Operands: []operand.Op{mrx, mrx1}, - Inputs: []operand.Op{mrx}, - Outputs: []operand.Op{mrx1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsR64(mrx) && operand.IsXMM(mrx1): - return &intrep.Instruction{ - Opcode: "VMOVQ", - Operands: []operand.Op{mrx, mrx1}, - Inputs: []operand.Op{mrx}, - Outputs: []operand.Op{mrx1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(mrx) && operand.IsXMM(mrx1): - return &intrep.Instruction{ - Opcode: "VMOVQ", - Operands: []operand.Op{mrx, mrx1}, - Inputs: []operand.Op{mrx}, - Outputs: []operand.Op{mrx1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM64(mrx) && operand.IsXMM(mrx1): - return &intrep.Instruction{ - Opcode: "VMOVQ", - Operands: []operand.Op{mrx, mrx1}, - Inputs: []operand.Op{mrx}, - Outputs: []operand.Op{mrx1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(mrx) && operand.IsM64(mrx1): - return &intrep.Instruction{ - Opcode: "VMOVQ", - Operands: []operand.Op{mrx, mrx1}, - Inputs: []operand.Op{mrx}, - Outputs: []operand.Op{mrx1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMOVQ: bad operands") +// VSCALEFPD.RD_SAE zmm zmm k zmm +// VSCALEFPD.RD_SAE zmm zmm zmm +func VSCALEFPD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFPD.Forms(), sffxs{sffxRD_SAE}, ops) } -// VMOVSD: Move Scalar Double-Precision Floating-Point Value. +// VSCALEFPD_RD_SAE_Z: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VMOVSD m64 xmm -// VMOVSD xmm m64 -// VMOVSD xmm xmm xmm -func VMOVSD(ops ...operand.Op) (*intrep.Instruction, error) { - switch { - case len(ops) == 2 && operand.IsM64(ops[0]) && operand.IsXMM(ops[1]): - return &intrep.Instruction{ - Opcode: "VMOVSD", - Operands: ops, - Inputs: []operand.Op{ops[0]}, - Outputs: []operand.Op{ops[1]}, - ISA: []string{"AVX"}, - }, nil - case len(ops) == 2 && operand.IsXMM(ops[0]) && operand.IsM64(ops[1]): - return &intrep.Instruction{ - Opcode: "VMOVSD", - Operands: ops, - Inputs: []operand.Op{ops[0]}, - Outputs: []operand.Op{ops[1]}, - ISA: []string{"AVX"}, - }, nil - case len(ops) == 3 && operand.IsXMM(ops[0]) && operand.IsXMM(ops[1]) && operand.IsXMM(ops[2]): - return &intrep.Instruction{ - Opcode: "VMOVSD", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1]}, - Outputs: []operand.Op{ops[2]}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMOVSD: bad operands") +// VSCALEFPD.RD_SAE.Z zmm zmm k zmm +func VSCALEFPD_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFPD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) } -// VMOVSHDUP: Move Packed Single-FP High and Duplicate. +// VSCALEFPD_RN_SAE: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Round Towards Nearest). // // Forms: // -// VMOVSHDUP xmm xmm -// VMOVSHDUP m128 xmm -// VMOVSHDUP ymm ymm -// VMOVSHDUP m256 ymm -func VMOVSHDUP(mxy, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VMOVSHDUP", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VMOVSHDUP", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VMOVSHDUP", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VMOVSHDUP", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMOVSHDUP: bad operands") +// VSCALEFPD.RN_SAE zmm zmm k zmm +// VSCALEFPD.RN_SAE zmm zmm zmm +func VSCALEFPD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFPD.Forms(), sffxs{sffxRN_SAE}, ops) } -// VMOVSLDUP: Move Packed Single-FP Low and Duplicate. +// VSCALEFPD_RN_SAE_Z: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VMOVSLDUP xmm xmm -// VMOVSLDUP m128 xmm -// VMOVSLDUP ymm ymm -// VMOVSLDUP m256 ymm -func VMOVSLDUP(mxy, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VMOVSLDUP", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VMOVSLDUP", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VMOVSLDUP", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VMOVSLDUP", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMOVSLDUP: bad operands") +// VSCALEFPD.RN_SAE.Z zmm zmm k zmm +func VSCALEFPD_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFPD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) } -// VMOVSS: Move Scalar Single-Precision Floating-Point Values. +// VSCALEFPD_RU_SAE: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Round Towards Positive Infinity). // // Forms: // -// VMOVSS m32 xmm -// VMOVSS xmm m32 -// VMOVSS xmm xmm xmm -func VMOVSS(ops ...operand.Op) (*intrep.Instruction, error) { - switch { - case len(ops) == 2 && operand.IsM32(ops[0]) && operand.IsXMM(ops[1]): - return &intrep.Instruction{ - Opcode: "VMOVSS", - Operands: ops, - Inputs: []operand.Op{ops[0]}, - Outputs: []operand.Op{ops[1]}, - ISA: []string{"AVX"}, - }, nil - case len(ops) == 2 && operand.IsXMM(ops[0]) && operand.IsM32(ops[1]): - return &intrep.Instruction{ - Opcode: "VMOVSS", - Operands: ops, - Inputs: []operand.Op{ops[0]}, - Outputs: []operand.Op{ops[1]}, - ISA: []string{"AVX"}, - }, nil - case len(ops) == 3 && operand.IsXMM(ops[0]) && operand.IsXMM(ops[1]) && operand.IsXMM(ops[2]): - return &intrep.Instruction{ - Opcode: "VMOVSS", - Operands: ops, - Inputs: []operand.Op{ops[0], ops[1]}, - Outputs: []operand.Op{ops[2]}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMOVSS: bad operands") +// VSCALEFPD.RU_SAE zmm zmm k zmm +// VSCALEFPD.RU_SAE zmm zmm zmm +func VSCALEFPD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFPD.Forms(), sffxs{sffxRU_SAE}, ops) } -// VMOVUPD: Move Unaligned Packed Double-Precision Floating-Point Values. +// VSCALEFPD_RU_SAE_Z: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VMOVUPD xmm xmm -// VMOVUPD m128 xmm -// VMOVUPD ymm ymm -// VMOVUPD m256 ymm -// VMOVUPD xmm m128 -// VMOVUPD ymm m256 -func VMOVUPD(mxy, mxy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVUPD", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVUPD", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVUPD", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVUPD", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(mxy) && operand.IsM128(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVUPD", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsM256(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVUPD", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMOVUPD: bad operands") +// VSCALEFPD.RU_SAE.Z zmm zmm k zmm +func VSCALEFPD_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFPD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) } -// VMOVUPS: Move Unaligned Packed Single-Precision Floating-Point Values. +// VSCALEFPD_RZ_SAE: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Round Towards Zero). // // Forms: // -// VMOVUPS xmm xmm -// VMOVUPS m128 xmm -// VMOVUPS ymm ymm -// VMOVUPS m256 ymm -// VMOVUPS xmm m128 -// VMOVUPS ymm m256 -func VMOVUPS(mxy, mxy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVUPS", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVUPS", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVUPS", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVUPS", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(mxy) && operand.IsM128(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVUPS", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsM256(mxy1): - return &intrep.Instruction{ - Opcode: "VMOVUPS", - Operands: []operand.Op{mxy, mxy1}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMOVUPS: bad operands") +// VSCALEFPD.RZ_SAE zmm zmm k zmm +// VSCALEFPD.RZ_SAE zmm zmm zmm +func VSCALEFPD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFPD.Forms(), sffxs{sffxRZ_SAE}, ops) } -// VMPSADBW: Compute Multiple Packed Sums of Absolute Difference. +// VSCALEFPD_RZ_SAE_Z: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). // // Forms: // -// VMPSADBW imm8 xmm xmm xmm -// VMPSADBW imm8 m128 xmm xmm -// VMPSADBW imm8 ymm ymm ymm -// VMPSADBW imm8 m256 ymm ymm -func VMPSADBW(i, mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VMPSADBW", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VMPSADBW", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VMPSADBW", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsIMM8(i) && operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VMPSADBW", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VMPSADBW: bad operands") +// VSCALEFPD.RZ_SAE.Z zmm zmm k zmm +func VSCALEFPD_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFPD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) } -// VMULPD: Multiply Packed Double-Precision Floating-Point Values. +// VSCALEFPD_Z: Scale Packed Double-Precision Floating-Point Values With Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VMULPD xmm xmm xmm -// VMULPD m128 xmm xmm -// VMULPD ymm ymm ymm -// VMULPD m256 ymm ymm -func VMULPD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VMULPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VMULPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VMULPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VMULPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMULPD: bad operands") +// VSCALEFPD.Z m128 xmm k xmm +// VSCALEFPD.Z m256 ymm k ymm +// VSCALEFPD.Z xmm xmm k xmm +// VSCALEFPD.Z ymm ymm k ymm +// VSCALEFPD.Z m512 zmm k zmm +// VSCALEFPD.Z zmm zmm k zmm +func VSCALEFPD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFPD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// VMULPS: Multiply Packed Single-Precision Floating-Point Values. +// VSCALEFPS: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values. // // Forms: // -// VMULPS xmm xmm xmm -// VMULPS m128 xmm xmm -// VMULPS ymm ymm ymm -// VMULPS m256 ymm ymm -func VMULPS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VMULPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VMULPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VMULPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VMULPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMULPS: bad operands") +// VSCALEFPS m128 xmm k xmm +// VSCALEFPS m128 xmm xmm +// VSCALEFPS m256 ymm k ymm +// VSCALEFPS m256 ymm ymm +// VSCALEFPS xmm xmm k xmm +// VSCALEFPS xmm xmm xmm +// VSCALEFPS ymm ymm k ymm +// VSCALEFPS ymm ymm ymm +// VSCALEFPS m512 zmm k zmm +// VSCALEFPS m512 zmm zmm +// VSCALEFPS zmm zmm k zmm +// VSCALEFPS zmm zmm zmm +func VSCALEFPS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFPS.Forms(), sffxs{}, ops) } -// VMULSD: Multiply Scalar Double-Precision Floating-Point Values. +// VSCALEFPS_BCST: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Broadcast). // // Forms: // -// VMULSD xmm xmm xmm -// VMULSD m64 xmm xmm -func VMULSD(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VMULSD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VMULSD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMULSD: bad operands") +// VSCALEFPS.BCST m32 xmm k xmm +// VSCALEFPS.BCST m32 xmm xmm +// VSCALEFPS.BCST m32 ymm k ymm +// VSCALEFPS.BCST m32 ymm ymm +// VSCALEFPS.BCST m32 zmm k zmm +// VSCALEFPS.BCST m32 zmm zmm +func VSCALEFPS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFPS.Forms(), sffxs{sffxBCST}, ops) } -// VMULSS: Multiply Scalar Single-Precision Floating-Point Values. +// VSCALEFPS_BCST_Z: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VMULSS xmm xmm xmm -// VMULSS m32 xmm xmm -func VMULSS(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VMULSS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VMULSS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VMULSS: bad operands") +// VSCALEFPS.BCST.Z m32 xmm k xmm +// VSCALEFPS.BCST.Z m32 ymm k ymm +// VSCALEFPS.BCST.Z m32 zmm k zmm +func VSCALEFPS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFPS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// VORPD: Bitwise Logical OR of Double-Precision Floating-Point Values. +// VSCALEFPS_RD_SAE: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Round Towards Negative Infinity). // // Forms: // -// VORPD xmm xmm xmm -// VORPD m128 xmm xmm -// VORPD ymm ymm ymm -// VORPD m256 ymm ymm -func VORPD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VORPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VORPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VORPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VORPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VORPD: bad operands") +// VSCALEFPS.RD_SAE zmm zmm k zmm +// VSCALEFPS.RD_SAE zmm zmm zmm +func VSCALEFPS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFPS.Forms(), sffxs{sffxRD_SAE}, ops) } -// VORPS: Bitwise Logical OR of Single-Precision Floating-Point Values. +// VSCALEFPS_RD_SAE_Z: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VORPS xmm xmm xmm -// VORPS m128 xmm xmm -// VORPS ymm ymm ymm -// VORPS m256 ymm ymm -func VORPS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VORPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VORPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VORPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VORPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VORPS: bad operands") +// VSCALEFPS.RD_SAE.Z zmm zmm k zmm +func VSCALEFPS_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFPS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) } -// VPABSB: Packed Absolute Value of Byte Integers. +// VSCALEFPS_RN_SAE: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Round Towards Nearest). // // Forms: // -// VPABSB xmm xmm -// VPABSB m128 xmm -// VPABSB ymm ymm -// VPABSB m256 ymm -func VPABSB(mxy, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPABSB", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPABSB", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPABSB", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPABSB", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPABSB: bad operands") +// VSCALEFPS.RN_SAE zmm zmm k zmm +// VSCALEFPS.RN_SAE zmm zmm zmm +func VSCALEFPS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFPS.Forms(), sffxs{sffxRN_SAE}, ops) } -// VPABSD: Packed Absolute Value of Doubleword Integers. +// VSCALEFPS_RN_SAE_Z: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VPABSD xmm xmm -// VPABSD m128 xmm -// VPABSD ymm ymm -// VPABSD m256 ymm -func VPABSD(mxy, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPABSD", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPABSD", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPABSD", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPABSD", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPABSD: bad operands") +// VSCALEFPS.RN_SAE.Z zmm zmm k zmm +func VSCALEFPS_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFPS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) } -// VPABSW: Packed Absolute Value of Word Integers. +// VSCALEFPS_RU_SAE: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Round Towards Positive Infinity). // // Forms: // -// VPABSW xmm xmm -// VPABSW m128 xmm -// VPABSW ymm ymm -// VPABSW m256 ymm -func VPABSW(mxy, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPABSW", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPABSW", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPABSW", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPABSW", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPABSW: bad operands") +// VSCALEFPS.RU_SAE zmm zmm k zmm +// VSCALEFPS.RU_SAE zmm zmm zmm +func VSCALEFPS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFPS.Forms(), sffxs{sffxRU_SAE}, ops) } -// VPACKSSDW: Pack Doublewords into Words with Signed Saturation. +// VSCALEFPS_RU_SAE_Z: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VPACKSSDW xmm xmm xmm -// VPACKSSDW m128 xmm xmm -// VPACKSSDW ymm ymm ymm -// VPACKSSDW m256 ymm ymm -func VPACKSSDW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPACKSSDW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPACKSSDW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPACKSSDW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPACKSSDW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPACKSSDW: bad operands") +// VSCALEFPS.RU_SAE.Z zmm zmm k zmm +func VSCALEFPS_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFPS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) } -// VPACKSSWB: Pack Words into Bytes with Signed Saturation. +// VSCALEFPS_RZ_SAE: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Round Towards Zero). // // Forms: // -// VPACKSSWB xmm xmm xmm -// VPACKSSWB m128 xmm xmm -// VPACKSSWB ymm ymm ymm -// VPACKSSWB m256 ymm ymm -func VPACKSSWB(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPACKSSWB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPACKSSWB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPACKSSWB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPACKSSWB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPACKSSWB: bad operands") +// VSCALEFPS.RZ_SAE zmm zmm k zmm +// VSCALEFPS.RZ_SAE zmm zmm zmm +func VSCALEFPS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFPS.Forms(), sffxs{sffxRZ_SAE}, ops) } -// VPACKUSDW: Pack Doublewords into Words with Unsigned Saturation. +// VSCALEFPS_RZ_SAE_Z: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). // // Forms: // -// VPACKUSDW xmm xmm xmm -// VPACKUSDW m128 xmm xmm -// VPACKUSDW ymm ymm ymm -// VPACKUSDW m256 ymm ymm -func VPACKUSDW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPACKUSDW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPACKUSDW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPACKUSDW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPACKUSDW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPACKUSDW: bad operands") +// VSCALEFPS.RZ_SAE.Z zmm zmm k zmm +func VSCALEFPS_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFPS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) } -// VPACKUSWB: Pack Words into Bytes with Unsigned Saturation. +// VSCALEFPS_Z: Scale Packed Single-Precision Floating-Point Values With Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VPACKUSWB xmm xmm xmm -// VPACKUSWB m128 xmm xmm -// VPACKUSWB ymm ymm ymm -// VPACKUSWB m256 ymm ymm -func VPACKUSWB(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPACKUSWB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPACKUSWB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPACKUSWB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPACKUSWB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPACKUSWB: bad operands") +// VSCALEFPS.Z m128 xmm k xmm +// VSCALEFPS.Z m256 ymm k ymm +// VSCALEFPS.Z xmm xmm k xmm +// VSCALEFPS.Z ymm ymm k ymm +// VSCALEFPS.Z m512 zmm k zmm +// VSCALEFPS.Z zmm zmm k zmm +func VSCALEFPS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFPS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// VPADDB: Add Packed Byte Integers. +// VSCALEFSD: Scale Scalar Double-Precision Floating-Point Value With a Double-Precision Floating-Point Value. // // Forms: // -// VPADDB xmm xmm xmm -// VPADDB m128 xmm xmm -// VPADDB ymm ymm ymm -// VPADDB m256 ymm ymm -func VPADDB(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPADDB: bad operands") +// VSCALEFSD m64 xmm k xmm +// VSCALEFSD m64 xmm xmm +// VSCALEFSD xmm xmm k xmm +// VSCALEFSD xmm xmm xmm +func VSCALEFSD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFSD.Forms(), sffxs{}, ops) } -// VPADDD: Add Packed Doubleword Integers. +// VSCALEFSD_RD_SAE: Scale Scalar Double-Precision Floating-Point Value With a Double-Precision Floating-Point Value (Round Towards Negative Infinity). // // Forms: // -// VPADDD xmm xmm xmm -// VPADDD m128 xmm xmm -// VPADDD ymm ymm ymm -// VPADDD m256 ymm ymm -func VPADDD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPADDD: bad operands") +// VSCALEFSD.RD_SAE xmm xmm k xmm +// VSCALEFSD.RD_SAE xmm xmm xmm +func VSCALEFSD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFSD.Forms(), sffxs{sffxRD_SAE}, ops) } -// VPADDQ: Add Packed Quadword Integers. +// VSCALEFSD_RD_SAE_Z: Scale Scalar Double-Precision Floating-Point Value With a Double-Precision Floating-Point Value (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VPADDQ xmm xmm xmm -// VPADDQ m128 xmm xmm -// VPADDQ ymm ymm ymm -// VPADDQ m256 ymm ymm -func VPADDQ(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPADDQ: bad operands") +// VSCALEFSD.RD_SAE.Z xmm xmm k xmm +func VSCALEFSD_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFSD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) } -// VPADDSB: Add Packed Signed Byte Integers with Signed Saturation. +// VSCALEFSD_RN_SAE: Scale Scalar Double-Precision Floating-Point Value With a Double-Precision Floating-Point Value (Round Towards Nearest). // // Forms: // -// VPADDSB xmm xmm xmm -// VPADDSB m128 xmm xmm -// VPADDSB ymm ymm ymm -// VPADDSB m256 ymm ymm -func VPADDSB(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDSB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDSB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDSB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDSB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPADDSB: bad operands") +// VSCALEFSD.RN_SAE xmm xmm k xmm +// VSCALEFSD.RN_SAE xmm xmm xmm +func VSCALEFSD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFSD.Forms(), sffxs{sffxRN_SAE}, ops) } -// VPADDSW: Add Packed Signed Word Integers with Signed Saturation. +// VSCALEFSD_RN_SAE_Z: Scale Scalar Double-Precision Floating-Point Value With a Double-Precision Floating-Point Value (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VPADDSW xmm xmm xmm -// VPADDSW m128 xmm xmm -// VPADDSW ymm ymm ymm -// VPADDSW m256 ymm ymm -func VPADDSW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPADDSW: bad operands") +// VSCALEFSD.RN_SAE.Z xmm xmm k xmm +func VSCALEFSD_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFSD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) } -// VPADDUSB: Add Packed Unsigned Byte Integers with Unsigned Saturation. +// VSCALEFSD_RU_SAE: Scale Scalar Double-Precision Floating-Point Value With a Double-Precision Floating-Point Value (Round Towards Positive Infinity). // // Forms: // -// VPADDUSB xmm xmm xmm -// VPADDUSB m128 xmm xmm -// VPADDUSB ymm ymm ymm -// VPADDUSB m256 ymm ymm -func VPADDUSB(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDUSB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDUSB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDUSB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDUSB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPADDUSB: bad operands") +// VSCALEFSD.RU_SAE xmm xmm k xmm +// VSCALEFSD.RU_SAE xmm xmm xmm +func VSCALEFSD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFSD.Forms(), sffxs{sffxRU_SAE}, ops) } -// VPADDUSW: Add Packed Unsigned Word Integers with Unsigned Saturation. +// VSCALEFSD_RU_SAE_Z: Scale Scalar Double-Precision Floating-Point Value With a Double-Precision Floating-Point Value (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VPADDUSW xmm xmm xmm -// VPADDUSW m128 xmm xmm -// VPADDUSW ymm ymm ymm -// VPADDUSW m256 ymm ymm -func VPADDUSW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDUSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDUSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDUSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDUSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPADDUSW: bad operands") +// VSCALEFSD.RU_SAE.Z xmm xmm k xmm +func VSCALEFSD_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFSD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) } -// VPADDW: Add Packed Word Integers. +// VSCALEFSD_RZ_SAE: Scale Scalar Double-Precision Floating-Point Value With a Double-Precision Floating-Point Value (Round Towards Zero). // // Forms: // -// VPADDW xmm xmm xmm -// VPADDW m128 xmm xmm -// VPADDW ymm ymm ymm -// VPADDW m256 ymm ymm -func VPADDW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPADDW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPADDW: bad operands") +// VSCALEFSD.RZ_SAE xmm xmm k xmm +// VSCALEFSD.RZ_SAE xmm xmm xmm +func VSCALEFSD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFSD.Forms(), sffxs{sffxRZ_SAE}, ops) } -// VPALIGNR: Packed Align Right. +// VSCALEFSD_RZ_SAE_Z: Scale Scalar Double-Precision Floating-Point Value With a Double-Precision Floating-Point Value (Round Towards Zero, Zeroing Masking). // // Forms: // -// VPALIGNR imm8 xmm xmm xmm -// VPALIGNR imm8 m128 xmm xmm -// VPALIGNR imm8 ymm ymm ymm -// VPALIGNR imm8 m256 ymm ymm -func VPALIGNR(i, mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPALIGNR", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPALIGNR", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPALIGNR", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsIMM8(i) && operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPALIGNR", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPALIGNR: bad operands") +// VSCALEFSD.RZ_SAE.Z xmm xmm k xmm +func VSCALEFSD_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFSD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) } -// VPAND: Packed Bitwise Logical AND. +// VSCALEFSD_Z: Scale Scalar Double-Precision Floating-Point Value With a Double-Precision Floating-Point Value (Zeroing Masking). // // Forms: // -// VPAND xmm xmm xmm -// VPAND m128 xmm xmm -// VPAND ymm ymm ymm -// VPAND m256 ymm ymm -func VPAND(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPAND", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPAND", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPAND", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPAND", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPAND: bad operands") +// VSCALEFSD.Z m64 xmm k xmm +// VSCALEFSD.Z xmm xmm k xmm +func VSCALEFSD_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFSD.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) } -// VPANDN: Packed Bitwise Logical AND NOT. +// VSCALEFSS: Scale Scalar Single-Precision Floating-Point Value With a Single-Precision Floating-Point Value. // // Forms: // -// VPANDN xmm xmm xmm -// VPANDN m128 xmm xmm -// VPANDN ymm ymm ymm -// VPANDN m256 ymm ymm -func VPANDN(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPANDN", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPANDN", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPANDN", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - CancellingInputs: true, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPANDN", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPANDN: bad operands") +// VSCALEFSS m32 xmm k xmm +// VSCALEFSS m32 xmm xmm +// VSCALEFSS xmm xmm k xmm +// VSCALEFSS xmm xmm xmm +func VSCALEFSS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFSS.Forms(), sffxs{}, ops) } -// VPAVGB: Average Packed Byte Integers. +// VSCALEFSS_RD_SAE: Scale Scalar Single-Precision Floating-Point Value With a Single-Precision Floating-Point Value (Round Towards Negative Infinity). // // Forms: // -// VPAVGB xmm xmm xmm -// VPAVGB m128 xmm xmm -// VPAVGB ymm ymm ymm -// VPAVGB m256 ymm ymm -func VPAVGB(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPAVGB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPAVGB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPAVGB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPAVGB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPAVGB: bad operands") +// VSCALEFSS.RD_SAE xmm xmm k xmm +// VSCALEFSS.RD_SAE xmm xmm xmm +func VSCALEFSS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFSS.Forms(), sffxs{sffxRD_SAE}, ops) } -// VPAVGW: Average Packed Word Integers. +// VSCALEFSS_RD_SAE_Z: Scale Scalar Single-Precision Floating-Point Value With a Single-Precision Floating-Point Value (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VPAVGW xmm xmm xmm -// VPAVGW m128 xmm xmm -// VPAVGW ymm ymm ymm -// VPAVGW m256 ymm ymm -func VPAVGW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPAVGW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPAVGW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPAVGW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPAVGW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPAVGW: bad operands") +// VSCALEFSS.RD_SAE.Z xmm xmm k xmm +func VSCALEFSS_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFSS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) } -// VPBLENDD: Blend Packed Doublewords. +// VSCALEFSS_RN_SAE: Scale Scalar Single-Precision Floating-Point Value With a Single-Precision Floating-Point Value (Round Towards Nearest). // // Forms: // -// VPBLENDD imm8 xmm xmm xmm -// VPBLENDD imm8 m128 xmm xmm -// VPBLENDD imm8 ymm ymm ymm -// VPBLENDD imm8 m256 ymm ymm -func VPBLENDD(i, mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPBLENDD", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPBLENDD", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsIMM8(i) && operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPBLENDD", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsIMM8(i) && operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPBLENDD", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPBLENDD: bad operands") +// VSCALEFSS.RN_SAE xmm xmm k xmm +// VSCALEFSS.RN_SAE xmm xmm xmm +func VSCALEFSS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFSS.Forms(), sffxs{sffxRN_SAE}, ops) } -// VPBLENDVB: Variable Blend Packed Bytes. +// VSCALEFSS_RN_SAE_Z: Scale Scalar Single-Precision Floating-Point Value With a Single-Precision Floating-Point Value (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VPBLENDVB xmm xmm xmm xmm -// VPBLENDVB xmm m128 xmm xmm -// VPBLENDVB ymm ymm ymm ymm -// VPBLENDVB ymm m256 ymm ymm -func VPBLENDVB(xy, mxy, xy1, xy2 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(xy) && operand.IsXMM(mxy) && operand.IsXMM(xy1) && operand.IsXMM(xy2): - return &intrep.Instruction{ - Opcode: "VPBLENDVB", - Operands: []operand.Op{xy, mxy, xy1, xy2}, - Inputs: []operand.Op{xy, mxy, xy1}, - Outputs: []operand.Op{xy2}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(xy) && operand.IsM128(mxy) && operand.IsXMM(xy1) && operand.IsXMM(xy2): - return &intrep.Instruction{ - Opcode: "VPBLENDVB", - Operands: []operand.Op{xy, mxy, xy1, xy2}, - Inputs: []operand.Op{xy, mxy, xy1}, - Outputs: []operand.Op{xy2}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(xy) && operand.IsYMM(mxy) && operand.IsYMM(xy1) && operand.IsYMM(xy2): - return &intrep.Instruction{ - Opcode: "VPBLENDVB", - Operands: []operand.Op{xy, mxy, xy1, xy2}, - Inputs: []operand.Op{xy, mxy, xy1}, - Outputs: []operand.Op{xy2}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsYMM(xy) && operand.IsM256(mxy) && operand.IsYMM(xy1) && operand.IsYMM(xy2): - return &intrep.Instruction{ - Opcode: "VPBLENDVB", - Operands: []operand.Op{xy, mxy, xy1, xy2}, - Inputs: []operand.Op{xy, mxy, xy1}, - Outputs: []operand.Op{xy2}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPBLENDVB: bad operands") +// VSCALEFSS.RN_SAE.Z xmm xmm k xmm +func VSCALEFSS_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFSS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) } -// VPBLENDW: Blend Packed Words. +// VSCALEFSS_RU_SAE: Scale Scalar Single-Precision Floating-Point Value With a Single-Precision Floating-Point Value (Round Towards Positive Infinity). // // Forms: // -// VPBLENDW imm8 xmm xmm xmm -// VPBLENDW imm8 m128 xmm xmm -// VPBLENDW imm8 ymm ymm ymm -// VPBLENDW imm8 m256 ymm ymm -func VPBLENDW(i, mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPBLENDW", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPBLENDW", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPBLENDW", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsIMM8(i) && operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPBLENDW", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPBLENDW: bad operands") +// VSCALEFSS.RU_SAE xmm xmm k xmm +// VSCALEFSS.RU_SAE xmm xmm xmm +func VSCALEFSS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFSS.Forms(), sffxs{sffxRU_SAE}, ops) } -// VPBROADCASTB: Broadcast Byte Integer. +// VSCALEFSS_RU_SAE_Z: Scale Scalar Single-Precision Floating-Point Value With a Single-Precision Floating-Point Value (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VPBROADCASTB xmm xmm -// VPBROADCASTB m8 xmm -// VPBROADCASTB xmm ymm -// VPBROADCASTB m8 ymm -func VPBROADCASTB(mx, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPBROADCASTB", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM8(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPBROADCASTB", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsXMM(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPBROADCASTB", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM8(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPBROADCASTB", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPBROADCASTB: bad operands") +// VSCALEFSS.RU_SAE.Z xmm xmm k xmm +func VSCALEFSS_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFSS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) } -// VPBROADCASTD: Broadcast Doubleword Integer. +// VSCALEFSS_RZ_SAE: Scale Scalar Single-Precision Floating-Point Value With a Single-Precision Floating-Point Value (Round Towards Zero). // // Forms: // -// VPBROADCASTD xmm xmm -// VPBROADCASTD m32 xmm -// VPBROADCASTD xmm ymm -// VPBROADCASTD m32 ymm -func VPBROADCASTD(mx, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPBROADCASTD", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPBROADCASTD", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsXMM(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPBROADCASTD", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM32(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPBROADCASTD", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPBROADCASTD: bad operands") +// VSCALEFSS.RZ_SAE xmm xmm k xmm +// VSCALEFSS.RZ_SAE xmm xmm xmm +func VSCALEFSS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFSS.Forms(), sffxs{sffxRZ_SAE}, ops) } -// VPBROADCASTQ: Broadcast Quadword Integer. +// VSCALEFSS_RZ_SAE_Z: Scale Scalar Single-Precision Floating-Point Value With a Single-Precision Floating-Point Value (Round Towards Zero, Zeroing Masking). // // Forms: // -// VPBROADCASTQ xmm xmm -// VPBROADCASTQ m64 xmm -// VPBROADCASTQ xmm ymm -// VPBROADCASTQ m64 ymm -func VPBROADCASTQ(mx, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPBROADCASTQ", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPBROADCASTQ", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsXMM(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPBROADCASTQ", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM64(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPBROADCASTQ", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPBROADCASTQ: bad operands") +// VSCALEFSS.RZ_SAE.Z xmm xmm k xmm +func VSCALEFSS_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFSS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) } -// VPBROADCASTW: Broadcast Word Integer. +// VSCALEFSS_Z: Scale Scalar Single-Precision Floating-Point Value With a Single-Precision Floating-Point Value (Zeroing Masking). // // Forms: // -// VPBROADCASTW xmm xmm -// VPBROADCASTW m16 xmm -// VPBROADCASTW xmm ymm -// VPBROADCASTW m16 ymm -func VPBROADCASTW(mx, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPBROADCASTW", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM16(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPBROADCASTW", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsXMM(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPBROADCASTW", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM16(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPBROADCASTW", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPBROADCASTW: bad operands") +// VSCALEFSS.Z m32 xmm k xmm +// VSCALEFSS.Z xmm xmm k xmm +func VSCALEFSS_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSCALEFSS.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) } -// VPCLMULQDQ: Carry-Less Quadword Multiplication. +// VSCATTERDPD: Scatter Packed Double-Precision Floating-Point Values with Signed Doubleword Indices. // // Forms: // -// VPCLMULQDQ imm8 xmm xmm xmm -// VPCLMULQDQ imm8 m128 xmm xmm -func VPCLMULQDQ(i, mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VPCLMULQDQ", - Operands: []operand.Op{i, mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX", "PCLMULQDQ"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VPCLMULQDQ", - Operands: []operand.Op{i, mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX", "PCLMULQDQ"}, - }, nil - } - return nil, errors.New("VPCLMULQDQ: bad operands") +// VSCATTERDPD xmm k vm32x +// VSCATTERDPD ymm k vm32x +// VSCATTERDPD zmm k vm32y +func VSCATTERDPD(xyz, k, v operand.Op) (*intrep.Instruction, error) { + return build(opcVSCATTERDPD.Forms(), sffxs{}, []operand.Op{xyz, k, v}) } -// VPCMPEQB: Compare Packed Byte Data for Equality. +// VSCATTERDPS: Scatter Packed Single-Precision Floating-Point Values with Signed Doubleword Indices. // // Forms: // -// VPCMPEQB xmm xmm xmm -// VPCMPEQB m128 xmm xmm -// VPCMPEQB ymm ymm ymm -// VPCMPEQB m256 ymm ymm -func VPCMPEQB(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPEQB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPEQB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPEQB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - CancellingInputs: true, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPEQB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPCMPEQB: bad operands") +// VSCATTERDPS xmm k vm32x +// VSCATTERDPS ymm k vm32y +// VSCATTERDPS zmm k vm32z +func VSCATTERDPS(xyz, k, v operand.Op) (*intrep.Instruction, error) { + return build(opcVSCATTERDPS.Forms(), sffxs{}, []operand.Op{xyz, k, v}) } -// VPCMPEQD: Compare Packed Doubleword Data for Equality. +// VSCATTERQPD: Scatter Packed Double-Precision Floating-Point Values with Signed Quadword Indices. // // Forms: // -// VPCMPEQD xmm xmm xmm -// VPCMPEQD m128 xmm xmm -// VPCMPEQD ymm ymm ymm -// VPCMPEQD m256 ymm ymm -func VPCMPEQD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPEQD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPEQD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPEQD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - CancellingInputs: true, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPEQD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPCMPEQD: bad operands") +// VSCATTERQPD xmm k vm64x +// VSCATTERQPD ymm k vm64y +// VSCATTERQPD zmm k vm64z +func VSCATTERQPD(xyz, k, v operand.Op) (*intrep.Instruction, error) { + return build(opcVSCATTERQPD.Forms(), sffxs{}, []operand.Op{xyz, k, v}) } -// VPCMPEQQ: Compare Packed Quadword Data for Equality. +// VSCATTERQPS: Scatter Packed Single-Precision Floating-Point Values with Signed Quadword Indices. // // Forms: // -// VPCMPEQQ xmm xmm xmm -// VPCMPEQQ m128 xmm xmm -// VPCMPEQQ ymm ymm ymm -// VPCMPEQQ m256 ymm ymm -func VPCMPEQQ(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPEQQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPEQQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPEQQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - CancellingInputs: true, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPEQQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPCMPEQQ: bad operands") +// VSCATTERQPS xmm k vm64x +// VSCATTERQPS xmm k vm64y +// VSCATTERQPS ymm k vm64z +func VSCATTERQPS(xy, k, v operand.Op) (*intrep.Instruction, error) { + return build(opcVSCATTERQPS.Forms(), sffxs{}, []operand.Op{xy, k, v}) } -// VPCMPEQW: Compare Packed Word Data for Equality. +// VSHUFF32X4: Shuffle 128-Bit Packed Single-Precision Floating-Point Values. // // Forms: // -// VPCMPEQW xmm xmm xmm -// VPCMPEQW m128 xmm xmm -// VPCMPEQW ymm ymm ymm -// VPCMPEQW m256 ymm ymm -func VPCMPEQW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPEQW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPEQW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPEQW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - CancellingInputs: true, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPEQW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPCMPEQW: bad operands") +// VSHUFF32X4 imm8 m256 ymm k ymm +// VSHUFF32X4 imm8 m256 ymm ymm +// VSHUFF32X4 imm8 ymm ymm k ymm +// VSHUFF32X4 imm8 ymm ymm ymm +// VSHUFF32X4 imm8 m512 zmm k zmm +// VSHUFF32X4 imm8 m512 zmm zmm +// VSHUFF32X4 imm8 zmm zmm k zmm +// VSHUFF32X4 imm8 zmm zmm zmm +func VSHUFF32X4(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSHUFF32X4.Forms(), sffxs{}, ops) } -// VPCMPESTRI: Packed Compare Explicit Length Strings, Return Index. +// VSHUFF32X4_BCST: Shuffle 128-Bit Packed Single-Precision Floating-Point Values (Broadcast). // // Forms: // -// VPCMPESTRI imm8 xmm xmm -// VPCMPESTRI imm8 m128 xmm -func VPCMPESTRI(i, mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VPCMPESTRI", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x, reg.EAX, reg.EDX}, - Outputs: []operand.Op{reg.ECX}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VPCMPESTRI", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x, reg.EAX, reg.EDX}, - Outputs: []operand.Op{reg.ECX}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VPCMPESTRI: bad operands") +// VSHUFF32X4.BCST imm8 m32 ymm k ymm +// VSHUFF32X4.BCST imm8 m32 ymm ymm +// VSHUFF32X4.BCST imm8 m32 zmm k zmm +// VSHUFF32X4.BCST imm8 m32 zmm zmm +func VSHUFF32X4_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSHUFF32X4.Forms(), sffxs{sffxBCST}, ops) } -// VPCMPESTRM: Packed Compare Explicit Length Strings, Return Mask. +// VSHUFF32X4_BCST_Z: Shuffle 128-Bit Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VPCMPESTRM imm8 xmm xmm -// VPCMPESTRM imm8 m128 xmm -func VPCMPESTRM(i, mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VPCMPESTRM", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x, reg.EAX, reg.EDX}, - Outputs: []operand.Op{reg.X0}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VPCMPESTRM", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x, reg.EAX, reg.EDX}, - Outputs: []operand.Op{reg.X0}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VPCMPESTRM: bad operands") +// VSHUFF32X4.BCST.Z imm8 m32 ymm k ymm +// VSHUFF32X4.BCST.Z imm8 m32 zmm k zmm +func VSHUFF32X4_BCST_Z(i, m, yz, k, yz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSHUFF32X4.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{i, m, yz, k, yz1}) } -// VPCMPGTB: Compare Packed Signed Byte Integers for Greater Than. +// VSHUFF32X4_Z: Shuffle 128-Bit Packed Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VPCMPGTB xmm xmm xmm -// VPCMPGTB m128 xmm xmm -// VPCMPGTB ymm ymm ymm -// VPCMPGTB m256 ymm ymm -func VPCMPGTB(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPGTB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPGTB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPGTB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - CancellingInputs: true, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPGTB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPCMPGTB: bad operands") +// VSHUFF32X4.Z imm8 m256 ymm k ymm +// VSHUFF32X4.Z imm8 ymm ymm k ymm +// VSHUFF32X4.Z imm8 m512 zmm k zmm +// VSHUFF32X4.Z imm8 zmm zmm k zmm +func VSHUFF32X4_Z(i, myz, yz, k, yz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSHUFF32X4.Forms(), sffxs{sffxZ}, []operand.Op{i, myz, yz, k, yz1}) } -// VPCMPGTD: Compare Packed Signed Doubleword Integers for Greater Than. +// VSHUFF64X2: Shuffle 128-Bit Packed Double-Precision Floating-Point Values. // // Forms: // -// VPCMPGTD xmm xmm xmm -// VPCMPGTD m128 xmm xmm -// VPCMPGTD ymm ymm ymm -// VPCMPGTD m256 ymm ymm -func VPCMPGTD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPGTD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPGTD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPGTD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - CancellingInputs: true, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPGTD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPCMPGTD: bad operands") +// VSHUFF64X2 imm8 m256 ymm k ymm +// VSHUFF64X2 imm8 m256 ymm ymm +// VSHUFF64X2 imm8 ymm ymm k ymm +// VSHUFF64X2 imm8 ymm ymm ymm +// VSHUFF64X2 imm8 m512 zmm k zmm +// VSHUFF64X2 imm8 m512 zmm zmm +// VSHUFF64X2 imm8 zmm zmm k zmm +// VSHUFF64X2 imm8 zmm zmm zmm +func VSHUFF64X2(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSHUFF64X2.Forms(), sffxs{}, ops) } -// VPCMPGTQ: Compare Packed Data for Greater Than. +// VSHUFF64X2_BCST: Shuffle 128-Bit Packed Double-Precision Floating-Point Values (Broadcast). // // Forms: // -// VPCMPGTQ xmm xmm xmm -// VPCMPGTQ m128 xmm xmm -// VPCMPGTQ ymm ymm ymm -// VPCMPGTQ m256 ymm ymm -func VPCMPGTQ(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPGTQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPGTQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPGTQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - CancellingInputs: true, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPGTQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPCMPGTQ: bad operands") +// VSHUFF64X2.BCST imm8 m64 ymm k ymm +// VSHUFF64X2.BCST imm8 m64 ymm ymm +// VSHUFF64X2.BCST imm8 m64 zmm k zmm +// VSHUFF64X2.BCST imm8 m64 zmm zmm +func VSHUFF64X2_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSHUFF64X2.Forms(), sffxs{sffxBCST}, ops) } -// VPCMPGTW: Compare Packed Signed Word Integers for Greater Than. +// VSHUFF64X2_BCST_Z: Shuffle 128-Bit Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VPCMPGTW xmm xmm xmm -// VPCMPGTW m128 xmm xmm -// VPCMPGTW ymm ymm ymm -// VPCMPGTW m256 ymm ymm -func VPCMPGTW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPGTW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPGTW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPGTW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - CancellingInputs: true, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPCMPGTW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPCMPGTW: bad operands") +// VSHUFF64X2.BCST.Z imm8 m64 ymm k ymm +// VSHUFF64X2.BCST.Z imm8 m64 zmm k zmm +func VSHUFF64X2_BCST_Z(i, m, yz, k, yz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSHUFF64X2.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{i, m, yz, k, yz1}) } -// VPCMPISTRI: Packed Compare Implicit Length Strings, Return Index. +// VSHUFF64X2_Z: Shuffle 128-Bit Packed Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VPCMPISTRI imm8 xmm xmm -// VPCMPISTRI imm8 m128 xmm -func VPCMPISTRI(i, mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VPCMPISTRI", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{reg.ECX}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VPCMPISTRI", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{reg.ECX}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VPCMPISTRI: bad operands") +// VSHUFF64X2.Z imm8 m256 ymm k ymm +// VSHUFF64X2.Z imm8 ymm ymm k ymm +// VSHUFF64X2.Z imm8 m512 zmm k zmm +// VSHUFF64X2.Z imm8 zmm zmm k zmm +func VSHUFF64X2_Z(i, myz, yz, k, yz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSHUFF64X2.Forms(), sffxs{sffxZ}, []operand.Op{i, myz, yz, k, yz1}) } -// VPCMPISTRM: Packed Compare Implicit Length Strings, Return Mask. +// VSHUFI32X4: Shuffle 128-Bit Packed Doubleword Integer Values. // // Forms: // -// VPCMPISTRM imm8 xmm xmm -// VPCMPISTRM imm8 m128 xmm -func VPCMPISTRM(i, mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VPCMPISTRM", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{reg.X0}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VPCMPISTRM", - Operands: []operand.Op{i, mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{reg.X0}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VPCMPISTRM: bad operands") +// VSHUFI32X4 imm8 m256 ymm k ymm +// VSHUFI32X4 imm8 m256 ymm ymm +// VSHUFI32X4 imm8 ymm ymm k ymm +// VSHUFI32X4 imm8 ymm ymm ymm +// VSHUFI32X4 imm8 m512 zmm k zmm +// VSHUFI32X4 imm8 m512 zmm zmm +// VSHUFI32X4 imm8 zmm zmm k zmm +// VSHUFI32X4 imm8 zmm zmm zmm +func VSHUFI32X4(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSHUFI32X4.Forms(), sffxs{}, ops) } -// VPERM2F128: Permute Floating-Point Values. +// VSHUFI32X4_BCST: Shuffle 128-Bit Packed Doubleword Integer Values (Broadcast). // // Forms: // -// VPERM2F128 imm8 ymm ymm ymm -// VPERM2F128 imm8 m256 ymm ymm -func VPERM2F128(i, my, y, y1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsYMM(my) && operand.IsYMM(y) && operand.IsYMM(y1): - return &intrep.Instruction{ - Opcode: "VPERM2F128", - Operands: []operand.Op{i, my, y, y1}, - Inputs: []operand.Op{my, y}, - Outputs: []operand.Op{y1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM256(my) && operand.IsYMM(y) && operand.IsYMM(y1): - return &intrep.Instruction{ - Opcode: "VPERM2F128", - Operands: []operand.Op{i, my, y, y1}, - Inputs: []operand.Op{my, y}, - Outputs: []operand.Op{y1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VPERM2F128: bad operands") +// VSHUFI32X4.BCST imm8 m32 ymm k ymm +// VSHUFI32X4.BCST imm8 m32 ymm ymm +// VSHUFI32X4.BCST imm8 m32 zmm k zmm +// VSHUFI32X4.BCST imm8 m32 zmm zmm +func VSHUFI32X4_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSHUFI32X4.Forms(), sffxs{sffxBCST}, ops) } -// VPERM2I128: Permute 128-Bit Integer Values. +// VSHUFI32X4_BCST_Z: Shuffle 128-Bit Packed Doubleword Integer Values (Broadcast, Zeroing Masking). // // Forms: // -// VPERM2I128 imm8 ymm ymm ymm -// VPERM2I128 imm8 m256 ymm ymm -func VPERM2I128(i, my, y, y1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsYMM(my) && operand.IsYMM(y) && operand.IsYMM(y1): - return &intrep.Instruction{ - Opcode: "VPERM2I128", - Operands: []operand.Op{i, my, y, y1}, - Inputs: []operand.Op{my, y}, - Outputs: []operand.Op{y1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsIMM8(i) && operand.IsM256(my) && operand.IsYMM(y) && operand.IsYMM(y1): - return &intrep.Instruction{ - Opcode: "VPERM2I128", - Operands: []operand.Op{i, my, y, y1}, - Inputs: []operand.Op{my, y}, - Outputs: []operand.Op{y1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPERM2I128: bad operands") +// VSHUFI32X4.BCST.Z imm8 m32 ymm k ymm +// VSHUFI32X4.BCST.Z imm8 m32 zmm k zmm +func VSHUFI32X4_BCST_Z(i, m, yz, k, yz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSHUFI32X4.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{i, m, yz, k, yz1}) } -// VPERMD: Permute Doubleword Integers. +// VSHUFI32X4_Z: Shuffle 128-Bit Packed Doubleword Integer Values (Zeroing Masking). // // Forms: // -// VPERMD ymm ymm ymm -// VPERMD m256 ymm ymm -func VPERMD(my, y, y1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsYMM(my) && operand.IsYMM(y) && operand.IsYMM(y1): - return &intrep.Instruction{ - Opcode: "VPERMD", - Operands: []operand.Op{my, y, y1}, - Inputs: []operand.Op{my, y}, - Outputs: []operand.Op{y1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(my) && operand.IsYMM(y) && operand.IsYMM(y1): - return &intrep.Instruction{ - Opcode: "VPERMD", - Operands: []operand.Op{my, y, y1}, - Inputs: []operand.Op{my, y}, - Outputs: []operand.Op{y1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPERMD: bad operands") +// VSHUFI32X4.Z imm8 m256 ymm k ymm +// VSHUFI32X4.Z imm8 ymm ymm k ymm +// VSHUFI32X4.Z imm8 m512 zmm k zmm +// VSHUFI32X4.Z imm8 zmm zmm k zmm +func VSHUFI32X4_Z(i, myz, yz, k, yz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSHUFI32X4.Forms(), sffxs{sffxZ}, []operand.Op{i, myz, yz, k, yz1}) } -// VPERMILPD: Permute Double-Precision Floating-Point Values. +// VSHUFI64X2: Shuffle 128-Bit Packed Quadword Integer Values. // // Forms: // -// VPERMILPD imm8 xmm xmm -// VPERMILPD xmm xmm xmm -// VPERMILPD m128 xmm xmm -// VPERMILPD imm8 m128 xmm -// VPERMILPD imm8 ymm ymm -// VPERMILPD ymm ymm ymm -// VPERMILPD m256 ymm ymm -// VPERMILPD imm8 m256 ymm -func VPERMILPD(imxy, mxy, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(imxy) && operand.IsXMM(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPERMILPD", - Operands: []operand.Op{imxy, mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(imxy) && operand.IsXMM(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPERMILPD", - Operands: []operand.Op{imxy, mxy, xy}, - Inputs: []operand.Op{imxy, mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(imxy) && operand.IsXMM(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPERMILPD", - Operands: []operand.Op{imxy, mxy, xy}, - Inputs: []operand.Op{imxy, mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(imxy) && operand.IsM128(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPERMILPD", - Operands: []operand.Op{imxy, mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(imxy) && operand.IsYMM(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPERMILPD", - Operands: []operand.Op{imxy, mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(imxy) && operand.IsYMM(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPERMILPD", - Operands: []operand.Op{imxy, mxy, xy}, - Inputs: []operand.Op{imxy, mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(imxy) && operand.IsYMM(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPERMILPD", - Operands: []operand.Op{imxy, mxy, xy}, - Inputs: []operand.Op{imxy, mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(imxy) && operand.IsM256(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPERMILPD", - Operands: []operand.Op{imxy, mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VPERMILPD: bad operands") +// VSHUFI64X2 imm8 m256 ymm k ymm +// VSHUFI64X2 imm8 m256 ymm ymm +// VSHUFI64X2 imm8 ymm ymm k ymm +// VSHUFI64X2 imm8 ymm ymm ymm +// VSHUFI64X2 imm8 m512 zmm k zmm +// VSHUFI64X2 imm8 m512 zmm zmm +// VSHUFI64X2 imm8 zmm zmm k zmm +// VSHUFI64X2 imm8 zmm zmm zmm +func VSHUFI64X2(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSHUFI64X2.Forms(), sffxs{}, ops) } -// VPERMILPS: Permute Single-Precision Floating-Point Values. +// VSHUFI64X2_BCST: Shuffle 128-Bit Packed Quadword Integer Values (Broadcast). // // Forms: // -// VPERMILPS imm8 xmm xmm -// VPERMILPS xmm xmm xmm -// VPERMILPS m128 xmm xmm -// VPERMILPS imm8 m128 xmm -// VPERMILPS imm8 ymm ymm -// VPERMILPS ymm ymm ymm -// VPERMILPS m256 ymm ymm -// VPERMILPS imm8 m256 ymm -func VPERMILPS(imxy, mxy, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(imxy) && operand.IsXMM(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPERMILPS", - Operands: []operand.Op{imxy, mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(imxy) && operand.IsXMM(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPERMILPS", - Operands: []operand.Op{imxy, mxy, xy}, - Inputs: []operand.Op{imxy, mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(imxy) && operand.IsXMM(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPERMILPS", - Operands: []operand.Op{imxy, mxy, xy}, - Inputs: []operand.Op{imxy, mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(imxy) && operand.IsM128(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPERMILPS", - Operands: []operand.Op{imxy, mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(imxy) && operand.IsYMM(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPERMILPS", - Operands: []operand.Op{imxy, mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(imxy) && operand.IsYMM(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPERMILPS", - Operands: []operand.Op{imxy, mxy, xy}, - Inputs: []operand.Op{imxy, mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(imxy) && operand.IsYMM(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPERMILPS", - Operands: []operand.Op{imxy, mxy, xy}, - Inputs: []operand.Op{imxy, mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(imxy) && operand.IsM256(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPERMILPS", - Operands: []operand.Op{imxy, mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VPERMILPS: bad operands") +// VSHUFI64X2.BCST imm8 m64 ymm k ymm +// VSHUFI64X2.BCST imm8 m64 ymm ymm +// VSHUFI64X2.BCST imm8 m64 zmm k zmm +// VSHUFI64X2.BCST imm8 m64 zmm zmm +func VSHUFI64X2_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSHUFI64X2.Forms(), sffxs{sffxBCST}, ops) } -// VPERMPD: Permute Double-Precision Floating-Point Elements. +// VSHUFI64X2_BCST_Z: Shuffle 128-Bit Packed Quadword Integer Values (Broadcast, Zeroing Masking). // // Forms: // -// VPERMPD imm8 ymm ymm -// VPERMPD imm8 m256 ymm -func VPERMPD(i, my, y operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsYMM(my) && operand.IsYMM(y): - return &intrep.Instruction{ - Opcode: "VPERMPD", - Operands: []operand.Op{i, my, y}, - Inputs: []operand.Op{my}, - Outputs: []operand.Op{y}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsIMM8(i) && operand.IsM256(my) && operand.IsYMM(y): - return &intrep.Instruction{ - Opcode: "VPERMPD", - Operands: []operand.Op{i, my, y}, - Inputs: []operand.Op{my}, - Outputs: []operand.Op{y}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPERMPD: bad operands") +// VSHUFI64X2.BCST.Z imm8 m64 ymm k ymm +// VSHUFI64X2.BCST.Z imm8 m64 zmm k zmm +func VSHUFI64X2_BCST_Z(i, m, yz, k, yz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSHUFI64X2.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{i, m, yz, k, yz1}) } -// VPERMPS: Permute Single-Precision Floating-Point Elements. +// VSHUFI64X2_Z: Shuffle 128-Bit Packed Quadword Integer Values (Zeroing Masking). // // Forms: // -// VPERMPS ymm ymm ymm -// VPERMPS m256 ymm ymm -func VPERMPS(my, y, y1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsYMM(my) && operand.IsYMM(y) && operand.IsYMM(y1): - return &intrep.Instruction{ - Opcode: "VPERMPS", - Operands: []operand.Op{my, y, y1}, - Inputs: []operand.Op{my, y}, - Outputs: []operand.Op{y1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(my) && operand.IsYMM(y) && operand.IsYMM(y1): - return &intrep.Instruction{ - Opcode: "VPERMPS", - Operands: []operand.Op{my, y, y1}, - Inputs: []operand.Op{my, y}, - Outputs: []operand.Op{y1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPERMPS: bad operands") +// VSHUFI64X2.Z imm8 m256 ymm k ymm +// VSHUFI64X2.Z imm8 ymm ymm k ymm +// VSHUFI64X2.Z imm8 m512 zmm k zmm +// VSHUFI64X2.Z imm8 zmm zmm k zmm +func VSHUFI64X2_Z(i, myz, yz, k, yz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSHUFI64X2.Forms(), sffxs{sffxZ}, []operand.Op{i, myz, yz, k, yz1}) } -// VPERMQ: Permute Quadword Integers. +// VSHUFPD: Shuffle Packed Double-Precision Floating-Point Values. // // Forms: // -// VPERMQ imm8 ymm ymm -// VPERMQ imm8 m256 ymm -func VPERMQ(i, my, y operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsYMM(my) && operand.IsYMM(y): - return &intrep.Instruction{ - Opcode: "VPERMQ", - Operands: []operand.Op{i, my, y}, - Inputs: []operand.Op{my}, - Outputs: []operand.Op{y}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsIMM8(i) && operand.IsM256(my) && operand.IsYMM(y): - return &intrep.Instruction{ - Opcode: "VPERMQ", - Operands: []operand.Op{i, my, y}, - Inputs: []operand.Op{my}, - Outputs: []operand.Op{y}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPERMQ: bad operands") +// VSHUFPD imm8 m128 xmm xmm +// VSHUFPD imm8 m256 ymm ymm +// VSHUFPD imm8 xmm xmm xmm +// VSHUFPD imm8 ymm ymm ymm +// VSHUFPD imm8 m128 xmm k xmm +// VSHUFPD imm8 m256 ymm k ymm +// VSHUFPD imm8 xmm xmm k xmm +// VSHUFPD imm8 ymm ymm k ymm +// VSHUFPD imm8 m512 zmm k zmm +// VSHUFPD imm8 m512 zmm zmm +// VSHUFPD imm8 zmm zmm k zmm +// VSHUFPD imm8 zmm zmm zmm +func VSHUFPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSHUFPD.Forms(), sffxs{}, ops) } -// VPEXTRB: Extract Byte. +// VSHUFPD_BCST: Shuffle Packed Double-Precision Floating-Point Values (Broadcast). // // Forms: // -// VPEXTRB imm8 xmm r32 -// VPEXTRB imm8 xmm m8 -func VPEXTRB(i, x, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(x) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "VPEXTRB", - Operands: []operand.Op{i, x, mr}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{mr}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsXMM(x) && operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "VPEXTRB", - Operands: []operand.Op{i, x, mr}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{mr}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VPEXTRB: bad operands") +// VSHUFPD.BCST imm8 m64 xmm k xmm +// VSHUFPD.BCST imm8 m64 xmm xmm +// VSHUFPD.BCST imm8 m64 ymm k ymm +// VSHUFPD.BCST imm8 m64 ymm ymm +// VSHUFPD.BCST imm8 m64 zmm k zmm +// VSHUFPD.BCST imm8 m64 zmm zmm +func VSHUFPD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSHUFPD.Forms(), sffxs{sffxBCST}, ops) } -// VPEXTRD: Extract Doubleword. +// VSHUFPD_BCST_Z: Shuffle Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VPEXTRD imm8 xmm r32 -// VPEXTRD imm8 xmm m32 -func VPEXTRD(i, x, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(x) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "VPEXTRD", - Operands: []operand.Op{i, x, mr}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{mr}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsXMM(x) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "VPEXTRD", - Operands: []operand.Op{i, x, mr}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{mr}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VPEXTRD: bad operands") +// VSHUFPD.BCST.Z imm8 m64 xmm k xmm +// VSHUFPD.BCST.Z imm8 m64 ymm k ymm +// VSHUFPD.BCST.Z imm8 m64 zmm k zmm +func VSHUFPD_BCST_Z(i, m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSHUFPD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{i, m, xyz, k, xyz1}) } -// VPEXTRQ: Extract Quadword. +// VSHUFPD_Z: Shuffle Packed Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VPEXTRQ imm8 xmm r64 -// VPEXTRQ imm8 xmm m64 -func VPEXTRQ(i, x, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(x) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "VPEXTRQ", - Operands: []operand.Op{i, x, mr}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{mr}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsXMM(x) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "VPEXTRQ", - Operands: []operand.Op{i, x, mr}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{mr}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VPEXTRQ: bad operands") +// VSHUFPD.Z imm8 m128 xmm k xmm +// VSHUFPD.Z imm8 m256 ymm k ymm +// VSHUFPD.Z imm8 xmm xmm k xmm +// VSHUFPD.Z imm8 ymm ymm k ymm +// VSHUFPD.Z imm8 m512 zmm k zmm +// VSHUFPD.Z imm8 zmm zmm k zmm +func VSHUFPD_Z(i, mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSHUFPD.Forms(), sffxs{sffxZ}, []operand.Op{i, mxyz, xyz, k, xyz1}) } -// VPEXTRW: Extract Word. +// VSHUFPS: Shuffle Packed Single-Precision Floating-Point Values. // // Forms: // -// VPEXTRW imm8 xmm r32 -// VPEXTRW imm8 xmm m16 -func VPEXTRW(i, x, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(x) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "VPEXTRW", - Operands: []operand.Op{i, x, mr}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{mr}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsXMM(x) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "VPEXTRW", - Operands: []operand.Op{i, x, mr}, - Inputs: []operand.Op{x}, - Outputs: []operand.Op{mr}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VPEXTRW: bad operands") +// VSHUFPS imm8 m128 xmm xmm +// VSHUFPS imm8 m256 ymm ymm +// VSHUFPS imm8 xmm xmm xmm +// VSHUFPS imm8 ymm ymm ymm +// VSHUFPS imm8 m128 xmm k xmm +// VSHUFPS imm8 m256 ymm k ymm +// VSHUFPS imm8 xmm xmm k xmm +// VSHUFPS imm8 ymm ymm k ymm +// VSHUFPS imm8 m512 zmm k zmm +// VSHUFPS imm8 m512 zmm zmm +// VSHUFPS imm8 zmm zmm k zmm +// VSHUFPS imm8 zmm zmm zmm +func VSHUFPS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSHUFPS.Forms(), sffxs{}, ops) } -// VPGATHERDD: Gather Packed Doubleword Values Using Signed Doubleword Indices. +// VSHUFPS_BCST: Shuffle Packed Single-Precision Floating-Point Values (Broadcast). // // Forms: // -// VPGATHERDD xmm vm32x xmm -// VPGATHERDD ymm vm32y ymm -func VPGATHERDD(xy, v, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(xy) && operand.IsVM32X(v) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPGATHERDD", - Operands: []operand.Op{xy, v, xy1}, - Inputs: []operand.Op{xy, v, xy1}, - Outputs: []operand.Op{xy, xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsYMM(xy) && operand.IsVM32Y(v) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPGATHERDD", - Operands: []operand.Op{xy, v, xy1}, - Inputs: []operand.Op{xy, v, xy1}, - Outputs: []operand.Op{xy, xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPGATHERDD: bad operands") +// VSHUFPS.BCST imm8 m32 xmm k xmm +// VSHUFPS.BCST imm8 m32 xmm xmm +// VSHUFPS.BCST imm8 m32 ymm k ymm +// VSHUFPS.BCST imm8 m32 ymm ymm +// VSHUFPS.BCST imm8 m32 zmm k zmm +// VSHUFPS.BCST imm8 m32 zmm zmm +func VSHUFPS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSHUFPS.Forms(), sffxs{sffxBCST}, ops) } -// VPGATHERDQ: Gather Packed Quadword Values Using Signed Doubleword Indices. +// VSHUFPS_BCST_Z: Shuffle Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VPGATHERDQ xmm vm32x xmm -// VPGATHERDQ ymm vm32x ymm -func VPGATHERDQ(xy, v, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(xy) && operand.IsVM32X(v) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPGATHERDQ", - Operands: []operand.Op{xy, v, xy1}, - Inputs: []operand.Op{xy, v, xy1}, - Outputs: []operand.Op{xy, xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsYMM(xy) && operand.IsVM32X(v) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPGATHERDQ", - Operands: []operand.Op{xy, v, xy1}, - Inputs: []operand.Op{xy, v, xy1}, - Outputs: []operand.Op{xy, xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPGATHERDQ: bad operands") +// VSHUFPS.BCST.Z imm8 m32 xmm k xmm +// VSHUFPS.BCST.Z imm8 m32 ymm k ymm +// VSHUFPS.BCST.Z imm8 m32 zmm k zmm +func VSHUFPS_BCST_Z(i, m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSHUFPS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{i, m, xyz, k, xyz1}) } -// VPGATHERQD: Gather Packed Doubleword Values Using Signed Quadword Indices. +// VSHUFPS_Z: Shuffle Packed Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VPGATHERQD xmm vm64x xmm -// VPGATHERQD xmm vm64y xmm -func VPGATHERQD(x, v, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(x) && operand.IsVM64X(v) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VPGATHERQD", - Operands: []operand.Op{x, v, x1}, - Inputs: []operand.Op{x, v, x1}, - Outputs: []operand.Op{x, x1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsXMM(x) && operand.IsVM64Y(v) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VPGATHERQD", - Operands: []operand.Op{x, v, x1}, - Inputs: []operand.Op{x, v, x1}, - Outputs: []operand.Op{x, x1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPGATHERQD: bad operands") +// VSHUFPS.Z imm8 m128 xmm k xmm +// VSHUFPS.Z imm8 m256 ymm k ymm +// VSHUFPS.Z imm8 xmm xmm k xmm +// VSHUFPS.Z imm8 ymm ymm k ymm +// VSHUFPS.Z imm8 m512 zmm k zmm +// VSHUFPS.Z imm8 zmm zmm k zmm +func VSHUFPS_Z(i, mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSHUFPS.Forms(), sffxs{sffxZ}, []operand.Op{i, mxyz, xyz, k, xyz1}) } -// VPGATHERQQ: Gather Packed Quadword Values Using Signed Quadword Indices. +// VSQRTPD: Compute Square Roots of Packed Double-Precision Floating-Point Values. // // Forms: // -// VPGATHERQQ xmm vm64x xmm -// VPGATHERQQ ymm vm64y ymm -func VPGATHERQQ(xy, v, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(xy) && operand.IsVM64X(v) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPGATHERQQ", - Operands: []operand.Op{xy, v, xy1}, - Inputs: []operand.Op{xy, v, xy1}, - Outputs: []operand.Op{xy, xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsYMM(xy) && operand.IsVM64Y(v) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPGATHERQQ", - Operands: []operand.Op{xy, v, xy1}, - Inputs: []operand.Op{xy, v, xy1}, - Outputs: []operand.Op{xy, xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPGATHERQQ: bad operands") +// VSQRTPD m128 xmm +// VSQRTPD m256 ymm +// VSQRTPD xmm xmm +// VSQRTPD ymm ymm +// VSQRTPD m128 k xmm +// VSQRTPD m256 k ymm +// VSQRTPD xmm k xmm +// VSQRTPD ymm k ymm +// VSQRTPD m512 k zmm +// VSQRTPD m512 zmm +// VSQRTPD zmm k zmm +// VSQRTPD zmm zmm +func VSQRTPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTPD.Forms(), sffxs{}, ops) } -// VPHADDD: Packed Horizontal Add Doubleword Integer. +// VSQRTPD_BCST: Compute Square Roots of Packed Double-Precision Floating-Point Values (Broadcast). // // Forms: // -// VPHADDD xmm xmm xmm -// VPHADDD m128 xmm xmm -// VPHADDD ymm ymm ymm -// VPHADDD m256 ymm ymm -func VPHADDD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPHADDD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPHADDD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPHADDD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPHADDD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPHADDD: bad operands") +// VSQRTPD.BCST m32 k xmm +// VSQRTPD.BCST m32 k ymm +// VSQRTPD.BCST m32 xmm +// VSQRTPD.BCST m32 ymm +// VSQRTPD.BCST m64 k zmm +// VSQRTPD.BCST m64 zmm +func VSQRTPD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTPD.Forms(), sffxs{sffxBCST}, ops) } -// VPHADDSW: Packed Horizontal Add Signed Word Integers with Signed Saturation. +// VSQRTPD_BCST_Z: Compute Square Roots of Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VPHADDSW xmm xmm xmm -// VPHADDSW m128 xmm xmm -// VPHADDSW ymm ymm ymm -// VPHADDSW m256 ymm ymm -func VPHADDSW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPHADDSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPHADDSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPHADDSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPHADDSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPHADDSW: bad operands") +// VSQRTPD.BCST.Z m32 k xmm +// VSQRTPD.BCST.Z m32 k ymm +// VSQRTPD.BCST.Z m64 k zmm +func VSQRTPD_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTPD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) } -// VPHADDW: Packed Horizontal Add Word Integers. +// VSQRTPD_RD_SAE: Compute Square Roots of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). // // Forms: // -// VPHADDW xmm xmm xmm -// VPHADDW m128 xmm xmm -// VPHADDW ymm ymm ymm -// VPHADDW m256 ymm ymm -func VPHADDW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPHADDW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPHADDW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPHADDW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPHADDW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPHADDW: bad operands") +// VSQRTPD.RD_SAE zmm k zmm +// VSQRTPD.RD_SAE zmm zmm +func VSQRTPD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTPD.Forms(), sffxs{sffxRD_SAE}, ops) } -// VPHMINPOSUW: Packed Horizontal Minimum of Unsigned Word Integers. +// VSQRTPD_RD_SAE_Z: Compute Square Roots of Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VPHMINPOSUW xmm xmm -// VPHMINPOSUW m128 xmm -func VPHMINPOSUW(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VPHMINPOSUW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VPHMINPOSUW", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{x}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VPHMINPOSUW: bad operands") +// VSQRTPD.RD_SAE.Z zmm k zmm +func VSQRTPD_RD_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTPD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, k, z1}) } -// VPHSUBD: Packed Horizontal Subtract Doubleword Integers. +// VSQRTPD_RN_SAE: Compute Square Roots of Packed Double-Precision Floating-Point Values (Round Towards Nearest). // // Forms: // -// VPHSUBD xmm xmm xmm -// VPHSUBD m128 xmm xmm -// VPHSUBD ymm ymm ymm -// VPHSUBD m256 ymm ymm -func VPHSUBD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPHSUBD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPHSUBD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPHSUBD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - CancellingInputs: true, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPHSUBD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPHSUBD: bad operands") +// VSQRTPD.RN_SAE zmm k zmm +// VSQRTPD.RN_SAE zmm zmm +func VSQRTPD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTPD.Forms(), sffxs{sffxRN_SAE}, ops) } -// VPHSUBSW: Packed Horizontal Subtract Signed Word Integers with Signed Saturation. +// VSQRTPD_RN_SAE_Z: Compute Square Roots of Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VPHSUBSW xmm xmm xmm -// VPHSUBSW m128 xmm xmm -// VPHSUBSW ymm ymm ymm -// VPHSUBSW m256 ymm ymm -func VPHSUBSW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPHSUBSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPHSUBSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPHSUBSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - CancellingInputs: true, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPHSUBSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPHSUBSW: bad operands") +// VSQRTPD.RN_SAE.Z zmm k zmm +func VSQRTPD_RN_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTPD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, k, z1}) } -// VPHSUBW: Packed Horizontal Subtract Word Integers. +// VSQRTPD_RU_SAE: Compute Square Roots of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). // // Forms: // -// VPHSUBW xmm xmm xmm -// VPHSUBW m128 xmm xmm -// VPHSUBW ymm ymm ymm -// VPHSUBW m256 ymm ymm -func VPHSUBW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPHSUBW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPHSUBW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPHSUBW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - CancellingInputs: true, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPHSUBW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPHSUBW: bad operands") +// VSQRTPD.RU_SAE zmm k zmm +// VSQRTPD.RU_SAE zmm zmm +func VSQRTPD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTPD.Forms(), sffxs{sffxRU_SAE}, ops) } -// VPINSRB: Insert Byte. +// VSQRTPD_RU_SAE_Z: Compute Square Roots of Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VPINSRB imm8 r32 xmm xmm -// VPINSRB imm8 m8 xmm xmm -func VPINSRB(i, mr, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsR32(mr) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VPINSRB", - Operands: []operand.Op{i, mr, x, x1}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM8(mr) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VPINSRB", - Operands: []operand.Op{i, mr, x, x1}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VPINSRB: bad operands") +// VSQRTPD.RU_SAE.Z zmm k zmm +func VSQRTPD_RU_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTPD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, k, z1}) } -// VPINSRD: Insert Doubleword. +// VSQRTPD_RZ_SAE: Compute Square Roots of Packed Double-Precision Floating-Point Values (Round Towards Zero). // // Forms: // -// VPINSRD imm8 r32 xmm xmm -// VPINSRD imm8 m32 xmm xmm -func VPINSRD(i, mr, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsR32(mr) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VPINSRD", - Operands: []operand.Op{i, mr, x, x1}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM32(mr) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VPINSRD", - Operands: []operand.Op{i, mr, x, x1}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VPINSRD: bad operands") +// VSQRTPD.RZ_SAE zmm k zmm +// VSQRTPD.RZ_SAE zmm zmm +func VSQRTPD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTPD.Forms(), sffxs{sffxRZ_SAE}, ops) } -// VPINSRQ: Insert Quadword. +// VSQRTPD_RZ_SAE_Z: Compute Square Roots of Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). // // Forms: // -// VPINSRQ imm8 r64 xmm xmm -// VPINSRQ imm8 m64 xmm xmm -func VPINSRQ(i, mr, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsR64(mr) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VPINSRQ", - Operands: []operand.Op{i, mr, x, x1}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM64(mr) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VPINSRQ", - Operands: []operand.Op{i, mr, x, x1}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VPINSRQ: bad operands") +// VSQRTPD.RZ_SAE.Z zmm k zmm +func VSQRTPD_RZ_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTPD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, k, z1}) } -// VPINSRW: Insert Word. +// VSQRTPD_Z: Compute Square Roots of Packed Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VPINSRW imm8 r32 xmm xmm -// VPINSRW imm8 m16 xmm xmm -func VPINSRW(i, mr, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsR32(mr) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VPINSRW", - Operands: []operand.Op{i, mr, x, x1}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM16(mr) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VPINSRW", - Operands: []operand.Op{i, mr, x, x1}, - Inputs: []operand.Op{mr, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VPINSRW: bad operands") +// VSQRTPD.Z m128 k xmm +// VSQRTPD.Z m256 k ymm +// VSQRTPD.Z xmm k xmm +// VSQRTPD.Z ymm k ymm +// VSQRTPD.Z m512 k zmm +// VSQRTPD.Z zmm k zmm +func VSQRTPD_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTPD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) } -// VPMADDUBSW: Multiply and Add Packed Signed and Unsigned Byte Integers. +// VSQRTPS: Compute Square Roots of Packed Single-Precision Floating-Point Values. // // Forms: // -// VPMADDUBSW xmm xmm xmm -// VPMADDUBSW m128 xmm xmm -// VPMADDUBSW ymm ymm ymm -// VPMADDUBSW m256 ymm ymm -func VPMADDUBSW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMADDUBSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMADDUBSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMADDUBSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMADDUBSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMADDUBSW: bad operands") +// VSQRTPS m128 xmm +// VSQRTPS m256 ymm +// VSQRTPS xmm xmm +// VSQRTPS ymm ymm +// VSQRTPS m128 k xmm +// VSQRTPS m256 k ymm +// VSQRTPS xmm k xmm +// VSQRTPS ymm k ymm +// VSQRTPS m512 k zmm +// VSQRTPS m512 zmm +// VSQRTPS zmm k zmm +// VSQRTPS zmm zmm +func VSQRTPS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTPS.Forms(), sffxs{}, ops) } -// VPMADDWD: Multiply and Add Packed Signed Word Integers. +// VSQRTPS_BCST: Compute Square Roots of Packed Single-Precision Floating-Point Values (Broadcast). // // Forms: // -// VPMADDWD xmm xmm xmm -// VPMADDWD m128 xmm xmm -// VPMADDWD ymm ymm ymm -// VPMADDWD m256 ymm ymm -func VPMADDWD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMADDWD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMADDWD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMADDWD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMADDWD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMADDWD: bad operands") +// VSQRTPS.BCST m32 k xmm +// VSQRTPS.BCST m32 k ymm +// VSQRTPS.BCST m32 xmm +// VSQRTPS.BCST m32 ymm +// VSQRTPS.BCST m32 k zmm +// VSQRTPS.BCST m32 zmm +func VSQRTPS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTPS.Forms(), sffxs{sffxBCST}, ops) } -// VPMASKMOVD: Conditional Move Packed Doubleword Integers. +// VSQRTPS_BCST_Z: Compute Square Roots of Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VPMASKMOVD m128 xmm xmm -// VPMASKMOVD m256 ymm ymm -// VPMASKMOVD xmm xmm m128 -// VPMASKMOVD ymm ymm m256 -func VPMASKMOVD(mxy, xy, mxy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(mxy1): - return &intrep.Instruction{ - Opcode: "VPMASKMOVD", - Operands: []operand.Op{mxy, xy, mxy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(mxy1): - return &intrep.Instruction{ - Opcode: "VPMASKMOVD", - Operands: []operand.Op{mxy, xy, mxy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsM128(mxy1): - return &intrep.Instruction{ - Opcode: "VPMASKMOVD", - Operands: []operand.Op{mxy, xy, mxy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsM256(mxy1): - return &intrep.Instruction{ - Opcode: "VPMASKMOVD", - Operands: []operand.Op{mxy, xy, mxy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMASKMOVD: bad operands") +// VSQRTPS.BCST.Z m32 k xmm +// VSQRTPS.BCST.Z m32 k ymm +// VSQRTPS.BCST.Z m32 k zmm +func VSQRTPS_BCST_Z(m, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTPS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, k, xyz}) } -// VPMASKMOVQ: Conditional Move Packed Quadword Integers. +// VSQRTPS_RD_SAE: Compute Square Roots of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). // // Forms: // -// VPMASKMOVQ m128 xmm xmm -// VPMASKMOVQ m256 ymm ymm -// VPMASKMOVQ xmm xmm m128 -// VPMASKMOVQ ymm ymm m256 -func VPMASKMOVQ(mxy, xy, mxy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(mxy1): - return &intrep.Instruction{ - Opcode: "VPMASKMOVQ", - Operands: []operand.Op{mxy, xy, mxy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(mxy1): - return &intrep.Instruction{ - Opcode: "VPMASKMOVQ", - Operands: []operand.Op{mxy, xy, mxy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsM128(mxy1): - return &intrep.Instruction{ - Opcode: "VPMASKMOVQ", - Operands: []operand.Op{mxy, xy, mxy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsM256(mxy1): - return &intrep.Instruction{ - Opcode: "VPMASKMOVQ", - Operands: []operand.Op{mxy, xy, mxy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{mxy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMASKMOVQ: bad operands") +// VSQRTPS.RD_SAE zmm k zmm +// VSQRTPS.RD_SAE zmm zmm +func VSQRTPS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTPS.Forms(), sffxs{sffxRD_SAE}, ops) } -// VPMAXSB: Maximum of Packed Signed Byte Integers. +// VSQRTPS_RD_SAE_Z: Compute Square Roots of Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VPMAXSB xmm xmm xmm -// VPMAXSB m128 xmm xmm -// VPMAXSB ymm ymm ymm -// VPMAXSB m256 ymm ymm -func VPMAXSB(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMAXSB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMAXSB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMAXSB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMAXSB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMAXSB: bad operands") +// VSQRTPS.RD_SAE.Z zmm k zmm +func VSQRTPS_RD_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTPS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, k, z1}) } -// VPMAXSD: Maximum of Packed Signed Doubleword Integers. +// VSQRTPS_RN_SAE: Compute Square Roots of Packed Single-Precision Floating-Point Values (Round Towards Nearest). // // Forms: // -// VPMAXSD xmm xmm xmm -// VPMAXSD m128 xmm xmm -// VPMAXSD ymm ymm ymm -// VPMAXSD m256 ymm ymm -func VPMAXSD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMAXSD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMAXSD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMAXSD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMAXSD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMAXSD: bad operands") +// VSQRTPS.RN_SAE zmm k zmm +// VSQRTPS.RN_SAE zmm zmm +func VSQRTPS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTPS.Forms(), sffxs{sffxRN_SAE}, ops) } -// VPMAXSW: Maximum of Packed Signed Word Integers. +// VSQRTPS_RN_SAE_Z: Compute Square Roots of Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VPMAXSW xmm xmm xmm -// VPMAXSW m128 xmm xmm -// VPMAXSW ymm ymm ymm -// VPMAXSW m256 ymm ymm -func VPMAXSW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMAXSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMAXSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMAXSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMAXSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMAXSW: bad operands") +// VSQRTPS.RN_SAE.Z zmm k zmm +func VSQRTPS_RN_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTPS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, k, z1}) } -// VPMAXUB: Maximum of Packed Unsigned Byte Integers. +// VSQRTPS_RU_SAE: Compute Square Roots of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). // // Forms: // -// VPMAXUB xmm xmm xmm -// VPMAXUB m128 xmm xmm -// VPMAXUB ymm ymm ymm -// VPMAXUB m256 ymm ymm -func VPMAXUB(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMAXUB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMAXUB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMAXUB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMAXUB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMAXUB: bad operands") +// VSQRTPS.RU_SAE zmm k zmm +// VSQRTPS.RU_SAE zmm zmm +func VSQRTPS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTPS.Forms(), sffxs{sffxRU_SAE}, ops) } -// VPMAXUD: Maximum of Packed Unsigned Doubleword Integers. +// VSQRTPS_RU_SAE_Z: Compute Square Roots of Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VPMAXUD xmm xmm xmm -// VPMAXUD m128 xmm xmm -// VPMAXUD ymm ymm ymm -// VPMAXUD m256 ymm ymm -func VPMAXUD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMAXUD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMAXUD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMAXUD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMAXUD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMAXUD: bad operands") +// VSQRTPS.RU_SAE.Z zmm k zmm +func VSQRTPS_RU_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTPS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, k, z1}) } -// VPMAXUW: Maximum of Packed Unsigned Word Integers. +// VSQRTPS_RZ_SAE: Compute Square Roots of Packed Single-Precision Floating-Point Values (Round Towards Zero). // // Forms: // -// VPMAXUW xmm xmm xmm -// VPMAXUW m128 xmm xmm -// VPMAXUW ymm ymm ymm -// VPMAXUW m256 ymm ymm -func VPMAXUW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMAXUW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMAXUW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMAXUW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMAXUW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMAXUW: bad operands") +// VSQRTPS.RZ_SAE zmm k zmm +// VSQRTPS.RZ_SAE zmm zmm +func VSQRTPS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTPS.Forms(), sffxs{sffxRZ_SAE}, ops) } -// VPMINSB: Minimum of Packed Signed Byte Integers. +// VSQRTPS_RZ_SAE_Z: Compute Square Roots of Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). // // Forms: // -// VPMINSB xmm xmm xmm -// VPMINSB m128 xmm xmm -// VPMINSB ymm ymm ymm -// VPMINSB m256 ymm ymm -func VPMINSB(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMINSB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMINSB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMINSB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMINSB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMINSB: bad operands") +// VSQRTPS.RZ_SAE.Z zmm k zmm +func VSQRTPS_RZ_SAE_Z(z, k, z1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTPS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, k, z1}) } -// VPMINSD: Minimum of Packed Signed Doubleword Integers. +// VSQRTPS_Z: Compute Square Roots of Packed Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VPMINSD xmm xmm xmm -// VPMINSD m128 xmm xmm -// VPMINSD ymm ymm ymm -// VPMINSD m256 ymm ymm -func VPMINSD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMINSD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMINSD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMINSD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMINSD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMINSD: bad operands") +// VSQRTPS.Z m128 k xmm +// VSQRTPS.Z m256 k ymm +// VSQRTPS.Z xmm k xmm +// VSQRTPS.Z ymm k ymm +// VSQRTPS.Z m512 k zmm +// VSQRTPS.Z zmm k zmm +func VSQRTPS_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTPS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) } -// VPMINSW: Minimum of Packed Signed Word Integers. +// VSQRTSD: Compute Square Root of Scalar Double-Precision Floating-Point Value. // // Forms: // -// VPMINSW xmm xmm xmm -// VPMINSW m128 xmm xmm -// VPMINSW ymm ymm ymm -// VPMINSW m256 ymm ymm -func VPMINSW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMINSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMINSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMINSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMINSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMINSW: bad operands") +// VSQRTSD m64 xmm xmm +// VSQRTSD xmm xmm xmm +// VSQRTSD m64 xmm k xmm +// VSQRTSD xmm xmm k xmm +func VSQRTSD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTSD.Forms(), sffxs{}, ops) } -// VPMINUB: Minimum of Packed Unsigned Byte Integers. +// VSQRTSD_RD_SAE: Compute Square Root of Scalar Double-Precision Floating-Point Value (Round Towards Negative Infinity). // // Forms: // -// VPMINUB xmm xmm xmm -// VPMINUB m128 xmm xmm -// VPMINUB ymm ymm ymm -// VPMINUB m256 ymm ymm -func VPMINUB(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMINUB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMINUB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMINUB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMINUB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMINUB: bad operands") +// VSQRTSD.RD_SAE xmm xmm k xmm +// VSQRTSD.RD_SAE xmm xmm xmm +func VSQRTSD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTSD.Forms(), sffxs{sffxRD_SAE}, ops) } -// VPMINUD: Minimum of Packed Unsigned Doubleword Integers. +// VSQRTSD_RD_SAE_Z: Compute Square Root of Scalar Double-Precision Floating-Point Value (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VPMINUD xmm xmm xmm -// VPMINUD m128 xmm xmm -// VPMINUD ymm ymm ymm -// VPMINUD m256 ymm ymm -func VPMINUD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMINUD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMINUD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMINUD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMINUD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMINUD: bad operands") +// VSQRTSD.RD_SAE.Z xmm xmm k xmm +func VSQRTSD_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTSD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) } -// VPMINUW: Minimum of Packed Unsigned Word Integers. +// VSQRTSD_RN_SAE: Compute Square Root of Scalar Double-Precision Floating-Point Value (Round Towards Nearest). // // Forms: // -// VPMINUW xmm xmm xmm -// VPMINUW m128 xmm xmm -// VPMINUW ymm ymm ymm -// VPMINUW m256 ymm ymm -func VPMINUW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMINUW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMINUW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMINUW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMINUW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMINUW: bad operands") +// VSQRTSD.RN_SAE xmm xmm k xmm +// VSQRTSD.RN_SAE xmm xmm xmm +func VSQRTSD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTSD.Forms(), sffxs{sffxRN_SAE}, ops) } -// VPMOVMSKB: Move Byte Mask. +// VSQRTSD_RN_SAE_Z: Compute Square Root of Scalar Double-Precision Floating-Point Value (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VPMOVMSKB xmm r32 -// VPMOVMSKB ymm r32 -func VPMOVMSKB(xy, r operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(xy) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "VPMOVMSKB", - Operands: []operand.Op{xy, r}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{r}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(xy) && operand.IsR32(r): - return &intrep.Instruction{ - Opcode: "VPMOVMSKB", - Operands: []operand.Op{xy, r}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{r}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMOVMSKB: bad operands") +// VSQRTSD.RN_SAE.Z xmm xmm k xmm +func VSQRTSD_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTSD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) } -// VPMOVSXBD: Move Packed Byte Integers to Doubleword Integers with Sign Extension. +// VSQRTSD_RU_SAE: Compute Square Root of Scalar Double-Precision Floating-Point Value (Round Towards Positive Infinity). // // Forms: // -// VPMOVSXBD xmm xmm -// VPMOVSXBD m32 xmm -// VPMOVSXBD xmm ymm -// VPMOVSXBD m64 ymm -func VPMOVSXBD(mx, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVSXBD", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVSXBD", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVSXBD", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM64(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVSXBD", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMOVSXBD: bad operands") +// VSQRTSD.RU_SAE xmm xmm k xmm +// VSQRTSD.RU_SAE xmm xmm xmm +func VSQRTSD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTSD.Forms(), sffxs{sffxRU_SAE}, ops) } -// VPMOVSXBQ: Move Packed Byte Integers to Quadword Integers with Sign Extension. +// VSQRTSD_RU_SAE_Z: Compute Square Root of Scalar Double-Precision Floating-Point Value (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VPMOVSXBQ xmm xmm -// VPMOVSXBQ m16 xmm -// VPMOVSXBQ xmm ymm -// VPMOVSXBQ m32 ymm -func VPMOVSXBQ(mx, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVSXBQ", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM16(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVSXBQ", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVSXBQ", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM32(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVSXBQ", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMOVSXBQ: bad operands") +// VSQRTSD.RU_SAE.Z xmm xmm k xmm +func VSQRTSD_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTSD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) } -// VPMOVSXBW: Move Packed Byte Integers to Word Integers with Sign Extension. +// VSQRTSD_RZ_SAE: Compute Square Root of Scalar Double-Precision Floating-Point Value (Round Towards Zero). // // Forms: // -// VPMOVSXBW xmm xmm -// VPMOVSXBW m64 xmm -// VPMOVSXBW xmm ymm -// VPMOVSXBW m128 ymm -func VPMOVSXBW(mx, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVSXBW", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVSXBW", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVSXBW", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM128(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVSXBW", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMOVSXBW: bad operands") +// VSQRTSD.RZ_SAE xmm xmm k xmm +// VSQRTSD.RZ_SAE xmm xmm xmm +func VSQRTSD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTSD.Forms(), sffxs{sffxRZ_SAE}, ops) } -// VPMOVSXDQ: Move Packed Doubleword Integers to Quadword Integers with Sign Extension. +// VSQRTSD_RZ_SAE_Z: Compute Square Root of Scalar Double-Precision Floating-Point Value (Round Towards Zero, Zeroing Masking). // // Forms: // -// VPMOVSXDQ xmm xmm -// VPMOVSXDQ m64 xmm -// VPMOVSXDQ xmm ymm -// VPMOVSXDQ m128 ymm -func VPMOVSXDQ(mx, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVSXDQ", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVSXDQ", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVSXDQ", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM128(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVSXDQ", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMOVSXDQ: bad operands") +// VSQRTSD.RZ_SAE.Z xmm xmm k xmm +func VSQRTSD_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTSD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) } -// VPMOVSXWD: Move Packed Word Integers to Doubleword Integers with Sign Extension. +// VSQRTSD_Z: Compute Square Root of Scalar Double-Precision Floating-Point Value (Zeroing Masking). // // Forms: // -// VPMOVSXWD xmm xmm -// VPMOVSXWD m64 xmm -// VPMOVSXWD xmm ymm -// VPMOVSXWD m128 ymm -func VPMOVSXWD(mx, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVSXWD", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVSXWD", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVSXWD", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM128(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVSXWD", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMOVSXWD: bad operands") +// VSQRTSD.Z m64 xmm k xmm +// VSQRTSD.Z xmm xmm k xmm +func VSQRTSD_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTSD.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) } -// VPMOVSXWQ: Move Packed Word Integers to Quadword Integers with Sign Extension. +// VSQRTSS: Compute Square Root of Scalar Single-Precision Floating-Point Value. // // Forms: // -// VPMOVSXWQ xmm xmm -// VPMOVSXWQ m32 xmm -// VPMOVSXWQ xmm ymm -// VPMOVSXWQ m64 ymm -func VPMOVSXWQ(mx, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVSXWQ", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVSXWQ", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVSXWQ", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM64(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVSXWQ", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMOVSXWQ: bad operands") +// VSQRTSS m32 xmm xmm +// VSQRTSS xmm xmm xmm +// VSQRTSS m32 xmm k xmm +// VSQRTSS xmm xmm k xmm +func VSQRTSS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTSS.Forms(), sffxs{}, ops) } -// VPMOVZXBD: Move Packed Byte Integers to Doubleword Integers with Zero Extension. +// VSQRTSS_RD_SAE: Compute Square Root of Scalar Single-Precision Floating-Point Value (Round Towards Negative Infinity). // // Forms: // -// VPMOVZXBD xmm xmm -// VPMOVZXBD m32 xmm -// VPMOVZXBD xmm ymm -// VPMOVZXBD m64 ymm -func VPMOVZXBD(mx, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVZXBD", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVZXBD", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVZXBD", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM64(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVZXBD", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMOVZXBD: bad operands") +// VSQRTSS.RD_SAE xmm xmm k xmm +// VSQRTSS.RD_SAE xmm xmm xmm +func VSQRTSS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTSS.Forms(), sffxs{sffxRD_SAE}, ops) } -// VPMOVZXBQ: Move Packed Byte Integers to Quadword Integers with Zero Extension. +// VSQRTSS_RD_SAE_Z: Compute Square Root of Scalar Single-Precision Floating-Point Value (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VPMOVZXBQ xmm xmm -// VPMOVZXBQ m16 xmm -// VPMOVZXBQ xmm ymm -// VPMOVZXBQ m32 ymm -func VPMOVZXBQ(mx, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVZXBQ", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM16(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVZXBQ", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVZXBQ", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM32(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVZXBQ", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMOVZXBQ: bad operands") +// VSQRTSS.RD_SAE.Z xmm xmm k xmm +func VSQRTSS_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTSS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) } -// VPMOVZXBW: Move Packed Byte Integers to Word Integers with Zero Extension. +// VSQRTSS_RN_SAE: Compute Square Root of Scalar Single-Precision Floating-Point Value (Round Towards Nearest). // // Forms: // -// VPMOVZXBW xmm xmm -// VPMOVZXBW m64 xmm -// VPMOVZXBW xmm ymm -// VPMOVZXBW m128 ymm -func VPMOVZXBW(mx, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVZXBW", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVZXBW", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVZXBW", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM128(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVZXBW", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMOVZXBW: bad operands") +// VSQRTSS.RN_SAE xmm xmm k xmm +// VSQRTSS.RN_SAE xmm xmm xmm +func VSQRTSS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTSS.Forms(), sffxs{sffxRN_SAE}, ops) } -// VPMOVZXDQ: Move Packed Doubleword Integers to Quadword Integers with Zero Extension. +// VSQRTSS_RN_SAE_Z: Compute Square Root of Scalar Single-Precision Floating-Point Value (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VPMOVZXDQ xmm xmm -// VPMOVZXDQ m64 xmm -// VPMOVZXDQ xmm ymm -// VPMOVZXDQ m128 ymm -func VPMOVZXDQ(mx, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVZXDQ", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVZXDQ", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVZXDQ", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM128(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVZXDQ", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMOVZXDQ: bad operands") +// VSQRTSS.RN_SAE.Z xmm xmm k xmm +func VSQRTSS_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTSS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) } -// VPMOVZXWD: Move Packed Word Integers to Doubleword Integers with Zero Extension. +// VSQRTSS_RU_SAE: Compute Square Root of Scalar Single-Precision Floating-Point Value (Round Towards Positive Infinity). // // Forms: // -// VPMOVZXWD xmm xmm -// VPMOVZXWD m64 xmm -// VPMOVZXWD xmm ymm -// VPMOVZXWD m128 ymm -func VPMOVZXWD(mx, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVZXWD", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVZXWD", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVZXWD", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM128(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVZXWD", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMOVZXWD: bad operands") +// VSQRTSS.RU_SAE xmm xmm k xmm +// VSQRTSS.RU_SAE xmm xmm xmm +func VSQRTSS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTSS.Forms(), sffxs{sffxRU_SAE}, ops) } -// VPMOVZXWQ: Move Packed Word Integers to Quadword Integers with Zero Extension. +// VSQRTSS_RU_SAE_Z: Compute Square Root of Scalar Single-Precision Floating-Point Value (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VPMOVZXWQ xmm xmm -// VPMOVZXWQ m32 xmm -// VPMOVZXWQ xmm ymm -// VPMOVZXWQ m64 ymm -func VPMOVZXWQ(mx, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVZXWQ", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVZXWQ", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVZXWQ", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM64(mx) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPMOVZXWQ", - Operands: []operand.Op{mx, xy}, - Inputs: []operand.Op{mx}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMOVZXWQ: bad operands") +// VSQRTSS.RU_SAE.Z xmm xmm k xmm +func VSQRTSS_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTSS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) } -// VPMULDQ: Multiply Packed Signed Doubleword Integers and Store Quadword Result. +// VSQRTSS_RZ_SAE: Compute Square Root of Scalar Single-Precision Floating-Point Value (Round Towards Zero). // // Forms: // -// VPMULDQ xmm xmm xmm -// VPMULDQ m128 xmm xmm -// VPMULDQ ymm ymm ymm -// VPMULDQ m256 ymm ymm -func VPMULDQ(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMULDQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMULDQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMULDQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMULDQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMULDQ: bad operands") +// VSQRTSS.RZ_SAE xmm xmm k xmm +// VSQRTSS.RZ_SAE xmm xmm xmm +func VSQRTSS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTSS.Forms(), sffxs{sffxRZ_SAE}, ops) } -// VPMULHRSW: Packed Multiply Signed Word Integers and Store High Result with Round and Scale. +// VSQRTSS_RZ_SAE_Z: Compute Square Root of Scalar Single-Precision Floating-Point Value (Round Towards Zero, Zeroing Masking). // // Forms: // -// VPMULHRSW xmm xmm xmm -// VPMULHRSW m128 xmm xmm -// VPMULHRSW ymm ymm ymm -// VPMULHRSW m256 ymm ymm -func VPMULHRSW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMULHRSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMULHRSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMULHRSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMULHRSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMULHRSW: bad operands") +// VSQRTSS.RZ_SAE.Z xmm xmm k xmm +func VSQRTSS_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTSS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) } -// VPMULHUW: Multiply Packed Unsigned Word Integers and Store High Result. +// VSQRTSS_Z: Compute Square Root of Scalar Single-Precision Floating-Point Value (Zeroing Masking). // // Forms: // -// VPMULHUW xmm xmm xmm -// VPMULHUW m128 xmm xmm -// VPMULHUW ymm ymm ymm -// VPMULHUW m256 ymm ymm -func VPMULHUW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMULHUW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMULHUW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMULHUW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMULHUW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMULHUW: bad operands") +// VSQRTSS.Z m32 xmm k xmm +// VSQRTSS.Z xmm xmm k xmm +func VSQRTSS_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSQRTSS.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) } -// VPMULHW: Multiply Packed Signed Word Integers and Store High Result. +// VSTMXCSR: Store MXCSR Register State. // // Forms: // -// VPMULHW xmm xmm xmm -// VPMULHW m128 xmm xmm -// VPMULHW ymm ymm ymm -// VPMULHW m256 ymm ymm -func VPMULHW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMULHW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMULHW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMULHW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMULHW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMULHW: bad operands") +// VSTMXCSR m32 +func VSTMXCSR(m operand.Op) (*intrep.Instruction, error) { + return build(opcVSTMXCSR.Forms(), sffxs{}, []operand.Op{m}) } -// VPMULLD: Multiply Packed Signed Doubleword Integers and Store Low Result. +// VSUBPD: Subtract Packed Double-Precision Floating-Point Values. // // Forms: // -// VPMULLD xmm xmm xmm -// VPMULLD m128 xmm xmm -// VPMULLD ymm ymm ymm -// VPMULLD m256 ymm ymm -func VPMULLD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMULLD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMULLD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMULLD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMULLD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMULLD: bad operands") +// VSUBPD m128 xmm xmm +// VSUBPD m256 ymm ymm +// VSUBPD xmm xmm xmm +// VSUBPD ymm ymm ymm +// VSUBPD m128 xmm k xmm +// VSUBPD m256 ymm k ymm +// VSUBPD xmm xmm k xmm +// VSUBPD ymm ymm k ymm +// VSUBPD m512 zmm k zmm +// VSUBPD m512 zmm zmm +// VSUBPD zmm zmm k zmm +// VSUBPD zmm zmm zmm +func VSUBPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBPD.Forms(), sffxs{}, ops) } -// VPMULLW: Multiply Packed Signed Word Integers and Store Low Result. +// VSUBPD_BCST: Subtract Packed Double-Precision Floating-Point Values (Broadcast). // // Forms: // -// VPMULLW xmm xmm xmm -// VPMULLW m128 xmm xmm -// VPMULLW ymm ymm ymm -// VPMULLW m256 ymm ymm -func VPMULLW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMULLW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMULLW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMULLW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMULLW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMULLW: bad operands") +// VSUBPD.BCST m64 xmm k xmm +// VSUBPD.BCST m64 xmm xmm +// VSUBPD.BCST m64 ymm k ymm +// VSUBPD.BCST m64 ymm ymm +// VSUBPD.BCST m64 zmm k zmm +// VSUBPD.BCST m64 zmm zmm +func VSUBPD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBPD.Forms(), sffxs{sffxBCST}, ops) } -// VPMULUDQ: Multiply Packed Unsigned Doubleword Integers. +// VSUBPD_BCST_Z: Subtract Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VPMULUDQ xmm xmm xmm -// VPMULUDQ m128 xmm xmm -// VPMULUDQ ymm ymm ymm -// VPMULUDQ m256 ymm ymm -func VPMULUDQ(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMULUDQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMULUDQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMULUDQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPMULUDQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPMULUDQ: bad operands") +// VSUBPD.BCST.Z m64 xmm k xmm +// VSUBPD.BCST.Z m64 ymm k ymm +// VSUBPD.BCST.Z m64 zmm k zmm +func VSUBPD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBPD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// VPOR: Packed Bitwise Logical OR. +// VSUBPD_RD_SAE: Subtract Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity). // // Forms: // -// VPOR xmm xmm xmm -// VPOR m128 xmm xmm -// VPOR ymm ymm ymm -// VPOR m256 ymm ymm -func VPOR(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPOR", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPOR", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPOR", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPOR", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPOR: bad operands") +// VSUBPD.RD_SAE zmm zmm k zmm +// VSUBPD.RD_SAE zmm zmm zmm +func VSUBPD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBPD.Forms(), sffxs{sffxRD_SAE}, ops) } -// VPSADBW: Compute Sum of Absolute Differences. +// VSUBPD_RD_SAE_Z: Subtract Packed Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VPSADBW xmm xmm xmm -// VPSADBW m128 xmm xmm -// VPSADBW ymm ymm ymm -// VPSADBW m256 ymm ymm -func VPSADBW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSADBW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSADBW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSADBW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - CancellingInputs: true, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSADBW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPSADBW: bad operands") +// VSUBPD.RD_SAE.Z zmm zmm k zmm +func VSUBPD_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBPD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) } -// VPSHUFB: Packed Shuffle Bytes. +// VSUBPD_RN_SAE: Subtract Packed Double-Precision Floating-Point Values (Round Towards Nearest). // // Forms: // -// VPSHUFB xmm xmm xmm -// VPSHUFB m128 xmm xmm -// VPSHUFB ymm ymm ymm -// VPSHUFB m256 ymm ymm -func VPSHUFB(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSHUFB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSHUFB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSHUFB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSHUFB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPSHUFB: bad operands") +// VSUBPD.RN_SAE zmm zmm k zmm +// VSUBPD.RN_SAE zmm zmm zmm +func VSUBPD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBPD.Forms(), sffxs{sffxRN_SAE}, ops) } -// VPSHUFD: Shuffle Packed Doublewords. +// VSUBPD_RN_SAE_Z: Subtract Packed Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VPSHUFD imm8 xmm xmm -// VPSHUFD imm8 m128 xmm -// VPSHUFD imm8 ymm ymm -// VPSHUFD imm8 m256 ymm -func VPSHUFD(i, mxy, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPSHUFD", - Operands: []operand.Op{i, mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPSHUFD", - Operands: []operand.Op{i, mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsYMM(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPSHUFD", - Operands: []operand.Op{i, mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsIMM8(i) && operand.IsM256(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPSHUFD", - Operands: []operand.Op{i, mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPSHUFD: bad operands") +// VSUBPD.RN_SAE.Z zmm zmm k zmm +func VSUBPD_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBPD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) } -// VPSHUFHW: Shuffle Packed High Words. +// VSUBPD_RU_SAE: Subtract Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity). // // Forms: // -// VPSHUFHW imm8 xmm xmm -// VPSHUFHW imm8 m128 xmm -// VPSHUFHW imm8 ymm ymm -// VPSHUFHW imm8 m256 ymm -func VPSHUFHW(i, mxy, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPSHUFHW", - Operands: []operand.Op{i, mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPSHUFHW", - Operands: []operand.Op{i, mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsYMM(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPSHUFHW", - Operands: []operand.Op{i, mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsIMM8(i) && operand.IsM256(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPSHUFHW", - Operands: []operand.Op{i, mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPSHUFHW: bad operands") +// VSUBPD.RU_SAE zmm zmm k zmm +// VSUBPD.RU_SAE zmm zmm zmm +func VSUBPD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBPD.Forms(), sffxs{sffxRU_SAE}, ops) } -// VPSHUFLW: Shuffle Packed Low Words. +// VSUBPD_RU_SAE_Z: Subtract Packed Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VPSHUFLW imm8 xmm xmm -// VPSHUFLW imm8 m128 xmm -// VPSHUFLW imm8 ymm ymm -// VPSHUFLW imm8 m256 ymm -func VPSHUFLW(i, mxy, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPSHUFLW", - Operands: []operand.Op{i, mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPSHUFLW", - Operands: []operand.Op{i, mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsYMM(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPSHUFLW", - Operands: []operand.Op{i, mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsIMM8(i) && operand.IsM256(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPSHUFLW", - Operands: []operand.Op{i, mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPSHUFLW: bad operands") +// VSUBPD.RU_SAE.Z zmm zmm k zmm +func VSUBPD_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBPD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) } -// VPSIGNB: Packed Sign of Byte Integers. +// VSUBPD_RZ_SAE: Subtract Packed Double-Precision Floating-Point Values (Round Towards Zero). // // Forms: // -// VPSIGNB xmm xmm xmm -// VPSIGNB m128 xmm xmm -// VPSIGNB ymm ymm ymm -// VPSIGNB m256 ymm ymm -func VPSIGNB(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSIGNB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSIGNB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSIGNB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSIGNB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPSIGNB: bad operands") +// VSUBPD.RZ_SAE zmm zmm k zmm +// VSUBPD.RZ_SAE zmm zmm zmm +func VSUBPD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBPD.Forms(), sffxs{sffxRZ_SAE}, ops) } -// VPSIGND: Packed Sign of Doubleword Integers. +// VSUBPD_RZ_SAE_Z: Subtract Packed Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). // // Forms: // -// VPSIGND xmm xmm xmm -// VPSIGND m128 xmm xmm -// VPSIGND ymm ymm ymm -// VPSIGND m256 ymm ymm -func VPSIGND(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSIGND", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSIGND", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSIGND", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSIGND", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPSIGND: bad operands") +// VSUBPD.RZ_SAE.Z zmm zmm k zmm +func VSUBPD_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBPD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) } -// VPSIGNW: Packed Sign of Word Integers. +// VSUBPD_Z: Subtract Packed Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VPSIGNW xmm xmm xmm -// VPSIGNW m128 xmm xmm -// VPSIGNW ymm ymm ymm -// VPSIGNW m256 ymm ymm -func VPSIGNW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSIGNW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSIGNW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSIGNW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSIGNW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPSIGNW: bad operands") +// VSUBPD.Z m128 xmm k xmm +// VSUBPD.Z m256 ymm k ymm +// VSUBPD.Z xmm xmm k xmm +// VSUBPD.Z ymm ymm k ymm +// VSUBPD.Z m512 zmm k zmm +// VSUBPD.Z zmm zmm k zmm +func VSUBPD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBPD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// VPSLLD: Shift Packed Doubleword Data Left Logical. +// VSUBPS: Subtract Packed Single-Precision Floating-Point Values. // // Forms: // -// VPSLLD imm8 xmm xmm -// VPSLLD xmm xmm xmm -// VPSLLD m128 xmm xmm -// VPSLLD imm8 ymm ymm -// VPSLLD xmm ymm ymm -// VPSLLD m128 ymm ymm -func VPSLLD(imx, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(imx) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSLLD", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(imx) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSLLD", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(imx) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSLLD", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(imx) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSLLD", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsXMM(imx) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSLLD", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM128(imx) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSLLD", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPSLLD: bad operands") +// VSUBPS m128 xmm xmm +// VSUBPS m256 ymm ymm +// VSUBPS xmm xmm xmm +// VSUBPS ymm ymm ymm +// VSUBPS m128 xmm k xmm +// VSUBPS m256 ymm k ymm +// VSUBPS xmm xmm k xmm +// VSUBPS ymm ymm k ymm +// VSUBPS m512 zmm k zmm +// VSUBPS m512 zmm zmm +// VSUBPS zmm zmm k zmm +// VSUBPS zmm zmm zmm +func VSUBPS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBPS.Forms(), sffxs{}, ops) } -// VPSLLDQ: Shift Packed Double Quadword Left Logical. +// VSUBPS_BCST: Subtract Packed Single-Precision Floating-Point Values (Broadcast). // // Forms: // -// VPSLLDQ imm8 xmm xmm -// VPSLLDQ imm8 ymm ymm -func VPSLLDQ(i, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSLLDQ", - Operands: []operand.Op{i, xy, xy1}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSLLDQ", - Operands: []operand.Op{i, xy, xy1}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPSLLDQ: bad operands") +// VSUBPS.BCST m32 xmm k xmm +// VSUBPS.BCST m32 xmm xmm +// VSUBPS.BCST m32 ymm k ymm +// VSUBPS.BCST m32 ymm ymm +// VSUBPS.BCST m32 zmm k zmm +// VSUBPS.BCST m32 zmm zmm +func VSUBPS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBPS.Forms(), sffxs{sffxBCST}, ops) } -// VPSLLQ: Shift Packed Quadword Data Left Logical. +// VSUBPS_BCST_Z: Subtract Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VPSLLQ imm8 xmm xmm -// VPSLLQ xmm xmm xmm -// VPSLLQ m128 xmm xmm -// VPSLLQ imm8 ymm ymm -// VPSLLQ xmm ymm ymm -// VPSLLQ m128 ymm ymm -func VPSLLQ(imx, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(imx) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSLLQ", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(imx) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSLLQ", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(imx) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSLLQ", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(imx) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSLLQ", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsXMM(imx) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSLLQ", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM128(imx) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSLLQ", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPSLLQ: bad operands") +// VSUBPS.BCST.Z m32 xmm k xmm +// VSUBPS.BCST.Z m32 ymm k ymm +// VSUBPS.BCST.Z m32 zmm k zmm +func VSUBPS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBPS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// VPSLLVD: Variable Shift Packed Doubleword Data Left Logical. +// VSUBPS_RD_SAE: Subtract Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity). // // Forms: // -// VPSLLVD xmm xmm xmm -// VPSLLVD m128 xmm xmm -// VPSLLVD ymm ymm ymm -// VPSLLVD m256 ymm ymm -func VPSLLVD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSLLVD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSLLVD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSLLVD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSLLVD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPSLLVD: bad operands") +// VSUBPS.RD_SAE zmm zmm k zmm +// VSUBPS.RD_SAE zmm zmm zmm +func VSUBPS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBPS.Forms(), sffxs{sffxRD_SAE}, ops) } -// VPSLLVQ: Variable Shift Packed Quadword Data Left Logical. +// VSUBPS_RD_SAE_Z: Subtract Packed Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VPSLLVQ xmm xmm xmm -// VPSLLVQ m128 xmm xmm -// VPSLLVQ ymm ymm ymm -// VPSLLVQ m256 ymm ymm -func VPSLLVQ(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSLLVQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSLLVQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSLLVQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSLLVQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPSLLVQ: bad operands") +// VSUBPS.RD_SAE.Z zmm zmm k zmm +func VSUBPS_RD_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBPS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) } -// VPSLLW: Shift Packed Word Data Left Logical. +// VSUBPS_RN_SAE: Subtract Packed Single-Precision Floating-Point Values (Round Towards Nearest). // // Forms: // -// VPSLLW imm8 xmm xmm -// VPSLLW xmm xmm xmm -// VPSLLW m128 xmm xmm -// VPSLLW imm8 ymm ymm -// VPSLLW xmm ymm ymm -// VPSLLW m128 ymm ymm -func VPSLLW(imx, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(imx) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSLLW", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(imx) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSLLW", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(imx) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSLLW", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(imx) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSLLW", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsXMM(imx) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSLLW", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM128(imx) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSLLW", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPSLLW: bad operands") +// VSUBPS.RN_SAE zmm zmm k zmm +// VSUBPS.RN_SAE zmm zmm zmm +func VSUBPS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBPS.Forms(), sffxs{sffxRN_SAE}, ops) } -// VPSRAD: Shift Packed Doubleword Data Right Arithmetic. +// VSUBPS_RN_SAE_Z: Subtract Packed Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VPSRAD imm8 xmm xmm -// VPSRAD xmm xmm xmm -// VPSRAD m128 xmm xmm -// VPSRAD imm8 ymm ymm -// VPSRAD xmm ymm ymm -// VPSRAD m128 ymm ymm -func VPSRAD(imx, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(imx) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRAD", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(imx) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRAD", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(imx) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRAD", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(imx) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRAD", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsXMM(imx) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRAD", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM128(imx) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRAD", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPSRAD: bad operands") +// VSUBPS.RN_SAE.Z zmm zmm k zmm +func VSUBPS_RN_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBPS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) } -// VPSRAVD: Variable Shift Packed Doubleword Data Right Arithmetic. +// VSUBPS_RU_SAE: Subtract Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity). // // Forms: // -// VPSRAVD xmm xmm xmm -// VPSRAVD m128 xmm xmm -// VPSRAVD ymm ymm ymm -// VPSRAVD m256 ymm ymm -func VPSRAVD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRAVD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRAVD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRAVD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRAVD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPSRAVD: bad operands") +// VSUBPS.RU_SAE zmm zmm k zmm +// VSUBPS.RU_SAE zmm zmm zmm +func VSUBPS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBPS.Forms(), sffxs{sffxRU_SAE}, ops) } -// VPSRAW: Shift Packed Word Data Right Arithmetic. +// VSUBPS_RU_SAE_Z: Subtract Packed Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VPSRAW imm8 xmm xmm -// VPSRAW xmm xmm xmm -// VPSRAW m128 xmm xmm -// VPSRAW imm8 ymm ymm -// VPSRAW xmm ymm ymm -// VPSRAW m128 ymm ymm -func VPSRAW(imx, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(imx) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRAW", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(imx) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRAW", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(imx) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRAW", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(imx) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRAW", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsXMM(imx) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRAW", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM128(imx) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRAW", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPSRAW: bad operands") +// VSUBPS.RU_SAE.Z zmm zmm k zmm +func VSUBPS_RU_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBPS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) } -// VPSRLD: Shift Packed Doubleword Data Right Logical. +// VSUBPS_RZ_SAE: Subtract Packed Single-Precision Floating-Point Values (Round Towards Zero). // // Forms: // -// VPSRLD imm8 xmm xmm -// VPSRLD xmm xmm xmm -// VPSRLD m128 xmm xmm -// VPSRLD imm8 ymm ymm -// VPSRLD xmm ymm ymm -// VPSRLD m128 ymm ymm -func VPSRLD(imx, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(imx) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRLD", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(imx) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRLD", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(imx) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRLD", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(imx) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRLD", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsXMM(imx) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRLD", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM128(imx) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRLD", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPSRLD: bad operands") +// VSUBPS.RZ_SAE zmm zmm k zmm +// VSUBPS.RZ_SAE zmm zmm zmm +func VSUBPS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBPS.Forms(), sffxs{sffxRZ_SAE}, ops) } -// VPSRLDQ: Shift Packed Double Quadword Right Logical. +// VSUBPS_RZ_SAE_Z: Subtract Packed Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). // // Forms: // -// VPSRLDQ imm8 xmm xmm -// VPSRLDQ imm8 ymm ymm -func VPSRLDQ(i, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRLDQ", - Operands: []operand.Op{i, xy, xy1}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRLDQ", - Operands: []operand.Op{i, xy, xy1}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPSRLDQ: bad operands") +// VSUBPS.RZ_SAE.Z zmm zmm k zmm +func VSUBPS_RZ_SAE_Z(z, z1, k, z2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBPS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{z, z1, k, z2}) } -// VPSRLQ: Shift Packed Quadword Data Right Logical. +// VSUBPS_Z: Subtract Packed Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VPSRLQ imm8 xmm xmm -// VPSRLQ xmm xmm xmm -// VPSRLQ m128 xmm xmm -// VPSRLQ imm8 ymm ymm -// VPSRLQ xmm ymm ymm -// VPSRLQ m128 ymm ymm -func VPSRLQ(imx, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(imx) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRLQ", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(imx) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRLQ", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(imx) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRLQ", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(imx) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRLQ", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsXMM(imx) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRLQ", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM128(imx) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRLQ", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPSRLQ: bad operands") +// VSUBPS.Z m128 xmm k xmm +// VSUBPS.Z m256 ymm k ymm +// VSUBPS.Z xmm xmm k xmm +// VSUBPS.Z ymm ymm k ymm +// VSUBPS.Z m512 zmm k zmm +// VSUBPS.Z zmm zmm k zmm +func VSUBPS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBPS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// VPSRLVD: Variable Shift Packed Doubleword Data Right Logical. +// VSUBSD: Subtract Scalar Double-Precision Floating-Point Values. // // Forms: // -// VPSRLVD xmm xmm xmm -// VPSRLVD m128 xmm xmm -// VPSRLVD ymm ymm ymm -// VPSRLVD m256 ymm ymm -func VPSRLVD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRLVD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRLVD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRLVD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRLVD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPSRLVD: bad operands") +// VSUBSD m64 xmm xmm +// VSUBSD xmm xmm xmm +// VSUBSD m64 xmm k xmm +// VSUBSD xmm xmm k xmm +func VSUBSD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBSD.Forms(), sffxs{}, ops) } -// VPSRLVQ: Variable Shift Packed Quadword Data Right Logical. +// VSUBSD_RD_SAE: Subtract Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity). // // Forms: // -// VPSRLVQ xmm xmm xmm -// VPSRLVQ m128 xmm xmm -// VPSRLVQ ymm ymm ymm -// VPSRLVQ m256 ymm ymm -func VPSRLVQ(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRLVQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRLVQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRLVQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRLVQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPSRLVQ: bad operands") +// VSUBSD.RD_SAE xmm xmm k xmm +// VSUBSD.RD_SAE xmm xmm xmm +func VSUBSD_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBSD.Forms(), sffxs{sffxRD_SAE}, ops) } -// VPSRLW: Shift Packed Word Data Right Logical. +// VSUBSD_RD_SAE_Z: Subtract Scalar Double-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VPSRLW imm8 xmm xmm -// VPSRLW xmm xmm xmm -// VPSRLW m128 xmm xmm -// VPSRLW imm8 ymm ymm -// VPSRLW xmm ymm ymm -// VPSRLW m128 ymm ymm -func VPSRLW(imx, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(imx) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRLW", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsXMM(imx) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRLW", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(imx) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRLW", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(imx) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRLW", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsXMM(imx) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRLW", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM128(imx) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSRLW", - Operands: []operand.Op{imx, xy, xy1}, - Inputs: []operand.Op{imx, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPSRLW: bad operands") +// VSUBSD.RD_SAE.Z xmm xmm k xmm +func VSUBSD_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBSD.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) } -// VPSUBB: Subtract Packed Byte Integers. +// VSUBSD_RN_SAE: Subtract Scalar Double-Precision Floating-Point Values (Round Towards Nearest). // // Forms: // -// VPSUBB xmm xmm xmm -// VPSUBB m128 xmm xmm -// VPSUBB ymm ymm ymm -// VPSUBB m256 ymm ymm -func VPSUBB(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - CancellingInputs: true, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPSUBB: bad operands") +// VSUBSD.RN_SAE xmm xmm k xmm +// VSUBSD.RN_SAE xmm xmm xmm +func VSUBSD_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBSD.Forms(), sffxs{sffxRN_SAE}, ops) } -// VPSUBD: Subtract Packed Doubleword Integers. +// VSUBSD_RN_SAE_Z: Subtract Scalar Double-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VPSUBD xmm xmm xmm -// VPSUBD m128 xmm xmm -// VPSUBD ymm ymm ymm -// VPSUBD m256 ymm ymm -func VPSUBD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - CancellingInputs: true, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPSUBD: bad operands") +// VSUBSD.RN_SAE.Z xmm xmm k xmm +func VSUBSD_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBSD.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) } -// VPSUBQ: Subtract Packed Quadword Integers. +// VSUBSD_RU_SAE: Subtract Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity). // // Forms: // -// VPSUBQ xmm xmm xmm -// VPSUBQ m128 xmm xmm -// VPSUBQ ymm ymm ymm -// VPSUBQ m256 ymm ymm -func VPSUBQ(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - CancellingInputs: true, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPSUBQ: bad operands") +// VSUBSD.RU_SAE xmm xmm k xmm +// VSUBSD.RU_SAE xmm xmm xmm +func VSUBSD_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBSD.Forms(), sffxs{sffxRU_SAE}, ops) } -// VPSUBSB: Subtract Packed Signed Byte Integers with Signed Saturation. +// VSUBSD_RU_SAE_Z: Subtract Scalar Double-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VPSUBSB xmm xmm xmm -// VPSUBSB m128 xmm xmm -// VPSUBSB ymm ymm ymm -// VPSUBSB m256 ymm ymm -func VPSUBSB(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBSB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBSB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBSB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - CancellingInputs: true, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBSB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPSUBSB: bad operands") +// VSUBSD.RU_SAE.Z xmm xmm k xmm +func VSUBSD_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBSD.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) } -// VPSUBSW: Subtract Packed Signed Word Integers with Signed Saturation. +// VSUBSD_RZ_SAE: Subtract Scalar Double-Precision Floating-Point Values (Round Towards Zero). // // Forms: // -// VPSUBSW xmm xmm xmm -// VPSUBSW m128 xmm xmm -// VPSUBSW ymm ymm ymm -// VPSUBSW m256 ymm ymm -func VPSUBSW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - CancellingInputs: true, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPSUBSW: bad operands") +// VSUBSD.RZ_SAE xmm xmm k xmm +// VSUBSD.RZ_SAE xmm xmm xmm +func VSUBSD_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBSD.Forms(), sffxs{sffxRZ_SAE}, ops) } -// VPSUBUSB: Subtract Packed Unsigned Byte Integers with Unsigned Saturation. +// VSUBSD_RZ_SAE_Z: Subtract Scalar Double-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). // // Forms: // -// VPSUBUSB xmm xmm xmm -// VPSUBUSB m128 xmm xmm -// VPSUBUSB ymm ymm ymm -// VPSUBUSB m256 ymm ymm -func VPSUBUSB(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBUSB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBUSB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBUSB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - CancellingInputs: true, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBUSB", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPSUBUSB: bad operands") +// VSUBSD.RZ_SAE.Z xmm xmm k xmm +func VSUBSD_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBSD.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) } -// VPSUBUSW: Subtract Packed Unsigned Word Integers with Unsigned Saturation. +// VSUBSD_Z: Subtract Scalar Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VPSUBUSW xmm xmm xmm -// VPSUBUSW m128 xmm xmm -// VPSUBUSW ymm ymm ymm -// VPSUBUSW m256 ymm ymm -func VPSUBUSW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBUSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBUSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBUSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - CancellingInputs: true, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBUSW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPSUBUSW: bad operands") +// VSUBSD.Z m64 xmm k xmm +// VSUBSD.Z xmm xmm k xmm +func VSUBSD_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBSD.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) } -// VPSUBW: Subtract Packed Word Integers. +// VSUBSS: Subtract Scalar Single-Precision Floating-Point Values. // // Forms: // -// VPSUBW xmm xmm xmm -// VPSUBW m128 xmm xmm -// VPSUBW ymm ymm ymm -// VPSUBW m256 ymm ymm -func VPSUBW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - CancellingInputs: true, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPSUBW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPSUBW: bad operands") +// VSUBSS m32 xmm xmm +// VSUBSS xmm xmm xmm +// VSUBSS m32 xmm k xmm +// VSUBSS xmm xmm k xmm +func VSUBSS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBSS.Forms(), sffxs{}, ops) } -// VPTEST: Packed Logical Compare. +// VSUBSS_RD_SAE: Subtract Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity). // // Forms: // -// VPTEST xmm xmm -// VPTEST m128 xmm -// VPTEST ymm ymm -// VPTEST m256 ymm -func VPTEST(mxy, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPTEST", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VPTEST", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPTEST", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VPTEST", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VPTEST: bad operands") +// VSUBSS.RD_SAE xmm xmm k xmm +// VSUBSS.RD_SAE xmm xmm xmm +func VSUBSS_RD_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBSS.Forms(), sffxs{sffxRD_SAE}, ops) } -// VPUNPCKHBW: Unpack and Interleave High-Order Bytes into Words. +// VSUBSS_RD_SAE_Z: Subtract Scalar Single-Precision Floating-Point Values (Round Towards Negative Infinity, Zeroing Masking). // // Forms: // -// VPUNPCKHBW xmm xmm xmm -// VPUNPCKHBW m128 xmm xmm -// VPUNPCKHBW ymm ymm ymm -// VPUNPCKHBW m256 ymm ymm -func VPUNPCKHBW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKHBW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKHBW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKHBW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKHBW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPUNPCKHBW: bad operands") +// VSUBSS.RD_SAE.Z xmm xmm k xmm +func VSUBSS_RD_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBSS.Forms(), sffxs{sffxRD_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) } -// VPUNPCKHDQ: Unpack and Interleave High-Order Doublewords into Quadwords. +// VSUBSS_RN_SAE: Subtract Scalar Single-Precision Floating-Point Values (Round Towards Nearest). // // Forms: // -// VPUNPCKHDQ xmm xmm xmm -// VPUNPCKHDQ m128 xmm xmm -// VPUNPCKHDQ ymm ymm ymm -// VPUNPCKHDQ m256 ymm ymm -func VPUNPCKHDQ(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKHDQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKHDQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKHDQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKHDQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPUNPCKHDQ: bad operands") +// VSUBSS.RN_SAE xmm xmm k xmm +// VSUBSS.RN_SAE xmm xmm xmm +func VSUBSS_RN_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBSS.Forms(), sffxs{sffxRN_SAE}, ops) } -// VPUNPCKHQDQ: Unpack and Interleave High-Order Quadwords into Double Quadwords. +// VSUBSS_RN_SAE_Z: Subtract Scalar Single-Precision Floating-Point Values (Round Towards Nearest, Zeroing Masking). // // Forms: // -// VPUNPCKHQDQ xmm xmm xmm -// VPUNPCKHQDQ m128 xmm xmm -// VPUNPCKHQDQ ymm ymm ymm -// VPUNPCKHQDQ m256 ymm ymm -func VPUNPCKHQDQ(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKHQDQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKHQDQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKHQDQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKHQDQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPUNPCKHQDQ: bad operands") +// VSUBSS.RN_SAE.Z xmm xmm k xmm +func VSUBSS_RN_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBSS.Forms(), sffxs{sffxRN_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) } -// VPUNPCKHWD: Unpack and Interleave High-Order Words into Doublewords. +// VSUBSS_RU_SAE: Subtract Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity). // // Forms: // -// VPUNPCKHWD xmm xmm xmm -// VPUNPCKHWD m128 xmm xmm -// VPUNPCKHWD ymm ymm ymm -// VPUNPCKHWD m256 ymm ymm -func VPUNPCKHWD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKHWD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKHWD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKHWD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKHWD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPUNPCKHWD: bad operands") +// VSUBSS.RU_SAE xmm xmm k xmm +// VSUBSS.RU_SAE xmm xmm xmm +func VSUBSS_RU_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBSS.Forms(), sffxs{sffxRU_SAE}, ops) } -// VPUNPCKLBW: Unpack and Interleave Low-Order Bytes into Words. +// VSUBSS_RU_SAE_Z: Subtract Scalar Single-Precision Floating-Point Values (Round Towards Positive Infinity, Zeroing Masking). // // Forms: // -// VPUNPCKLBW xmm xmm xmm -// VPUNPCKLBW m128 xmm xmm -// VPUNPCKLBW ymm ymm ymm -// VPUNPCKLBW m256 ymm ymm -func VPUNPCKLBW(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKLBW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKLBW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKLBW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKLBW", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPUNPCKLBW: bad operands") +// VSUBSS.RU_SAE.Z xmm xmm k xmm +func VSUBSS_RU_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBSS.Forms(), sffxs{sffxRU_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) } -// VPUNPCKLDQ: Unpack and Interleave Low-Order Doublewords into Quadwords. +// VSUBSS_RZ_SAE: Subtract Scalar Single-Precision Floating-Point Values (Round Towards Zero). // // Forms: // -// VPUNPCKLDQ xmm xmm xmm -// VPUNPCKLDQ m128 xmm xmm -// VPUNPCKLDQ ymm ymm ymm -// VPUNPCKLDQ m256 ymm ymm -func VPUNPCKLDQ(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKLDQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKLDQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKLDQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKLDQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPUNPCKLDQ: bad operands") +// VSUBSS.RZ_SAE xmm xmm k xmm +// VSUBSS.RZ_SAE xmm xmm xmm +func VSUBSS_RZ_SAE(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBSS.Forms(), sffxs{sffxRZ_SAE}, ops) } -// VPUNPCKLQDQ: Unpack and Interleave Low-Order Quadwords into Double Quadwords. +// VSUBSS_RZ_SAE_Z: Subtract Scalar Single-Precision Floating-Point Values (Round Towards Zero, Zeroing Masking). // // Forms: // -// VPUNPCKLQDQ xmm xmm xmm -// VPUNPCKLQDQ m128 xmm xmm -// VPUNPCKLQDQ ymm ymm ymm -// VPUNPCKLQDQ m256 ymm ymm -func VPUNPCKLQDQ(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKLQDQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKLQDQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKLQDQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKLQDQ", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPUNPCKLQDQ: bad operands") +// VSUBSS.RZ_SAE.Z xmm xmm k xmm +func VSUBSS_RZ_SAE_Z(x, x1, k, x2 operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBSS.Forms(), sffxs{sffxRZ_SAE, sffxZ}, []operand.Op{x, x1, k, x2}) } -// VPUNPCKLWD: Unpack and Interleave Low-Order Words into Doublewords. +// VSUBSS_Z: Subtract Scalar Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VPUNPCKLWD xmm xmm xmm -// VPUNPCKLWD m128 xmm xmm -// VPUNPCKLWD ymm ymm ymm -// VPUNPCKLWD m256 ymm ymm -func VPUNPCKLWD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKLWD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKLWD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKLWD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPUNPCKLWD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPUNPCKLWD: bad operands") +// VSUBSS.Z m32 xmm k xmm +// VSUBSS.Z xmm xmm k xmm +func VSUBSS_Z(mx, x, k, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVSUBSS.Forms(), sffxs{sffxZ}, []operand.Op{mx, x, k, x1}) } -// VPXOR: Packed Bitwise Logical Exclusive OR. +// VTESTPD: Packed Double-Precision Floating-Point Bit Test. // // Forms: // -// VPXOR xmm xmm xmm -// VPXOR m128 xmm xmm -// VPXOR ymm ymm ymm -// VPXOR m256 ymm ymm -func VPXOR(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPXOR", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VPXOR", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPXOR", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - CancellingInputs: true, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VPXOR", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX2"}, - }, nil - } - return nil, errors.New("VPXOR: bad operands") +// VTESTPD m128 xmm +// VTESTPD m256 ymm +// VTESTPD xmm xmm +// VTESTPD ymm ymm +func VTESTPD(mxy, xy operand.Op) (*intrep.Instruction, error) { + return build(opcVTESTPD.Forms(), sffxs{}, []operand.Op{mxy, xy}) } -// VRCPPS: Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values. +// VTESTPS: Packed Single-Precision Floating-Point Bit Test. // // Forms: // -// VRCPPS xmm xmm -// VRCPPS m128 xmm -// VRCPPS ymm ymm -// VRCPPS m256 ymm -func VRCPPS(mxy, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VRCPPS", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VRCPPS", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VRCPPS", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VRCPPS", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VRCPPS: bad operands") +// VTESTPS m128 xmm +// VTESTPS m256 ymm +// VTESTPS xmm xmm +// VTESTPS ymm ymm +func VTESTPS(mxy, xy operand.Op) (*intrep.Instruction, error) { + return build(opcVTESTPS.Forms(), sffxs{}, []operand.Op{mxy, xy}) } -// VRCPSS: Compute Approximate Reciprocal of Scalar Single-Precision Floating-Point Values. +// VUCOMISD: Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS. // // Forms: // -// VRCPSS xmm xmm xmm -// VRCPSS m32 xmm xmm -func VRCPSS(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VRCPSS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VRCPSS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VRCPSS: bad operands") +// VUCOMISD m64 xmm +// VUCOMISD xmm xmm +func VUCOMISD(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcVUCOMISD.Forms(), sffxs{}, []operand.Op{mx, x}) } -// VROUNDPD: Round Packed Double Precision Floating-Point Values. +// VUCOMISD_SAE: Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS (Suppress All Exceptions). // // Forms: // -// VROUNDPD imm8 xmm xmm -// VROUNDPD imm8 m128 xmm -// VROUNDPD imm8 ymm ymm -// VROUNDPD imm8 m256 ymm -func VROUNDPD(i, mxy, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VROUNDPD", - Operands: []operand.Op{i, mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VROUNDPD", - Operands: []operand.Op{i, mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsYMM(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VROUNDPD", - Operands: []operand.Op{i, mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM256(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VROUNDPD", - Operands: []operand.Op{i, mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VROUNDPD: bad operands") +// VUCOMISD.SAE xmm xmm +func VUCOMISD_SAE(x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVUCOMISD.Forms(), sffxs{sffxSAE}, []operand.Op{x, x1}) } -// VROUNDPS: Round Packed Single Precision Floating-Point Values. +// VUCOMISS: Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS. // // Forms: // -// VROUNDPS imm8 xmm xmm -// VROUNDPS imm8 m128 xmm -// VROUNDPS imm8 ymm ymm -// VROUNDPS imm8 m256 ymm -func VROUNDPS(i, mxy, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VROUNDPS", - Operands: []operand.Op{i, mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VROUNDPS", - Operands: []operand.Op{i, mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsYMM(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VROUNDPS", - Operands: []operand.Op{i, mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM256(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VROUNDPS", - Operands: []operand.Op{i, mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VROUNDPS: bad operands") +// VUCOMISS m32 xmm +// VUCOMISS xmm xmm +func VUCOMISS(mx, x operand.Op) (*intrep.Instruction, error) { + return build(opcVUCOMISS.Forms(), sffxs{}, []operand.Op{mx, x}) } -// VROUNDSD: Round Scalar Double Precision Floating-Point Values. +// VUCOMISS_SAE: Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS (Suppress All Exceptions). // // Forms: // -// VROUNDSD imm8 xmm xmm xmm -// VROUNDSD imm8 m64 xmm xmm -func VROUNDSD(i, mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VROUNDSD", - Operands: []operand.Op{i, mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM64(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VROUNDSD", - Operands: []operand.Op{i, mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VROUNDSD: bad operands") +// VUCOMISS.SAE xmm xmm +func VUCOMISS_SAE(x, x1 operand.Op) (*intrep.Instruction, error) { + return build(opcVUCOMISS.Forms(), sffxs{sffxSAE}, []operand.Op{x, x1}) } -// VROUNDSS: Round Scalar Single Precision Floating-Point Values. +// VUNPCKHPD: Unpack and Interleave High Packed Double-Precision Floating-Point Values. // // Forms: // -// VROUNDSS imm8 xmm xmm xmm -// VROUNDSS imm8 m32 xmm xmm -func VROUNDSS(i, mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VROUNDSS", - Operands: []operand.Op{i, mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM32(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VROUNDSS", - Operands: []operand.Op{i, mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VROUNDSS: bad operands") +// VUNPCKHPD m128 xmm xmm +// VUNPCKHPD m256 ymm ymm +// VUNPCKHPD xmm xmm xmm +// VUNPCKHPD ymm ymm ymm +// VUNPCKHPD m128 xmm k xmm +// VUNPCKHPD m256 ymm k ymm +// VUNPCKHPD xmm xmm k xmm +// VUNPCKHPD ymm ymm k ymm +// VUNPCKHPD m512 zmm k zmm +// VUNPCKHPD m512 zmm zmm +// VUNPCKHPD zmm zmm k zmm +// VUNPCKHPD zmm zmm zmm +func VUNPCKHPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVUNPCKHPD.Forms(), sffxs{}, ops) } -// VRSQRTPS: Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values. +// VUNPCKHPD_BCST: Unpack and Interleave High Packed Double-Precision Floating-Point Values (Broadcast). // // Forms: // -// VRSQRTPS xmm xmm -// VRSQRTPS m128 xmm -// VRSQRTPS ymm ymm -// VRSQRTPS m256 ymm -func VRSQRTPS(mxy, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VRSQRTPS", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VRSQRTPS", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VRSQRTPS", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VRSQRTPS", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VRSQRTPS: bad operands") +// VUNPCKHPD.BCST m64 xmm k xmm +// VUNPCKHPD.BCST m64 xmm xmm +// VUNPCKHPD.BCST m64 ymm k ymm +// VUNPCKHPD.BCST m64 ymm ymm +// VUNPCKHPD.BCST m64 zmm k zmm +// VUNPCKHPD.BCST m64 zmm zmm +func VUNPCKHPD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVUNPCKHPD.Forms(), sffxs{sffxBCST}, ops) } -// VRSQRTSS: Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value. +// VUNPCKHPD_BCST_Z: Unpack and Interleave High Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VRSQRTSS xmm xmm xmm -// VRSQRTSS m32 xmm xmm -func VRSQRTSS(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VRSQRTSS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VRSQRTSS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VRSQRTSS: bad operands") +// VUNPCKHPD.BCST.Z m64 xmm k xmm +// VUNPCKHPD.BCST.Z m64 ymm k ymm +// VUNPCKHPD.BCST.Z m64 zmm k zmm +func VUNPCKHPD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVUNPCKHPD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// VSHUFPD: Shuffle Packed Double-Precision Floating-Point Values. +// VUNPCKHPD_Z: Unpack and Interleave High Packed Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VSHUFPD imm8 xmm xmm xmm -// VSHUFPD imm8 m128 xmm xmm -// VSHUFPD imm8 ymm ymm ymm -// VSHUFPD imm8 m256 ymm ymm -func VSHUFPD(i, mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VSHUFPD", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VSHUFPD", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VSHUFPD", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VSHUFPD", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VSHUFPD: bad operands") +// VUNPCKHPD.Z m128 xmm k xmm +// VUNPCKHPD.Z m256 ymm k ymm +// VUNPCKHPD.Z xmm xmm k xmm +// VUNPCKHPD.Z ymm ymm k ymm +// VUNPCKHPD.Z m512 zmm k zmm +// VUNPCKHPD.Z zmm zmm k zmm +func VUNPCKHPD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVUNPCKHPD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// VSHUFPS: Shuffle Packed Single-Precision Floating-Point Values. +// VUNPCKHPS: Unpack and Interleave High Packed Single-Precision Floating-Point Values. // // Forms: // -// VSHUFPS imm8 xmm xmm xmm -// VSHUFPS imm8 m128 xmm xmm -// VSHUFPS imm8 ymm ymm ymm -// VSHUFPS imm8 m256 ymm ymm -func VSHUFPS(i, mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(i) && operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VSHUFPS", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VSHUFPS", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VSHUFPS", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsIMM8(i) && operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VSHUFPS", - Operands: []operand.Op{i, mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VSHUFPS: bad operands") +// VUNPCKHPS m128 xmm xmm +// VUNPCKHPS m256 ymm ymm +// VUNPCKHPS xmm xmm xmm +// VUNPCKHPS ymm ymm ymm +// VUNPCKHPS m128 xmm k xmm +// VUNPCKHPS m256 ymm k ymm +// VUNPCKHPS xmm xmm k xmm +// VUNPCKHPS ymm ymm k ymm +// VUNPCKHPS m512 zmm k zmm +// VUNPCKHPS m512 zmm zmm +// VUNPCKHPS zmm zmm k zmm +// VUNPCKHPS zmm zmm zmm +func VUNPCKHPS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVUNPCKHPS.Forms(), sffxs{}, ops) } -// VSQRTPD: Compute Square Roots of Packed Double-Precision Floating-Point Values. +// VUNPCKHPS_BCST: Unpack and Interleave High Packed Single-Precision Floating-Point Values (Broadcast). // // Forms: // -// VSQRTPD xmm xmm -// VSQRTPD m128 xmm -// VSQRTPD ymm ymm -// VSQRTPD m256 ymm -func VSQRTPD(mxy, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VSQRTPD", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VSQRTPD", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VSQRTPD", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VSQRTPD", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VSQRTPD: bad operands") +// VUNPCKHPS.BCST m32 xmm k xmm +// VUNPCKHPS.BCST m32 xmm xmm +// VUNPCKHPS.BCST m32 ymm k ymm +// VUNPCKHPS.BCST m32 ymm ymm +// VUNPCKHPS.BCST m32 zmm k zmm +// VUNPCKHPS.BCST m32 zmm zmm +func VUNPCKHPS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVUNPCKHPS.Forms(), sffxs{sffxBCST}, ops) } -// VSQRTPS: Compute Square Roots of Packed Single-Precision Floating-Point Values. +// VUNPCKHPS_BCST_Z: Unpack and Interleave High Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VSQRTPS xmm xmm -// VSQRTPS m128 xmm -// VSQRTPS ymm ymm -// VSQRTPS m256 ymm -func VSQRTPS(mxy, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VSQRTPS", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VSQRTPS", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VSQRTPS", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VSQRTPS", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy}, - Outputs: []operand.Op{xy}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VSQRTPS: bad operands") +// VUNPCKHPS.BCST.Z m32 xmm k xmm +// VUNPCKHPS.BCST.Z m32 ymm k ymm +// VUNPCKHPS.BCST.Z m32 zmm k zmm +func VUNPCKHPS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVUNPCKHPS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// VSQRTSD: Compute Square Root of Scalar Double-Precision Floating-Point Value. +// VUNPCKHPS_Z: Unpack and Interleave High Packed Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VSQRTSD xmm xmm xmm -// VSQRTSD m64 xmm xmm -func VSQRTSD(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VSQRTSD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VSQRTSD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VSQRTSD: bad operands") +// VUNPCKHPS.Z m128 xmm k xmm +// VUNPCKHPS.Z m256 ymm k ymm +// VUNPCKHPS.Z xmm xmm k xmm +// VUNPCKHPS.Z ymm ymm k ymm +// VUNPCKHPS.Z m512 zmm k zmm +// VUNPCKHPS.Z zmm zmm k zmm +func VUNPCKHPS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVUNPCKHPS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// VSQRTSS: Compute Square Root of Scalar Single-Precision Floating-Point Value. +// VUNPCKLPD: Unpack and Interleave Low Packed Double-Precision Floating-Point Values. // // Forms: // -// VSQRTSS xmm xmm xmm -// VSQRTSS m32 xmm xmm -func VSQRTSS(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VSQRTSS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VSQRTSS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VSQRTSS: bad operands") +// VUNPCKLPD m128 xmm xmm +// VUNPCKLPD m256 ymm ymm +// VUNPCKLPD xmm xmm xmm +// VUNPCKLPD ymm ymm ymm +// VUNPCKLPD m128 xmm k xmm +// VUNPCKLPD m256 ymm k ymm +// VUNPCKLPD xmm xmm k xmm +// VUNPCKLPD ymm ymm k ymm +// VUNPCKLPD m512 zmm k zmm +// VUNPCKLPD m512 zmm zmm +// VUNPCKLPD zmm zmm k zmm +// VUNPCKLPD zmm zmm zmm +func VUNPCKLPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVUNPCKLPD.Forms(), sffxs{}, ops) } -// VSTMXCSR: Store MXCSR Register State. +// VUNPCKLPD_BCST: Unpack and Interleave Low Packed Double-Precision Floating-Point Values (Broadcast). // // Forms: // -// VSTMXCSR m32 -func VSTMXCSR(m operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsM32(m): - return &intrep.Instruction{ - Opcode: "VSTMXCSR", - Operands: []operand.Op{m}, - Inputs: []operand.Op{}, - Outputs: []operand.Op{m}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VSTMXCSR: bad operands") +// VUNPCKLPD.BCST m64 xmm k xmm +// VUNPCKLPD.BCST m64 xmm xmm +// VUNPCKLPD.BCST m64 ymm k ymm +// VUNPCKLPD.BCST m64 ymm ymm +// VUNPCKLPD.BCST m64 zmm k zmm +// VUNPCKLPD.BCST m64 zmm zmm +func VUNPCKLPD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVUNPCKLPD.Forms(), sffxs{sffxBCST}, ops) } -// VSUBPD: Subtract Packed Double-Precision Floating-Point Values. +// VUNPCKLPD_BCST_Z: Unpack and Interleave Low Packed Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VSUBPD xmm xmm xmm -// VSUBPD m128 xmm xmm -// VSUBPD ymm ymm ymm -// VSUBPD m256 ymm ymm -func VSUBPD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VSUBPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VSUBPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VSUBPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VSUBPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VSUBPD: bad operands") +// VUNPCKLPD.BCST.Z m64 xmm k xmm +// VUNPCKLPD.BCST.Z m64 ymm k ymm +// VUNPCKLPD.BCST.Z m64 zmm k zmm +func VUNPCKLPD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVUNPCKLPD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// VSUBPS: Subtract Packed Single-Precision Floating-Point Values. +// VUNPCKLPD_Z: Unpack and Interleave Low Packed Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VSUBPS xmm xmm xmm -// VSUBPS m128 xmm xmm -// VSUBPS ymm ymm ymm -// VSUBPS m256 ymm ymm -func VSUBPS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VSUBPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VSUBPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VSUBPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VSUBPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VSUBPS: bad operands") +// VUNPCKLPD.Z m128 xmm k xmm +// VUNPCKLPD.Z m256 ymm k ymm +// VUNPCKLPD.Z xmm xmm k xmm +// VUNPCKLPD.Z ymm ymm k ymm +// VUNPCKLPD.Z m512 zmm k zmm +// VUNPCKLPD.Z zmm zmm k zmm +func VUNPCKLPD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVUNPCKLPD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// VSUBSD: Subtract Scalar Double-Precision Floating-Point Values. +// VUNPCKLPS: Unpack and Interleave Low Packed Single-Precision Floating-Point Values. // // Forms: // -// VSUBSD xmm xmm xmm -// VSUBSD m64 xmm xmm -func VSUBSD(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VSUBSD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VSUBSD", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VSUBSD: bad operands") +// VUNPCKLPS m128 xmm xmm +// VUNPCKLPS m256 ymm ymm +// VUNPCKLPS xmm xmm xmm +// VUNPCKLPS ymm ymm ymm +// VUNPCKLPS m128 xmm k xmm +// VUNPCKLPS m256 ymm k ymm +// VUNPCKLPS xmm xmm k xmm +// VUNPCKLPS ymm ymm k ymm +// VUNPCKLPS m512 zmm k zmm +// VUNPCKLPS m512 zmm zmm +// VUNPCKLPS zmm zmm k zmm +// VUNPCKLPS zmm zmm zmm +func VUNPCKLPS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVUNPCKLPS.Forms(), sffxs{}, ops) } -// VSUBSS: Subtract Scalar Single-Precision Floating-Point Values. +// VUNPCKLPS_BCST: Unpack and Interleave Low Packed Single-Precision Floating-Point Values (Broadcast). // // Forms: // -// VSUBSS xmm xmm xmm -// VSUBSS m32 xmm xmm -func VSUBSS(mx, x, x1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VSUBSS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x) && operand.IsXMM(x1): - return &intrep.Instruction{ - Opcode: "VSUBSS", - Operands: []operand.Op{mx, x, x1}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VSUBSS: bad operands") +// VUNPCKLPS.BCST m32 xmm k xmm +// VUNPCKLPS.BCST m32 xmm xmm +// VUNPCKLPS.BCST m32 ymm k ymm +// VUNPCKLPS.BCST m32 ymm ymm +// VUNPCKLPS.BCST m32 zmm k zmm +// VUNPCKLPS.BCST m32 zmm zmm +func VUNPCKLPS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVUNPCKLPS.Forms(), sffxs{sffxBCST}, ops) } -// VTESTPD: Packed Double-Precision Floating-Point Bit Test. +// VUNPCKLPS_BCST_Z: Unpack and Interleave Low Packed Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VTESTPD xmm xmm -// VTESTPD m128 xmm -// VTESTPD ymm ymm -// VTESTPD m256 ymm -func VTESTPD(mxy, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VTESTPD", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VTESTPD", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VTESTPD", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VTESTPD", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VTESTPD: bad operands") +// VUNPCKLPS.BCST.Z m32 xmm k xmm +// VUNPCKLPS.BCST.Z m32 ymm k ymm +// VUNPCKLPS.BCST.Z m32 zmm k zmm +func VUNPCKLPS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVUNPCKLPS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// VTESTPS: Packed Single-Precision Floating-Point Bit Test. +// VUNPCKLPS_Z: Unpack and Interleave Low Packed Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VTESTPS xmm xmm -// VTESTPS m128 xmm -// VTESTPS ymm ymm -// VTESTPS m256 ymm -func VTESTPS(mxy, xy operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VTESTPS", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy): - return &intrep.Instruction{ - Opcode: "VTESTPS", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VTESTPS", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy): - return &intrep.Instruction{ - Opcode: "VTESTPS", - Operands: []operand.Op{mxy, xy}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VTESTPS: bad operands") +// VUNPCKLPS.Z m128 xmm k xmm +// VUNPCKLPS.Z m256 ymm k ymm +// VUNPCKLPS.Z xmm xmm k xmm +// VUNPCKLPS.Z ymm ymm k ymm +// VUNPCKLPS.Z m512 zmm k zmm +// VUNPCKLPS.Z zmm zmm k zmm +func VUNPCKLPS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVUNPCKLPS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// VUCOMISD: Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS. +// VXORPD: Bitwise Logical XOR for Double-Precision Floating-Point Values. // // Forms: // -// VUCOMISD xmm xmm -// VUCOMISD m64 xmm -func VUCOMISD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VUCOMISD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM64(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VUCOMISD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VUCOMISD: bad operands") +// VXORPD m128 xmm xmm +// VXORPD m256 ymm ymm +// VXORPD xmm xmm xmm +// VXORPD ymm ymm ymm +// VXORPD m128 xmm k xmm +// VXORPD m256 ymm k ymm +// VXORPD xmm xmm k xmm +// VXORPD ymm ymm k ymm +// VXORPD m512 zmm k zmm +// VXORPD m512 zmm zmm +// VXORPD zmm zmm k zmm +// VXORPD zmm zmm zmm +func VXORPD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVXORPD.Forms(), sffxs{}, ops) } -// VUCOMISS: Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS. +// VXORPD_BCST: Bitwise Logical XOR for Double-Precision Floating-Point Values (Broadcast). // // Forms: // -// VUCOMISS xmm xmm -// VUCOMISS m32 xmm -func VUCOMISS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VUCOMISS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM32(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "VUCOMISS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VUCOMISS: bad operands") +// VXORPD.BCST m64 xmm k xmm +// VXORPD.BCST m64 xmm xmm +// VXORPD.BCST m64 ymm k ymm +// VXORPD.BCST m64 ymm ymm +// VXORPD.BCST m64 zmm k zmm +// VXORPD.BCST m64 zmm zmm +func VXORPD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVXORPD.Forms(), sffxs{sffxBCST}, ops) } -// VUNPCKHPD: Unpack and Interleave High Packed Double-Precision Floating-Point Values. +// VXORPD_BCST_Z: Bitwise Logical XOR for Double-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VUNPCKHPD xmm xmm xmm -// VUNPCKHPD m128 xmm xmm -// VUNPCKHPD ymm ymm ymm -// VUNPCKHPD m256 ymm ymm -func VUNPCKHPD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VUNPCKHPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VUNPCKHPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VUNPCKHPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VUNPCKHPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VUNPCKHPD: bad operands") +// VXORPD.BCST.Z m64 xmm k xmm +// VXORPD.BCST.Z m64 ymm k ymm +// VXORPD.BCST.Z m64 zmm k zmm +func VXORPD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVXORPD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// VUNPCKHPS: Unpack and Interleave High Packed Single-Precision Floating-Point Values. +// VXORPD_Z: Bitwise Logical XOR for Double-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VUNPCKHPS xmm xmm xmm -// VUNPCKHPS m128 xmm xmm -// VUNPCKHPS ymm ymm ymm -// VUNPCKHPS m256 ymm ymm -func VUNPCKHPS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VUNPCKHPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VUNPCKHPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VUNPCKHPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VUNPCKHPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VUNPCKHPS: bad operands") +// VXORPD.Z m128 xmm k xmm +// VXORPD.Z m256 ymm k ymm +// VXORPD.Z xmm xmm k xmm +// VXORPD.Z ymm ymm k ymm +// VXORPD.Z m512 zmm k zmm +// VXORPD.Z zmm zmm k zmm +func VXORPD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVXORPD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } -// VUNPCKLPD: Unpack and Interleave Low Packed Double-Precision Floating-Point Values. +// VXORPS: Bitwise Logical XOR for Single-Precision Floating-Point Values. // // Forms: // -// VUNPCKLPD xmm xmm xmm -// VUNPCKLPD m128 xmm xmm -// VUNPCKLPD ymm ymm ymm -// VUNPCKLPD m256 ymm ymm -func VUNPCKLPD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VUNPCKLPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VUNPCKLPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VUNPCKLPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VUNPCKLPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VUNPCKLPD: bad operands") +// VXORPS m128 xmm xmm +// VXORPS m256 ymm ymm +// VXORPS xmm xmm xmm +// VXORPS ymm ymm ymm +// VXORPS m128 xmm k xmm +// VXORPS m256 ymm k ymm +// VXORPS xmm xmm k xmm +// VXORPS ymm ymm k ymm +// VXORPS m512 zmm k zmm +// VXORPS m512 zmm zmm +// VXORPS zmm zmm k zmm +// VXORPS zmm zmm zmm +func VXORPS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVXORPS.Forms(), sffxs{}, ops) } -// VUNPCKLPS: Unpack and Interleave Low Packed Single-Precision Floating-Point Values. +// VXORPS_BCST: Bitwise Logical XOR for Single-Precision Floating-Point Values (Broadcast). // // Forms: // -// VUNPCKLPS xmm xmm xmm -// VUNPCKLPS m128 xmm xmm -// VUNPCKLPS ymm ymm ymm -// VUNPCKLPS m256 ymm ymm -func VUNPCKLPS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VUNPCKLPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VUNPCKLPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VUNPCKLPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VUNPCKLPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VUNPCKLPS: bad operands") +// VXORPS.BCST m32 xmm k xmm +// VXORPS.BCST m32 xmm xmm +// VXORPS.BCST m32 ymm k ymm +// VXORPS.BCST m32 ymm ymm +// VXORPS.BCST m32 zmm k zmm +// VXORPS.BCST m32 zmm zmm +func VXORPS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVXORPS.Forms(), sffxs{sffxBCST}, ops) } -// VXORPD: Bitwise Logical XOR for Double-Precision Floating-Point Values. +// VXORPS_BCST_Z: Bitwise Logical XOR for Single-Precision Floating-Point Values (Broadcast, Zeroing Masking). // // Forms: // -// VXORPD xmm xmm xmm -// VXORPD m128 xmm xmm -// VXORPD ymm ymm ymm -// VXORPD m256 ymm ymm -func VXORPD(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VXORPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VXORPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VXORPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - CancellingInputs: true, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VXORPD", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VXORPD: bad operands") +// VXORPS.BCST.Z m32 xmm k xmm +// VXORPS.BCST.Z m32 ymm k ymm +// VXORPS.BCST.Z m32 zmm k zmm +func VXORPS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVXORPS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) } -// VXORPS: Bitwise Logical XOR for Single-Precision Floating-Point Values. +// VXORPS_Z: Bitwise Logical XOR for Single-Precision Floating-Point Values (Zeroing Masking). // // Forms: // -// VXORPS xmm xmm xmm -// VXORPS m128 xmm xmm -// VXORPS ymm ymm ymm -// VXORPS m256 ymm ymm -func VXORPS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VXORPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mxy) && operand.IsXMM(xy) && operand.IsXMM(xy1): - return &intrep.Instruction{ - Opcode: "VXORPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - case operand.IsYMM(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VXORPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - CancellingInputs: true, - }, nil - case operand.IsM256(mxy) && operand.IsYMM(xy) && operand.IsYMM(xy1): - return &intrep.Instruction{ - Opcode: "VXORPS", - Operands: []operand.Op{mxy, xy, xy1}, - Inputs: []operand.Op{mxy, xy}, - Outputs: []operand.Op{xy1}, - ISA: []string{"AVX"}, - }, nil - } - return nil, errors.New("VXORPS: bad operands") +// VXORPS.Z m128 xmm k xmm +// VXORPS.Z m256 ymm k ymm +// VXORPS.Z xmm xmm k xmm +// VXORPS.Z ymm ymm k ymm +// VXORPS.Z m512 zmm k zmm +// VXORPS.Z zmm zmm k zmm +func VXORPS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVXORPS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } // VZEROALL: Zero All YMM Registers. @@ -33946,13 +37142,7 @@ func VXORPS(mxy, xy, xy1 operand.Op) (*intrep.Instruction, error) { // // VZEROALL func VZEROALL() (*intrep.Instruction, error) { - return &intrep.Instruction{ - Opcode: "VZEROALL", - Operands: nil, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - ISA: []string{"AVX"}, - }, nil + return build(opcVZEROALL.Forms(), sffxs{}, []operand.Op{}) } // VZEROUPPER: Zero Upper Bits of YMM Registers. @@ -33961,301 +37151,97 @@ func VZEROALL() (*intrep.Instruction, error) { // // VZEROUPPER func VZEROUPPER() (*intrep.Instruction, error) { - return &intrep.Instruction{ - Opcode: "VZEROUPPER", - Operands: nil, - Inputs: []operand.Op{}, - Outputs: []operand.Op{}, - ISA: []string{"AVX"}, - }, nil + return build(opcVZEROUPPER.Forms(), sffxs{}, []operand.Op{}) } // XADDB: Exchange and Add. // // Forms: // -// XADDB r8 r8 // XADDB r8 m8 +// XADDB r8 r8 func XADDB(r, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(r) && operand.IsR8(mr): - return &intrep.Instruction{ - Opcode: "XADDB", - Operands: []operand.Op{r, mr}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{r, mr}, - }, nil - case operand.IsR8(r) && operand.IsM8(mr): - return &intrep.Instruction{ - Opcode: "XADDB", - Operands: []operand.Op{r, mr}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{r, mr}, - }, nil - } - return nil, errors.New("XADDB: bad operands") + return build(opcXADDB.Forms(), sffxs{}, []operand.Op{r, mr}) } // XADDL: Exchange and Add. // // Forms: // -// XADDL r32 r32 // XADDL r32 m32 +// XADDL r32 r32 func XADDL(r, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(r) && operand.IsR32(mr): - return &intrep.Instruction{ - Opcode: "XADDL", - Operands: []operand.Op{r, mr}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{r, mr}, - }, nil - case operand.IsR32(r) && operand.IsM32(mr): - return &intrep.Instruction{ - Opcode: "XADDL", - Operands: []operand.Op{r, mr}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{r, mr}, - }, nil - } - return nil, errors.New("XADDL: bad operands") + return build(opcXADDL.Forms(), sffxs{}, []operand.Op{r, mr}) } // XADDQ: Exchange and Add. // // Forms: // -// XADDQ r64 r64 // XADDQ r64 m64 +// XADDQ r64 r64 func XADDQ(r, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(r) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "XADDQ", - Operands: []operand.Op{r, mr}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{r, mr}, - }, nil - case operand.IsR64(r) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "XADDQ", - Operands: []operand.Op{r, mr}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{r, mr}, - }, nil - } - return nil, errors.New("XADDQ: bad operands") + return build(opcXADDQ.Forms(), sffxs{}, []operand.Op{r, mr}) } // XADDW: Exchange and Add. // // Forms: // -// XADDW r16 r16 // XADDW r16 m16 +// XADDW r16 r16 func XADDW(r, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(r) && operand.IsR16(mr): - return &intrep.Instruction{ - Opcode: "XADDW", - Operands: []operand.Op{r, mr}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{r, mr}, - }, nil - case operand.IsR16(r) && operand.IsM16(mr): - return &intrep.Instruction{ - Opcode: "XADDW", - Operands: []operand.Op{r, mr}, - Inputs: []operand.Op{r, mr}, - Outputs: []operand.Op{r, mr}, - }, nil - } - return nil, errors.New("XADDW: bad operands") + return build(opcXADDW.Forms(), sffxs{}, []operand.Op{r, mr}) } // XCHGB: Exchange Register/Memory with Register. // // Forms: // -// XCHGB r8 r8 // XCHGB m8 r8 // XCHGB r8 m8 +// XCHGB r8 r8 func XCHGB(mr, mr1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR8(mr) && operand.IsR8(mr1): - return &intrep.Instruction{ - Opcode: "XCHGB", - Operands: []operand.Op{mr, mr1}, - Inputs: []operand.Op{mr, mr1}, - Outputs: []operand.Op{mr, mr1}, - }, nil - case operand.IsM8(mr) && operand.IsR8(mr1): - return &intrep.Instruction{ - Opcode: "XCHGB", - Operands: []operand.Op{mr, mr1}, - Inputs: []operand.Op{mr, mr1}, - Outputs: []operand.Op{mr, mr1}, - }, nil - case operand.IsR8(mr) && operand.IsM8(mr1): - return &intrep.Instruction{ - Opcode: "XCHGB", - Operands: []operand.Op{mr, mr1}, - Inputs: []operand.Op{mr, mr1}, - Outputs: []operand.Op{mr, mr1}, - }, nil - } - return nil, errors.New("XCHGB: bad operands") + return build(opcXCHGB.Forms(), sffxs{}, []operand.Op{mr, mr1}) } // XCHGL: Exchange Register/Memory with Register. // // Forms: // -// XCHGL r32 eax // XCHGL eax r32 -// XCHGL r32 r32 // XCHGL m32 r32 +// XCHGL r32 eax // XCHGL r32 m32 +// XCHGL r32 r32 func XCHGL(emr, emr1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR32(emr) && operand.IsEAX(emr1): - return &intrep.Instruction{ - Opcode: "XCHGL", - Operands: []operand.Op{emr, emr1}, - Inputs: []operand.Op{emr, emr1}, - Outputs: []operand.Op{emr, emr1}, - }, nil - case operand.IsEAX(emr) && operand.IsR32(emr1): - return &intrep.Instruction{ - Opcode: "XCHGL", - Operands: []operand.Op{emr, emr1}, - Inputs: []operand.Op{emr, emr1}, - Outputs: []operand.Op{emr, emr1}, - }, nil - case operand.IsR32(emr) && operand.IsR32(emr1): - return &intrep.Instruction{ - Opcode: "XCHGL", - Operands: []operand.Op{emr, emr1}, - Inputs: []operand.Op{emr, emr1}, - Outputs: []operand.Op{emr, emr1}, - }, nil - case operand.IsM32(emr) && operand.IsR32(emr1): - return &intrep.Instruction{ - Opcode: "XCHGL", - Operands: []operand.Op{emr, emr1}, - Inputs: []operand.Op{emr, emr1}, - Outputs: []operand.Op{emr, emr1}, - }, nil - case operand.IsR32(emr) && operand.IsM32(emr1): - return &intrep.Instruction{ - Opcode: "XCHGL", - Operands: []operand.Op{emr, emr1}, - Inputs: []operand.Op{emr, emr1}, - Outputs: []operand.Op{emr, emr1}, - }, nil - } - return nil, errors.New("XCHGL: bad operands") + return build(opcXCHGL.Forms(), sffxs{}, []operand.Op{emr, emr1}) } // XCHGQ: Exchange Register/Memory with Register. // // Forms: // -// XCHGQ r64 rax -// XCHGQ rax r64 -// XCHGQ r64 r64 // XCHGQ m64 r64 // XCHGQ r64 m64 +// XCHGQ r64 r64 +// XCHGQ r64 rax +// XCHGQ rax r64 func XCHGQ(mr, mr1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR64(mr) && operand.IsRAX(mr1): - return &intrep.Instruction{ - Opcode: "XCHGQ", - Operands: []operand.Op{mr, mr1}, - Inputs: []operand.Op{mr, mr1}, - Outputs: []operand.Op{mr, mr1}, - }, nil - case operand.IsRAX(mr) && operand.IsR64(mr1): - return &intrep.Instruction{ - Opcode: "XCHGQ", - Operands: []operand.Op{mr, mr1}, - Inputs: []operand.Op{mr, mr1}, - Outputs: []operand.Op{mr, mr1}, - }, nil - case operand.IsR64(mr) && operand.IsR64(mr1): - return &intrep.Instruction{ - Opcode: "XCHGQ", - Operands: []operand.Op{mr, mr1}, - Inputs: []operand.Op{mr, mr1}, - Outputs: []operand.Op{mr, mr1}, - }, nil - case operand.IsM64(mr) && operand.IsR64(mr1): - return &intrep.Instruction{ - Opcode: "XCHGQ", - Operands: []operand.Op{mr, mr1}, - Inputs: []operand.Op{mr, mr1}, - Outputs: []operand.Op{mr, mr1}, - }, nil - case operand.IsR64(mr) && operand.IsM64(mr1): - return &intrep.Instruction{ - Opcode: "XCHGQ", - Operands: []operand.Op{mr, mr1}, - Inputs: []operand.Op{mr, mr1}, - Outputs: []operand.Op{mr, mr1}, - }, nil - } - return nil, errors.New("XCHGQ: bad operands") + return build(opcXCHGQ.Forms(), sffxs{}, []operand.Op{mr, mr1}) } // XCHGW: Exchange Register/Memory with Register. // // Forms: // -// XCHGW r16 ax // XCHGW ax r16 -// XCHGW r16 r16 // XCHGW m16 r16 +// XCHGW r16 ax // XCHGW r16 m16 +// XCHGW r16 r16 func XCHGW(amr, amr1 operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsR16(amr) && operand.IsAX(amr1): - return &intrep.Instruction{ - Opcode: "XCHGW", - Operands: []operand.Op{amr, amr1}, - Inputs: []operand.Op{amr, amr1}, - Outputs: []operand.Op{amr, amr1}, - }, nil - case operand.IsAX(amr) && operand.IsR16(amr1): - return &intrep.Instruction{ - Opcode: "XCHGW", - Operands: []operand.Op{amr, amr1}, - Inputs: []operand.Op{amr, amr1}, - Outputs: []operand.Op{amr, amr1}, - }, nil - case operand.IsR16(amr) && operand.IsR16(amr1): - return &intrep.Instruction{ - Opcode: "XCHGW", - Operands: []operand.Op{amr, amr1}, - Inputs: []operand.Op{amr, amr1}, - Outputs: []operand.Op{amr, amr1}, - }, nil - case operand.IsM16(amr) && operand.IsR16(amr1): - return &intrep.Instruction{ - Opcode: "XCHGW", - Operands: []operand.Op{amr, amr1}, - Inputs: []operand.Op{amr, amr1}, - Outputs: []operand.Op{amr, amr1}, - }, nil - case operand.IsR16(amr) && operand.IsM16(amr1): - return &intrep.Instruction{ - Opcode: "XCHGW", - Operands: []operand.Op{amr, amr1}, - Inputs: []operand.Op{amr, amr1}, - Outputs: []operand.Op{amr, amr1}, - }, nil - } - return nil, errors.New("XCHGW: bad operands") + return build(opcXCHGW.Forms(), sffxs{}, []operand.Op{amr, amr1}) } // XGETBV: Get Value of Extended Control Register. @@ -34264,12 +37250,7 @@ func XCHGW(amr, amr1 operand.Op) (*intrep.Instruction, error) { // // XGETBV func XGETBV() (*intrep.Instruction, error) { - return &intrep.Instruction{ - Opcode: "XGETBV", - Operands: nil, - Inputs: []operand.Op{reg.ECX}, - Outputs: []operand.Op{reg.EAX, reg.EDX}, - }, nil + return build(opcXGETBV.Forms(), sffxs{}, []operand.Op{}) } // XLAT: Table Look-up Translation. @@ -34278,12 +37259,7 @@ func XGETBV() (*intrep.Instruction, error) { // // XLAT func XLAT() (*intrep.Instruction, error) { - return &intrep.Instruction{ - Opcode: "XLAT", - Operands: nil, - Inputs: []operand.Op{reg.AL, reg.EBX}, - Outputs: []operand.Op{reg.AL}, - }, nil + return build(opcXLAT.Forms(), sffxs{}, []operand.Op{}) } // XORB: Logical Exclusive OR. @@ -34291,58 +37267,13 @@ func XLAT() (*intrep.Instruction, error) { // Forms: // // XORB imm8 al +// XORB imm8 m8 // XORB imm8 r8 -// XORB r8 r8 // XORB m8 r8 -// XORB imm8 m8 // XORB r8 m8 +// XORB r8 r8 func XORB(imr, amr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM8(imr) && operand.IsAL(amr): - return &intrep.Instruction{ - Opcode: "XORB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM8(imr) && operand.IsR8(amr): - return &intrep.Instruction{ - Opcode: "XORB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsR8(imr) && operand.IsR8(amr): - return &intrep.Instruction{ - Opcode: "XORB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - CancellingInputs: true, - }, nil - case operand.IsM8(imr) && operand.IsR8(amr): - return &intrep.Instruction{ - Opcode: "XORB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM8(imr) && operand.IsM8(amr): - return &intrep.Instruction{ - Opcode: "XORB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsR8(imr) && operand.IsM8(amr): - return &intrep.Instruction{ - Opcode: "XORB", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - } - return nil, errors.New("XORB: bad operands") + return build(opcXORB.Forms(), sffxs{}, []operand.Op{imr, amr}) } // XORL: Logical Exclusive OR. @@ -34350,207 +37281,51 @@ func XORB(imr, amr operand.Op) (*intrep.Instruction, error) { // Forms: // // XORL imm32 eax -// XORL imm8 r32 +// XORL imm32 m32 // XORL imm32 r32 -// XORL r32 r32 -// XORL m32 r32 // XORL imm8 m32 -// XORL imm32 m32 +// XORL imm8 r32 +// XORL m32 r32 // XORL r32 m32 +// XORL r32 r32 func XORL(imr, emr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM32(imr) && operand.IsEAX(emr): - return &intrep.Instruction{ - Opcode: "XORL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsIMM8(imr) && operand.IsR32(emr): - return &intrep.Instruction{ - Opcode: "XORL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsIMM32(imr) && operand.IsR32(emr): - return &intrep.Instruction{ - Opcode: "XORL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsR32(imr) && operand.IsR32(emr): - return &intrep.Instruction{ - Opcode: "XORL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{imr, emr}, - Outputs: []operand.Op{emr}, - CancellingInputs: true, - }, nil - case operand.IsM32(imr) && operand.IsR32(emr): - return &intrep.Instruction{ - Opcode: "XORL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{imr, emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsIMM8(imr) && operand.IsM32(emr): - return &intrep.Instruction{ - Opcode: "XORL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsIMM32(imr) && operand.IsM32(emr): - return &intrep.Instruction{ - Opcode: "XORL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{emr}, - Outputs: []operand.Op{emr}, - }, nil - case operand.IsR32(imr) && operand.IsM32(emr): - return &intrep.Instruction{ - Opcode: "XORL", - Operands: []operand.Op{imr, emr}, - Inputs: []operand.Op{imr, emr}, - Outputs: []operand.Op{emr}, - }, nil - } - return nil, errors.New("XORL: bad operands") + return build(opcXORL.Forms(), sffxs{}, []operand.Op{imr, emr}) } // XORPD: Bitwise Logical XOR for Double-Precision Floating-Point Values. // // Forms: // -// XORPD xmm xmm // XORPD m128 xmm +// XORPD xmm xmm func XORPD(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "XORPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "XORPD", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE2"}, - }, nil - } - return nil, errors.New("XORPD: bad operands") + return build(opcXORPD.Forms(), sffxs{}, []operand.Op{mx, x}) } // XORPS: Bitwise Logical XOR for Single-Precision Floating-Point Values. // // Forms: // -// XORPS xmm xmm // XORPS m128 xmm +// XORPS xmm xmm func XORPS(mx, x operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsXMM(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "XORPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - CancellingInputs: true, - }, nil - case operand.IsM128(mx) && operand.IsXMM(x): - return &intrep.Instruction{ - Opcode: "XORPS", - Operands: []operand.Op{mx, x}, - Inputs: []operand.Op{mx, x}, - Outputs: []operand.Op{x}, - ISA: []string{"SSE"}, - }, nil - } - return nil, errors.New("XORPS: bad operands") + return build(opcXORPS.Forms(), sffxs{}, []operand.Op{mx, x}) } // XORQ: Logical Exclusive OR. // // Forms: // +// XORQ imm32 m64 +// XORQ imm32 r64 // XORQ imm32 rax +// XORQ imm8 m64 // XORQ imm8 r64 -// XORQ imm32 r64 -// XORQ r64 r64 // XORQ m64 r64 -// XORQ imm8 m64 -// XORQ imm32 m64 // XORQ r64 m64 +// XORQ r64 r64 func XORQ(imr, mr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM32(imr) && operand.IsRAX(mr): - return &intrep.Instruction{ - Opcode: "XORQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(imr) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "XORQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM32(imr) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "XORQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR64(imr) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "XORQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{imr, mr}, - Outputs: []operand.Op{mr}, - CancellingInputs: true, - }, nil - case operand.IsM64(imr) && operand.IsR64(mr): - return &intrep.Instruction{ - Opcode: "XORQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{imr, mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM8(imr) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "XORQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsIMM32(imr) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "XORQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{mr}, - Outputs: []operand.Op{mr}, - }, nil - case operand.IsR64(imr) && operand.IsM64(mr): - return &intrep.Instruction{ - Opcode: "XORQ", - Operands: []operand.Op{imr, mr}, - Inputs: []operand.Op{imr, mr}, - Outputs: []operand.Op{mr}, - }, nil - } - return nil, errors.New("XORQ: bad operands") + return build(opcXORQ.Forms(), sffxs{}, []operand.Op{imr, mr}) } // XORW: Logical Exclusive OR. @@ -34558,72 +37333,13 @@ func XORQ(imr, mr operand.Op) (*intrep.Instruction, error) { // Forms: // // XORW imm16 ax -// XORW imm8 r16 +// XORW imm16 m16 // XORW imm16 r16 -// XORW r16 r16 -// XORW m16 r16 // XORW imm8 m16 -// XORW imm16 m16 +// XORW imm8 r16 +// XORW m16 r16 // XORW r16 m16 +// XORW r16 r16 func XORW(imr, amr operand.Op) (*intrep.Instruction, error) { - switch { - case operand.IsIMM16(imr) && operand.IsAX(amr): - return &intrep.Instruction{ - Opcode: "XORW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM8(imr) && operand.IsR16(amr): - return &intrep.Instruction{ - Opcode: "XORW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM16(imr) && operand.IsR16(amr): - return &intrep.Instruction{ - Opcode: "XORW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsR16(imr) && operand.IsR16(amr): - return &intrep.Instruction{ - Opcode: "XORW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - CancellingInputs: true, - }, nil - case operand.IsM16(imr) && operand.IsR16(amr): - return &intrep.Instruction{ - Opcode: "XORW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM8(imr) && operand.IsM16(amr): - return &intrep.Instruction{ - Opcode: "XORW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsIMM16(imr) && operand.IsM16(amr): - return &intrep.Instruction{ - Opcode: "XORW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{amr}, - Outputs: []operand.Op{amr}, - }, nil - case operand.IsR16(imr) && operand.IsM16(amr): - return &intrep.Instruction{ - Opcode: "XORW", - Operands: []operand.Op{imr, amr}, - Inputs: []operand.Op{imr, amr}, - Outputs: []operand.Op{amr}, - }, nil - } - return nil, errors.New("XORW: bad operands") + return build(opcXORW.Forms(), sffxs{}, []operand.Op{imr, amr}) } diff --git a/x86/zctors_test.go b/x86/zctors_test.go index 1c703399..aa169f60 100644 --- a/x86/zctors_test.go +++ b/x86/zctors_test.go @@ -1,5 +1,8 @@ // Code generated by command: avogen -output zctors_test.go ctorstest. DO NOT EDIT. +//go:build !integration +// +build !integration + package x86 import ( @@ -10,18908 +13,46407 @@ import ( "github.com/mmcloughlin/avo/reg" ) -func TestADCBValidForms(t *testing.T) { - t.Run("form=imm8_al", func(t *testing.T) { - if _, err := ADCB(operand.Imm(math.MaxInt8), reg.AL); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r8", func(t *testing.T) { - if _, err := ADCB(operand.Imm(math.MaxInt8), reg.CH); err != nil { - t.Fatal(err) - } - if _, err := ADCB(operand.Imm(math.MaxInt8), reg.BL); err != nil { - t.Fatal(err) - } - if _, err := ADCB(operand.Imm(math.MaxInt8), reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r8_r8", func(t *testing.T) { - if _, err := ADCB(reg.CH, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := ADCB(reg.CH, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := ADCB(reg.CH, reg.R13B); err != nil { - t.Fatal(err) - } - if _, err := ADCB(reg.BL, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := ADCB(reg.BL, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := ADCB(reg.BL, reg.R13B); err != nil { - t.Fatal(err) - } - if _, err := ADCB(reg.R13B, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := ADCB(reg.R13B, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := ADCB(reg.R13B, reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8_r8", func(t *testing.T) { - if _, err := ADCB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := ADCB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := ADCB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m8", func(t *testing.T) { - if _, err := ADCB(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r8_m8", func(t *testing.T) { - if _, err := ADCB(reg.CH, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - if _, err := ADCB(reg.BL, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - if _, err := ADCB(reg.R13B, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestADCLValidForms(t *testing.T) { - t.Run("form=imm32_eax", func(t *testing.T) { - if _, err := ADCL(operand.Imm(math.MaxInt32), reg.EAX); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r32", func(t *testing.T) { - if _, err := ADCL(operand.Imm(math.MaxInt8), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_r32", func(t *testing.T) { - if _, err := ADCL(operand.Imm(math.MaxInt32), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := ADCL(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := ADCL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m32", func(t *testing.T) { - if _, err := ADCL(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_m32", func(t *testing.T) { - if _, err := ADCL(operand.Imm(math.MaxInt32), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_m32", func(t *testing.T) { - if _, err := ADCL(reg.R10L, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestADCQValidForms(t *testing.T) { - t.Run("form=imm32_rax", func(t *testing.T) { - if _, err := ADCQ(operand.Imm(math.MaxInt32), reg.RAX); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r64", func(t *testing.T) { - if _, err := ADCQ(operand.Imm(math.MaxInt8), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_r64", func(t *testing.T) { - if _, err := ADCQ(operand.Imm(math.MaxInt32), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := ADCQ(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := ADCQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m64", func(t *testing.T) { - if _, err := ADCQ(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_m64", func(t *testing.T) { - if _, err := ADCQ(operand.Imm(math.MaxInt32), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_m64", func(t *testing.T) { - if _, err := ADCQ(reg.R11, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestADCWValidForms(t *testing.T) { - t.Run("form=imm16_ax", func(t *testing.T) { - if _, err := ADCW(operand.Imm(math.MaxInt16), reg.AX); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r16", func(t *testing.T) { - if _, err := ADCW(operand.Imm(math.MaxInt8), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := ADCW(operand.Imm(math.MaxInt8), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm16_r16", func(t *testing.T) { - if _, err := ADCW(operand.Imm(math.MaxInt16), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := ADCW(operand.Imm(math.MaxInt16), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := ADCW(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := ADCW(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := ADCW(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := ADCW(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := ADCW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := ADCW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m16", func(t *testing.T) { - if _, err := ADCW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm16_m16", func(t *testing.T) { - if _, err := ADCW(operand.Imm(math.MaxInt16), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_m16", func(t *testing.T) { - if _, err := ADCW(reg.CX, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - if _, err := ADCW(reg.R9W, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestADCXLValidForms(t *testing.T) { - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := ADCXL(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := ADCXL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestADCXQValidForms(t *testing.T) { - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := ADCXQ(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := ADCXQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestADDBValidForms(t *testing.T) { - t.Run("form=imm8_al", func(t *testing.T) { - if _, err := ADDB(operand.Imm(math.MaxInt8), reg.AL); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r8", func(t *testing.T) { - if _, err := ADDB(operand.Imm(math.MaxInt8), reg.CH); err != nil { - t.Fatal(err) - } - if _, err := ADDB(operand.Imm(math.MaxInt8), reg.BL); err != nil { - t.Fatal(err) - } - if _, err := ADDB(operand.Imm(math.MaxInt8), reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r8_r8", func(t *testing.T) { - if _, err := ADDB(reg.CH, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := ADDB(reg.CH, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := ADDB(reg.CH, reg.R13B); err != nil { - t.Fatal(err) - } - if _, err := ADDB(reg.BL, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := ADDB(reg.BL, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := ADDB(reg.BL, reg.R13B); err != nil { - t.Fatal(err) - } - if _, err := ADDB(reg.R13B, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := ADDB(reg.R13B, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := ADDB(reg.R13B, reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8_r8", func(t *testing.T) { - if _, err := ADDB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := ADDB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := ADDB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m8", func(t *testing.T) { - if _, err := ADDB(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r8_m8", func(t *testing.T) { - if _, err := ADDB(reg.CH, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - if _, err := ADDB(reg.BL, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - if _, err := ADDB(reg.R13B, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestADDLValidForms(t *testing.T) { - t.Run("form=imm32_eax", func(t *testing.T) { - if _, err := ADDL(operand.Imm(math.MaxInt32), reg.EAX); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r32", func(t *testing.T) { - if _, err := ADDL(operand.Imm(math.MaxInt8), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_r32", func(t *testing.T) { - if _, err := ADDL(operand.Imm(math.MaxInt32), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := ADDL(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := ADDL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m32", func(t *testing.T) { - if _, err := ADDL(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_m32", func(t *testing.T) { - if _, err := ADDL(operand.Imm(math.MaxInt32), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_m32", func(t *testing.T) { - if _, err := ADDL(reg.R10L, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestADDPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := ADDPD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := ADDPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestADDPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := ADDPS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := ADDPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestADDQValidForms(t *testing.T) { - t.Run("form=imm32_rax", func(t *testing.T) { - if _, err := ADDQ(operand.Imm(math.MaxInt32), reg.RAX); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r64", func(t *testing.T) { - if _, err := ADDQ(operand.Imm(math.MaxInt8), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_r64", func(t *testing.T) { - if _, err := ADDQ(operand.Imm(math.MaxInt32), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := ADDQ(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := ADDQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m64", func(t *testing.T) { - if _, err := ADDQ(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_m64", func(t *testing.T) { - if _, err := ADDQ(operand.Imm(math.MaxInt32), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_m64", func(t *testing.T) { - if _, err := ADDQ(reg.R11, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestADDSDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := ADDSD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := ADDSD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestADDSSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := ADDSS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := ADDSS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestADDSUBPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := ADDSUBPD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := ADDSUBPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestADDSUBPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := ADDSUBPS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := ADDSUBPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestADDWValidForms(t *testing.T) { - t.Run("form=imm16_ax", func(t *testing.T) { - if _, err := ADDW(operand.Imm(math.MaxInt16), reg.AX); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r16", func(t *testing.T) { - if _, err := ADDW(operand.Imm(math.MaxInt8), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := ADDW(operand.Imm(math.MaxInt8), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm16_r16", func(t *testing.T) { - if _, err := ADDW(operand.Imm(math.MaxInt16), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := ADDW(operand.Imm(math.MaxInt16), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := ADDW(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := ADDW(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := ADDW(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := ADDW(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := ADDW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := ADDW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m16", func(t *testing.T) { - if _, err := ADDW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm16_m16", func(t *testing.T) { - if _, err := ADDW(operand.Imm(math.MaxInt16), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_m16", func(t *testing.T) { - if _, err := ADDW(reg.CX, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - if _, err := ADDW(reg.R9W, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestADOXLValidForms(t *testing.T) { - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := ADOXL(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := ADOXL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestADOXQValidForms(t *testing.T) { - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := ADOXQ(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := ADOXQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestAESDECValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := AESDEC(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := AESDEC(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestAESDECLASTValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := AESDECLAST(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := AESDECLAST(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestAESENCValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := AESENC(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := AESENC(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestAESENCLASTValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := AESENCLAST(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := AESENCLAST(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestAESIMCValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := AESIMC(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := AESIMC(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestAESKEYGENASSISTValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := AESKEYGENASSIST(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := AESKEYGENASSIST(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestANDBValidForms(t *testing.T) { - t.Run("form=imm8_al", func(t *testing.T) { - if _, err := ANDB(operand.Imm(math.MaxInt8), reg.AL); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r8", func(t *testing.T) { - if _, err := ANDB(operand.Imm(math.MaxInt8), reg.CH); err != nil { - t.Fatal(err) - } - if _, err := ANDB(operand.Imm(math.MaxInt8), reg.BL); err != nil { - t.Fatal(err) - } - if _, err := ANDB(operand.Imm(math.MaxInt8), reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r8_r8", func(t *testing.T) { - if _, err := ANDB(reg.CH, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := ANDB(reg.CH, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := ANDB(reg.CH, reg.R13B); err != nil { - t.Fatal(err) - } - if _, err := ANDB(reg.BL, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := ANDB(reg.BL, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := ANDB(reg.BL, reg.R13B); err != nil { - t.Fatal(err) - } - if _, err := ANDB(reg.R13B, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := ANDB(reg.R13B, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := ANDB(reg.R13B, reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8_r8", func(t *testing.T) { - if _, err := ANDB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := ANDB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := ANDB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m8", func(t *testing.T) { - if _, err := ANDB(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r8_m8", func(t *testing.T) { - if _, err := ANDB(reg.CH, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - if _, err := ANDB(reg.BL, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - if _, err := ANDB(reg.R13B, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestANDLValidForms(t *testing.T) { - t.Run("form=imm32_eax", func(t *testing.T) { - if _, err := ANDL(operand.Imm(math.MaxInt32), reg.EAX); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r32", func(t *testing.T) { - if _, err := ANDL(operand.Imm(math.MaxInt8), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_r32", func(t *testing.T) { - if _, err := ANDL(operand.Imm(math.MaxInt32), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := ANDL(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := ANDL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m32", func(t *testing.T) { - if _, err := ANDL(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_m32", func(t *testing.T) { - if _, err := ANDL(operand.Imm(math.MaxInt32), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_m32", func(t *testing.T) { - if _, err := ANDL(reg.R10L, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestANDNLValidForms(t *testing.T) { - t.Run("form=r32_r32_r32", func(t *testing.T) { - if _, err := ANDNL(reg.R10L, reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32_r32", func(t *testing.T) { - if _, err := ANDNL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestANDNPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := ANDNPD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := ANDNPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestANDNPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := ANDNPS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := ANDNPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestANDNQValidForms(t *testing.T) { - t.Run("form=r64_r64_r64", func(t *testing.T) { - if _, err := ANDNQ(reg.R11, reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64_r64", func(t *testing.T) { - if _, err := ANDNQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestANDPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := ANDPD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := ANDPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestANDPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := ANDPS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := ANDPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestANDQValidForms(t *testing.T) { - t.Run("form=imm32_rax", func(t *testing.T) { - if _, err := ANDQ(operand.Imm(math.MaxInt32), reg.RAX); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r64", func(t *testing.T) { - if _, err := ANDQ(operand.Imm(math.MaxInt8), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_r64", func(t *testing.T) { - if _, err := ANDQ(operand.Imm(math.MaxInt32), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := ANDQ(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := ANDQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m64", func(t *testing.T) { - if _, err := ANDQ(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_m64", func(t *testing.T) { - if _, err := ANDQ(operand.Imm(math.MaxInt32), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_m64", func(t *testing.T) { - if _, err := ANDQ(reg.R11, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestANDWValidForms(t *testing.T) { - t.Run("form=imm16_ax", func(t *testing.T) { - if _, err := ANDW(operand.Imm(math.MaxInt16), reg.AX); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r16", func(t *testing.T) { - if _, err := ANDW(operand.Imm(math.MaxInt8), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := ANDW(operand.Imm(math.MaxInt8), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm16_r16", func(t *testing.T) { - if _, err := ANDW(operand.Imm(math.MaxInt16), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := ANDW(operand.Imm(math.MaxInt16), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := ANDW(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := ANDW(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := ANDW(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := ANDW(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := ANDW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := ANDW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m16", func(t *testing.T) { - if _, err := ANDW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm16_m16", func(t *testing.T) { - if _, err := ANDW(operand.Imm(math.MaxInt16), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_m16", func(t *testing.T) { - if _, err := ANDW(reg.CX, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - if _, err := ANDW(reg.R9W, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestBEXTRLValidForms(t *testing.T) { - t.Run("form=r32_r32_r32", func(t *testing.T) { - if _, err := BEXTRL(reg.R10L, reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_m32_r32", func(t *testing.T) { - if _, err := BEXTRL(reg.R10L, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestBEXTRQValidForms(t *testing.T) { - t.Run("form=r64_r64_r64", func(t *testing.T) { - if _, err := BEXTRQ(reg.R11, reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_m64_r64", func(t *testing.T) { - if _, err := BEXTRQ(reg.R11, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestBLENDPDValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := BLENDPD(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := BLENDPD(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestBLENDPSValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := BLENDPS(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := BLENDPS(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestBLENDVPDValidForms(t *testing.T) { - t.Run("form=xmm0_xmm_xmm", func(t *testing.T) { - if _, err := BLENDVPD(reg.X0, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm0_m128_xmm", func(t *testing.T) { - if _, err := BLENDVPD(reg.X0, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestBLENDVPSValidForms(t *testing.T) { - t.Run("form=xmm0_xmm_xmm", func(t *testing.T) { - if _, err := BLENDVPS(reg.X0, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm0_m128_xmm", func(t *testing.T) { - if _, err := BLENDVPS(reg.X0, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestBLSILValidForms(t *testing.T) { - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := BLSIL(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := BLSIL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestBLSIQValidForms(t *testing.T) { - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := BLSIQ(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := BLSIQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestBLSMSKLValidForms(t *testing.T) { - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := BLSMSKL(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := BLSMSKL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestBLSMSKQValidForms(t *testing.T) { - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := BLSMSKQ(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := BLSMSKQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestBLSRLValidForms(t *testing.T) { - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := BLSRL(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := BLSRL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestBLSRQValidForms(t *testing.T) { - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := BLSRQ(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := BLSRQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestBSFLValidForms(t *testing.T) { - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := BSFL(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := BSFL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestBSFQValidForms(t *testing.T) { - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := BSFQ(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := BSFQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestBSFWValidForms(t *testing.T) { - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := BSFW(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := BSFW(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := BSFW(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := BSFW(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := BSFW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := BSFW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) -} - -func TestBSRLValidForms(t *testing.T) { - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := BSRL(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := BSRL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestBSRQValidForms(t *testing.T) { - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := BSRQ(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := BSRQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestBSRWValidForms(t *testing.T) { - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := BSRW(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := BSRW(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := BSRW(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := BSRW(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := BSRW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := BSRW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) -} - -func TestBSWAPLValidForms(t *testing.T) { - t.Run("form=r32", func(t *testing.T) { - if _, err := BSWAPL(reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestBSWAPQValidForms(t *testing.T) { - t.Run("form=r64", func(t *testing.T) { - if _, err := BSWAPQ(reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestBTCLValidForms(t *testing.T) { - t.Run("form=imm8_r32", func(t *testing.T) { - if _, err := BTCL(operand.Imm(math.MaxInt8), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := BTCL(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m32", func(t *testing.T) { - if _, err := BTCL(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_m32", func(t *testing.T) { - if _, err := BTCL(reg.R10L, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestBTCQValidForms(t *testing.T) { - t.Run("form=imm8_r64", func(t *testing.T) { - if _, err := BTCQ(operand.Imm(math.MaxInt8), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := BTCQ(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m64", func(t *testing.T) { - if _, err := BTCQ(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_m64", func(t *testing.T) { - if _, err := BTCQ(reg.R11, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestBTCWValidForms(t *testing.T) { - t.Run("form=imm8_r16", func(t *testing.T) { - if _, err := BTCW(operand.Imm(math.MaxInt8), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := BTCW(operand.Imm(math.MaxInt8), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := BTCW(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := BTCW(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := BTCW(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := BTCW(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m16", func(t *testing.T) { - if _, err := BTCW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_m16", func(t *testing.T) { - if _, err := BTCW(reg.CX, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - if _, err := BTCW(reg.R9W, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestBTLValidForms(t *testing.T) { - t.Run("form=imm8_r32", func(t *testing.T) { - if _, err := BTL(operand.Imm(math.MaxInt8), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := BTL(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m32", func(t *testing.T) { - if _, err := BTL(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_m32", func(t *testing.T) { - if _, err := BTL(reg.R10L, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestBTQValidForms(t *testing.T) { - t.Run("form=imm8_r64", func(t *testing.T) { - if _, err := BTQ(operand.Imm(math.MaxInt8), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := BTQ(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m64", func(t *testing.T) { - if _, err := BTQ(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_m64", func(t *testing.T) { - if _, err := BTQ(reg.R11, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestBTRLValidForms(t *testing.T) { - t.Run("form=imm8_r32", func(t *testing.T) { - if _, err := BTRL(operand.Imm(math.MaxInt8), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := BTRL(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m32", func(t *testing.T) { - if _, err := BTRL(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_m32", func(t *testing.T) { - if _, err := BTRL(reg.R10L, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestBTRQValidForms(t *testing.T) { - t.Run("form=imm8_r64", func(t *testing.T) { - if _, err := BTRQ(operand.Imm(math.MaxInt8), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := BTRQ(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m64", func(t *testing.T) { - if _, err := BTRQ(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_m64", func(t *testing.T) { - if _, err := BTRQ(reg.R11, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestBTRWValidForms(t *testing.T) { - t.Run("form=imm8_r16", func(t *testing.T) { - if _, err := BTRW(operand.Imm(math.MaxInt8), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := BTRW(operand.Imm(math.MaxInt8), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := BTRW(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := BTRW(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := BTRW(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := BTRW(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m16", func(t *testing.T) { - if _, err := BTRW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_m16", func(t *testing.T) { - if _, err := BTRW(reg.CX, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - if _, err := BTRW(reg.R9W, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestBTSLValidForms(t *testing.T) { - t.Run("form=imm8_r32", func(t *testing.T) { - if _, err := BTSL(operand.Imm(math.MaxInt8), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := BTSL(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m32", func(t *testing.T) { - if _, err := BTSL(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_m32", func(t *testing.T) { - if _, err := BTSL(reg.R10L, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestBTSQValidForms(t *testing.T) { - t.Run("form=imm8_r64", func(t *testing.T) { - if _, err := BTSQ(operand.Imm(math.MaxInt8), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := BTSQ(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m64", func(t *testing.T) { - if _, err := BTSQ(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_m64", func(t *testing.T) { - if _, err := BTSQ(reg.R11, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestBTSWValidForms(t *testing.T) { - t.Run("form=imm8_r16", func(t *testing.T) { - if _, err := BTSW(operand.Imm(math.MaxInt8), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := BTSW(operand.Imm(math.MaxInt8), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := BTSW(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := BTSW(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := BTSW(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := BTSW(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m16", func(t *testing.T) { - if _, err := BTSW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_m16", func(t *testing.T) { - if _, err := BTSW(reg.CX, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - if _, err := BTSW(reg.R9W, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestBTWValidForms(t *testing.T) { - t.Run("form=imm8_r16", func(t *testing.T) { - if _, err := BTW(operand.Imm(math.MaxInt8), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := BTW(operand.Imm(math.MaxInt8), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := BTW(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := BTW(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := BTW(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := BTW(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m16", func(t *testing.T) { - if _, err := BTW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_m16", func(t *testing.T) { - if _, err := BTW(reg.CX, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - if _, err := BTW(reg.R9W, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestBZHILValidForms(t *testing.T) { - t.Run("form=r32_r32_r32", func(t *testing.T) { - if _, err := BZHIL(reg.R10L, reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_m32_r32", func(t *testing.T) { - if _, err := BZHIL(reg.R10L, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestBZHIQValidForms(t *testing.T) { - t.Run("form=r64_r64_r64", func(t *testing.T) { - if _, err := BZHIQ(reg.R11, reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_m64_r64", func(t *testing.T) { - if _, err := BZHIQ(reg.R11, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestCALLValidForms(t *testing.T) { - t.Run("form=rel32", func(t *testing.T) { - if _, err := CALL(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := CALL(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestCBWValidForms(t *testing.T) { - t.Run("form=", func(t *testing.T) { - if _, err := CBW(); err != nil { - t.Fatal(err) - } - }) -} - -func TestCDQValidForms(t *testing.T) { - t.Run("form=", func(t *testing.T) { - if _, err := CDQ(); err != nil { - t.Fatal(err) - } - }) -} - -func TestCDQEValidForms(t *testing.T) { - t.Run("form=", func(t *testing.T) { - if _, err := CDQE(); err != nil { - t.Fatal(err) - } - }) -} - -func TestCLCValidForms(t *testing.T) { - t.Run("form=", func(t *testing.T) { - if _, err := CLC(); err != nil { - t.Fatal(err) - } - }) -} - -func TestCLDValidForms(t *testing.T) { - t.Run("form=", func(t *testing.T) { - if _, err := CLD(); err != nil { - t.Fatal(err) - } - }) -} - -func TestCLFLUSHValidForms(t *testing.T) { - t.Run("form=m8", func(t *testing.T) { - if _, err := CLFLUSH(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestCLFLUSHOPTValidForms(t *testing.T) { - t.Run("form=m8", func(t *testing.T) { - if _, err := CLFLUSHOPT(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMCValidForms(t *testing.T) { - t.Run("form=", func(t *testing.T) { - if _, err := CMC(); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVLCCValidForms(t *testing.T) { - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := CMOVLCC(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := CMOVLCC(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVLCSValidForms(t *testing.T) { - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := CMOVLCS(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := CMOVLCS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVLEQValidForms(t *testing.T) { - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := CMOVLEQ(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := CMOVLEQ(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVLGEValidForms(t *testing.T) { - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := CMOVLGE(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := CMOVLGE(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVLGTValidForms(t *testing.T) { - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := CMOVLGT(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := CMOVLGT(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVLHIValidForms(t *testing.T) { - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := CMOVLHI(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := CMOVLHI(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVLLEValidForms(t *testing.T) { - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := CMOVLLE(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := CMOVLLE(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVLLSValidForms(t *testing.T) { - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := CMOVLLS(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := CMOVLLS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVLLTValidForms(t *testing.T) { - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := CMOVLLT(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := CMOVLLT(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVLMIValidForms(t *testing.T) { - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := CMOVLMI(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := CMOVLMI(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVLNEValidForms(t *testing.T) { - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := CMOVLNE(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := CMOVLNE(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVLOCValidForms(t *testing.T) { - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := CMOVLOC(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := CMOVLOC(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVLOSValidForms(t *testing.T) { - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := CMOVLOS(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := CMOVLOS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVLPCValidForms(t *testing.T) { - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := CMOVLPC(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := CMOVLPC(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVLPLValidForms(t *testing.T) { - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := CMOVLPL(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := CMOVLPL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVLPSValidForms(t *testing.T) { - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := CMOVLPS(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := CMOVLPS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVQCCValidForms(t *testing.T) { - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := CMOVQCC(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := CMOVQCC(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVQCSValidForms(t *testing.T) { - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := CMOVQCS(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := CMOVQCS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVQEQValidForms(t *testing.T) { - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := CMOVQEQ(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := CMOVQEQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVQGEValidForms(t *testing.T) { - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := CMOVQGE(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := CMOVQGE(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVQGTValidForms(t *testing.T) { - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := CMOVQGT(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := CMOVQGT(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVQHIValidForms(t *testing.T) { - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := CMOVQHI(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := CMOVQHI(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVQLEValidForms(t *testing.T) { - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := CMOVQLE(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := CMOVQLE(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVQLSValidForms(t *testing.T) { - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := CMOVQLS(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := CMOVQLS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVQLTValidForms(t *testing.T) { - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := CMOVQLT(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := CMOVQLT(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVQMIValidForms(t *testing.T) { - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := CMOVQMI(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := CMOVQMI(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVQNEValidForms(t *testing.T) { - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := CMOVQNE(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := CMOVQNE(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVQOCValidForms(t *testing.T) { - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := CMOVQOC(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := CMOVQOC(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVQOSValidForms(t *testing.T) { - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := CMOVQOS(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := CMOVQOS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVQPCValidForms(t *testing.T) { - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := CMOVQPC(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := CMOVQPC(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVQPLValidForms(t *testing.T) { - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := CMOVQPL(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := CMOVQPL(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVQPSValidForms(t *testing.T) { - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := CMOVQPS(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := CMOVQPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVWCCValidForms(t *testing.T) { - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := CMOVWCC(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWCC(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := CMOVWCC(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWCC(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := CMOVWCC(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWCC(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVWCSValidForms(t *testing.T) { - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := CMOVWCS(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWCS(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := CMOVWCS(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWCS(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := CMOVWCS(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWCS(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVWEQValidForms(t *testing.T) { - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := CMOVWEQ(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWEQ(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := CMOVWEQ(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWEQ(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := CMOVWEQ(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWEQ(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVWGEValidForms(t *testing.T) { - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := CMOVWGE(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWGE(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := CMOVWGE(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWGE(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := CMOVWGE(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWGE(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVWGTValidForms(t *testing.T) { - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := CMOVWGT(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWGT(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := CMOVWGT(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWGT(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := CMOVWGT(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWGT(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVWHIValidForms(t *testing.T) { - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := CMOVWHI(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWHI(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := CMOVWHI(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWHI(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := CMOVWHI(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWHI(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVWLEValidForms(t *testing.T) { - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := CMOVWLE(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWLE(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := CMOVWLE(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWLE(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := CMOVWLE(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWLE(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVWLSValidForms(t *testing.T) { - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := CMOVWLS(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWLS(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := CMOVWLS(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWLS(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := CMOVWLS(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWLS(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVWLTValidForms(t *testing.T) { - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := CMOVWLT(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWLT(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := CMOVWLT(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWLT(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := CMOVWLT(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWLT(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVWMIValidForms(t *testing.T) { - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := CMOVWMI(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWMI(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := CMOVWMI(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWMI(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := CMOVWMI(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWMI(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVWNEValidForms(t *testing.T) { - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := CMOVWNE(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWNE(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := CMOVWNE(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWNE(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := CMOVWNE(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWNE(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVWOCValidForms(t *testing.T) { - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := CMOVWOC(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWOC(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := CMOVWOC(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWOC(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := CMOVWOC(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWOC(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVWOSValidForms(t *testing.T) { - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := CMOVWOS(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWOS(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := CMOVWOS(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWOS(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := CMOVWOS(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWOS(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVWPCValidForms(t *testing.T) { - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := CMOVWPC(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWPC(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := CMOVWPC(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWPC(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := CMOVWPC(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWPC(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVWPLValidForms(t *testing.T) { - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := CMOVWPL(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWPL(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := CMOVWPL(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWPL(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := CMOVWPL(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWPL(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMOVWPSValidForms(t *testing.T) { - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := CMOVWPS(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWPS(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := CMOVWPS(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWPS(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := CMOVWPS(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMOVWPS(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMPBValidForms(t *testing.T) { - t.Run("form=al_imm8", func(t *testing.T) { - if _, err := CMPB(reg.AL, operand.Imm(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r8_imm8", func(t *testing.T) { - if _, err := CMPB(reg.CH, operand.Imm(math.MaxInt8)); err != nil { - t.Fatal(err) - } - if _, err := CMPB(reg.BL, operand.Imm(math.MaxInt8)); err != nil { - t.Fatal(err) - } - if _, err := CMPB(reg.R13B, operand.Imm(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r8_r8", func(t *testing.T) { - if _, err := CMPB(reg.CH, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := CMPB(reg.CH, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := CMPB(reg.CH, reg.R13B); err != nil { - t.Fatal(err) - } - if _, err := CMPB(reg.BL, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := CMPB(reg.BL, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := CMPB(reg.BL, reg.R13B); err != nil { - t.Fatal(err) - } - if _, err := CMPB(reg.R13B, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := CMPB(reg.R13B, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := CMPB(reg.R13B, reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r8_m8", func(t *testing.T) { - if _, err := CMPB(reg.CH, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - if _, err := CMPB(reg.BL, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - if _, err := CMPB(reg.R13B, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8_imm8", func(t *testing.T) { - if _, err := CMPB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, operand.Imm(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8_r8", func(t *testing.T) { - if _, err := CMPB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := CMPB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := CMPB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.R13B); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMPLValidForms(t *testing.T) { - t.Run("form=eax_imm32", func(t *testing.T) { - if _, err := CMPL(reg.EAX, operand.Imm(math.MaxInt32)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_imm8", func(t *testing.T) { - if _, err := CMPL(reg.R10L, operand.Imm(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_imm32", func(t *testing.T) { - if _, err := CMPL(reg.R10L, operand.Imm(math.MaxInt32)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := CMPL(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_m32", func(t *testing.T) { - if _, err := CMPL(reg.R10L, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_imm8", func(t *testing.T) { - if _, err := CMPL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, operand.Imm(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_imm32", func(t *testing.T) { - if _, err := CMPL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, operand.Imm(math.MaxInt32)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := CMPL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMPPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_imm8", func(t *testing.T) { - if _, err := CMPPD(reg.X7, reg.X7, operand.Imm(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_imm8", func(t *testing.T) { - if _, err := CMPPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, operand.Imm(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMPPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_imm8", func(t *testing.T) { - if _, err := CMPPS(reg.X7, reg.X7, operand.Imm(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_imm8", func(t *testing.T) { - if _, err := CMPPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, operand.Imm(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMPQValidForms(t *testing.T) { - t.Run("form=rax_imm32", func(t *testing.T) { - if _, err := CMPQ(reg.RAX, operand.Imm(math.MaxInt32)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_imm8", func(t *testing.T) { - if _, err := CMPQ(reg.R11, operand.Imm(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_imm32", func(t *testing.T) { - if _, err := CMPQ(reg.R11, operand.Imm(math.MaxInt32)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := CMPQ(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_m64", func(t *testing.T) { - if _, err := CMPQ(reg.R11, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_imm8", func(t *testing.T) { - if _, err := CMPQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, operand.Imm(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_imm32", func(t *testing.T) { - if _, err := CMPQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, operand.Imm(math.MaxInt32)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := CMPQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMPSDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_imm8", func(t *testing.T) { - if _, err := CMPSD(reg.X7, reg.X7, operand.Imm(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm_imm8", func(t *testing.T) { - if _, err := CMPSD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, operand.Imm(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMPSSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_imm8", func(t *testing.T) { - if _, err := CMPSS(reg.X7, reg.X7, operand.Imm(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm_imm8", func(t *testing.T) { - if _, err := CMPSS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7, operand.Imm(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMPWValidForms(t *testing.T) { - t.Run("form=ax_imm16", func(t *testing.T) { - if _, err := CMPW(reg.AX, operand.Imm(math.MaxInt16)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_imm8", func(t *testing.T) { - if _, err := CMPW(reg.CX, operand.Imm(math.MaxInt8)); err != nil { - t.Fatal(err) - } - if _, err := CMPW(reg.R9W, operand.Imm(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_imm16", func(t *testing.T) { - if _, err := CMPW(reg.CX, operand.Imm(math.MaxInt16)); err != nil { - t.Fatal(err) - } - if _, err := CMPW(reg.R9W, operand.Imm(math.MaxInt16)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := CMPW(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMPW(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := CMPW(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMPW(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_m16", func(t *testing.T) { - if _, err := CMPW(reg.CX, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - if _, err := CMPW(reg.R9W, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_imm8", func(t *testing.T) { - if _, err := CMPW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, operand.Imm(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_imm16", func(t *testing.T) { - if _, err := CMPW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, operand.Imm(math.MaxInt16)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := CMPW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMPW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMPXCHG16BValidForms(t *testing.T) { - t.Run("form=m128", func(t *testing.T) { - if _, err := CMPXCHG16B(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMPXCHG8BValidForms(t *testing.T) { - t.Run("form=m64", func(t *testing.T) { - if _, err := CMPXCHG8B(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMPXCHGBValidForms(t *testing.T) { - t.Run("form=r8_r8", func(t *testing.T) { - if _, err := CMPXCHGB(reg.CH, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := CMPXCHGB(reg.CH, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := CMPXCHGB(reg.CH, reg.R13B); err != nil { - t.Fatal(err) - } - if _, err := CMPXCHGB(reg.BL, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := CMPXCHGB(reg.BL, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := CMPXCHGB(reg.BL, reg.R13B); err != nil { - t.Fatal(err) - } - if _, err := CMPXCHGB(reg.R13B, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := CMPXCHGB(reg.R13B, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := CMPXCHGB(reg.R13B, reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r8_m8", func(t *testing.T) { - if _, err := CMPXCHGB(reg.CH, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - if _, err := CMPXCHGB(reg.BL, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - if _, err := CMPXCHGB(reg.R13B, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMPXCHGLValidForms(t *testing.T) { - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := CMPXCHGL(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_m32", func(t *testing.T) { - if _, err := CMPXCHGL(reg.R10L, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMPXCHGQValidForms(t *testing.T) { - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := CMPXCHGQ(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_m64", func(t *testing.T) { - if _, err := CMPXCHGQ(reg.R11, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestCMPXCHGWValidForms(t *testing.T) { - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := CMPXCHGW(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMPXCHGW(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := CMPXCHGW(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := CMPXCHGW(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_m16", func(t *testing.T) { - if _, err := CMPXCHGW(reg.CX, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - if _, err := CMPXCHGW(reg.R9W, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestCOMISDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := COMISD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := COMISD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestCOMISSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := COMISS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := COMISS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestCPUIDValidForms(t *testing.T) { - t.Run("form=", func(t *testing.T) { - if _, err := CPUID(); err != nil { - t.Fatal(err) - } - }) -} - -func TestCQOValidForms(t *testing.T) { - t.Run("form=", func(t *testing.T) { - if _, err := CQO(); err != nil { - t.Fatal(err) - } - }) -} - -func TestCRC32BValidForms(t *testing.T) { - t.Run("form=r8_r32", func(t *testing.T) { - if _, err := CRC32B(reg.CH, reg.R10L); err != nil { - t.Fatal(err) - } - if _, err := CRC32B(reg.BL, reg.R10L); err != nil { - t.Fatal(err) - } - if _, err := CRC32B(reg.R13B, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8_r32", func(t *testing.T) { - if _, err := CRC32B(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r8_r64", func(t *testing.T) { - if _, err := CRC32B(reg.CH, reg.R11); err != nil { - t.Fatal(err) - } - if _, err := CRC32B(reg.BL, reg.R11); err != nil { - t.Fatal(err) - } - if _, err := CRC32B(reg.R13B, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8_r64", func(t *testing.T) { - if _, err := CRC32B(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestCRC32LValidForms(t *testing.T) { - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := CRC32L(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := CRC32L(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestCRC32QValidForms(t *testing.T) { - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := CRC32Q(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := CRC32Q(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestCRC32WValidForms(t *testing.T) { - t.Run("form=r16_r32", func(t *testing.T) { - if _, err := CRC32W(reg.CX, reg.R10L); err != nil { - t.Fatal(err) - } - if _, err := CRC32W(reg.R9W, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r32", func(t *testing.T) { - if _, err := CRC32W(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestCVTPD2PLValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := CVTPD2PL(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := CVTPD2PL(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestCVTPD2PSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := CVTPD2PS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := CVTPD2PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestCVTPL2PDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := CVTPL2PD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := CVTPL2PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestCVTPL2PSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := CVTPL2PS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := CVTPL2PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestCVTPS2PDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := CVTPS2PD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := CVTPS2PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestCVTPS2PLValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := CVTPS2PL(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := CVTPS2PL(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestCVTSD2SLValidForms(t *testing.T) { - t.Run("form=xmm_r32", func(t *testing.T) { - if _, err := CVTSD2SL(reg.X7, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r32", func(t *testing.T) { - if _, err := CVTSD2SL(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_r64", func(t *testing.T) { - if _, err := CVTSD2SL(reg.X7, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := CVTSD2SL(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestCVTSD2SSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := CVTSD2SS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := CVTSD2SS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestCVTSL2SDValidForms(t *testing.T) { - t.Run("form=r32_xmm", func(t *testing.T) { - if _, err := CVTSL2SD(reg.R10L, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := CVTSL2SD(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestCVTSL2SSValidForms(t *testing.T) { - t.Run("form=r32_xmm", func(t *testing.T) { - if _, err := CVTSL2SS(reg.R10L, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := CVTSL2SS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestCVTSQ2SDValidForms(t *testing.T) { - t.Run("form=r64_xmm", func(t *testing.T) { - if _, err := CVTSQ2SD(reg.R11, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := CVTSQ2SD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestCVTSQ2SSValidForms(t *testing.T) { - t.Run("form=r64_xmm", func(t *testing.T) { - if _, err := CVTSQ2SS(reg.R11, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := CVTSQ2SS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestCVTSS2SDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := CVTSS2SD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := CVTSS2SD(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestCVTSS2SLValidForms(t *testing.T) { - t.Run("form=xmm_r32", func(t *testing.T) { - if _, err := CVTSS2SL(reg.X7, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := CVTSS2SL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_r64", func(t *testing.T) { - if _, err := CVTSS2SL(reg.X7, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r64", func(t *testing.T) { - if _, err := CVTSS2SL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestCVTTPD2PLValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := CVTTPD2PL(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := CVTTPD2PL(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestCVTTPS2PLValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := CVTTPS2PL(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := CVTTPS2PL(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestCVTTSD2SLValidForms(t *testing.T) { - t.Run("form=xmm_r32", func(t *testing.T) { - if _, err := CVTTSD2SL(reg.X7, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r32", func(t *testing.T) { - if _, err := CVTTSD2SL(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestCVTTSD2SQValidForms(t *testing.T) { - t.Run("form=xmm_r64", func(t *testing.T) { - if _, err := CVTTSD2SQ(reg.X7, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := CVTTSD2SQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestCVTTSS2SLValidForms(t *testing.T) { - t.Run("form=xmm_r32", func(t *testing.T) { - if _, err := CVTTSS2SL(reg.X7, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := CVTTSS2SL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_r64", func(t *testing.T) { - if _, err := CVTTSS2SL(reg.X7, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r64", func(t *testing.T) { - if _, err := CVTTSS2SL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestCWDValidForms(t *testing.T) { - t.Run("form=", func(t *testing.T) { - if _, err := CWD(); err != nil { - t.Fatal(err) - } - }) -} - -func TestCWDEValidForms(t *testing.T) { - t.Run("form=", func(t *testing.T) { - if _, err := CWDE(); err != nil { - t.Fatal(err) - } - }) -} - -func TestDECBValidForms(t *testing.T) { - t.Run("form=r8", func(t *testing.T) { - if _, err := DECB(reg.CH); err != nil { - t.Fatal(err) - } - if _, err := DECB(reg.BL); err != nil { - t.Fatal(err) - } - if _, err := DECB(reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8", func(t *testing.T) { - if _, err := DECB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestDECLValidForms(t *testing.T) { - t.Run("form=r32", func(t *testing.T) { - if _, err := DECL(reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32", func(t *testing.T) { - if _, err := DECL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestDECQValidForms(t *testing.T) { - t.Run("form=r64", func(t *testing.T) { - if _, err := DECQ(reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64", func(t *testing.T) { - if _, err := DECQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestDECWValidForms(t *testing.T) { - t.Run("form=r16", func(t *testing.T) { - if _, err := DECW(reg.CX); err != nil { - t.Fatal(err) - } - if _, err := DECW(reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16", func(t *testing.T) { - if _, err := DECW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestDIVBValidForms(t *testing.T) { - t.Run("form=r8", func(t *testing.T) { - if _, err := DIVB(reg.CH); err != nil { - t.Fatal(err) - } - if _, err := DIVB(reg.BL); err != nil { - t.Fatal(err) - } - if _, err := DIVB(reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8", func(t *testing.T) { - if _, err := DIVB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestDIVLValidForms(t *testing.T) { - t.Run("form=r32", func(t *testing.T) { - if _, err := DIVL(reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32", func(t *testing.T) { - if _, err := DIVL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestDIVPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := DIVPD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := DIVPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestDIVPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := DIVPS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := DIVPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestDIVQValidForms(t *testing.T) { - t.Run("form=r64", func(t *testing.T) { - if _, err := DIVQ(reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64", func(t *testing.T) { - if _, err := DIVQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestDIVSDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := DIVSD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := DIVSD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestDIVSSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := DIVSS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := DIVSS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestDIVWValidForms(t *testing.T) { - t.Run("form=r16", func(t *testing.T) { - if _, err := DIVW(reg.CX); err != nil { - t.Fatal(err) - } - if _, err := DIVW(reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16", func(t *testing.T) { - if _, err := DIVW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestDPPDValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := DPPD(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := DPPD(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestDPPSValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := DPPS(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := DPPS(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestEXTRACTPSValidForms(t *testing.T) { - t.Run("form=imm2u_xmm_r32", func(t *testing.T) { - if _, err := EXTRACTPS(operand.Imm(1), reg.X7, reg.R10L); err != nil { - t.Fatal(err) - } - if _, err := EXTRACTPS(operand.Imm(3), reg.X7, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm2u_xmm_m32", func(t *testing.T) { - if _, err := EXTRACTPS(operand.Imm(1), reg.X7, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - if _, err := EXTRACTPS(operand.Imm(3), reg.X7, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestHADDPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := HADDPD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := HADDPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestHADDPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := HADDPS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := HADDPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestHSUBPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := HSUBPD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := HSUBPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestHSUBPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := HSUBPS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := HSUBPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestIDIVBValidForms(t *testing.T) { - t.Run("form=r8", func(t *testing.T) { - if _, err := IDIVB(reg.CH); err != nil { - t.Fatal(err) - } - if _, err := IDIVB(reg.BL); err != nil { - t.Fatal(err) - } - if _, err := IDIVB(reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8", func(t *testing.T) { - if _, err := IDIVB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestIDIVLValidForms(t *testing.T) { - t.Run("form=r32", func(t *testing.T) { - if _, err := IDIVL(reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32", func(t *testing.T) { - if _, err := IDIVL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestIDIVQValidForms(t *testing.T) { - t.Run("form=r64", func(t *testing.T) { - if _, err := IDIVQ(reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64", func(t *testing.T) { - if _, err := IDIVQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestIDIVWValidForms(t *testing.T) { - t.Run("form=r16", func(t *testing.T) { - if _, err := IDIVW(reg.CX); err != nil { - t.Fatal(err) - } - if _, err := IDIVW(reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16", func(t *testing.T) { - if _, err := IDIVW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestIMUL3LValidForms(t *testing.T) { - t.Run("form=imm8_r32_r32", func(t *testing.T) { - if _, err := IMUL3L(operand.Imm(math.MaxInt8), reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_r32_r32", func(t *testing.T) { - if _, err := IMUL3L(operand.Imm(math.MaxInt32), reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m32_r32", func(t *testing.T) { - if _, err := IMUL3L(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_m32_r32", func(t *testing.T) { - if _, err := IMUL3L(operand.Imm(math.MaxInt32), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestIMUL3QValidForms(t *testing.T) { - t.Run("form=imm8_r64_r64", func(t *testing.T) { - if _, err := IMUL3Q(operand.Imm(math.MaxInt8), reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_r64_r64", func(t *testing.T) { - if _, err := IMUL3Q(operand.Imm(math.MaxInt32), reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m64_r64", func(t *testing.T) { - if _, err := IMUL3Q(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_m64_r64", func(t *testing.T) { - if _, err := IMUL3Q(operand.Imm(math.MaxInt32), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestIMUL3WValidForms(t *testing.T) { - t.Run("form=imm8_r16_r16", func(t *testing.T) { - if _, err := IMUL3W(operand.Imm(math.MaxInt8), reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := IMUL3W(operand.Imm(math.MaxInt8), reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := IMUL3W(operand.Imm(math.MaxInt8), reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := IMUL3W(operand.Imm(math.MaxInt8), reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm16_r16_r16", func(t *testing.T) { - if _, err := IMUL3W(operand.Imm(math.MaxInt16), reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := IMUL3W(operand.Imm(math.MaxInt16), reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := IMUL3W(operand.Imm(math.MaxInt16), reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := IMUL3W(operand.Imm(math.MaxInt16), reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m16_r16", func(t *testing.T) { - if _, err := IMUL3W(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := IMUL3W(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm16_m16_r16", func(t *testing.T) { - if _, err := IMUL3W(operand.Imm(math.MaxInt16), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := IMUL3W(operand.Imm(math.MaxInt16), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) -} - -func TestIMULBValidForms(t *testing.T) { - t.Run("form=r8", func(t *testing.T) { - if _, err := IMULB(reg.CH); err != nil { - t.Fatal(err) - } - if _, err := IMULB(reg.BL); err != nil { - t.Fatal(err) - } - if _, err := IMULB(reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8", func(t *testing.T) { - if _, err := IMULB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestIMULLValidForms(t *testing.T) { - t.Run("form=r32", func(t *testing.T) { - if _, err := IMULL(reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32", func(t *testing.T) { - if _, err := IMULL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := IMULL(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := IMULL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestIMULQValidForms(t *testing.T) { - t.Run("form=r64", func(t *testing.T) { - if _, err := IMULQ(reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64", func(t *testing.T) { - if _, err := IMULQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := IMULQ(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := IMULQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestIMULWValidForms(t *testing.T) { - t.Run("form=r16", func(t *testing.T) { - if _, err := IMULW(reg.CX); err != nil { - t.Fatal(err) - } - if _, err := IMULW(reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16", func(t *testing.T) { - if _, err := IMULW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := IMULW(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := IMULW(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := IMULW(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := IMULW(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := IMULW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := IMULW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) -} - -func TestINCBValidForms(t *testing.T) { - t.Run("form=r8", func(t *testing.T) { - if _, err := INCB(reg.CH); err != nil { - t.Fatal(err) - } - if _, err := INCB(reg.BL); err != nil { - t.Fatal(err) - } - if _, err := INCB(reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8", func(t *testing.T) { - if _, err := INCB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestINCLValidForms(t *testing.T) { - t.Run("form=r32", func(t *testing.T) { - if _, err := INCL(reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32", func(t *testing.T) { - if _, err := INCL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestINCQValidForms(t *testing.T) { - t.Run("form=r64", func(t *testing.T) { - if _, err := INCQ(reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64", func(t *testing.T) { - if _, err := INCQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestINCWValidForms(t *testing.T) { - t.Run("form=r16", func(t *testing.T) { - if _, err := INCW(reg.CX); err != nil { - t.Fatal(err) - } - if _, err := INCW(reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16", func(t *testing.T) { - if _, err := INCW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestINSERTPSValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := INSERTPS(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m32_xmm", func(t *testing.T) { - if _, err := INSERTPS(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestINTValidForms(t *testing.T) { - t.Run("form=3", func(t *testing.T) { - if _, err := INT(operand.Imm(3)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8", func(t *testing.T) { - if _, err := INT(operand.Imm(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) -} - -func TestJAValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JA(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JA(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JA(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJAEValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JAE(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JAE(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JAE(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJBValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JB(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JB(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JB(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJBEValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JBE(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JBE(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JBE(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJCValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JC(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JC(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JC(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJCCValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JCC(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JCC(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JCC(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJCSValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JCS(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JCS(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JCS(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJCXZLValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JCXZL(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) -} - -func TestJCXZQValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JCXZQ(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) -} - -func TestJEValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JE(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JE(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JE(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJEQValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JEQ(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JEQ(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JEQ(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJGValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JG(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JG(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JG(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJGEValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JGE(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JGE(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JGE(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJGTValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JGT(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JGT(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JGT(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJHIValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JHI(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JHI(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JHI(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJHSValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JHS(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JHS(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JHS(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJLValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JL(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JL(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JL(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJLEValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JLE(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JLE(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JLE(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJLOValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JLO(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JLO(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JLO(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJLSValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JLS(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JLS(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JLS(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJLTValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JLT(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JLT(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JLT(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJMIValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JMI(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JMI(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JMI(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJMPValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JMP(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JMP(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JMP(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64", func(t *testing.T) { - if _, err := JMP(reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64", func(t *testing.T) { - if _, err := JMP(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestJNAValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JNA(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JNA(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JNA(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJNAEValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JNAE(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JNAE(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JNAE(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJNBValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JNB(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JNB(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JNB(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJNBEValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JNBE(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JNBE(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JNBE(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJNCValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JNC(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JNC(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JNC(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJNEValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JNE(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JNE(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JNE(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJNGValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JNG(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JNG(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JNG(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJNGEValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JNGE(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JNGE(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JNGE(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJNLValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JNL(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JNL(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JNL(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJNLEValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JNLE(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JNLE(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JNLE(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJNOValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JNO(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JNO(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JNO(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJNPValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JNP(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JNP(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JNP(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJNSValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JNS(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JNS(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JNS(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJNZValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JNZ(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JNZ(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JNZ(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJOValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JO(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JO(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JO(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJOCValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JOC(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JOC(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JOC(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJOSValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JOS(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JOS(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JOS(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJPValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JP(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JP(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JP(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJPCValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JPC(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JPC(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JPC(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJPEValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JPE(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JPE(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JPE(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJPLValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JPL(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JPL(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JPL(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJPOValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JPO(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JPO(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JPO(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJPSValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JPS(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JPS(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JPS(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJSValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JS(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JS(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JS(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestJZValidForms(t *testing.T) { - t.Run("form=rel8", func(t *testing.T) { - if _, err := JZ(operand.Rel(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rel32", func(t *testing.T) { - if _, err := JZ(operand.Rel(math.MaxInt32)); err != nil { - t.Fatal(err) - } - if _, err := JZ(operand.LabelRef("lbl")); err != nil { - t.Fatal(err) - } - }) -} - -func TestLDDQUValidForms(t *testing.T) { - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := LDDQU(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestLDMXCSRValidForms(t *testing.T) { - t.Run("form=m32", func(t *testing.T) { - if _, err := LDMXCSR(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestLEALValidForms(t *testing.T) { - t.Run("form=m_r32", func(t *testing.T) { - if _, err := LEAL(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestLEAQValidForms(t *testing.T) { - t.Run("form=m_r64", func(t *testing.T) { - if _, err := LEAQ(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestLEAWValidForms(t *testing.T) { - t.Run("form=m_r16", func(t *testing.T) { - if _, err := LEAW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := LEAW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) -} - -func TestLFENCEValidForms(t *testing.T) { - t.Run("form=", func(t *testing.T) { - if _, err := LFENCE(); err != nil { - t.Fatal(err) - } - }) -} - -func TestLZCNTLValidForms(t *testing.T) { - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := LZCNTL(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := LZCNTL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestLZCNTQValidForms(t *testing.T) { - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := LZCNTQ(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := LZCNTQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestLZCNTWValidForms(t *testing.T) { - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := LZCNTW(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := LZCNTW(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := LZCNTW(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := LZCNTW(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := LZCNTW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := LZCNTW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) -} - -func TestMASKMOVDQUValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := MASKMOVDQU(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestMASKMOVOUValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := MASKMOVOU(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestMAXPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := MAXPD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := MAXPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestMAXPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := MAXPS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := MAXPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestMAXSDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := MAXSD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := MAXSD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestMAXSSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := MAXSS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := MAXSS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestMFENCEValidForms(t *testing.T) { - t.Run("form=", func(t *testing.T) { - if _, err := MFENCE(); err != nil { - t.Fatal(err) - } - }) -} - -func TestMINPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := MINPD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := MINPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestMINPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := MINPS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := MINPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestMINSDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := MINSD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := MINSD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestMINSSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := MINSS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := MINSS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestMONITORValidForms(t *testing.T) { - t.Run("form=", func(t *testing.T) { - if _, err := MONITOR(); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVAPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := MOVAPD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := MOVAPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m128", func(t *testing.T) { - if _, err := MOVAPD(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVAPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := MOVAPS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := MOVAPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m128", func(t *testing.T) { - if _, err := MOVAPS(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVBValidForms(t *testing.T) { - t.Run("form=imm8_r8", func(t *testing.T) { - if _, err := MOVB(operand.Imm(math.MaxInt8), reg.CH); err != nil { - t.Fatal(err) - } - if _, err := MOVB(operand.Imm(math.MaxInt8), reg.BL); err != nil { - t.Fatal(err) - } - if _, err := MOVB(operand.Imm(math.MaxInt8), reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r8_r8", func(t *testing.T) { - if _, err := MOVB(reg.CH, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := MOVB(reg.CH, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := MOVB(reg.CH, reg.R13B); err != nil { - t.Fatal(err) - } - if _, err := MOVB(reg.BL, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := MOVB(reg.BL, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := MOVB(reg.BL, reg.R13B); err != nil { - t.Fatal(err) - } - if _, err := MOVB(reg.R13B, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := MOVB(reg.R13B, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := MOVB(reg.R13B, reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8_r8", func(t *testing.T) { - if _, err := MOVB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := MOVB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := MOVB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m8", func(t *testing.T) { - if _, err := MOVB(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r8_m8", func(t *testing.T) { - if _, err := MOVB(reg.CH, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - if _, err := MOVB(reg.BL, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - if _, err := MOVB(reg.R13B, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVBELLValidForms(t *testing.T) { - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := MOVBELL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_m32", func(t *testing.T) { - if _, err := MOVBELL(reg.R10L, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVBEQQValidForms(t *testing.T) { - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := MOVBEQQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_m64", func(t *testing.T) { - if _, err := MOVBEQQ(reg.R11, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVBEWWValidForms(t *testing.T) { - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := MOVBEWW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := MOVBEWW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_m16", func(t *testing.T) { - if _, err := MOVBEWW(reg.CX, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - if _, err := MOVBEWW(reg.R9W, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVBLSXValidForms(t *testing.T) { - t.Run("form=r8_r32", func(t *testing.T) { - if _, err := MOVBLSX(reg.CH, reg.R10L); err != nil { - t.Fatal(err) - } - if _, err := MOVBLSX(reg.BL, reg.R10L); err != nil { - t.Fatal(err) - } - if _, err := MOVBLSX(reg.R13B, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8_r32", func(t *testing.T) { - if _, err := MOVBLSX(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVBLZXValidForms(t *testing.T) { - t.Run("form=r8_r32", func(t *testing.T) { - if _, err := MOVBLZX(reg.CH, reg.R10L); err != nil { - t.Fatal(err) - } - if _, err := MOVBLZX(reg.BL, reg.R10L); err != nil { - t.Fatal(err) - } - if _, err := MOVBLZX(reg.R13B, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8_r32", func(t *testing.T) { - if _, err := MOVBLZX(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVBQSXValidForms(t *testing.T) { - t.Run("form=r8_r64", func(t *testing.T) { - if _, err := MOVBQSX(reg.CH, reg.R11); err != nil { - t.Fatal(err) - } - if _, err := MOVBQSX(reg.BL, reg.R11); err != nil { - t.Fatal(err) - } - if _, err := MOVBQSX(reg.R13B, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8_r64", func(t *testing.T) { - if _, err := MOVBQSX(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVBQZXValidForms(t *testing.T) { - t.Run("form=r8_r64", func(t *testing.T) { - if _, err := MOVBQZX(reg.CH, reg.R11); err != nil { - t.Fatal(err) - } - if _, err := MOVBQZX(reg.BL, reg.R11); err != nil { - t.Fatal(err) - } - if _, err := MOVBQZX(reg.R13B, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8_r64", func(t *testing.T) { - if _, err := MOVBQZX(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVBWSXValidForms(t *testing.T) { - t.Run("form=r8_r16", func(t *testing.T) { - if _, err := MOVBWSX(reg.CH, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := MOVBWSX(reg.CH, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := MOVBWSX(reg.BL, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := MOVBWSX(reg.BL, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := MOVBWSX(reg.R13B, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := MOVBWSX(reg.R13B, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8_r16", func(t *testing.T) { - if _, err := MOVBWSX(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := MOVBWSX(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.R9W); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVBWZXValidForms(t *testing.T) { - t.Run("form=r8_r16", func(t *testing.T) { - if _, err := MOVBWZX(reg.CH, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := MOVBWZX(reg.CH, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := MOVBWZX(reg.BL, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := MOVBWZX(reg.BL, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := MOVBWZX(reg.R13B, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := MOVBWZX(reg.R13B, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8_r16", func(t *testing.T) { - if _, err := MOVBWZX(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := MOVBWZX(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.R9W); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVDValidForms(t *testing.T) { - t.Run("form=imm32_r64", func(t *testing.T) { - if _, err := MOVD(operand.Imm(math.MaxInt32), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm64_r64", func(t *testing.T) { - if _, err := MOVD(operand.Imm(math.MaxInt64), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := MOVD(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := MOVD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_m64", func(t *testing.T) { - if _, err := MOVD(operand.Imm(math.MaxInt32), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_m64", func(t *testing.T) { - if _, err := MOVD(reg.R11, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_r64", func(t *testing.T) { - if _, err := MOVD(reg.X7, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_xmm", func(t *testing.T) { - if _, err := MOVD(reg.R11, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := MOVD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := MOVD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m64", func(t *testing.T) { - if _, err := MOVD(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_r32", func(t *testing.T) { - if _, err := MOVD(reg.X7, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_xmm", func(t *testing.T) { - if _, err := MOVD(reg.R10L, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := MOVD(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m32", func(t *testing.T) { - if _, err := MOVD(reg.X7, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVDDUPValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := MOVDDUP(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := MOVDDUP(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVDQ2QValidForms(t *testing.T) { - t.Run("form=imm32_r64", func(t *testing.T) { - if _, err := MOVDQ2Q(operand.Imm(math.MaxInt32), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm64_r64", func(t *testing.T) { - if _, err := MOVDQ2Q(operand.Imm(math.MaxInt64), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := MOVDQ2Q(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := MOVDQ2Q(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_m64", func(t *testing.T) { - if _, err := MOVDQ2Q(operand.Imm(math.MaxInt32), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_m64", func(t *testing.T) { - if _, err := MOVDQ2Q(reg.R11, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_r64", func(t *testing.T) { - if _, err := MOVDQ2Q(reg.X7, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_xmm", func(t *testing.T) { - if _, err := MOVDQ2Q(reg.R11, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := MOVDQ2Q(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := MOVDQ2Q(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m64", func(t *testing.T) { - if _, err := MOVDQ2Q(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_r32", func(t *testing.T) { - if _, err := MOVDQ2Q(reg.X7, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_xmm", func(t *testing.T) { - if _, err := MOVDQ2Q(reg.R10L, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := MOVDQ2Q(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m32", func(t *testing.T) { - if _, err := MOVDQ2Q(reg.X7, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVHLPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := MOVHLPS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVHPDValidForms(t *testing.T) { - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := MOVHPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m64", func(t *testing.T) { - if _, err := MOVHPD(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVHPSValidForms(t *testing.T) { - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := MOVHPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m64", func(t *testing.T) { - if _, err := MOVHPS(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVLValidForms(t *testing.T) { - t.Run("form=imm32_r32", func(t *testing.T) { - if _, err := MOVL(operand.Imm(math.MaxInt32), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := MOVL(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := MOVL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_m32", func(t *testing.T) { - if _, err := MOVL(operand.Imm(math.MaxInt32), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_m32", func(t *testing.T) { - if _, err := MOVL(reg.R10L, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVLHPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := MOVLHPS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVLPDValidForms(t *testing.T) { - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := MOVLPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m64", func(t *testing.T) { - if _, err := MOVLPD(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVLPSValidForms(t *testing.T) { - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := MOVLPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m64", func(t *testing.T) { - if _, err := MOVLPS(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVLQSXValidForms(t *testing.T) { - t.Run("form=r32_r64", func(t *testing.T) { - if _, err := MOVLQSX(reg.R10L, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r64", func(t *testing.T) { - if _, err := MOVLQSX(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVLQZXValidForms(t *testing.T) { - t.Run("form=m32_r64", func(t *testing.T) { - if _, err := MOVLQZX(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVMSKPDValidForms(t *testing.T) { - t.Run("form=xmm_r32", func(t *testing.T) { - if _, err := MOVMSKPD(reg.X7, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVMSKPSValidForms(t *testing.T) { - t.Run("form=xmm_r32", func(t *testing.T) { - if _, err := MOVMSKPS(reg.X7, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVNTDQValidForms(t *testing.T) { - t.Run("form=xmm_m128", func(t *testing.T) { - if _, err := MOVNTDQ(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVNTDQAValidForms(t *testing.T) { - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := MOVNTDQA(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVNTILValidForms(t *testing.T) { - t.Run("form=r32_m32", func(t *testing.T) { - if _, err := MOVNTIL(reg.R10L, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVNTIQValidForms(t *testing.T) { - t.Run("form=r64_m64", func(t *testing.T) { - if _, err := MOVNTIQ(reg.R11, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVNTOValidForms(t *testing.T) { - t.Run("form=xmm_m128", func(t *testing.T) { - if _, err := MOVNTO(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVNTPDValidForms(t *testing.T) { - t.Run("form=xmm_m128", func(t *testing.T) { - if _, err := MOVNTPD(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVNTPSValidForms(t *testing.T) { - t.Run("form=xmm_m128", func(t *testing.T) { - if _, err := MOVNTPS(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVOValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := MOVO(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := MOVO(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m128", func(t *testing.T) { - if _, err := MOVO(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVOAValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := MOVOA(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := MOVOA(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m128", func(t *testing.T) { - if _, err := MOVOA(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVOUValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := MOVOU(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := MOVOU(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m128", func(t *testing.T) { - if _, err := MOVOU(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVQValidForms(t *testing.T) { - t.Run("form=imm32_r64", func(t *testing.T) { - if _, err := MOVQ(operand.Imm(math.MaxInt32), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm64_r64", func(t *testing.T) { - if _, err := MOVQ(operand.Imm(math.MaxInt64), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := MOVQ(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := MOVQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_m64", func(t *testing.T) { - if _, err := MOVQ(operand.Imm(math.MaxInt32), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_m64", func(t *testing.T) { - if _, err := MOVQ(reg.R11, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_r64", func(t *testing.T) { - if _, err := MOVQ(reg.X7, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_xmm", func(t *testing.T) { - if _, err := MOVQ(reg.R11, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := MOVQ(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := MOVQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m64", func(t *testing.T) { - if _, err := MOVQ(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_r32", func(t *testing.T) { - if _, err := MOVQ(reg.X7, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_xmm", func(t *testing.T) { - if _, err := MOVQ(reg.R10L, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := MOVQ(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m32", func(t *testing.T) { - if _, err := MOVQ(reg.X7, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVSDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := MOVSD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := MOVSD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m64", func(t *testing.T) { - if _, err := MOVSD(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVSHDUPValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := MOVSHDUP(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := MOVSHDUP(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVSLDUPValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := MOVSLDUP(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := MOVSLDUP(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVSSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := MOVSS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := MOVSS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m32", func(t *testing.T) { - if _, err := MOVSS(reg.X7, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVUPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := MOVUPD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := MOVUPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m128", func(t *testing.T) { - if _, err := MOVUPD(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVUPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := MOVUPS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := MOVUPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m128", func(t *testing.T) { - if _, err := MOVUPS(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVWValidForms(t *testing.T) { - t.Run("form=imm16_r16", func(t *testing.T) { - if _, err := MOVW(operand.Imm(math.MaxInt16), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := MOVW(operand.Imm(math.MaxInt16), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := MOVW(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := MOVW(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := MOVW(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := MOVW(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := MOVW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := MOVW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm16_m16", func(t *testing.T) { - if _, err := MOVW(operand.Imm(math.MaxInt16), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_m16", func(t *testing.T) { - if _, err := MOVW(reg.CX, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - if _, err := MOVW(reg.R9W, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVWLSXValidForms(t *testing.T) { - t.Run("form=r16_r32", func(t *testing.T) { - if _, err := MOVWLSX(reg.CX, reg.R10L); err != nil { - t.Fatal(err) - } - if _, err := MOVWLSX(reg.R9W, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r32", func(t *testing.T) { - if _, err := MOVWLSX(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVWLZXValidForms(t *testing.T) { - t.Run("form=r16_r32", func(t *testing.T) { - if _, err := MOVWLZX(reg.CX, reg.R10L); err != nil { - t.Fatal(err) - } - if _, err := MOVWLZX(reg.R9W, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r32", func(t *testing.T) { - if _, err := MOVWLZX(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVWQSXValidForms(t *testing.T) { - t.Run("form=r16_r64", func(t *testing.T) { - if _, err := MOVWQSX(reg.CX, reg.R11); err != nil { - t.Fatal(err) - } - if _, err := MOVWQSX(reg.R9W, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r64", func(t *testing.T) { - if _, err := MOVWQSX(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestMOVWQZXValidForms(t *testing.T) { - t.Run("form=r16_r64", func(t *testing.T) { - if _, err := MOVWQZX(reg.CX, reg.R11); err != nil { - t.Fatal(err) - } - if _, err := MOVWQZX(reg.R9W, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r64", func(t *testing.T) { - if _, err := MOVWQZX(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestMPSADBWValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := MPSADBW(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := MPSADBW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestMULBValidForms(t *testing.T) { - t.Run("form=r8", func(t *testing.T) { - if _, err := MULB(reg.CH); err != nil { - t.Fatal(err) - } - if _, err := MULB(reg.BL); err != nil { - t.Fatal(err) - } - if _, err := MULB(reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8", func(t *testing.T) { - if _, err := MULB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMULLValidForms(t *testing.T) { - t.Run("form=r32", func(t *testing.T) { - if _, err := MULL(reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32", func(t *testing.T) { - if _, err := MULL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMULPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := MULPD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := MULPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestMULPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := MULPS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := MULPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestMULQValidForms(t *testing.T) { - t.Run("form=r64", func(t *testing.T) { - if _, err := MULQ(reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64", func(t *testing.T) { - if _, err := MULQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMULSDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := MULSD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := MULSD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestMULSSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := MULSS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := MULSS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestMULWValidForms(t *testing.T) { - t.Run("form=r16", func(t *testing.T) { - if _, err := MULW(reg.CX); err != nil { - t.Fatal(err) - } - if _, err := MULW(reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16", func(t *testing.T) { - if _, err := MULW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestMULXLValidForms(t *testing.T) { - t.Run("form=r32_r32_r32", func(t *testing.T) { - if _, err := MULXL(reg.R10L, reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32_r32", func(t *testing.T) { - if _, err := MULXL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestMULXQValidForms(t *testing.T) { - t.Run("form=r64_r64_r64", func(t *testing.T) { - if _, err := MULXQ(reg.R11, reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64_r64", func(t *testing.T) { - if _, err := MULXQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestMWAITValidForms(t *testing.T) { - t.Run("form=", func(t *testing.T) { - if _, err := MWAIT(); err != nil { - t.Fatal(err) - } - }) -} - -func TestNEGBValidForms(t *testing.T) { - t.Run("form=r8", func(t *testing.T) { - if _, err := NEGB(reg.CH); err != nil { - t.Fatal(err) - } - if _, err := NEGB(reg.BL); err != nil { - t.Fatal(err) - } - if _, err := NEGB(reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8", func(t *testing.T) { - if _, err := NEGB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestNEGLValidForms(t *testing.T) { - t.Run("form=r32", func(t *testing.T) { - if _, err := NEGL(reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32", func(t *testing.T) { - if _, err := NEGL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestNEGQValidForms(t *testing.T) { - t.Run("form=r64", func(t *testing.T) { - if _, err := NEGQ(reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64", func(t *testing.T) { - if _, err := NEGQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestNEGWValidForms(t *testing.T) { - t.Run("form=r16", func(t *testing.T) { - if _, err := NEGW(reg.CX); err != nil { - t.Fatal(err) - } - if _, err := NEGW(reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16", func(t *testing.T) { - if _, err := NEGW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestNOPValidForms(t *testing.T) { - t.Run("form=", func(t *testing.T) { - if _, err := NOP(); err != nil { - t.Fatal(err) - } - }) -} - -func TestNOTBValidForms(t *testing.T) { - t.Run("form=r8", func(t *testing.T) { - if _, err := NOTB(reg.CH); err != nil { - t.Fatal(err) - } - if _, err := NOTB(reg.BL); err != nil { - t.Fatal(err) - } - if _, err := NOTB(reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8", func(t *testing.T) { - if _, err := NOTB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestNOTLValidForms(t *testing.T) { - t.Run("form=r32", func(t *testing.T) { - if _, err := NOTL(reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32", func(t *testing.T) { - if _, err := NOTL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestNOTQValidForms(t *testing.T) { - t.Run("form=r64", func(t *testing.T) { - if _, err := NOTQ(reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64", func(t *testing.T) { - if _, err := NOTQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestNOTWValidForms(t *testing.T) { - t.Run("form=r16", func(t *testing.T) { - if _, err := NOTW(reg.CX); err != nil { - t.Fatal(err) - } - if _, err := NOTW(reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16", func(t *testing.T) { - if _, err := NOTW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestORBValidForms(t *testing.T) { - t.Run("form=imm8_al", func(t *testing.T) { - if _, err := ORB(operand.Imm(math.MaxInt8), reg.AL); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r8", func(t *testing.T) { - if _, err := ORB(operand.Imm(math.MaxInt8), reg.CH); err != nil { - t.Fatal(err) - } - if _, err := ORB(operand.Imm(math.MaxInt8), reg.BL); err != nil { - t.Fatal(err) - } - if _, err := ORB(operand.Imm(math.MaxInt8), reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r8_r8", func(t *testing.T) { - if _, err := ORB(reg.CH, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := ORB(reg.CH, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := ORB(reg.CH, reg.R13B); err != nil { - t.Fatal(err) - } - if _, err := ORB(reg.BL, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := ORB(reg.BL, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := ORB(reg.BL, reg.R13B); err != nil { - t.Fatal(err) - } - if _, err := ORB(reg.R13B, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := ORB(reg.R13B, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := ORB(reg.R13B, reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8_r8", func(t *testing.T) { - if _, err := ORB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := ORB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := ORB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m8", func(t *testing.T) { - if _, err := ORB(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r8_m8", func(t *testing.T) { - if _, err := ORB(reg.CH, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - if _, err := ORB(reg.BL, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - if _, err := ORB(reg.R13B, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestORLValidForms(t *testing.T) { - t.Run("form=imm32_eax", func(t *testing.T) { - if _, err := ORL(operand.Imm(math.MaxInt32), reg.EAX); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r32", func(t *testing.T) { - if _, err := ORL(operand.Imm(math.MaxInt8), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_r32", func(t *testing.T) { - if _, err := ORL(operand.Imm(math.MaxInt32), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := ORL(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := ORL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m32", func(t *testing.T) { - if _, err := ORL(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_m32", func(t *testing.T) { - if _, err := ORL(operand.Imm(math.MaxInt32), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_m32", func(t *testing.T) { - if _, err := ORL(reg.R10L, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestORPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := ORPD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := ORPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestORPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := ORPS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := ORPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestORQValidForms(t *testing.T) { - t.Run("form=imm32_rax", func(t *testing.T) { - if _, err := ORQ(operand.Imm(math.MaxInt32), reg.RAX); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r64", func(t *testing.T) { - if _, err := ORQ(operand.Imm(math.MaxInt8), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_r64", func(t *testing.T) { - if _, err := ORQ(operand.Imm(math.MaxInt32), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := ORQ(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := ORQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m64", func(t *testing.T) { - if _, err := ORQ(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_m64", func(t *testing.T) { - if _, err := ORQ(operand.Imm(math.MaxInt32), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_m64", func(t *testing.T) { - if _, err := ORQ(reg.R11, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestORWValidForms(t *testing.T) { - t.Run("form=imm16_ax", func(t *testing.T) { - if _, err := ORW(operand.Imm(math.MaxInt16), reg.AX); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r16", func(t *testing.T) { - if _, err := ORW(operand.Imm(math.MaxInt8), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := ORW(operand.Imm(math.MaxInt8), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm16_r16", func(t *testing.T) { - if _, err := ORW(operand.Imm(math.MaxInt16), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := ORW(operand.Imm(math.MaxInt16), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := ORW(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := ORW(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := ORW(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := ORW(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := ORW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := ORW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m16", func(t *testing.T) { - if _, err := ORW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm16_m16", func(t *testing.T) { - if _, err := ORW(operand.Imm(math.MaxInt16), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_m16", func(t *testing.T) { - if _, err := ORW(reg.CX, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - if _, err := ORW(reg.R9W, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestPABSBValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PABSB(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PABSB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPABSDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PABSD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PABSD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPABSWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PABSW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PABSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPACKSSLWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PACKSSLW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PACKSSLW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPACKSSWBValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PACKSSWB(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PACKSSWB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPACKUSDWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PACKUSDW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PACKUSDW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPACKUSWBValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PACKUSWB(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PACKUSWB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPADDBValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PADDB(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PADDB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPADDDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PADDD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PADDD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPADDLValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PADDL(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PADDL(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPADDQValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PADDQ(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PADDQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPADDSBValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PADDSB(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PADDSB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPADDSWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PADDSW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PADDSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPADDUSBValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PADDUSB(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PADDUSB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPADDUSWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PADDUSW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PADDUSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPADDWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PADDW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PADDW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPALIGNRValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := PALIGNR(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := PALIGNR(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPANDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PAND(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PAND(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPANDNValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PANDN(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PANDN(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPAUSEValidForms(t *testing.T) { - t.Run("form=", func(t *testing.T) { - if _, err := PAUSE(); err != nil { - t.Fatal(err) - } - }) -} - -func TestPAVGBValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PAVGB(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PAVGB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPAVGWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PAVGW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PAVGW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPBLENDVBValidForms(t *testing.T) { - t.Run("form=xmm0_xmm_xmm", func(t *testing.T) { - if _, err := PBLENDVB(reg.X0, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm0_m128_xmm", func(t *testing.T) { - if _, err := PBLENDVB(reg.X0, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPBLENDWValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := PBLENDW(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := PBLENDW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPCLMULQDQValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := PCLMULQDQ(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := PCLMULQDQ(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPCMPEQBValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PCMPEQB(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PCMPEQB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPCMPEQLValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PCMPEQL(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PCMPEQL(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPCMPEQQValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PCMPEQQ(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PCMPEQQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPCMPEQWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PCMPEQW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PCMPEQW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPCMPESTRIValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := PCMPESTRI(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := PCMPESTRI(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPCMPESTRMValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := PCMPESTRM(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := PCMPESTRM(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPCMPGTBValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PCMPGTB(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PCMPGTB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPCMPGTLValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PCMPGTL(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PCMPGTL(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPCMPGTQValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PCMPGTQ(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PCMPGTQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPCMPGTWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PCMPGTW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PCMPGTW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPCMPISTRIValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := PCMPISTRI(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := PCMPISTRI(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPCMPISTRMValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := PCMPISTRM(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := PCMPISTRM(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPDEPLValidForms(t *testing.T) { - t.Run("form=r32_r32_r32", func(t *testing.T) { - if _, err := PDEPL(reg.R10L, reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32_r32", func(t *testing.T) { - if _, err := PDEPL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestPDEPQValidForms(t *testing.T) { - t.Run("form=r64_r64_r64", func(t *testing.T) { - if _, err := PDEPQ(reg.R11, reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64_r64", func(t *testing.T) { - if _, err := PDEPQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestPEXTLValidForms(t *testing.T) { - t.Run("form=r32_r32_r32", func(t *testing.T) { - if _, err := PEXTL(reg.R10L, reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32_r32", func(t *testing.T) { - if _, err := PEXTL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestPEXTQValidForms(t *testing.T) { - t.Run("form=r64_r64_r64", func(t *testing.T) { - if _, err := PEXTQ(reg.R11, reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64_r64", func(t *testing.T) { - if _, err := PEXTQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestPEXTRBValidForms(t *testing.T) { - t.Run("form=imm8_xmm_r32", func(t *testing.T) { - if _, err := PEXTRB(operand.Imm(math.MaxInt8), reg.X7, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_xmm_m8", func(t *testing.T) { - if _, err := PEXTRB(operand.Imm(math.MaxInt8), reg.X7, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestPEXTRDValidForms(t *testing.T) { - t.Run("form=imm8_xmm_r32", func(t *testing.T) { - if _, err := PEXTRD(operand.Imm(math.MaxInt8), reg.X7, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_xmm_m32", func(t *testing.T) { - if _, err := PEXTRD(operand.Imm(math.MaxInt8), reg.X7, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestPEXTRQValidForms(t *testing.T) { - t.Run("form=imm8_xmm_r64", func(t *testing.T) { - if _, err := PEXTRQ(operand.Imm(math.MaxInt8), reg.X7, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_xmm_m64", func(t *testing.T) { - if _, err := PEXTRQ(operand.Imm(math.MaxInt8), reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestPEXTRWValidForms(t *testing.T) { - t.Run("form=imm8_xmm_r32", func(t *testing.T) { - if _, err := PEXTRW(operand.Imm(math.MaxInt8), reg.X7, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_xmm_m16", func(t *testing.T) { - if _, err := PEXTRW(operand.Imm(math.MaxInt8), reg.X7, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestPHADDDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PHADDD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PHADDD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPHADDSWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PHADDSW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PHADDSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPHADDWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PHADDW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PHADDW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPHMINPOSUWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PHMINPOSUW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PHMINPOSUW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPHSUBDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PHSUBD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PHSUBD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPHSUBSWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PHSUBSW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PHSUBSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPHSUBWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PHSUBW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PHSUBW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPINSRBValidForms(t *testing.T) { - t.Run("form=imm8_r32_xmm", func(t *testing.T) { - if _, err := PINSRB(operand.Imm(math.MaxInt8), reg.R10L, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m8_xmm", func(t *testing.T) { - if _, err := PINSRB(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPINSRDValidForms(t *testing.T) { - t.Run("form=imm8_r32_xmm", func(t *testing.T) { - if _, err := PINSRD(operand.Imm(math.MaxInt8), reg.R10L, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m32_xmm", func(t *testing.T) { - if _, err := PINSRD(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPINSRQValidForms(t *testing.T) { - t.Run("form=imm8_r64_xmm", func(t *testing.T) { - if _, err := PINSRQ(operand.Imm(math.MaxInt8), reg.R11, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m64_xmm", func(t *testing.T) { - if _, err := PINSRQ(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPINSRWValidForms(t *testing.T) { - t.Run("form=imm8_r32_xmm", func(t *testing.T) { - if _, err := PINSRW(operand.Imm(math.MaxInt8), reg.R10L, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m16_xmm", func(t *testing.T) { - if _, err := PINSRW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMADDUBSWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMADDUBSW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PMADDUBSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMADDWLValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMADDWL(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PMADDWL(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMAXSBValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMAXSB(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PMAXSB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMAXSDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMAXSD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PMAXSD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMAXSWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMAXSW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PMAXSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMAXUBValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMAXUB(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PMAXUB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMAXUDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMAXUD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PMAXUD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMAXUWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMAXUW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PMAXUW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMINSBValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMINSB(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PMINSB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMINSDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMINSD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PMINSD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMINSWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMINSW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PMINSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMINUBValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMINUB(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PMINUB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMINUDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMINUD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PMINUD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMINUWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMINUW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PMINUW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMOVMSKBValidForms(t *testing.T) { - t.Run("form=xmm_r32", func(t *testing.T) { - if _, err := PMOVMSKB(reg.X7, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMOVSXBDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMOVSXBD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := PMOVSXBD(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMOVSXBQValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMOVSXBQ(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_xmm", func(t *testing.T) { - if _, err := PMOVSXBQ(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMOVSXBWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMOVSXBW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := PMOVSXBW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMOVSXDQValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMOVSXDQ(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := PMOVSXDQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMOVSXWDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMOVSXWD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := PMOVSXWD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMOVSXWQValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMOVSXWQ(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := PMOVSXWQ(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMOVZXBDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMOVZXBD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := PMOVZXBD(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMOVZXBQValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMOVZXBQ(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_xmm", func(t *testing.T) { - if _, err := PMOVZXBQ(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMOVZXBWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMOVZXBW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := PMOVZXBW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMOVZXDQValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMOVZXDQ(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := PMOVZXDQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMOVZXWDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMOVZXWD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := PMOVZXWD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMOVZXWQValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMOVZXWQ(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := PMOVZXWQ(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMULDQValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMULDQ(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PMULDQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMULHRSWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMULHRSW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PMULHRSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMULHUWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMULHUW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PMULHUW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMULHWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMULHW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PMULHW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMULLDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMULLD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PMULLD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMULLWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMULLW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PMULLW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPMULULQValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PMULULQ(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PMULULQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPOPCNTLValidForms(t *testing.T) { - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := POPCNTL(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := POPCNTL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestPOPCNTQValidForms(t *testing.T) { - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := POPCNTQ(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := POPCNTQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestPOPCNTWValidForms(t *testing.T) { - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := POPCNTW(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := POPCNTW(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := POPCNTW(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := POPCNTW(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := POPCNTW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := POPCNTW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) -} - -func TestPOPQValidForms(t *testing.T) { - t.Run("form=r64", func(t *testing.T) { - if _, err := POPQ(reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64", func(t *testing.T) { - if _, err := POPQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestPOPWValidForms(t *testing.T) { - t.Run("form=r16", func(t *testing.T) { - if _, err := POPW(reg.CX); err != nil { - t.Fatal(err) - } - if _, err := POPW(reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16", func(t *testing.T) { - if _, err := POPW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestPORValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := POR(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := POR(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPREFETCHNTAValidForms(t *testing.T) { - t.Run("form=m8", func(t *testing.T) { - if _, err := PREFETCHNTA(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestPREFETCHT0ValidForms(t *testing.T) { - t.Run("form=m8", func(t *testing.T) { - if _, err := PREFETCHT0(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestPREFETCHT1ValidForms(t *testing.T) { - t.Run("form=m8", func(t *testing.T) { - if _, err := PREFETCHT1(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestPREFETCHT2ValidForms(t *testing.T) { - t.Run("form=m8", func(t *testing.T) { - if _, err := PREFETCHT2(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestPSADBWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PSADBW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PSADBW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPSHUFBValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PSHUFB(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PSHUFB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPSHUFDValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := PSHUFD(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := PSHUFD(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPSHUFHWValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := PSHUFHW(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := PSHUFHW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPSHUFLValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := PSHUFL(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := PSHUFL(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPSHUFLWValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := PSHUFLW(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := PSHUFLW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPSIGNBValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PSIGNB(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PSIGNB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPSIGNDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PSIGND(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PSIGND(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPSIGNWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PSIGNW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PSIGNW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPSLLDQValidForms(t *testing.T) { - t.Run("form=imm8_xmm", func(t *testing.T) { - if _, err := PSLLDQ(operand.Imm(math.MaxInt8), reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPSLLLValidForms(t *testing.T) { - t.Run("form=imm8_xmm", func(t *testing.T) { - if _, err := PSLLL(operand.Imm(math.MaxInt8), reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PSLLL(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PSLLL(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPSLLOValidForms(t *testing.T) { - t.Run("form=imm8_xmm", func(t *testing.T) { - if _, err := PSLLO(operand.Imm(math.MaxInt8), reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPSLLQValidForms(t *testing.T) { - t.Run("form=imm8_xmm", func(t *testing.T) { - if _, err := PSLLQ(operand.Imm(math.MaxInt8), reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PSLLQ(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PSLLQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPSLLWValidForms(t *testing.T) { - t.Run("form=imm8_xmm", func(t *testing.T) { - if _, err := PSLLW(operand.Imm(math.MaxInt8), reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PSLLW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PSLLW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPSRALValidForms(t *testing.T) { - t.Run("form=imm8_xmm", func(t *testing.T) { - if _, err := PSRAL(operand.Imm(math.MaxInt8), reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PSRAL(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PSRAL(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPSRAWValidForms(t *testing.T) { - t.Run("form=imm8_xmm", func(t *testing.T) { - if _, err := PSRAW(operand.Imm(math.MaxInt8), reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PSRAW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PSRAW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPSRLDQValidForms(t *testing.T) { - t.Run("form=imm8_xmm", func(t *testing.T) { - if _, err := PSRLDQ(operand.Imm(math.MaxInt8), reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPSRLLValidForms(t *testing.T) { - t.Run("form=imm8_xmm", func(t *testing.T) { - if _, err := PSRLL(operand.Imm(math.MaxInt8), reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PSRLL(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PSRLL(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPSRLOValidForms(t *testing.T) { - t.Run("form=imm8_xmm", func(t *testing.T) { - if _, err := PSRLO(operand.Imm(math.MaxInt8), reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPSRLQValidForms(t *testing.T) { - t.Run("form=imm8_xmm", func(t *testing.T) { - if _, err := PSRLQ(operand.Imm(math.MaxInt8), reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PSRLQ(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PSRLQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPSRLWValidForms(t *testing.T) { - t.Run("form=imm8_xmm", func(t *testing.T) { - if _, err := PSRLW(operand.Imm(math.MaxInt8), reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PSRLW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PSRLW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPSUBBValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PSUBB(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PSUBB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPSUBLValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PSUBL(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PSUBL(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPSUBQValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PSUBQ(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PSUBQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPSUBSBValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PSUBSB(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PSUBSB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPSUBSWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PSUBSW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PSUBSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPSUBUSBValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PSUBUSB(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PSUBUSB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPSUBUSWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PSUBUSW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PSUBUSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPSUBWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PSUBW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PSUBW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPTESTValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PTEST(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PTEST(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPUNPCKHBWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PUNPCKHBW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PUNPCKHBW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPUNPCKHLQValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PUNPCKHLQ(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PUNPCKHLQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPUNPCKHQDQValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PUNPCKHQDQ(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PUNPCKHQDQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPUNPCKHWLValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PUNPCKHWL(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PUNPCKHWL(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPUNPCKLBWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PUNPCKLBW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PUNPCKLBW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPUNPCKLLQValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PUNPCKLLQ(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PUNPCKLLQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPUNPCKLQDQValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PUNPCKLQDQ(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PUNPCKLQDQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPUNPCKLWLValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PUNPCKLWL(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PUNPCKLWL(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestPUSHQValidForms(t *testing.T) { - t.Run("form=imm8", func(t *testing.T) { - if _, err := PUSHQ(operand.Imm(math.MaxInt8)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32", func(t *testing.T) { - if _, err := PUSHQ(operand.Imm(math.MaxInt32)); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64", func(t *testing.T) { - if _, err := PUSHQ(reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64", func(t *testing.T) { - if _, err := PUSHQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestPUSHWValidForms(t *testing.T) { - t.Run("form=r16", func(t *testing.T) { - if _, err := PUSHW(reg.CX); err != nil { - t.Fatal(err) - } - if _, err := PUSHW(reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16", func(t *testing.T) { - if _, err := PUSHW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestPXORValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := PXOR(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := PXOR(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestRCLBValidForms(t *testing.T) { - t.Run("form=1_r8", func(t *testing.T) { - if _, err := RCLB(operand.Imm(1), reg.CH); err != nil { - t.Fatal(err) - } - if _, err := RCLB(operand.Imm(1), reg.BL); err != nil { - t.Fatal(err) - } - if _, err := RCLB(operand.Imm(1), reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r8", func(t *testing.T) { - if _, err := RCLB(operand.Imm(math.MaxInt8), reg.CH); err != nil { - t.Fatal(err) - } - if _, err := RCLB(operand.Imm(math.MaxInt8), reg.BL); err != nil { - t.Fatal(err) - } - if _, err := RCLB(operand.Imm(math.MaxInt8), reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r8", func(t *testing.T) { - if _, err := RCLB(reg.CL, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := RCLB(reg.CL, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := RCLB(reg.CL, reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m8", func(t *testing.T) { - if _, err := RCLB(operand.Imm(1), operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m8", func(t *testing.T) { - if _, err := RCLB(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m8", func(t *testing.T) { - if _, err := RCLB(reg.CL, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestRCLLValidForms(t *testing.T) { - t.Run("form=1_r32", func(t *testing.T) { - if _, err := RCLL(operand.Imm(1), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r32", func(t *testing.T) { - if _, err := RCLL(operand.Imm(math.MaxInt8), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r32", func(t *testing.T) { - if _, err := RCLL(reg.CL, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m32", func(t *testing.T) { - if _, err := RCLL(operand.Imm(1), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m32", func(t *testing.T) { - if _, err := RCLL(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m32", func(t *testing.T) { - if _, err := RCLL(reg.CL, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestRCLQValidForms(t *testing.T) { - t.Run("form=1_r64", func(t *testing.T) { - if _, err := RCLQ(operand.Imm(1), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r64", func(t *testing.T) { - if _, err := RCLQ(operand.Imm(math.MaxInt8), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r64", func(t *testing.T) { - if _, err := RCLQ(reg.CL, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m64", func(t *testing.T) { - if _, err := RCLQ(operand.Imm(1), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m64", func(t *testing.T) { - if _, err := RCLQ(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m64", func(t *testing.T) { - if _, err := RCLQ(reg.CL, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestRCLWValidForms(t *testing.T) { - t.Run("form=1_r16", func(t *testing.T) { - if _, err := RCLW(operand.Imm(1), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := RCLW(operand.Imm(1), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r16", func(t *testing.T) { - if _, err := RCLW(operand.Imm(math.MaxInt8), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := RCLW(operand.Imm(math.MaxInt8), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r16", func(t *testing.T) { - if _, err := RCLW(reg.CL, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := RCLW(reg.CL, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m16", func(t *testing.T) { - if _, err := RCLW(operand.Imm(1), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m16", func(t *testing.T) { - if _, err := RCLW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m16", func(t *testing.T) { - if _, err := RCLW(reg.CL, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestRCPPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := RCPPS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := RCPPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestRCPSSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := RCPSS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := RCPSS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestRCRBValidForms(t *testing.T) { - t.Run("form=1_r8", func(t *testing.T) { - if _, err := RCRB(operand.Imm(1), reg.CH); err != nil { - t.Fatal(err) - } - if _, err := RCRB(operand.Imm(1), reg.BL); err != nil { - t.Fatal(err) - } - if _, err := RCRB(operand.Imm(1), reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r8", func(t *testing.T) { - if _, err := RCRB(operand.Imm(math.MaxInt8), reg.CH); err != nil { - t.Fatal(err) - } - if _, err := RCRB(operand.Imm(math.MaxInt8), reg.BL); err != nil { - t.Fatal(err) - } - if _, err := RCRB(operand.Imm(math.MaxInt8), reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r8", func(t *testing.T) { - if _, err := RCRB(reg.CL, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := RCRB(reg.CL, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := RCRB(reg.CL, reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m8", func(t *testing.T) { - if _, err := RCRB(operand.Imm(1), operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m8", func(t *testing.T) { - if _, err := RCRB(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m8", func(t *testing.T) { - if _, err := RCRB(reg.CL, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestRCRLValidForms(t *testing.T) { - t.Run("form=1_r32", func(t *testing.T) { - if _, err := RCRL(operand.Imm(1), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r32", func(t *testing.T) { - if _, err := RCRL(operand.Imm(math.MaxInt8), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r32", func(t *testing.T) { - if _, err := RCRL(reg.CL, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m32", func(t *testing.T) { - if _, err := RCRL(operand.Imm(1), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m32", func(t *testing.T) { - if _, err := RCRL(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m32", func(t *testing.T) { - if _, err := RCRL(reg.CL, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestRCRQValidForms(t *testing.T) { - t.Run("form=1_r64", func(t *testing.T) { - if _, err := RCRQ(operand.Imm(1), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r64", func(t *testing.T) { - if _, err := RCRQ(operand.Imm(math.MaxInt8), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r64", func(t *testing.T) { - if _, err := RCRQ(reg.CL, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m64", func(t *testing.T) { - if _, err := RCRQ(operand.Imm(1), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m64", func(t *testing.T) { - if _, err := RCRQ(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m64", func(t *testing.T) { - if _, err := RCRQ(reg.CL, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestRCRWValidForms(t *testing.T) { - t.Run("form=1_r16", func(t *testing.T) { - if _, err := RCRW(operand.Imm(1), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := RCRW(operand.Imm(1), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r16", func(t *testing.T) { - if _, err := RCRW(operand.Imm(math.MaxInt8), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := RCRW(operand.Imm(math.MaxInt8), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r16", func(t *testing.T) { - if _, err := RCRW(reg.CL, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := RCRW(reg.CL, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m16", func(t *testing.T) { - if _, err := RCRW(operand.Imm(1), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m16", func(t *testing.T) { - if _, err := RCRW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m16", func(t *testing.T) { - if _, err := RCRW(reg.CL, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestRDRANDLValidForms(t *testing.T) { - t.Run("form=r32", func(t *testing.T) { - if _, err := RDRANDL(reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestRDRANDQValidForms(t *testing.T) { - t.Run("form=r64", func(t *testing.T) { - if _, err := RDRANDQ(reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestRDRANDWValidForms(t *testing.T) { - t.Run("form=r16", func(t *testing.T) { - if _, err := RDRANDW(reg.CX); err != nil { - t.Fatal(err) - } - if _, err := RDRANDW(reg.R9W); err != nil { - t.Fatal(err) - } - }) -} - -func TestRDSEEDLValidForms(t *testing.T) { - t.Run("form=r32", func(t *testing.T) { - if _, err := RDSEEDL(reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestRDSEEDQValidForms(t *testing.T) { - t.Run("form=r64", func(t *testing.T) { - if _, err := RDSEEDQ(reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestRDSEEDWValidForms(t *testing.T) { - t.Run("form=r16", func(t *testing.T) { - if _, err := RDSEEDW(reg.CX); err != nil { - t.Fatal(err) - } - if _, err := RDSEEDW(reg.R9W); err != nil { - t.Fatal(err) - } - }) -} - -func TestRDTSCValidForms(t *testing.T) { - t.Run("form=", func(t *testing.T) { - if _, err := RDTSC(); err != nil { - t.Fatal(err) - } - }) -} - -func TestRDTSCPValidForms(t *testing.T) { - t.Run("form=", func(t *testing.T) { - if _, err := RDTSCP(); err != nil { - t.Fatal(err) - } - }) -} - -func TestRETValidForms(t *testing.T) { - t.Run("form=", func(t *testing.T) { - if _, err := RET(); err != nil { - t.Fatal(err) - } - }) -} - -func TestRETFLValidForms(t *testing.T) { - t.Run("form=imm16", func(t *testing.T) { - if _, err := RETFL(operand.Imm(math.MaxInt16)); err != nil { - t.Fatal(err) - } - }) -} - -func TestRETFQValidForms(t *testing.T) { - t.Run("form=imm16", func(t *testing.T) { - if _, err := RETFQ(operand.Imm(math.MaxInt16)); err != nil { - t.Fatal(err) - } - }) -} - -func TestRETFWValidForms(t *testing.T) { - t.Run("form=imm16", func(t *testing.T) { - if _, err := RETFW(operand.Imm(math.MaxInt16)); err != nil { - t.Fatal(err) - } - }) -} - -func TestROLBValidForms(t *testing.T) { - t.Run("form=1_r8", func(t *testing.T) { - if _, err := ROLB(operand.Imm(1), reg.CH); err != nil { - t.Fatal(err) - } - if _, err := ROLB(operand.Imm(1), reg.BL); err != nil { - t.Fatal(err) - } - if _, err := ROLB(operand.Imm(1), reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r8", func(t *testing.T) { - if _, err := ROLB(operand.Imm(math.MaxInt8), reg.CH); err != nil { - t.Fatal(err) - } - if _, err := ROLB(operand.Imm(math.MaxInt8), reg.BL); err != nil { - t.Fatal(err) - } - if _, err := ROLB(operand.Imm(math.MaxInt8), reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r8", func(t *testing.T) { - if _, err := ROLB(reg.CL, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := ROLB(reg.CL, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := ROLB(reg.CL, reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m8", func(t *testing.T) { - if _, err := ROLB(operand.Imm(1), operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m8", func(t *testing.T) { - if _, err := ROLB(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m8", func(t *testing.T) { - if _, err := ROLB(reg.CL, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestROLLValidForms(t *testing.T) { - t.Run("form=1_r32", func(t *testing.T) { - if _, err := ROLL(operand.Imm(1), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r32", func(t *testing.T) { - if _, err := ROLL(operand.Imm(math.MaxInt8), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r32", func(t *testing.T) { - if _, err := ROLL(reg.CL, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m32", func(t *testing.T) { - if _, err := ROLL(operand.Imm(1), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m32", func(t *testing.T) { - if _, err := ROLL(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m32", func(t *testing.T) { - if _, err := ROLL(reg.CL, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestROLQValidForms(t *testing.T) { - t.Run("form=1_r64", func(t *testing.T) { - if _, err := ROLQ(operand.Imm(1), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r64", func(t *testing.T) { - if _, err := ROLQ(operand.Imm(math.MaxInt8), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r64", func(t *testing.T) { - if _, err := ROLQ(reg.CL, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m64", func(t *testing.T) { - if _, err := ROLQ(operand.Imm(1), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m64", func(t *testing.T) { - if _, err := ROLQ(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m64", func(t *testing.T) { - if _, err := ROLQ(reg.CL, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestROLWValidForms(t *testing.T) { - t.Run("form=1_r16", func(t *testing.T) { - if _, err := ROLW(operand.Imm(1), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := ROLW(operand.Imm(1), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r16", func(t *testing.T) { - if _, err := ROLW(operand.Imm(math.MaxInt8), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := ROLW(operand.Imm(math.MaxInt8), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r16", func(t *testing.T) { - if _, err := ROLW(reg.CL, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := ROLW(reg.CL, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m16", func(t *testing.T) { - if _, err := ROLW(operand.Imm(1), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m16", func(t *testing.T) { - if _, err := ROLW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m16", func(t *testing.T) { - if _, err := ROLW(reg.CL, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestRORBValidForms(t *testing.T) { - t.Run("form=1_r8", func(t *testing.T) { - if _, err := RORB(operand.Imm(1), reg.CH); err != nil { - t.Fatal(err) - } - if _, err := RORB(operand.Imm(1), reg.BL); err != nil { - t.Fatal(err) - } - if _, err := RORB(operand.Imm(1), reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r8", func(t *testing.T) { - if _, err := RORB(operand.Imm(math.MaxInt8), reg.CH); err != nil { - t.Fatal(err) - } - if _, err := RORB(operand.Imm(math.MaxInt8), reg.BL); err != nil { - t.Fatal(err) - } - if _, err := RORB(operand.Imm(math.MaxInt8), reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r8", func(t *testing.T) { - if _, err := RORB(reg.CL, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := RORB(reg.CL, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := RORB(reg.CL, reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m8", func(t *testing.T) { - if _, err := RORB(operand.Imm(1), operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m8", func(t *testing.T) { - if _, err := RORB(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m8", func(t *testing.T) { - if _, err := RORB(reg.CL, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestRORLValidForms(t *testing.T) { - t.Run("form=1_r32", func(t *testing.T) { - if _, err := RORL(operand.Imm(1), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r32", func(t *testing.T) { - if _, err := RORL(operand.Imm(math.MaxInt8), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r32", func(t *testing.T) { - if _, err := RORL(reg.CL, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m32", func(t *testing.T) { - if _, err := RORL(operand.Imm(1), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m32", func(t *testing.T) { - if _, err := RORL(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m32", func(t *testing.T) { - if _, err := RORL(reg.CL, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestRORQValidForms(t *testing.T) { - t.Run("form=1_r64", func(t *testing.T) { - if _, err := RORQ(operand.Imm(1), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r64", func(t *testing.T) { - if _, err := RORQ(operand.Imm(math.MaxInt8), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r64", func(t *testing.T) { - if _, err := RORQ(reg.CL, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m64", func(t *testing.T) { - if _, err := RORQ(operand.Imm(1), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m64", func(t *testing.T) { - if _, err := RORQ(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m64", func(t *testing.T) { - if _, err := RORQ(reg.CL, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestRORWValidForms(t *testing.T) { - t.Run("form=1_r16", func(t *testing.T) { - if _, err := RORW(operand.Imm(1), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := RORW(operand.Imm(1), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r16", func(t *testing.T) { - if _, err := RORW(operand.Imm(math.MaxInt8), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := RORW(operand.Imm(math.MaxInt8), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r16", func(t *testing.T) { - if _, err := RORW(reg.CL, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := RORW(reg.CL, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m16", func(t *testing.T) { - if _, err := RORW(operand.Imm(1), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m16", func(t *testing.T) { - if _, err := RORW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m16", func(t *testing.T) { - if _, err := RORW(reg.CL, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestRORXLValidForms(t *testing.T) { - t.Run("form=imm8_r32_r32", func(t *testing.T) { - if _, err := RORXL(operand.Imm(math.MaxInt8), reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m32_r32", func(t *testing.T) { - if _, err := RORXL(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestRORXQValidForms(t *testing.T) { - t.Run("form=imm8_r64_r64", func(t *testing.T) { - if _, err := RORXQ(operand.Imm(math.MaxInt8), reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m64_r64", func(t *testing.T) { - if _, err := RORXQ(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestROUNDPDValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := ROUNDPD(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := ROUNDPD(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestROUNDPSValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := ROUNDPS(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := ROUNDPS(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestROUNDSDValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := ROUNDSD(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m64_xmm", func(t *testing.T) { - if _, err := ROUNDSD(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestROUNDSSValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := ROUNDSS(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m32_xmm", func(t *testing.T) { - if _, err := ROUNDSS(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestRSQRTPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := RSQRTPS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := RSQRTPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestRSQRTSSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := RSQRTSS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := RSQRTSS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestSALBValidForms(t *testing.T) { - t.Run("form=1_r8", func(t *testing.T) { - if _, err := SALB(operand.Imm(1), reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SALB(operand.Imm(1), reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SALB(operand.Imm(1), reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r8", func(t *testing.T) { - if _, err := SALB(operand.Imm(math.MaxInt8), reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SALB(operand.Imm(math.MaxInt8), reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SALB(operand.Imm(math.MaxInt8), reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r8", func(t *testing.T) { - if _, err := SALB(reg.CL, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SALB(reg.CL, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SALB(reg.CL, reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m8", func(t *testing.T) { - if _, err := SALB(operand.Imm(1), operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m8", func(t *testing.T) { - if _, err := SALB(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m8", func(t *testing.T) { - if _, err := SALB(reg.CL, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSALLValidForms(t *testing.T) { - t.Run("form=1_r32", func(t *testing.T) { - if _, err := SALL(operand.Imm(1), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r32", func(t *testing.T) { - if _, err := SALL(operand.Imm(math.MaxInt8), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r32", func(t *testing.T) { - if _, err := SALL(reg.CL, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m32", func(t *testing.T) { - if _, err := SALL(operand.Imm(1), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m32", func(t *testing.T) { - if _, err := SALL(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m32", func(t *testing.T) { - if _, err := SALL(reg.CL, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSALQValidForms(t *testing.T) { - t.Run("form=1_r64", func(t *testing.T) { - if _, err := SALQ(operand.Imm(1), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r64", func(t *testing.T) { - if _, err := SALQ(operand.Imm(math.MaxInt8), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r64", func(t *testing.T) { - if _, err := SALQ(reg.CL, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m64", func(t *testing.T) { - if _, err := SALQ(operand.Imm(1), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m64", func(t *testing.T) { - if _, err := SALQ(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m64", func(t *testing.T) { - if _, err := SALQ(reg.CL, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSALWValidForms(t *testing.T) { - t.Run("form=1_r16", func(t *testing.T) { - if _, err := SALW(operand.Imm(1), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := SALW(operand.Imm(1), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r16", func(t *testing.T) { - if _, err := SALW(operand.Imm(math.MaxInt8), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := SALW(operand.Imm(math.MaxInt8), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r16", func(t *testing.T) { - if _, err := SALW(reg.CL, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := SALW(reg.CL, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m16", func(t *testing.T) { - if _, err := SALW(operand.Imm(1), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m16", func(t *testing.T) { - if _, err := SALW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m16", func(t *testing.T) { - if _, err := SALW(reg.CL, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSARBValidForms(t *testing.T) { - t.Run("form=1_r8", func(t *testing.T) { - if _, err := SARB(operand.Imm(1), reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SARB(operand.Imm(1), reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SARB(operand.Imm(1), reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r8", func(t *testing.T) { - if _, err := SARB(operand.Imm(math.MaxInt8), reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SARB(operand.Imm(math.MaxInt8), reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SARB(operand.Imm(math.MaxInt8), reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r8", func(t *testing.T) { - if _, err := SARB(reg.CL, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SARB(reg.CL, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SARB(reg.CL, reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m8", func(t *testing.T) { - if _, err := SARB(operand.Imm(1), operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m8", func(t *testing.T) { - if _, err := SARB(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m8", func(t *testing.T) { - if _, err := SARB(reg.CL, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSARLValidForms(t *testing.T) { - t.Run("form=1_r32", func(t *testing.T) { - if _, err := SARL(operand.Imm(1), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r32", func(t *testing.T) { - if _, err := SARL(operand.Imm(math.MaxInt8), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r32", func(t *testing.T) { - if _, err := SARL(reg.CL, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m32", func(t *testing.T) { - if _, err := SARL(operand.Imm(1), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m32", func(t *testing.T) { - if _, err := SARL(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m32", func(t *testing.T) { - if _, err := SARL(reg.CL, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSARQValidForms(t *testing.T) { - t.Run("form=1_r64", func(t *testing.T) { - if _, err := SARQ(operand.Imm(1), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r64", func(t *testing.T) { - if _, err := SARQ(operand.Imm(math.MaxInt8), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r64", func(t *testing.T) { - if _, err := SARQ(reg.CL, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m64", func(t *testing.T) { - if _, err := SARQ(operand.Imm(1), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m64", func(t *testing.T) { - if _, err := SARQ(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m64", func(t *testing.T) { - if _, err := SARQ(reg.CL, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSARWValidForms(t *testing.T) { - t.Run("form=1_r16", func(t *testing.T) { - if _, err := SARW(operand.Imm(1), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := SARW(operand.Imm(1), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r16", func(t *testing.T) { - if _, err := SARW(operand.Imm(math.MaxInt8), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := SARW(operand.Imm(math.MaxInt8), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r16", func(t *testing.T) { - if _, err := SARW(reg.CL, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := SARW(reg.CL, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m16", func(t *testing.T) { - if _, err := SARW(operand.Imm(1), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m16", func(t *testing.T) { - if _, err := SARW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m16", func(t *testing.T) { - if _, err := SARW(reg.CL, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSARXLValidForms(t *testing.T) { - t.Run("form=r32_r32_r32", func(t *testing.T) { - if _, err := SARXL(reg.R10L, reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_m32_r32", func(t *testing.T) { - if _, err := SARXL(reg.R10L, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestSARXQValidForms(t *testing.T) { - t.Run("form=r64_r64_r64", func(t *testing.T) { - if _, err := SARXQ(reg.R11, reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_m64_r64", func(t *testing.T) { - if _, err := SARXQ(reg.R11, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestSBBBValidForms(t *testing.T) { - t.Run("form=imm8_al", func(t *testing.T) { - if _, err := SBBB(operand.Imm(math.MaxInt8), reg.AL); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r8", func(t *testing.T) { - if _, err := SBBB(operand.Imm(math.MaxInt8), reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SBBB(operand.Imm(math.MaxInt8), reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SBBB(operand.Imm(math.MaxInt8), reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r8_r8", func(t *testing.T) { - if _, err := SBBB(reg.CH, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SBBB(reg.CH, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SBBB(reg.CH, reg.R13B); err != nil { - t.Fatal(err) - } - if _, err := SBBB(reg.BL, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SBBB(reg.BL, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SBBB(reg.BL, reg.R13B); err != nil { - t.Fatal(err) - } - if _, err := SBBB(reg.R13B, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SBBB(reg.R13B, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SBBB(reg.R13B, reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8_r8", func(t *testing.T) { - if _, err := SBBB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SBBB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SBBB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m8", func(t *testing.T) { - if _, err := SBBB(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r8_m8", func(t *testing.T) { - if _, err := SBBB(reg.CH, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - if _, err := SBBB(reg.BL, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - if _, err := SBBB(reg.R13B, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSBBLValidForms(t *testing.T) { - t.Run("form=imm32_eax", func(t *testing.T) { - if _, err := SBBL(operand.Imm(math.MaxInt32), reg.EAX); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r32", func(t *testing.T) { - if _, err := SBBL(operand.Imm(math.MaxInt8), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_r32", func(t *testing.T) { - if _, err := SBBL(operand.Imm(math.MaxInt32), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := SBBL(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := SBBL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m32", func(t *testing.T) { - if _, err := SBBL(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_m32", func(t *testing.T) { - if _, err := SBBL(operand.Imm(math.MaxInt32), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_m32", func(t *testing.T) { - if _, err := SBBL(reg.R10L, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSBBQValidForms(t *testing.T) { - t.Run("form=imm32_rax", func(t *testing.T) { - if _, err := SBBQ(operand.Imm(math.MaxInt32), reg.RAX); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r64", func(t *testing.T) { - if _, err := SBBQ(operand.Imm(math.MaxInt8), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_r64", func(t *testing.T) { - if _, err := SBBQ(operand.Imm(math.MaxInt32), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := SBBQ(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := SBBQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m64", func(t *testing.T) { - if _, err := SBBQ(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_m64", func(t *testing.T) { - if _, err := SBBQ(operand.Imm(math.MaxInt32), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_m64", func(t *testing.T) { - if _, err := SBBQ(reg.R11, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSBBWValidForms(t *testing.T) { - t.Run("form=imm16_ax", func(t *testing.T) { - if _, err := SBBW(operand.Imm(math.MaxInt16), reg.AX); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r16", func(t *testing.T) { - if _, err := SBBW(operand.Imm(math.MaxInt8), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := SBBW(operand.Imm(math.MaxInt8), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm16_r16", func(t *testing.T) { - if _, err := SBBW(operand.Imm(math.MaxInt16), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := SBBW(operand.Imm(math.MaxInt16), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := SBBW(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := SBBW(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := SBBW(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := SBBW(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := SBBW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := SBBW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m16", func(t *testing.T) { - if _, err := SBBW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm16_m16", func(t *testing.T) { - if _, err := SBBW(operand.Imm(math.MaxInt16), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_m16", func(t *testing.T) { - if _, err := SBBW(reg.CX, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - if _, err := SBBW(reg.R9W, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSETCCValidForms(t *testing.T) { - t.Run("form=r8", func(t *testing.T) { - if _, err := SETCC(reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SETCC(reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SETCC(reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8", func(t *testing.T) { - if _, err := SETCC(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSETCSValidForms(t *testing.T) { - t.Run("form=r8", func(t *testing.T) { - if _, err := SETCS(reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SETCS(reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SETCS(reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8", func(t *testing.T) { - if _, err := SETCS(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSETEQValidForms(t *testing.T) { - t.Run("form=r8", func(t *testing.T) { - if _, err := SETEQ(reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SETEQ(reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SETEQ(reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8", func(t *testing.T) { - if _, err := SETEQ(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSETGEValidForms(t *testing.T) { - t.Run("form=r8", func(t *testing.T) { - if _, err := SETGE(reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SETGE(reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SETGE(reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8", func(t *testing.T) { - if _, err := SETGE(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSETGTValidForms(t *testing.T) { - t.Run("form=r8", func(t *testing.T) { - if _, err := SETGT(reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SETGT(reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SETGT(reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8", func(t *testing.T) { - if _, err := SETGT(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSETHIValidForms(t *testing.T) { - t.Run("form=r8", func(t *testing.T) { - if _, err := SETHI(reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SETHI(reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SETHI(reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8", func(t *testing.T) { - if _, err := SETHI(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSETLEValidForms(t *testing.T) { - t.Run("form=r8", func(t *testing.T) { - if _, err := SETLE(reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SETLE(reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SETLE(reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8", func(t *testing.T) { - if _, err := SETLE(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSETLSValidForms(t *testing.T) { - t.Run("form=r8", func(t *testing.T) { - if _, err := SETLS(reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SETLS(reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SETLS(reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8", func(t *testing.T) { - if _, err := SETLS(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSETLTValidForms(t *testing.T) { - t.Run("form=r8", func(t *testing.T) { - if _, err := SETLT(reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SETLT(reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SETLT(reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8", func(t *testing.T) { - if _, err := SETLT(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSETMIValidForms(t *testing.T) { - t.Run("form=r8", func(t *testing.T) { - if _, err := SETMI(reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SETMI(reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SETMI(reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8", func(t *testing.T) { - if _, err := SETMI(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSETNEValidForms(t *testing.T) { - t.Run("form=r8", func(t *testing.T) { - if _, err := SETNE(reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SETNE(reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SETNE(reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8", func(t *testing.T) { - if _, err := SETNE(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSETOCValidForms(t *testing.T) { - t.Run("form=r8", func(t *testing.T) { - if _, err := SETOC(reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SETOC(reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SETOC(reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8", func(t *testing.T) { - if _, err := SETOC(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSETOSValidForms(t *testing.T) { - t.Run("form=r8", func(t *testing.T) { - if _, err := SETOS(reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SETOS(reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SETOS(reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8", func(t *testing.T) { - if _, err := SETOS(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSETPCValidForms(t *testing.T) { - t.Run("form=r8", func(t *testing.T) { - if _, err := SETPC(reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SETPC(reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SETPC(reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8", func(t *testing.T) { - if _, err := SETPC(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSETPLValidForms(t *testing.T) { - t.Run("form=r8", func(t *testing.T) { - if _, err := SETPL(reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SETPL(reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SETPL(reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8", func(t *testing.T) { - if _, err := SETPL(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSETPSValidForms(t *testing.T) { - t.Run("form=r8", func(t *testing.T) { - if _, err := SETPS(reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SETPS(reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SETPS(reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8", func(t *testing.T) { - if _, err := SETPS(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSFENCEValidForms(t *testing.T) { - t.Run("form=", func(t *testing.T) { - if _, err := SFENCE(); err != nil { - t.Fatal(err) - } - }) -} - -func TestSHA1MSG1ValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := SHA1MSG1(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := SHA1MSG1(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestSHA1MSG2ValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := SHA1MSG2(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := SHA1MSG2(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestSHA1NEXTEValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := SHA1NEXTE(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := SHA1NEXTE(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestSHA1RNDS4ValidForms(t *testing.T) { - t.Run("form=imm2u_xmm_xmm", func(t *testing.T) { - if _, err := SHA1RNDS4(operand.Imm(1), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - if _, err := SHA1RNDS4(operand.Imm(3), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm2u_m128_xmm", func(t *testing.T) { - if _, err := SHA1RNDS4(operand.Imm(1), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - if _, err := SHA1RNDS4(operand.Imm(3), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestSHA256MSG1ValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := SHA256MSG1(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := SHA256MSG1(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestSHA256MSG2ValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := SHA256MSG2(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := SHA256MSG2(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestSHA256RNDS2ValidForms(t *testing.T) { - t.Run("form=xmm0_xmm_xmm", func(t *testing.T) { - if _, err := SHA256RNDS2(reg.X0, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm0_m128_xmm", func(t *testing.T) { - if _, err := SHA256RNDS2(reg.X0, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestSHLBValidForms(t *testing.T) { - t.Run("form=1_r8", func(t *testing.T) { - if _, err := SHLB(operand.Imm(1), reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SHLB(operand.Imm(1), reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SHLB(operand.Imm(1), reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r8", func(t *testing.T) { - if _, err := SHLB(operand.Imm(math.MaxInt8), reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SHLB(operand.Imm(math.MaxInt8), reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SHLB(operand.Imm(math.MaxInt8), reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r8", func(t *testing.T) { - if _, err := SHLB(reg.CL, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SHLB(reg.CL, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SHLB(reg.CL, reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m8", func(t *testing.T) { - if _, err := SHLB(operand.Imm(1), operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m8", func(t *testing.T) { - if _, err := SHLB(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m8", func(t *testing.T) { - if _, err := SHLB(reg.CL, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSHLLValidForms(t *testing.T) { - t.Run("form=1_r32", func(t *testing.T) { - if _, err := SHLL(operand.Imm(1), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r32", func(t *testing.T) { - if _, err := SHLL(operand.Imm(math.MaxInt8), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r32", func(t *testing.T) { - if _, err := SHLL(reg.CL, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m32", func(t *testing.T) { - if _, err := SHLL(operand.Imm(1), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m32", func(t *testing.T) { - if _, err := SHLL(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m32", func(t *testing.T) { - if _, err := SHLL(reg.CL, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r32_r32", func(t *testing.T) { - if _, err := SHLL(operand.Imm(math.MaxInt8), reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r32_r32", func(t *testing.T) { - if _, err := SHLL(reg.CL, reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r32_m32", func(t *testing.T) { - if _, err := SHLL(operand.Imm(math.MaxInt8), reg.R10L, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r32_m32", func(t *testing.T) { - if _, err := SHLL(reg.CL, reg.R10L, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSHLQValidForms(t *testing.T) { - t.Run("form=1_r64", func(t *testing.T) { - if _, err := SHLQ(operand.Imm(1), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r64", func(t *testing.T) { - if _, err := SHLQ(operand.Imm(math.MaxInt8), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r64", func(t *testing.T) { - if _, err := SHLQ(reg.CL, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m64", func(t *testing.T) { - if _, err := SHLQ(operand.Imm(1), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m64", func(t *testing.T) { - if _, err := SHLQ(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m64", func(t *testing.T) { - if _, err := SHLQ(reg.CL, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r64_r64", func(t *testing.T) { - if _, err := SHLQ(operand.Imm(math.MaxInt8), reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r64_r64", func(t *testing.T) { - if _, err := SHLQ(reg.CL, reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r64_m64", func(t *testing.T) { - if _, err := SHLQ(operand.Imm(math.MaxInt8), reg.R11, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r64_m64", func(t *testing.T) { - if _, err := SHLQ(reg.CL, reg.R11, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSHLWValidForms(t *testing.T) { - t.Run("form=1_r16", func(t *testing.T) { - if _, err := SHLW(operand.Imm(1), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := SHLW(operand.Imm(1), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r16", func(t *testing.T) { - if _, err := SHLW(operand.Imm(math.MaxInt8), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := SHLW(operand.Imm(math.MaxInt8), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r16", func(t *testing.T) { - if _, err := SHLW(reg.CL, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := SHLW(reg.CL, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m16", func(t *testing.T) { - if _, err := SHLW(operand.Imm(1), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m16", func(t *testing.T) { - if _, err := SHLW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m16", func(t *testing.T) { - if _, err := SHLW(reg.CL, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r16_r16", func(t *testing.T) { - if _, err := SHLW(operand.Imm(math.MaxInt8), reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := SHLW(operand.Imm(math.MaxInt8), reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := SHLW(operand.Imm(math.MaxInt8), reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := SHLW(operand.Imm(math.MaxInt8), reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r16_r16", func(t *testing.T) { - if _, err := SHLW(reg.CL, reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := SHLW(reg.CL, reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := SHLW(reg.CL, reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := SHLW(reg.CL, reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r16_m16", func(t *testing.T) { - if _, err := SHLW(operand.Imm(math.MaxInt8), reg.CX, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - if _, err := SHLW(operand.Imm(math.MaxInt8), reg.R9W, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r16_m16", func(t *testing.T) { - if _, err := SHLW(reg.CL, reg.CX, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - if _, err := SHLW(reg.CL, reg.R9W, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSHLXLValidForms(t *testing.T) { - t.Run("form=r32_r32_r32", func(t *testing.T) { - if _, err := SHLXL(reg.R10L, reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_m32_r32", func(t *testing.T) { - if _, err := SHLXL(reg.R10L, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestSHLXQValidForms(t *testing.T) { - t.Run("form=r64_r64_r64", func(t *testing.T) { - if _, err := SHLXQ(reg.R11, reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_m64_r64", func(t *testing.T) { - if _, err := SHLXQ(reg.R11, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestSHRBValidForms(t *testing.T) { - t.Run("form=1_r8", func(t *testing.T) { - if _, err := SHRB(operand.Imm(1), reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SHRB(operand.Imm(1), reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SHRB(operand.Imm(1), reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r8", func(t *testing.T) { - if _, err := SHRB(operand.Imm(math.MaxInt8), reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SHRB(operand.Imm(math.MaxInt8), reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SHRB(operand.Imm(math.MaxInt8), reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r8", func(t *testing.T) { - if _, err := SHRB(reg.CL, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SHRB(reg.CL, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SHRB(reg.CL, reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m8", func(t *testing.T) { - if _, err := SHRB(operand.Imm(1), operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m8", func(t *testing.T) { - if _, err := SHRB(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m8", func(t *testing.T) { - if _, err := SHRB(reg.CL, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSHRLValidForms(t *testing.T) { - t.Run("form=1_r32", func(t *testing.T) { - if _, err := SHRL(operand.Imm(1), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r32", func(t *testing.T) { - if _, err := SHRL(operand.Imm(math.MaxInt8), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r32", func(t *testing.T) { - if _, err := SHRL(reg.CL, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m32", func(t *testing.T) { - if _, err := SHRL(operand.Imm(1), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m32", func(t *testing.T) { - if _, err := SHRL(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m32", func(t *testing.T) { - if _, err := SHRL(reg.CL, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r32_r32", func(t *testing.T) { - if _, err := SHRL(operand.Imm(math.MaxInt8), reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r32_r32", func(t *testing.T) { - if _, err := SHRL(reg.CL, reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r32_m32", func(t *testing.T) { - if _, err := SHRL(operand.Imm(math.MaxInt8), reg.R10L, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r32_m32", func(t *testing.T) { - if _, err := SHRL(reg.CL, reg.R10L, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSHRQValidForms(t *testing.T) { - t.Run("form=1_r64", func(t *testing.T) { - if _, err := SHRQ(operand.Imm(1), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r64", func(t *testing.T) { - if _, err := SHRQ(operand.Imm(math.MaxInt8), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r64", func(t *testing.T) { - if _, err := SHRQ(reg.CL, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m64", func(t *testing.T) { - if _, err := SHRQ(operand.Imm(1), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m64", func(t *testing.T) { - if _, err := SHRQ(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m64", func(t *testing.T) { - if _, err := SHRQ(reg.CL, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r64_r64", func(t *testing.T) { - if _, err := SHRQ(operand.Imm(math.MaxInt8), reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r64_r64", func(t *testing.T) { - if _, err := SHRQ(reg.CL, reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r64_m64", func(t *testing.T) { - if _, err := SHRQ(operand.Imm(math.MaxInt8), reg.R11, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r64_m64", func(t *testing.T) { - if _, err := SHRQ(reg.CL, reg.R11, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSHRWValidForms(t *testing.T) { - t.Run("form=1_r16", func(t *testing.T) { - if _, err := SHRW(operand.Imm(1), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := SHRW(operand.Imm(1), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r16", func(t *testing.T) { - if _, err := SHRW(operand.Imm(math.MaxInt8), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := SHRW(operand.Imm(math.MaxInt8), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r16", func(t *testing.T) { - if _, err := SHRW(reg.CL, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := SHRW(reg.CL, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=1_m16", func(t *testing.T) { - if _, err := SHRW(operand.Imm(1), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m16", func(t *testing.T) { - if _, err := SHRW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_m16", func(t *testing.T) { - if _, err := SHRW(reg.CL, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r16_r16", func(t *testing.T) { - if _, err := SHRW(operand.Imm(math.MaxInt8), reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := SHRW(operand.Imm(math.MaxInt8), reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := SHRW(operand.Imm(math.MaxInt8), reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := SHRW(operand.Imm(math.MaxInt8), reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r16_r16", func(t *testing.T) { - if _, err := SHRW(reg.CL, reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := SHRW(reg.CL, reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := SHRW(reg.CL, reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := SHRW(reg.CL, reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r16_m16", func(t *testing.T) { - if _, err := SHRW(operand.Imm(math.MaxInt8), reg.CX, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - if _, err := SHRW(operand.Imm(math.MaxInt8), reg.R9W, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=cl_r16_m16", func(t *testing.T) { - if _, err := SHRW(reg.CL, reg.CX, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - if _, err := SHRW(reg.CL, reg.R9W, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSHRXLValidForms(t *testing.T) { - t.Run("form=r32_r32_r32", func(t *testing.T) { - if _, err := SHRXL(reg.R10L, reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_m32_r32", func(t *testing.T) { - if _, err := SHRXL(reg.R10L, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestSHRXQValidForms(t *testing.T) { - t.Run("form=r64_r64_r64", func(t *testing.T) { - if _, err := SHRXQ(reg.R11, reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_m64_r64", func(t *testing.T) { - if _, err := SHRXQ(reg.R11, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestSHUFPDValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := SHUFPD(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := SHUFPD(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestSHUFPSValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := SHUFPS(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := SHUFPS(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestSQRTPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := SQRTPD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := SQRTPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestSQRTPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := SQRTPS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := SQRTPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestSQRTSDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := SQRTSD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := SQRTSD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestSQRTSSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := SQRTSS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := SQRTSS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestSTCValidForms(t *testing.T) { - t.Run("form=", func(t *testing.T) { - if _, err := STC(); err != nil { - t.Fatal(err) - } - }) -} - -func TestSTDValidForms(t *testing.T) { - t.Run("form=", func(t *testing.T) { - if _, err := STD(); err != nil { - t.Fatal(err) - } - }) -} - -func TestSTMXCSRValidForms(t *testing.T) { - t.Run("form=m32", func(t *testing.T) { - if _, err := STMXCSR(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSUBBValidForms(t *testing.T) { - t.Run("form=imm8_al", func(t *testing.T) { - if _, err := SUBB(operand.Imm(math.MaxInt8), reg.AL); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r8", func(t *testing.T) { - if _, err := SUBB(operand.Imm(math.MaxInt8), reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SUBB(operand.Imm(math.MaxInt8), reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SUBB(operand.Imm(math.MaxInt8), reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r8_r8", func(t *testing.T) { - if _, err := SUBB(reg.CH, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SUBB(reg.CH, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SUBB(reg.CH, reg.R13B); err != nil { - t.Fatal(err) - } - if _, err := SUBB(reg.BL, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SUBB(reg.BL, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SUBB(reg.BL, reg.R13B); err != nil { - t.Fatal(err) - } - if _, err := SUBB(reg.R13B, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SUBB(reg.R13B, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SUBB(reg.R13B, reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8_r8", func(t *testing.T) { - if _, err := SUBB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := SUBB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := SUBB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m8", func(t *testing.T) { - if _, err := SUBB(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r8_m8", func(t *testing.T) { - if _, err := SUBB(reg.CH, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - if _, err := SUBB(reg.BL, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - if _, err := SUBB(reg.R13B, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSUBLValidForms(t *testing.T) { - t.Run("form=imm32_eax", func(t *testing.T) { - if _, err := SUBL(operand.Imm(math.MaxInt32), reg.EAX); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r32", func(t *testing.T) { - if _, err := SUBL(operand.Imm(math.MaxInt8), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_r32", func(t *testing.T) { - if _, err := SUBL(operand.Imm(math.MaxInt32), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := SUBL(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := SUBL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m32", func(t *testing.T) { - if _, err := SUBL(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_m32", func(t *testing.T) { - if _, err := SUBL(operand.Imm(math.MaxInt32), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_m32", func(t *testing.T) { - if _, err := SUBL(reg.R10L, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSUBPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := SUBPD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := SUBPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestSUBPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := SUBPS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := SUBPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestSUBQValidForms(t *testing.T) { - t.Run("form=imm32_rax", func(t *testing.T) { - if _, err := SUBQ(operand.Imm(math.MaxInt32), reg.RAX); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r64", func(t *testing.T) { - if _, err := SUBQ(operand.Imm(math.MaxInt8), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_r64", func(t *testing.T) { - if _, err := SUBQ(operand.Imm(math.MaxInt32), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := SUBQ(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := SUBQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m64", func(t *testing.T) { - if _, err := SUBQ(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_m64", func(t *testing.T) { - if _, err := SUBQ(operand.Imm(math.MaxInt32), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_m64", func(t *testing.T) { - if _, err := SUBQ(reg.R11, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSUBSDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := SUBSD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := SUBSD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestSUBSSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := SUBSS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := SUBSS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestSUBWValidForms(t *testing.T) { - t.Run("form=imm16_ax", func(t *testing.T) { - if _, err := SUBW(operand.Imm(math.MaxInt16), reg.AX); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r16", func(t *testing.T) { - if _, err := SUBW(operand.Imm(math.MaxInt8), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := SUBW(operand.Imm(math.MaxInt8), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm16_r16", func(t *testing.T) { - if _, err := SUBW(operand.Imm(math.MaxInt16), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := SUBW(operand.Imm(math.MaxInt16), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := SUBW(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := SUBW(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := SUBW(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := SUBW(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := SUBW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := SUBW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m16", func(t *testing.T) { - if _, err := SUBW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm16_m16", func(t *testing.T) { - if _, err := SUBW(operand.Imm(math.MaxInt16), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_m16", func(t *testing.T) { - if _, err := SUBW(reg.CX, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - if _, err := SUBW(reg.R9W, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestSYSCALLValidForms(t *testing.T) { - t.Run("form=", func(t *testing.T) { - if _, err := SYSCALL(); err != nil { - t.Fatal(err) - } - }) -} - -func TestTESTBValidForms(t *testing.T) { - t.Run("form=imm8_al", func(t *testing.T) { - if _, err := TESTB(operand.Imm(math.MaxInt8), reg.AL); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r8", func(t *testing.T) { - if _, err := TESTB(operand.Imm(math.MaxInt8), reg.CH); err != nil { - t.Fatal(err) - } - if _, err := TESTB(operand.Imm(math.MaxInt8), reg.BL); err != nil { - t.Fatal(err) - } - if _, err := TESTB(operand.Imm(math.MaxInt8), reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r8_r8", func(t *testing.T) { - if _, err := TESTB(reg.CH, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := TESTB(reg.CH, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := TESTB(reg.CH, reg.R13B); err != nil { - t.Fatal(err) - } - if _, err := TESTB(reg.BL, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := TESTB(reg.BL, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := TESTB(reg.BL, reg.R13B); err != nil { - t.Fatal(err) - } - if _, err := TESTB(reg.R13B, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := TESTB(reg.R13B, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := TESTB(reg.R13B, reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m8", func(t *testing.T) { - if _, err := TESTB(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r8_m8", func(t *testing.T) { - if _, err := TESTB(reg.CH, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - if _, err := TESTB(reg.BL, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - if _, err := TESTB(reg.R13B, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestTESTLValidForms(t *testing.T) { - t.Run("form=imm32_eax", func(t *testing.T) { - if _, err := TESTL(operand.Imm(math.MaxInt32), reg.EAX); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_r32", func(t *testing.T) { - if _, err := TESTL(operand.Imm(math.MaxInt32), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := TESTL(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_m32", func(t *testing.T) { - if _, err := TESTL(operand.Imm(math.MaxInt32), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_m32", func(t *testing.T) { - if _, err := TESTL(reg.R10L, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestTESTQValidForms(t *testing.T) { - t.Run("form=imm32_rax", func(t *testing.T) { - if _, err := TESTQ(operand.Imm(math.MaxInt32), reg.RAX); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_r64", func(t *testing.T) { - if _, err := TESTQ(operand.Imm(math.MaxInt32), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := TESTQ(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_m64", func(t *testing.T) { - if _, err := TESTQ(operand.Imm(math.MaxInt32), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_m64", func(t *testing.T) { - if _, err := TESTQ(reg.R11, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestTESTWValidForms(t *testing.T) { - t.Run("form=imm16_ax", func(t *testing.T) { - if _, err := TESTW(operand.Imm(math.MaxInt16), reg.AX); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm16_r16", func(t *testing.T) { - if _, err := TESTW(operand.Imm(math.MaxInt16), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := TESTW(operand.Imm(math.MaxInt16), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := TESTW(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := TESTW(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := TESTW(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := TESTW(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm16_m16", func(t *testing.T) { - if _, err := TESTW(operand.Imm(math.MaxInt16), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_m16", func(t *testing.T) { - if _, err := TESTW(reg.CX, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - if _, err := TESTW(reg.R9W, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestTZCNTLValidForms(t *testing.T) { - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := TZCNTL(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := TZCNTL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestTZCNTQValidForms(t *testing.T) { - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := TZCNTQ(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := TZCNTQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestTZCNTWValidForms(t *testing.T) { - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := TZCNTW(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := TZCNTW(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := TZCNTW(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := TZCNTW(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := TZCNTW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := TZCNTW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) -} - -func TestUCOMISDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := UCOMISD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := UCOMISD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestUCOMISSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := UCOMISS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := UCOMISS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestUD2ValidForms(t *testing.T) { - t.Run("form=", func(t *testing.T) { - if _, err := UD2(); err != nil { - t.Fatal(err) - } - }) -} - -func TestUNPCKHPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := UNPCKHPD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := UNPCKHPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestUNPCKHPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := UNPCKHPS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := UNPCKHPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestUNPCKLPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := UNPCKLPD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := UNPCKLPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestUNPCKLPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := UNPCKLPS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := UNPCKLPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVADDPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VADDPD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VADDPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VADDPD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VADDPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVADDPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VADDPS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VADDPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VADDPS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VADDPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVADDSDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VADDSD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm_xmm", func(t *testing.T) { - if _, err := VADDSD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVADDSSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VADDSS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm_xmm", func(t *testing.T) { - if _, err := VADDSS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVADDSUBPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VADDSUBPD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VADDSUBPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VADDSUBPD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VADDSUBPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVADDSUBPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VADDSUBPS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VADDSUBPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VADDSUBPS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VADDSUBPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVAESDECValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VAESDEC(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VAESDEC(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVAESDECLASTValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VAESDECLAST(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VAESDECLAST(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVAESENCValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VAESENC(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VAESENC(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVAESENCLASTValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VAESENCLAST(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VAESENCLAST(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVAESIMCValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VAESIMC(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := VAESIMC(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVAESKEYGENASSISTValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := VAESKEYGENASSIST(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := VAESKEYGENASSIST(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVANDNPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VANDNPD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VANDNPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VANDNPD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VANDNPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVANDNPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VANDNPS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VANDNPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VANDNPS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VANDNPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVANDPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VANDPD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VANDPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VANDPD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VANDPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVANDPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VANDPS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VANDPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VANDPS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VANDPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVBLENDPDValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm_xmm", func(t *testing.T) { - if _, err := VBLENDPD(operand.Imm(math.MaxInt8), reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm_xmm", func(t *testing.T) { - if _, err := VBLENDPD(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_ymm_ymm", func(t *testing.T) { - if _, err := VBLENDPD(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m256_ymm_ymm", func(t *testing.T) { - if _, err := VBLENDPD(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVBLENDPSValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm_xmm", func(t *testing.T) { - if _, err := VBLENDPS(operand.Imm(math.MaxInt8), reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm_xmm", func(t *testing.T) { - if _, err := VBLENDPS(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_ymm_ymm", func(t *testing.T) { - if _, err := VBLENDPS(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m256_ymm_ymm", func(t *testing.T) { - if _, err := VBLENDPS(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVBLENDVPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm_xmm", func(t *testing.T) { - if _, err := VBLENDVPD(reg.X7, reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m128_xmm_xmm", func(t *testing.T) { - if _, err := VBLENDVPD(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm_ymm", func(t *testing.T) { - if _, err := VBLENDVPD(reg.Y15, reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_m256_ymm_ymm", func(t *testing.T) { - if _, err := VBLENDVPD(reg.Y15, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVBLENDVPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm_xmm", func(t *testing.T) { - if _, err := VBLENDVPS(reg.X7, reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m128_xmm_xmm", func(t *testing.T) { - if _, err := VBLENDVPS(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm_ymm", func(t *testing.T) { - if _, err := VBLENDVPS(reg.Y15, reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_m256_ymm_ymm", func(t *testing.T) { - if _, err := VBLENDVPS(reg.Y15, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVBROADCASTF128ValidForms(t *testing.T) { - t.Run("form=m128_ymm", func(t *testing.T) { - if _, err := VBROADCASTF128(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVBROADCASTI128ValidForms(t *testing.T) { - t.Run("form=m128_ymm", func(t *testing.T) { - if _, err := VBROADCASTI128(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVBROADCASTSDValidForms(t *testing.T) { - t.Run("form=xmm_ymm", func(t *testing.T) { - if _, err := VBROADCASTSD(reg.X7, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_ymm", func(t *testing.T) { - if _, err := VBROADCASTSD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVBROADCASTSSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VBROADCASTSS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := VBROADCASTSS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_ymm", func(t *testing.T) { - if _, err := VBROADCASTSS(reg.X7, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_ymm", func(t *testing.T) { - if _, err := VBROADCASTSS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCMPPDValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm_xmm", func(t *testing.T) { - if _, err := VCMPPD(operand.Imm(math.MaxInt8), reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm_xmm", func(t *testing.T) { - if _, err := VCMPPD(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_ymm_ymm", func(t *testing.T) { - if _, err := VCMPPD(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m256_ymm_ymm", func(t *testing.T) { - if _, err := VCMPPD(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCMPPSValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm_xmm", func(t *testing.T) { - if _, err := VCMPPS(operand.Imm(math.MaxInt8), reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm_xmm", func(t *testing.T) { - if _, err := VCMPPS(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_ymm_ymm", func(t *testing.T) { - if _, err := VCMPPS(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m256_ymm_ymm", func(t *testing.T) { - if _, err := VCMPPS(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCMPSDValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm_xmm", func(t *testing.T) { - if _, err := VCMPSD(operand.Imm(math.MaxInt8), reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m64_xmm_xmm", func(t *testing.T) { - if _, err := VCMPSD(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCMPSSValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm_xmm", func(t *testing.T) { - if _, err := VCMPSS(operand.Imm(math.MaxInt8), reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m32_xmm_xmm", func(t *testing.T) { - if _, err := VCMPSS(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCOMISDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VCOMISD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := VCOMISD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCOMISSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VCOMISS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := VCOMISS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCVTDQ2PDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VCVTDQ2PD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := VCVTDQ2PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_ymm", func(t *testing.T) { - if _, err := VCVTDQ2PD(reg.X7, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_ymm", func(t *testing.T) { - if _, err := VCVTDQ2PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCVTDQ2PSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VCVTDQ2PS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := VCVTDQ2PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm", func(t *testing.T) { - if _, err := VCVTDQ2PS(reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm", func(t *testing.T) { - if _, err := VCVTDQ2PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCVTPD2DQXValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VCVTPD2DQX(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := VCVTPD2DQX(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCVTPD2DQYValidForms(t *testing.T) { - t.Run("form=ymm_xmm", func(t *testing.T) { - if _, err := VCVTPD2DQY(reg.Y15, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_xmm", func(t *testing.T) { - if _, err := VCVTPD2DQY(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCVTPD2PSXValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VCVTPD2PSX(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := VCVTPD2PSX(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCVTPD2PSYValidForms(t *testing.T) { - t.Run("form=ymm_xmm", func(t *testing.T) { - if _, err := VCVTPD2PSY(reg.Y15, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_xmm", func(t *testing.T) { - if _, err := VCVTPD2PSY(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCVTPH2PSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VCVTPH2PS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := VCVTPH2PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_ymm", func(t *testing.T) { - if _, err := VCVTPH2PS(reg.X7, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_ymm", func(t *testing.T) { - if _, err := VCVTPH2PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCVTPS2DQValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VCVTPS2DQ(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := VCVTPS2DQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm", func(t *testing.T) { - if _, err := VCVTPS2DQ(reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm", func(t *testing.T) { - if _, err := VCVTPS2DQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCVTPS2PDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VCVTPS2PD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := VCVTPS2PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_ymm", func(t *testing.T) { - if _, err := VCVTPS2PD(reg.X7, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_ymm", func(t *testing.T) { - if _, err := VCVTPS2PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCVTPS2PHValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := VCVTPS2PH(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_xmm", func(t *testing.T) { - if _, err := VCVTPS2PH(operand.Imm(math.MaxInt8), reg.Y15, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_xmm_m64", func(t *testing.T) { - if _, err := VCVTPS2PH(operand.Imm(math.MaxInt8), reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_m128", func(t *testing.T) { - if _, err := VCVTPS2PH(operand.Imm(math.MaxInt8), reg.Y15, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCVTSD2SIValidForms(t *testing.T) { - t.Run("form=xmm_r32", func(t *testing.T) { - if _, err := VCVTSD2SI(reg.X7, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r32", func(t *testing.T) { - if _, err := VCVTSD2SI(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCVTSD2SIQValidForms(t *testing.T) { - t.Run("form=xmm_r64", func(t *testing.T) { - if _, err := VCVTSD2SIQ(reg.X7, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := VCVTSD2SIQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCVTSD2SSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VCVTSD2SS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm_xmm", func(t *testing.T) { - if _, err := VCVTSD2SS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCVTSI2SDLValidForms(t *testing.T) { - t.Run("form=r32_xmm_xmm", func(t *testing.T) { - if _, err := VCVTSI2SDL(reg.R10L, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm_xmm", func(t *testing.T) { - if _, err := VCVTSI2SDL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCVTSI2SDQValidForms(t *testing.T) { - t.Run("form=r64_xmm_xmm", func(t *testing.T) { - if _, err := VCVTSI2SDQ(reg.R11, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm_xmm", func(t *testing.T) { - if _, err := VCVTSI2SDQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCVTSI2SSLValidForms(t *testing.T) { - t.Run("form=r32_xmm_xmm", func(t *testing.T) { - if _, err := VCVTSI2SSL(reg.R10L, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm_xmm", func(t *testing.T) { - if _, err := VCVTSI2SSL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCVTSI2SSQValidForms(t *testing.T) { - t.Run("form=r64_xmm_xmm", func(t *testing.T) { - if _, err := VCVTSI2SSQ(reg.R11, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm_xmm", func(t *testing.T) { - if _, err := VCVTSI2SSQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCVTSS2SDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VCVTSS2SD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm_xmm", func(t *testing.T) { - if _, err := VCVTSS2SD(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCVTSS2SIValidForms(t *testing.T) { - t.Run("form=xmm_r32", func(t *testing.T) { - if _, err := VCVTSS2SI(reg.X7, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := VCVTSS2SI(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCVTSS2SIQValidForms(t *testing.T) { - t.Run("form=xmm_r64", func(t *testing.T) { - if _, err := VCVTSS2SIQ(reg.X7, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r64", func(t *testing.T) { - if _, err := VCVTSS2SIQ(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCVTTPD2DQXValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VCVTTPD2DQX(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := VCVTTPD2DQX(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCVTTPD2DQYValidForms(t *testing.T) { - t.Run("form=ymm_xmm", func(t *testing.T) { - if _, err := VCVTTPD2DQY(reg.Y15, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_xmm", func(t *testing.T) { - if _, err := VCVTTPD2DQY(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCVTTPS2DQValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VCVTTPS2DQ(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := VCVTTPS2DQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm", func(t *testing.T) { - if _, err := VCVTTPS2DQ(reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm", func(t *testing.T) { - if _, err := VCVTTPS2DQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCVTTSD2SIValidForms(t *testing.T) { - t.Run("form=xmm_r32", func(t *testing.T) { - if _, err := VCVTTSD2SI(reg.X7, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r32", func(t *testing.T) { - if _, err := VCVTTSD2SI(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCVTTSD2SIQValidForms(t *testing.T) { - t.Run("form=xmm_r64", func(t *testing.T) { - if _, err := VCVTTSD2SIQ(reg.X7, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := VCVTTSD2SIQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCVTTSS2SIValidForms(t *testing.T) { - t.Run("form=xmm_r32", func(t *testing.T) { - if _, err := VCVTTSS2SI(reg.X7, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := VCVTTSS2SI(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestVCVTTSS2SIQValidForms(t *testing.T) { - t.Run("form=xmm_r64", func(t *testing.T) { - if _, err := VCVTTSS2SIQ(reg.X7, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r64", func(t *testing.T) { - if _, err := VCVTTSS2SIQ(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R11); err != nil { - t.Fatal(err) - } - }) -} - -func TestVDIVPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VDIVPD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VDIVPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VDIVPD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VDIVPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVDIVPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VDIVPS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VDIVPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VDIVPS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VDIVPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVDIVSDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VDIVSD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm_xmm", func(t *testing.T) { - if _, err := VDIVSD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVDIVSSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VDIVSS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm_xmm", func(t *testing.T) { - if _, err := VDIVSS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVDPPDValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm_xmm", func(t *testing.T) { - if _, err := VDPPD(operand.Imm(math.MaxInt8), reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm_xmm", func(t *testing.T) { - if _, err := VDPPD(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVDPPSValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm_xmm", func(t *testing.T) { - if _, err := VDPPS(operand.Imm(math.MaxInt8), reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm_xmm", func(t *testing.T) { - if _, err := VDPPS(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_ymm_ymm", func(t *testing.T) { - if _, err := VDPPS(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m256_ymm_ymm", func(t *testing.T) { - if _, err := VDPPS(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVEXTRACTF128ValidForms(t *testing.T) { - t.Run("form=imm8_ymm_xmm", func(t *testing.T) { - if _, err := VEXTRACTF128(operand.Imm(math.MaxInt8), reg.Y15, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_m128", func(t *testing.T) { - if _, err := VEXTRACTF128(operand.Imm(math.MaxInt8), reg.Y15, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestVEXTRACTI128ValidForms(t *testing.T) { - t.Run("form=imm8_ymm_xmm", func(t *testing.T) { - if _, err := VEXTRACTI128(operand.Imm(math.MaxInt8), reg.Y15, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_m128", func(t *testing.T) { - if _, err := VEXTRACTI128(operand.Imm(math.MaxInt8), reg.Y15, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestVEXTRACTPSValidForms(t *testing.T) { - t.Run("form=imm8_xmm_r32", func(t *testing.T) { - if _, err := VEXTRACTPS(operand.Imm(math.MaxInt8), reg.X7, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_xmm_m32", func(t *testing.T) { - if _, err := VEXTRACTPS(operand.Imm(math.MaxInt8), reg.X7, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMADD132PDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMADD132PD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFMADD132PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFMADD132PD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFMADD132PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMADD132PSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMADD132PS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFMADD132PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFMADD132PS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFMADD132PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMADD132SDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMADD132SD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm_xmm", func(t *testing.T) { - if _, err := VFMADD132SD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMADD132SSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMADD132SS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm_xmm", func(t *testing.T) { - if _, err := VFMADD132SS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMADD213PDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMADD213PD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFMADD213PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFMADD213PD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFMADD213PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMADD213PSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMADD213PS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFMADD213PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFMADD213PS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFMADD213PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMADD213SDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMADD213SD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm_xmm", func(t *testing.T) { - if _, err := VFMADD213SD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMADD213SSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMADD213SS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm_xmm", func(t *testing.T) { - if _, err := VFMADD213SS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMADD231PDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMADD231PD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFMADD231PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFMADD231PD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFMADD231PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMADD231PSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMADD231PS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFMADD231PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFMADD231PS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFMADD231PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMADD231SDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMADD231SD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm_xmm", func(t *testing.T) { - if _, err := VFMADD231SD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMADD231SSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMADD231SS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm_xmm", func(t *testing.T) { - if _, err := VFMADD231SS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMADDSUB132PDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMADDSUB132PD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFMADDSUB132PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFMADDSUB132PD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFMADDSUB132PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMADDSUB132PSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMADDSUB132PS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFMADDSUB132PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFMADDSUB132PS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFMADDSUB132PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMADDSUB213PDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMADDSUB213PD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFMADDSUB213PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFMADDSUB213PD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFMADDSUB213PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMADDSUB213PSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMADDSUB213PS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFMADDSUB213PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFMADDSUB213PS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFMADDSUB213PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMADDSUB231PDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMADDSUB231PD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFMADDSUB231PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFMADDSUB231PD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFMADDSUB231PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMADDSUB231PSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMADDSUB231PS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFMADDSUB231PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFMADDSUB231PS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFMADDSUB231PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMSUB132PDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUB132PD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUB132PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFMSUB132PD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFMSUB132PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMSUB132PSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUB132PS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUB132PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFMSUB132PS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFMSUB132PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMSUB132SDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUB132SD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUB132SD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMSUB132SSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUB132SS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUB132SS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMSUB213PDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUB213PD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUB213PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFMSUB213PD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFMSUB213PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMSUB213PSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUB213PS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUB213PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFMSUB213PS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFMSUB213PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMSUB213SDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUB213SD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUB213SD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMSUB213SSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUB213SS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUB213SS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMSUB231PDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUB231PD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUB231PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFMSUB231PD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFMSUB231PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMSUB231PSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUB231PS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUB231PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFMSUB231PS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFMSUB231PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMSUB231SDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUB231SD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUB231SD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMSUB231SSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUB231SS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUB231SS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMSUBADD132PDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUBADD132PD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUBADD132PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFMSUBADD132PD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFMSUBADD132PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMSUBADD132PSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUBADD132PS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUBADD132PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFMSUBADD132PS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFMSUBADD132PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMSUBADD213PDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUBADD213PD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUBADD213PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFMSUBADD213PD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFMSUBADD213PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMSUBADD213PSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUBADD213PS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUBADD213PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFMSUBADD213PS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFMSUBADD213PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMSUBADD231PDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUBADD231PD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUBADD231PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFMSUBADD231PD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFMSUBADD231PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFMSUBADD231PSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUBADD231PS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFMSUBADD231PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFMSUBADD231PS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFMSUBADD231PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFNMADD132PDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFNMADD132PD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFNMADD132PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFNMADD132PD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFNMADD132PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFNMADD132PSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFNMADD132PS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFNMADD132PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFNMADD132PS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFNMADD132PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFNMADD132SDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFNMADD132SD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm_xmm", func(t *testing.T) { - if _, err := VFNMADD132SD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFNMADD132SSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFNMADD132SS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm_xmm", func(t *testing.T) { - if _, err := VFNMADD132SS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFNMADD213PDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFNMADD213PD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFNMADD213PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFNMADD213PD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFNMADD213PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFNMADD213PSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFNMADD213PS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFNMADD213PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFNMADD213PS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFNMADD213PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFNMADD213SDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFNMADD213SD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm_xmm", func(t *testing.T) { - if _, err := VFNMADD213SD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFNMADD213SSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFNMADD213SS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm_xmm", func(t *testing.T) { - if _, err := VFNMADD213SS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFNMADD231PDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFNMADD231PD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFNMADD231PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFNMADD231PD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFNMADD231PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFNMADD231PSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFNMADD231PS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFNMADD231PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFNMADD231PS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFNMADD231PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFNMADD231SDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFNMADD231SD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm_xmm", func(t *testing.T) { - if _, err := VFNMADD231SD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFNMADD231SSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFNMADD231SS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm_xmm", func(t *testing.T) { - if _, err := VFNMADD231SS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFNMSUB132PDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFNMSUB132PD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFNMSUB132PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFNMSUB132PD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFNMSUB132PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFNMSUB132PSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFNMSUB132PS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFNMSUB132PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFNMSUB132PS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFNMSUB132PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFNMSUB132SDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFNMSUB132SD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm_xmm", func(t *testing.T) { - if _, err := VFNMSUB132SD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFNMSUB132SSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFNMSUB132SS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm_xmm", func(t *testing.T) { - if _, err := VFNMSUB132SS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFNMSUB213PDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFNMSUB213PD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFNMSUB213PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFNMSUB213PD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFNMSUB213PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFNMSUB213PSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFNMSUB213PS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFNMSUB213PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFNMSUB213PS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFNMSUB213PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFNMSUB213SDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFNMSUB213SD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm_xmm", func(t *testing.T) { - if _, err := VFNMSUB213SD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFNMSUB213SSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFNMSUB213SS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm_xmm", func(t *testing.T) { - if _, err := VFNMSUB213SS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFNMSUB231PDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFNMSUB231PD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFNMSUB231PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFNMSUB231PD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFNMSUB231PD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFNMSUB231PSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFNMSUB231PS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VFNMSUB231PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VFNMSUB231PS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VFNMSUB231PS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFNMSUB231SDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFNMSUB231SD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm_xmm", func(t *testing.T) { - if _, err := VFNMSUB231SD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVFNMSUB231SSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VFNMSUB231SS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm_xmm", func(t *testing.T) { - if _, err := VFNMSUB231SS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVGATHERDPDValidForms(t *testing.T) { - t.Run("form=xmm_vm32x_xmm", func(t *testing.T) { - if _, err := VGATHERDPD(reg.X7, operand.Mem{Base: reg.R13, Index: reg.X4, Scale: 1}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_vm32x_ymm", func(t *testing.T) { - if _, err := VGATHERDPD(reg.Y15, operand.Mem{Base: reg.R13, Index: reg.X4, Scale: 1}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVGATHERDPSValidForms(t *testing.T) { - t.Run("form=xmm_vm32x_xmm", func(t *testing.T) { - if _, err := VGATHERDPS(reg.X7, operand.Mem{Base: reg.R13, Index: reg.X4, Scale: 1}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_vm32y_ymm", func(t *testing.T) { - if _, err := VGATHERDPS(reg.Y15, operand.Mem{Base: reg.R13, Index: reg.Y4, Scale: 1}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVGATHERQPDValidForms(t *testing.T) { - t.Run("form=xmm_vm64x_xmm", func(t *testing.T) { - if _, err := VGATHERQPD(reg.X7, operand.Mem{Base: reg.R13, Index: reg.X8, Scale: 1}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_vm64y_ymm", func(t *testing.T) { - if _, err := VGATHERQPD(reg.Y15, operand.Mem{Base: reg.R13, Index: reg.Y8, Scale: 1}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVGATHERQPSValidForms(t *testing.T) { - t.Run("form=xmm_vm64x_xmm", func(t *testing.T) { - if _, err := VGATHERQPS(reg.X7, operand.Mem{Base: reg.R13, Index: reg.X8, Scale: 1}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_vm64y_xmm", func(t *testing.T) { - if _, err := VGATHERQPS(reg.X7, operand.Mem{Base: reg.R13, Index: reg.Y8, Scale: 1}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVHADDPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VHADDPD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VHADDPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VHADDPD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VHADDPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVHADDPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VHADDPS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VHADDPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VHADDPS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VHADDPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVHSUBPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VHSUBPD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VHSUBPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VHSUBPD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VHSUBPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVHSUBPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VHSUBPS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VHSUBPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VHSUBPS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VHSUBPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVINSERTF128ValidForms(t *testing.T) { - t.Run("form=imm8_xmm_ymm_ymm", func(t *testing.T) { - if _, err := VINSERTF128(operand.Imm(math.MaxInt8), reg.X7, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_ymm_ymm", func(t *testing.T) { - if _, err := VINSERTF128(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVINSERTI128ValidForms(t *testing.T) { - t.Run("form=imm8_xmm_ymm_ymm", func(t *testing.T) { - if _, err := VINSERTI128(operand.Imm(math.MaxInt8), reg.X7, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_ymm_ymm", func(t *testing.T) { - if _, err := VINSERTI128(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVINSERTPSValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm_xmm", func(t *testing.T) { - if _, err := VINSERTPS(operand.Imm(math.MaxInt8), reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m32_xmm_xmm", func(t *testing.T) { - if _, err := VINSERTPS(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVLDDQUValidForms(t *testing.T) { - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := VLDDQU(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm", func(t *testing.T) { - if _, err := VLDDQU(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVLDMXCSRValidForms(t *testing.T) { - t.Run("form=m32", func(t *testing.T) { - if _, err := VLDMXCSR(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMASKMOVDQUValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VMASKMOVDQU(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMASKMOVPDValidForms(t *testing.T) { - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VMASKMOVPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VMASKMOVPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_xmm_m128", func(t *testing.T) { - if _, err := VMASKMOVPD(reg.X7, reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_m256", func(t *testing.T) { - if _, err := VMASKMOVPD(reg.Y15, reg.Y15, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMASKMOVPSValidForms(t *testing.T) { - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VMASKMOVPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VMASKMOVPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_xmm_m128", func(t *testing.T) { - if _, err := VMASKMOVPS(reg.X7, reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_m256", func(t *testing.T) { - if _, err := VMASKMOVPS(reg.Y15, reg.Y15, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMAXPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VMAXPD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VMAXPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VMAXPD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VMAXPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMAXPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VMAXPS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VMAXPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VMAXPS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VMAXPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMAXSDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VMAXSD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm_xmm", func(t *testing.T) { - if _, err := VMAXSD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMAXSSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VMAXSS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm_xmm", func(t *testing.T) { - if _, err := VMAXSS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMINPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VMINPD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VMINPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VMINPD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VMINPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMINPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VMINPS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VMINPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VMINPS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VMINPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMINSDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VMINSD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm_xmm", func(t *testing.T) { - if _, err := VMINSD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMINSSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VMINSS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm_xmm", func(t *testing.T) { - if _, err := VMINSS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMOVAPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VMOVAPD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := VMOVAPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm", func(t *testing.T) { - if _, err := VMOVAPD(reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm", func(t *testing.T) { - if _, err := VMOVAPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m128", func(t *testing.T) { - if _, err := VMOVAPD(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_m256", func(t *testing.T) { - if _, err := VMOVAPD(reg.Y15, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMOVAPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VMOVAPS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := VMOVAPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm", func(t *testing.T) { - if _, err := VMOVAPS(reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm", func(t *testing.T) { - if _, err := VMOVAPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m128", func(t *testing.T) { - if _, err := VMOVAPS(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_m256", func(t *testing.T) { - if _, err := VMOVAPS(reg.Y15, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMOVDValidForms(t *testing.T) { - t.Run("form=xmm_r32", func(t *testing.T) { - if _, err := VMOVD(reg.X7, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_xmm", func(t *testing.T) { - if _, err := VMOVD(reg.R10L, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := VMOVD(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m32", func(t *testing.T) { - if _, err := VMOVD(reg.X7, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMOVDDUPValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VMOVDDUP(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := VMOVDDUP(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm", func(t *testing.T) { - if _, err := VMOVDDUP(reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm", func(t *testing.T) { - if _, err := VMOVDDUP(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMOVDQAValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VMOVDQA(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := VMOVDQA(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm", func(t *testing.T) { - if _, err := VMOVDQA(reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm", func(t *testing.T) { - if _, err := VMOVDQA(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m128", func(t *testing.T) { - if _, err := VMOVDQA(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_m256", func(t *testing.T) { - if _, err := VMOVDQA(reg.Y15, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMOVDQUValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VMOVDQU(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := VMOVDQU(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm", func(t *testing.T) { - if _, err := VMOVDQU(reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm", func(t *testing.T) { - if _, err := VMOVDQU(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m128", func(t *testing.T) { - if _, err := VMOVDQU(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_m256", func(t *testing.T) { - if _, err := VMOVDQU(reg.Y15, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMOVHLPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VMOVHLPS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMOVHPDValidForms(t *testing.T) { - t.Run("form=xmm_m64", func(t *testing.T) { - if _, err := VMOVHPD(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm_xmm", func(t *testing.T) { - if _, err := VMOVHPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMOVHPSValidForms(t *testing.T) { - t.Run("form=xmm_m64", func(t *testing.T) { - if _, err := VMOVHPS(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm_xmm", func(t *testing.T) { - if _, err := VMOVHPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMOVLHPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VMOVLHPS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMOVLPDValidForms(t *testing.T) { - t.Run("form=xmm_m64", func(t *testing.T) { - if _, err := VMOVLPD(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm_xmm", func(t *testing.T) { - if _, err := VMOVLPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMOVLPSValidForms(t *testing.T) { - t.Run("form=xmm_m64", func(t *testing.T) { - if _, err := VMOVLPS(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm_xmm", func(t *testing.T) { - if _, err := VMOVLPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMOVMSKPDValidForms(t *testing.T) { - t.Run("form=xmm_r32", func(t *testing.T) { - if _, err := VMOVMSKPD(reg.X7, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_r32", func(t *testing.T) { - if _, err := VMOVMSKPD(reg.Y15, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMOVMSKPSValidForms(t *testing.T) { - t.Run("form=xmm_r32", func(t *testing.T) { - if _, err := VMOVMSKPS(reg.X7, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_r32", func(t *testing.T) { - if _, err := VMOVMSKPS(reg.Y15, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMOVNTDQValidForms(t *testing.T) { - t.Run("form=xmm_m128", func(t *testing.T) { - if _, err := VMOVNTDQ(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_m256", func(t *testing.T) { - if _, err := VMOVNTDQ(reg.Y15, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMOVNTDQAValidForms(t *testing.T) { - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := VMOVNTDQA(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm", func(t *testing.T) { - if _, err := VMOVNTDQA(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMOVNTPDValidForms(t *testing.T) { - t.Run("form=xmm_m128", func(t *testing.T) { - if _, err := VMOVNTPD(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_m256", func(t *testing.T) { - if _, err := VMOVNTPD(reg.Y15, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMOVNTPSValidForms(t *testing.T) { - t.Run("form=xmm_m128", func(t *testing.T) { - if _, err := VMOVNTPS(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_m256", func(t *testing.T) { - if _, err := VMOVNTPS(reg.Y15, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMOVQValidForms(t *testing.T) { - t.Run("form=xmm_r64", func(t *testing.T) { - if _, err := VMOVQ(reg.X7, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_xmm", func(t *testing.T) { - if _, err := VMOVQ(reg.R11, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VMOVQ(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := VMOVQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m64", func(t *testing.T) { - if _, err := VMOVQ(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMOVSDValidForms(t *testing.T) { - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := VMOVSD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m64", func(t *testing.T) { - if _, err := VMOVSD(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VMOVSD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMOVSHDUPValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VMOVSHDUP(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := VMOVSHDUP(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm", func(t *testing.T) { - if _, err := VMOVSHDUP(reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm", func(t *testing.T) { - if _, err := VMOVSHDUP(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMOVSLDUPValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VMOVSLDUP(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := VMOVSLDUP(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm", func(t *testing.T) { - if _, err := VMOVSLDUP(reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm", func(t *testing.T) { - if _, err := VMOVSLDUP(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMOVSSValidForms(t *testing.T) { - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := VMOVSS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m32", func(t *testing.T) { - if _, err := VMOVSS(reg.X7, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VMOVSS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMOVUPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VMOVUPD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := VMOVUPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm", func(t *testing.T) { - if _, err := VMOVUPD(reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm", func(t *testing.T) { - if _, err := VMOVUPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m128", func(t *testing.T) { - if _, err := VMOVUPD(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_m256", func(t *testing.T) { - if _, err := VMOVUPD(reg.Y15, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMOVUPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VMOVUPS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := VMOVUPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm", func(t *testing.T) { - if _, err := VMOVUPS(reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm", func(t *testing.T) { - if _, err := VMOVUPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m128", func(t *testing.T) { - if _, err := VMOVUPS(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_m256", func(t *testing.T) { - if _, err := VMOVUPS(reg.Y15, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMPSADBWValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm_xmm", func(t *testing.T) { - if _, err := VMPSADBW(operand.Imm(math.MaxInt8), reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm_xmm", func(t *testing.T) { - if _, err := VMPSADBW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_ymm_ymm", func(t *testing.T) { - if _, err := VMPSADBW(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m256_ymm_ymm", func(t *testing.T) { - if _, err := VMPSADBW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMULPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VMULPD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VMULPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VMULPD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VMULPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMULPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VMULPS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VMULPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VMULPS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VMULPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMULSDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VMULSD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm_xmm", func(t *testing.T) { - if _, err := VMULSD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVMULSSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VMULSS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm_xmm", func(t *testing.T) { - if _, err := VMULSS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVORPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VORPD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VORPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VORPD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VORPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVORPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VORPS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VORPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VORPS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VORPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPABSBValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VPABSB(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := VPABSB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm", func(t *testing.T) { - if _, err := VPABSB(reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm", func(t *testing.T) { - if _, err := VPABSB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPABSDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VPABSD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := VPABSD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm", func(t *testing.T) { - if _, err := VPABSD(reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm", func(t *testing.T) { - if _, err := VPABSD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPABSWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VPABSW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := VPABSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm", func(t *testing.T) { - if _, err := VPABSW(reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm", func(t *testing.T) { - if _, err := VPABSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPACKSSDWValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPACKSSDW(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPACKSSDW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPACKSSDW(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPACKSSDW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPACKSSWBValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPACKSSWB(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPACKSSWB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPACKSSWB(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPACKSSWB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPACKUSDWValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPACKUSDW(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPACKUSDW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPACKUSDW(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPACKUSDW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPACKUSWBValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPACKUSWB(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPACKUSWB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPACKUSWB(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPACKUSWB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPADDBValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPADDB(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPADDB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPADDB(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPADDB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPADDDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPADDD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPADDD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPADDD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPADDD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPADDQValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPADDQ(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPADDQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPADDQ(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPADDQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPADDSBValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPADDSB(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPADDSB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPADDSB(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPADDSB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPADDSWValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPADDSW(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPADDSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPADDSW(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPADDSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPADDUSBValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPADDUSB(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPADDUSB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPADDUSB(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPADDUSB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPADDUSWValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPADDUSW(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPADDUSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPADDUSW(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPADDUSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPADDWValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPADDW(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPADDW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPADDW(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPADDW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPALIGNRValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPALIGNR(operand.Imm(math.MaxInt8), reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm_xmm", func(t *testing.T) { - if _, err := VPALIGNR(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPALIGNR(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m256_ymm_ymm", func(t *testing.T) { - if _, err := VPALIGNR(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPANDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPAND(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPAND(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPAND(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPAND(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPANDNValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPANDN(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPANDN(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPANDN(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPANDN(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPAVGBValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPAVGB(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPAVGB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPAVGB(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPAVGB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPAVGWValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPAVGW(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPAVGW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPAVGW(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPAVGW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPBLENDDValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPBLENDD(operand.Imm(math.MaxInt8), reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm_xmm", func(t *testing.T) { - if _, err := VPBLENDD(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPBLENDD(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m256_ymm_ymm", func(t *testing.T) { - if _, err := VPBLENDD(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPBLENDVBValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPBLENDVB(reg.X7, reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_m128_xmm_xmm", func(t *testing.T) { - if _, err := VPBLENDVB(reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPBLENDVB(reg.Y15, reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_m256_ymm_ymm", func(t *testing.T) { - if _, err := VPBLENDVB(reg.Y15, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPBLENDWValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPBLENDW(operand.Imm(math.MaxInt8), reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm_xmm", func(t *testing.T) { - if _, err := VPBLENDW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPBLENDW(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m256_ymm_ymm", func(t *testing.T) { - if _, err := VPBLENDW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPBROADCASTBValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VPBROADCASTB(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8_xmm", func(t *testing.T) { - if _, err := VPBROADCASTB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_ymm", func(t *testing.T) { - if _, err := VPBROADCASTB(reg.X7, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8_ymm", func(t *testing.T) { - if _, err := VPBROADCASTB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPBROADCASTDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VPBROADCASTD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := VPBROADCASTD(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_ymm", func(t *testing.T) { - if _, err := VPBROADCASTD(reg.X7, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_ymm", func(t *testing.T) { - if _, err := VPBROADCASTD(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPBROADCASTQValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VPBROADCASTQ(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := VPBROADCASTQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_ymm", func(t *testing.T) { - if _, err := VPBROADCASTQ(reg.X7, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_ymm", func(t *testing.T) { - if _, err := VPBROADCASTQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPBROADCASTWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VPBROADCASTW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_xmm", func(t *testing.T) { - if _, err := VPBROADCASTW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_ymm", func(t *testing.T) { - if _, err := VPBROADCASTW(reg.X7, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_ymm", func(t *testing.T) { - if _, err := VPBROADCASTW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPCLMULQDQValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPCLMULQDQ(operand.Imm(math.MaxInt8), reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm_xmm", func(t *testing.T) { - if _, err := VPCLMULQDQ(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPCMPEQBValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPCMPEQB(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPCMPEQB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPCMPEQB(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPCMPEQB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPCMPEQDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPCMPEQD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPCMPEQD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPCMPEQD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPCMPEQD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPCMPEQQValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPCMPEQQ(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPCMPEQQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPCMPEQQ(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPCMPEQQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPCMPEQWValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPCMPEQW(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPCMPEQW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPCMPEQW(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPCMPEQW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPCMPESTRIValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := VPCMPESTRI(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := VPCMPESTRI(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPCMPESTRMValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := VPCMPESTRM(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := VPCMPESTRM(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPCMPGTBValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPCMPGTB(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPCMPGTB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPCMPGTB(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPCMPGTB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPCMPGTDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPCMPGTD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPCMPGTD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPCMPGTD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPCMPGTD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPCMPGTQValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPCMPGTQ(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPCMPGTQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPCMPGTQ(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPCMPGTQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPCMPGTWValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPCMPGTW(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPCMPGTW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPCMPGTW(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPCMPGTW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPCMPISTRIValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := VPCMPISTRI(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := VPCMPISTRI(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPCMPISTRMValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := VPCMPISTRM(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := VPCMPISTRM(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPERM2F128ValidForms(t *testing.T) { - t.Run("form=imm8_ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPERM2F128(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m256_ymm_ymm", func(t *testing.T) { - if _, err := VPERM2F128(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPERM2I128ValidForms(t *testing.T) { - t.Run("form=imm8_ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPERM2I128(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m256_ymm_ymm", func(t *testing.T) { - if _, err := VPERM2I128(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPERMDValidForms(t *testing.T) { - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPERMD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPERMD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPERMILPDValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := VPERMILPD(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPERMILPD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPERMILPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := VPERMILPD(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_ymm", func(t *testing.T) { - if _, err := VPERMILPD(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPERMILPD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPERMILPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m256_ymm", func(t *testing.T) { - if _, err := VPERMILPD(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPERMILPSValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := VPERMILPS(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPERMILPS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPERMILPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := VPERMILPS(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_ymm", func(t *testing.T) { - if _, err := VPERMILPS(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPERMILPS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPERMILPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m256_ymm", func(t *testing.T) { - if _, err := VPERMILPS(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPERMPDValidForms(t *testing.T) { - t.Run("form=imm8_ymm_ymm", func(t *testing.T) { - if _, err := VPERMPD(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m256_ymm", func(t *testing.T) { - if _, err := VPERMPD(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPERMPSValidForms(t *testing.T) { - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPERMPS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPERMPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPERMQValidForms(t *testing.T) { - t.Run("form=imm8_ymm_ymm", func(t *testing.T) { - if _, err := VPERMQ(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m256_ymm", func(t *testing.T) { - if _, err := VPERMQ(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPEXTRBValidForms(t *testing.T) { - t.Run("form=imm8_xmm_r32", func(t *testing.T) { - if _, err := VPEXTRB(operand.Imm(math.MaxInt8), reg.X7, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_xmm_m8", func(t *testing.T) { - if _, err := VPEXTRB(operand.Imm(math.MaxInt8), reg.X7, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPEXTRDValidForms(t *testing.T) { - t.Run("form=imm8_xmm_r32", func(t *testing.T) { - if _, err := VPEXTRD(operand.Imm(math.MaxInt8), reg.X7, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_xmm_m32", func(t *testing.T) { - if _, err := VPEXTRD(operand.Imm(math.MaxInt8), reg.X7, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPEXTRQValidForms(t *testing.T) { - t.Run("form=imm8_xmm_r64", func(t *testing.T) { - if _, err := VPEXTRQ(operand.Imm(math.MaxInt8), reg.X7, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_xmm_m64", func(t *testing.T) { - if _, err := VPEXTRQ(operand.Imm(math.MaxInt8), reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPEXTRWValidForms(t *testing.T) { - t.Run("form=imm8_xmm_r32", func(t *testing.T) { - if _, err := VPEXTRW(operand.Imm(math.MaxInt8), reg.X7, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_xmm_m16", func(t *testing.T) { - if _, err := VPEXTRW(operand.Imm(math.MaxInt8), reg.X7, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPGATHERDDValidForms(t *testing.T) { - t.Run("form=xmm_vm32x_xmm", func(t *testing.T) { - if _, err := VPGATHERDD(reg.X7, operand.Mem{Base: reg.R13, Index: reg.X4, Scale: 1}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_vm32y_ymm", func(t *testing.T) { - if _, err := VPGATHERDD(reg.Y15, operand.Mem{Base: reg.R13, Index: reg.Y4, Scale: 1}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPGATHERDQValidForms(t *testing.T) { - t.Run("form=xmm_vm32x_xmm", func(t *testing.T) { - if _, err := VPGATHERDQ(reg.X7, operand.Mem{Base: reg.R13, Index: reg.X4, Scale: 1}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_vm32x_ymm", func(t *testing.T) { - if _, err := VPGATHERDQ(reg.Y15, operand.Mem{Base: reg.R13, Index: reg.X4, Scale: 1}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPGATHERQDValidForms(t *testing.T) { - t.Run("form=xmm_vm64x_xmm", func(t *testing.T) { - if _, err := VPGATHERQD(reg.X7, operand.Mem{Base: reg.R13, Index: reg.X8, Scale: 1}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_vm64y_xmm", func(t *testing.T) { - if _, err := VPGATHERQD(reg.X7, operand.Mem{Base: reg.R13, Index: reg.Y8, Scale: 1}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPGATHERQQValidForms(t *testing.T) { - t.Run("form=xmm_vm64x_xmm", func(t *testing.T) { - if _, err := VPGATHERQQ(reg.X7, operand.Mem{Base: reg.R13, Index: reg.X8, Scale: 1}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_vm64y_ymm", func(t *testing.T) { - if _, err := VPGATHERQQ(reg.Y15, operand.Mem{Base: reg.R13, Index: reg.Y8, Scale: 1}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPHADDDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPHADDD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPHADDD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPHADDD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPHADDD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPHADDSWValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPHADDSW(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPHADDSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPHADDSW(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPHADDSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPHADDWValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPHADDW(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPHADDW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPHADDW(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPHADDW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPHMINPOSUWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VPHMINPOSUW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := VPHMINPOSUW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPHSUBDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPHSUBD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPHSUBD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPHSUBD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPHSUBD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPHSUBSWValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPHSUBSW(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPHSUBSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPHSUBSW(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPHSUBSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPHSUBWValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPHSUBW(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPHSUBW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPHSUBW(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPHSUBW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPINSRBValidForms(t *testing.T) { - t.Run("form=imm8_r32_xmm_xmm", func(t *testing.T) { - if _, err := VPINSRB(operand.Imm(math.MaxInt8), reg.R10L, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m8_xmm_xmm", func(t *testing.T) { - if _, err := VPINSRB(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPINSRDValidForms(t *testing.T) { - t.Run("form=imm8_r32_xmm_xmm", func(t *testing.T) { - if _, err := VPINSRD(operand.Imm(math.MaxInt8), reg.R10L, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m32_xmm_xmm", func(t *testing.T) { - if _, err := VPINSRD(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPINSRQValidForms(t *testing.T) { - t.Run("form=imm8_r64_xmm_xmm", func(t *testing.T) { - if _, err := VPINSRQ(operand.Imm(math.MaxInt8), reg.R11, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m64_xmm_xmm", func(t *testing.T) { - if _, err := VPINSRQ(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPINSRWValidForms(t *testing.T) { - t.Run("form=imm8_r32_xmm_xmm", func(t *testing.T) { - if _, err := VPINSRW(operand.Imm(math.MaxInt8), reg.R10L, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m16_xmm_xmm", func(t *testing.T) { - if _, err := VPINSRW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMADDUBSWValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPMADDUBSW(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPMADDUBSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPMADDUBSW(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPMADDUBSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMADDWDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPMADDWD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPMADDWD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPMADDWD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPMADDWD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMASKMOVDValidForms(t *testing.T) { - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPMASKMOVD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPMASKMOVD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_xmm_m128", func(t *testing.T) { - if _, err := VPMASKMOVD(reg.X7, reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_m256", func(t *testing.T) { - if _, err := VPMASKMOVD(reg.Y15, reg.Y15, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMASKMOVQValidForms(t *testing.T) { - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPMASKMOVQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPMASKMOVQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_xmm_m128", func(t *testing.T) { - if _, err := VPMASKMOVQ(reg.X7, reg.X7, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_m256", func(t *testing.T) { - if _, err := VPMASKMOVQ(reg.Y15, reg.Y15, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMAXSBValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPMAXSB(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPMAXSB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPMAXSB(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPMAXSB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMAXSDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPMAXSD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPMAXSD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPMAXSD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPMAXSD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMAXSWValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPMAXSW(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPMAXSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPMAXSW(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPMAXSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMAXUBValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPMAXUB(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPMAXUB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPMAXUB(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPMAXUB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMAXUDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPMAXUD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPMAXUD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPMAXUD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPMAXUD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMAXUWValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPMAXUW(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPMAXUW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPMAXUW(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPMAXUW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMINSBValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPMINSB(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPMINSB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPMINSB(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPMINSB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMINSDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPMINSD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPMINSD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPMINSD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPMINSD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMINSWValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPMINSW(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPMINSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPMINSW(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPMINSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMINUBValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPMINUB(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPMINUB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPMINUB(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPMINUB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMINUDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPMINUD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPMINUD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPMINUD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPMINUD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMINUWValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPMINUW(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPMINUW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPMINUW(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPMINUW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMOVMSKBValidForms(t *testing.T) { - t.Run("form=xmm_r32", func(t *testing.T) { - if _, err := VPMOVMSKB(reg.X7, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_r32", func(t *testing.T) { - if _, err := VPMOVMSKB(reg.Y15, reg.R10L); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMOVSXBDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VPMOVSXBD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := VPMOVSXBD(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_ymm", func(t *testing.T) { - if _, err := VPMOVSXBD(reg.X7, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_ymm", func(t *testing.T) { - if _, err := VPMOVSXBD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMOVSXBQValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VPMOVSXBQ(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_xmm", func(t *testing.T) { - if _, err := VPMOVSXBQ(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_ymm", func(t *testing.T) { - if _, err := VPMOVSXBQ(reg.X7, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_ymm", func(t *testing.T) { - if _, err := VPMOVSXBQ(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMOVSXBWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VPMOVSXBW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := VPMOVSXBW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_ymm", func(t *testing.T) { - if _, err := VPMOVSXBW(reg.X7, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_ymm", func(t *testing.T) { - if _, err := VPMOVSXBW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMOVSXDQValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VPMOVSXDQ(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := VPMOVSXDQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_ymm", func(t *testing.T) { - if _, err := VPMOVSXDQ(reg.X7, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_ymm", func(t *testing.T) { - if _, err := VPMOVSXDQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMOVSXWDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VPMOVSXWD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := VPMOVSXWD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_ymm", func(t *testing.T) { - if _, err := VPMOVSXWD(reg.X7, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_ymm", func(t *testing.T) { - if _, err := VPMOVSXWD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMOVSXWQValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VPMOVSXWQ(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := VPMOVSXWQ(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_ymm", func(t *testing.T) { - if _, err := VPMOVSXWQ(reg.X7, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_ymm", func(t *testing.T) { - if _, err := VPMOVSXWQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMOVZXBDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VPMOVZXBD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := VPMOVZXBD(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_ymm", func(t *testing.T) { - if _, err := VPMOVZXBD(reg.X7, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_ymm", func(t *testing.T) { - if _, err := VPMOVZXBD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMOVZXBQValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VPMOVZXBQ(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_xmm", func(t *testing.T) { - if _, err := VPMOVZXBQ(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_ymm", func(t *testing.T) { - if _, err := VPMOVZXBQ(reg.X7, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_ymm", func(t *testing.T) { - if _, err := VPMOVZXBQ(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMOVZXBWValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VPMOVZXBW(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := VPMOVZXBW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_ymm", func(t *testing.T) { - if _, err := VPMOVZXBW(reg.X7, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_ymm", func(t *testing.T) { - if _, err := VPMOVZXBW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMOVZXDQValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VPMOVZXDQ(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := VPMOVZXDQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_ymm", func(t *testing.T) { - if _, err := VPMOVZXDQ(reg.X7, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_ymm", func(t *testing.T) { - if _, err := VPMOVZXDQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMOVZXWDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VPMOVZXWD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := VPMOVZXWD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_ymm", func(t *testing.T) { - if _, err := VPMOVZXWD(reg.X7, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_ymm", func(t *testing.T) { - if _, err := VPMOVZXWD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMOVZXWQValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VPMOVZXWQ(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := VPMOVZXWQ(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_ymm", func(t *testing.T) { - if _, err := VPMOVZXWQ(reg.X7, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_ymm", func(t *testing.T) { - if _, err := VPMOVZXWQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMULDQValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPMULDQ(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPMULDQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPMULDQ(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPMULDQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMULHRSWValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPMULHRSW(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPMULHRSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPMULHRSW(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPMULHRSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMULHUWValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPMULHUW(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPMULHUW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPMULHUW(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPMULHUW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMULHWValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPMULHW(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPMULHW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPMULHW(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPMULHW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMULLDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPMULLD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPMULLD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPMULLD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPMULLD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMULLWValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPMULLW(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPMULLW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPMULLW(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPMULLW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPMULUDQValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPMULUDQ(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPMULUDQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPMULUDQ(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPMULUDQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPORValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPOR(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPOR(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPOR(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPOR(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPSADBWValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPSADBW(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPSADBW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPSADBW(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPSADBW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPSHUFBValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPSHUFB(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPSHUFB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPSHUFB(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPSHUFB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPSHUFDValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := VPSHUFD(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := VPSHUFD(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_ymm", func(t *testing.T) { - if _, err := VPSHUFD(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m256_ymm", func(t *testing.T) { - if _, err := VPSHUFD(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPSHUFHWValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := VPSHUFHW(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := VPSHUFHW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_ymm", func(t *testing.T) { - if _, err := VPSHUFHW(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m256_ymm", func(t *testing.T) { - if _, err := VPSHUFHW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPSHUFLWValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := VPSHUFLW(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := VPSHUFLW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_ymm", func(t *testing.T) { - if _, err := VPSHUFLW(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m256_ymm", func(t *testing.T) { - if _, err := VPSHUFLW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPSIGNBValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPSIGNB(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPSIGNB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPSIGNB(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPSIGNB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPSIGNDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPSIGND(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPSIGND(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPSIGND(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPSIGND(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPSIGNWValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPSIGNW(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPSIGNW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPSIGNW(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPSIGNW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPSLLDValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := VPSLLD(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPSLLD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPSLLD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_ymm", func(t *testing.T) { - if _, err := VPSLLD(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_ymm_ymm", func(t *testing.T) { - if _, err := VPSLLD(reg.X7, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_ymm_ymm", func(t *testing.T) { - if _, err := VPSLLD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPSLLDQValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := VPSLLDQ(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_ymm", func(t *testing.T) { - if _, err := VPSLLDQ(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPSLLQValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := VPSLLQ(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPSLLQ(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPSLLQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_ymm", func(t *testing.T) { - if _, err := VPSLLQ(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_ymm_ymm", func(t *testing.T) { - if _, err := VPSLLQ(reg.X7, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_ymm_ymm", func(t *testing.T) { - if _, err := VPSLLQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPSLLVDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPSLLVD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPSLLVD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPSLLVD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPSLLVD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPSLLVQValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPSLLVQ(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPSLLVQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPSLLVQ(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPSLLVQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPSLLWValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := VPSLLW(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPSLLW(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPSLLW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_ymm", func(t *testing.T) { - if _, err := VPSLLW(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_ymm_ymm", func(t *testing.T) { - if _, err := VPSLLW(reg.X7, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_ymm_ymm", func(t *testing.T) { - if _, err := VPSLLW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPSRADValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := VPSRAD(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPSRAD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPSRAD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_ymm", func(t *testing.T) { - if _, err := VPSRAD(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_ymm_ymm", func(t *testing.T) { - if _, err := VPSRAD(reg.X7, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_ymm_ymm", func(t *testing.T) { - if _, err := VPSRAD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPSRAVDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPSRAVD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPSRAVD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPSRAVD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPSRAVD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPSRAWValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := VPSRAW(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPSRAW(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPSRAW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_ymm", func(t *testing.T) { - if _, err := VPSRAW(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_ymm_ymm", func(t *testing.T) { - if _, err := VPSRAW(reg.X7, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_ymm_ymm", func(t *testing.T) { - if _, err := VPSRAW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPSRLDValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := VPSRLD(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPSRLD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPSRLD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_ymm", func(t *testing.T) { - if _, err := VPSRLD(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_ymm_ymm", func(t *testing.T) { - if _, err := VPSRLD(reg.X7, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_ymm_ymm", func(t *testing.T) { - if _, err := VPSRLD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPSRLDQValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := VPSRLDQ(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_ymm", func(t *testing.T) { - if _, err := VPSRLDQ(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPSRLQValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := VPSRLQ(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPSRLQ(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPSRLQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_ymm", func(t *testing.T) { - if _, err := VPSRLQ(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_ymm_ymm", func(t *testing.T) { - if _, err := VPSRLQ(reg.X7, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_ymm_ymm", func(t *testing.T) { - if _, err := VPSRLQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPSRLVDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPSRLVD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPSRLVD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPSRLVD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPSRLVD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPSRLVQValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPSRLVQ(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPSRLVQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPSRLVQ(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPSRLVQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPSRLWValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := VPSRLW(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPSRLW(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPSRLW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_ymm", func(t *testing.T) { - if _, err := VPSRLW(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=xmm_ymm_ymm", func(t *testing.T) { - if _, err := VPSRLW(reg.X7, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_ymm_ymm", func(t *testing.T) { - if _, err := VPSRLW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPSUBBValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPSUBB(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPSUBB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPSUBB(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPSUBB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPSUBDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPSUBD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPSUBD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPSUBD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPSUBD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPSUBQValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPSUBQ(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPSUBQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPSUBQ(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPSUBQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPSUBSBValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPSUBSB(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPSUBSB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPSUBSB(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPSUBSB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPSUBSWValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPSUBSW(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPSUBSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPSUBSW(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPSUBSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPSUBUSBValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPSUBUSB(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPSUBUSB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPSUBUSB(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPSUBUSB(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPSUBUSWValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPSUBUSW(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPSUBUSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPSUBUSW(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPSUBUSW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPSUBWValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPSUBW(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPSUBW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPSUBW(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPSUBW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPTESTValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VPTEST(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := VPTEST(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm", func(t *testing.T) { - if _, err := VPTEST(reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm", func(t *testing.T) { - if _, err := VPTEST(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPUNPCKHBWValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPUNPCKHBW(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPUNPCKHBW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPUNPCKHBW(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPUNPCKHBW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPUNPCKHDQValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPUNPCKHDQ(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPUNPCKHDQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPUNPCKHDQ(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPUNPCKHDQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPUNPCKHQDQValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPUNPCKHQDQ(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPUNPCKHQDQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPUNPCKHQDQ(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPUNPCKHQDQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPUNPCKHWDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPUNPCKHWD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPUNPCKHWD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPUNPCKHWD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPUNPCKHWD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPUNPCKLBWValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPUNPCKLBW(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPUNPCKLBW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPUNPCKLBW(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPUNPCKLBW(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPUNPCKLDQValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPUNPCKLDQ(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPUNPCKLDQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPUNPCKLDQ(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPUNPCKLDQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPUNPCKLQDQValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPUNPCKLQDQ(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPUNPCKLQDQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPUNPCKLQDQ(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPUNPCKLQDQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPUNPCKLWDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPUNPCKLWD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPUNPCKLWD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPUNPCKLWD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPUNPCKLWD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVPXORValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VPXOR(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VPXOR(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VPXOR(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VPXOR(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVRCPPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VRCPPS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := VRCPPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm", func(t *testing.T) { - if _, err := VRCPPS(reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm", func(t *testing.T) { - if _, err := VRCPPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVRCPSSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VRCPSS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm_xmm", func(t *testing.T) { - if _, err := VRCPSS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVROUNDPDValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := VROUNDPD(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := VROUNDPD(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_ymm", func(t *testing.T) { - if _, err := VROUNDPD(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m256_ymm", func(t *testing.T) { - if _, err := VROUNDPD(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVROUNDPSValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm", func(t *testing.T) { - if _, err := VROUNDPS(operand.Imm(math.MaxInt8), reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm", func(t *testing.T) { - if _, err := VROUNDPS(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_ymm", func(t *testing.T) { - if _, err := VROUNDPS(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m256_ymm", func(t *testing.T) { - if _, err := VROUNDPS(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVROUNDSDValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm_xmm", func(t *testing.T) { - if _, err := VROUNDSD(operand.Imm(math.MaxInt8), reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m64_xmm_xmm", func(t *testing.T) { - if _, err := VROUNDSD(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVROUNDSSValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm_xmm", func(t *testing.T) { - if _, err := VROUNDSS(operand.Imm(math.MaxInt8), reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m32_xmm_xmm", func(t *testing.T) { - if _, err := VROUNDSS(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVRSQRTPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VRSQRTPS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := VRSQRTPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm", func(t *testing.T) { - if _, err := VRSQRTPS(reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm", func(t *testing.T) { - if _, err := VRSQRTPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVRSQRTSSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VRSQRTSS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm_xmm", func(t *testing.T) { - if _, err := VRSQRTSS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVSHUFPDValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm_xmm", func(t *testing.T) { - if _, err := VSHUFPD(operand.Imm(math.MaxInt8), reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm_xmm", func(t *testing.T) { - if _, err := VSHUFPD(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_ymm_ymm", func(t *testing.T) { - if _, err := VSHUFPD(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m256_ymm_ymm", func(t *testing.T) { - if _, err := VSHUFPD(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVSHUFPSValidForms(t *testing.T) { - t.Run("form=imm8_xmm_xmm_xmm", func(t *testing.T) { - if _, err := VSHUFPS(operand.Imm(math.MaxInt8), reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m128_xmm_xmm", func(t *testing.T) { - if _, err := VSHUFPS(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_ymm_ymm_ymm", func(t *testing.T) { - if _, err := VSHUFPS(operand.Imm(math.MaxInt8), reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m256_ymm_ymm", func(t *testing.T) { - if _, err := VSHUFPS(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVSQRTPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VSQRTPD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := VSQRTPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm", func(t *testing.T) { - if _, err := VSQRTPD(reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm", func(t *testing.T) { - if _, err := VSQRTPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVSQRTPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VSQRTPS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := VSQRTPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm", func(t *testing.T) { - if _, err := VSQRTPS(reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm", func(t *testing.T) { - if _, err := VSQRTPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVSQRTSDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VSQRTSD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm_xmm", func(t *testing.T) { - if _, err := VSQRTSD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVSQRTSSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VSQRTSS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm_xmm", func(t *testing.T) { - if _, err := VSQRTSS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVSTMXCSRValidForms(t *testing.T) { - t.Run("form=m32", func(t *testing.T) { - if _, err := VSTMXCSR(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestVSUBPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VSUBPD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VSUBPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VSUBPD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VSUBPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVSUBPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VSUBPS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VSUBPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VSUBPS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VSUBPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVSUBSDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VSUBSD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm_xmm", func(t *testing.T) { - if _, err := VSUBSD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVSUBSSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VSUBSS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm_xmm", func(t *testing.T) { - if _, err := VSUBSS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVTESTPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VTESTPD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := VTESTPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm", func(t *testing.T) { - if _, err := VTESTPD(reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm", func(t *testing.T) { - if _, err := VTESTPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVTESTPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VTESTPS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := VTESTPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm", func(t *testing.T) { - if _, err := VTESTPS(reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm", func(t *testing.T) { - if _, err := VTESTPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVUCOMISDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VUCOMISD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_xmm", func(t *testing.T) { - if _, err := VUCOMISD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVUCOMISSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := VUCOMISS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_xmm", func(t *testing.T) { - if _, err := VUCOMISS(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestVUNPCKHPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VUNPCKHPD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VUNPCKHPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VUNPCKHPD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VUNPCKHPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVUNPCKHPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VUNPCKHPS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VUNPCKHPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VUNPCKHPS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VUNPCKHPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVUNPCKLPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VUNPCKLPD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VUNPCKLPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VUNPCKLPD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VUNPCKLPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVUNPCKLPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VUNPCKLPS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VUNPCKLPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VUNPCKLPS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VUNPCKLPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVXORPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VXORPD(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VXORPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VXORPD(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VXORPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVXORPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm_xmm", func(t *testing.T) { - if _, err := VXORPS(reg.X7, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm_xmm", func(t *testing.T) { - if _, err := VXORPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ymm_ymm_ymm", func(t *testing.T) { - if _, err := VXORPS(reg.Y15, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m256_ymm_ymm", func(t *testing.T) { - if _, err := VXORPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.Y15, reg.Y15); err != nil { - t.Fatal(err) - } - }) -} - -func TestVZEROALLValidForms(t *testing.T) { - t.Run("form=", func(t *testing.T) { - if _, err := VZEROALL(); err != nil { - t.Fatal(err) - } - }) -} - -func TestVZEROUPPERValidForms(t *testing.T) { - t.Run("form=", func(t *testing.T) { - if _, err := VZEROUPPER(); err != nil { - t.Fatal(err) - } - }) -} - -func TestXADDBValidForms(t *testing.T) { - t.Run("form=r8_r8", func(t *testing.T) { - if _, err := XADDB(reg.CH, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := XADDB(reg.CH, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := XADDB(reg.CH, reg.R13B); err != nil { - t.Fatal(err) - } - if _, err := XADDB(reg.BL, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := XADDB(reg.BL, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := XADDB(reg.BL, reg.R13B); err != nil { - t.Fatal(err) - } - if _, err := XADDB(reg.R13B, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := XADDB(reg.R13B, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := XADDB(reg.R13B, reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r8_m8", func(t *testing.T) { - if _, err := XADDB(reg.CH, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - if _, err := XADDB(reg.BL, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - if _, err := XADDB(reg.R13B, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestXADDLValidForms(t *testing.T) { - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := XADDL(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_m32", func(t *testing.T) { - if _, err := XADDL(reg.R10L, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestXADDQValidForms(t *testing.T) { - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := XADDQ(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_m64", func(t *testing.T) { - if _, err := XADDQ(reg.R11, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestXADDWValidForms(t *testing.T) { - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := XADDW(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := XADDW(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := XADDW(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := XADDW(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_m16", func(t *testing.T) { - if _, err := XADDW(reg.CX, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - if _, err := XADDW(reg.R9W, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestXCHGBValidForms(t *testing.T) { - t.Run("form=r8_r8", func(t *testing.T) { - if _, err := XCHGB(reg.CH, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := XCHGB(reg.CH, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := XCHGB(reg.CH, reg.R13B); err != nil { - t.Fatal(err) - } - if _, err := XCHGB(reg.BL, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := XCHGB(reg.BL, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := XCHGB(reg.BL, reg.R13B); err != nil { - t.Fatal(err) - } - if _, err := XCHGB(reg.R13B, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := XCHGB(reg.R13B, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := XCHGB(reg.R13B, reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8_r8", func(t *testing.T) { - if _, err := XCHGB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := XCHGB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := XCHGB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r8_m8", func(t *testing.T) { - if _, err := XCHGB(reg.CH, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - if _, err := XCHGB(reg.BL, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - if _, err := XCHGB(reg.R13B, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestXCHGLValidForms(t *testing.T) { - t.Run("form=r32_eax", func(t *testing.T) { - if _, err := XCHGL(reg.R10L, reg.EAX); err != nil { - t.Fatal(err) - } - }) - t.Run("form=eax_r32", func(t *testing.T) { - if _, err := XCHGL(reg.EAX, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := XCHGL(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := XCHGL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_m32", func(t *testing.T) { - if _, err := XCHGL(reg.R10L, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestXCHGQValidForms(t *testing.T) { - t.Run("form=r64_rax", func(t *testing.T) { - if _, err := XCHGQ(reg.R11, reg.RAX); err != nil { - t.Fatal(err) - } - }) - t.Run("form=rax_r64", func(t *testing.T) { - if _, err := XCHGQ(reg.RAX, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := XCHGQ(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := XCHGQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_m64", func(t *testing.T) { - if _, err := XCHGQ(reg.R11, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestXCHGWValidForms(t *testing.T) { - t.Run("form=r16_ax", func(t *testing.T) { - if _, err := XCHGW(reg.CX, reg.AX); err != nil { - t.Fatal(err) - } - if _, err := XCHGW(reg.R9W, reg.AX); err != nil { - t.Fatal(err) - } - }) - t.Run("form=ax_r16", func(t *testing.T) { - if _, err := XCHGW(reg.AX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := XCHGW(reg.AX, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := XCHGW(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := XCHGW(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := XCHGW(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := XCHGW(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := XCHGW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := XCHGW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_m16", func(t *testing.T) { - if _, err := XCHGW(reg.CX, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - if _, err := XCHGW(reg.R9W, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) -} - -func TestXGETBVValidForms(t *testing.T) { - t.Run("form=", func(t *testing.T) { - if _, err := XGETBV(); err != nil { - t.Fatal(err) - } - }) -} - -func TestXLATValidForms(t *testing.T) { - t.Run("form=", func(t *testing.T) { - if _, err := XLAT(); err != nil { - t.Fatal(err) - } - }) -} - -func TestXORBValidForms(t *testing.T) { - t.Run("form=imm8_al", func(t *testing.T) { - if _, err := XORB(operand.Imm(math.MaxInt8), reg.AL); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r8", func(t *testing.T) { - if _, err := XORB(operand.Imm(math.MaxInt8), reg.CH); err != nil { - t.Fatal(err) - } - if _, err := XORB(operand.Imm(math.MaxInt8), reg.BL); err != nil { - t.Fatal(err) - } - if _, err := XORB(operand.Imm(math.MaxInt8), reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r8_r8", func(t *testing.T) { - if _, err := XORB(reg.CH, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := XORB(reg.CH, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := XORB(reg.CH, reg.R13B); err != nil { - t.Fatal(err) - } - if _, err := XORB(reg.BL, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := XORB(reg.BL, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := XORB(reg.BL, reg.R13B); err != nil { - t.Fatal(err) - } - if _, err := XORB(reg.R13B, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := XORB(reg.R13B, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := XORB(reg.R13B, reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m8_r8", func(t *testing.T) { - if _, err := XORB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.CH); err != nil { - t.Fatal(err) - } - if _, err := XORB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.BL); err != nil { - t.Fatal(err) - } - if _, err := XORB(operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}, reg.R13B); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m8", func(t *testing.T) { - if _, err := XORB(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r8_m8", func(t *testing.T) { - if _, err := XORB(reg.CH, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - if _, err := XORB(reg.BL, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - if _, err := XORB(reg.R13B, operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}); err != nil { - t.Fatal(err) - } - }) -} - -func TestXORLValidForms(t *testing.T) { - t.Run("form=imm32_eax", func(t *testing.T) { - if _, err := XORL(operand.Imm(math.MaxInt32), reg.EAX); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r32", func(t *testing.T) { - if _, err := XORL(operand.Imm(math.MaxInt8), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_r32", func(t *testing.T) { - if _, err := XORL(operand.Imm(math.MaxInt32), reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_r32", func(t *testing.T) { - if _, err := XORL(reg.R10L, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m32_r32", func(t *testing.T) { - if _, err := XORL(operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}, reg.R10L); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m32", func(t *testing.T) { - if _, err := XORL(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_m32", func(t *testing.T) { - if _, err := XORL(operand.Imm(math.MaxInt32), operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r32_m32", func(t *testing.T) { - if _, err := XORL(reg.R10L, operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}); err != nil { - t.Fatal(err) - } - }) -} - -func TestXORPDValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := XORPD(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := XORPD(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestXORPSValidForms(t *testing.T) { - t.Run("form=xmm_xmm", func(t *testing.T) { - if _, err := XORPS(reg.X7, reg.X7); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m128_xmm", func(t *testing.T) { - if _, err := XORPS(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.X7); err != nil { - t.Fatal(err) - } - }) -} - -func TestXORQValidForms(t *testing.T) { - t.Run("form=imm32_rax", func(t *testing.T) { - if _, err := XORQ(operand.Imm(math.MaxInt32), reg.RAX); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r64", func(t *testing.T) { - if _, err := XORQ(operand.Imm(math.MaxInt8), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_r64", func(t *testing.T) { - if _, err := XORQ(operand.Imm(math.MaxInt32), reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_r64", func(t *testing.T) { - if _, err := XORQ(reg.R11, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m64_r64", func(t *testing.T) { - if _, err := XORQ(operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}, reg.R11); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m64", func(t *testing.T) { - if _, err := XORQ(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm32_m64", func(t *testing.T) { - if _, err := XORQ(operand.Imm(math.MaxInt32), operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r64_m64", func(t *testing.T) { - if _, err := XORQ(reg.R11, operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}); err != nil { - t.Fatal(err) - } - }) -} - -func TestXORWValidForms(t *testing.T) { - t.Run("form=imm16_ax", func(t *testing.T) { - if _, err := XORW(operand.Imm(math.MaxInt16), reg.AX); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_r16", func(t *testing.T) { - if _, err := XORW(operand.Imm(math.MaxInt8), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := XORW(operand.Imm(math.MaxInt8), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm16_r16", func(t *testing.T) { - if _, err := XORW(operand.Imm(math.MaxInt16), reg.CX); err != nil { - t.Fatal(err) - } - if _, err := XORW(operand.Imm(math.MaxInt16), reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_r16", func(t *testing.T) { - if _, err := XORW(reg.CX, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := XORW(reg.CX, reg.R9W); err != nil { - t.Fatal(err) - } - if _, err := XORW(reg.R9W, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := XORW(reg.R9W, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=m16_r16", func(t *testing.T) { - if _, err := XORW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.CX); err != nil { - t.Fatal(err) - } - if _, err := XORW(operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}, reg.R9W); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm8_m16", func(t *testing.T) { - if _, err := XORW(operand.Imm(math.MaxInt8), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=imm16_m16", func(t *testing.T) { - if _, err := XORW(operand.Imm(math.MaxInt16), operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) - t.Run("form=r16_m16", func(t *testing.T) { - if _, err := XORW(reg.CX, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - if _, err := XORW(reg.R9W, operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}); err != nil { - t.Fatal(err) - } - }) +var ( + op1 operand.Op = operand.Imm(1) + op3 operand.Op = operand.Imm(3) + opimm2u operand.Op = operand.Imm(3) + opimm8 operand.Op = operand.Imm(math.MaxInt8) + opimm16 operand.Op = operand.Imm(math.MaxInt16) + opimm32 operand.Op = operand.Imm(math.MaxInt32) + opimm64 operand.Op = operand.Imm(math.MaxInt64) + opal operand.Op = reg.AL + opcl operand.Op = reg.CL + opax operand.Op = reg.AX + opeax operand.Op = reg.EAX + oprax operand.Op = reg.RAX + opr8 operand.Op = reg.CH + opr16 operand.Op = reg.R9W + opr32 operand.Op = reg.R10L + opr64 operand.Op = reg.R11 + opxmm0 operand.Op = reg.X0 + opxmm operand.Op = reg.X7 + opymm operand.Op = reg.Y15 + opzmm operand.Op = reg.Z31 + opk operand.Op = reg.K7 + opm operand.Op = operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2} + opm8 operand.Op = operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1} + opm16 operand.Op = operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2} + opm32 operand.Op = operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4} + opm64 operand.Op = operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8} + opm128 operand.Op = operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8} + opm256 operand.Op = operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8} + opm512 operand.Op = operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8} + opvm32x operand.Op = operand.Mem{Base: reg.R13, Index: reg.X4, Scale: 1} + opvm64x operand.Op = operand.Mem{Base: reg.R13, Index: reg.X8, Scale: 1} + opvm32y operand.Op = operand.Mem{Base: reg.R13, Index: reg.Y4, Scale: 1} + opvm64y operand.Op = operand.Mem{Base: reg.R13, Index: reg.Y8, Scale: 1} + opvm32z operand.Op = operand.Mem{Base: reg.R13, Index: reg.Z4, Scale: 1} + opvm64z operand.Op = operand.Mem{Base: reg.R13, Index: reg.Z8, Scale: 1} + oprel8 operand.Op = operand.Rel(math.MaxInt8) + oprel32 operand.Op = operand.LabelRef("lbl") +) + +func TestADCBValidFormsNoError(t *testing.T) { + if _, err := ADCB(opimm8, opal); err != nil { + t.Fatal(err) + } + if _, err := ADCB(opimm8, opm8); err != nil { + t.Fatal(err) + } + if _, err := ADCB(opimm8, opr8); err != nil { + t.Fatal(err) + } + if _, err := ADCB(opm8, opr8); err != nil { + t.Fatal(err) + } + if _, err := ADCB(opr8, opm8); err != nil { + t.Fatal(err) + } + if _, err := ADCB(opr8, opr8); err != nil { + t.Fatal(err) + } +} + +func TestADCLValidFormsNoError(t *testing.T) { + if _, err := ADCL(opimm32, opeax); err != nil { + t.Fatal(err) + } + if _, err := ADCL(opimm32, opm32); err != nil { + t.Fatal(err) + } + if _, err := ADCL(opimm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := ADCL(opimm8, opm32); err != nil { + t.Fatal(err) + } + if _, err := ADCL(opimm8, opr32); err != nil { + t.Fatal(err) + } + if _, err := ADCL(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := ADCL(opr32, opm32); err != nil { + t.Fatal(err) + } + if _, err := ADCL(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestADCQValidFormsNoError(t *testing.T) { + if _, err := ADCQ(opimm32, opm64); err != nil { + t.Fatal(err) + } + if _, err := ADCQ(opimm32, opr64); err != nil { + t.Fatal(err) + } + if _, err := ADCQ(opimm32, oprax); err != nil { + t.Fatal(err) + } + if _, err := ADCQ(opimm8, opm64); err != nil { + t.Fatal(err) + } + if _, err := ADCQ(opimm8, opr64); err != nil { + t.Fatal(err) + } + if _, err := ADCQ(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := ADCQ(opr64, opm64); err != nil { + t.Fatal(err) + } + if _, err := ADCQ(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestADCWValidFormsNoError(t *testing.T) { + if _, err := ADCW(opimm16, opax); err != nil { + t.Fatal(err) + } + if _, err := ADCW(opimm16, opm16); err != nil { + t.Fatal(err) + } + if _, err := ADCW(opimm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := ADCW(opimm8, opm16); err != nil { + t.Fatal(err) + } + if _, err := ADCW(opimm8, opr16); err != nil { + t.Fatal(err) + } + if _, err := ADCW(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := ADCW(opr16, opm16); err != nil { + t.Fatal(err) + } + if _, err := ADCW(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestADCXLValidFormsNoError(t *testing.T) { + if _, err := ADCXL(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := ADCXL(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestADCXQValidFormsNoError(t *testing.T) { + if _, err := ADCXQ(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := ADCXQ(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestADDBValidFormsNoError(t *testing.T) { + if _, err := ADDB(opimm8, opal); err != nil { + t.Fatal(err) + } + if _, err := ADDB(opimm8, opm8); err != nil { + t.Fatal(err) + } + if _, err := ADDB(opimm8, opr8); err != nil { + t.Fatal(err) + } + if _, err := ADDB(opm8, opr8); err != nil { + t.Fatal(err) + } + if _, err := ADDB(opr8, opm8); err != nil { + t.Fatal(err) + } + if _, err := ADDB(opr8, opr8); err != nil { + t.Fatal(err) + } +} + +func TestADDLValidFormsNoError(t *testing.T) { + if _, err := ADDL(opimm32, opeax); err != nil { + t.Fatal(err) + } + if _, err := ADDL(opimm32, opm32); err != nil { + t.Fatal(err) + } + if _, err := ADDL(opimm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := ADDL(opimm8, opm32); err != nil { + t.Fatal(err) + } + if _, err := ADDL(opimm8, opr32); err != nil { + t.Fatal(err) + } + if _, err := ADDL(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := ADDL(opr32, opm32); err != nil { + t.Fatal(err) + } + if _, err := ADDL(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestADDPDValidFormsNoError(t *testing.T) { + if _, err := ADDPD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := ADDPD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestADDPSValidFormsNoError(t *testing.T) { + if _, err := ADDPS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := ADDPS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestADDQValidFormsNoError(t *testing.T) { + if _, err := ADDQ(opimm32, opm64); err != nil { + t.Fatal(err) + } + if _, err := ADDQ(opimm32, opr64); err != nil { + t.Fatal(err) + } + if _, err := ADDQ(opimm32, oprax); err != nil { + t.Fatal(err) + } + if _, err := ADDQ(opimm8, opm64); err != nil { + t.Fatal(err) + } + if _, err := ADDQ(opimm8, opr64); err != nil { + t.Fatal(err) + } + if _, err := ADDQ(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := ADDQ(opr64, opm64); err != nil { + t.Fatal(err) + } + if _, err := ADDQ(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestADDSDValidFormsNoError(t *testing.T) { + if _, err := ADDSD(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := ADDSD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestADDSSValidFormsNoError(t *testing.T) { + if _, err := ADDSS(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := ADDSS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestADDSUBPDValidFormsNoError(t *testing.T) { + if _, err := ADDSUBPD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := ADDSUBPD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestADDSUBPSValidFormsNoError(t *testing.T) { + if _, err := ADDSUBPS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := ADDSUBPS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestADDWValidFormsNoError(t *testing.T) { + if _, err := ADDW(opimm16, opax); err != nil { + t.Fatal(err) + } + if _, err := ADDW(opimm16, opm16); err != nil { + t.Fatal(err) + } + if _, err := ADDW(opimm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := ADDW(opimm8, opm16); err != nil { + t.Fatal(err) + } + if _, err := ADDW(opimm8, opr16); err != nil { + t.Fatal(err) + } + if _, err := ADDW(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := ADDW(opr16, opm16); err != nil { + t.Fatal(err) + } + if _, err := ADDW(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestADOXLValidFormsNoError(t *testing.T) { + if _, err := ADOXL(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := ADOXL(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestADOXQValidFormsNoError(t *testing.T) { + if _, err := ADOXQ(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := ADOXQ(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestAESDECValidFormsNoError(t *testing.T) { + if _, err := AESDEC(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := AESDEC(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestAESDECLASTValidFormsNoError(t *testing.T) { + if _, err := AESDECLAST(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := AESDECLAST(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestAESENCValidFormsNoError(t *testing.T) { + if _, err := AESENC(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := AESENC(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestAESENCLASTValidFormsNoError(t *testing.T) { + if _, err := AESENCLAST(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := AESENCLAST(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestAESIMCValidFormsNoError(t *testing.T) { + if _, err := AESIMC(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := AESIMC(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestAESKEYGENASSISTValidFormsNoError(t *testing.T) { + if _, err := AESKEYGENASSIST(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := AESKEYGENASSIST(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestANDBValidFormsNoError(t *testing.T) { + if _, err := ANDB(opimm8, opal); err != nil { + t.Fatal(err) + } + if _, err := ANDB(opimm8, opm8); err != nil { + t.Fatal(err) + } + if _, err := ANDB(opimm8, opr8); err != nil { + t.Fatal(err) + } + if _, err := ANDB(opm8, opr8); err != nil { + t.Fatal(err) + } + if _, err := ANDB(opr8, opm8); err != nil { + t.Fatal(err) + } + if _, err := ANDB(opr8, opr8); err != nil { + t.Fatal(err) + } +} + +func TestANDLValidFormsNoError(t *testing.T) { + if _, err := ANDL(opimm32, opeax); err != nil { + t.Fatal(err) + } + if _, err := ANDL(opimm32, opm32); err != nil { + t.Fatal(err) + } + if _, err := ANDL(opimm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := ANDL(opimm8, opm32); err != nil { + t.Fatal(err) + } + if _, err := ANDL(opimm8, opr32); err != nil { + t.Fatal(err) + } + if _, err := ANDL(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := ANDL(opr32, opm32); err != nil { + t.Fatal(err) + } + if _, err := ANDL(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestANDNLValidFormsNoError(t *testing.T) { + if _, err := ANDNL(opm32, opr32, opr32); err != nil { + t.Fatal(err) + } + if _, err := ANDNL(opr32, opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestANDNPDValidFormsNoError(t *testing.T) { + if _, err := ANDNPD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := ANDNPD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestANDNPSValidFormsNoError(t *testing.T) { + if _, err := ANDNPS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := ANDNPS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestANDNQValidFormsNoError(t *testing.T) { + if _, err := ANDNQ(opm64, opr64, opr64); err != nil { + t.Fatal(err) + } + if _, err := ANDNQ(opr64, opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestANDPDValidFormsNoError(t *testing.T) { + if _, err := ANDPD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := ANDPD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestANDPSValidFormsNoError(t *testing.T) { + if _, err := ANDPS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := ANDPS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestANDQValidFormsNoError(t *testing.T) { + if _, err := ANDQ(opimm32, opm64); err != nil { + t.Fatal(err) + } + if _, err := ANDQ(opimm32, opr64); err != nil { + t.Fatal(err) + } + if _, err := ANDQ(opimm32, oprax); err != nil { + t.Fatal(err) + } + if _, err := ANDQ(opimm8, opm64); err != nil { + t.Fatal(err) + } + if _, err := ANDQ(opimm8, opr64); err != nil { + t.Fatal(err) + } + if _, err := ANDQ(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := ANDQ(opr64, opm64); err != nil { + t.Fatal(err) + } + if _, err := ANDQ(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestANDWValidFormsNoError(t *testing.T) { + if _, err := ANDW(opimm16, opax); err != nil { + t.Fatal(err) + } + if _, err := ANDW(opimm16, opm16); err != nil { + t.Fatal(err) + } + if _, err := ANDW(opimm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := ANDW(opimm8, opm16); err != nil { + t.Fatal(err) + } + if _, err := ANDW(opimm8, opr16); err != nil { + t.Fatal(err) + } + if _, err := ANDW(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := ANDW(opr16, opm16); err != nil { + t.Fatal(err) + } + if _, err := ANDW(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestBEXTRLValidFormsNoError(t *testing.T) { + if _, err := BEXTRL(opr32, opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := BEXTRL(opr32, opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestBEXTRQValidFormsNoError(t *testing.T) { + if _, err := BEXTRQ(opr64, opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := BEXTRQ(opr64, opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestBLENDPDValidFormsNoError(t *testing.T) { + if _, err := BLENDPD(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := BLENDPD(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestBLENDPSValidFormsNoError(t *testing.T) { + if _, err := BLENDPS(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := BLENDPS(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestBLENDVPDValidFormsNoError(t *testing.T) { + if _, err := BLENDVPD(opxmm0, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := BLENDVPD(opxmm0, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestBLENDVPSValidFormsNoError(t *testing.T) { + if _, err := BLENDVPS(opxmm0, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := BLENDVPS(opxmm0, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestBLSILValidFormsNoError(t *testing.T) { + if _, err := BLSIL(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := BLSIL(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestBLSIQValidFormsNoError(t *testing.T) { + if _, err := BLSIQ(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := BLSIQ(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestBLSMSKLValidFormsNoError(t *testing.T) { + if _, err := BLSMSKL(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := BLSMSKL(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestBLSMSKQValidFormsNoError(t *testing.T) { + if _, err := BLSMSKQ(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := BLSMSKQ(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestBLSRLValidFormsNoError(t *testing.T) { + if _, err := BLSRL(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := BLSRL(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestBLSRQValidFormsNoError(t *testing.T) { + if _, err := BLSRQ(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := BLSRQ(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestBSFLValidFormsNoError(t *testing.T) { + if _, err := BSFL(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := BSFL(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestBSFQValidFormsNoError(t *testing.T) { + if _, err := BSFQ(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := BSFQ(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestBSFWValidFormsNoError(t *testing.T) { + if _, err := BSFW(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := BSFW(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestBSRLValidFormsNoError(t *testing.T) { + if _, err := BSRL(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := BSRL(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestBSRQValidFormsNoError(t *testing.T) { + if _, err := BSRQ(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := BSRQ(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestBSRWValidFormsNoError(t *testing.T) { + if _, err := BSRW(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := BSRW(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestBSWAPLValidFormsNoError(t *testing.T) { + if _, err := BSWAPL(opr32); err != nil { + t.Fatal(err) + } +} + +func TestBSWAPQValidFormsNoError(t *testing.T) { + if _, err := BSWAPQ(opr64); err != nil { + t.Fatal(err) + } +} + +func TestBTCLValidFormsNoError(t *testing.T) { + if _, err := BTCL(opimm8, opm32); err != nil { + t.Fatal(err) + } + if _, err := BTCL(opimm8, opr32); err != nil { + t.Fatal(err) + } + if _, err := BTCL(opr32, opm32); err != nil { + t.Fatal(err) + } + if _, err := BTCL(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestBTCQValidFormsNoError(t *testing.T) { + if _, err := BTCQ(opimm8, opm64); err != nil { + t.Fatal(err) + } + if _, err := BTCQ(opimm8, opr64); err != nil { + t.Fatal(err) + } + if _, err := BTCQ(opr64, opm64); err != nil { + t.Fatal(err) + } + if _, err := BTCQ(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestBTCWValidFormsNoError(t *testing.T) { + if _, err := BTCW(opimm8, opm16); err != nil { + t.Fatal(err) + } + if _, err := BTCW(opimm8, opr16); err != nil { + t.Fatal(err) + } + if _, err := BTCW(opr16, opm16); err != nil { + t.Fatal(err) + } + if _, err := BTCW(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestBTLValidFormsNoError(t *testing.T) { + if _, err := BTL(opimm8, opm32); err != nil { + t.Fatal(err) + } + if _, err := BTL(opimm8, opr32); err != nil { + t.Fatal(err) + } + if _, err := BTL(opr32, opm32); err != nil { + t.Fatal(err) + } + if _, err := BTL(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestBTQValidFormsNoError(t *testing.T) { + if _, err := BTQ(opimm8, opm64); err != nil { + t.Fatal(err) + } + if _, err := BTQ(opimm8, opr64); err != nil { + t.Fatal(err) + } + if _, err := BTQ(opr64, opm64); err != nil { + t.Fatal(err) + } + if _, err := BTQ(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestBTRLValidFormsNoError(t *testing.T) { + if _, err := BTRL(opimm8, opm32); err != nil { + t.Fatal(err) + } + if _, err := BTRL(opimm8, opr32); err != nil { + t.Fatal(err) + } + if _, err := BTRL(opr32, opm32); err != nil { + t.Fatal(err) + } + if _, err := BTRL(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestBTRQValidFormsNoError(t *testing.T) { + if _, err := BTRQ(opimm8, opm64); err != nil { + t.Fatal(err) + } + if _, err := BTRQ(opimm8, opr64); err != nil { + t.Fatal(err) + } + if _, err := BTRQ(opr64, opm64); err != nil { + t.Fatal(err) + } + if _, err := BTRQ(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestBTRWValidFormsNoError(t *testing.T) { + if _, err := BTRW(opimm8, opm16); err != nil { + t.Fatal(err) + } + if _, err := BTRW(opimm8, opr16); err != nil { + t.Fatal(err) + } + if _, err := BTRW(opr16, opm16); err != nil { + t.Fatal(err) + } + if _, err := BTRW(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestBTSLValidFormsNoError(t *testing.T) { + if _, err := BTSL(opimm8, opm32); err != nil { + t.Fatal(err) + } + if _, err := BTSL(opimm8, opr32); err != nil { + t.Fatal(err) + } + if _, err := BTSL(opr32, opm32); err != nil { + t.Fatal(err) + } + if _, err := BTSL(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestBTSQValidFormsNoError(t *testing.T) { + if _, err := BTSQ(opimm8, opm64); err != nil { + t.Fatal(err) + } + if _, err := BTSQ(opimm8, opr64); err != nil { + t.Fatal(err) + } + if _, err := BTSQ(opr64, opm64); err != nil { + t.Fatal(err) + } + if _, err := BTSQ(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestBTSWValidFormsNoError(t *testing.T) { + if _, err := BTSW(opimm8, opm16); err != nil { + t.Fatal(err) + } + if _, err := BTSW(opimm8, opr16); err != nil { + t.Fatal(err) + } + if _, err := BTSW(opr16, opm16); err != nil { + t.Fatal(err) + } + if _, err := BTSW(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestBTWValidFormsNoError(t *testing.T) { + if _, err := BTW(opimm8, opm16); err != nil { + t.Fatal(err) + } + if _, err := BTW(opimm8, opr16); err != nil { + t.Fatal(err) + } + if _, err := BTW(opr16, opm16); err != nil { + t.Fatal(err) + } + if _, err := BTW(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestBZHILValidFormsNoError(t *testing.T) { + if _, err := BZHIL(opr32, opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := BZHIL(opr32, opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestBZHIQValidFormsNoError(t *testing.T) { + if _, err := BZHIQ(opr64, opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := BZHIQ(opr64, opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestCALLValidFormsNoError(t *testing.T) { + if _, err := CALL(oprel32); err != nil { + t.Fatal(err) + } +} + +func TestCBWValidFormsNoError(t *testing.T) { + if _, err := CBW(); err != nil { + t.Fatal(err) + } +} + +func TestCDQValidFormsNoError(t *testing.T) { + if _, err := CDQ(); err != nil { + t.Fatal(err) + } +} + +func TestCDQEValidFormsNoError(t *testing.T) { + if _, err := CDQE(); err != nil { + t.Fatal(err) + } +} + +func TestCLCValidFormsNoError(t *testing.T) { + if _, err := CLC(); err != nil { + t.Fatal(err) + } +} + +func TestCLDValidFormsNoError(t *testing.T) { + if _, err := CLD(); err != nil { + t.Fatal(err) + } +} + +func TestCLFLUSHValidFormsNoError(t *testing.T) { + if _, err := CLFLUSH(opm8); err != nil { + t.Fatal(err) + } +} + +func TestCLFLUSHOPTValidFormsNoError(t *testing.T) { + if _, err := CLFLUSHOPT(opm8); err != nil { + t.Fatal(err) + } +} + +func TestCMCValidFormsNoError(t *testing.T) { + if _, err := CMC(); err != nil { + t.Fatal(err) + } +} + +func TestCMOVLCCValidFormsNoError(t *testing.T) { + if _, err := CMOVLCC(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := CMOVLCC(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestCMOVLCSValidFormsNoError(t *testing.T) { + if _, err := CMOVLCS(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := CMOVLCS(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestCMOVLEQValidFormsNoError(t *testing.T) { + if _, err := CMOVLEQ(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := CMOVLEQ(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestCMOVLGEValidFormsNoError(t *testing.T) { + if _, err := CMOVLGE(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := CMOVLGE(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestCMOVLGTValidFormsNoError(t *testing.T) { + if _, err := CMOVLGT(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := CMOVLGT(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestCMOVLHIValidFormsNoError(t *testing.T) { + if _, err := CMOVLHI(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := CMOVLHI(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestCMOVLLEValidFormsNoError(t *testing.T) { + if _, err := CMOVLLE(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := CMOVLLE(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestCMOVLLSValidFormsNoError(t *testing.T) { + if _, err := CMOVLLS(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := CMOVLLS(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestCMOVLLTValidFormsNoError(t *testing.T) { + if _, err := CMOVLLT(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := CMOVLLT(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestCMOVLMIValidFormsNoError(t *testing.T) { + if _, err := CMOVLMI(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := CMOVLMI(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestCMOVLNEValidFormsNoError(t *testing.T) { + if _, err := CMOVLNE(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := CMOVLNE(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestCMOVLOCValidFormsNoError(t *testing.T) { + if _, err := CMOVLOC(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := CMOVLOC(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestCMOVLOSValidFormsNoError(t *testing.T) { + if _, err := CMOVLOS(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := CMOVLOS(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestCMOVLPCValidFormsNoError(t *testing.T) { + if _, err := CMOVLPC(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := CMOVLPC(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestCMOVLPLValidFormsNoError(t *testing.T) { + if _, err := CMOVLPL(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := CMOVLPL(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestCMOVLPSValidFormsNoError(t *testing.T) { + if _, err := CMOVLPS(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := CMOVLPS(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestCMOVQCCValidFormsNoError(t *testing.T) { + if _, err := CMOVQCC(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := CMOVQCC(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestCMOVQCSValidFormsNoError(t *testing.T) { + if _, err := CMOVQCS(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := CMOVQCS(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestCMOVQEQValidFormsNoError(t *testing.T) { + if _, err := CMOVQEQ(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := CMOVQEQ(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestCMOVQGEValidFormsNoError(t *testing.T) { + if _, err := CMOVQGE(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := CMOVQGE(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestCMOVQGTValidFormsNoError(t *testing.T) { + if _, err := CMOVQGT(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := CMOVQGT(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestCMOVQHIValidFormsNoError(t *testing.T) { + if _, err := CMOVQHI(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := CMOVQHI(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestCMOVQLEValidFormsNoError(t *testing.T) { + if _, err := CMOVQLE(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := CMOVQLE(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestCMOVQLSValidFormsNoError(t *testing.T) { + if _, err := CMOVQLS(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := CMOVQLS(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestCMOVQLTValidFormsNoError(t *testing.T) { + if _, err := CMOVQLT(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := CMOVQLT(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestCMOVQMIValidFormsNoError(t *testing.T) { + if _, err := CMOVQMI(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := CMOVQMI(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestCMOVQNEValidFormsNoError(t *testing.T) { + if _, err := CMOVQNE(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := CMOVQNE(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestCMOVQOCValidFormsNoError(t *testing.T) { + if _, err := CMOVQOC(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := CMOVQOC(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestCMOVQOSValidFormsNoError(t *testing.T) { + if _, err := CMOVQOS(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := CMOVQOS(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestCMOVQPCValidFormsNoError(t *testing.T) { + if _, err := CMOVQPC(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := CMOVQPC(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestCMOVQPLValidFormsNoError(t *testing.T) { + if _, err := CMOVQPL(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := CMOVQPL(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestCMOVQPSValidFormsNoError(t *testing.T) { + if _, err := CMOVQPS(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := CMOVQPS(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestCMOVWCCValidFormsNoError(t *testing.T) { + if _, err := CMOVWCC(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := CMOVWCC(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestCMOVWCSValidFormsNoError(t *testing.T) { + if _, err := CMOVWCS(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := CMOVWCS(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestCMOVWEQValidFormsNoError(t *testing.T) { + if _, err := CMOVWEQ(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := CMOVWEQ(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestCMOVWGEValidFormsNoError(t *testing.T) { + if _, err := CMOVWGE(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := CMOVWGE(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestCMOVWGTValidFormsNoError(t *testing.T) { + if _, err := CMOVWGT(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := CMOVWGT(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestCMOVWHIValidFormsNoError(t *testing.T) { + if _, err := CMOVWHI(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := CMOVWHI(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestCMOVWLEValidFormsNoError(t *testing.T) { + if _, err := CMOVWLE(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := CMOVWLE(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestCMOVWLSValidFormsNoError(t *testing.T) { + if _, err := CMOVWLS(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := CMOVWLS(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestCMOVWLTValidFormsNoError(t *testing.T) { + if _, err := CMOVWLT(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := CMOVWLT(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestCMOVWMIValidFormsNoError(t *testing.T) { + if _, err := CMOVWMI(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := CMOVWMI(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestCMOVWNEValidFormsNoError(t *testing.T) { + if _, err := CMOVWNE(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := CMOVWNE(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestCMOVWOCValidFormsNoError(t *testing.T) { + if _, err := CMOVWOC(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := CMOVWOC(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestCMOVWOSValidFormsNoError(t *testing.T) { + if _, err := CMOVWOS(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := CMOVWOS(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestCMOVWPCValidFormsNoError(t *testing.T) { + if _, err := CMOVWPC(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := CMOVWPC(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestCMOVWPLValidFormsNoError(t *testing.T) { + if _, err := CMOVWPL(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := CMOVWPL(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestCMOVWPSValidFormsNoError(t *testing.T) { + if _, err := CMOVWPS(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := CMOVWPS(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestCMPBValidFormsNoError(t *testing.T) { + if _, err := CMPB(opal, opimm8); err != nil { + t.Fatal(err) + } + if _, err := CMPB(opm8, opimm8); err != nil { + t.Fatal(err) + } + if _, err := CMPB(opm8, opr8); err != nil { + t.Fatal(err) + } + if _, err := CMPB(opr8, opimm8); err != nil { + t.Fatal(err) + } + if _, err := CMPB(opr8, opm8); err != nil { + t.Fatal(err) + } + if _, err := CMPB(opr8, opr8); err != nil { + t.Fatal(err) + } +} + +func TestCMPLValidFormsNoError(t *testing.T) { + if _, err := CMPL(opeax, opimm32); err != nil { + t.Fatal(err) + } + if _, err := CMPL(opm32, opimm32); err != nil { + t.Fatal(err) + } + if _, err := CMPL(opm32, opimm8); err != nil { + t.Fatal(err) + } + if _, err := CMPL(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := CMPL(opr32, opimm32); err != nil { + t.Fatal(err) + } + if _, err := CMPL(opr32, opimm8); err != nil { + t.Fatal(err) + } + if _, err := CMPL(opr32, opm32); err != nil { + t.Fatal(err) + } + if _, err := CMPL(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestCMPPDValidFormsNoError(t *testing.T) { + if _, err := CMPPD(opm128, opxmm, opimm8); err != nil { + t.Fatal(err) + } + if _, err := CMPPD(opxmm, opxmm, opimm8); err != nil { + t.Fatal(err) + } +} + +func TestCMPPSValidFormsNoError(t *testing.T) { + if _, err := CMPPS(opm128, opxmm, opimm8); err != nil { + t.Fatal(err) + } + if _, err := CMPPS(opxmm, opxmm, opimm8); err != nil { + t.Fatal(err) + } +} + +func TestCMPQValidFormsNoError(t *testing.T) { + if _, err := CMPQ(opm64, opimm32); err != nil { + t.Fatal(err) + } + if _, err := CMPQ(opm64, opimm8); err != nil { + t.Fatal(err) + } + if _, err := CMPQ(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := CMPQ(opr64, opimm32); err != nil { + t.Fatal(err) + } + if _, err := CMPQ(opr64, opimm8); err != nil { + t.Fatal(err) + } + if _, err := CMPQ(opr64, opm64); err != nil { + t.Fatal(err) + } + if _, err := CMPQ(opr64, opr64); err != nil { + t.Fatal(err) + } + if _, err := CMPQ(oprax, opimm32); err != nil { + t.Fatal(err) + } +} + +func TestCMPSDValidFormsNoError(t *testing.T) { + if _, err := CMPSD(opm64, opxmm, opimm8); err != nil { + t.Fatal(err) + } + if _, err := CMPSD(opxmm, opxmm, opimm8); err != nil { + t.Fatal(err) + } +} + +func TestCMPSSValidFormsNoError(t *testing.T) { + if _, err := CMPSS(opm32, opxmm, opimm8); err != nil { + t.Fatal(err) + } + if _, err := CMPSS(opxmm, opxmm, opimm8); err != nil { + t.Fatal(err) + } +} + +func TestCMPWValidFormsNoError(t *testing.T) { + if _, err := CMPW(opax, opimm16); err != nil { + t.Fatal(err) + } + if _, err := CMPW(opm16, opimm16); err != nil { + t.Fatal(err) + } + if _, err := CMPW(opm16, opimm8); err != nil { + t.Fatal(err) + } + if _, err := CMPW(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := CMPW(opr16, opimm16); err != nil { + t.Fatal(err) + } + if _, err := CMPW(opr16, opimm8); err != nil { + t.Fatal(err) + } + if _, err := CMPW(opr16, opm16); err != nil { + t.Fatal(err) + } + if _, err := CMPW(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestCMPXCHG16BValidFormsNoError(t *testing.T) { + if _, err := CMPXCHG16B(opm128); err != nil { + t.Fatal(err) + } +} + +func TestCMPXCHG8BValidFormsNoError(t *testing.T) { + if _, err := CMPXCHG8B(opm64); err != nil { + t.Fatal(err) + } +} + +func TestCMPXCHGBValidFormsNoError(t *testing.T) { + if _, err := CMPXCHGB(opr8, opm8); err != nil { + t.Fatal(err) + } + if _, err := CMPXCHGB(opr8, opr8); err != nil { + t.Fatal(err) + } +} + +func TestCMPXCHGLValidFormsNoError(t *testing.T) { + if _, err := CMPXCHGL(opr32, opm32); err != nil { + t.Fatal(err) + } + if _, err := CMPXCHGL(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestCMPXCHGQValidFormsNoError(t *testing.T) { + if _, err := CMPXCHGQ(opr64, opm64); err != nil { + t.Fatal(err) + } + if _, err := CMPXCHGQ(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestCMPXCHGWValidFormsNoError(t *testing.T) { + if _, err := CMPXCHGW(opr16, opm16); err != nil { + t.Fatal(err) + } + if _, err := CMPXCHGW(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestCOMISDValidFormsNoError(t *testing.T) { + if _, err := COMISD(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := COMISD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestCOMISSValidFormsNoError(t *testing.T) { + if _, err := COMISS(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := COMISS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestCPUIDValidFormsNoError(t *testing.T) { + if _, err := CPUID(); err != nil { + t.Fatal(err) + } +} + +func TestCQOValidFormsNoError(t *testing.T) { + if _, err := CQO(); err != nil { + t.Fatal(err) + } +} + +func TestCRC32BValidFormsNoError(t *testing.T) { + if _, err := CRC32B(opm8, opr32); err != nil { + t.Fatal(err) + } + if _, err := CRC32B(opm8, opr64); err != nil { + t.Fatal(err) + } + if _, err := CRC32B(opr8, opr32); err != nil { + t.Fatal(err) + } + if _, err := CRC32B(opr8, opr64); err != nil { + t.Fatal(err) + } +} + +func TestCRC32LValidFormsNoError(t *testing.T) { + if _, err := CRC32L(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := CRC32L(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestCRC32QValidFormsNoError(t *testing.T) { + if _, err := CRC32Q(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := CRC32Q(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestCRC32WValidFormsNoError(t *testing.T) { + if _, err := CRC32W(opm16, opr32); err != nil { + t.Fatal(err) + } + if _, err := CRC32W(opr16, opr32); err != nil { + t.Fatal(err) + } +} + +func TestCVTPD2PLValidFormsNoError(t *testing.T) { + if _, err := CVTPD2PL(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := CVTPD2PL(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestCVTPD2PSValidFormsNoError(t *testing.T) { + if _, err := CVTPD2PS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := CVTPD2PS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestCVTPL2PDValidFormsNoError(t *testing.T) { + if _, err := CVTPL2PD(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := CVTPL2PD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestCVTPL2PSValidFormsNoError(t *testing.T) { + if _, err := CVTPL2PS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := CVTPL2PS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestCVTPS2PDValidFormsNoError(t *testing.T) { + if _, err := CVTPS2PD(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := CVTPS2PD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestCVTPS2PLValidFormsNoError(t *testing.T) { + if _, err := CVTPS2PL(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := CVTPS2PL(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestCVTSD2SLValidFormsNoError(t *testing.T) { + if _, err := CVTSD2SL(opm64, opr32); err != nil { + t.Fatal(err) + } + if _, err := CVTSD2SL(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := CVTSD2SL(opxmm, opr32); err != nil { + t.Fatal(err) + } + if _, err := CVTSD2SL(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestCVTSD2SSValidFormsNoError(t *testing.T) { + if _, err := CVTSD2SS(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := CVTSD2SS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestCVTSL2SDValidFormsNoError(t *testing.T) { + if _, err := CVTSL2SD(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := CVTSL2SD(opr32, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestCVTSL2SSValidFormsNoError(t *testing.T) { + if _, err := CVTSL2SS(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := CVTSL2SS(opr32, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestCVTSQ2SDValidFormsNoError(t *testing.T) { + if _, err := CVTSQ2SD(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := CVTSQ2SD(opr64, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestCVTSQ2SSValidFormsNoError(t *testing.T) { + if _, err := CVTSQ2SS(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := CVTSQ2SS(opr64, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestCVTSS2SDValidFormsNoError(t *testing.T) { + if _, err := CVTSS2SD(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := CVTSS2SD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestCVTSS2SLValidFormsNoError(t *testing.T) { + if _, err := CVTSS2SL(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := CVTSS2SL(opm32, opr64); err != nil { + t.Fatal(err) + } + if _, err := CVTSS2SL(opxmm, opr32); err != nil { + t.Fatal(err) + } + if _, err := CVTSS2SL(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestCVTTPD2PLValidFormsNoError(t *testing.T) { + if _, err := CVTTPD2PL(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := CVTTPD2PL(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestCVTTPS2PLValidFormsNoError(t *testing.T) { + if _, err := CVTTPS2PL(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := CVTTPS2PL(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestCVTTSD2SLValidFormsNoError(t *testing.T) { + if _, err := CVTTSD2SL(opm64, opr32); err != nil { + t.Fatal(err) + } + if _, err := CVTTSD2SL(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestCVTTSD2SQValidFormsNoError(t *testing.T) { + if _, err := CVTTSD2SQ(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := CVTTSD2SQ(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestCVTTSS2SLValidFormsNoError(t *testing.T) { + if _, err := CVTTSS2SL(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := CVTTSS2SL(opm32, opr64); err != nil { + t.Fatal(err) + } + if _, err := CVTTSS2SL(opxmm, opr32); err != nil { + t.Fatal(err) + } + if _, err := CVTTSS2SL(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestCWDValidFormsNoError(t *testing.T) { + if _, err := CWD(); err != nil { + t.Fatal(err) + } +} + +func TestCWDEValidFormsNoError(t *testing.T) { + if _, err := CWDE(); err != nil { + t.Fatal(err) + } +} + +func TestDECBValidFormsNoError(t *testing.T) { + if _, err := DECB(opm8); err != nil { + t.Fatal(err) + } + if _, err := DECB(opr8); err != nil { + t.Fatal(err) + } +} + +func TestDECLValidFormsNoError(t *testing.T) { + if _, err := DECL(opm32); err != nil { + t.Fatal(err) + } + if _, err := DECL(opr32); err != nil { + t.Fatal(err) + } +} + +func TestDECQValidFormsNoError(t *testing.T) { + if _, err := DECQ(opm64); err != nil { + t.Fatal(err) + } + if _, err := DECQ(opr64); err != nil { + t.Fatal(err) + } +} + +func TestDECWValidFormsNoError(t *testing.T) { + if _, err := DECW(opm16); err != nil { + t.Fatal(err) + } + if _, err := DECW(opr16); err != nil { + t.Fatal(err) + } +} + +func TestDIVBValidFormsNoError(t *testing.T) { + if _, err := DIVB(opm8); err != nil { + t.Fatal(err) + } + if _, err := DIVB(opr8); err != nil { + t.Fatal(err) + } +} + +func TestDIVLValidFormsNoError(t *testing.T) { + if _, err := DIVL(opm32); err != nil { + t.Fatal(err) + } + if _, err := DIVL(opr32); err != nil { + t.Fatal(err) + } +} + +func TestDIVPDValidFormsNoError(t *testing.T) { + if _, err := DIVPD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := DIVPD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestDIVPSValidFormsNoError(t *testing.T) { + if _, err := DIVPS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := DIVPS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestDIVQValidFormsNoError(t *testing.T) { + if _, err := DIVQ(opm64); err != nil { + t.Fatal(err) + } + if _, err := DIVQ(opr64); err != nil { + t.Fatal(err) + } +} + +func TestDIVSDValidFormsNoError(t *testing.T) { + if _, err := DIVSD(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := DIVSD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestDIVSSValidFormsNoError(t *testing.T) { + if _, err := DIVSS(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := DIVSS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestDIVWValidFormsNoError(t *testing.T) { + if _, err := DIVW(opm16); err != nil { + t.Fatal(err) + } + if _, err := DIVW(opr16); err != nil { + t.Fatal(err) + } +} + +func TestDPPDValidFormsNoError(t *testing.T) { + if _, err := DPPD(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := DPPD(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestDPPSValidFormsNoError(t *testing.T) { + if _, err := DPPS(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := DPPS(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestEXTRACTPSValidFormsNoError(t *testing.T) { + if _, err := EXTRACTPS(opimm2u, opxmm, opm32); err != nil { + t.Fatal(err) + } + if _, err := EXTRACTPS(opimm2u, opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestHADDPDValidFormsNoError(t *testing.T) { + if _, err := HADDPD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := HADDPD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestHADDPSValidFormsNoError(t *testing.T) { + if _, err := HADDPS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := HADDPS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestHSUBPDValidFormsNoError(t *testing.T) { + if _, err := HSUBPD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := HSUBPD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestHSUBPSValidFormsNoError(t *testing.T) { + if _, err := HSUBPS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := HSUBPS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestIDIVBValidFormsNoError(t *testing.T) { + if _, err := IDIVB(opm8); err != nil { + t.Fatal(err) + } + if _, err := IDIVB(opr8); err != nil { + t.Fatal(err) + } +} + +func TestIDIVLValidFormsNoError(t *testing.T) { + if _, err := IDIVL(opm32); err != nil { + t.Fatal(err) + } + if _, err := IDIVL(opr32); err != nil { + t.Fatal(err) + } +} + +func TestIDIVQValidFormsNoError(t *testing.T) { + if _, err := IDIVQ(opm64); err != nil { + t.Fatal(err) + } + if _, err := IDIVQ(opr64); err != nil { + t.Fatal(err) + } +} + +func TestIDIVWValidFormsNoError(t *testing.T) { + if _, err := IDIVW(opm16); err != nil { + t.Fatal(err) + } + if _, err := IDIVW(opr16); err != nil { + t.Fatal(err) + } +} + +func TestIMUL3LValidFormsNoError(t *testing.T) { + if _, err := IMUL3L(opimm32, opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := IMUL3L(opimm32, opr32, opr32); err != nil { + t.Fatal(err) + } + if _, err := IMUL3L(opimm8, opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := IMUL3L(opimm8, opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestIMUL3QValidFormsNoError(t *testing.T) { + if _, err := IMUL3Q(opimm32, opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := IMUL3Q(opimm32, opr64, opr64); err != nil { + t.Fatal(err) + } + if _, err := IMUL3Q(opimm8, opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := IMUL3Q(opimm8, opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestIMUL3WValidFormsNoError(t *testing.T) { + if _, err := IMUL3W(opimm16, opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := IMUL3W(opimm16, opr16, opr16); err != nil { + t.Fatal(err) + } + if _, err := IMUL3W(opimm8, opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := IMUL3W(opimm8, opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestIMULBValidFormsNoError(t *testing.T) { + if _, err := IMULB(opm8); err != nil { + t.Fatal(err) + } + if _, err := IMULB(opr8); err != nil { + t.Fatal(err) + } +} + +func TestIMULLValidFormsNoError(t *testing.T) { + if _, err := IMULL(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := IMULL(opm32); err != nil { + t.Fatal(err) + } + if _, err := IMULL(opr32, opr32); err != nil { + t.Fatal(err) + } + if _, err := IMULL(opr32); err != nil { + t.Fatal(err) + } +} + +func TestIMULQValidFormsNoError(t *testing.T) { + if _, err := IMULQ(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := IMULQ(opm64); err != nil { + t.Fatal(err) + } + if _, err := IMULQ(opr64, opr64); err != nil { + t.Fatal(err) + } + if _, err := IMULQ(opr64); err != nil { + t.Fatal(err) + } +} + +func TestIMULWValidFormsNoError(t *testing.T) { + if _, err := IMULW(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := IMULW(opm16); err != nil { + t.Fatal(err) + } + if _, err := IMULW(opr16, opr16); err != nil { + t.Fatal(err) + } + if _, err := IMULW(opr16); err != nil { + t.Fatal(err) + } +} + +func TestINCBValidFormsNoError(t *testing.T) { + if _, err := INCB(opm8); err != nil { + t.Fatal(err) + } + if _, err := INCB(opr8); err != nil { + t.Fatal(err) + } +} + +func TestINCLValidFormsNoError(t *testing.T) { + if _, err := INCL(opm32); err != nil { + t.Fatal(err) + } + if _, err := INCL(opr32); err != nil { + t.Fatal(err) + } +} + +func TestINCQValidFormsNoError(t *testing.T) { + if _, err := INCQ(opm64); err != nil { + t.Fatal(err) + } + if _, err := INCQ(opr64); err != nil { + t.Fatal(err) + } +} + +func TestINCWValidFormsNoError(t *testing.T) { + if _, err := INCW(opm16); err != nil { + t.Fatal(err) + } + if _, err := INCW(opr16); err != nil { + t.Fatal(err) + } +} + +func TestINSERTPSValidFormsNoError(t *testing.T) { + if _, err := INSERTPS(opimm8, opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := INSERTPS(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestINTValidFormsNoError(t *testing.T) { + if _, err := INT(op3); err != nil { + t.Fatal(err) + } + if _, err := INT(opimm8); err != nil { + t.Fatal(err) + } +} + +func TestJAValidFormsNoError(t *testing.T) { + if _, err := JA(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JA(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJAEValidFormsNoError(t *testing.T) { + if _, err := JAE(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JAE(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJBValidFormsNoError(t *testing.T) { + if _, err := JB(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JB(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJBEValidFormsNoError(t *testing.T) { + if _, err := JBE(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JBE(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJCValidFormsNoError(t *testing.T) { + if _, err := JC(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JC(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJCCValidFormsNoError(t *testing.T) { + if _, err := JCC(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JCC(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJCSValidFormsNoError(t *testing.T) { + if _, err := JCS(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JCS(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJCXZLValidFormsNoError(t *testing.T) { + if _, err := JCXZL(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJCXZQValidFormsNoError(t *testing.T) { + if _, err := JCXZQ(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJEValidFormsNoError(t *testing.T) { + if _, err := JE(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JE(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJEQValidFormsNoError(t *testing.T) { + if _, err := JEQ(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JEQ(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJGValidFormsNoError(t *testing.T) { + if _, err := JG(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JG(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJGEValidFormsNoError(t *testing.T) { + if _, err := JGE(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JGE(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJGTValidFormsNoError(t *testing.T) { + if _, err := JGT(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JGT(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJHIValidFormsNoError(t *testing.T) { + if _, err := JHI(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JHI(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJHSValidFormsNoError(t *testing.T) { + if _, err := JHS(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JHS(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJLValidFormsNoError(t *testing.T) { + if _, err := JL(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JL(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJLEValidFormsNoError(t *testing.T) { + if _, err := JLE(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JLE(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJLOValidFormsNoError(t *testing.T) { + if _, err := JLO(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JLO(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJLSValidFormsNoError(t *testing.T) { + if _, err := JLS(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JLS(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJLTValidFormsNoError(t *testing.T) { + if _, err := JLT(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JLT(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJMIValidFormsNoError(t *testing.T) { + if _, err := JMI(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JMI(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJMPValidFormsNoError(t *testing.T) { + if _, err := JMP(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JMP(oprel8); err != nil { + t.Fatal(err) + } + if _, err := JMP(opm64); err != nil { + t.Fatal(err) + } + if _, err := JMP(opr64); err != nil { + t.Fatal(err) + } +} + +func TestJNAValidFormsNoError(t *testing.T) { + if _, err := JNA(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JNA(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJNAEValidFormsNoError(t *testing.T) { + if _, err := JNAE(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JNAE(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJNBValidFormsNoError(t *testing.T) { + if _, err := JNB(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JNB(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJNBEValidFormsNoError(t *testing.T) { + if _, err := JNBE(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JNBE(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJNCValidFormsNoError(t *testing.T) { + if _, err := JNC(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JNC(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJNEValidFormsNoError(t *testing.T) { + if _, err := JNE(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JNE(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJNGValidFormsNoError(t *testing.T) { + if _, err := JNG(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JNG(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJNGEValidFormsNoError(t *testing.T) { + if _, err := JNGE(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JNGE(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJNLValidFormsNoError(t *testing.T) { + if _, err := JNL(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JNL(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJNLEValidFormsNoError(t *testing.T) { + if _, err := JNLE(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JNLE(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJNOValidFormsNoError(t *testing.T) { + if _, err := JNO(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JNO(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJNPValidFormsNoError(t *testing.T) { + if _, err := JNP(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JNP(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJNSValidFormsNoError(t *testing.T) { + if _, err := JNS(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JNS(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJNZValidFormsNoError(t *testing.T) { + if _, err := JNZ(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JNZ(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJOValidFormsNoError(t *testing.T) { + if _, err := JO(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JO(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJOCValidFormsNoError(t *testing.T) { + if _, err := JOC(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JOC(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJOSValidFormsNoError(t *testing.T) { + if _, err := JOS(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JOS(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJPValidFormsNoError(t *testing.T) { + if _, err := JP(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JP(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJPCValidFormsNoError(t *testing.T) { + if _, err := JPC(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JPC(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJPEValidFormsNoError(t *testing.T) { + if _, err := JPE(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JPE(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJPLValidFormsNoError(t *testing.T) { + if _, err := JPL(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JPL(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJPOValidFormsNoError(t *testing.T) { + if _, err := JPO(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JPO(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJPSValidFormsNoError(t *testing.T) { + if _, err := JPS(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JPS(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJSValidFormsNoError(t *testing.T) { + if _, err := JS(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JS(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestJZValidFormsNoError(t *testing.T) { + if _, err := JZ(oprel32); err != nil { + t.Fatal(err) + } + if _, err := JZ(oprel8); err != nil { + t.Fatal(err) + } +} + +func TestKADDBValidFormsNoError(t *testing.T) { + if _, err := KADDB(opk, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKADDDValidFormsNoError(t *testing.T) { + if _, err := KADDD(opk, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKADDQValidFormsNoError(t *testing.T) { + if _, err := KADDQ(opk, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKADDWValidFormsNoError(t *testing.T) { + if _, err := KADDW(opk, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKANDBValidFormsNoError(t *testing.T) { + if _, err := KANDB(opk, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKANDDValidFormsNoError(t *testing.T) { + if _, err := KANDD(opk, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKANDNBValidFormsNoError(t *testing.T) { + if _, err := KANDNB(opk, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKANDNDValidFormsNoError(t *testing.T) { + if _, err := KANDND(opk, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKANDNQValidFormsNoError(t *testing.T) { + if _, err := KANDNQ(opk, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKANDNWValidFormsNoError(t *testing.T) { + if _, err := KANDNW(opk, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKANDQValidFormsNoError(t *testing.T) { + if _, err := KANDQ(opk, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKANDWValidFormsNoError(t *testing.T) { + if _, err := KANDW(opk, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKMOVBValidFormsNoError(t *testing.T) { + if _, err := KMOVB(opk, opk); err != nil { + t.Fatal(err) + } + if _, err := KMOVB(opk, opm8); err != nil { + t.Fatal(err) + } + if _, err := KMOVB(opk, opr32); err != nil { + t.Fatal(err) + } + if _, err := KMOVB(opm8, opk); err != nil { + t.Fatal(err) + } + if _, err := KMOVB(opr32, opk); err != nil { + t.Fatal(err) + } +} + +func TestKMOVDValidFormsNoError(t *testing.T) { + if _, err := KMOVD(opk, opk); err != nil { + t.Fatal(err) + } + if _, err := KMOVD(opk, opm32); err != nil { + t.Fatal(err) + } + if _, err := KMOVD(opk, opr32); err != nil { + t.Fatal(err) + } + if _, err := KMOVD(opm32, opk); err != nil { + t.Fatal(err) + } + if _, err := KMOVD(opr32, opk); err != nil { + t.Fatal(err) + } +} + +func TestKMOVQValidFormsNoError(t *testing.T) { + if _, err := KMOVQ(opk, opk); err != nil { + t.Fatal(err) + } + if _, err := KMOVQ(opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := KMOVQ(opk, opr64); err != nil { + t.Fatal(err) + } + if _, err := KMOVQ(opm64, opk); err != nil { + t.Fatal(err) + } + if _, err := KMOVQ(opr64, opk); err != nil { + t.Fatal(err) + } +} + +func TestKMOVWValidFormsNoError(t *testing.T) { + if _, err := KMOVW(opk, opk); err != nil { + t.Fatal(err) + } + if _, err := KMOVW(opk, opm16); err != nil { + t.Fatal(err) + } + if _, err := KMOVW(opk, opr32); err != nil { + t.Fatal(err) + } + if _, err := KMOVW(opm16, opk); err != nil { + t.Fatal(err) + } + if _, err := KMOVW(opr32, opk); err != nil { + t.Fatal(err) + } +} + +func TestKNOTBValidFormsNoError(t *testing.T) { + if _, err := KNOTB(opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKNOTDValidFormsNoError(t *testing.T) { + if _, err := KNOTD(opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKNOTQValidFormsNoError(t *testing.T) { + if _, err := KNOTQ(opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKNOTWValidFormsNoError(t *testing.T) { + if _, err := KNOTW(opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKORBValidFormsNoError(t *testing.T) { + if _, err := KORB(opk, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKORDValidFormsNoError(t *testing.T) { + if _, err := KORD(opk, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKORQValidFormsNoError(t *testing.T) { + if _, err := KORQ(opk, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKORTESTBValidFormsNoError(t *testing.T) { + if _, err := KORTESTB(opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKORTESTDValidFormsNoError(t *testing.T) { + if _, err := KORTESTD(opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKORTESTQValidFormsNoError(t *testing.T) { + if _, err := KORTESTQ(opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKORTESTWValidFormsNoError(t *testing.T) { + if _, err := KORTESTW(opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKORWValidFormsNoError(t *testing.T) { + if _, err := KORW(opk, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKSHIFTLBValidFormsNoError(t *testing.T) { + if _, err := KSHIFTLB(opimm8, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKSHIFTLDValidFormsNoError(t *testing.T) { + if _, err := KSHIFTLD(opimm8, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKSHIFTLQValidFormsNoError(t *testing.T) { + if _, err := KSHIFTLQ(opimm8, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKSHIFTLWValidFormsNoError(t *testing.T) { + if _, err := KSHIFTLW(opimm8, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKSHIFTRBValidFormsNoError(t *testing.T) { + if _, err := KSHIFTRB(opimm8, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKSHIFTRDValidFormsNoError(t *testing.T) { + if _, err := KSHIFTRD(opimm8, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKSHIFTRQValidFormsNoError(t *testing.T) { + if _, err := KSHIFTRQ(opimm8, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKSHIFTRWValidFormsNoError(t *testing.T) { + if _, err := KSHIFTRW(opimm8, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKTESTBValidFormsNoError(t *testing.T) { + if _, err := KTESTB(opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKTESTDValidFormsNoError(t *testing.T) { + if _, err := KTESTD(opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKTESTQValidFormsNoError(t *testing.T) { + if _, err := KTESTQ(opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKTESTWValidFormsNoError(t *testing.T) { + if _, err := KTESTW(opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKUNPCKBWValidFormsNoError(t *testing.T) { + if _, err := KUNPCKBW(opk, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKUNPCKDQValidFormsNoError(t *testing.T) { + if _, err := KUNPCKDQ(opk, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKUNPCKWDValidFormsNoError(t *testing.T) { + if _, err := KUNPCKWD(opk, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKXNORBValidFormsNoError(t *testing.T) { + if _, err := KXNORB(opk, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKXNORDValidFormsNoError(t *testing.T) { + if _, err := KXNORD(opk, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKXNORQValidFormsNoError(t *testing.T) { + if _, err := KXNORQ(opk, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKXNORWValidFormsNoError(t *testing.T) { + if _, err := KXNORW(opk, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKXORBValidFormsNoError(t *testing.T) { + if _, err := KXORB(opk, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKXORDValidFormsNoError(t *testing.T) { + if _, err := KXORD(opk, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKXORQValidFormsNoError(t *testing.T) { + if _, err := KXORQ(opk, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestKXORWValidFormsNoError(t *testing.T) { + if _, err := KXORW(opk, opk, opk); err != nil { + t.Fatal(err) + } +} + +func TestLDDQUValidFormsNoError(t *testing.T) { + if _, err := LDDQU(opm128, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestLDMXCSRValidFormsNoError(t *testing.T) { + if _, err := LDMXCSR(opm32); err != nil { + t.Fatal(err) + } +} + +func TestLEALValidFormsNoError(t *testing.T) { + if _, err := LEAL(opm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestLEAQValidFormsNoError(t *testing.T) { + if _, err := LEAQ(opm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestLEAWValidFormsNoError(t *testing.T) { + if _, err := LEAW(opm, opr16); err != nil { + t.Fatal(err) + } +} + +func TestLFENCEValidFormsNoError(t *testing.T) { + if _, err := LFENCE(); err != nil { + t.Fatal(err) + } +} + +func TestLZCNTLValidFormsNoError(t *testing.T) { + if _, err := LZCNTL(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := LZCNTL(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestLZCNTQValidFormsNoError(t *testing.T) { + if _, err := LZCNTQ(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := LZCNTQ(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestLZCNTWValidFormsNoError(t *testing.T) { + if _, err := LZCNTW(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := LZCNTW(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestMASKMOVDQUValidFormsNoError(t *testing.T) { + if _, err := MASKMOVDQU(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestMASKMOVOUValidFormsNoError(t *testing.T) { + if _, err := MASKMOVOU(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestMAXPDValidFormsNoError(t *testing.T) { + if _, err := MAXPD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MAXPD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestMAXPSValidFormsNoError(t *testing.T) { + if _, err := MAXPS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MAXPS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestMAXSDValidFormsNoError(t *testing.T) { + if _, err := MAXSD(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MAXSD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestMAXSSValidFormsNoError(t *testing.T) { + if _, err := MAXSS(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MAXSS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestMFENCEValidFormsNoError(t *testing.T) { + if _, err := MFENCE(); err != nil { + t.Fatal(err) + } +} + +func TestMINPDValidFormsNoError(t *testing.T) { + if _, err := MINPD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MINPD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestMINPSValidFormsNoError(t *testing.T) { + if _, err := MINPS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MINPS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestMINSDValidFormsNoError(t *testing.T) { + if _, err := MINSD(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MINSD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestMINSSValidFormsNoError(t *testing.T) { + if _, err := MINSS(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MINSS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestMONITORValidFormsNoError(t *testing.T) { + if _, err := MONITOR(); err != nil { + t.Fatal(err) + } +} + +func TestMOVAPDValidFormsNoError(t *testing.T) { + if _, err := MOVAPD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MOVAPD(opxmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := MOVAPD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestMOVAPSValidFormsNoError(t *testing.T) { + if _, err := MOVAPS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MOVAPS(opxmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := MOVAPS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestMOVBValidFormsNoError(t *testing.T) { + if _, err := MOVB(opimm8, opm8); err != nil { + t.Fatal(err) + } + if _, err := MOVB(opimm8, opr8); err != nil { + t.Fatal(err) + } + if _, err := MOVB(opm8, opr8); err != nil { + t.Fatal(err) + } + if _, err := MOVB(opr8, opm8); err != nil { + t.Fatal(err) + } + if _, err := MOVB(opr8, opr8); err != nil { + t.Fatal(err) + } +} + +func TestMOVBELLValidFormsNoError(t *testing.T) { + if _, err := MOVBELL(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := MOVBELL(opr32, opm32); err != nil { + t.Fatal(err) + } +} + +func TestMOVBEQQValidFormsNoError(t *testing.T) { + if _, err := MOVBEQQ(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := MOVBEQQ(opr64, opm64); err != nil { + t.Fatal(err) + } +} + +func TestMOVBEWWValidFormsNoError(t *testing.T) { + if _, err := MOVBEWW(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := MOVBEWW(opr16, opm16); err != nil { + t.Fatal(err) + } +} + +func TestMOVBLSXValidFormsNoError(t *testing.T) { + if _, err := MOVBLSX(opm8, opr32); err != nil { + t.Fatal(err) + } + if _, err := MOVBLSX(opr8, opr32); err != nil { + t.Fatal(err) + } +} + +func TestMOVBLZXValidFormsNoError(t *testing.T) { + if _, err := MOVBLZX(opm8, opr32); err != nil { + t.Fatal(err) + } + if _, err := MOVBLZX(opr8, opr32); err != nil { + t.Fatal(err) + } +} + +func TestMOVBQSXValidFormsNoError(t *testing.T) { + if _, err := MOVBQSX(opm8, opr64); err != nil { + t.Fatal(err) + } + if _, err := MOVBQSX(opr8, opr64); err != nil { + t.Fatal(err) + } +} + +func TestMOVBQZXValidFormsNoError(t *testing.T) { + if _, err := MOVBQZX(opm8, opr64); err != nil { + t.Fatal(err) + } + if _, err := MOVBQZX(opr8, opr64); err != nil { + t.Fatal(err) + } +} + +func TestMOVBWSXValidFormsNoError(t *testing.T) { + if _, err := MOVBWSX(opm8, opr16); err != nil { + t.Fatal(err) + } + if _, err := MOVBWSX(opr8, opr16); err != nil { + t.Fatal(err) + } +} + +func TestMOVBWZXValidFormsNoError(t *testing.T) { + if _, err := MOVBWZX(opm8, opr16); err != nil { + t.Fatal(err) + } + if _, err := MOVBWZX(opr8, opr16); err != nil { + t.Fatal(err) + } +} + +func TestMOVDValidFormsNoError(t *testing.T) { + if _, err := MOVD(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MOVD(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MOVD(opr32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MOVD(opr64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MOVD(opxmm, opm32); err != nil { + t.Fatal(err) + } + if _, err := MOVD(opxmm, opm64); err != nil { + t.Fatal(err) + } + if _, err := MOVD(opxmm, opr32); err != nil { + t.Fatal(err) + } + if _, err := MOVD(opxmm, opr64); err != nil { + t.Fatal(err) + } + if _, err := MOVD(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MOVD(opimm32, opm64); err != nil { + t.Fatal(err) + } + if _, err := MOVD(opimm32, opr64); err != nil { + t.Fatal(err) + } + if _, err := MOVD(opimm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := MOVD(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := MOVD(opr64, opm64); err != nil { + t.Fatal(err) + } + if _, err := MOVD(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestMOVDDUPValidFormsNoError(t *testing.T) { + if _, err := MOVDDUP(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MOVDDUP(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestMOVDQ2QValidFormsNoError(t *testing.T) { + if _, err := MOVDQ2Q(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MOVDQ2Q(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MOVDQ2Q(opr32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MOVDQ2Q(opr64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MOVDQ2Q(opxmm, opm32); err != nil { + t.Fatal(err) + } + if _, err := MOVDQ2Q(opxmm, opm64); err != nil { + t.Fatal(err) + } + if _, err := MOVDQ2Q(opxmm, opr32); err != nil { + t.Fatal(err) + } + if _, err := MOVDQ2Q(opxmm, opr64); err != nil { + t.Fatal(err) + } + if _, err := MOVDQ2Q(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MOVDQ2Q(opimm32, opm64); err != nil { + t.Fatal(err) + } + if _, err := MOVDQ2Q(opimm32, opr64); err != nil { + t.Fatal(err) + } + if _, err := MOVDQ2Q(opimm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := MOVDQ2Q(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := MOVDQ2Q(opr64, opm64); err != nil { + t.Fatal(err) + } + if _, err := MOVDQ2Q(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestMOVHLPSValidFormsNoError(t *testing.T) { + if _, err := MOVHLPS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestMOVHPDValidFormsNoError(t *testing.T) { + if _, err := MOVHPD(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MOVHPD(opxmm, opm64); err != nil { + t.Fatal(err) + } +} + +func TestMOVHPSValidFormsNoError(t *testing.T) { + if _, err := MOVHPS(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MOVHPS(opxmm, opm64); err != nil { + t.Fatal(err) + } +} + +func TestMOVLValidFormsNoError(t *testing.T) { + if _, err := MOVL(opimm32, opm32); err != nil { + t.Fatal(err) + } + if _, err := MOVL(opimm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := MOVL(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := MOVL(opr32, opm32); err != nil { + t.Fatal(err) + } + if _, err := MOVL(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestMOVLHPSValidFormsNoError(t *testing.T) { + if _, err := MOVLHPS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestMOVLPDValidFormsNoError(t *testing.T) { + if _, err := MOVLPD(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MOVLPD(opxmm, opm64); err != nil { + t.Fatal(err) + } +} + +func TestMOVLPSValidFormsNoError(t *testing.T) { + if _, err := MOVLPS(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MOVLPS(opxmm, opm64); err != nil { + t.Fatal(err) + } +} + +func TestMOVLQSXValidFormsNoError(t *testing.T) { + if _, err := MOVLQSX(opm32, opr64); err != nil { + t.Fatal(err) + } + if _, err := MOVLQSX(opr32, opr64); err != nil { + t.Fatal(err) + } +} + +func TestMOVLQZXValidFormsNoError(t *testing.T) { + if _, err := MOVLQZX(opm32, opr64); err != nil { + t.Fatal(err) + } +} + +func TestMOVMSKPDValidFormsNoError(t *testing.T) { + if _, err := MOVMSKPD(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestMOVMSKPSValidFormsNoError(t *testing.T) { + if _, err := MOVMSKPS(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestMOVNTDQValidFormsNoError(t *testing.T) { + if _, err := MOVNTDQ(opxmm, opm128); err != nil { + t.Fatal(err) + } +} + +func TestMOVNTDQAValidFormsNoError(t *testing.T) { + if _, err := MOVNTDQA(opm128, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestMOVNTILValidFormsNoError(t *testing.T) { + if _, err := MOVNTIL(opr32, opm32); err != nil { + t.Fatal(err) + } +} + +func TestMOVNTIQValidFormsNoError(t *testing.T) { + if _, err := MOVNTIQ(opr64, opm64); err != nil { + t.Fatal(err) + } +} + +func TestMOVNTOValidFormsNoError(t *testing.T) { + if _, err := MOVNTO(opxmm, opm128); err != nil { + t.Fatal(err) + } +} + +func TestMOVNTPDValidFormsNoError(t *testing.T) { + if _, err := MOVNTPD(opxmm, opm128); err != nil { + t.Fatal(err) + } +} + +func TestMOVNTPSValidFormsNoError(t *testing.T) { + if _, err := MOVNTPS(opxmm, opm128); err != nil { + t.Fatal(err) + } +} + +func TestMOVOValidFormsNoError(t *testing.T) { + if _, err := MOVO(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MOVO(opxmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := MOVO(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestMOVOAValidFormsNoError(t *testing.T) { + if _, err := MOVOA(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MOVOA(opxmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := MOVOA(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestMOVOUValidFormsNoError(t *testing.T) { + if _, err := MOVOU(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MOVOU(opxmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := MOVOU(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestMOVQValidFormsNoError(t *testing.T) { + if _, err := MOVQ(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MOVQ(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MOVQ(opr32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MOVQ(opr64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MOVQ(opxmm, opm32); err != nil { + t.Fatal(err) + } + if _, err := MOVQ(opxmm, opm64); err != nil { + t.Fatal(err) + } + if _, err := MOVQ(opxmm, opr32); err != nil { + t.Fatal(err) + } + if _, err := MOVQ(opxmm, opr64); err != nil { + t.Fatal(err) + } + if _, err := MOVQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MOVQ(opimm32, opm64); err != nil { + t.Fatal(err) + } + if _, err := MOVQ(opimm32, opr64); err != nil { + t.Fatal(err) + } + if _, err := MOVQ(opimm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := MOVQ(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := MOVQ(opr64, opm64); err != nil { + t.Fatal(err) + } + if _, err := MOVQ(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestMOVSDValidFormsNoError(t *testing.T) { + if _, err := MOVSD(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MOVSD(opxmm, opm64); err != nil { + t.Fatal(err) + } + if _, err := MOVSD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestMOVSHDUPValidFormsNoError(t *testing.T) { + if _, err := MOVSHDUP(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MOVSHDUP(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestMOVSLDUPValidFormsNoError(t *testing.T) { + if _, err := MOVSLDUP(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MOVSLDUP(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestMOVSSValidFormsNoError(t *testing.T) { + if _, err := MOVSS(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MOVSS(opxmm, opm32); err != nil { + t.Fatal(err) + } + if _, err := MOVSS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestMOVUPDValidFormsNoError(t *testing.T) { + if _, err := MOVUPD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MOVUPD(opxmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := MOVUPD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestMOVUPSValidFormsNoError(t *testing.T) { + if _, err := MOVUPS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MOVUPS(opxmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := MOVUPS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestMOVWValidFormsNoError(t *testing.T) { + if _, err := MOVW(opimm16, opm16); err != nil { + t.Fatal(err) + } + if _, err := MOVW(opimm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := MOVW(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := MOVW(opr16, opm16); err != nil { + t.Fatal(err) + } + if _, err := MOVW(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestMOVWLSXValidFormsNoError(t *testing.T) { + if _, err := MOVWLSX(opm16, opr32); err != nil { + t.Fatal(err) + } + if _, err := MOVWLSX(opr16, opr32); err != nil { + t.Fatal(err) + } +} + +func TestMOVWLZXValidFormsNoError(t *testing.T) { + if _, err := MOVWLZX(opm16, opr32); err != nil { + t.Fatal(err) + } + if _, err := MOVWLZX(opr16, opr32); err != nil { + t.Fatal(err) + } +} + +func TestMOVWQSXValidFormsNoError(t *testing.T) { + if _, err := MOVWQSX(opm16, opr64); err != nil { + t.Fatal(err) + } + if _, err := MOVWQSX(opr16, opr64); err != nil { + t.Fatal(err) + } +} + +func TestMOVWQZXValidFormsNoError(t *testing.T) { + if _, err := MOVWQZX(opm16, opr64); err != nil { + t.Fatal(err) + } + if _, err := MOVWQZX(opr16, opr64); err != nil { + t.Fatal(err) + } +} + +func TestMPSADBWValidFormsNoError(t *testing.T) { + if _, err := MPSADBW(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MPSADBW(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestMULBValidFormsNoError(t *testing.T) { + if _, err := MULB(opm8); err != nil { + t.Fatal(err) + } + if _, err := MULB(opr8); err != nil { + t.Fatal(err) + } +} + +func TestMULLValidFormsNoError(t *testing.T) { + if _, err := MULL(opm32); err != nil { + t.Fatal(err) + } + if _, err := MULL(opr32); err != nil { + t.Fatal(err) + } +} + +func TestMULPDValidFormsNoError(t *testing.T) { + if _, err := MULPD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MULPD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestMULPSValidFormsNoError(t *testing.T) { + if _, err := MULPS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MULPS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestMULQValidFormsNoError(t *testing.T) { + if _, err := MULQ(opm64); err != nil { + t.Fatal(err) + } + if _, err := MULQ(opr64); err != nil { + t.Fatal(err) + } +} + +func TestMULSDValidFormsNoError(t *testing.T) { + if _, err := MULSD(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MULSD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestMULSSValidFormsNoError(t *testing.T) { + if _, err := MULSS(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := MULSS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestMULWValidFormsNoError(t *testing.T) { + if _, err := MULW(opm16); err != nil { + t.Fatal(err) + } + if _, err := MULW(opr16); err != nil { + t.Fatal(err) + } +} + +func TestMULXLValidFormsNoError(t *testing.T) { + if _, err := MULXL(opm32, opr32, opr32); err != nil { + t.Fatal(err) + } + if _, err := MULXL(opr32, opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestMULXQValidFormsNoError(t *testing.T) { + if _, err := MULXQ(opm64, opr64, opr64); err != nil { + t.Fatal(err) + } + if _, err := MULXQ(opr64, opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestMWAITValidFormsNoError(t *testing.T) { + if _, err := MWAIT(); err != nil { + t.Fatal(err) + } +} + +func TestNEGBValidFormsNoError(t *testing.T) { + if _, err := NEGB(opm8); err != nil { + t.Fatal(err) + } + if _, err := NEGB(opr8); err != nil { + t.Fatal(err) + } +} + +func TestNEGLValidFormsNoError(t *testing.T) { + if _, err := NEGL(opm32); err != nil { + t.Fatal(err) + } + if _, err := NEGL(opr32); err != nil { + t.Fatal(err) + } +} + +func TestNEGQValidFormsNoError(t *testing.T) { + if _, err := NEGQ(opm64); err != nil { + t.Fatal(err) + } + if _, err := NEGQ(opr64); err != nil { + t.Fatal(err) + } +} + +func TestNEGWValidFormsNoError(t *testing.T) { + if _, err := NEGW(opm16); err != nil { + t.Fatal(err) + } + if _, err := NEGW(opr16); err != nil { + t.Fatal(err) + } +} + +func TestNOPValidFormsNoError(t *testing.T) { + if _, err := NOP(); err != nil { + t.Fatal(err) + } +} + +func TestNOTBValidFormsNoError(t *testing.T) { + if _, err := NOTB(opm8); err != nil { + t.Fatal(err) + } + if _, err := NOTB(opr8); err != nil { + t.Fatal(err) + } +} + +func TestNOTLValidFormsNoError(t *testing.T) { + if _, err := NOTL(opm32); err != nil { + t.Fatal(err) + } + if _, err := NOTL(opr32); err != nil { + t.Fatal(err) + } +} + +func TestNOTQValidFormsNoError(t *testing.T) { + if _, err := NOTQ(opm64); err != nil { + t.Fatal(err) + } + if _, err := NOTQ(opr64); err != nil { + t.Fatal(err) + } +} + +func TestNOTWValidFormsNoError(t *testing.T) { + if _, err := NOTW(opm16); err != nil { + t.Fatal(err) + } + if _, err := NOTW(opr16); err != nil { + t.Fatal(err) + } +} + +func TestORBValidFormsNoError(t *testing.T) { + if _, err := ORB(opimm8, opal); err != nil { + t.Fatal(err) + } + if _, err := ORB(opimm8, opm8); err != nil { + t.Fatal(err) + } + if _, err := ORB(opimm8, opr8); err != nil { + t.Fatal(err) + } + if _, err := ORB(opm8, opr8); err != nil { + t.Fatal(err) + } + if _, err := ORB(opr8, opm8); err != nil { + t.Fatal(err) + } + if _, err := ORB(opr8, opr8); err != nil { + t.Fatal(err) + } +} + +func TestORLValidFormsNoError(t *testing.T) { + if _, err := ORL(opimm32, opeax); err != nil { + t.Fatal(err) + } + if _, err := ORL(opimm32, opm32); err != nil { + t.Fatal(err) + } + if _, err := ORL(opimm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := ORL(opimm8, opm32); err != nil { + t.Fatal(err) + } + if _, err := ORL(opimm8, opr32); err != nil { + t.Fatal(err) + } + if _, err := ORL(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := ORL(opr32, opm32); err != nil { + t.Fatal(err) + } + if _, err := ORL(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestORPDValidFormsNoError(t *testing.T) { + if _, err := ORPD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := ORPD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestORPSValidFormsNoError(t *testing.T) { + if _, err := ORPS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := ORPS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestORQValidFormsNoError(t *testing.T) { + if _, err := ORQ(opimm32, opm64); err != nil { + t.Fatal(err) + } + if _, err := ORQ(opimm32, opr64); err != nil { + t.Fatal(err) + } + if _, err := ORQ(opimm32, oprax); err != nil { + t.Fatal(err) + } + if _, err := ORQ(opimm8, opm64); err != nil { + t.Fatal(err) + } + if _, err := ORQ(opimm8, opr64); err != nil { + t.Fatal(err) + } + if _, err := ORQ(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := ORQ(opr64, opm64); err != nil { + t.Fatal(err) + } + if _, err := ORQ(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestORWValidFormsNoError(t *testing.T) { + if _, err := ORW(opimm16, opax); err != nil { + t.Fatal(err) + } + if _, err := ORW(opimm16, opm16); err != nil { + t.Fatal(err) + } + if _, err := ORW(opimm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := ORW(opimm8, opm16); err != nil { + t.Fatal(err) + } + if _, err := ORW(opimm8, opr16); err != nil { + t.Fatal(err) + } + if _, err := ORW(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := ORW(opr16, opm16); err != nil { + t.Fatal(err) + } + if _, err := ORW(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestPABSBValidFormsNoError(t *testing.T) { + if _, err := PABSB(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PABSB(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPABSDValidFormsNoError(t *testing.T) { + if _, err := PABSD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PABSD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPABSWValidFormsNoError(t *testing.T) { + if _, err := PABSW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PABSW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPACKSSLWValidFormsNoError(t *testing.T) { + if _, err := PACKSSLW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PACKSSLW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPACKSSWBValidFormsNoError(t *testing.T) { + if _, err := PACKSSWB(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PACKSSWB(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPACKUSDWValidFormsNoError(t *testing.T) { + if _, err := PACKUSDW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PACKUSDW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPACKUSWBValidFormsNoError(t *testing.T) { + if _, err := PACKUSWB(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PACKUSWB(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPADDBValidFormsNoError(t *testing.T) { + if _, err := PADDB(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PADDB(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPADDDValidFormsNoError(t *testing.T) { + if _, err := PADDD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PADDD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPADDLValidFormsNoError(t *testing.T) { + if _, err := PADDL(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PADDL(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPADDQValidFormsNoError(t *testing.T) { + if _, err := PADDQ(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PADDQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPADDSBValidFormsNoError(t *testing.T) { + if _, err := PADDSB(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PADDSB(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPADDSWValidFormsNoError(t *testing.T) { + if _, err := PADDSW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PADDSW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPADDUSBValidFormsNoError(t *testing.T) { + if _, err := PADDUSB(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PADDUSB(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPADDUSWValidFormsNoError(t *testing.T) { + if _, err := PADDUSW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PADDUSW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPADDWValidFormsNoError(t *testing.T) { + if _, err := PADDW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PADDW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPALIGNRValidFormsNoError(t *testing.T) { + if _, err := PALIGNR(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PALIGNR(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPANDValidFormsNoError(t *testing.T) { + if _, err := PAND(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PAND(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPANDNValidFormsNoError(t *testing.T) { + if _, err := PANDN(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PANDN(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPAUSEValidFormsNoError(t *testing.T) { + if _, err := PAUSE(); err != nil { + t.Fatal(err) + } +} + +func TestPAVGBValidFormsNoError(t *testing.T) { + if _, err := PAVGB(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PAVGB(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPAVGWValidFormsNoError(t *testing.T) { + if _, err := PAVGW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PAVGW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPBLENDVBValidFormsNoError(t *testing.T) { + if _, err := PBLENDVB(opxmm0, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PBLENDVB(opxmm0, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPBLENDWValidFormsNoError(t *testing.T) { + if _, err := PBLENDW(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PBLENDW(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPCLMULQDQValidFormsNoError(t *testing.T) { + if _, err := PCLMULQDQ(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PCLMULQDQ(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPCMPEQBValidFormsNoError(t *testing.T) { + if _, err := PCMPEQB(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PCMPEQB(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPCMPEQLValidFormsNoError(t *testing.T) { + if _, err := PCMPEQL(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PCMPEQL(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPCMPEQQValidFormsNoError(t *testing.T) { + if _, err := PCMPEQQ(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PCMPEQQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPCMPEQWValidFormsNoError(t *testing.T) { + if _, err := PCMPEQW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PCMPEQW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPCMPESTRIValidFormsNoError(t *testing.T) { + if _, err := PCMPESTRI(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PCMPESTRI(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPCMPESTRMValidFormsNoError(t *testing.T) { + if _, err := PCMPESTRM(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PCMPESTRM(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPCMPGTBValidFormsNoError(t *testing.T) { + if _, err := PCMPGTB(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PCMPGTB(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPCMPGTLValidFormsNoError(t *testing.T) { + if _, err := PCMPGTL(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PCMPGTL(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPCMPGTQValidFormsNoError(t *testing.T) { + if _, err := PCMPGTQ(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PCMPGTQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPCMPGTWValidFormsNoError(t *testing.T) { + if _, err := PCMPGTW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PCMPGTW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPCMPISTRIValidFormsNoError(t *testing.T) { + if _, err := PCMPISTRI(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PCMPISTRI(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPCMPISTRMValidFormsNoError(t *testing.T) { + if _, err := PCMPISTRM(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PCMPISTRM(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPDEPLValidFormsNoError(t *testing.T) { + if _, err := PDEPL(opm32, opr32, opr32); err != nil { + t.Fatal(err) + } + if _, err := PDEPL(opr32, opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestPDEPQValidFormsNoError(t *testing.T) { + if _, err := PDEPQ(opm64, opr64, opr64); err != nil { + t.Fatal(err) + } + if _, err := PDEPQ(opr64, opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestPEXTLValidFormsNoError(t *testing.T) { + if _, err := PEXTL(opm32, opr32, opr32); err != nil { + t.Fatal(err) + } + if _, err := PEXTL(opr32, opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestPEXTQValidFormsNoError(t *testing.T) { + if _, err := PEXTQ(opm64, opr64, opr64); err != nil { + t.Fatal(err) + } + if _, err := PEXTQ(opr64, opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestPEXTRBValidFormsNoError(t *testing.T) { + if _, err := PEXTRB(opimm8, opxmm, opm8); err != nil { + t.Fatal(err) + } + if _, err := PEXTRB(opimm8, opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestPEXTRDValidFormsNoError(t *testing.T) { + if _, err := PEXTRD(opimm8, opxmm, opm32); err != nil { + t.Fatal(err) + } + if _, err := PEXTRD(opimm8, opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestPEXTRQValidFormsNoError(t *testing.T) { + if _, err := PEXTRQ(opimm8, opxmm, opm64); err != nil { + t.Fatal(err) + } + if _, err := PEXTRQ(opimm8, opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestPEXTRWValidFormsNoError(t *testing.T) { + if _, err := PEXTRW(opimm8, opxmm, opm16); err != nil { + t.Fatal(err) + } + if _, err := PEXTRW(opimm8, opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestPHADDDValidFormsNoError(t *testing.T) { + if _, err := PHADDD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PHADDD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPHADDSWValidFormsNoError(t *testing.T) { + if _, err := PHADDSW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PHADDSW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPHADDWValidFormsNoError(t *testing.T) { + if _, err := PHADDW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PHADDW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPHMINPOSUWValidFormsNoError(t *testing.T) { + if _, err := PHMINPOSUW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PHMINPOSUW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPHSUBDValidFormsNoError(t *testing.T) { + if _, err := PHSUBD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PHSUBD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPHSUBSWValidFormsNoError(t *testing.T) { + if _, err := PHSUBSW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PHSUBSW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPHSUBWValidFormsNoError(t *testing.T) { + if _, err := PHSUBW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PHSUBW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPINSRBValidFormsNoError(t *testing.T) { + if _, err := PINSRB(opimm8, opm8, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PINSRB(opimm8, opr32, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPINSRDValidFormsNoError(t *testing.T) { + if _, err := PINSRD(opimm8, opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PINSRD(opimm8, opr32, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPINSRQValidFormsNoError(t *testing.T) { + if _, err := PINSRQ(opimm8, opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PINSRQ(opimm8, opr64, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPINSRWValidFormsNoError(t *testing.T) { + if _, err := PINSRW(opimm8, opm16, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PINSRW(opimm8, opr32, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMADDUBSWValidFormsNoError(t *testing.T) { + if _, err := PMADDUBSW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMADDUBSW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMADDWLValidFormsNoError(t *testing.T) { + if _, err := PMADDWL(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMADDWL(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMAXSBValidFormsNoError(t *testing.T) { + if _, err := PMAXSB(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMAXSB(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMAXSDValidFormsNoError(t *testing.T) { + if _, err := PMAXSD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMAXSD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMAXSWValidFormsNoError(t *testing.T) { + if _, err := PMAXSW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMAXSW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMAXUBValidFormsNoError(t *testing.T) { + if _, err := PMAXUB(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMAXUB(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMAXUDValidFormsNoError(t *testing.T) { + if _, err := PMAXUD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMAXUD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMAXUWValidFormsNoError(t *testing.T) { + if _, err := PMAXUW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMAXUW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMINSBValidFormsNoError(t *testing.T) { + if _, err := PMINSB(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMINSB(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMINSDValidFormsNoError(t *testing.T) { + if _, err := PMINSD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMINSD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMINSWValidFormsNoError(t *testing.T) { + if _, err := PMINSW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMINSW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMINUBValidFormsNoError(t *testing.T) { + if _, err := PMINUB(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMINUB(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMINUDValidFormsNoError(t *testing.T) { + if _, err := PMINUD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMINUD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMINUWValidFormsNoError(t *testing.T) { + if _, err := PMINUW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMINUW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMOVMSKBValidFormsNoError(t *testing.T) { + if _, err := PMOVMSKB(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestPMOVSXBDValidFormsNoError(t *testing.T) { + if _, err := PMOVSXBD(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMOVSXBD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMOVSXBQValidFormsNoError(t *testing.T) { + if _, err := PMOVSXBQ(opm16, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMOVSXBQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMOVSXBWValidFormsNoError(t *testing.T) { + if _, err := PMOVSXBW(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMOVSXBW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMOVSXDQValidFormsNoError(t *testing.T) { + if _, err := PMOVSXDQ(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMOVSXDQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMOVSXWDValidFormsNoError(t *testing.T) { + if _, err := PMOVSXWD(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMOVSXWD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMOVSXWQValidFormsNoError(t *testing.T) { + if _, err := PMOVSXWQ(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMOVSXWQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMOVZXBDValidFormsNoError(t *testing.T) { + if _, err := PMOVZXBD(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMOVZXBD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMOVZXBQValidFormsNoError(t *testing.T) { + if _, err := PMOVZXBQ(opm16, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMOVZXBQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMOVZXBWValidFormsNoError(t *testing.T) { + if _, err := PMOVZXBW(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMOVZXBW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMOVZXDQValidFormsNoError(t *testing.T) { + if _, err := PMOVZXDQ(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMOVZXDQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMOVZXWDValidFormsNoError(t *testing.T) { + if _, err := PMOVZXWD(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMOVZXWD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMOVZXWQValidFormsNoError(t *testing.T) { + if _, err := PMOVZXWQ(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMOVZXWQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMULDQValidFormsNoError(t *testing.T) { + if _, err := PMULDQ(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMULDQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMULHRSWValidFormsNoError(t *testing.T) { + if _, err := PMULHRSW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMULHRSW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMULHUWValidFormsNoError(t *testing.T) { + if _, err := PMULHUW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMULHUW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMULHWValidFormsNoError(t *testing.T) { + if _, err := PMULHW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMULHW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMULLDValidFormsNoError(t *testing.T) { + if _, err := PMULLD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMULLD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMULLWValidFormsNoError(t *testing.T) { + if _, err := PMULLW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMULLW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPMULULQValidFormsNoError(t *testing.T) { + if _, err := PMULULQ(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PMULULQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPOPCNTLValidFormsNoError(t *testing.T) { + if _, err := POPCNTL(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := POPCNTL(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestPOPCNTQValidFormsNoError(t *testing.T) { + if _, err := POPCNTQ(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := POPCNTQ(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestPOPCNTWValidFormsNoError(t *testing.T) { + if _, err := POPCNTW(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := POPCNTW(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestPOPQValidFormsNoError(t *testing.T) { + if _, err := POPQ(opm64); err != nil { + t.Fatal(err) + } + if _, err := POPQ(opr64); err != nil { + t.Fatal(err) + } +} + +func TestPOPWValidFormsNoError(t *testing.T) { + if _, err := POPW(opm16); err != nil { + t.Fatal(err) + } + if _, err := POPW(opr16); err != nil { + t.Fatal(err) + } +} + +func TestPORValidFormsNoError(t *testing.T) { + if _, err := POR(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := POR(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPREFETCHNTAValidFormsNoError(t *testing.T) { + if _, err := PREFETCHNTA(opm8); err != nil { + t.Fatal(err) + } +} + +func TestPREFETCHT0ValidFormsNoError(t *testing.T) { + if _, err := PREFETCHT0(opm8); err != nil { + t.Fatal(err) + } +} + +func TestPREFETCHT1ValidFormsNoError(t *testing.T) { + if _, err := PREFETCHT1(opm8); err != nil { + t.Fatal(err) + } +} + +func TestPREFETCHT2ValidFormsNoError(t *testing.T) { + if _, err := PREFETCHT2(opm8); err != nil { + t.Fatal(err) + } +} + +func TestPSADBWValidFormsNoError(t *testing.T) { + if _, err := PSADBW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSADBW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPSHUFBValidFormsNoError(t *testing.T) { + if _, err := PSHUFB(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSHUFB(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPSHUFDValidFormsNoError(t *testing.T) { + if _, err := PSHUFD(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSHUFD(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPSHUFHWValidFormsNoError(t *testing.T) { + if _, err := PSHUFHW(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSHUFHW(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPSHUFLValidFormsNoError(t *testing.T) { + if _, err := PSHUFL(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSHUFL(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPSHUFLWValidFormsNoError(t *testing.T) { + if _, err := PSHUFLW(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSHUFLW(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPSIGNBValidFormsNoError(t *testing.T) { + if _, err := PSIGNB(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSIGNB(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPSIGNDValidFormsNoError(t *testing.T) { + if _, err := PSIGND(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSIGND(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPSIGNWValidFormsNoError(t *testing.T) { + if _, err := PSIGNW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSIGNW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPSLLDQValidFormsNoError(t *testing.T) { + if _, err := PSLLDQ(opimm8, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPSLLLValidFormsNoError(t *testing.T) { + if _, err := PSLLL(opimm8, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSLLL(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSLLL(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPSLLOValidFormsNoError(t *testing.T) { + if _, err := PSLLO(opimm8, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPSLLQValidFormsNoError(t *testing.T) { + if _, err := PSLLQ(opimm8, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSLLQ(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSLLQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPSLLWValidFormsNoError(t *testing.T) { + if _, err := PSLLW(opimm8, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSLLW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSLLW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPSRALValidFormsNoError(t *testing.T) { + if _, err := PSRAL(opimm8, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSRAL(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSRAL(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPSRAWValidFormsNoError(t *testing.T) { + if _, err := PSRAW(opimm8, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSRAW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSRAW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPSRLDQValidFormsNoError(t *testing.T) { + if _, err := PSRLDQ(opimm8, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPSRLLValidFormsNoError(t *testing.T) { + if _, err := PSRLL(opimm8, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSRLL(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSRLL(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPSRLOValidFormsNoError(t *testing.T) { + if _, err := PSRLO(opimm8, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPSRLQValidFormsNoError(t *testing.T) { + if _, err := PSRLQ(opimm8, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSRLQ(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSRLQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPSRLWValidFormsNoError(t *testing.T) { + if _, err := PSRLW(opimm8, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSRLW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSRLW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPSUBBValidFormsNoError(t *testing.T) { + if _, err := PSUBB(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSUBB(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPSUBLValidFormsNoError(t *testing.T) { + if _, err := PSUBL(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSUBL(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPSUBQValidFormsNoError(t *testing.T) { + if _, err := PSUBQ(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSUBQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPSUBSBValidFormsNoError(t *testing.T) { + if _, err := PSUBSB(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSUBSB(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPSUBSWValidFormsNoError(t *testing.T) { + if _, err := PSUBSW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSUBSW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPSUBUSBValidFormsNoError(t *testing.T) { + if _, err := PSUBUSB(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSUBUSB(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPSUBUSWValidFormsNoError(t *testing.T) { + if _, err := PSUBUSW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSUBUSW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPSUBWValidFormsNoError(t *testing.T) { + if _, err := PSUBW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PSUBW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPTESTValidFormsNoError(t *testing.T) { + if _, err := PTEST(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PTEST(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPUNPCKHBWValidFormsNoError(t *testing.T) { + if _, err := PUNPCKHBW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PUNPCKHBW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPUNPCKHLQValidFormsNoError(t *testing.T) { + if _, err := PUNPCKHLQ(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PUNPCKHLQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPUNPCKHQDQValidFormsNoError(t *testing.T) { + if _, err := PUNPCKHQDQ(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PUNPCKHQDQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPUNPCKHWLValidFormsNoError(t *testing.T) { + if _, err := PUNPCKHWL(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PUNPCKHWL(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPUNPCKLBWValidFormsNoError(t *testing.T) { + if _, err := PUNPCKLBW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PUNPCKLBW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPUNPCKLLQValidFormsNoError(t *testing.T) { + if _, err := PUNPCKLLQ(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PUNPCKLLQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPUNPCKLQDQValidFormsNoError(t *testing.T) { + if _, err := PUNPCKLQDQ(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PUNPCKLQDQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPUNPCKLWLValidFormsNoError(t *testing.T) { + if _, err := PUNPCKLWL(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PUNPCKLWL(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestPUSHQValidFormsNoError(t *testing.T) { + if _, err := PUSHQ(opimm32); err != nil { + t.Fatal(err) + } + if _, err := PUSHQ(opimm8); err != nil { + t.Fatal(err) + } + if _, err := PUSHQ(opm64); err != nil { + t.Fatal(err) + } + if _, err := PUSHQ(opr64); err != nil { + t.Fatal(err) + } +} + +func TestPUSHWValidFormsNoError(t *testing.T) { + if _, err := PUSHW(opm16); err != nil { + t.Fatal(err) + } + if _, err := PUSHW(opr16); err != nil { + t.Fatal(err) + } +} + +func TestPXORValidFormsNoError(t *testing.T) { + if _, err := PXOR(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := PXOR(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestRCLBValidFormsNoError(t *testing.T) { + if _, err := RCLB(op1, opm8); err != nil { + t.Fatal(err) + } + if _, err := RCLB(op1, opr8); err != nil { + t.Fatal(err) + } + if _, err := RCLB(opcl, opm8); err != nil { + t.Fatal(err) + } + if _, err := RCLB(opcl, opr8); err != nil { + t.Fatal(err) + } + if _, err := RCLB(opimm8, opm8); err != nil { + t.Fatal(err) + } + if _, err := RCLB(opimm8, opr8); err != nil { + t.Fatal(err) + } +} + +func TestRCLLValidFormsNoError(t *testing.T) { + if _, err := RCLL(op1, opm32); err != nil { + t.Fatal(err) + } + if _, err := RCLL(op1, opr32); err != nil { + t.Fatal(err) + } + if _, err := RCLL(opcl, opm32); err != nil { + t.Fatal(err) + } + if _, err := RCLL(opcl, opr32); err != nil { + t.Fatal(err) + } + if _, err := RCLL(opimm8, opm32); err != nil { + t.Fatal(err) + } + if _, err := RCLL(opimm8, opr32); err != nil { + t.Fatal(err) + } +} + +func TestRCLQValidFormsNoError(t *testing.T) { + if _, err := RCLQ(op1, opm64); err != nil { + t.Fatal(err) + } + if _, err := RCLQ(op1, opr64); err != nil { + t.Fatal(err) + } + if _, err := RCLQ(opcl, opm64); err != nil { + t.Fatal(err) + } + if _, err := RCLQ(opcl, opr64); err != nil { + t.Fatal(err) + } + if _, err := RCLQ(opimm8, opm64); err != nil { + t.Fatal(err) + } + if _, err := RCLQ(opimm8, opr64); err != nil { + t.Fatal(err) + } +} + +func TestRCLWValidFormsNoError(t *testing.T) { + if _, err := RCLW(op1, opm16); err != nil { + t.Fatal(err) + } + if _, err := RCLW(op1, opr16); err != nil { + t.Fatal(err) + } + if _, err := RCLW(opcl, opm16); err != nil { + t.Fatal(err) + } + if _, err := RCLW(opcl, opr16); err != nil { + t.Fatal(err) + } + if _, err := RCLW(opimm8, opm16); err != nil { + t.Fatal(err) + } + if _, err := RCLW(opimm8, opr16); err != nil { + t.Fatal(err) + } +} + +func TestRCPPSValidFormsNoError(t *testing.T) { + if _, err := RCPPS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := RCPPS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestRCPSSValidFormsNoError(t *testing.T) { + if _, err := RCPSS(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := RCPSS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestRCRBValidFormsNoError(t *testing.T) { + if _, err := RCRB(op1, opm8); err != nil { + t.Fatal(err) + } + if _, err := RCRB(op1, opr8); err != nil { + t.Fatal(err) + } + if _, err := RCRB(opcl, opm8); err != nil { + t.Fatal(err) + } + if _, err := RCRB(opcl, opr8); err != nil { + t.Fatal(err) + } + if _, err := RCRB(opimm8, opm8); err != nil { + t.Fatal(err) + } + if _, err := RCRB(opimm8, opr8); err != nil { + t.Fatal(err) + } +} + +func TestRCRLValidFormsNoError(t *testing.T) { + if _, err := RCRL(op1, opm32); err != nil { + t.Fatal(err) + } + if _, err := RCRL(op1, opr32); err != nil { + t.Fatal(err) + } + if _, err := RCRL(opcl, opm32); err != nil { + t.Fatal(err) + } + if _, err := RCRL(opcl, opr32); err != nil { + t.Fatal(err) + } + if _, err := RCRL(opimm8, opm32); err != nil { + t.Fatal(err) + } + if _, err := RCRL(opimm8, opr32); err != nil { + t.Fatal(err) + } +} + +func TestRCRQValidFormsNoError(t *testing.T) { + if _, err := RCRQ(op1, opm64); err != nil { + t.Fatal(err) + } + if _, err := RCRQ(op1, opr64); err != nil { + t.Fatal(err) + } + if _, err := RCRQ(opcl, opm64); err != nil { + t.Fatal(err) + } + if _, err := RCRQ(opcl, opr64); err != nil { + t.Fatal(err) + } + if _, err := RCRQ(opimm8, opm64); err != nil { + t.Fatal(err) + } + if _, err := RCRQ(opimm8, opr64); err != nil { + t.Fatal(err) + } +} + +func TestRCRWValidFormsNoError(t *testing.T) { + if _, err := RCRW(op1, opm16); err != nil { + t.Fatal(err) + } + if _, err := RCRW(op1, opr16); err != nil { + t.Fatal(err) + } + if _, err := RCRW(opcl, opm16); err != nil { + t.Fatal(err) + } + if _, err := RCRW(opcl, opr16); err != nil { + t.Fatal(err) + } + if _, err := RCRW(opimm8, opm16); err != nil { + t.Fatal(err) + } + if _, err := RCRW(opimm8, opr16); err != nil { + t.Fatal(err) + } +} + +func TestRDRANDLValidFormsNoError(t *testing.T) { + if _, err := RDRANDL(opr16); err != nil { + t.Fatal(err) + } + if _, err := RDRANDL(opr32); err != nil { + t.Fatal(err) + } + if _, err := RDRANDL(opr64); err != nil { + t.Fatal(err) + } +} + +func TestRDSEEDLValidFormsNoError(t *testing.T) { + if _, err := RDSEEDL(opr16); err != nil { + t.Fatal(err) + } + if _, err := RDSEEDL(opr32); err != nil { + t.Fatal(err) + } + if _, err := RDSEEDL(opr64); err != nil { + t.Fatal(err) + } +} + +func TestRDTSCValidFormsNoError(t *testing.T) { + if _, err := RDTSC(); err != nil { + t.Fatal(err) + } +} + +func TestRDTSCPValidFormsNoError(t *testing.T) { + if _, err := RDTSCP(); err != nil { + t.Fatal(err) + } +} + +func TestRETValidFormsNoError(t *testing.T) { + if _, err := RET(); err != nil { + t.Fatal(err) + } +} + +func TestRETFLValidFormsNoError(t *testing.T) { + if _, err := RETFL(opimm16); err != nil { + t.Fatal(err) + } +} + +func TestRETFQValidFormsNoError(t *testing.T) { + if _, err := RETFQ(opimm16); err != nil { + t.Fatal(err) + } +} + +func TestRETFWValidFormsNoError(t *testing.T) { + if _, err := RETFW(opimm16); err != nil { + t.Fatal(err) + } +} + +func TestROLBValidFormsNoError(t *testing.T) { + if _, err := ROLB(op1, opm8); err != nil { + t.Fatal(err) + } + if _, err := ROLB(op1, opr8); err != nil { + t.Fatal(err) + } + if _, err := ROLB(opcl, opm8); err != nil { + t.Fatal(err) + } + if _, err := ROLB(opcl, opr8); err != nil { + t.Fatal(err) + } + if _, err := ROLB(opimm8, opm8); err != nil { + t.Fatal(err) + } + if _, err := ROLB(opimm8, opr8); err != nil { + t.Fatal(err) + } +} + +func TestROLLValidFormsNoError(t *testing.T) { + if _, err := ROLL(op1, opm32); err != nil { + t.Fatal(err) + } + if _, err := ROLL(op1, opr32); err != nil { + t.Fatal(err) + } + if _, err := ROLL(opcl, opm32); err != nil { + t.Fatal(err) + } + if _, err := ROLL(opcl, opr32); err != nil { + t.Fatal(err) + } + if _, err := ROLL(opimm8, opm32); err != nil { + t.Fatal(err) + } + if _, err := ROLL(opimm8, opr32); err != nil { + t.Fatal(err) + } +} + +func TestROLQValidFormsNoError(t *testing.T) { + if _, err := ROLQ(op1, opm64); err != nil { + t.Fatal(err) + } + if _, err := ROLQ(op1, opr64); err != nil { + t.Fatal(err) + } + if _, err := ROLQ(opcl, opm64); err != nil { + t.Fatal(err) + } + if _, err := ROLQ(opcl, opr64); err != nil { + t.Fatal(err) + } + if _, err := ROLQ(opimm8, opm64); err != nil { + t.Fatal(err) + } + if _, err := ROLQ(opimm8, opr64); err != nil { + t.Fatal(err) + } +} + +func TestROLWValidFormsNoError(t *testing.T) { + if _, err := ROLW(op1, opm16); err != nil { + t.Fatal(err) + } + if _, err := ROLW(op1, opr16); err != nil { + t.Fatal(err) + } + if _, err := ROLW(opcl, opm16); err != nil { + t.Fatal(err) + } + if _, err := ROLW(opcl, opr16); err != nil { + t.Fatal(err) + } + if _, err := ROLW(opimm8, opm16); err != nil { + t.Fatal(err) + } + if _, err := ROLW(opimm8, opr16); err != nil { + t.Fatal(err) + } +} + +func TestRORBValidFormsNoError(t *testing.T) { + if _, err := RORB(op1, opm8); err != nil { + t.Fatal(err) + } + if _, err := RORB(op1, opr8); err != nil { + t.Fatal(err) + } + if _, err := RORB(opcl, opm8); err != nil { + t.Fatal(err) + } + if _, err := RORB(opcl, opr8); err != nil { + t.Fatal(err) + } + if _, err := RORB(opimm8, opm8); err != nil { + t.Fatal(err) + } + if _, err := RORB(opimm8, opr8); err != nil { + t.Fatal(err) + } +} + +func TestRORLValidFormsNoError(t *testing.T) { + if _, err := RORL(op1, opm32); err != nil { + t.Fatal(err) + } + if _, err := RORL(op1, opr32); err != nil { + t.Fatal(err) + } + if _, err := RORL(opcl, opm32); err != nil { + t.Fatal(err) + } + if _, err := RORL(opcl, opr32); err != nil { + t.Fatal(err) + } + if _, err := RORL(opimm8, opm32); err != nil { + t.Fatal(err) + } + if _, err := RORL(opimm8, opr32); err != nil { + t.Fatal(err) + } +} + +func TestRORQValidFormsNoError(t *testing.T) { + if _, err := RORQ(op1, opm64); err != nil { + t.Fatal(err) + } + if _, err := RORQ(op1, opr64); err != nil { + t.Fatal(err) + } + if _, err := RORQ(opcl, opm64); err != nil { + t.Fatal(err) + } + if _, err := RORQ(opcl, opr64); err != nil { + t.Fatal(err) + } + if _, err := RORQ(opimm8, opm64); err != nil { + t.Fatal(err) + } + if _, err := RORQ(opimm8, opr64); err != nil { + t.Fatal(err) + } +} + +func TestRORWValidFormsNoError(t *testing.T) { + if _, err := RORW(op1, opm16); err != nil { + t.Fatal(err) + } + if _, err := RORW(op1, opr16); err != nil { + t.Fatal(err) + } + if _, err := RORW(opcl, opm16); err != nil { + t.Fatal(err) + } + if _, err := RORW(opcl, opr16); err != nil { + t.Fatal(err) + } + if _, err := RORW(opimm8, opm16); err != nil { + t.Fatal(err) + } + if _, err := RORW(opimm8, opr16); err != nil { + t.Fatal(err) + } +} + +func TestRORXLValidFormsNoError(t *testing.T) { + if _, err := RORXL(opimm8, opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := RORXL(opimm8, opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestRORXQValidFormsNoError(t *testing.T) { + if _, err := RORXQ(opimm8, opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := RORXQ(opimm8, opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestROUNDPDValidFormsNoError(t *testing.T) { + if _, err := ROUNDPD(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := ROUNDPD(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestROUNDPSValidFormsNoError(t *testing.T) { + if _, err := ROUNDPS(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := ROUNDPS(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestROUNDSDValidFormsNoError(t *testing.T) { + if _, err := ROUNDSD(opimm8, opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := ROUNDSD(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestROUNDSSValidFormsNoError(t *testing.T) { + if _, err := ROUNDSS(opimm8, opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := ROUNDSS(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestRSQRTPSValidFormsNoError(t *testing.T) { + if _, err := RSQRTPS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := RSQRTPS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestRSQRTSSValidFormsNoError(t *testing.T) { + if _, err := RSQRTSS(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := RSQRTSS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestSALBValidFormsNoError(t *testing.T) { + if _, err := SALB(op1, opm8); err != nil { + t.Fatal(err) + } + if _, err := SALB(op1, opr8); err != nil { + t.Fatal(err) + } + if _, err := SALB(opcl, opm8); err != nil { + t.Fatal(err) + } + if _, err := SALB(opcl, opr8); err != nil { + t.Fatal(err) + } + if _, err := SALB(opimm8, opm8); err != nil { + t.Fatal(err) + } + if _, err := SALB(opimm8, opr8); err != nil { + t.Fatal(err) + } +} + +func TestSALLValidFormsNoError(t *testing.T) { + if _, err := SALL(op1, opm32); err != nil { + t.Fatal(err) + } + if _, err := SALL(op1, opr32); err != nil { + t.Fatal(err) + } + if _, err := SALL(opcl, opm32); err != nil { + t.Fatal(err) + } + if _, err := SALL(opcl, opr32); err != nil { + t.Fatal(err) + } + if _, err := SALL(opimm8, opm32); err != nil { + t.Fatal(err) + } + if _, err := SALL(opimm8, opr32); err != nil { + t.Fatal(err) + } +} + +func TestSALQValidFormsNoError(t *testing.T) { + if _, err := SALQ(op1, opm64); err != nil { + t.Fatal(err) + } + if _, err := SALQ(op1, opr64); err != nil { + t.Fatal(err) + } + if _, err := SALQ(opcl, opm64); err != nil { + t.Fatal(err) + } + if _, err := SALQ(opcl, opr64); err != nil { + t.Fatal(err) + } + if _, err := SALQ(opimm8, opm64); err != nil { + t.Fatal(err) + } + if _, err := SALQ(opimm8, opr64); err != nil { + t.Fatal(err) + } +} + +func TestSALWValidFormsNoError(t *testing.T) { + if _, err := SALW(op1, opm16); err != nil { + t.Fatal(err) + } + if _, err := SALW(op1, opr16); err != nil { + t.Fatal(err) + } + if _, err := SALW(opcl, opm16); err != nil { + t.Fatal(err) + } + if _, err := SALW(opcl, opr16); err != nil { + t.Fatal(err) + } + if _, err := SALW(opimm8, opm16); err != nil { + t.Fatal(err) + } + if _, err := SALW(opimm8, opr16); err != nil { + t.Fatal(err) + } +} + +func TestSARBValidFormsNoError(t *testing.T) { + if _, err := SARB(op1, opm8); err != nil { + t.Fatal(err) + } + if _, err := SARB(op1, opr8); err != nil { + t.Fatal(err) + } + if _, err := SARB(opcl, opm8); err != nil { + t.Fatal(err) + } + if _, err := SARB(opcl, opr8); err != nil { + t.Fatal(err) + } + if _, err := SARB(opimm8, opm8); err != nil { + t.Fatal(err) + } + if _, err := SARB(opimm8, opr8); err != nil { + t.Fatal(err) + } +} + +func TestSARLValidFormsNoError(t *testing.T) { + if _, err := SARL(op1, opm32); err != nil { + t.Fatal(err) + } + if _, err := SARL(op1, opr32); err != nil { + t.Fatal(err) + } + if _, err := SARL(opcl, opm32); err != nil { + t.Fatal(err) + } + if _, err := SARL(opcl, opr32); err != nil { + t.Fatal(err) + } + if _, err := SARL(opimm8, opm32); err != nil { + t.Fatal(err) + } + if _, err := SARL(opimm8, opr32); err != nil { + t.Fatal(err) + } +} + +func TestSARQValidFormsNoError(t *testing.T) { + if _, err := SARQ(op1, opm64); err != nil { + t.Fatal(err) + } + if _, err := SARQ(op1, opr64); err != nil { + t.Fatal(err) + } + if _, err := SARQ(opcl, opm64); err != nil { + t.Fatal(err) + } + if _, err := SARQ(opcl, opr64); err != nil { + t.Fatal(err) + } + if _, err := SARQ(opimm8, opm64); err != nil { + t.Fatal(err) + } + if _, err := SARQ(opimm8, opr64); err != nil { + t.Fatal(err) + } +} + +func TestSARWValidFormsNoError(t *testing.T) { + if _, err := SARW(op1, opm16); err != nil { + t.Fatal(err) + } + if _, err := SARW(op1, opr16); err != nil { + t.Fatal(err) + } + if _, err := SARW(opcl, opm16); err != nil { + t.Fatal(err) + } + if _, err := SARW(opcl, opr16); err != nil { + t.Fatal(err) + } + if _, err := SARW(opimm8, opm16); err != nil { + t.Fatal(err) + } + if _, err := SARW(opimm8, opr16); err != nil { + t.Fatal(err) + } +} + +func TestSARXLValidFormsNoError(t *testing.T) { + if _, err := SARXL(opr32, opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := SARXL(opr32, opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestSARXQValidFormsNoError(t *testing.T) { + if _, err := SARXQ(opr64, opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := SARXQ(opr64, opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestSBBBValidFormsNoError(t *testing.T) { + if _, err := SBBB(opimm8, opal); err != nil { + t.Fatal(err) + } + if _, err := SBBB(opimm8, opm8); err != nil { + t.Fatal(err) + } + if _, err := SBBB(opimm8, opr8); err != nil { + t.Fatal(err) + } + if _, err := SBBB(opm8, opr8); err != nil { + t.Fatal(err) + } + if _, err := SBBB(opr8, opm8); err != nil { + t.Fatal(err) + } + if _, err := SBBB(opr8, opr8); err != nil { + t.Fatal(err) + } +} + +func TestSBBLValidFormsNoError(t *testing.T) { + if _, err := SBBL(opimm32, opeax); err != nil { + t.Fatal(err) + } + if _, err := SBBL(opimm32, opm32); err != nil { + t.Fatal(err) + } + if _, err := SBBL(opimm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := SBBL(opimm8, opm32); err != nil { + t.Fatal(err) + } + if _, err := SBBL(opimm8, opr32); err != nil { + t.Fatal(err) + } + if _, err := SBBL(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := SBBL(opr32, opm32); err != nil { + t.Fatal(err) + } + if _, err := SBBL(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestSBBQValidFormsNoError(t *testing.T) { + if _, err := SBBQ(opimm32, opm64); err != nil { + t.Fatal(err) + } + if _, err := SBBQ(opimm32, opr64); err != nil { + t.Fatal(err) + } + if _, err := SBBQ(opimm32, oprax); err != nil { + t.Fatal(err) + } + if _, err := SBBQ(opimm8, opm64); err != nil { + t.Fatal(err) + } + if _, err := SBBQ(opimm8, opr64); err != nil { + t.Fatal(err) + } + if _, err := SBBQ(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := SBBQ(opr64, opm64); err != nil { + t.Fatal(err) + } + if _, err := SBBQ(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestSBBWValidFormsNoError(t *testing.T) { + if _, err := SBBW(opimm16, opax); err != nil { + t.Fatal(err) + } + if _, err := SBBW(opimm16, opm16); err != nil { + t.Fatal(err) + } + if _, err := SBBW(opimm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := SBBW(opimm8, opm16); err != nil { + t.Fatal(err) + } + if _, err := SBBW(opimm8, opr16); err != nil { + t.Fatal(err) + } + if _, err := SBBW(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := SBBW(opr16, opm16); err != nil { + t.Fatal(err) + } + if _, err := SBBW(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestSETCCValidFormsNoError(t *testing.T) { + if _, err := SETCC(opm8); err != nil { + t.Fatal(err) + } + if _, err := SETCC(opr8); err != nil { + t.Fatal(err) + } +} + +func TestSETCSValidFormsNoError(t *testing.T) { + if _, err := SETCS(opm8); err != nil { + t.Fatal(err) + } + if _, err := SETCS(opr8); err != nil { + t.Fatal(err) + } +} + +func TestSETEQValidFormsNoError(t *testing.T) { + if _, err := SETEQ(opm8); err != nil { + t.Fatal(err) + } + if _, err := SETEQ(opr8); err != nil { + t.Fatal(err) + } +} + +func TestSETGEValidFormsNoError(t *testing.T) { + if _, err := SETGE(opm8); err != nil { + t.Fatal(err) + } + if _, err := SETGE(opr8); err != nil { + t.Fatal(err) + } +} + +func TestSETGTValidFormsNoError(t *testing.T) { + if _, err := SETGT(opm8); err != nil { + t.Fatal(err) + } + if _, err := SETGT(opr8); err != nil { + t.Fatal(err) + } +} + +func TestSETHIValidFormsNoError(t *testing.T) { + if _, err := SETHI(opm8); err != nil { + t.Fatal(err) + } + if _, err := SETHI(opr8); err != nil { + t.Fatal(err) + } +} + +func TestSETLEValidFormsNoError(t *testing.T) { + if _, err := SETLE(opm8); err != nil { + t.Fatal(err) + } + if _, err := SETLE(opr8); err != nil { + t.Fatal(err) + } +} + +func TestSETLSValidFormsNoError(t *testing.T) { + if _, err := SETLS(opm8); err != nil { + t.Fatal(err) + } + if _, err := SETLS(opr8); err != nil { + t.Fatal(err) + } +} + +func TestSETLTValidFormsNoError(t *testing.T) { + if _, err := SETLT(opm8); err != nil { + t.Fatal(err) + } + if _, err := SETLT(opr8); err != nil { + t.Fatal(err) + } +} + +func TestSETMIValidFormsNoError(t *testing.T) { + if _, err := SETMI(opm8); err != nil { + t.Fatal(err) + } + if _, err := SETMI(opr8); err != nil { + t.Fatal(err) + } +} + +func TestSETNEValidFormsNoError(t *testing.T) { + if _, err := SETNE(opm8); err != nil { + t.Fatal(err) + } + if _, err := SETNE(opr8); err != nil { + t.Fatal(err) + } +} + +func TestSETOCValidFormsNoError(t *testing.T) { + if _, err := SETOC(opm8); err != nil { + t.Fatal(err) + } + if _, err := SETOC(opr8); err != nil { + t.Fatal(err) + } +} + +func TestSETOSValidFormsNoError(t *testing.T) { + if _, err := SETOS(opm8); err != nil { + t.Fatal(err) + } + if _, err := SETOS(opr8); err != nil { + t.Fatal(err) + } +} + +func TestSETPCValidFormsNoError(t *testing.T) { + if _, err := SETPC(opm8); err != nil { + t.Fatal(err) + } + if _, err := SETPC(opr8); err != nil { + t.Fatal(err) + } +} + +func TestSETPLValidFormsNoError(t *testing.T) { + if _, err := SETPL(opm8); err != nil { + t.Fatal(err) + } + if _, err := SETPL(opr8); err != nil { + t.Fatal(err) + } +} + +func TestSETPSValidFormsNoError(t *testing.T) { + if _, err := SETPS(opm8); err != nil { + t.Fatal(err) + } + if _, err := SETPS(opr8); err != nil { + t.Fatal(err) + } +} + +func TestSFENCEValidFormsNoError(t *testing.T) { + if _, err := SFENCE(); err != nil { + t.Fatal(err) + } +} + +func TestSHA1MSG1ValidFormsNoError(t *testing.T) { + if _, err := SHA1MSG1(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := SHA1MSG1(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestSHA1MSG2ValidFormsNoError(t *testing.T) { + if _, err := SHA1MSG2(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := SHA1MSG2(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestSHA1NEXTEValidFormsNoError(t *testing.T) { + if _, err := SHA1NEXTE(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := SHA1NEXTE(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestSHA1RNDS4ValidFormsNoError(t *testing.T) { + if _, err := SHA1RNDS4(opimm2u, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := SHA1RNDS4(opimm2u, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestSHA256MSG1ValidFormsNoError(t *testing.T) { + if _, err := SHA256MSG1(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := SHA256MSG1(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestSHA256MSG2ValidFormsNoError(t *testing.T) { + if _, err := SHA256MSG2(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := SHA256MSG2(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestSHA256RNDS2ValidFormsNoError(t *testing.T) { + if _, err := SHA256RNDS2(opxmm0, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := SHA256RNDS2(opxmm0, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestSHLBValidFormsNoError(t *testing.T) { + if _, err := SHLB(op1, opm8); err != nil { + t.Fatal(err) + } + if _, err := SHLB(op1, opr8); err != nil { + t.Fatal(err) + } + if _, err := SHLB(opcl, opm8); err != nil { + t.Fatal(err) + } + if _, err := SHLB(opcl, opr8); err != nil { + t.Fatal(err) + } + if _, err := SHLB(opimm8, opm8); err != nil { + t.Fatal(err) + } + if _, err := SHLB(opimm8, opr8); err != nil { + t.Fatal(err) + } +} + +func TestSHLLValidFormsNoError(t *testing.T) { + if _, err := SHLL(op1, opm32); err != nil { + t.Fatal(err) + } + if _, err := SHLL(op1, opr32); err != nil { + t.Fatal(err) + } + if _, err := SHLL(opcl, opm32); err != nil { + t.Fatal(err) + } + if _, err := SHLL(opcl, opr32); err != nil { + t.Fatal(err) + } + if _, err := SHLL(opcl, opr32, opm32); err != nil { + t.Fatal(err) + } + if _, err := SHLL(opcl, opr32, opr32); err != nil { + t.Fatal(err) + } + if _, err := SHLL(opimm8, opm32); err != nil { + t.Fatal(err) + } + if _, err := SHLL(opimm8, opr32); err != nil { + t.Fatal(err) + } + if _, err := SHLL(opimm8, opr32, opm32); err != nil { + t.Fatal(err) + } + if _, err := SHLL(opimm8, opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestSHLQValidFormsNoError(t *testing.T) { + if _, err := SHLQ(op1, opm64); err != nil { + t.Fatal(err) + } + if _, err := SHLQ(op1, opr64); err != nil { + t.Fatal(err) + } + if _, err := SHLQ(opcl, opm64); err != nil { + t.Fatal(err) + } + if _, err := SHLQ(opcl, opr64); err != nil { + t.Fatal(err) + } + if _, err := SHLQ(opcl, opr64, opm64); err != nil { + t.Fatal(err) + } + if _, err := SHLQ(opcl, opr64, opr64); err != nil { + t.Fatal(err) + } + if _, err := SHLQ(opimm8, opm64); err != nil { + t.Fatal(err) + } + if _, err := SHLQ(opimm8, opr64); err != nil { + t.Fatal(err) + } + if _, err := SHLQ(opimm8, opr64, opm64); err != nil { + t.Fatal(err) + } + if _, err := SHLQ(opimm8, opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestSHLWValidFormsNoError(t *testing.T) { + if _, err := SHLW(op1, opm16); err != nil { + t.Fatal(err) + } + if _, err := SHLW(op1, opr16); err != nil { + t.Fatal(err) + } + if _, err := SHLW(opcl, opm16); err != nil { + t.Fatal(err) + } + if _, err := SHLW(opcl, opr16); err != nil { + t.Fatal(err) + } + if _, err := SHLW(opcl, opr16, opm16); err != nil { + t.Fatal(err) + } + if _, err := SHLW(opcl, opr16, opr16); err != nil { + t.Fatal(err) + } + if _, err := SHLW(opimm8, opm16); err != nil { + t.Fatal(err) + } + if _, err := SHLW(opimm8, opr16); err != nil { + t.Fatal(err) + } + if _, err := SHLW(opimm8, opr16, opm16); err != nil { + t.Fatal(err) + } + if _, err := SHLW(opimm8, opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestSHLXLValidFormsNoError(t *testing.T) { + if _, err := SHLXL(opr32, opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := SHLXL(opr32, opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestSHLXQValidFormsNoError(t *testing.T) { + if _, err := SHLXQ(opr64, opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := SHLXQ(opr64, opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestSHRBValidFormsNoError(t *testing.T) { + if _, err := SHRB(op1, opm8); err != nil { + t.Fatal(err) + } + if _, err := SHRB(op1, opr8); err != nil { + t.Fatal(err) + } + if _, err := SHRB(opcl, opm8); err != nil { + t.Fatal(err) + } + if _, err := SHRB(opcl, opr8); err != nil { + t.Fatal(err) + } + if _, err := SHRB(opimm8, opm8); err != nil { + t.Fatal(err) + } + if _, err := SHRB(opimm8, opr8); err != nil { + t.Fatal(err) + } +} + +func TestSHRLValidFormsNoError(t *testing.T) { + if _, err := SHRL(op1, opm32); err != nil { + t.Fatal(err) + } + if _, err := SHRL(op1, opr32); err != nil { + t.Fatal(err) + } + if _, err := SHRL(opcl, opm32); err != nil { + t.Fatal(err) + } + if _, err := SHRL(opcl, opr32); err != nil { + t.Fatal(err) + } + if _, err := SHRL(opcl, opr32, opm32); err != nil { + t.Fatal(err) + } + if _, err := SHRL(opcl, opr32, opr32); err != nil { + t.Fatal(err) + } + if _, err := SHRL(opimm8, opm32); err != nil { + t.Fatal(err) + } + if _, err := SHRL(opimm8, opr32); err != nil { + t.Fatal(err) + } + if _, err := SHRL(opimm8, opr32, opm32); err != nil { + t.Fatal(err) + } + if _, err := SHRL(opimm8, opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestSHRQValidFormsNoError(t *testing.T) { + if _, err := SHRQ(op1, opm64); err != nil { + t.Fatal(err) + } + if _, err := SHRQ(op1, opr64); err != nil { + t.Fatal(err) + } + if _, err := SHRQ(opcl, opm64); err != nil { + t.Fatal(err) + } + if _, err := SHRQ(opcl, opr64); err != nil { + t.Fatal(err) + } + if _, err := SHRQ(opcl, opr64, opm64); err != nil { + t.Fatal(err) + } + if _, err := SHRQ(opcl, opr64, opr64); err != nil { + t.Fatal(err) + } + if _, err := SHRQ(opimm8, opm64); err != nil { + t.Fatal(err) + } + if _, err := SHRQ(opimm8, opr64); err != nil { + t.Fatal(err) + } + if _, err := SHRQ(opimm8, opr64, opm64); err != nil { + t.Fatal(err) + } + if _, err := SHRQ(opimm8, opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestSHRWValidFormsNoError(t *testing.T) { + if _, err := SHRW(op1, opm16); err != nil { + t.Fatal(err) + } + if _, err := SHRW(op1, opr16); err != nil { + t.Fatal(err) + } + if _, err := SHRW(opcl, opm16); err != nil { + t.Fatal(err) + } + if _, err := SHRW(opcl, opr16); err != nil { + t.Fatal(err) + } + if _, err := SHRW(opcl, opr16, opm16); err != nil { + t.Fatal(err) + } + if _, err := SHRW(opcl, opr16, opr16); err != nil { + t.Fatal(err) + } + if _, err := SHRW(opimm8, opm16); err != nil { + t.Fatal(err) + } + if _, err := SHRW(opimm8, opr16); err != nil { + t.Fatal(err) + } + if _, err := SHRW(opimm8, opr16, opm16); err != nil { + t.Fatal(err) + } + if _, err := SHRW(opimm8, opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestSHRXLValidFormsNoError(t *testing.T) { + if _, err := SHRXL(opr32, opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := SHRXL(opr32, opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestSHRXQValidFormsNoError(t *testing.T) { + if _, err := SHRXQ(opr64, opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := SHRXQ(opr64, opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestSHUFPDValidFormsNoError(t *testing.T) { + if _, err := SHUFPD(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := SHUFPD(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestSHUFPSValidFormsNoError(t *testing.T) { + if _, err := SHUFPS(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := SHUFPS(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestSQRTPDValidFormsNoError(t *testing.T) { + if _, err := SQRTPD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := SQRTPD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestSQRTPSValidFormsNoError(t *testing.T) { + if _, err := SQRTPS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := SQRTPS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestSQRTSDValidFormsNoError(t *testing.T) { + if _, err := SQRTSD(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := SQRTSD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestSQRTSSValidFormsNoError(t *testing.T) { + if _, err := SQRTSS(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := SQRTSS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestSTCValidFormsNoError(t *testing.T) { + if _, err := STC(); err != nil { + t.Fatal(err) + } +} + +func TestSTDValidFormsNoError(t *testing.T) { + if _, err := STD(); err != nil { + t.Fatal(err) + } +} + +func TestSTMXCSRValidFormsNoError(t *testing.T) { + if _, err := STMXCSR(opm32); err != nil { + t.Fatal(err) + } +} + +func TestSUBBValidFormsNoError(t *testing.T) { + if _, err := SUBB(opimm8, opal); err != nil { + t.Fatal(err) + } + if _, err := SUBB(opimm8, opm8); err != nil { + t.Fatal(err) + } + if _, err := SUBB(opimm8, opr8); err != nil { + t.Fatal(err) + } + if _, err := SUBB(opm8, opr8); err != nil { + t.Fatal(err) + } + if _, err := SUBB(opr8, opm8); err != nil { + t.Fatal(err) + } + if _, err := SUBB(opr8, opr8); err != nil { + t.Fatal(err) + } +} + +func TestSUBLValidFormsNoError(t *testing.T) { + if _, err := SUBL(opimm32, opeax); err != nil { + t.Fatal(err) + } + if _, err := SUBL(opimm32, opm32); err != nil { + t.Fatal(err) + } + if _, err := SUBL(opimm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := SUBL(opimm8, opm32); err != nil { + t.Fatal(err) + } + if _, err := SUBL(opimm8, opr32); err != nil { + t.Fatal(err) + } + if _, err := SUBL(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := SUBL(opr32, opm32); err != nil { + t.Fatal(err) + } + if _, err := SUBL(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestSUBPDValidFormsNoError(t *testing.T) { + if _, err := SUBPD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := SUBPD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestSUBPSValidFormsNoError(t *testing.T) { + if _, err := SUBPS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := SUBPS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestSUBQValidFormsNoError(t *testing.T) { + if _, err := SUBQ(opimm32, opm64); err != nil { + t.Fatal(err) + } + if _, err := SUBQ(opimm32, opr64); err != nil { + t.Fatal(err) + } + if _, err := SUBQ(opimm32, oprax); err != nil { + t.Fatal(err) + } + if _, err := SUBQ(opimm8, opm64); err != nil { + t.Fatal(err) + } + if _, err := SUBQ(opimm8, opr64); err != nil { + t.Fatal(err) + } + if _, err := SUBQ(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := SUBQ(opr64, opm64); err != nil { + t.Fatal(err) + } + if _, err := SUBQ(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestSUBSDValidFormsNoError(t *testing.T) { + if _, err := SUBSD(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := SUBSD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestSUBSSValidFormsNoError(t *testing.T) { + if _, err := SUBSS(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := SUBSS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestSUBWValidFormsNoError(t *testing.T) { + if _, err := SUBW(opimm16, opax); err != nil { + t.Fatal(err) + } + if _, err := SUBW(opimm16, opm16); err != nil { + t.Fatal(err) + } + if _, err := SUBW(opimm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := SUBW(opimm8, opm16); err != nil { + t.Fatal(err) + } + if _, err := SUBW(opimm8, opr16); err != nil { + t.Fatal(err) + } + if _, err := SUBW(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := SUBW(opr16, opm16); err != nil { + t.Fatal(err) + } + if _, err := SUBW(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestSYSCALLValidFormsNoError(t *testing.T) { + if _, err := SYSCALL(); err != nil { + t.Fatal(err) + } +} + +func TestTESTBValidFormsNoError(t *testing.T) { + if _, err := TESTB(opimm8, opal); err != nil { + t.Fatal(err) + } + if _, err := TESTB(opimm8, opm8); err != nil { + t.Fatal(err) + } + if _, err := TESTB(opimm8, opr8); err != nil { + t.Fatal(err) + } + if _, err := TESTB(opr8, opm8); err != nil { + t.Fatal(err) + } + if _, err := TESTB(opr8, opr8); err != nil { + t.Fatal(err) + } +} + +func TestTESTLValidFormsNoError(t *testing.T) { + if _, err := TESTL(opimm32, opeax); err != nil { + t.Fatal(err) + } + if _, err := TESTL(opimm32, opm32); err != nil { + t.Fatal(err) + } + if _, err := TESTL(opimm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := TESTL(opr32, opm32); err != nil { + t.Fatal(err) + } + if _, err := TESTL(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestTESTQValidFormsNoError(t *testing.T) { + if _, err := TESTQ(opimm32, opm64); err != nil { + t.Fatal(err) + } + if _, err := TESTQ(opimm32, opr64); err != nil { + t.Fatal(err) + } + if _, err := TESTQ(opimm32, oprax); err != nil { + t.Fatal(err) + } + if _, err := TESTQ(opr64, opm64); err != nil { + t.Fatal(err) + } + if _, err := TESTQ(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestTESTWValidFormsNoError(t *testing.T) { + if _, err := TESTW(opimm16, opax); err != nil { + t.Fatal(err) + } + if _, err := TESTW(opimm16, opm16); err != nil { + t.Fatal(err) + } + if _, err := TESTW(opimm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := TESTW(opr16, opm16); err != nil { + t.Fatal(err) + } + if _, err := TESTW(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestTZCNTLValidFormsNoError(t *testing.T) { + if _, err := TZCNTL(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := TZCNTL(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestTZCNTQValidFormsNoError(t *testing.T) { + if _, err := TZCNTQ(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := TZCNTQ(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestTZCNTWValidFormsNoError(t *testing.T) { + if _, err := TZCNTW(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := TZCNTW(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestUCOMISDValidFormsNoError(t *testing.T) { + if _, err := UCOMISD(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := UCOMISD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestUCOMISSValidFormsNoError(t *testing.T) { + if _, err := UCOMISS(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := UCOMISS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestUD2ValidFormsNoError(t *testing.T) { + if _, err := UD2(); err != nil { + t.Fatal(err) + } +} + +func TestUNPCKHPDValidFormsNoError(t *testing.T) { + if _, err := UNPCKHPD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := UNPCKHPD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestUNPCKHPSValidFormsNoError(t *testing.T) { + if _, err := UNPCKHPS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := UNPCKHPS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestUNPCKLPDValidFormsNoError(t *testing.T) { + if _, err := UNPCKLPD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := UNPCKLPD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestUNPCKLPSValidFormsNoError(t *testing.T) { + if _, err := UNPCKLPS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := UNPCKLPS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDPDValidFormsNoError(t *testing.T) { + if _, err := VADDPD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VADDPD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VADDPD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VADDPD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VADDPD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDPD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VADDPD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VADDPD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VADDPD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDPD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VADDPD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VADDPD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDPD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VADDPD_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPD_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDPD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VADDPD_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDPD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VADDPD_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPD_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDPD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VADDPD_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDPD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VADDPD_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPD_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDPD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VADDPD_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDPD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VADDPD_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPD_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDPD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VADDPD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDPD_ZValidFormsNoError(t *testing.T) { + if _, err := VADDPD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VADDPD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VADDPD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDPSValidFormsNoError(t *testing.T) { + if _, err := VADDPS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VADDPS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VADDPS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VADDPS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VADDPS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDPS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VADDPS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VADDPS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VADDPS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDPS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VADDPS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VADDPS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDPS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VADDPS_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPS_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDPS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VADDPS_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDPS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VADDPS_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPS_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDPS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VADDPS_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDPS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VADDPS_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPS_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDPS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VADDPS_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDPS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VADDPS_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPS_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDPS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VADDPS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDPS_ZValidFormsNoError(t *testing.T) { + if _, err := VADDPS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VADDPS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VADDPS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VADDPS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDSDValidFormsNoError(t *testing.T) { + if _, err := VADDSD(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDSD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDSD(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDSD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDSD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VADDSD_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDSD_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDSD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VADDSD_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDSD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VADDSD_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDSD_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDSD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VADDSD_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDSD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VADDSD_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDSD_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDSD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VADDSD_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDSD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VADDSD_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDSD_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDSD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VADDSD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDSD_ZValidFormsNoError(t *testing.T) { + if _, err := VADDSD_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDSD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDSSValidFormsNoError(t *testing.T) { + if _, err := VADDSS(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDSS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDSS(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDSS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDSS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VADDSS_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDSS_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDSS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VADDSS_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDSS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VADDSS_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDSS_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDSS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VADDSS_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDSS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VADDSS_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDSS_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDSS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VADDSS_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDSS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VADDSS_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDSS_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDSS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VADDSS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDSS_ZValidFormsNoError(t *testing.T) { + if _, err := VADDSS_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDSS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVADDSUBPDValidFormsNoError(t *testing.T) { + if _, err := VADDSUBPD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDSUBPD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VADDSUBPD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDSUBPD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVADDSUBPSValidFormsNoError(t *testing.T) { + if _, err := VADDSUBPS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDSUBPS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VADDSUBPS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VADDSUBPS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVAESDECValidFormsNoError(t *testing.T) { + if _, err := VAESDEC(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VAESDEC(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVAESDECLASTValidFormsNoError(t *testing.T) { + if _, err := VAESDECLAST(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VAESDECLAST(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVAESENCValidFormsNoError(t *testing.T) { + if _, err := VAESENC(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VAESENC(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVAESENCLASTValidFormsNoError(t *testing.T) { + if _, err := VAESENCLAST(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VAESENCLAST(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVAESIMCValidFormsNoError(t *testing.T) { + if _, err := VAESIMC(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VAESIMC(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVAESKEYGENASSISTValidFormsNoError(t *testing.T) { + if _, err := VAESKEYGENASSIST(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VAESKEYGENASSIST(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVALIGNDValidFormsNoError(t *testing.T) { + if _, err := VALIGND(opimm8, opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VALIGND(opimm8, opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VALIGND(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VALIGND(opimm8, opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VALIGND(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VALIGND(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VALIGND(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VALIGND(opimm8, opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VALIGND(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VALIGND(opimm8, opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VALIGND(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VALIGND(opimm8, opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVALIGND_BCSTValidFormsNoError(t *testing.T) { + if _, err := VALIGND_BCST(opimm8, opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VALIGND_BCST(opimm8, opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VALIGND_BCST(opimm8, opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VALIGND_BCST(opimm8, opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VALIGND_BCST(opimm8, opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VALIGND_BCST(opimm8, opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVALIGND_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VALIGND_BCST_Z(opimm8, opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VALIGND_BCST_Z(opimm8, opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VALIGND_BCST_Z(opimm8, opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVALIGND_ZValidFormsNoError(t *testing.T) { + if _, err := VALIGND_Z(opimm8, opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VALIGND_Z(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VALIGND_Z(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VALIGND_Z(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VALIGND_Z(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VALIGND_Z(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVALIGNQValidFormsNoError(t *testing.T) { + if _, err := VALIGNQ(opimm8, opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VALIGNQ(opimm8, opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VALIGNQ(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VALIGNQ(opimm8, opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VALIGNQ(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VALIGNQ(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VALIGNQ(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VALIGNQ(opimm8, opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VALIGNQ(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VALIGNQ(opimm8, opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VALIGNQ(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VALIGNQ(opimm8, opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVALIGNQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VALIGNQ_BCST(opimm8, opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VALIGNQ_BCST(opimm8, opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VALIGNQ_BCST(opimm8, opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VALIGNQ_BCST(opimm8, opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VALIGNQ_BCST(opimm8, opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VALIGNQ_BCST(opimm8, opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVALIGNQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VALIGNQ_BCST_Z(opimm8, opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VALIGNQ_BCST_Z(opimm8, opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VALIGNQ_BCST_Z(opimm8, opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVALIGNQ_ZValidFormsNoError(t *testing.T) { + if _, err := VALIGNQ_Z(opimm8, opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VALIGNQ_Z(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VALIGNQ_Z(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VALIGNQ_Z(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VALIGNQ_Z(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VALIGNQ_Z(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVANDNPDValidFormsNoError(t *testing.T) { + if _, err := VANDNPD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVANDNPD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VANDNPD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVANDNPD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VANDNPD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVANDNPD_ZValidFormsNoError(t *testing.T) { + if _, err := VANDNPD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVANDNPSValidFormsNoError(t *testing.T) { + if _, err := VANDNPS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVANDNPS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VANDNPS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVANDNPS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VANDNPS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVANDNPS_ZValidFormsNoError(t *testing.T) { + if _, err := VANDNPS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VANDNPS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVANDPDValidFormsNoError(t *testing.T) { + if _, err := VANDPD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDPD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDPD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDPD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDPD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDPD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDPD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDPD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDPD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VANDPD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VANDPD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VANDPD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVANDPD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VANDPD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDPD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDPD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDPD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDPD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VANDPD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVANDPD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VANDPD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDPD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDPD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVANDPD_ZValidFormsNoError(t *testing.T) { + if _, err := VANDPD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDPD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDPD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDPD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDPD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VANDPD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVANDPSValidFormsNoError(t *testing.T) { + if _, err := VANDPS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDPS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDPS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDPS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDPS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDPS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDPS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDPS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDPS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VANDPS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VANDPS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VANDPS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVANDPS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VANDPS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDPS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDPS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDPS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDPS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VANDPS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVANDPS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VANDPS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDPS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDPS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVANDPS_ZValidFormsNoError(t *testing.T) { + if _, err := VANDPS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDPS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDPS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VANDPS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VANDPS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VANDPS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBLENDMPDValidFormsNoError(t *testing.T) { + if _, err := VBLENDMPD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBLENDMPD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VBLENDMPD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBLENDMPD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VBLENDMPD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBLENDMPD_ZValidFormsNoError(t *testing.T) { + if _, err := VBLENDMPD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBLENDMPSValidFormsNoError(t *testing.T) { + if _, err := VBLENDMPS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBLENDMPS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VBLENDMPS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBLENDMPS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VBLENDMPS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBLENDMPS_ZValidFormsNoError(t *testing.T) { + if _, err := VBLENDMPS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDMPS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBLENDPDValidFormsNoError(t *testing.T) { + if _, err := VBLENDPD(opimm8, opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDPD(opimm8, opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDPD(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDPD(opimm8, opymm, opymm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVBLENDPSValidFormsNoError(t *testing.T) { + if _, err := VBLENDPS(opimm8, opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDPS(opimm8, opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDPS(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDPS(opimm8, opymm, opymm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVBLENDVPDValidFormsNoError(t *testing.T) { + if _, err := VBLENDVPD(opxmm, opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDVPD(opxmm, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDVPD(opymm, opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDVPD(opymm, opymm, opymm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVBLENDVPSValidFormsNoError(t *testing.T) { + if _, err := VBLENDVPS(opxmm, opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDVPS(opxmm, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDVPS(opymm, opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBLENDVPS(opymm, opymm, opymm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVBROADCASTF128ValidFormsNoError(t *testing.T) { + if _, err := VBROADCASTF128(opm128, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVBROADCASTF32X2ValidFormsNoError(t *testing.T) { + if _, err := VBROADCASTF32X2(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTF32X2(opm64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTF32X2(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTF32X2(opxmm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTF32X2(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTF32X2(opm64, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTF32X2(opxmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTF32X2(opxmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBROADCASTF32X2_ZValidFormsNoError(t *testing.T) { + if _, err := VBROADCASTF32X2_Z(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTF32X2_Z(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTF32X2_Z(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTF32X2_Z(opxmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBROADCASTF32X4ValidFormsNoError(t *testing.T) { + if _, err := VBROADCASTF32X4(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTF32X4(opm128, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTF32X4(opm128, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTF32X4(opm128, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBROADCASTF32X4_ZValidFormsNoError(t *testing.T) { + if _, err := VBROADCASTF32X4_Z(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTF32X4_Z(opm128, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBROADCASTF32X8ValidFormsNoError(t *testing.T) { + if _, err := VBROADCASTF32X8(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTF32X8(opm256, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBROADCASTF32X8_ZValidFormsNoError(t *testing.T) { + if _, err := VBROADCASTF32X8_Z(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBROADCASTF64X2ValidFormsNoError(t *testing.T) { + if _, err := VBROADCASTF64X2(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTF64X2(opm128, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTF64X2(opm128, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTF64X2(opm128, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBROADCASTF64X2_ZValidFormsNoError(t *testing.T) { + if _, err := VBROADCASTF64X2_Z(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTF64X2_Z(opm128, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBROADCASTF64X4ValidFormsNoError(t *testing.T) { + if _, err := VBROADCASTF64X4(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTF64X4(opm256, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBROADCASTF64X4_ZValidFormsNoError(t *testing.T) { + if _, err := VBROADCASTF64X4_Z(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBROADCASTI128ValidFormsNoError(t *testing.T) { + if _, err := VBROADCASTI128(opm128, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVBROADCASTI32X2ValidFormsNoError(t *testing.T) { + if _, err := VBROADCASTI32X2(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTI32X2(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTI32X2(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTI32X2(opm64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTI32X2(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTI32X2(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTI32X2(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTI32X2(opxmm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTI32X2(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTI32X2(opm64, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTI32X2(opxmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTI32X2(opxmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBROADCASTI32X2_ZValidFormsNoError(t *testing.T) { + if _, err := VBROADCASTI32X2_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTI32X2_Z(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTI32X2_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTI32X2_Z(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTI32X2_Z(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTI32X2_Z(opxmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBROADCASTI32X4ValidFormsNoError(t *testing.T) { + if _, err := VBROADCASTI32X4(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTI32X4(opm128, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTI32X4(opm128, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTI32X4(opm128, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBROADCASTI32X4_ZValidFormsNoError(t *testing.T) { + if _, err := VBROADCASTI32X4_Z(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTI32X4_Z(opm128, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBROADCASTI32X8ValidFormsNoError(t *testing.T) { + if _, err := VBROADCASTI32X8(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTI32X8(opm256, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBROADCASTI32X8_ZValidFormsNoError(t *testing.T) { + if _, err := VBROADCASTI32X8_Z(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBROADCASTI64X2ValidFormsNoError(t *testing.T) { + if _, err := VBROADCASTI64X2(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTI64X2(opm128, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTI64X2(opm128, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTI64X2(opm128, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBROADCASTI64X2_ZValidFormsNoError(t *testing.T) { + if _, err := VBROADCASTI64X2_Z(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTI64X2_Z(opm128, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBROADCASTI64X4ValidFormsNoError(t *testing.T) { + if _, err := VBROADCASTI64X4(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTI64X4(opm256, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBROADCASTI64X4_ZValidFormsNoError(t *testing.T) { + if _, err := VBROADCASTI64X4_Z(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBROADCASTSDValidFormsNoError(t *testing.T) { + if _, err := VBROADCASTSD(opxmm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTSD(opm64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTSD(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTSD(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTSD(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTSD(opm64, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTSD(opxmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTSD(opxmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBROADCASTSD_ZValidFormsNoError(t *testing.T) { + if _, err := VBROADCASTSD_Z(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTSD_Z(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTSD_Z(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTSD_Z(opxmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBROADCASTSSValidFormsNoError(t *testing.T) { + if _, err := VBROADCASTSS(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTSS(opxmm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTSS(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTSS(opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTSS(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTSS(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTSS(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTSS(opm32, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTSS(opxmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTSS(opxmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVBROADCASTSS_ZValidFormsNoError(t *testing.T) { + if _, err := VBROADCASTSS_Z(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTSS_Z(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTSS_Z(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VBROADCASTSS_Z(opxmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCMPPDValidFormsNoError(t *testing.T) { + if _, err := VCMPPD(opimm8, opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCMPPD(opimm8, opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCMPPD(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCMPPD(opimm8, opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCMPPD(opimm8, opm128, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPD(opimm8, opm128, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPD(opimm8, opm256, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPD(opimm8, opm256, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPD(opimm8, opxmm, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPD(opimm8, opxmm, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPD(opimm8, opymm, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPD(opimm8, opymm, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPD(opimm8, opm512, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPD(opimm8, opm512, opzmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPD(opimm8, opzmm, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPD(opimm8, opzmm, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVCMPPD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCMPPD_BCST(opimm8, opm64, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPD_BCST(opimm8, opm64, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPD_BCST(opimm8, opm64, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPD_BCST(opimm8, opm64, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPD_BCST(opimm8, opm64, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPD_BCST(opimm8, opm64, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVCMPPD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCMPPD_SAE(opimm8, opzmm, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPD_SAE(opimm8, opzmm, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVCMPPSValidFormsNoError(t *testing.T) { + if _, err := VCMPPS(opimm8, opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCMPPS(opimm8, opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCMPPS(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCMPPS(opimm8, opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCMPPS(opimm8, opm128, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPS(opimm8, opm128, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPS(opimm8, opm256, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPS(opimm8, opm256, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPS(opimm8, opxmm, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPS(opimm8, opxmm, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPS(opimm8, opymm, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPS(opimm8, opymm, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPS(opimm8, opm512, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPS(opimm8, opm512, opzmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPS(opimm8, opzmm, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPS(opimm8, opzmm, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVCMPPS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCMPPS_BCST(opimm8, opm32, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPS_BCST(opimm8, opm32, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPS_BCST(opimm8, opm32, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPS_BCST(opimm8, opm32, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPS_BCST(opimm8, opm32, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPS_BCST(opimm8, opm32, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVCMPPS_SAEValidFormsNoError(t *testing.T) { + if _, err := VCMPPS_SAE(opimm8, opzmm, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPPS_SAE(opimm8, opzmm, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVCMPSDValidFormsNoError(t *testing.T) { + if _, err := VCMPSD(opimm8, opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCMPSD(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCMPSD(opimm8, opm64, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPSD(opimm8, opm64, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPSD(opimm8, opxmm, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPSD(opimm8, opxmm, opxmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVCMPSD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCMPSD_SAE(opimm8, opxmm, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPSD_SAE(opimm8, opxmm, opxmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVCMPSSValidFormsNoError(t *testing.T) { + if _, err := VCMPSS(opimm8, opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCMPSS(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCMPSS(opimm8, opm32, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPSS(opimm8, opm32, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPSS(opimm8, opxmm, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPSS(opimm8, opxmm, opxmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVCMPSS_SAEValidFormsNoError(t *testing.T) { + if _, err := VCMPSS_SAE(opimm8, opxmm, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VCMPSS_SAE(opimm8, opxmm, opxmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVCOMISDValidFormsNoError(t *testing.T) { + if _, err := VCOMISD(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCOMISD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCOMISD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCOMISD_SAE(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCOMISSValidFormsNoError(t *testing.T) { + if _, err := VCOMISS(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCOMISS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCOMISS_SAEValidFormsNoError(t *testing.T) { + if _, err := VCOMISS_SAE(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCOMPRESSPDValidFormsNoError(t *testing.T) { + if _, err := VCOMPRESSPD(opxmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPD(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPD(opxmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPD(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPD(opymm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPD(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPD(opymm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPD(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPD(opzmm, opk, opm512); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPD(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPD(opzmm, opm512); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPD(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCOMPRESSPD_ZValidFormsNoError(t *testing.T) { + if _, err := VCOMPRESSPD_Z(opxmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPD_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPD_Z(opymm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPD_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPD_Z(opzmm, opk, opm512); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPD_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCOMPRESSPSValidFormsNoError(t *testing.T) { + if _, err := VCOMPRESSPS(opxmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPS(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPS(opxmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPS(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPS(opymm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPS(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPS(opymm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPS(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPS(opzmm, opk, opm512); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPS(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPS(opzmm, opm512); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPS(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCOMPRESSPS_ZValidFormsNoError(t *testing.T) { + if _, err := VCOMPRESSPS_Z(opxmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPS_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPS_Z(opymm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPS_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPS_Z(opzmm, opk, opm512); err != nil { + t.Fatal(err) + } + if _, err := VCOMPRESSPS_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTDQ2PDValidFormsNoError(t *testing.T) { + if _, err := VCVTDQ2PD(opm128, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PD(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PD(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PD(opxmm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PD(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PD(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PD(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PD(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PD(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PD(opm256, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PD(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PD(opymm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTDQ2PD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTDQ2PD_BCST(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PD_BCST(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PD_BCST(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PD_BCST(opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PD_BCST(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PD_BCST(opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTDQ2PD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTDQ2PD_BCST_Z(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PD_BCST_Z(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PD_BCST_Z(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTDQ2PD_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTDQ2PD_Z(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PD_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PD_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PD_Z(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PD_Z(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PD_Z(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTDQ2PSValidFormsNoError(t *testing.T) { + if _, err := VCVTDQ2PS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PS(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PS(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PS(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PS(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PS(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PS(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PS(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PS(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PS(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PS(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PS(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTDQ2PS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTDQ2PS_BCST(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PS_BCST(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PS_BCST(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PS_BCST(opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PS_BCST(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PS_BCST(opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTDQ2PS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTDQ2PS_BCST_Z(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PS_BCST_Z(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PS_BCST_Z(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTDQ2PS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTDQ2PS_RD_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PS_RD_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTDQ2PS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTDQ2PS_RD_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTDQ2PS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTDQ2PS_RN_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PS_RN_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTDQ2PS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTDQ2PS_RN_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTDQ2PS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTDQ2PS_RU_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PS_RU_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTDQ2PS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTDQ2PS_RU_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTDQ2PS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTDQ2PS_RZ_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PS_RZ_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTDQ2PS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTDQ2PS_RZ_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTDQ2PS_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTDQ2PS_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PS_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PS_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PS_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PS_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTDQ2PS_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2DQValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2DQ(opm512, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2DQ(opm512, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2DQ(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2DQ(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2DQXValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2DQX(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2DQX(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2DQX(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2DQX(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2DQX_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2DQX_BCST(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2DQX_BCST(opm64, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2DQX_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2DQX_BCST_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2DQX_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2DQX_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2DQX_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2DQYValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2DQY(opm256, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2DQY(opymm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2DQY(opm256, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2DQY(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2DQY_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2DQY_BCST(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2DQY_BCST(opm64, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2DQY_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2DQY_BCST_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2DQY_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2DQY_Z(opm256, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2DQY_Z(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2DQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2DQ_BCST(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2DQ_BCST(opm64, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2DQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2DQ_BCST_Z(opm64, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2DQ_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2DQ_RD_SAE(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2DQ_RD_SAE(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2DQ_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2DQ_RD_SAE_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2DQ_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2DQ_RN_SAE(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2DQ_RN_SAE(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2DQ_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2DQ_RN_SAE_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2DQ_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2DQ_RU_SAE(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2DQ_RU_SAE(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2DQ_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2DQ_RU_SAE_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2DQ_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2DQ_RZ_SAE(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2DQ_RZ_SAE(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2DQ_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2DQ_RZ_SAE_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2DQ_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2DQ_Z(opm512, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2DQ_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2PSValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2PS(opm512, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2PS(opm512, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2PS(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2PS(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2PSXValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2PSX(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2PSX(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2PSX(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2PSX(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2PSX_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2PSX_BCST(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2PSX_BCST(opm64, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2PSX_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2PSX_BCST_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2PSX_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2PSX_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2PSX_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2PSYValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2PSY(opm256, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2PSY(opymm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2PSY(opm256, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2PSY(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2PSY_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2PSY_BCST(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2PSY_BCST(opm64, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2PSY_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2PSY_BCST_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2PSY_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2PSY_Z(opm256, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2PSY_Z(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2PS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2PS_BCST(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2PS_BCST(opm64, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2PS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2PS_BCST_Z(opm64, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2PS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2PS_RD_SAE(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2PS_RD_SAE(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2PS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2PS_RD_SAE_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2PS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2PS_RN_SAE(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2PS_RN_SAE(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2PS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2PS_RN_SAE_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2PS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2PS_RU_SAE(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2PS_RU_SAE(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2PS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2PS_RU_SAE_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2PS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2PS_RZ_SAE(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2PS_RZ_SAE(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2PS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2PS_RZ_SAE_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2PS_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2PS_Z(opm512, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2PS_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2QQValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2QQ(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2QQ(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2QQ(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2QQ(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2QQ(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2QQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2QQ(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2QQ(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2QQ(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2QQ(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2QQ(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2QQ(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2QQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2QQ_BCST(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2QQ_BCST(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2QQ_BCST(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2QQ_BCST(opm64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2QQ_BCST(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2QQ_BCST(opm64, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2QQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2QQ_BCST_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2QQ_BCST_Z(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2QQ_BCST_Z(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2QQ_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2QQ_RD_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2QQ_RD_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2QQ_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2QQ_RD_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2QQ_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2QQ_RN_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2QQ_RN_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2QQ_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2QQ_RN_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2QQ_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2QQ_RU_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2QQ_RU_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2QQ_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2QQ_RU_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2QQ_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2QQ_RZ_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2QQ_RZ_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2QQ_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2QQ_RZ_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2QQ_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2QQ_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2QQ_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2QQ_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2QQ_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2QQ_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2QQ_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UDQValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UDQ(opm512, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UDQ(opm512, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UDQ(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UDQ(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UDQXValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UDQX(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UDQX(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UDQX(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UDQX(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UDQX_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UDQX_BCST(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UDQX_BCST(opm64, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UDQX_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UDQX_BCST_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UDQX_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UDQX_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UDQX_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UDQYValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UDQY(opm256, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UDQY(opm256, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UDQY(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UDQY(opymm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UDQY_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UDQY_BCST(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UDQY_BCST(opm64, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UDQY_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UDQY_BCST_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UDQY_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UDQY_Z(opm256, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UDQY_Z(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UDQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UDQ_BCST(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UDQ_BCST(opm64, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UDQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UDQ_BCST_Z(opm64, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UDQ_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UDQ_RD_SAE(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UDQ_RD_SAE(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UDQ_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UDQ_RD_SAE_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UDQ_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UDQ_RN_SAE(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UDQ_RN_SAE(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UDQ_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UDQ_RN_SAE_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UDQ_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UDQ_RU_SAE(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UDQ_RU_SAE(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UDQ_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UDQ_RU_SAE_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UDQ_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UDQ_RZ_SAE(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UDQ_RZ_SAE(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UDQ_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UDQ_RZ_SAE_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UDQ_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UDQ_Z(opm512, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UDQ_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UQQValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UQQ(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UQQ(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UQQ(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UQQ(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UQQ(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UQQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UQQ(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UQQ(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UQQ(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UQQ(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UQQ(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UQQ(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UQQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UQQ_BCST(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UQQ_BCST(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UQQ_BCST(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UQQ_BCST(opm64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UQQ_BCST(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UQQ_BCST(opm64, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UQQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UQQ_BCST_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UQQ_BCST_Z(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UQQ_BCST_Z(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UQQ_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UQQ_RD_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UQQ_RD_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UQQ_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UQQ_RD_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UQQ_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UQQ_RN_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UQQ_RN_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UQQ_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UQQ_RN_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UQQ_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UQQ_RU_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UQQ_RU_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UQQ_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UQQ_RU_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UQQ_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UQQ_RZ_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UQQ_RZ_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UQQ_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UQQ_RZ_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPD2UQQ_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPD2UQQ_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UQQ_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UQQ_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UQQ_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UQQ_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPD2UQQ_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPH2PSValidFormsNoError(t *testing.T) { + if _, err := VCVTPH2PS(opm128, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPH2PS(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPH2PS(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPH2PS(opxmm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPH2PS(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPH2PS(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPH2PS(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPH2PS(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPH2PS(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPH2PS(opm256, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPH2PS(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPH2PS(opymm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPH2PS_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPH2PS_SAE(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPH2PS_SAE(opymm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPH2PS_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPH2PS_SAE_Z(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPH2PS_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPH2PS_Z(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPH2PS_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPH2PS_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPH2PS_Z(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPH2PS_Z(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPH2PS_Z(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2DQValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2DQ(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2DQ(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2DQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2DQ(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2DQ(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2DQ(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2DQ(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2DQ(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2DQ(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2DQ(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2DQ(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2DQ(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2DQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2DQ_BCST(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2DQ_BCST(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2DQ_BCST(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2DQ_BCST(opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2DQ_BCST(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2DQ_BCST(opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2DQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2DQ_BCST_Z(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2DQ_BCST_Z(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2DQ_BCST_Z(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2DQ_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2DQ_RD_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2DQ_RD_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2DQ_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2DQ_RD_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2DQ_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2DQ_RN_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2DQ_RN_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2DQ_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2DQ_RN_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2DQ_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2DQ_RU_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2DQ_RU_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2DQ_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2DQ_RU_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2DQ_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2DQ_RZ_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2DQ_RZ_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2DQ_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2DQ_RZ_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2DQ_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2DQ_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2DQ_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2DQ_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2DQ_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2DQ_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2DQ_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2PDValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2PD(opm128, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PD(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PD(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PD(opxmm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PD(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PD(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PD(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PD(opm256, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PD(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PD(opymm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PD(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PD(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2PD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2PD_BCST(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PD_BCST(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PD_BCST(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PD_BCST(opm32, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PD_BCST(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PD_BCST(opm32, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2PD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2PD_BCST_Z(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PD_BCST_Z(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PD_BCST_Z(opm32, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2PD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2PD_SAE(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PD_SAE(opymm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2PD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2PD_SAE_Z(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2PD_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2PD_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PD_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PD_Z(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PD_Z(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PD_Z(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PD_Z(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2PHValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2PH(opimm8, opxmm, opm64); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PH(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PH(opimm8, opymm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PH(opimm8, opymm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PH(opimm8, opxmm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PH(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PH(opimm8, opymm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PH(opimm8, opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PH(opimm8, opzmm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PH(opimm8, opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PH(opimm8, opzmm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PH(opimm8, opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2PH_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2PH_SAE(opimm8, opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PH_SAE(opimm8, opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2PH_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2PH_SAE_Z(opimm8, opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2PH_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2PH_Z(opimm8, opxmm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PH_Z(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PH_Z(opimm8, opymm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PH_Z(opimm8, opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PH_Z(opimm8, opzmm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2PH_Z(opimm8, opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2QQValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2QQ(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2QQ(opm128, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2QQ(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2QQ(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2QQ(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2QQ(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2QQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2QQ(opxmm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2QQ(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2QQ(opm256, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2QQ(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2QQ(opymm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2QQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2QQ_BCST(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2QQ_BCST(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2QQ_BCST(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2QQ_BCST(opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2QQ_BCST(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2QQ_BCST(opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2QQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2QQ_BCST_Z(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2QQ_BCST_Z(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2QQ_BCST_Z(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2QQ_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2QQ_RD_SAE(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2QQ_RD_SAE(opymm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2QQ_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2QQ_RD_SAE_Z(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2QQ_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2QQ_RN_SAE(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2QQ_RN_SAE(opymm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2QQ_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2QQ_RN_SAE_Z(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2QQ_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2QQ_RU_SAE(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2QQ_RU_SAE(opymm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2QQ_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2QQ_RU_SAE_Z(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2QQ_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2QQ_RZ_SAE(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2QQ_RZ_SAE(opymm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2QQ_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2QQ_RZ_SAE_Z(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2QQ_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2QQ_Z(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2QQ_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2QQ_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2QQ_Z(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2QQ_Z(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2QQ_Z(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2UDQValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2UDQ(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UDQ(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UDQ(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UDQ(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UDQ(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UDQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UDQ(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UDQ(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UDQ(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UDQ(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UDQ(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UDQ(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2UDQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2UDQ_BCST(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UDQ_BCST(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UDQ_BCST(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UDQ_BCST(opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UDQ_BCST(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UDQ_BCST(opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2UDQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2UDQ_BCST_Z(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UDQ_BCST_Z(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UDQ_BCST_Z(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2UDQ_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2UDQ_RD_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UDQ_RD_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2UDQ_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2UDQ_RD_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2UDQ_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2UDQ_RN_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UDQ_RN_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2UDQ_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2UDQ_RN_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2UDQ_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2UDQ_RU_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UDQ_RU_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2UDQ_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2UDQ_RU_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2UDQ_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2UDQ_RZ_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UDQ_RZ_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2UDQ_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2UDQ_RZ_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2UDQ_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2UDQ_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UDQ_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UDQ_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UDQ_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UDQ_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UDQ_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2UQQValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2UQQ(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UQQ(opm128, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UQQ(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UQQ(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UQQ(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UQQ(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UQQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UQQ(opxmm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UQQ(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UQQ(opm256, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UQQ(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UQQ(opymm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2UQQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2UQQ_BCST(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UQQ_BCST(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UQQ_BCST(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UQQ_BCST(opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UQQ_BCST(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UQQ_BCST(opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2UQQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2UQQ_BCST_Z(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UQQ_BCST_Z(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UQQ_BCST_Z(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2UQQ_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2UQQ_RD_SAE(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UQQ_RD_SAE(opymm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2UQQ_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2UQQ_RD_SAE_Z(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2UQQ_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2UQQ_RN_SAE(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UQQ_RN_SAE(opymm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2UQQ_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2UQQ_RN_SAE_Z(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2UQQ_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2UQQ_RU_SAE(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UQQ_RU_SAE(opymm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2UQQ_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2UQQ_RU_SAE_Z(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2UQQ_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2UQQ_RZ_SAE(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UQQ_RZ_SAE(opymm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2UQQ_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2UQQ_RZ_SAE_Z(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTPS2UQQ_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTPS2UQQ_Z(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UQQ_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UQQ_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UQQ_Z(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UQQ_Z(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTPS2UQQ_Z(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PDValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PD(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PD(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PD(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PD(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PD(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PD(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PD(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PD(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PD(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PD(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PD(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PD_BCST(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PD_BCST(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PD_BCST(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PD_BCST(opm64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PD_BCST(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PD_BCST(opm64, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PD_BCST_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PD_BCST_Z(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PD_BCST_Z(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PD_RD_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PD_RD_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PD_RD_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PD_RN_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PD_RN_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PD_RN_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PD_RU_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PD_RU_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PD_RU_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PD_RZ_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PD_RZ_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PD_RZ_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PD_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PD_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PD_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PD_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PD_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PD_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PD_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PSValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PS(opm512, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PS(opm512, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PS(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PS(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PSXValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PSX(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PSX(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PSX(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PSX(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PSX_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PSX_BCST(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PSX_BCST(opm64, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PSX_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PSX_BCST_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PSX_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PSX_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PSX_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PSYValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PSY(opm256, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PSY(opm256, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PSY(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PSY(opymm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PSY_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PSY_BCST(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PSY_BCST(opm64, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PSY_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PSY_BCST_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PSY_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PSY_Z(opm256, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PSY_Z(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PS_BCST(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PS_BCST(opm64, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PS_BCST_Z(opm64, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PS_RD_SAE(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PS_RD_SAE(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PS_RD_SAE_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PS_RN_SAE(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PS_RN_SAE(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PS_RN_SAE_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PS_RU_SAE(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PS_RU_SAE(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PS_RU_SAE_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PS_RZ_SAE(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PS_RZ_SAE(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PS_RZ_SAE_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTQQ2PS_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTQQ2PS_Z(opm512, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTQQ2PS_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSD2SIValidFormsNoError(t *testing.T) { + if _, err := VCVTSD2SI(opm64, opr32); err != nil { + t.Fatal(err) + } + if _, err := VCVTSD2SI(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSD2SIQValidFormsNoError(t *testing.T) { + if _, err := VCVTSD2SIQ(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := VCVTSD2SIQ(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSD2SIQ_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSD2SIQ_RD_SAE(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSD2SIQ_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSD2SIQ_RN_SAE(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSD2SIQ_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSD2SIQ_RU_SAE(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSD2SIQ_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSD2SIQ_RZ_SAE(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSD2SI_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSD2SI_RD_SAE(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSD2SI_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSD2SI_RN_SAE(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSD2SI_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSD2SI_RU_SAE(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSD2SI_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSD2SI_RZ_SAE(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSD2SSValidFormsNoError(t *testing.T) { + if _, err := VCVTSD2SS(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTSD2SS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTSD2SS(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTSD2SS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSD2SS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSD2SS_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTSD2SS_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSD2SS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTSD2SS_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSD2SS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSD2SS_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTSD2SS_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSD2SS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTSD2SS_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSD2SS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSD2SS_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTSD2SS_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSD2SS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTSD2SS_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSD2SS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSD2SS_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTSD2SS_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSD2SS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTSD2SS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSD2SS_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTSD2SS_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTSD2SS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSD2USILValidFormsNoError(t *testing.T) { + if _, err := VCVTSD2USIL(opm64, opr32); err != nil { + t.Fatal(err) + } + if _, err := VCVTSD2USIL(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSD2USIL_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSD2USIL_RD_SAE(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSD2USIL_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSD2USIL_RN_SAE(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSD2USIL_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSD2USIL_RU_SAE(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSD2USIL_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSD2USIL_RZ_SAE(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSD2USIQValidFormsNoError(t *testing.T) { + if _, err := VCVTSD2USIQ(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := VCVTSD2USIQ(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSD2USIQ_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSD2USIQ_RD_SAE(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSD2USIQ_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSD2USIQ_RN_SAE(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSD2USIQ_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSD2USIQ_RU_SAE(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSD2USIQ_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSD2USIQ_RZ_SAE(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSI2SDLValidFormsNoError(t *testing.T) { + if _, err := VCVTSI2SDL(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTSI2SDL(opr32, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSI2SDQValidFormsNoError(t *testing.T) { + if _, err := VCVTSI2SDQ(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTSI2SDQ(opr64, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSI2SDQ_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSI2SDQ_RD_SAE(opr64, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSI2SDQ_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSI2SDQ_RN_SAE(opr64, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSI2SDQ_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSI2SDQ_RU_SAE(opr64, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSI2SDQ_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSI2SDQ_RZ_SAE(opr64, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSI2SSLValidFormsNoError(t *testing.T) { + if _, err := VCVTSI2SSL(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTSI2SSL(opr32, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSI2SSL_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSI2SSL_RD_SAE(opr32, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSI2SSL_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSI2SSL_RN_SAE(opr32, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSI2SSL_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSI2SSL_RU_SAE(opr32, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSI2SSL_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSI2SSL_RZ_SAE(opr32, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSI2SSQValidFormsNoError(t *testing.T) { + if _, err := VCVTSI2SSQ(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTSI2SSQ(opr64, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSI2SSQ_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSI2SSQ_RD_SAE(opr64, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSI2SSQ_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSI2SSQ_RN_SAE(opr64, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSI2SSQ_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSI2SSQ_RU_SAE(opr64, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSI2SSQ_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSI2SSQ_RZ_SAE(opr64, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSS2SDValidFormsNoError(t *testing.T) { + if _, err := VCVTSS2SD(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTSS2SD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTSS2SD(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTSS2SD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSS2SD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSS2SD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTSS2SD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSS2SD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTSS2SD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSS2SD_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTSS2SD_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTSS2SD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSS2SIValidFormsNoError(t *testing.T) { + if _, err := VCVTSS2SI(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := VCVTSS2SI(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSS2SIQValidFormsNoError(t *testing.T) { + if _, err := VCVTSS2SIQ(opm32, opr64); err != nil { + t.Fatal(err) + } + if _, err := VCVTSS2SIQ(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSS2SIQ_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSS2SIQ_RD_SAE(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSS2SIQ_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSS2SIQ_RN_SAE(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSS2SIQ_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSS2SIQ_RU_SAE(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSS2SIQ_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSS2SIQ_RZ_SAE(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSS2SI_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSS2SI_RD_SAE(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSS2SI_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSS2SI_RN_SAE(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSS2SI_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSS2SI_RU_SAE(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSS2SI_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSS2SI_RZ_SAE(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSS2USILValidFormsNoError(t *testing.T) { + if _, err := VCVTSS2USIL(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := VCVTSS2USIL(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSS2USIL_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSS2USIL_RD_SAE(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSS2USIL_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSS2USIL_RN_SAE(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSS2USIL_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSS2USIL_RU_SAE(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSS2USIL_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSS2USIL_RZ_SAE(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSS2USIQValidFormsNoError(t *testing.T) { + if _, err := VCVTSS2USIQ(opm32, opr64); err != nil { + t.Fatal(err) + } + if _, err := VCVTSS2USIQ(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSS2USIQ_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSS2USIQ_RD_SAE(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSS2USIQ_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSS2USIQ_RN_SAE(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSS2USIQ_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSS2USIQ_RU_SAE(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestVCVTSS2USIQ_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTSS2USIQ_RZ_SAE(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2DQValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2DQ(opm512, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2DQ(opm512, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2DQ(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2DQ(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2DQXValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2DQX(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2DQX(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2DQX(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2DQX(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2DQX_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2DQX_BCST(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2DQX_BCST(opm64, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2DQX_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2DQX_BCST_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2DQX_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2DQX_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2DQX_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2DQYValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2DQY(opm256, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2DQY(opymm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2DQY(opm256, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2DQY(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2DQY_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2DQY_BCST(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2DQY_BCST(opm64, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2DQY_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2DQY_BCST_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2DQY_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2DQY_Z(opm256, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2DQY_Z(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2DQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2DQ_BCST(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2DQ_BCST(opm64, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2DQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2DQ_BCST_Z(opm64, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2DQ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2DQ_SAE(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2DQ_SAE(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2DQ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2DQ_SAE_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2DQ_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2DQ_Z(opm512, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2DQ_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2QQValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2QQ(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2QQ(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2QQ(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2QQ(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2QQ(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2QQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2QQ(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2QQ(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2QQ(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2QQ(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2QQ(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2QQ(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2QQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2QQ_BCST(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2QQ_BCST(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2QQ_BCST(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2QQ_BCST(opm64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2QQ_BCST(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2QQ_BCST(opm64, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2QQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2QQ_BCST_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2QQ_BCST_Z(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2QQ_BCST_Z(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2QQ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2QQ_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2QQ_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2QQ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2QQ_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2QQ_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2QQ_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2QQ_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2QQ_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2QQ_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2QQ_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2QQ_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2UDQValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2UDQ(opm512, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UDQ(opm512, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UDQ(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UDQ(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2UDQXValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2UDQX(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UDQX(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UDQX(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UDQX(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2UDQX_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2UDQX_BCST(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UDQX_BCST(opm64, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2UDQX_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2UDQX_BCST_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2UDQX_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2UDQX_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UDQX_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2UDQYValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2UDQY(opm256, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UDQY(opm256, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UDQY(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UDQY(opymm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2UDQY_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2UDQY_BCST(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UDQY_BCST(opm64, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2UDQY_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2UDQY_BCST_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2UDQY_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2UDQY_Z(opm256, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UDQY_Z(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2UDQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2UDQ_BCST(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UDQ_BCST(opm64, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2UDQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2UDQ_BCST_Z(opm64, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2UDQ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2UDQ_SAE(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UDQ_SAE(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2UDQ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2UDQ_SAE_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2UDQ_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2UDQ_Z(opm512, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UDQ_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2UQQValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2UQQ(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UQQ(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UQQ(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UQQ(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UQQ(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UQQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UQQ(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UQQ(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UQQ(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UQQ(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UQQ(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UQQ(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2UQQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2UQQ_BCST(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UQQ_BCST(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UQQ_BCST(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UQQ_BCST(opm64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UQQ_BCST(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UQQ_BCST(opm64, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2UQQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2UQQ_BCST_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UQQ_BCST_Z(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UQQ_BCST_Z(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2UQQ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2UQQ_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UQQ_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2UQQ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2UQQ_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPD2UQQ_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPD2UQQ_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UQQ_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UQQ_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UQQ_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UQQ_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPD2UQQ_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPS2DQValidFormsNoError(t *testing.T) { + if _, err := VCVTTPS2DQ(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2DQ(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2DQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2DQ(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2DQ(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2DQ(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2DQ(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2DQ(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2DQ(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2DQ(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2DQ(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2DQ(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPS2DQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTTPS2DQ_BCST(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2DQ_BCST(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2DQ_BCST(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2DQ_BCST(opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2DQ_BCST(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2DQ_BCST(opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPS2DQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPS2DQ_BCST_Z(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2DQ_BCST_Z(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2DQ_BCST_Z(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPS2DQ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTTPS2DQ_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2DQ_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPS2DQ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPS2DQ_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPS2DQ_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPS2DQ_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2DQ_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2DQ_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2DQ_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2DQ_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2DQ_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPS2QQValidFormsNoError(t *testing.T) { + if _, err := VCVTTPS2QQ(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2QQ(opm128, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2QQ(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2QQ(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2QQ(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2QQ(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2QQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2QQ(opxmm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2QQ(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2QQ(opm256, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2QQ(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2QQ(opymm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPS2QQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTTPS2QQ_BCST(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2QQ_BCST(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2QQ_BCST(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2QQ_BCST(opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2QQ_BCST(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2QQ_BCST(opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPS2QQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPS2QQ_BCST_Z(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2QQ_BCST_Z(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2QQ_BCST_Z(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPS2QQ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTTPS2QQ_SAE(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2QQ_SAE(opymm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPS2QQ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPS2QQ_SAE_Z(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPS2QQ_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPS2QQ_Z(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2QQ_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2QQ_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2QQ_Z(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2QQ_Z(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2QQ_Z(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPS2UDQValidFormsNoError(t *testing.T) { + if _, err := VCVTTPS2UDQ(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UDQ(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UDQ(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UDQ(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UDQ(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UDQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UDQ(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UDQ(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UDQ(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UDQ(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UDQ(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UDQ(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPS2UDQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTTPS2UDQ_BCST(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UDQ_BCST(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UDQ_BCST(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UDQ_BCST(opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UDQ_BCST(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UDQ_BCST(opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPS2UDQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPS2UDQ_BCST_Z(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UDQ_BCST_Z(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UDQ_BCST_Z(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPS2UDQ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTTPS2UDQ_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UDQ_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPS2UDQ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPS2UDQ_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPS2UDQ_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPS2UDQ_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UDQ_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UDQ_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UDQ_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UDQ_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UDQ_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPS2UQQValidFormsNoError(t *testing.T) { + if _, err := VCVTTPS2UQQ(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UQQ(opm128, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UQQ(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UQQ(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UQQ(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UQQ(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UQQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UQQ(opxmm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UQQ(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UQQ(opm256, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UQQ(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UQQ(opymm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPS2UQQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTTPS2UQQ_BCST(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UQQ_BCST(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UQQ_BCST(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UQQ_BCST(opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UQQ_BCST(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UQQ_BCST(opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPS2UQQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPS2UQQ_BCST_Z(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UQQ_BCST_Z(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UQQ_BCST_Z(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPS2UQQ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTTPS2UQQ_SAE(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UQQ_SAE(opymm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPS2UQQ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPS2UQQ_SAE_Z(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTPS2UQQ_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTTPS2UQQ_Z(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UQQ_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UQQ_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UQQ_Z(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UQQ_Z(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTTPS2UQQ_Z(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTSD2SIValidFormsNoError(t *testing.T) { + if _, err := VCVTTSD2SI(opm64, opr32); err != nil { + t.Fatal(err) + } + if _, err := VCVTTSD2SI(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTSD2SIQValidFormsNoError(t *testing.T) { + if _, err := VCVTTSD2SIQ(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := VCVTTSD2SIQ(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTSD2SIQ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTTSD2SIQ_SAE(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTSD2SI_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTTSD2SI_SAE(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTSD2USILValidFormsNoError(t *testing.T) { + if _, err := VCVTTSD2USIL(opm64, opr32); err != nil { + t.Fatal(err) + } + if _, err := VCVTTSD2USIL(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTSD2USIL_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTTSD2USIL_SAE(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTSD2USIQValidFormsNoError(t *testing.T) { + if _, err := VCVTTSD2USIQ(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := VCVTTSD2USIQ(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTSD2USIQ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTTSD2USIQ_SAE(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTSS2SIValidFormsNoError(t *testing.T) { + if _, err := VCVTTSS2SI(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := VCVTTSS2SI(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTSS2SIQValidFormsNoError(t *testing.T) { + if _, err := VCVTTSS2SIQ(opm32, opr64); err != nil { + t.Fatal(err) + } + if _, err := VCVTTSS2SIQ(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTSS2SIQ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTTSS2SIQ_SAE(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTSS2SI_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTTSS2SI_SAE(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTSS2USILValidFormsNoError(t *testing.T) { + if _, err := VCVTTSS2USIL(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := VCVTTSS2USIL(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTSS2USIL_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTTSS2USIL_SAE(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTSS2USIQValidFormsNoError(t *testing.T) { + if _, err := VCVTTSS2USIQ(opm32, opr64); err != nil { + t.Fatal(err) + } + if _, err := VCVTTSS2USIQ(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestVCVTTSS2USIQ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTTSS2USIQ_SAE(opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUDQ2PDValidFormsNoError(t *testing.T) { + if _, err := VCVTUDQ2PD(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PD(opm128, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PD(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PD(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PD(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PD(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PD(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PD(opxmm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PD(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PD(opm256, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PD(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PD(opymm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUDQ2PD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTUDQ2PD_BCST(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PD_BCST(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PD_BCST(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PD_BCST(opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PD_BCST(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PD_BCST(opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUDQ2PD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTUDQ2PD_BCST_Z(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PD_BCST_Z(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PD_BCST_Z(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUDQ2PD_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTUDQ2PD_Z(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PD_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PD_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PD_Z(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PD_Z(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PD_Z(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUDQ2PSValidFormsNoError(t *testing.T) { + if _, err := VCVTUDQ2PS(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PS(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PS(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PS(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PS(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PS(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PS(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PS(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PS(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PS(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PS(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUDQ2PS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTUDQ2PS_BCST(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PS_BCST(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PS_BCST(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PS_BCST(opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PS_BCST(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PS_BCST(opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUDQ2PS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTUDQ2PS_BCST_Z(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PS_BCST_Z(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PS_BCST_Z(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUDQ2PS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTUDQ2PS_RD_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PS_RD_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUDQ2PS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTUDQ2PS_RD_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUDQ2PS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTUDQ2PS_RN_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PS_RN_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUDQ2PS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTUDQ2PS_RN_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUDQ2PS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTUDQ2PS_RU_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PS_RU_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUDQ2PS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTUDQ2PS_RU_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUDQ2PS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTUDQ2PS_RZ_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PS_RZ_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUDQ2PS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTUDQ2PS_RZ_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUDQ2PS_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTUDQ2PS_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PS_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PS_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PS_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PS_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUDQ2PS_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PDValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PD(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PD(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PD(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PD(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PD(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PD(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PD(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PD(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PD(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PD(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PD(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PD_BCST(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PD_BCST(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PD_BCST(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PD_BCST(opm64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PD_BCST(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PD_BCST(opm64, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PD_BCST_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PD_BCST_Z(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PD_BCST_Z(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PD_RD_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PD_RD_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PD_RD_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PD_RN_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PD_RN_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PD_RN_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PD_RU_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PD_RU_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PD_RU_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PD_RZ_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PD_RZ_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PD_RZ_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PD_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PD_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PD_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PD_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PD_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PD_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PD_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PSValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PS(opm512, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PS(opm512, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PS(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PS(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PSXValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PSX(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PSX(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PSX(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PSX(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PSX_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PSX_BCST(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PSX_BCST(opm64, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PSX_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PSX_BCST_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PSX_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PSX_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PSX_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PSYValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PSY(opm256, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PSY(opm256, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PSY(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PSY(opymm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PSY_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PSY_BCST(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PSY_BCST(opm64, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PSY_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PSY_BCST_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PSY_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PSY_Z(opm256, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PSY_Z(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PS_BCST(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PS_BCST(opm64, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PS_BCST_Z(opm64, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PS_RD_SAE(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PS_RD_SAE(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PS_RD_SAE_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PS_RN_SAE(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PS_RN_SAE(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PS_RN_SAE_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PS_RU_SAE(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PS_RU_SAE(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PS_RU_SAE_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PS_RZ_SAE(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PS_RZ_SAE(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PS_RZ_SAE_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUQQ2PS_ZValidFormsNoError(t *testing.T) { + if _, err := VCVTUQQ2PS_Z(opm512, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUQQ2PS_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUSI2SDLValidFormsNoError(t *testing.T) { + if _, err := VCVTUSI2SDL(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUSI2SDL(opr32, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUSI2SDQValidFormsNoError(t *testing.T) { + if _, err := VCVTUSI2SDQ(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUSI2SDQ(opr64, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUSI2SDQ_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTUSI2SDQ_RD_SAE(opr64, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUSI2SDQ_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTUSI2SDQ_RN_SAE(opr64, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUSI2SDQ_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTUSI2SDQ_RU_SAE(opr64, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUSI2SDQ_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTUSI2SDQ_RZ_SAE(opr64, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUSI2SSLValidFormsNoError(t *testing.T) { + if _, err := VCVTUSI2SSL(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUSI2SSL(opr32, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUSI2SSL_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTUSI2SSL_RD_SAE(opr32, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUSI2SSL_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTUSI2SSL_RN_SAE(opr32, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUSI2SSL_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTUSI2SSL_RU_SAE(opr32, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUSI2SSL_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTUSI2SSL_RZ_SAE(opr32, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUSI2SSQValidFormsNoError(t *testing.T) { + if _, err := VCVTUSI2SSQ(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VCVTUSI2SSQ(opr64, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUSI2SSQ_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTUSI2SSQ_RD_SAE(opr64, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUSI2SSQ_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTUSI2SSQ_RN_SAE(opr64, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUSI2SSQ_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTUSI2SSQ_RU_SAE(opr64, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVCVTUSI2SSQ_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VCVTUSI2SSQ_RZ_SAE(opr64, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVDBPSADBWValidFormsNoError(t *testing.T) { + if _, err := VDBPSADBW(opimm8, opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDBPSADBW(opimm8, opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDBPSADBW(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VDBPSADBW(opimm8, opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VDBPSADBW(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDBPSADBW(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDBPSADBW(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VDBPSADBW(opimm8, opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VDBPSADBW(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VDBPSADBW(opimm8, opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VDBPSADBW(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VDBPSADBW(opimm8, opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVDBPSADBW_ZValidFormsNoError(t *testing.T) { + if _, err := VDBPSADBW_Z(opimm8, opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDBPSADBW_Z(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VDBPSADBW_Z(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDBPSADBW_Z(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VDBPSADBW_Z(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VDBPSADBW_Z(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVPDValidFormsNoError(t *testing.T) { + if _, err := VDIVPD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVPD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VDIVPD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVPD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VDIVPD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVPD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VDIVPD_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPD_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVPD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VDIVPD_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVPD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VDIVPD_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPD_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVPD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VDIVPD_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVPD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VDIVPD_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPD_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVPD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VDIVPD_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVPD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VDIVPD_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPD_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVPD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VDIVPD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVPD_ZValidFormsNoError(t *testing.T) { + if _, err := VDIVPD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVPSValidFormsNoError(t *testing.T) { + if _, err := VDIVPS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVPS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VDIVPS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVPS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VDIVPS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVPS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VDIVPS_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPS_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVPS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VDIVPS_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVPS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VDIVPS_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPS_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVPS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VDIVPS_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVPS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VDIVPS_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPS_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVPS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VDIVPS_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVPS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VDIVPS_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPS_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVPS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VDIVPS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVPS_ZValidFormsNoError(t *testing.T) { + if _, err := VDIVPS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVPS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVSDValidFormsNoError(t *testing.T) { + if _, err := VDIVSD(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVSD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVSD(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVSD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVSD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VDIVSD_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVSD_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVSD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VDIVSD_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVSD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VDIVSD_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVSD_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVSD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VDIVSD_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVSD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VDIVSD_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVSD_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVSD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VDIVSD_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVSD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VDIVSD_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVSD_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVSD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VDIVSD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVSD_ZValidFormsNoError(t *testing.T) { + if _, err := VDIVSD_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVSD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVSSValidFormsNoError(t *testing.T) { + if _, err := VDIVSS(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVSS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVSS(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVSS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVSS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VDIVSS_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVSS_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVSS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VDIVSS_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVSS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VDIVSS_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVSS_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVSS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VDIVSS_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVSS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VDIVSS_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVSS_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVSS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VDIVSS_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVSS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VDIVSS_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVSS_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVSS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VDIVSS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVDIVSS_ZValidFormsNoError(t *testing.T) { + if _, err := VDIVSS_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDIVSS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVDPPDValidFormsNoError(t *testing.T) { + if _, err := VDPPD(opimm8, opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDPPD(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVDPPSValidFormsNoError(t *testing.T) { + if _, err := VDPPS(opimm8, opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDPPS(opimm8, opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VDPPS(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VDPPS(opimm8, opymm, opymm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVEXP2PDValidFormsNoError(t *testing.T) { + if _, err := VEXP2PD(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VEXP2PD(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VEXP2PD(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VEXP2PD(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVEXP2PD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VEXP2PD_BCST(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VEXP2PD_BCST(opm64, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVEXP2PD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VEXP2PD_BCST_Z(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVEXP2PD_SAEValidFormsNoError(t *testing.T) { + if _, err := VEXP2PD_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VEXP2PD_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVEXP2PD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VEXP2PD_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVEXP2PD_ZValidFormsNoError(t *testing.T) { + if _, err := VEXP2PD_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VEXP2PD_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVEXP2PSValidFormsNoError(t *testing.T) { + if _, err := VEXP2PS(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VEXP2PS(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VEXP2PS(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VEXP2PS(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVEXP2PS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VEXP2PS_BCST(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VEXP2PS_BCST(opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVEXP2PS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VEXP2PS_BCST_Z(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVEXP2PS_SAEValidFormsNoError(t *testing.T) { + if _, err := VEXP2PS_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VEXP2PS_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVEXP2PS_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VEXP2PS_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVEXP2PS_ZValidFormsNoError(t *testing.T) { + if _, err := VEXP2PS_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VEXP2PS_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVEXPANDPDValidFormsNoError(t *testing.T) { + if _, err := VEXPANDPD(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPD(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPD(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPD(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPD(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPD(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPD(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPD(opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPD(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPD(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVEXPANDPD_ZValidFormsNoError(t *testing.T) { + if _, err := VEXPANDPD_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPD_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPD_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPD_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPD_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPD_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVEXPANDPSValidFormsNoError(t *testing.T) { + if _, err := VEXPANDPS(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPS(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPS(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPS(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPS(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPS(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPS(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPS(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPS(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPS(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPS(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVEXPANDPS_ZValidFormsNoError(t *testing.T) { + if _, err := VEXPANDPS_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPS_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPS_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPS_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPS_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VEXPANDPS_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVEXTRACTF128ValidFormsNoError(t *testing.T) { + if _, err := VEXTRACTF128(opimm8, opymm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTF128(opimm8, opymm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVEXTRACTF32X4ValidFormsNoError(t *testing.T) { + if _, err := VEXTRACTF32X4(opimm8, opymm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTF32X4(opimm8, opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTF32X4(opimm8, opymm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTF32X4(opimm8, opymm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTF32X4(opimm8, opzmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTF32X4(opimm8, opzmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTF32X4(opimm8, opzmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTF32X4(opimm8, opzmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVEXTRACTF32X4_ZValidFormsNoError(t *testing.T) { + if _, err := VEXTRACTF32X4_Z(opimm8, opymm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTF32X4_Z(opimm8, opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTF32X4_Z(opimm8, opzmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTF32X4_Z(opimm8, opzmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVEXTRACTF32X8ValidFormsNoError(t *testing.T) { + if _, err := VEXTRACTF32X8(opimm8, opzmm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTF32X8(opimm8, opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTF32X8(opimm8, opzmm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTF32X8(opimm8, opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVEXTRACTF32X8_ZValidFormsNoError(t *testing.T) { + if _, err := VEXTRACTF32X8_Z(opimm8, opzmm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTF32X8_Z(opimm8, opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVEXTRACTF64X2ValidFormsNoError(t *testing.T) { + if _, err := VEXTRACTF64X2(opimm8, opymm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTF64X2(opimm8, opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTF64X2(opimm8, opymm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTF64X2(opimm8, opymm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTF64X2(opimm8, opzmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTF64X2(opimm8, opzmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTF64X2(opimm8, opzmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTF64X2(opimm8, opzmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVEXTRACTF64X2_ZValidFormsNoError(t *testing.T) { + if _, err := VEXTRACTF64X2_Z(opimm8, opymm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTF64X2_Z(opimm8, opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTF64X2_Z(opimm8, opzmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTF64X2_Z(opimm8, opzmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVEXTRACTF64X4ValidFormsNoError(t *testing.T) { + if _, err := VEXTRACTF64X4(opimm8, opzmm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTF64X4(opimm8, opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTF64X4(opimm8, opzmm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTF64X4(opimm8, opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVEXTRACTF64X4_ZValidFormsNoError(t *testing.T) { + if _, err := VEXTRACTF64X4_Z(opimm8, opzmm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTF64X4_Z(opimm8, opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVEXTRACTI128ValidFormsNoError(t *testing.T) { + if _, err := VEXTRACTI128(opimm8, opymm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTI128(opimm8, opymm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVEXTRACTI32X4ValidFormsNoError(t *testing.T) { + if _, err := VEXTRACTI32X4(opimm8, opymm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTI32X4(opimm8, opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTI32X4(opimm8, opymm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTI32X4(opimm8, opymm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTI32X4(opimm8, opzmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTI32X4(opimm8, opzmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTI32X4(opimm8, opzmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTI32X4(opimm8, opzmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVEXTRACTI32X4_ZValidFormsNoError(t *testing.T) { + if _, err := VEXTRACTI32X4_Z(opimm8, opymm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTI32X4_Z(opimm8, opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTI32X4_Z(opimm8, opzmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTI32X4_Z(opimm8, opzmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVEXTRACTI32X8ValidFormsNoError(t *testing.T) { + if _, err := VEXTRACTI32X8(opimm8, opzmm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTI32X8(opimm8, opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTI32X8(opimm8, opzmm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTI32X8(opimm8, opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVEXTRACTI32X8_ZValidFormsNoError(t *testing.T) { + if _, err := VEXTRACTI32X8_Z(opimm8, opzmm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTI32X8_Z(opimm8, opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVEXTRACTI64X2ValidFormsNoError(t *testing.T) { + if _, err := VEXTRACTI64X2(opimm8, opymm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTI64X2(opimm8, opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTI64X2(opimm8, opymm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTI64X2(opimm8, opymm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTI64X2(opimm8, opzmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTI64X2(opimm8, opzmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTI64X2(opimm8, opzmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTI64X2(opimm8, opzmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVEXTRACTI64X2_ZValidFormsNoError(t *testing.T) { + if _, err := VEXTRACTI64X2_Z(opimm8, opymm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTI64X2_Z(opimm8, opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTI64X2_Z(opimm8, opzmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTI64X2_Z(opimm8, opzmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVEXTRACTI64X4ValidFormsNoError(t *testing.T) { + if _, err := VEXTRACTI64X4(opimm8, opzmm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTI64X4(opimm8, opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTI64X4(opimm8, opzmm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTI64X4(opimm8, opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVEXTRACTI64X4_ZValidFormsNoError(t *testing.T) { + if _, err := VEXTRACTI64X4_Z(opimm8, opzmm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTI64X4_Z(opimm8, opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVEXTRACTPSValidFormsNoError(t *testing.T) { + if _, err := VEXTRACTPS(opimm8, opxmm, opm32); err != nil { + t.Fatal(err) + } + if _, err := VEXTRACTPS(opimm8, opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVFIXUPIMMPDValidFormsNoError(t *testing.T) { + if _, err := VFIXUPIMMPD(opimm8, opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPD(opimm8, opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPD(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPD(opimm8, opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPD(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPD(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPD(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPD(opimm8, opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPD(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPD(opimm8, opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPD(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPD(opimm8, opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFIXUPIMMPD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFIXUPIMMPD_BCST(opimm8, opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPD_BCST(opimm8, opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPD_BCST(opimm8, opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPD_BCST(opimm8, opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPD_BCST(opimm8, opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPD_BCST(opimm8, opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFIXUPIMMPD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFIXUPIMMPD_BCST_Z(opimm8, opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPD_BCST_Z(opimm8, opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPD_BCST_Z(opimm8, opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFIXUPIMMPD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFIXUPIMMPD_SAE(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPD_SAE(opimm8, opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFIXUPIMMPD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFIXUPIMMPD_SAE_Z(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFIXUPIMMPD_ZValidFormsNoError(t *testing.T) { + if _, err := VFIXUPIMMPD_Z(opimm8, opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPD_Z(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPD_Z(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPD_Z(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPD_Z(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPD_Z(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFIXUPIMMPSValidFormsNoError(t *testing.T) { + if _, err := VFIXUPIMMPS(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPS(opimm8, opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPS(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPS(opimm8, opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPS(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPS(opimm8, opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPS(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPS(opimm8, opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPS(opimm8, opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPS(opimm8, opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPS(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPS(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFIXUPIMMPS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFIXUPIMMPS_BCST(opimm8, opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPS_BCST(opimm8, opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPS_BCST(opimm8, opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPS_BCST(opimm8, opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPS_BCST(opimm8, opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPS_BCST(opimm8, opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFIXUPIMMPS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFIXUPIMMPS_BCST_Z(opimm8, opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPS_BCST_Z(opimm8, opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPS_BCST_Z(opimm8, opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFIXUPIMMPS_SAEValidFormsNoError(t *testing.T) { + if _, err := VFIXUPIMMPS_SAE(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPS_SAE(opimm8, opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFIXUPIMMPS_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFIXUPIMMPS_SAE_Z(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFIXUPIMMPS_ZValidFormsNoError(t *testing.T) { + if _, err := VFIXUPIMMPS_Z(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPS_Z(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPS_Z(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPS_Z(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPS_Z(opimm8, opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMPS_Z(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFIXUPIMMSDValidFormsNoError(t *testing.T) { + if _, err := VFIXUPIMMSD(opimm8, opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMSD(opimm8, opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMSD(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMSD(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFIXUPIMMSD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFIXUPIMMSD_SAE(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMSD_SAE(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFIXUPIMMSD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFIXUPIMMSD_SAE_Z(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFIXUPIMMSD_ZValidFormsNoError(t *testing.T) { + if _, err := VFIXUPIMMSD_Z(opimm8, opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMSD_Z(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFIXUPIMMSSValidFormsNoError(t *testing.T) { + if _, err := VFIXUPIMMSS(opimm8, opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMSS(opimm8, opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMSS(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMSS(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFIXUPIMMSS_SAEValidFormsNoError(t *testing.T) { + if _, err := VFIXUPIMMSS_SAE(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMSS_SAE(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFIXUPIMMSS_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFIXUPIMMSS_SAE_Z(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFIXUPIMMSS_ZValidFormsNoError(t *testing.T) { + if _, err := VFIXUPIMMSS_Z(opimm8, opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFIXUPIMMSS_Z(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132PDValidFormsNoError(t *testing.T) { + if _, err := VFMADD132PD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132PD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFMADD132PD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132PD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD132PD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132PD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD132PD_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PD_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132PD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD132PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132PD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD132PD_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PD_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132PD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD132PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132PD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD132PD_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PD_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132PD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD132PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132PD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD132PD_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PD_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132PD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD132PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132PD_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD132PD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132PSValidFormsNoError(t *testing.T) { + if _, err := VFMADD132PS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132PS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFMADD132PS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132PS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD132PS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132PS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD132PS_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PS_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132PS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD132PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132PS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD132PS_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PS_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132PS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD132PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132PS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD132PS_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PS_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132PS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD132PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132PS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD132PS_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PS_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132PS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD132PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132PS_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD132PS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132PS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132SDValidFormsNoError(t *testing.T) { + if _, err := VFMADD132SD(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132SD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132SD(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132SD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132SD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD132SD_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132SD_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132SD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD132SD_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132SD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD132SD_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132SD_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132SD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD132SD_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132SD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD132SD_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132SD_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132SD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD132SD_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132SD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD132SD_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132SD_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132SD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD132SD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132SD_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD132SD_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132SD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132SSValidFormsNoError(t *testing.T) { + if _, err := VFMADD132SS(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132SS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132SS(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132SS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132SS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD132SS_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132SS_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132SS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD132SS_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132SS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD132SS_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132SS_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132SS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD132SS_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132SS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD132SS_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132SS_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132SS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD132SS_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132SS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD132SS_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132SS_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132SS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD132SS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD132SS_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD132SS_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD132SS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213PDValidFormsNoError(t *testing.T) { + if _, err := VFMADD213PD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213PD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFMADD213PD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213PD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD213PD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213PD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD213PD_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PD_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213PD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD213PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213PD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD213PD_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PD_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213PD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD213PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213PD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD213PD_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PD_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213PD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD213PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213PD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD213PD_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PD_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213PD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD213PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213PD_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD213PD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213PSValidFormsNoError(t *testing.T) { + if _, err := VFMADD213PS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213PS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFMADD213PS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213PS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD213PS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213PS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD213PS_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PS_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213PS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD213PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213PS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD213PS_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PS_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213PS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD213PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213PS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD213PS_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PS_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213PS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD213PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213PS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD213PS_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PS_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213PS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD213PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213PS_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD213PS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213PS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213SDValidFormsNoError(t *testing.T) { + if _, err := VFMADD213SD(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213SD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213SD(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213SD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213SD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD213SD_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213SD_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213SD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD213SD_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213SD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD213SD_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213SD_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213SD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD213SD_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213SD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD213SD_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213SD_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213SD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD213SD_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213SD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD213SD_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213SD_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213SD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD213SD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213SD_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD213SD_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213SD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213SSValidFormsNoError(t *testing.T) { + if _, err := VFMADD213SS(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213SS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213SS(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213SS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213SS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD213SS_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213SS_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213SS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD213SS_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213SS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD213SS_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213SS_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213SS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD213SS_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213SS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD213SS_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213SS_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213SS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD213SS_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213SS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD213SS_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213SS_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213SS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD213SS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD213SS_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD213SS_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD213SS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231PDValidFormsNoError(t *testing.T) { + if _, err := VFMADD231PD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231PD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFMADD231PD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231PD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD231PD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231PD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD231PD_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PD_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231PD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD231PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231PD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD231PD_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PD_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231PD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD231PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231PD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD231PD_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PD_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231PD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD231PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231PD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD231PD_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PD_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231PD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD231PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231PD_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD231PD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231PSValidFormsNoError(t *testing.T) { + if _, err := VFMADD231PS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231PS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFMADD231PS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231PS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD231PS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231PS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD231PS_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PS_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231PS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD231PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231PS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD231PS_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PS_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231PS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD231PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231PS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD231PS_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PS_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231PS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD231PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231PS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD231PS_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PS_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231PS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD231PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231PS_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD231PS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231PS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231SDValidFormsNoError(t *testing.T) { + if _, err := VFMADD231SD(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231SD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231SD(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231SD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231SD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD231SD_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231SD_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231SD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD231SD_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231SD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD231SD_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231SD_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231SD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD231SD_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231SD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD231SD_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231SD_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231SD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD231SD_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231SD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD231SD_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231SD_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231SD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD231SD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231SD_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD231SD_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231SD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231SSValidFormsNoError(t *testing.T) { + if _, err := VFMADD231SS(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231SS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231SS(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231SS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231SS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD231SS_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231SS_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231SS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD231SS_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231SS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD231SS_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231SS_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231SS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD231SS_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231SS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD231SS_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231SS_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231SS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD231SS_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231SS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADD231SS_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231SS_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231SS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD231SS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADD231SS_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADD231SS_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADD231SS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB132PDValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB132PD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB132PD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB132PD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB132PD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB132PD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB132PD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB132PD_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PD_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB132PD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB132PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB132PD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB132PD_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PD_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB132PD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB132PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB132PD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB132PD_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PD_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB132PD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB132PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB132PD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB132PD_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PD_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB132PD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB132PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB132PD_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB132PD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB132PSValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB132PS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB132PS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB132PS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB132PS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB132PS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB132PS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB132PS_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PS_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB132PS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB132PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB132PS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB132PS_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PS_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB132PS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB132PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB132PS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB132PS_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PS_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB132PS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB132PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB132PS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB132PS_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PS_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB132PS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB132PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB132PS_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB132PS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB132PS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB213PDValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB213PD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB213PD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB213PD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB213PD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB213PD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB213PD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB213PD_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PD_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB213PD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB213PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB213PD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB213PD_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PD_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB213PD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB213PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB213PD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB213PD_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PD_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB213PD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB213PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB213PD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB213PD_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PD_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB213PD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB213PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB213PD_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB213PD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB213PSValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB213PS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB213PS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB213PS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB213PS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB213PS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB213PS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB213PS_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PS_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB213PS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB213PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB213PS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB213PS_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PS_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB213PS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB213PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB213PS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB213PS_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PS_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB213PS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB213PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB213PS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB213PS_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PS_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB213PS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB213PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB213PS_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB213PS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB213PS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB231PDValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB231PD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB231PD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB231PD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB231PD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB231PD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB231PD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB231PD_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PD_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB231PD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB231PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB231PD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB231PD_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PD_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB231PD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB231PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB231PD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB231PD_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PD_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB231PD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB231PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB231PD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB231PD_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PD_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB231PD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB231PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB231PD_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB231PD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB231PSValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB231PS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB231PS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB231PS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB231PS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB231PS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB231PS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB231PS_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PS_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB231PS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB231PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB231PS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB231PS_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PS_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB231PS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB231PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB231PS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB231PS_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PS_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB231PS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB231PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB231PS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB231PS_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PS_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB231PS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB231PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMADDSUB231PS_ZValidFormsNoError(t *testing.T) { + if _, err := VFMADDSUB231PS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMADDSUB231PS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132PDValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132PD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132PD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132PD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132PD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132PD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132PD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132PD_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PD_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132PD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132PD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132PD_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PD_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132PD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132PD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132PD_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PD_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132PD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132PD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132PD_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PD_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132PD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132PD_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132PD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132PSValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132PS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132PS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132PS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132PS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132PS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132PS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132PS_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PS_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132PS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132PS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132PS_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PS_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132PS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132PS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132PS_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PS_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132PS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132PS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132PS_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PS_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132PS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132PS_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132PS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132PS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132SDValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132SD(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132SD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132SD(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132SD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132SD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132SD_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132SD_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132SD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132SD_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132SD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132SD_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132SD_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132SD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132SD_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132SD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132SD_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132SD_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132SD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132SD_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132SD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132SD_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132SD_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132SD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132SD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132SD_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132SD_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132SD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132SSValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132SS(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132SS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132SS(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132SS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132SS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132SS_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132SS_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132SS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132SS_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132SS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132SS_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132SS_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132SS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132SS_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132SS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132SS_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132SS_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132SS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132SS_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132SS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132SS_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132SS_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132SS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132SS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB132SS_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB132SS_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB132SS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213PDValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213PD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213PD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213PD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213PD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213PD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213PD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213PD_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PD_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213PD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213PD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213PD_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PD_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213PD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213PD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213PD_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PD_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213PD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213PD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213PD_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PD_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213PD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213PD_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213PD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213PSValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213PS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213PS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213PS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213PS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213PS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213PS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213PS_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PS_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213PS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213PS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213PS_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PS_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213PS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213PS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213PS_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PS_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213PS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213PS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213PS_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PS_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213PS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213PS_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213PS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213PS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213SDValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213SD(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213SD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213SD(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213SD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213SD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213SD_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213SD_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213SD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213SD_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213SD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213SD_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213SD_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213SD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213SD_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213SD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213SD_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213SD_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213SD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213SD_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213SD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213SD_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213SD_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213SD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213SD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213SD_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213SD_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213SD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213SSValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213SS(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213SS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213SS(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213SS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213SS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213SS_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213SS_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213SS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213SS_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213SS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213SS_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213SS_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213SS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213SS_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213SS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213SS_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213SS_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213SS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213SS_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213SS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213SS_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213SS_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213SS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213SS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB213SS_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB213SS_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB213SS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231PDValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231PD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231PD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231PD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231PD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231PD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231PD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231PD_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PD_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231PD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231PD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231PD_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PD_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231PD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231PD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231PD_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PD_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231PD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231PD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231PD_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PD_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231PD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231PD_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231PD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231PSValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231PS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231PS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231PS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231PS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231PS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231PS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231PS_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PS_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231PS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231PS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231PS_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PS_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231PS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231PS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231PS_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PS_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231PS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231PS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231PS_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PS_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231PS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231PS_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231PS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231PS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231SDValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231SD(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231SD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231SD(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231SD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231SD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231SD_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231SD_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231SD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231SD_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231SD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231SD_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231SD_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231SD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231SD_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231SD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231SD_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231SD_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231SD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231SD_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231SD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231SD_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231SD_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231SD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231SD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231SD_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231SD_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231SD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231SSValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231SS(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231SS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231SS(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231SS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231SS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231SS_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231SS_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231SS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231SS_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231SS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231SS_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231SS_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231SS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231SS_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231SS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231SS_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231SS_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231SS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231SS_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231SS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231SS_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231SS_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231SS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231SS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUB231SS_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUB231SS_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUB231SS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD132PDValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD132PD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD132PD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD132PD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD132PD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD132PD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD132PD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD132PD_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PD_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD132PD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD132PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD132PD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD132PD_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PD_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD132PD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD132PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD132PD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD132PD_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PD_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD132PD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD132PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD132PD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD132PD_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PD_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD132PD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD132PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD132PD_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD132PD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD132PSValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD132PS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD132PS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD132PS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD132PS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD132PS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD132PS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD132PS_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PS_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD132PS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD132PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD132PS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD132PS_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PS_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD132PS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD132PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD132PS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD132PS_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PS_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD132PS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD132PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD132PS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD132PS_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PS_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD132PS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD132PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD132PS_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD132PS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD132PS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD213PDValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD213PD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD213PD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD213PD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD213PD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD213PD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD213PD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD213PD_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PD_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD213PD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD213PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD213PD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD213PD_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PD_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD213PD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD213PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD213PD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD213PD_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PD_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD213PD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD213PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD213PD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD213PD_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PD_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD213PD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD213PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD213PD_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD213PD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD213PSValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD213PS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD213PS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD213PS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD213PS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD213PS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD213PS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD213PS_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PS_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD213PS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD213PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD213PS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD213PS_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PS_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD213PS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD213PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD213PS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD213PS_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PS_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD213PS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD213PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD213PS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD213PS_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PS_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD213PS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD213PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD213PS_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD213PS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD213PS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD231PDValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD231PD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD231PD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD231PD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD231PD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD231PD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD231PD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD231PD_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PD_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD231PD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD231PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD231PD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD231PD_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PD_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD231PD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD231PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD231PD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD231PD_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PD_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD231PD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD231PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD231PD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD231PD_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PD_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD231PD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD231PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD231PD_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD231PD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD231PSValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD231PS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD231PS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD231PS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD231PS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD231PS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD231PS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD231PS_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PS_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD231PS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD231PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD231PS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD231PS_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PS_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD231PS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD231PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD231PS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD231PS_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PS_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD231PS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD231PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD231PS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD231PS_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PS_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD231PS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD231PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFMSUBADD231PS_ZValidFormsNoError(t *testing.T) { + if _, err := VFMSUBADD231PS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFMSUBADD231PS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132PDValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132PD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132PD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132PD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132PD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132PD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132PD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132PD_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PD_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132PD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132PD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132PD_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PD_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132PD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132PD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132PD_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PD_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132PD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132PD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132PD_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PD_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132PD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132PD_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132PD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132PSValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132PS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132PS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132PS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132PS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132PS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132PS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132PS_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PS_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132PS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132PS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132PS_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PS_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132PS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132PS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132PS_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PS_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132PS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132PS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132PS_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PS_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132PS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132PS_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132PS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132PS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132SDValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132SD(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132SD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132SD(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132SD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132SD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132SD_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132SD_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132SD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132SD_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132SD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132SD_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132SD_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132SD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132SD_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132SD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132SD_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132SD_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132SD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132SD_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132SD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132SD_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132SD_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132SD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132SD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132SD_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132SD_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132SD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132SSValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132SS(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132SS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132SS(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132SS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132SS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132SS_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132SS_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132SS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132SS_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132SS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132SS_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132SS_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132SS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132SS_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132SS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132SS_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132SS_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132SS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132SS_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132SS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132SS_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132SS_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132SS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132SS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD132SS_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD132SS_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD132SS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213PDValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213PD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213PD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213PD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213PD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213PD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213PD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213PD_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PD_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213PD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213PD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213PD_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PD_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213PD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213PD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213PD_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PD_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213PD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213PD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213PD_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PD_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213PD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213PD_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213PD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213PSValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213PS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213PS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213PS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213PS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213PS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213PS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213PS_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PS_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213PS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213PS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213PS_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PS_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213PS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213PS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213PS_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PS_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213PS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213PS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213PS_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PS_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213PS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213PS_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213PS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213PS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213SDValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213SD(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213SD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213SD(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213SD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213SD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213SD_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213SD_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213SD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213SD_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213SD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213SD_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213SD_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213SD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213SD_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213SD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213SD_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213SD_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213SD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213SD_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213SD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213SD_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213SD_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213SD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213SD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213SD_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213SD_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213SD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213SSValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213SS(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213SS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213SS(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213SS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213SS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213SS_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213SS_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213SS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213SS_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213SS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213SS_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213SS_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213SS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213SS_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213SS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213SS_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213SS_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213SS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213SS_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213SS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213SS_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213SS_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213SS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213SS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD213SS_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD213SS_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD213SS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231PDValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231PD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231PD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231PD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231PD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231PD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231PD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231PD_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PD_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231PD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231PD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231PD_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PD_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231PD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231PD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231PD_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PD_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231PD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231PD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231PD_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PD_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231PD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231PD_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231PD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231PSValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231PS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231PS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231PS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231PS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231PS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231PS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231PS_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PS_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231PS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231PS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231PS_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PS_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231PS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231PS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231PS_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PS_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231PS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231PS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231PS_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PS_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231PS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231PS_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231PS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231PS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231SDValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231SD(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231SD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231SD(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231SD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231SD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231SD_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231SD_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231SD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231SD_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231SD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231SD_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231SD_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231SD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231SD_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231SD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231SD_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231SD_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231SD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231SD_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231SD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231SD_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231SD_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231SD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231SD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231SD_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231SD_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231SD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231SSValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231SS(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231SS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231SS(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231SS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231SS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231SS_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231SS_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231SS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231SS_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231SS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231SS_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231SS_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231SS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231SS_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231SS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231SS_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231SS_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231SS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231SS_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231SS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231SS_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231SS_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231SS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231SS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMADD231SS_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMADD231SS_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMADD231SS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132PDValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132PD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132PD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132PD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132PD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132PD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132PD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132PD_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PD_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132PD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132PD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132PD_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PD_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132PD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132PD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132PD_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PD_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132PD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132PD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132PD_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PD_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132PD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132PD_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132PD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132PSValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132PS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132PS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132PS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132PS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132PS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132PS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132PS_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PS_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132PS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132PS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132PS_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PS_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132PS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132PS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132PS_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PS_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132PS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132PS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132PS_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PS_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132PS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132PS_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132PS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132PS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132SDValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132SD(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132SD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132SD(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132SD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132SD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132SD_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132SD_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132SD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132SD_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132SD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132SD_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132SD_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132SD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132SD_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132SD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132SD_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132SD_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132SD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132SD_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132SD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132SD_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132SD_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132SD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132SD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132SD_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132SD_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132SD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132SSValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132SS(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132SS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132SS(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132SS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132SS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132SS_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132SS_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132SS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132SS_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132SS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132SS_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132SS_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132SS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132SS_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132SS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132SS_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132SS_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132SS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132SS_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132SS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132SS_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132SS_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132SS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132SS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB132SS_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB132SS_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB132SS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213PDValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213PD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213PD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213PD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213PD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213PD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213PD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213PD_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PD_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213PD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213PD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213PD_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PD_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213PD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213PD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213PD_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PD_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213PD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213PD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213PD_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PD_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213PD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213PD_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213PD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213PSValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213PS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213PS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213PS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213PS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213PS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213PS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213PS_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PS_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213PS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213PS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213PS_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PS_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213PS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213PS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213PS_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PS_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213PS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213PS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213PS_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PS_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213PS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213PS_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213PS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213PS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213SDValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213SD(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213SD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213SD(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213SD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213SD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213SD_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213SD_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213SD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213SD_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213SD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213SD_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213SD_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213SD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213SD_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213SD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213SD_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213SD_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213SD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213SD_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213SD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213SD_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213SD_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213SD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213SD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213SD_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213SD_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213SD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213SSValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213SS(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213SS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213SS(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213SS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213SS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213SS_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213SS_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213SS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213SS_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213SS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213SS_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213SS_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213SS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213SS_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213SS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213SS_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213SS_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213SS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213SS_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213SS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213SS_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213SS_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213SS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213SS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB213SS_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB213SS_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB213SS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231PDValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231PD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231PD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231PD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231PD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231PD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231PD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231PD_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PD_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231PD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231PD_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231PD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231PD_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PD_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231PD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231PD_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231PD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231PD_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PD_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231PD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231PD_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231PD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231PD_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PD_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231PD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231PD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231PD_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231PD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231PSValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231PS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231PS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231PS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231PS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231PS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231PS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231PS_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PS_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231PS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231PS_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231PS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231PS_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PS_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231PS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231PS_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231PS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231PS_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PS_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231PS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231PS_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231PS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231PS_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PS_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231PS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231PS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231PS_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231PS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231PS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231SDValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231SD(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231SD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231SD(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231SD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231SD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231SD_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231SD_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231SD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231SD_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231SD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231SD_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231SD_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231SD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231SD_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231SD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231SD_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231SD_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231SD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231SD_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231SD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231SD_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231SD_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231SD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231SD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231SD_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231SD_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231SD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231SSValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231SS(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231SS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231SS(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231SS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231SS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231SS_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231SS_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231SS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231SS_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231SS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231SS_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231SS_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231SS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231SS_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231SS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231SS_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231SS_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231SS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231SS_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231SS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231SS_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231SS_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231SS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231SS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFNMSUB231SS_ZValidFormsNoError(t *testing.T) { + if _, err := VFNMSUB231SS_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VFNMSUB231SS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVFPCLASSPDXValidFormsNoError(t *testing.T) { + if _, err := VFPCLASSPDX(opimm8, opm128, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VFPCLASSPDX(opimm8, opm128, opk); err != nil { + t.Fatal(err) + } + if _, err := VFPCLASSPDX(opimm8, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VFPCLASSPDX(opimm8, opxmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVFPCLASSPDX_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFPCLASSPDX_BCST(opimm8, opm64, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VFPCLASSPDX_BCST(opimm8, opm64, opk); err != nil { + t.Fatal(err) + } +} + +func TestVFPCLASSPDYValidFormsNoError(t *testing.T) { + if _, err := VFPCLASSPDY(opimm8, opm256, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VFPCLASSPDY(opimm8, opm256, opk); err != nil { + t.Fatal(err) + } + if _, err := VFPCLASSPDY(opimm8, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VFPCLASSPDY(opimm8, opymm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVFPCLASSPDY_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFPCLASSPDY_BCST(opimm8, opm64, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VFPCLASSPDY_BCST(opimm8, opm64, opk); err != nil { + t.Fatal(err) + } +} + +func TestVFPCLASSPDZValidFormsNoError(t *testing.T) { + if _, err := VFPCLASSPDZ(opimm8, opm512, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VFPCLASSPDZ(opimm8, opm512, opk); err != nil { + t.Fatal(err) + } + if _, err := VFPCLASSPDZ(opimm8, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VFPCLASSPDZ(opimm8, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVFPCLASSPDZ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFPCLASSPDZ_BCST(opimm8, opm64, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VFPCLASSPDZ_BCST(opimm8, opm64, opk); err != nil { + t.Fatal(err) + } +} + +func TestVFPCLASSPSXValidFormsNoError(t *testing.T) { + if _, err := VFPCLASSPSX(opimm8, opm128, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VFPCLASSPSX(opimm8, opm128, opk); err != nil { + t.Fatal(err) + } + if _, err := VFPCLASSPSX(opimm8, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VFPCLASSPSX(opimm8, opxmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVFPCLASSPSX_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFPCLASSPSX_BCST(opimm8, opm32, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VFPCLASSPSX_BCST(opimm8, opm32, opk); err != nil { + t.Fatal(err) + } +} + +func TestVFPCLASSPSYValidFormsNoError(t *testing.T) { + if _, err := VFPCLASSPSY(opimm8, opm256, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VFPCLASSPSY(opimm8, opm256, opk); err != nil { + t.Fatal(err) + } + if _, err := VFPCLASSPSY(opimm8, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VFPCLASSPSY(opimm8, opymm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVFPCLASSPSY_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFPCLASSPSY_BCST(opimm8, opm32, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VFPCLASSPSY_BCST(opimm8, opm32, opk); err != nil { + t.Fatal(err) + } +} + +func TestVFPCLASSPSZValidFormsNoError(t *testing.T) { + if _, err := VFPCLASSPSZ(opimm8, opm512, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VFPCLASSPSZ(opimm8, opm512, opk); err != nil { + t.Fatal(err) + } + if _, err := VFPCLASSPSZ(opimm8, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VFPCLASSPSZ(opimm8, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVFPCLASSPSZ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VFPCLASSPSZ_BCST(opimm8, opm32, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VFPCLASSPSZ_BCST(opimm8, opm32, opk); err != nil { + t.Fatal(err) + } +} + +func TestVFPCLASSSDValidFormsNoError(t *testing.T) { + if _, err := VFPCLASSSD(opimm8, opm64, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VFPCLASSSD(opimm8, opm64, opk); err != nil { + t.Fatal(err) + } + if _, err := VFPCLASSSD(opimm8, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VFPCLASSSD(opimm8, opxmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVFPCLASSSSValidFormsNoError(t *testing.T) { + if _, err := VFPCLASSSS(opimm8, opm32, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VFPCLASSSS(opimm8, opm32, opk); err != nil { + t.Fatal(err) + } + if _, err := VFPCLASSSS(opimm8, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VFPCLASSSS(opimm8, opxmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVGATHERDPDValidFormsNoError(t *testing.T) { + if _, err := VGATHERDPD(opxmm, opvm32x, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGATHERDPD(opymm, opvm32x, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGATHERDPD(opvm32x, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGATHERDPD(opvm32x, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGATHERDPD(opvm32y, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVGATHERDPSValidFormsNoError(t *testing.T) { + if _, err := VGATHERDPS(opxmm, opvm32x, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGATHERDPS(opymm, opvm32y, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGATHERDPS(opvm32x, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGATHERDPS(opvm32y, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGATHERDPS(opvm32z, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVGATHERQPDValidFormsNoError(t *testing.T) { + if _, err := VGATHERQPD(opxmm, opvm64x, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGATHERQPD(opymm, opvm64y, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGATHERQPD(opvm64x, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGATHERQPD(opvm64y, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGATHERQPD(opvm64z, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVGATHERQPSValidFormsNoError(t *testing.T) { + if _, err := VGATHERQPS(opxmm, opvm64x, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGATHERQPS(opxmm, opvm64y, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGATHERQPS(opvm64x, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGATHERQPS(opvm64y, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGATHERQPS(opvm64z, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVGETEXPPDValidFormsNoError(t *testing.T) { + if _, err := VGETEXPPD(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPD(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPD(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPD(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPD(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPD(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPD(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPD(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPD(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPD(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPD(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETEXPPD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VGETEXPPD_BCST(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPD_BCST(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPD_BCST(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPD_BCST(opm64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPD_BCST(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPD_BCST(opm64, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETEXPPD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VGETEXPPD_BCST_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPD_BCST_Z(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPD_BCST_Z(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETEXPPD_SAEValidFormsNoError(t *testing.T) { + if _, err := VGETEXPPD_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPD_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETEXPPD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VGETEXPPD_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETEXPPD_ZValidFormsNoError(t *testing.T) { + if _, err := VGETEXPPD_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPD_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPD_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPD_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPD_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPD_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETEXPPSValidFormsNoError(t *testing.T) { + if _, err := VGETEXPPS(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPS(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPS(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPS(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPS(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPS(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPS(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPS(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPS(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPS(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPS(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETEXPPS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VGETEXPPS_BCST(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPS_BCST(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPS_BCST(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPS_BCST(opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPS_BCST(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPS_BCST(opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETEXPPS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VGETEXPPS_BCST_Z(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPS_BCST_Z(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPS_BCST_Z(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETEXPPS_SAEValidFormsNoError(t *testing.T) { + if _, err := VGETEXPPS_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPS_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETEXPPS_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VGETEXPPS_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETEXPPS_ZValidFormsNoError(t *testing.T) { + if _, err := VGETEXPPS_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPS_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPS_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPS_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPS_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPPS_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETEXPSDValidFormsNoError(t *testing.T) { + if _, err := VGETEXPSD(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPSD(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPSD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPSD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETEXPSD_SAEValidFormsNoError(t *testing.T) { + if _, err := VGETEXPSD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPSD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETEXPSD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VGETEXPSD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETEXPSD_ZValidFormsNoError(t *testing.T) { + if _, err := VGETEXPSD_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPSD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETEXPSSValidFormsNoError(t *testing.T) { + if _, err := VGETEXPSS(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPSS(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPSS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPSS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETEXPSS_SAEValidFormsNoError(t *testing.T) { + if _, err := VGETEXPSS_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPSS_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETEXPSS_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VGETEXPSS_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETEXPSS_ZValidFormsNoError(t *testing.T) { + if _, err := VGETEXPSS_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETEXPSS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETMANTPDValidFormsNoError(t *testing.T) { + if _, err := VGETMANTPD(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPD(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPD(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPD(opimm8, opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPD(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPD(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPD(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPD(opimm8, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPD(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPD(opimm8, opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPD(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPD(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETMANTPD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VGETMANTPD_BCST(opimm8, opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPD_BCST(opimm8, opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPD_BCST(opimm8, opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPD_BCST(opimm8, opm64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPD_BCST(opimm8, opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPD_BCST(opimm8, opm64, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETMANTPD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VGETMANTPD_BCST_Z(opimm8, opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPD_BCST_Z(opimm8, opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPD_BCST_Z(opimm8, opm64, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETMANTPD_SAEValidFormsNoError(t *testing.T) { + if _, err := VGETMANTPD_SAE(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPD_SAE(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETMANTPD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VGETMANTPD_SAE_Z(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETMANTPD_ZValidFormsNoError(t *testing.T) { + if _, err := VGETMANTPD_Z(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPD_Z(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPD_Z(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPD_Z(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPD_Z(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPD_Z(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETMANTPSValidFormsNoError(t *testing.T) { + if _, err := VGETMANTPS(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPS(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPS(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPS(opimm8, opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPS(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPS(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPS(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPS(opimm8, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPS(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPS(opimm8, opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPS(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPS(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETMANTPS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VGETMANTPS_BCST(opimm8, opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPS_BCST(opimm8, opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPS_BCST(opimm8, opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPS_BCST(opimm8, opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPS_BCST(opimm8, opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPS_BCST(opimm8, opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETMANTPS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VGETMANTPS_BCST_Z(opimm8, opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPS_BCST_Z(opimm8, opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPS_BCST_Z(opimm8, opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETMANTPS_SAEValidFormsNoError(t *testing.T) { + if _, err := VGETMANTPS_SAE(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPS_SAE(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETMANTPS_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VGETMANTPS_SAE_Z(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETMANTPS_ZValidFormsNoError(t *testing.T) { + if _, err := VGETMANTPS_Z(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPS_Z(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPS_Z(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPS_Z(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPS_Z(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTPS_Z(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETMANTSDValidFormsNoError(t *testing.T) { + if _, err := VGETMANTSD(opimm8, opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTSD(opimm8, opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTSD(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTSD(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETMANTSD_SAEValidFormsNoError(t *testing.T) { + if _, err := VGETMANTSD_SAE(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTSD_SAE(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETMANTSD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VGETMANTSD_SAE_Z(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETMANTSD_ZValidFormsNoError(t *testing.T) { + if _, err := VGETMANTSD_Z(opimm8, opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTSD_Z(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETMANTSSValidFormsNoError(t *testing.T) { + if _, err := VGETMANTSS(opimm8, opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTSS(opimm8, opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTSS(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTSS(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETMANTSS_SAEValidFormsNoError(t *testing.T) { + if _, err := VGETMANTSS_SAE(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTSS_SAE(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETMANTSS_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VGETMANTSS_SAE_Z(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVGETMANTSS_ZValidFormsNoError(t *testing.T) { + if _, err := VGETMANTSS_Z(opimm8, opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VGETMANTSS_Z(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVHADDPDValidFormsNoError(t *testing.T) { + if _, err := VHADDPD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VHADDPD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VHADDPD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VHADDPD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVHADDPSValidFormsNoError(t *testing.T) { + if _, err := VHADDPS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VHADDPS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VHADDPS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VHADDPS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVHSUBPDValidFormsNoError(t *testing.T) { + if _, err := VHSUBPD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VHSUBPD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VHSUBPD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VHSUBPD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVHSUBPSValidFormsNoError(t *testing.T) { + if _, err := VHSUBPS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VHSUBPS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VHSUBPS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VHSUBPS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVINSERTF128ValidFormsNoError(t *testing.T) { + if _, err := VINSERTF128(opimm8, opm128, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTF128(opimm8, opxmm, opymm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVINSERTF32X4ValidFormsNoError(t *testing.T) { + if _, err := VINSERTF32X4(opimm8, opm128, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTF32X4(opimm8, opm128, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTF32X4(opimm8, opxmm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTF32X4(opimm8, opxmm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTF32X4(opimm8, opm128, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTF32X4(opimm8, opm128, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTF32X4(opimm8, opxmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTF32X4(opimm8, opxmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVINSERTF32X4_ZValidFormsNoError(t *testing.T) { + if _, err := VINSERTF32X4_Z(opimm8, opm128, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTF32X4_Z(opimm8, opxmm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTF32X4_Z(opimm8, opm128, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTF32X4_Z(opimm8, opxmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVINSERTF32X8ValidFormsNoError(t *testing.T) { + if _, err := VINSERTF32X8(opimm8, opm256, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTF32X8(opimm8, opm256, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTF32X8(opimm8, opymm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTF32X8(opimm8, opymm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVINSERTF32X8_ZValidFormsNoError(t *testing.T) { + if _, err := VINSERTF32X8_Z(opimm8, opm256, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTF32X8_Z(opimm8, opymm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVINSERTF64X2ValidFormsNoError(t *testing.T) { + if _, err := VINSERTF64X2(opimm8, opm128, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTF64X2(opimm8, opm128, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTF64X2(opimm8, opxmm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTF64X2(opimm8, opxmm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTF64X2(opimm8, opm128, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTF64X2(opimm8, opm128, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTF64X2(opimm8, opxmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTF64X2(opimm8, opxmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVINSERTF64X2_ZValidFormsNoError(t *testing.T) { + if _, err := VINSERTF64X2_Z(opimm8, opm128, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTF64X2_Z(opimm8, opxmm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTF64X2_Z(opimm8, opm128, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTF64X2_Z(opimm8, opxmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVINSERTF64X4ValidFormsNoError(t *testing.T) { + if _, err := VINSERTF64X4(opimm8, opm256, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTF64X4(opimm8, opm256, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTF64X4(opimm8, opymm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTF64X4(opimm8, opymm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVINSERTF64X4_ZValidFormsNoError(t *testing.T) { + if _, err := VINSERTF64X4_Z(opimm8, opm256, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTF64X4_Z(opimm8, opymm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVINSERTI128ValidFormsNoError(t *testing.T) { + if _, err := VINSERTI128(opimm8, opm128, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTI128(opimm8, opxmm, opymm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVINSERTI32X4ValidFormsNoError(t *testing.T) { + if _, err := VINSERTI32X4(opimm8, opm128, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTI32X4(opimm8, opm128, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTI32X4(opimm8, opxmm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTI32X4(opimm8, opxmm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTI32X4(opimm8, opm128, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTI32X4(opimm8, opm128, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTI32X4(opimm8, opxmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTI32X4(opimm8, opxmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVINSERTI32X4_ZValidFormsNoError(t *testing.T) { + if _, err := VINSERTI32X4_Z(opimm8, opm128, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTI32X4_Z(opimm8, opxmm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTI32X4_Z(opimm8, opm128, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTI32X4_Z(opimm8, opxmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVINSERTI32X8ValidFormsNoError(t *testing.T) { + if _, err := VINSERTI32X8(opimm8, opm256, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTI32X8(opimm8, opm256, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTI32X8(opimm8, opymm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTI32X8(opimm8, opymm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVINSERTI32X8_ZValidFormsNoError(t *testing.T) { + if _, err := VINSERTI32X8_Z(opimm8, opm256, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTI32X8_Z(opimm8, opymm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVINSERTI64X2ValidFormsNoError(t *testing.T) { + if _, err := VINSERTI64X2(opimm8, opm128, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTI64X2(opimm8, opm128, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTI64X2(opimm8, opxmm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTI64X2(opimm8, opxmm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTI64X2(opimm8, opm128, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTI64X2(opimm8, opm128, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTI64X2(opimm8, opxmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTI64X2(opimm8, opxmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVINSERTI64X2_ZValidFormsNoError(t *testing.T) { + if _, err := VINSERTI64X2_Z(opimm8, opm128, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTI64X2_Z(opimm8, opxmm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTI64X2_Z(opimm8, opm128, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTI64X2_Z(opimm8, opxmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVINSERTI64X4ValidFormsNoError(t *testing.T) { + if _, err := VINSERTI64X4(opimm8, opm256, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTI64X4(opimm8, opm256, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTI64X4(opimm8, opymm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTI64X4(opimm8, opymm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVINSERTI64X4_ZValidFormsNoError(t *testing.T) { + if _, err := VINSERTI64X4_Z(opimm8, opm256, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTI64X4_Z(opimm8, opymm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVINSERTPSValidFormsNoError(t *testing.T) { + if _, err := VINSERTPS(opimm8, opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VINSERTPS(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVLDDQUValidFormsNoError(t *testing.T) { + if _, err := VLDDQU(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VLDDQU(opm256, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVLDMXCSRValidFormsNoError(t *testing.T) { + if _, err := VLDMXCSR(opm32); err != nil { + t.Fatal(err) + } +} + +func TestVMASKMOVDQUValidFormsNoError(t *testing.T) { + if _, err := VMASKMOVDQU(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMASKMOVPDValidFormsNoError(t *testing.T) { + if _, err := VMASKMOVPD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMASKMOVPD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMASKMOVPD(opxmm, opxmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMASKMOVPD(opymm, opymm, opm256); err != nil { + t.Fatal(err) + } +} + +func TestVMASKMOVPSValidFormsNoError(t *testing.T) { + if _, err := VMASKMOVPS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMASKMOVPS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMASKMOVPS(opxmm, opxmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMASKMOVPS(opymm, opymm, opm256); err != nil { + t.Fatal(err) + } +} + +func TestVMAXPDValidFormsNoError(t *testing.T) { + if _, err := VMAXPD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMAXPD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VMAXPD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMAXPD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VMAXPD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMAXPD_SAEValidFormsNoError(t *testing.T) { + if _, err := VMAXPD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMAXPD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VMAXPD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMAXPD_ZValidFormsNoError(t *testing.T) { + if _, err := VMAXPD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMAXPSValidFormsNoError(t *testing.T) { + if _, err := VMAXPS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMAXPS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VMAXPS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMAXPS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VMAXPS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMAXPS_SAEValidFormsNoError(t *testing.T) { + if _, err := VMAXPS_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPS_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMAXPS_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VMAXPS_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMAXPS_ZValidFormsNoError(t *testing.T) { + if _, err := VMAXPS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXPS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMAXSDValidFormsNoError(t *testing.T) { + if _, err := VMAXSD(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXSD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXSD(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXSD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMAXSD_SAEValidFormsNoError(t *testing.T) { + if _, err := VMAXSD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXSD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMAXSD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VMAXSD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMAXSD_ZValidFormsNoError(t *testing.T) { + if _, err := VMAXSD_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXSD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMAXSSValidFormsNoError(t *testing.T) { + if _, err := VMAXSS(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXSS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXSS(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXSS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMAXSS_SAEValidFormsNoError(t *testing.T) { + if _, err := VMAXSS_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXSS_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMAXSS_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VMAXSS_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMAXSS_ZValidFormsNoError(t *testing.T) { + if _, err := VMAXSS_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMAXSS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMINPDValidFormsNoError(t *testing.T) { + if _, err := VMINPD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMINPD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMINPD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMINPD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMINPD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMINPD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMINPD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMINPD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMINPD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMINPD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMINPD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMINPD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMINPD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VMINPD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMINPD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMINPD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMINPD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMINPD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMINPD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMINPD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VMINPD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMINPD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMINPD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMINPD_SAEValidFormsNoError(t *testing.T) { + if _, err := VMINPD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMINPD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMINPD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VMINPD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMINPD_ZValidFormsNoError(t *testing.T) { + if _, err := VMINPD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMINPD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMINPD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMINPD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMINPD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMINPD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMINPSValidFormsNoError(t *testing.T) { + if _, err := VMINPS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMINPS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMINPS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMINPS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMINPS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMINPS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMINPS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMINPS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMINPS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMINPS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMINPS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMINPS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMINPS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VMINPS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMINPS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMINPS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMINPS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMINPS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMINPS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMINPS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VMINPS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMINPS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMINPS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMINPS_SAEValidFormsNoError(t *testing.T) { + if _, err := VMINPS_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMINPS_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMINPS_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VMINPS_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMINPS_ZValidFormsNoError(t *testing.T) { + if _, err := VMINPS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMINPS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMINPS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMINPS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMINPS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMINPS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMINSDValidFormsNoError(t *testing.T) { + if _, err := VMINSD(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMINSD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMINSD(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMINSD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMINSD_SAEValidFormsNoError(t *testing.T) { + if _, err := VMINSD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMINSD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMINSD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VMINSD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMINSD_ZValidFormsNoError(t *testing.T) { + if _, err := VMINSD_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMINSD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMINSSValidFormsNoError(t *testing.T) { + if _, err := VMINSS(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMINSS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMINSS(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMINSS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMINSS_SAEValidFormsNoError(t *testing.T) { + if _, err := VMINSS_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMINSS_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMINSS_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VMINSS_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMINSS_ZValidFormsNoError(t *testing.T) { + if _, err := VMINSS_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMINSS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVAPDValidFormsNoError(t *testing.T) { + if _, err := VMOVAPD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPD(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPD(opxmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPD(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPD(opymm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPD(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPD(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPD(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPD(opxmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPD(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPD(opymm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPD(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPD(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPD(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPD(opzmm, opk, opm512); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPD(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPD(opzmm, opm512); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPD(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVAPD_ZValidFormsNoError(t *testing.T) { + if _, err := VMOVAPD_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPD_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPD_Z(opxmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPD_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPD_Z(opymm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPD_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPD_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPD_Z(opzmm, opk, opm512); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPD_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVAPSValidFormsNoError(t *testing.T) { + if _, err := VMOVAPS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPS(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPS(opxmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPS(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPS(opymm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPS(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPS(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPS(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPS(opxmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPS(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPS(opymm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPS(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPS(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPS(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPS(opzmm, opk, opm512); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPS(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPS(opzmm, opm512); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPS(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVAPS_ZValidFormsNoError(t *testing.T) { + if _, err := VMOVAPS_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPS_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPS_Z(opxmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPS_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPS_Z(opymm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPS_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPS_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPS_Z(opzmm, opk, opm512); err != nil { + t.Fatal(err) + } + if _, err := VMOVAPS_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVDValidFormsNoError(t *testing.T) { + if _, err := VMOVD(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVD(opr32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVD(opxmm, opm32); err != nil { + t.Fatal(err) + } + if _, err := VMOVD(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVMOVDDUPValidFormsNoError(t *testing.T) { + if _, err := VMOVDDUP(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDDUP(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDDUP(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDDUP(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDDUP(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDDUP(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDDUP(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDDUP(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDDUP(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDDUP(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDDUP(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDDUP(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVDDUP_ZValidFormsNoError(t *testing.T) { + if _, err := VMOVDDUP_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDDUP_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDDUP_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDDUP_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDDUP_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDDUP_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVDQAValidFormsNoError(t *testing.T) { + if _, err := VMOVDQA(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA(opxmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA(opymm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA(opymm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVDQA32ValidFormsNoError(t *testing.T) { + if _, err := VMOVDQA32(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA32(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA32(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA32(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA32(opxmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA32(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA32(opxmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA32(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA32(opymm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA32(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA32(opymm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA32(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA32(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA32(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA32(opzmm, opk, opm512); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA32(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA32(opzmm, opm512); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA32(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVDQA32_ZValidFormsNoError(t *testing.T) { + if _, err := VMOVDQA32_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA32_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA32_Z(opxmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA32_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA32_Z(opymm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA32_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA32_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA32_Z(opzmm, opk, opm512); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA32_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVDQA64ValidFormsNoError(t *testing.T) { + if _, err := VMOVDQA64(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA64(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA64(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA64(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA64(opxmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA64(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA64(opxmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA64(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA64(opymm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA64(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA64(opymm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA64(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA64(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA64(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA64(opzmm, opk, opm512); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA64(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA64(opzmm, opm512); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA64(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVDQA64_ZValidFormsNoError(t *testing.T) { + if _, err := VMOVDQA64_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA64_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA64_Z(opxmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA64_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA64_Z(opymm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA64_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA64_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA64_Z(opzmm, opk, opm512); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQA64_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVDQUValidFormsNoError(t *testing.T) { + if _, err := VMOVDQU(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU(opxmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU(opymm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU(opymm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVDQU16ValidFormsNoError(t *testing.T) { + if _, err := VMOVDQU16(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU16(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU16(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU16(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU16(opxmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU16(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU16(opxmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU16(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU16(opymm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU16(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU16(opymm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU16(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU16(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU16(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU16(opzmm, opk, opm512); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU16(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU16(opzmm, opm512); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU16(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVDQU16_ZValidFormsNoError(t *testing.T) { + if _, err := VMOVDQU16_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU16_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU16_Z(opxmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU16_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU16_Z(opymm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU16_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU16_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU16_Z(opzmm, opk, opm512); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU16_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVDQU32ValidFormsNoError(t *testing.T) { + if _, err := VMOVDQU32(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU32(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU32(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU32(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU32(opxmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU32(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU32(opxmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU32(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU32(opymm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU32(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU32(opymm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU32(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU32(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU32(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU32(opzmm, opk, opm512); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU32(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU32(opzmm, opm512); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU32(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVDQU32_ZValidFormsNoError(t *testing.T) { + if _, err := VMOVDQU32_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU32_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU32_Z(opxmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU32_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU32_Z(opymm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU32_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU32_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU32_Z(opzmm, opk, opm512); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU32_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVDQU64ValidFormsNoError(t *testing.T) { + if _, err := VMOVDQU64(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU64(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU64(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU64(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU64(opxmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU64(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU64(opxmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU64(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU64(opymm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU64(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU64(opymm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU64(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU64(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU64(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU64(opzmm, opk, opm512); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU64(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU64(opzmm, opm512); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU64(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVDQU64_ZValidFormsNoError(t *testing.T) { + if _, err := VMOVDQU64_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU64_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU64_Z(opxmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU64_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU64_Z(opymm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU64_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU64_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU64_Z(opzmm, opk, opm512); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU64_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVDQU8ValidFormsNoError(t *testing.T) { + if _, err := VMOVDQU8(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU8(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU8(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU8(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU8(opxmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU8(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU8(opxmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU8(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU8(opymm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU8(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU8(opymm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU8(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU8(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU8(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU8(opzmm, opk, opm512); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU8(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU8(opzmm, opm512); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU8(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVDQU8_ZValidFormsNoError(t *testing.T) { + if _, err := VMOVDQU8_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU8_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU8_Z(opxmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU8_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU8_Z(opymm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU8_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU8_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU8_Z(opzmm, opk, opm512); err != nil { + t.Fatal(err) + } + if _, err := VMOVDQU8_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVHLPSValidFormsNoError(t *testing.T) { + if _, err := VMOVHLPS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVHPDValidFormsNoError(t *testing.T) { + if _, err := VMOVHPD(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVHPD(opxmm, opm64); err != nil { + t.Fatal(err) + } +} + +func TestVMOVHPSValidFormsNoError(t *testing.T) { + if _, err := VMOVHPS(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVHPS(opxmm, opm64); err != nil { + t.Fatal(err) + } +} + +func TestVMOVLHPSValidFormsNoError(t *testing.T) { + if _, err := VMOVLHPS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVLPDValidFormsNoError(t *testing.T) { + if _, err := VMOVLPD(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVLPD(opxmm, opm64); err != nil { + t.Fatal(err) + } +} + +func TestVMOVLPSValidFormsNoError(t *testing.T) { + if _, err := VMOVLPS(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVLPS(opxmm, opm64); err != nil { + t.Fatal(err) + } +} + +func TestVMOVMSKPDValidFormsNoError(t *testing.T) { + if _, err := VMOVMSKPD(opxmm, opr32); err != nil { + t.Fatal(err) + } + if _, err := VMOVMSKPD(opymm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVMOVMSKPSValidFormsNoError(t *testing.T) { + if _, err := VMOVMSKPS(opxmm, opr32); err != nil { + t.Fatal(err) + } + if _, err := VMOVMSKPS(opymm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVMOVNTDQValidFormsNoError(t *testing.T) { + if _, err := VMOVNTDQ(opxmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVNTDQ(opymm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVNTDQ(opzmm, opm512); err != nil { + t.Fatal(err) + } +} + +func TestVMOVNTDQAValidFormsNoError(t *testing.T) { + if _, err := VMOVNTDQA(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVNTDQA(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVNTDQA(opm512, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVNTPDValidFormsNoError(t *testing.T) { + if _, err := VMOVNTPD(opxmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVNTPD(opymm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVNTPD(opzmm, opm512); err != nil { + t.Fatal(err) + } +} + +func TestVMOVNTPSValidFormsNoError(t *testing.T) { + if _, err := VMOVNTPS(opxmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVNTPS(opymm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVNTPS(opzmm, opm512); err != nil { + t.Fatal(err) + } +} + +func TestVMOVQValidFormsNoError(t *testing.T) { + if _, err := VMOVQ(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVQ(opr64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVQ(opxmm, opm64); err != nil { + t.Fatal(err) + } + if _, err := VMOVQ(opxmm, opr64); err != nil { + t.Fatal(err) + } + if _, err := VMOVQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVSDValidFormsNoError(t *testing.T) { + if _, err := VMOVSD(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSD(opxmm, opm64); err != nil { + t.Fatal(err) + } + if _, err := VMOVSD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSD(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSD(opxmm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VMOVSD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVSD_ZValidFormsNoError(t *testing.T) { + if _, err := VMOVSD_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVSHDUPValidFormsNoError(t *testing.T) { + if _, err := VMOVSHDUP(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSHDUP(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSHDUP(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSHDUP(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSHDUP(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSHDUP(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSHDUP(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSHDUP(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSHDUP(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSHDUP(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSHDUP(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSHDUP(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVSHDUP_ZValidFormsNoError(t *testing.T) { + if _, err := VMOVSHDUP_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSHDUP_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSHDUP_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSHDUP_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSHDUP_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSHDUP_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVSLDUPValidFormsNoError(t *testing.T) { + if _, err := VMOVSLDUP(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSLDUP(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSLDUP(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSLDUP(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSLDUP(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSLDUP(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSLDUP(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSLDUP(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSLDUP(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSLDUP(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSLDUP(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSLDUP(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVSLDUP_ZValidFormsNoError(t *testing.T) { + if _, err := VMOVSLDUP_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSLDUP_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSLDUP_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSLDUP_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSLDUP_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSLDUP_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVSSValidFormsNoError(t *testing.T) { + if _, err := VMOVSS(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSS(opxmm, opm32); err != nil { + t.Fatal(err) + } + if _, err := VMOVSS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSS(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSS(opxmm, opk, opm32); err != nil { + t.Fatal(err) + } + if _, err := VMOVSS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVSS_ZValidFormsNoError(t *testing.T) { + if _, err := VMOVSS_Z(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVSS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVUPDValidFormsNoError(t *testing.T) { + if _, err := VMOVUPD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPD(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPD(opxmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPD(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPD(opymm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPD(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPD(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPD(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPD(opxmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPD(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPD(opymm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPD(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPD(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPD(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPD(opzmm, opk, opm512); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPD(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPD(opzmm, opm512); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPD(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVUPD_ZValidFormsNoError(t *testing.T) { + if _, err := VMOVUPD_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPD_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPD_Z(opxmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPD_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPD_Z(opymm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPD_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPD_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPD_Z(opzmm, opk, opm512); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPD_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVUPSValidFormsNoError(t *testing.T) { + if _, err := VMOVUPS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPS(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPS(opxmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPS(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPS(opymm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPS(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPS(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPS(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPS(opxmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPS(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPS(opymm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPS(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPS(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPS(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPS(opzmm, opk, opm512); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPS(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPS(opzmm, opm512); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPS(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMOVUPS_ZValidFormsNoError(t *testing.T) { + if _, err := VMOVUPS_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPS_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPS_Z(opxmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPS_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPS_Z(opymm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPS_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPS_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPS_Z(opzmm, opk, opm512); err != nil { + t.Fatal(err) + } + if _, err := VMOVUPS_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMPSADBWValidFormsNoError(t *testing.T) { + if _, err := VMPSADBW(opimm8, opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMPSADBW(opimm8, opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMPSADBW(opimm8, opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMPSADBW(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULPDValidFormsNoError(t *testing.T) { + if _, err := VMULPD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMULPD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMULPD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMULPD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMULPD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULPD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VMULPD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMULPD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMULPD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULPD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VMULPD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMULPD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULPD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VMULPD_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPD_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULPD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VMULPD_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULPD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VMULPD_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPD_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULPD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VMULPD_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULPD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VMULPD_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPD_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULPD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VMULPD_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULPD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VMULPD_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPD_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULPD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VMULPD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULPD_ZValidFormsNoError(t *testing.T) { + if _, err := VMULPD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMULPD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMULPD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULPSValidFormsNoError(t *testing.T) { + if _, err := VMULPS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMULPS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMULPS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMULPS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMULPS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULPS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VMULPS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMULPS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMULPS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULPS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VMULPS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMULPS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULPS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VMULPS_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPS_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULPS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VMULPS_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULPS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VMULPS_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPS_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULPS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VMULPS_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULPS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VMULPS_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPS_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULPS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VMULPS_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULPS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VMULPS_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPS_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULPS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VMULPS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULPS_ZValidFormsNoError(t *testing.T) { + if _, err := VMULPS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMULPS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VMULPS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VMULPS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULSDValidFormsNoError(t *testing.T) { + if _, err := VMULSD(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULSD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULSD(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULSD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULSD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VMULSD_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULSD_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULSD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VMULSD_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULSD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VMULSD_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULSD_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULSD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VMULSD_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULSD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VMULSD_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULSD_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULSD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VMULSD_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULSD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VMULSD_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULSD_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULSD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VMULSD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULSD_ZValidFormsNoError(t *testing.T) { + if _, err := VMULSD_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULSD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULSSValidFormsNoError(t *testing.T) { + if _, err := VMULSS(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULSS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULSS(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULSS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULSS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VMULSS_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULSS_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULSS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VMULSS_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULSS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VMULSS_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULSS_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULSS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VMULSS_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULSS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VMULSS_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULSS_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULSS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VMULSS_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULSS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VMULSS_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULSS_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULSS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VMULSS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVMULSS_ZValidFormsNoError(t *testing.T) { + if _, err := VMULSS_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VMULSS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVORPDValidFormsNoError(t *testing.T) { + if _, err := VORPD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VORPD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VORPD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VORPD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VORPD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VORPD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VORPD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VORPD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VORPD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VORPD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VORPD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VORPD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVORPD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VORPD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VORPD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VORPD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VORPD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VORPD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VORPD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVORPD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VORPD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VORPD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VORPD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVORPD_ZValidFormsNoError(t *testing.T) { + if _, err := VORPD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VORPD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VORPD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VORPD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VORPD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VORPD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVORPSValidFormsNoError(t *testing.T) { + if _, err := VORPS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VORPS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VORPS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VORPS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VORPS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VORPS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VORPS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VORPS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VORPS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VORPS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VORPS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VORPS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVORPS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VORPS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VORPS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VORPS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VORPS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VORPS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VORPS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVORPS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VORPS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VORPS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VORPS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVORPS_ZValidFormsNoError(t *testing.T) { + if _, err := VORPS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VORPS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VORPS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VORPS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VORPS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VORPS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPABSBValidFormsNoError(t *testing.T) { + if _, err := VPABSB(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPABSB(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPABSB(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSB(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSB(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSB(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPABSB(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSB(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPABSB(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSB(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSB(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSB(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPABSB_ZValidFormsNoError(t *testing.T) { + if _, err := VPABSB_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSB_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPABSB_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSB_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPABSB_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSB_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPABSDValidFormsNoError(t *testing.T) { + if _, err := VPABSD(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPABSD(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPABSD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSD(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSD(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSD(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPABSD(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSD(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPABSD(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSD(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSD(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSD(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPABSD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPABSD_BCST(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSD_BCST(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPABSD_BCST(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSD_BCST(opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPABSD_BCST(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSD_BCST(opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPABSD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPABSD_BCST_Z(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSD_BCST_Z(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPABSD_BCST_Z(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPABSD_ZValidFormsNoError(t *testing.T) { + if _, err := VPABSD_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSD_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPABSD_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSD_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPABSD_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSD_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPABSQValidFormsNoError(t *testing.T) { + if _, err := VPABSQ(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSQ(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSQ(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPABSQ(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPABSQ(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSQ(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPABSQ(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPABSQ(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSQ(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSQ(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSQ(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPABSQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPABSQ_BCST(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSQ_BCST(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPABSQ_BCST(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSQ_BCST(opm64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPABSQ_BCST(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSQ_BCST(opm64, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPABSQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPABSQ_BCST_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSQ_BCST_Z(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPABSQ_BCST_Z(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPABSQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPABSQ_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSQ_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPABSQ_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSQ_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPABSQ_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSQ_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPABSWValidFormsNoError(t *testing.T) { + if _, err := VPABSW(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPABSW(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPABSW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSW(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSW(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSW(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPABSW(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSW(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPABSW(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSW(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSW(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSW(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPABSW_ZValidFormsNoError(t *testing.T) { + if _, err := VPABSW_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSW_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPABSW_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSW_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPABSW_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPABSW_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPACKSSDWValidFormsNoError(t *testing.T) { + if _, err := VPACKSSDW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSDW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSDW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSDW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSDW(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSDW(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSDW(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSDW(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSDW(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSDW(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSDW(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSDW(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPACKSSDW_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPACKSSDW_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSDW_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSDW_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSDW_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSDW_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSDW_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPACKSSDW_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPACKSSDW_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSDW_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSDW_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPACKSSDW_ZValidFormsNoError(t *testing.T) { + if _, err := VPACKSSDW_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSDW_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSDW_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSDW_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSDW_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSDW_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPACKSSWBValidFormsNoError(t *testing.T) { + if _, err := VPACKSSWB(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSWB(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSWB(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSWB(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSWB(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSWB(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSWB(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSWB(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSWB(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSWB(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSWB(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSWB(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPACKSSWB_ZValidFormsNoError(t *testing.T) { + if _, err := VPACKSSWB_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSWB_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSWB_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSWB_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSWB_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKSSWB_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPACKUSDWValidFormsNoError(t *testing.T) { + if _, err := VPACKUSDW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSDW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSDW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSDW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSDW(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSDW(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSDW(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSDW(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSDW(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSDW(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSDW(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSDW(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPACKUSDW_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPACKUSDW_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSDW_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSDW_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSDW_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSDW_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSDW_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPACKUSDW_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPACKUSDW_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSDW_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSDW_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPACKUSDW_ZValidFormsNoError(t *testing.T) { + if _, err := VPACKUSDW_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSDW_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSDW_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSDW_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSDW_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSDW_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPACKUSWBValidFormsNoError(t *testing.T) { + if _, err := VPACKUSWB(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSWB(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSWB(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSWB(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSWB(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSWB(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSWB(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSWB(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSWB(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSWB(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSWB(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSWB(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPACKUSWB_ZValidFormsNoError(t *testing.T) { + if _, err := VPACKUSWB_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSWB_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSWB_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSWB_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSWB_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPACKUSWB_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPADDBValidFormsNoError(t *testing.T) { + if _, err := VPADDB(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDB(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDB(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDB(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDB(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDB(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDB(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDB(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDB(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDB(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDB(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDB(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPADDB_ZValidFormsNoError(t *testing.T) { + if _, err := VPADDB_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDB_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDB_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDB_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDB_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDB_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPADDDValidFormsNoError(t *testing.T) { + if _, err := VPADDD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPADDD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPADDD_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDD_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDD_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDD_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDD_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDD_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPADDD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPADDD_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDD_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDD_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPADDD_ZValidFormsNoError(t *testing.T) { + if _, err := VPADDD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPADDQValidFormsNoError(t *testing.T) { + if _, err := VPADDQ(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDQ(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDQ(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDQ(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDQ(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDQ(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDQ(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDQ(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDQ(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDQ(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDQ(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDQ(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPADDQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPADDQ_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDQ_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDQ_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDQ_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDQ_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDQ_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPADDQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPADDQ_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDQ_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDQ_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPADDQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPADDQ_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDQ_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDQ_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDQ_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDQ_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDQ_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPADDSBValidFormsNoError(t *testing.T) { + if _, err := VPADDSB(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSB(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSB(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSB(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSB(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSB(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSB(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSB(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSB(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSB(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSB(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSB(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPADDSB_ZValidFormsNoError(t *testing.T) { + if _, err := VPADDSB_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSB_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSB_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSB_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSB_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSB_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPADDSWValidFormsNoError(t *testing.T) { + if _, err := VPADDSW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSW(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSW(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSW(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSW(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSW(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSW(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSW(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSW(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPADDSW_ZValidFormsNoError(t *testing.T) { + if _, err := VPADDSW_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSW_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSW_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSW_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSW_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDSW_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPADDUSBValidFormsNoError(t *testing.T) { + if _, err := VPADDUSB(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSB(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSB(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSB(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSB(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSB(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSB(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSB(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSB(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSB(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSB(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSB(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPADDUSB_ZValidFormsNoError(t *testing.T) { + if _, err := VPADDUSB_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSB_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSB_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSB_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSB_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSB_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPADDUSWValidFormsNoError(t *testing.T) { + if _, err := VPADDUSW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSW(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSW(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSW(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSW(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSW(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSW(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSW(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSW(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPADDUSW_ZValidFormsNoError(t *testing.T) { + if _, err := VPADDUSW_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSW_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSW_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSW_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSW_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDUSW_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPADDWValidFormsNoError(t *testing.T) { + if _, err := VPADDW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDW(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDW(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDW(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDW(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDW(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDW(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDW(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDW(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPADDW_ZValidFormsNoError(t *testing.T) { + if _, err := VPADDW_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDW_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDW_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDW_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPADDW_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPADDW_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPALIGNRValidFormsNoError(t *testing.T) { + if _, err := VPALIGNR(opimm8, opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPALIGNR(opimm8, opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPALIGNR(opimm8, opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPALIGNR(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPALIGNR(opimm8, opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPALIGNR(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPALIGNR(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPALIGNR(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPALIGNR(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPALIGNR(opimm8, opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPALIGNR(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPALIGNR(opimm8, opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPALIGNR_ZValidFormsNoError(t *testing.T) { + if _, err := VPALIGNR_Z(opimm8, opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPALIGNR_Z(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPALIGNR_Z(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPALIGNR_Z(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPALIGNR_Z(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPALIGNR_Z(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPANDValidFormsNoError(t *testing.T) { + if _, err := VPAND(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPAND(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPAND(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPAND(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPANDDValidFormsNoError(t *testing.T) { + if _, err := VPANDD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPANDD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPANDD_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDD_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDD_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDD_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDD_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDD_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPANDD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPANDD_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDD_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDD_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPANDD_ZValidFormsNoError(t *testing.T) { + if _, err := VPANDD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPANDNValidFormsNoError(t *testing.T) { + if _, err := VPANDN(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDN(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDN(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDN(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPANDNDValidFormsNoError(t *testing.T) { + if _, err := VPANDND(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDND(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDND(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDND(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDND(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDND(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDND(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDND(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDND(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDND(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDND(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDND(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPANDND_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPANDND_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDND_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDND_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDND_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDND_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDND_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPANDND_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPANDND_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDND_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDND_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPANDND_ZValidFormsNoError(t *testing.T) { + if _, err := VPANDND_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDND_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDND_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDND_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDND_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDND_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPANDNQValidFormsNoError(t *testing.T) { + if _, err := VPANDNQ(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDNQ(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDNQ(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDNQ(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDNQ(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDNQ(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDNQ(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDNQ(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDNQ(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDNQ(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDNQ(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDNQ(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPANDNQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPANDNQ_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDNQ_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDNQ_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDNQ_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDNQ_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDNQ_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPANDNQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPANDNQ_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDNQ_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDNQ_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPANDNQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPANDNQ_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDNQ_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDNQ_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDNQ_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDNQ_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDNQ_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPANDQValidFormsNoError(t *testing.T) { + if _, err := VPANDQ(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDQ(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDQ(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDQ(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDQ(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDQ(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDQ(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDQ(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDQ(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDQ(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDQ(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDQ(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPANDQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPANDQ_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDQ_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDQ_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDQ_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDQ_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDQ_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPANDQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPANDQ_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDQ_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDQ_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPANDQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPANDQ_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDQ_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDQ_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDQ_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPANDQ_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPANDQ_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPAVGBValidFormsNoError(t *testing.T) { + if _, err := VPAVGB(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGB(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGB(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGB(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGB(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGB(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGB(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGB(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGB(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGB(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGB(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGB(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPAVGB_ZValidFormsNoError(t *testing.T) { + if _, err := VPAVGB_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGB_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGB_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGB_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGB_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGB_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPAVGWValidFormsNoError(t *testing.T) { + if _, err := VPAVGW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGW(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGW(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGW(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGW(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGW(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGW(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGW(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGW(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPAVGW_ZValidFormsNoError(t *testing.T) { + if _, err := VPAVGW_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGW_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGW_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGW_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGW_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPAVGW_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPBLENDDValidFormsNoError(t *testing.T) { + if _, err := VPBLENDD(opimm8, opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDD(opimm8, opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDD(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDD(opimm8, opymm, opymm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVPBLENDMBValidFormsNoError(t *testing.T) { + if _, err := VPBLENDMB(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMB(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMB(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMB(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMB(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMB(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMB(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMB(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMB(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMB(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMB(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMB(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPBLENDMB_ZValidFormsNoError(t *testing.T) { + if _, err := VPBLENDMB_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMB_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMB_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMB_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMB_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMB_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPBLENDMDValidFormsNoError(t *testing.T) { + if _, err := VPBLENDMD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPBLENDMD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPBLENDMD_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMD_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMD_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMD_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMD_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMD_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPBLENDMD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPBLENDMD_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMD_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMD_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPBLENDMD_ZValidFormsNoError(t *testing.T) { + if _, err := VPBLENDMD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPBLENDMQValidFormsNoError(t *testing.T) { + if _, err := VPBLENDMQ(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMQ(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMQ(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMQ(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMQ(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMQ(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMQ(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMQ(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMQ(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMQ(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMQ(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMQ(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPBLENDMQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPBLENDMQ_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMQ_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMQ_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMQ_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMQ_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMQ_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPBLENDMQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPBLENDMQ_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMQ_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMQ_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPBLENDMQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPBLENDMQ_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMQ_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMQ_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMQ_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMQ_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMQ_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPBLENDMWValidFormsNoError(t *testing.T) { + if _, err := VPBLENDMW(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMW(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMW(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMW(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMW(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMW(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMW(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMW(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPBLENDMW_ZValidFormsNoError(t *testing.T) { + if _, err := VPBLENDMW_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMW_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMW_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMW_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMW_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDMW_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPBLENDVBValidFormsNoError(t *testing.T) { + if _, err := VPBLENDVB(opymm, opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDVB(opymm, opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDVB(opxmm, opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDVB(opxmm, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPBLENDWValidFormsNoError(t *testing.T) { + if _, err := VPBLENDW(opimm8, opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDW(opimm8, opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDW(opimm8, opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBLENDW(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPBROADCASTBValidFormsNoError(t *testing.T) { + if _, err := VPBROADCASTB(opm8, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTB(opm8, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTB(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTB(opxmm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTB(opm8, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTB(opm8, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTB(opr32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTB(opr32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTB(opr32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTB(opr32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTB(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTB(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTB(opm8, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTB(opm8, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTB(opr32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTB(opr32, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTB(opxmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTB(opxmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPBROADCASTB_ZValidFormsNoError(t *testing.T) { + if _, err := VPBROADCASTB_Z(opm8, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTB_Z(opm8, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTB_Z(opr32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTB_Z(opr32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTB_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTB_Z(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTB_Z(opm8, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTB_Z(opr32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTB_Z(opxmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPBROADCASTDValidFormsNoError(t *testing.T) { + if _, err := VPBROADCASTD(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTD(opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTD(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTD(opxmm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTD(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTD(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTD(opr32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTD(opr32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTD(opr32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTD(opr32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTD(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTD(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTD(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTD(opm32, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTD(opr32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTD(opr32, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTD(opxmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTD(opxmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPBROADCASTD_ZValidFormsNoError(t *testing.T) { + if _, err := VPBROADCASTD_Z(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTD_Z(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTD_Z(opr32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTD_Z(opr32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTD_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTD_Z(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTD_Z(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTD_Z(opr32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTD_Z(opxmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPBROADCASTMB2QValidFormsNoError(t *testing.T) { + if _, err := VPBROADCASTMB2Q(opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTMB2Q(opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTMB2Q(opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPBROADCASTMW2DValidFormsNoError(t *testing.T) { + if _, err := VPBROADCASTMW2D(opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTMW2D(opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTMW2D(opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPBROADCASTQValidFormsNoError(t *testing.T) { + if _, err := VPBROADCASTQ(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTQ(opm64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTQ(opxmm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTQ(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTQ(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTQ(opr64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTQ(opr64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTQ(opr64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTQ(opr64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTQ(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTQ(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTQ(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTQ(opm64, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTQ(opr64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTQ(opr64, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTQ(opxmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTQ(opxmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPBROADCASTQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPBROADCASTQ_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTQ_Z(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTQ_Z(opr64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTQ_Z(opr64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTQ_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTQ_Z(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTQ_Z(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTQ_Z(opr64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTQ_Z(opxmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPBROADCASTWValidFormsNoError(t *testing.T) { + if _, err := VPBROADCASTW(opm16, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTW(opm16, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTW(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTW(opxmm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTW(opm16, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTW(opm16, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTW(opr32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTW(opr32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTW(opr32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTW(opr32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTW(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTW(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTW(opm16, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTW(opm16, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTW(opr32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTW(opr32, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTW(opxmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTW(opxmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPBROADCASTW_ZValidFormsNoError(t *testing.T) { + if _, err := VPBROADCASTW_Z(opm16, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTW_Z(opm16, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTW_Z(opr32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTW_Z(opr32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTW_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTW_Z(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTW_Z(opm16, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTW_Z(opr32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPBROADCASTW_Z(opxmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPCLMULQDQValidFormsNoError(t *testing.T) { + if _, err := VPCLMULQDQ(opimm8, opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCLMULQDQ(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPCMPBValidFormsNoError(t *testing.T) { + if _, err := VPCMPB(opimm8, opm128, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPB(opimm8, opm128, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPB(opimm8, opm256, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPB(opimm8, opm256, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPB(opimm8, opxmm, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPB(opimm8, opxmm, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPB(opimm8, opymm, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPB(opimm8, opymm, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPB(opimm8, opm512, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPB(opimm8, opm512, opzmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPB(opimm8, opzmm, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPB(opimm8, opzmm, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPCMPDValidFormsNoError(t *testing.T) { + if _, err := VPCMPD(opimm8, opm128, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPD(opimm8, opm128, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPD(opimm8, opm256, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPD(opimm8, opm256, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPD(opimm8, opxmm, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPD(opimm8, opxmm, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPD(opimm8, opymm, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPD(opimm8, opymm, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPD(opimm8, opm512, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPD(opimm8, opm512, opzmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPD(opimm8, opzmm, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPD(opimm8, opzmm, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPCMPD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPCMPD_BCST(opimm8, opm32, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPD_BCST(opimm8, opm32, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPD_BCST(opimm8, opm32, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPD_BCST(opimm8, opm32, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPD_BCST(opimm8, opm32, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPD_BCST(opimm8, opm32, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPCMPEQBValidFormsNoError(t *testing.T) { + if _, err := VPCMPEQB(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQB(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQB(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQB(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQB(opm128, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQB(opm128, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQB(opm256, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQB(opm256, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQB(opxmm, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQB(opxmm, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQB(opymm, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQB(opymm, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQB(opm512, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQB(opm512, opzmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQB(opzmm, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQB(opzmm, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPCMPEQDValidFormsNoError(t *testing.T) { + if _, err := VPCMPEQD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQD(opm128, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQD(opm128, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQD(opm256, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQD(opm256, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQD(opxmm, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQD(opxmm, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQD(opymm, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQD(opymm, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQD(opm512, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQD(opm512, opzmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQD(opzmm, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQD(opzmm, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPCMPEQD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPCMPEQD_BCST(opm32, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQD_BCST(opm32, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQD_BCST(opm32, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQD_BCST(opm32, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQD_BCST(opm32, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQD_BCST(opm32, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPCMPEQQValidFormsNoError(t *testing.T) { + if _, err := VPCMPEQQ(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQQ(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQQ(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQQ(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQQ(opm128, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQQ(opm128, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQQ(opm256, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQQ(opm256, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQQ(opxmm, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQQ(opxmm, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQQ(opymm, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQQ(opymm, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQQ(opm512, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQQ(opm512, opzmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQQ(opzmm, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQQ(opzmm, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPCMPEQQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPCMPEQQ_BCST(opm64, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQQ_BCST(opm64, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQQ_BCST(opm64, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQQ_BCST(opm64, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQQ_BCST(opm64, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQQ_BCST(opm64, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPCMPEQWValidFormsNoError(t *testing.T) { + if _, err := VPCMPEQW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQW(opm128, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQW(opm128, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQW(opm256, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQW(opm256, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQW(opxmm, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQW(opxmm, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQW(opymm, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQW(opymm, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQW(opm512, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQW(opm512, opzmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQW(opzmm, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPEQW(opzmm, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPCMPESTRIValidFormsNoError(t *testing.T) { + if _, err := VPCMPESTRI(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPESTRI(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPCMPESTRMValidFormsNoError(t *testing.T) { + if _, err := VPCMPESTRM(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPESTRM(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPCMPGTBValidFormsNoError(t *testing.T) { + if _, err := VPCMPGTB(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTB(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTB(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTB(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTB(opm128, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTB(opm128, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTB(opm256, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTB(opm256, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTB(opxmm, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTB(opxmm, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTB(opymm, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTB(opymm, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTB(opm512, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTB(opm512, opzmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTB(opzmm, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTB(opzmm, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPCMPGTDValidFormsNoError(t *testing.T) { + if _, err := VPCMPGTD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTD(opm128, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTD(opm128, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTD(opm256, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTD(opm256, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTD(opxmm, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTD(opxmm, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTD(opymm, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTD(opymm, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTD(opm512, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTD(opm512, opzmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTD(opzmm, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTD(opzmm, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPCMPGTD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPCMPGTD_BCST(opm32, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTD_BCST(opm32, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTD_BCST(opm32, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTD_BCST(opm32, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTD_BCST(opm32, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTD_BCST(opm32, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPCMPGTQValidFormsNoError(t *testing.T) { + if _, err := VPCMPGTQ(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTQ(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTQ(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTQ(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTQ(opm128, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTQ(opm128, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTQ(opm256, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTQ(opm256, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTQ(opxmm, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTQ(opxmm, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTQ(opymm, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTQ(opymm, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTQ(opm512, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTQ(opm512, opzmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTQ(opzmm, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTQ(opzmm, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPCMPGTQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPCMPGTQ_BCST(opm64, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTQ_BCST(opm64, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTQ_BCST(opm64, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTQ_BCST(opm64, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTQ_BCST(opm64, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTQ_BCST(opm64, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPCMPGTWValidFormsNoError(t *testing.T) { + if _, err := VPCMPGTW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTW(opm128, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTW(opm128, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTW(opm256, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTW(opm256, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTW(opxmm, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTW(opxmm, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTW(opymm, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTW(opymm, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTW(opm512, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTW(opm512, opzmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTW(opzmm, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPGTW(opzmm, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPCMPISTRIValidFormsNoError(t *testing.T) { + if _, err := VPCMPISTRI(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPISTRI(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPCMPISTRMValidFormsNoError(t *testing.T) { + if _, err := VPCMPISTRM(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCMPISTRM(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPCMPQValidFormsNoError(t *testing.T) { + if _, err := VPCMPQ(opimm8, opm128, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPQ(opimm8, opm128, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPQ(opimm8, opm256, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPQ(opimm8, opm256, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPQ(opimm8, opxmm, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPQ(opimm8, opxmm, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPQ(opimm8, opymm, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPQ(opimm8, opymm, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPQ(opimm8, opm512, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPQ(opimm8, opm512, opzmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPQ(opimm8, opzmm, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPQ(opimm8, opzmm, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPCMPQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPCMPQ_BCST(opimm8, opm64, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPQ_BCST(opimm8, opm64, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPQ_BCST(opimm8, opm64, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPQ_BCST(opimm8, opm64, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPQ_BCST(opimm8, opm64, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPQ_BCST(opimm8, opm64, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPCMPUBValidFormsNoError(t *testing.T) { + if _, err := VPCMPUB(opimm8, opm128, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUB(opimm8, opm128, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUB(opimm8, opm256, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUB(opimm8, opm256, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUB(opimm8, opxmm, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUB(opimm8, opxmm, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUB(opimm8, opymm, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUB(opimm8, opymm, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUB(opimm8, opm512, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUB(opimm8, opm512, opzmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUB(opimm8, opzmm, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUB(opimm8, opzmm, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPCMPUDValidFormsNoError(t *testing.T) { + if _, err := VPCMPUD(opimm8, opm128, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUD(opimm8, opm128, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUD(opimm8, opm256, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUD(opimm8, opm256, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUD(opimm8, opxmm, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUD(opimm8, opxmm, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUD(opimm8, opymm, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUD(opimm8, opymm, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUD(opimm8, opm512, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUD(opimm8, opm512, opzmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUD(opimm8, opzmm, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUD(opimm8, opzmm, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPCMPUD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPCMPUD_BCST(opimm8, opm32, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUD_BCST(opimm8, opm32, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUD_BCST(opimm8, opm32, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUD_BCST(opimm8, opm32, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUD_BCST(opimm8, opm32, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUD_BCST(opimm8, opm32, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPCMPUQValidFormsNoError(t *testing.T) { + if _, err := VPCMPUQ(opimm8, opm128, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUQ(opimm8, opm128, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUQ(opimm8, opm256, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUQ(opimm8, opm256, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUQ(opimm8, opxmm, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUQ(opimm8, opxmm, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUQ(opimm8, opymm, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUQ(opimm8, opymm, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUQ(opimm8, opm512, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUQ(opimm8, opm512, opzmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUQ(opimm8, opzmm, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUQ(opimm8, opzmm, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPCMPUQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPCMPUQ_BCST(opimm8, opm64, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUQ_BCST(opimm8, opm64, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUQ_BCST(opimm8, opm64, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUQ_BCST(opimm8, opm64, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUQ_BCST(opimm8, opm64, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUQ_BCST(opimm8, opm64, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPCMPUWValidFormsNoError(t *testing.T) { + if _, err := VPCMPUW(opimm8, opm128, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUW(opimm8, opm128, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUW(opimm8, opm256, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUW(opimm8, opm256, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUW(opimm8, opxmm, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUW(opimm8, opxmm, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUW(opimm8, opymm, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUW(opimm8, opymm, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUW(opimm8, opm512, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUW(opimm8, opm512, opzmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUW(opimm8, opzmm, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPUW(opimm8, opzmm, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPCMPWValidFormsNoError(t *testing.T) { + if _, err := VPCMPW(opimm8, opm128, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPW(opimm8, opm128, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPW(opimm8, opm256, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPW(opimm8, opm256, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPW(opimm8, opxmm, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPW(opimm8, opxmm, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPW(opimm8, opymm, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPW(opimm8, opymm, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPW(opimm8, opm512, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPW(opimm8, opm512, opzmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPW(opimm8, opzmm, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPCMPW(opimm8, opzmm, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPCOMPRESSDValidFormsNoError(t *testing.T) { + if _, err := VPCOMPRESSD(opxmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSD(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSD(opxmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSD(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSD(opymm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSD(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSD(opymm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSD(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSD(opzmm, opk, opm512); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSD(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSD(opzmm, opm512); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSD(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPCOMPRESSD_ZValidFormsNoError(t *testing.T) { + if _, err := VPCOMPRESSD_Z(opxmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSD_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSD_Z(opymm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSD_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSD_Z(opzmm, opk, opm512); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSD_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPCOMPRESSQValidFormsNoError(t *testing.T) { + if _, err := VPCOMPRESSQ(opxmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSQ(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSQ(opxmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSQ(opymm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSQ(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSQ(opymm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSQ(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSQ(opzmm, opk, opm512); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSQ(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSQ(opzmm, opm512); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSQ(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPCOMPRESSQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPCOMPRESSQ_Z(opxmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSQ_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSQ_Z(opymm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSQ_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSQ_Z(opzmm, opk, opm512); err != nil { + t.Fatal(err) + } + if _, err := VPCOMPRESSQ_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPCONFLICTDValidFormsNoError(t *testing.T) { + if _, err := VPCONFLICTD(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTD(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTD(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTD(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTD(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTD(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTD(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTD(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTD(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTD(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTD(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPCONFLICTD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPCONFLICTD_BCST(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTD_BCST(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTD_BCST(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTD_BCST(opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTD_BCST(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTD_BCST(opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPCONFLICTD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPCONFLICTD_BCST_Z(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTD_BCST_Z(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTD_BCST_Z(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPCONFLICTD_ZValidFormsNoError(t *testing.T) { + if _, err := VPCONFLICTD_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTD_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTD_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTD_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTD_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTD_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPCONFLICTQValidFormsNoError(t *testing.T) { + if _, err := VPCONFLICTQ(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTQ(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTQ(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTQ(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTQ(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTQ(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTQ(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTQ(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTQ(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTQ(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTQ(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPCONFLICTQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPCONFLICTQ_BCST(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTQ_BCST(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTQ_BCST(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTQ_BCST(opm64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTQ_BCST(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTQ_BCST(opm64, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPCONFLICTQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPCONFLICTQ_BCST_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTQ_BCST_Z(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTQ_BCST_Z(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPCONFLICTQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPCONFLICTQ_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTQ_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTQ_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTQ_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTQ_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPCONFLICTQ_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERM2F128ValidFormsNoError(t *testing.T) { + if _, err := VPERM2F128(opimm8, opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERM2F128(opimm8, opymm, opymm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVPERM2I128ValidFormsNoError(t *testing.T) { + if _, err := VPERM2I128(opimm8, opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERM2I128(opimm8, opymm, opymm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMBValidFormsNoError(t *testing.T) { + if _, err := VPERMB(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMB(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMB(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMB(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMB(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMB(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMB(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMB(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMB(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMB(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMB(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMB(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMB_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMB_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMB_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMB_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMB_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMB_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMB_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMDValidFormsNoError(t *testing.T) { + if _, err := VPERMD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPERMD_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMD_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMD_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMD_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMD_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMD_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMD_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMI2BValidFormsNoError(t *testing.T) { + if _, err := VPERMI2B(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2B(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2B(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2B(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2B(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2B(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2B(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2B(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2B(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2B(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2B(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2B(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMI2B_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMI2B_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2B_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2B_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2B_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2B_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2B_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMI2DValidFormsNoError(t *testing.T) { + if _, err := VPERMI2D(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2D(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2D(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2D(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2D(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2D(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2D(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2D(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2D(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2D(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2D(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2D(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMI2D_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPERMI2D_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2D_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2D_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2D_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2D_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2D_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMI2D_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMI2D_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2D_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2D_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMI2D_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMI2D_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2D_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2D_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2D_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2D_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2D_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMI2PDValidFormsNoError(t *testing.T) { + if _, err := VPERMI2PD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMI2PD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPERMI2PD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMI2PD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMI2PD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMI2PD_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMI2PD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMI2PSValidFormsNoError(t *testing.T) { + if _, err := VPERMI2PS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMI2PS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPERMI2PS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMI2PS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMI2PS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMI2PS_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMI2PS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2PS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMI2QValidFormsNoError(t *testing.T) { + if _, err := VPERMI2Q(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2Q(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2Q(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2Q(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2Q(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2Q(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2Q(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2Q(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2Q(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2Q(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2Q(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2Q(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMI2Q_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPERMI2Q_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2Q_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2Q_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2Q_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2Q_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2Q_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMI2Q_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMI2Q_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2Q_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2Q_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMI2Q_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMI2Q_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2Q_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2Q_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2Q_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2Q_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2Q_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMI2WValidFormsNoError(t *testing.T) { + if _, err := VPERMI2W(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2W(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2W(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2W(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2W(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2W(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2W(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2W(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2W(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2W(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2W(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2W(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMI2W_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMI2W_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2W_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2W_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2W_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2W_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMI2W_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMILPDValidFormsNoError(t *testing.T) { + if _, err := VPERMILPD(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD(opimm8, opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD(opimm8, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD(opimm8, opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMILPD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPERMILPD_BCST(opimm8, opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD_BCST(opimm8, opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD_BCST(opimm8, opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD_BCST(opimm8, opm64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD_BCST(opimm8, opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD_BCST(opimm8, opm64, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMILPD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMILPD_BCST_Z(opimm8, opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD_BCST_Z(opimm8, opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD_BCST_Z(opimm8, opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMILPD_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMILPD_Z(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD_Z(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD_Z(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD_Z(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD_Z(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD_Z(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMILPSValidFormsNoError(t *testing.T) { + if _, err := VPERMILPS(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS(opimm8, opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS(opimm8, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS(opimm8, opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMILPS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPERMILPS_BCST(opimm8, opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS_BCST(opimm8, opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS_BCST(opimm8, opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS_BCST(opimm8, opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS_BCST(opimm8, opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS_BCST(opimm8, opm32, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMILPS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMILPS_BCST_Z(opimm8, opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS_BCST_Z(opimm8, opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS_BCST_Z(opimm8, opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMILPS_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMILPS_Z(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS_Z(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS_Z(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS_Z(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS_Z(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS_Z(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMILPS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMPDValidFormsNoError(t *testing.T) { + if _, err := VPERMPD(opimm8, opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD(opimm8, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD(opimm8, opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMPD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPERMPD_BCST(opimm8, opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD_BCST(opimm8, opm64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD_BCST(opimm8, opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD_BCST(opimm8, opm64, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMPD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMPD_BCST_Z(opimm8, opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD_BCST_Z(opimm8, opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMPD_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMPD_Z(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD_Z(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD_Z(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD_Z(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMPSValidFormsNoError(t *testing.T) { + if _, err := VPERMPS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMPS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPERMPS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMPS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMPS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMPS_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMPS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMPS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMQValidFormsNoError(t *testing.T) { + if _, err := VPERMQ(opimm8, opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ(opimm8, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ(opimm8, opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPERMQ_BCST(opimm8, opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ_BCST(opimm8, opm64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ_BCST(opimm8, opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ_BCST(opimm8, opm64, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMQ_BCST_Z(opimm8, opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ_BCST_Z(opimm8, opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMQ_Z(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ_Z(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ_Z(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ_Z(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMQ_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMT2BValidFormsNoError(t *testing.T) { + if _, err := VPERMT2B(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2B(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2B(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2B(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2B(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2B(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2B(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2B(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2B(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2B(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2B(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2B(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMT2B_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMT2B_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2B_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2B_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2B_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2B_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2B_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMT2DValidFormsNoError(t *testing.T) { + if _, err := VPERMT2D(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2D(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2D(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2D(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2D(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2D(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2D(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2D(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2D(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2D(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2D(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2D(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMT2D_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPERMT2D_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2D_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2D_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2D_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2D_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2D_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMT2D_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMT2D_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2D_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2D_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMT2D_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMT2D_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2D_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2D_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2D_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2D_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2D_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMT2PDValidFormsNoError(t *testing.T) { + if _, err := VPERMT2PD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMT2PD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPERMT2PD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMT2PD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMT2PD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMT2PD_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMT2PD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMT2PSValidFormsNoError(t *testing.T) { + if _, err := VPERMT2PS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMT2PS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPERMT2PS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMT2PS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMT2PS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMT2PS_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMT2PS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2PS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMT2QValidFormsNoError(t *testing.T) { + if _, err := VPERMT2Q(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2Q(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2Q(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2Q(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2Q(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2Q(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2Q(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2Q(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2Q(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2Q(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2Q(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2Q(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMT2Q_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPERMT2Q_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2Q_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2Q_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2Q_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2Q_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2Q_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMT2Q_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMT2Q_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2Q_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2Q_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMT2Q_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMT2Q_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2Q_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2Q_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2Q_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2Q_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2Q_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMT2WValidFormsNoError(t *testing.T) { + if _, err := VPERMT2W(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2W(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2W(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2W(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2W(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2W(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2W(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2W(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2W(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2W(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2W(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2W(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMT2W_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMT2W_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2W_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2W_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2W_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2W_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMT2W_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMWValidFormsNoError(t *testing.T) { + if _, err := VPERMW(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMW(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMW(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMW(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMW(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMW(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMW(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMW(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPERMW_ZValidFormsNoError(t *testing.T) { + if _, err := VPERMW_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMW_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMW_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMW_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPERMW_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPERMW_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPEXPANDDValidFormsNoError(t *testing.T) { + if _, err := VPEXPANDD(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDD(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDD(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDD(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDD(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDD(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDD(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDD(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDD(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDD(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDD(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPEXPANDD_ZValidFormsNoError(t *testing.T) { + if _, err := VPEXPANDD_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDD_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDD_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDD_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDD_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDD_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPEXPANDQValidFormsNoError(t *testing.T) { + if _, err := VPEXPANDQ(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDQ(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDQ(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDQ(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDQ(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDQ(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDQ(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDQ(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDQ(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDQ(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDQ(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPEXPANDQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPEXPANDQ_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDQ_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDQ_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDQ_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDQ_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPEXPANDQ_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPEXTRBValidFormsNoError(t *testing.T) { + if _, err := VPEXTRB(opimm8, opxmm, opm8); err != nil { + t.Fatal(err) + } + if _, err := VPEXTRB(opimm8, opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVPEXTRDValidFormsNoError(t *testing.T) { + if _, err := VPEXTRD(opimm8, opxmm, opm32); err != nil { + t.Fatal(err) + } + if _, err := VPEXTRD(opimm8, opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVPEXTRQValidFormsNoError(t *testing.T) { + if _, err := VPEXTRQ(opimm8, opxmm, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPEXTRQ(opimm8, opxmm, opr64); err != nil { + t.Fatal(err) + } +} + +func TestVPEXTRWValidFormsNoError(t *testing.T) { + if _, err := VPEXTRW(opimm8, opxmm, opm16); err != nil { + t.Fatal(err) + } + if _, err := VPEXTRW(opimm8, opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVPGATHERDDValidFormsNoError(t *testing.T) { + if _, err := VPGATHERDD(opxmm, opvm32x, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPGATHERDD(opymm, opvm32y, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPGATHERDD(opvm32x, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPGATHERDD(opvm32y, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPGATHERDD(opvm32z, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPGATHERDQValidFormsNoError(t *testing.T) { + if _, err := VPGATHERDQ(opxmm, opvm32x, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPGATHERDQ(opymm, opvm32x, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPGATHERDQ(opvm32x, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPGATHERDQ(opvm32x, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPGATHERDQ(opvm32y, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPGATHERQDValidFormsNoError(t *testing.T) { + if _, err := VPGATHERQD(opxmm, opvm64x, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPGATHERQD(opxmm, opvm64y, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPGATHERQD(opvm64x, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPGATHERQD(opvm64y, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPGATHERQD(opvm64z, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVPGATHERQQValidFormsNoError(t *testing.T) { + if _, err := VPGATHERQQ(opxmm, opvm64x, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPGATHERQQ(opymm, opvm64y, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPGATHERQQ(opvm64x, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPGATHERQQ(opvm64y, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPGATHERQQ(opvm64z, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPHADDDValidFormsNoError(t *testing.T) { + if _, err := VPHADDD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPHADDD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPHADDD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPHADDD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPHADDSWValidFormsNoError(t *testing.T) { + if _, err := VPHADDSW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPHADDSW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPHADDSW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPHADDSW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPHADDWValidFormsNoError(t *testing.T) { + if _, err := VPHADDW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPHADDW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPHADDW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPHADDW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPHMINPOSUWValidFormsNoError(t *testing.T) { + if _, err := VPHMINPOSUW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPHMINPOSUW(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPHSUBDValidFormsNoError(t *testing.T) { + if _, err := VPHSUBD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPHSUBD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPHSUBD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPHSUBD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPHSUBSWValidFormsNoError(t *testing.T) { + if _, err := VPHSUBSW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPHSUBSW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPHSUBSW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPHSUBSW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPHSUBWValidFormsNoError(t *testing.T) { + if _, err := VPHSUBW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPHSUBW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPHSUBW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPHSUBW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPINSRBValidFormsNoError(t *testing.T) { + if _, err := VPINSRB(opimm8, opm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPINSRB(opimm8, opr32, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPINSRDValidFormsNoError(t *testing.T) { + if _, err := VPINSRD(opimm8, opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPINSRD(opimm8, opr32, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPINSRQValidFormsNoError(t *testing.T) { + if _, err := VPINSRQ(opimm8, opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPINSRQ(opimm8, opr64, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPINSRWValidFormsNoError(t *testing.T) { + if _, err := VPINSRW(opimm8, opm16, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPINSRW(opimm8, opr32, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPLZCNTDValidFormsNoError(t *testing.T) { + if _, err := VPLZCNTD(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTD(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTD(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTD(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTD(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTD(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTD(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTD(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTD(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTD(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTD(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPLZCNTD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPLZCNTD_BCST(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTD_BCST(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTD_BCST(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTD_BCST(opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTD_BCST(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTD_BCST(opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPLZCNTD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPLZCNTD_BCST_Z(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTD_BCST_Z(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTD_BCST_Z(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPLZCNTD_ZValidFormsNoError(t *testing.T) { + if _, err := VPLZCNTD_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTD_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTD_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTD_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTD_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTD_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPLZCNTQValidFormsNoError(t *testing.T) { + if _, err := VPLZCNTQ(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTQ(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTQ(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTQ(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTQ(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTQ(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTQ(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTQ(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTQ(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTQ(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTQ(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPLZCNTQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPLZCNTQ_BCST(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTQ_BCST(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTQ_BCST(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTQ_BCST(opm64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTQ_BCST(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTQ_BCST(opm64, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPLZCNTQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPLZCNTQ_BCST_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTQ_BCST_Z(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTQ_BCST_Z(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPLZCNTQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPLZCNTQ_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTQ_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTQ_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTQ_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTQ_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPLZCNTQ_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMADD52HUQValidFormsNoError(t *testing.T) { + if _, err := VPMADD52HUQ(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52HUQ(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52HUQ(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52HUQ(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52HUQ(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52HUQ(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52HUQ(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52HUQ(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52HUQ(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52HUQ(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52HUQ(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52HUQ(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMADD52HUQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPMADD52HUQ_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52HUQ_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52HUQ_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52HUQ_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52HUQ_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52HUQ_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMADD52HUQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPMADD52HUQ_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52HUQ_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52HUQ_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMADD52HUQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPMADD52HUQ_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52HUQ_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52HUQ_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52HUQ_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52HUQ_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52HUQ_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMADD52LUQValidFormsNoError(t *testing.T) { + if _, err := VPMADD52LUQ(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52LUQ(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52LUQ(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52LUQ(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52LUQ(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52LUQ(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52LUQ(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52LUQ(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52LUQ(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52LUQ(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52LUQ(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52LUQ(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMADD52LUQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPMADD52LUQ_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52LUQ_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52LUQ_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52LUQ_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52LUQ_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52LUQ_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMADD52LUQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPMADD52LUQ_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52LUQ_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52LUQ_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMADD52LUQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPMADD52LUQ_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52LUQ_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52LUQ_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52LUQ_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52LUQ_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADD52LUQ_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMADDUBSWValidFormsNoError(t *testing.T) { + if _, err := VPMADDUBSW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDUBSW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDUBSW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDUBSW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDUBSW(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDUBSW(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDUBSW(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDUBSW(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDUBSW(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDUBSW(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDUBSW(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDUBSW(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMADDUBSW_ZValidFormsNoError(t *testing.T) { + if _, err := VPMADDUBSW_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDUBSW_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDUBSW_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDUBSW_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDUBSW_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDUBSW_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMADDWDValidFormsNoError(t *testing.T) { + if _, err := VPMADDWD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDWD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDWD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDWD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDWD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDWD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDWD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDWD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDWD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDWD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDWD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDWD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMADDWD_ZValidFormsNoError(t *testing.T) { + if _, err := VPMADDWD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDWD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDWD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDWD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDWD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMADDWD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMASKMOVDValidFormsNoError(t *testing.T) { + if _, err := VPMASKMOVD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMASKMOVD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMASKMOVD(opxmm, opxmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMASKMOVD(opymm, opymm, opm256); err != nil { + t.Fatal(err) + } +} + +func TestVPMASKMOVQValidFormsNoError(t *testing.T) { + if _, err := VPMASKMOVQ(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMASKMOVQ(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMASKMOVQ(opxmm, opxmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMASKMOVQ(opymm, opymm, opm256); err != nil { + t.Fatal(err) + } +} + +func TestVPMAXSBValidFormsNoError(t *testing.T) { + if _, err := VPMAXSB(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSB(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSB(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSB(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSB(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSB(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSB(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSB(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSB(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSB(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSB(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSB(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMAXSB_ZValidFormsNoError(t *testing.T) { + if _, err := VPMAXSB_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSB_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSB_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSB_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSB_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSB_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMAXSDValidFormsNoError(t *testing.T) { + if _, err := VPMAXSD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMAXSD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPMAXSD_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSD_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSD_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSD_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSD_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSD_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMAXSD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPMAXSD_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSD_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSD_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMAXSD_ZValidFormsNoError(t *testing.T) { + if _, err := VPMAXSD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMAXSQValidFormsNoError(t *testing.T) { + if _, err := VPMAXSQ(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSQ(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSQ(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSQ(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSQ(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSQ(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSQ(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSQ(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSQ(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSQ(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSQ(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSQ(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMAXSQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPMAXSQ_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSQ_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSQ_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSQ_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSQ_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSQ_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMAXSQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPMAXSQ_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSQ_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSQ_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMAXSQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPMAXSQ_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSQ_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSQ_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSQ_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSQ_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSQ_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMAXSWValidFormsNoError(t *testing.T) { + if _, err := VPMAXSW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSW(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSW(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSW(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSW(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSW(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSW(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSW(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSW(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMAXSW_ZValidFormsNoError(t *testing.T) { + if _, err := VPMAXSW_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSW_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSW_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSW_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSW_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXSW_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMAXUBValidFormsNoError(t *testing.T) { + if _, err := VPMAXUB(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUB(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUB(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUB(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUB(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUB(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUB(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUB(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUB(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUB(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUB(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUB(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMAXUB_ZValidFormsNoError(t *testing.T) { + if _, err := VPMAXUB_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUB_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUB_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUB_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUB_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUB_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMAXUDValidFormsNoError(t *testing.T) { + if _, err := VPMAXUD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMAXUD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPMAXUD_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUD_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUD_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUD_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUD_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUD_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMAXUD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPMAXUD_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUD_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUD_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMAXUD_ZValidFormsNoError(t *testing.T) { + if _, err := VPMAXUD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMAXUQValidFormsNoError(t *testing.T) { + if _, err := VPMAXUQ(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUQ(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUQ(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUQ(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUQ(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUQ(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUQ(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUQ(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUQ(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUQ(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUQ(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUQ(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMAXUQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPMAXUQ_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUQ_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUQ_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUQ_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUQ_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUQ_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMAXUQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPMAXUQ_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUQ_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUQ_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMAXUQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPMAXUQ_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUQ_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUQ_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUQ_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUQ_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUQ_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMAXUWValidFormsNoError(t *testing.T) { + if _, err := VPMAXUW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUW(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUW(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUW(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUW(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUW(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUW(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUW(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUW(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMAXUW_ZValidFormsNoError(t *testing.T) { + if _, err := VPMAXUW_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUW_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUW_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUW_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUW_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMAXUW_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMINSBValidFormsNoError(t *testing.T) { + if _, err := VPMINSB(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSB(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSB(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSB(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSB(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSB(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSB(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSB(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSB(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSB(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSB(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSB(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMINSB_ZValidFormsNoError(t *testing.T) { + if _, err := VPMINSB_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSB_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSB_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSB_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSB_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSB_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMINSDValidFormsNoError(t *testing.T) { + if _, err := VPMINSD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMINSD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPMINSD_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSD_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSD_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSD_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSD_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSD_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMINSD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPMINSD_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSD_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSD_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMINSD_ZValidFormsNoError(t *testing.T) { + if _, err := VPMINSD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMINSQValidFormsNoError(t *testing.T) { + if _, err := VPMINSQ(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSQ(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSQ(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSQ(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSQ(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSQ(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSQ(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSQ(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSQ(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSQ(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSQ(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSQ(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMINSQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPMINSQ_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSQ_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSQ_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSQ_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSQ_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSQ_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMINSQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPMINSQ_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSQ_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSQ_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMINSQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPMINSQ_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSQ_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSQ_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSQ_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSQ_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSQ_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMINSWValidFormsNoError(t *testing.T) { + if _, err := VPMINSW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSW(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSW(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSW(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSW(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSW(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSW(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSW(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSW(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMINSW_ZValidFormsNoError(t *testing.T) { + if _, err := VPMINSW_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSW_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSW_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSW_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSW_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINSW_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMINUBValidFormsNoError(t *testing.T) { + if _, err := VPMINUB(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUB(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUB(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUB(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUB(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUB(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUB(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUB(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUB(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUB(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUB(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUB(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMINUB_ZValidFormsNoError(t *testing.T) { + if _, err := VPMINUB_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUB_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUB_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUB_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUB_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUB_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMINUDValidFormsNoError(t *testing.T) { + if _, err := VPMINUD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMINUD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPMINUD_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUD_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUD_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUD_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUD_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUD_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMINUD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPMINUD_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUD_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUD_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMINUD_ZValidFormsNoError(t *testing.T) { + if _, err := VPMINUD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMINUQValidFormsNoError(t *testing.T) { + if _, err := VPMINUQ(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUQ(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUQ(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUQ(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUQ(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUQ(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUQ(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUQ(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUQ(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUQ(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUQ(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUQ(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMINUQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPMINUQ_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUQ_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUQ_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUQ_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUQ_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUQ_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMINUQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPMINUQ_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUQ_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUQ_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMINUQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPMINUQ_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUQ_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUQ_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUQ_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUQ_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUQ_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMINUWValidFormsNoError(t *testing.T) { + if _, err := VPMINUW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUW(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUW(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUW(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUW(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUW(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUW(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUW(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUW(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMINUW_ZValidFormsNoError(t *testing.T) { + if _, err := VPMINUW_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUW_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUW_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUW_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUW_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMINUW_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVB2MValidFormsNoError(t *testing.T) { + if _, err := VPMOVB2M(opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPMOVB2M(opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPMOVB2M(opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVD2MValidFormsNoError(t *testing.T) { + if _, err := VPMOVD2M(opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPMOVD2M(opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPMOVD2M(opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVDBValidFormsNoError(t *testing.T) { + if _, err := VPMOVDB(opxmm, opk, opm32); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDB(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDB(opxmm, opm32); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDB(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDB(opymm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDB(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDB(opymm, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDB(opymm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDB(opzmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDB(opzmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDB(opzmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDB(opzmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVDB_ZValidFormsNoError(t *testing.T) { + if _, err := VPMOVDB_Z(opxmm, opk, opm32); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDB_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDB_Z(opymm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDB_Z(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDB_Z(opzmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDB_Z(opzmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVDWValidFormsNoError(t *testing.T) { + if _, err := VPMOVDW(opxmm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDW(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDW(opxmm, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDW(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDW(opymm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDW(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDW(opymm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDW(opymm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDW(opzmm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDW(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDW(opzmm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDW(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVDW_ZValidFormsNoError(t *testing.T) { + if _, err := VPMOVDW_Z(opxmm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDW_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDW_Z(opymm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDW_Z(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDW_Z(opzmm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPMOVDW_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVM2BValidFormsNoError(t *testing.T) { + if _, err := VPMOVM2B(opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVM2B(opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVM2B(opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVM2DValidFormsNoError(t *testing.T) { + if _, err := VPMOVM2D(opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVM2D(opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVM2D(opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVM2QValidFormsNoError(t *testing.T) { + if _, err := VPMOVM2Q(opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVM2Q(opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVM2Q(opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVM2WValidFormsNoError(t *testing.T) { + if _, err := VPMOVM2W(opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVM2W(opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVM2W(opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVMSKBValidFormsNoError(t *testing.T) { + if _, err := VPMOVMSKB(opymm, opr32); err != nil { + t.Fatal(err) + } + if _, err := VPMOVMSKB(opxmm, opr32); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVQ2MValidFormsNoError(t *testing.T) { + if _, err := VPMOVQ2M(opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQ2M(opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQ2M(opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVQBValidFormsNoError(t *testing.T) { + if _, err := VPMOVQB(opxmm, opk, opm16); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQB(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQB(opxmm, opm16); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQB(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQB(opymm, opk, opm32); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQB(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQB(opymm, opm32); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQB(opymm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQB(opzmm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQB(opzmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQB(opzmm, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQB(opzmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVQB_ZValidFormsNoError(t *testing.T) { + if _, err := VPMOVQB_Z(opxmm, opk, opm16); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQB_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQB_Z(opymm, opk, opm32); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQB_Z(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQB_Z(opzmm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQB_Z(opzmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVQDValidFormsNoError(t *testing.T) { + if _, err := VPMOVQD(opxmm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQD(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQD(opxmm, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQD(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQD(opymm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQD(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQD(opymm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQD(opymm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQD(opzmm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQD(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQD(opzmm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQD(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVQD_ZValidFormsNoError(t *testing.T) { + if _, err := VPMOVQD_Z(opxmm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQD_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQD_Z(opymm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQD_Z(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQD_Z(opzmm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQD_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVQWValidFormsNoError(t *testing.T) { + if _, err := VPMOVQW(opxmm, opk, opm32); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQW(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQW(opxmm, opm32); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQW(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQW(opymm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQW(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQW(opymm, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQW(opymm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQW(opzmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQW(opzmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQW(opzmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQW(opzmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVQW_ZValidFormsNoError(t *testing.T) { + if _, err := VPMOVQW_Z(opxmm, opk, opm32); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQW_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQW_Z(opymm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQW_Z(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQW_Z(opzmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVQW_Z(opzmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVSDBValidFormsNoError(t *testing.T) { + if _, err := VPMOVSDB(opxmm, opk, opm32); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDB(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDB(opxmm, opm32); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDB(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDB(opymm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDB(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDB(opymm, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDB(opymm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDB(opzmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDB(opzmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDB(opzmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDB(opzmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVSDB_ZValidFormsNoError(t *testing.T) { + if _, err := VPMOVSDB_Z(opxmm, opk, opm32); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDB_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDB_Z(opymm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDB_Z(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDB_Z(opzmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDB_Z(opzmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVSDWValidFormsNoError(t *testing.T) { + if _, err := VPMOVSDW(opxmm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDW(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDW(opxmm, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDW(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDW(opymm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDW(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDW(opymm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDW(opymm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDW(opzmm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDW(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDW(opzmm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDW(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVSDW_ZValidFormsNoError(t *testing.T) { + if _, err := VPMOVSDW_Z(opxmm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDW_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDW_Z(opymm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDW_Z(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDW_Z(opzmm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSDW_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVSQBValidFormsNoError(t *testing.T) { + if _, err := VPMOVSQB(opxmm, opk, opm16); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQB(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQB(opxmm, opm16); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQB(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQB(opymm, opk, opm32); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQB(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQB(opymm, opm32); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQB(opymm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQB(opzmm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQB(opzmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQB(opzmm, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQB(opzmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVSQB_ZValidFormsNoError(t *testing.T) { + if _, err := VPMOVSQB_Z(opxmm, opk, opm16); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQB_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQB_Z(opymm, opk, opm32); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQB_Z(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQB_Z(opzmm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQB_Z(opzmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVSQDValidFormsNoError(t *testing.T) { + if _, err := VPMOVSQD(opxmm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQD(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQD(opxmm, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQD(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQD(opymm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQD(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQD(opymm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQD(opymm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQD(opzmm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQD(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQD(opzmm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQD(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVSQD_ZValidFormsNoError(t *testing.T) { + if _, err := VPMOVSQD_Z(opxmm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQD_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQD_Z(opymm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQD_Z(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQD_Z(opzmm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQD_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVSQWValidFormsNoError(t *testing.T) { + if _, err := VPMOVSQW(opxmm, opk, opm32); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQW(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQW(opxmm, opm32); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQW(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQW(opymm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQW(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQW(opymm, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQW(opymm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQW(opzmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQW(opzmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQW(opzmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQW(opzmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVSQW_ZValidFormsNoError(t *testing.T) { + if _, err := VPMOVSQW_Z(opxmm, opk, opm32); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQW_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQW_Z(opymm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQW_Z(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQW_Z(opzmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSQW_Z(opzmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVSWBValidFormsNoError(t *testing.T) { + if _, err := VPMOVSWB(opxmm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSWB(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSWB(opxmm, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSWB(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSWB(opymm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSWB(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSWB(opymm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSWB(opymm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSWB(opzmm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSWB(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSWB(opzmm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSWB(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVSWB_ZValidFormsNoError(t *testing.T) { + if _, err := VPMOVSWB_Z(opxmm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSWB_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSWB_Z(opymm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSWB_Z(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSWB_Z(opzmm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSWB_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVSXBDValidFormsNoError(t *testing.T) { + if _, err := VPMOVSXBD(opm64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBD(opxmm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBD(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBD(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBD(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBD(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBD(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBD(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBD(opm128, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBD(opm128, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBD(opxmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBD(opxmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVSXBD_ZValidFormsNoError(t *testing.T) { + if _, err := VPMOVSXBD_Z(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBD_Z(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBD_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBD_Z(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBD_Z(opm128, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBD_Z(opxmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVSXBQValidFormsNoError(t *testing.T) { + if _, err := VPMOVSXBQ(opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBQ(opxmm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBQ(opm16, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBQ(opm16, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBQ(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBQ(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBQ(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBQ(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBQ(opm64, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBQ(opxmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBQ(opxmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVSXBQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPMOVSXBQ_Z(opm16, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBQ_Z(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBQ_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBQ_Z(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBQ_Z(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBQ_Z(opxmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVSXBWValidFormsNoError(t *testing.T) { + if _, err := VPMOVSXBW(opm128, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBW(opxmm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBW(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBW(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBW(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBW(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBW(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBW(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBW(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBW(opm256, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBW(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBW(opymm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVSXBW_ZValidFormsNoError(t *testing.T) { + if _, err := VPMOVSXBW_Z(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBW_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBW_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBW_Z(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBW_Z(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXBW_Z(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVSXDQValidFormsNoError(t *testing.T) { + if _, err := VPMOVSXDQ(opm128, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXDQ(opxmm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXDQ(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXDQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXDQ(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXDQ(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXDQ(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXDQ(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXDQ(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXDQ(opm256, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXDQ(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXDQ(opymm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVSXDQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPMOVSXDQ_Z(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXDQ_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXDQ_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXDQ_Z(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXDQ_Z(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXDQ_Z(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVSXWDValidFormsNoError(t *testing.T) { + if _, err := VPMOVSXWD(opm128, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWD(opxmm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWD(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWD(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWD(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWD(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWD(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWD(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWD(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWD(opm256, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWD(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWD(opymm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVSXWD_ZValidFormsNoError(t *testing.T) { + if _, err := VPMOVSXWD_Z(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWD_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWD_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWD_Z(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWD_Z(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWD_Z(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVSXWQValidFormsNoError(t *testing.T) { + if _, err := VPMOVSXWQ(opm64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWQ(opxmm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWQ(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWQ(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWQ(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWQ(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWQ(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWQ(opm128, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWQ(opm128, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWQ(opxmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWQ(opxmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVSXWQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPMOVSXWQ_Z(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWQ_Z(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWQ_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWQ_Z(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWQ_Z(opm128, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVSXWQ_Z(opxmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVUSDBValidFormsNoError(t *testing.T) { + if _, err := VPMOVUSDB(opxmm, opk, opm32); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDB(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDB(opxmm, opm32); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDB(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDB(opymm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDB(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDB(opymm, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDB(opymm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDB(opzmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDB(opzmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDB(opzmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDB(opzmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVUSDB_ZValidFormsNoError(t *testing.T) { + if _, err := VPMOVUSDB_Z(opxmm, opk, opm32); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDB_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDB_Z(opymm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDB_Z(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDB_Z(opzmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDB_Z(opzmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVUSDWValidFormsNoError(t *testing.T) { + if _, err := VPMOVUSDW(opxmm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDW(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDW(opxmm, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDW(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDW(opymm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDW(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDW(opymm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDW(opymm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDW(opzmm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDW(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDW(opzmm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDW(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVUSDW_ZValidFormsNoError(t *testing.T) { + if _, err := VPMOVUSDW_Z(opxmm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDW_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDW_Z(opymm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDW_Z(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDW_Z(opzmm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSDW_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVUSQBValidFormsNoError(t *testing.T) { + if _, err := VPMOVUSQB(opxmm, opk, opm16); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQB(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQB(opxmm, opm16); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQB(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQB(opymm, opk, opm32); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQB(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQB(opymm, opm32); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQB(opymm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQB(opzmm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQB(opzmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQB(opzmm, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQB(opzmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVUSQB_ZValidFormsNoError(t *testing.T) { + if _, err := VPMOVUSQB_Z(opxmm, opk, opm16); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQB_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQB_Z(opymm, opk, opm32); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQB_Z(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQB_Z(opzmm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQB_Z(opzmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVUSQDValidFormsNoError(t *testing.T) { + if _, err := VPMOVUSQD(opxmm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQD(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQD(opxmm, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQD(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQD(opymm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQD(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQD(opymm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQD(opymm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQD(opzmm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQD(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQD(opzmm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQD(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVUSQD_ZValidFormsNoError(t *testing.T) { + if _, err := VPMOVUSQD_Z(opxmm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQD_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQD_Z(opymm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQD_Z(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQD_Z(opzmm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQD_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVUSQWValidFormsNoError(t *testing.T) { + if _, err := VPMOVUSQW(opxmm, opk, opm32); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQW(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQW(opxmm, opm32); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQW(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQW(opymm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQW(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQW(opymm, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQW(opymm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQW(opzmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQW(opzmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQW(opzmm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQW(opzmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVUSQW_ZValidFormsNoError(t *testing.T) { + if _, err := VPMOVUSQW_Z(opxmm, opk, opm32); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQW_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQW_Z(opymm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQW_Z(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQW_Z(opzmm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSQW_Z(opzmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVUSWBValidFormsNoError(t *testing.T) { + if _, err := VPMOVUSWB(opxmm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSWB(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSWB(opxmm, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSWB(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSWB(opymm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSWB(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSWB(opymm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSWB(opymm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSWB(opzmm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSWB(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSWB(opzmm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSWB(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVUSWB_ZValidFormsNoError(t *testing.T) { + if _, err := VPMOVUSWB_Z(opxmm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSWB_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSWB_Z(opymm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSWB_Z(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSWB_Z(opzmm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPMOVUSWB_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVW2MValidFormsNoError(t *testing.T) { + if _, err := VPMOVW2M(opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPMOVW2M(opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPMOVW2M(opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVWBValidFormsNoError(t *testing.T) { + if _, err := VPMOVWB(opxmm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVWB(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVWB(opxmm, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVWB(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVWB(opymm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVWB(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVWB(opymm, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVWB(opymm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVWB(opzmm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPMOVWB(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVWB(opzmm, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPMOVWB(opzmm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVWB_ZValidFormsNoError(t *testing.T) { + if _, err := VPMOVWB_Z(opxmm, opk, opm64); err != nil { + t.Fatal(err) + } + if _, err := VPMOVWB_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVWB_Z(opymm, opk, opm128); err != nil { + t.Fatal(err) + } + if _, err := VPMOVWB_Z(opymm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVWB_Z(opzmm, opk, opm256); err != nil { + t.Fatal(err) + } + if _, err := VPMOVWB_Z(opzmm, opk, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVZXBDValidFormsNoError(t *testing.T) { + if _, err := VPMOVZXBD(opm64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBD(opxmm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBD(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBD(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBD(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBD(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBD(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBD(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBD(opm128, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBD(opm128, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBD(opxmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBD(opxmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVZXBD_ZValidFormsNoError(t *testing.T) { + if _, err := VPMOVZXBD_Z(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBD_Z(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBD_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBD_Z(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBD_Z(opm128, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBD_Z(opxmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVZXBQValidFormsNoError(t *testing.T) { + if _, err := VPMOVZXBQ(opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBQ(opxmm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBQ(opm16, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBQ(opm16, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBQ(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBQ(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBQ(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBQ(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBQ(opm64, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBQ(opxmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBQ(opxmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVZXBQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPMOVZXBQ_Z(opm16, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBQ_Z(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBQ_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBQ_Z(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBQ_Z(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBQ_Z(opxmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVZXBWValidFormsNoError(t *testing.T) { + if _, err := VPMOVZXBW(opm128, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBW(opxmm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBW(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBW(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBW(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBW(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBW(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBW(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBW(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBW(opm256, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBW(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBW(opymm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVZXBW_ZValidFormsNoError(t *testing.T) { + if _, err := VPMOVZXBW_Z(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBW_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBW_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBW_Z(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBW_Z(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXBW_Z(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVZXDQValidFormsNoError(t *testing.T) { + if _, err := VPMOVZXDQ(opm128, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXDQ(opxmm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXDQ(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXDQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXDQ(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXDQ(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXDQ(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXDQ(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXDQ(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXDQ(opm256, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXDQ(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXDQ(opymm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVZXDQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPMOVZXDQ_Z(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXDQ_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXDQ_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXDQ_Z(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXDQ_Z(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXDQ_Z(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVZXWDValidFormsNoError(t *testing.T) { + if _, err := VPMOVZXWD(opm128, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWD(opxmm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWD(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWD(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWD(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWD(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWD(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWD(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWD(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWD(opm256, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWD(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWD(opymm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVZXWD_ZValidFormsNoError(t *testing.T) { + if _, err := VPMOVZXWD_Z(opm128, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWD_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWD_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWD_Z(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWD_Z(opm256, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWD_Z(opymm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVZXWQValidFormsNoError(t *testing.T) { + if _, err := VPMOVZXWQ(opm64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWQ(opxmm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWQ(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWQ(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWQ(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWQ(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWQ(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWQ(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWQ(opm128, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWQ(opm128, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWQ(opxmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWQ(opxmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMOVZXWQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPMOVZXWQ_Z(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWQ_Z(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWQ_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWQ_Z(opxmm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWQ_Z(opm128, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMOVZXWQ_Z(opxmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMULDQValidFormsNoError(t *testing.T) { + if _, err := VPMULDQ(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULDQ(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULDQ(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULDQ(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULDQ(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULDQ(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULDQ(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULDQ(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULDQ(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULDQ(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULDQ(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULDQ(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMULDQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPMULDQ_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULDQ_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULDQ_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULDQ_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULDQ_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULDQ_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMULDQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPMULDQ_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULDQ_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULDQ_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMULDQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPMULDQ_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULDQ_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULDQ_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULDQ_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULDQ_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULDQ_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMULHRSWValidFormsNoError(t *testing.T) { + if _, err := VPMULHRSW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHRSW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHRSW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHRSW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHRSW(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHRSW(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHRSW(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHRSW(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHRSW(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHRSW(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHRSW(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHRSW(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMULHRSW_ZValidFormsNoError(t *testing.T) { + if _, err := VPMULHRSW_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHRSW_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHRSW_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHRSW_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHRSW_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHRSW_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMULHUWValidFormsNoError(t *testing.T) { + if _, err := VPMULHUW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHUW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHUW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHUW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHUW(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHUW(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHUW(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHUW(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHUW(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHUW(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHUW(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHUW(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMULHUW_ZValidFormsNoError(t *testing.T) { + if _, err := VPMULHUW_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHUW_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHUW_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHUW_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHUW_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHUW_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMULHWValidFormsNoError(t *testing.T) { + if _, err := VPMULHW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHW(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHW(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHW(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHW(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHW(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHW(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHW(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHW(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMULHW_ZValidFormsNoError(t *testing.T) { + if _, err := VPMULHW_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHW_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHW_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHW_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHW_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULHW_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMULLDValidFormsNoError(t *testing.T) { + if _, err := VPMULLD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMULLD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPMULLD_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLD_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLD_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLD_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLD_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLD_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMULLD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPMULLD_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLD_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLD_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMULLD_ZValidFormsNoError(t *testing.T) { + if _, err := VPMULLD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMULLQValidFormsNoError(t *testing.T) { + if _, err := VPMULLQ(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLQ(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLQ(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLQ(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLQ(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLQ(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLQ(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLQ(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLQ(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLQ(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLQ(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLQ(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMULLQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPMULLQ_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLQ_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLQ_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLQ_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLQ_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLQ_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMULLQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPMULLQ_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLQ_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLQ_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMULLQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPMULLQ_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLQ_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLQ_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLQ_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLQ_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLQ_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMULLWValidFormsNoError(t *testing.T) { + if _, err := VPMULLW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLW(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLW(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLW(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLW(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLW(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLW(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLW(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLW(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMULLW_ZValidFormsNoError(t *testing.T) { + if _, err := VPMULLW_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLW_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLW_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLW_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLW_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULLW_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMULTISHIFTQBValidFormsNoError(t *testing.T) { + if _, err := VPMULTISHIFTQB(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULTISHIFTQB(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULTISHIFTQB(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULTISHIFTQB(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULTISHIFTQB(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULTISHIFTQB(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULTISHIFTQB(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULTISHIFTQB(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULTISHIFTQB(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULTISHIFTQB(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULTISHIFTQB(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULTISHIFTQB(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMULTISHIFTQB_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPMULTISHIFTQB_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULTISHIFTQB_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULTISHIFTQB_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULTISHIFTQB_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULTISHIFTQB_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULTISHIFTQB_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMULTISHIFTQB_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPMULTISHIFTQB_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULTISHIFTQB_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULTISHIFTQB_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMULTISHIFTQB_ZValidFormsNoError(t *testing.T) { + if _, err := VPMULTISHIFTQB_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULTISHIFTQB_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULTISHIFTQB_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULTISHIFTQB_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULTISHIFTQB_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULTISHIFTQB_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMULUDQValidFormsNoError(t *testing.T) { + if _, err := VPMULUDQ(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULUDQ(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULUDQ(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULUDQ(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULUDQ(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULUDQ(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULUDQ(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULUDQ(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULUDQ(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULUDQ(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULUDQ(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULUDQ(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMULUDQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPMULUDQ_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULUDQ_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULUDQ_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULUDQ_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULUDQ_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULUDQ_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMULUDQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPMULUDQ_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULUDQ_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULUDQ_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPMULUDQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPMULUDQ_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULUDQ_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULUDQ_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULUDQ_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPMULUDQ_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPMULUDQ_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPOPCNTDValidFormsNoError(t *testing.T) { + if _, err := VPOPCNTD(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTD(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTD(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTD(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPOPCNTD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPOPCNTD_BCST(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTD_BCST(opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPOPCNTD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPOPCNTD_BCST_Z(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPOPCNTD_ZValidFormsNoError(t *testing.T) { + if _, err := VPOPCNTD_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTD_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPOPCNTQValidFormsNoError(t *testing.T) { + if _, err := VPOPCNTQ(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTQ(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTQ(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTQ(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPOPCNTQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPOPCNTQ_BCST(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTQ_BCST(opm64, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPOPCNTQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPOPCNTQ_BCST_Z(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPOPCNTQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPOPCNTQ_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTQ_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPORValidFormsNoError(t *testing.T) { + if _, err := VPOR(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPOR(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPOR(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPOR(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPORDValidFormsNoError(t *testing.T) { + if _, err := VPORD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPORD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPORD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPORD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPORD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPORD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPORD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPORD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPORD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPORD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPORD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPORD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPORD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPORD_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPORD_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPORD_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPORD_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPORD_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPORD_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPORD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPORD_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPORD_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPORD_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPORD_ZValidFormsNoError(t *testing.T) { + if _, err := VPORD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPORD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPORD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPORD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPORD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPORD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPORQValidFormsNoError(t *testing.T) { + if _, err := VPORQ(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPORQ(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPORQ(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPORQ(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPORQ(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPORQ(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPORQ(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPORQ(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPORQ(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPORQ(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPORQ(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPORQ(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPORQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPORQ_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPORQ_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPORQ_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPORQ_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPORQ_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPORQ_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPORQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPORQ_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPORQ_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPORQ_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPORQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPORQ_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPORQ_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPORQ_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPORQ_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPORQ_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPORQ_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPROLDValidFormsNoError(t *testing.T) { + if _, err := VPROLD(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLD(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLD(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLD(opimm8, opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLD(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLD(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLD(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLD(opimm8, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLD(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLD(opimm8, opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLD(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLD(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPROLD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPROLD_BCST(opimm8, opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLD_BCST(opimm8, opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLD_BCST(opimm8, opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLD_BCST(opimm8, opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLD_BCST(opimm8, opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLD_BCST(opimm8, opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPROLD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPROLD_BCST_Z(opimm8, opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLD_BCST_Z(opimm8, opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLD_BCST_Z(opimm8, opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPROLD_ZValidFormsNoError(t *testing.T) { + if _, err := VPROLD_Z(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLD_Z(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLD_Z(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLD_Z(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLD_Z(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLD_Z(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPROLQValidFormsNoError(t *testing.T) { + if _, err := VPROLQ(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLQ(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLQ(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLQ(opimm8, opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLQ(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLQ(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLQ(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLQ(opimm8, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLQ(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLQ(opimm8, opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLQ(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLQ(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPROLQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPROLQ_BCST(opimm8, opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLQ_BCST(opimm8, opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLQ_BCST(opimm8, opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLQ_BCST(opimm8, opm64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLQ_BCST(opimm8, opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLQ_BCST(opimm8, opm64, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPROLQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPROLQ_BCST_Z(opimm8, opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLQ_BCST_Z(opimm8, opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLQ_BCST_Z(opimm8, opm64, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPROLQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPROLQ_Z(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLQ_Z(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLQ_Z(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLQ_Z(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLQ_Z(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLQ_Z(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPROLVDValidFormsNoError(t *testing.T) { + if _, err := VPROLVD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPROLVD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPROLVD_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVD_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVD_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVD_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVD_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVD_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPROLVD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPROLVD_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVD_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVD_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPROLVD_ZValidFormsNoError(t *testing.T) { + if _, err := VPROLVD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPROLVQValidFormsNoError(t *testing.T) { + if _, err := VPROLVQ(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVQ(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVQ(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVQ(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVQ(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVQ(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVQ(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVQ(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVQ(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVQ(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVQ(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVQ(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPROLVQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPROLVQ_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVQ_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVQ_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVQ_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVQ_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVQ_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPROLVQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPROLVQ_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVQ_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVQ_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPROLVQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPROLVQ_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVQ_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVQ_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVQ_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVQ_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPROLVQ_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPRORDValidFormsNoError(t *testing.T) { + if _, err := VPRORD(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORD(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORD(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORD(opimm8, opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORD(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORD(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORD(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORD(opimm8, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORD(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORD(opimm8, opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORD(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORD(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPRORD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPRORD_BCST(opimm8, opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORD_BCST(opimm8, opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORD_BCST(opimm8, opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORD_BCST(opimm8, opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORD_BCST(opimm8, opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORD_BCST(opimm8, opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPRORD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPRORD_BCST_Z(opimm8, opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORD_BCST_Z(opimm8, opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORD_BCST_Z(opimm8, opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPRORD_ZValidFormsNoError(t *testing.T) { + if _, err := VPRORD_Z(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORD_Z(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORD_Z(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORD_Z(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORD_Z(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORD_Z(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPRORQValidFormsNoError(t *testing.T) { + if _, err := VPRORQ(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORQ(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORQ(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORQ(opimm8, opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORQ(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORQ(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORQ(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORQ(opimm8, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORQ(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORQ(opimm8, opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORQ(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORQ(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPRORQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPRORQ_BCST(opimm8, opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORQ_BCST(opimm8, opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORQ_BCST(opimm8, opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORQ_BCST(opimm8, opm64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORQ_BCST(opimm8, opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORQ_BCST(opimm8, opm64, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPRORQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPRORQ_BCST_Z(opimm8, opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORQ_BCST_Z(opimm8, opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORQ_BCST_Z(opimm8, opm64, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPRORQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPRORQ_Z(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORQ_Z(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORQ_Z(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORQ_Z(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORQ_Z(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORQ_Z(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPRORVDValidFormsNoError(t *testing.T) { + if _, err := VPRORVD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPRORVD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPRORVD_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVD_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVD_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVD_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVD_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVD_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPRORVD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPRORVD_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVD_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVD_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPRORVD_ZValidFormsNoError(t *testing.T) { + if _, err := VPRORVD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPRORVQValidFormsNoError(t *testing.T) { + if _, err := VPRORVQ(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVQ(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVQ(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVQ(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVQ(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVQ(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVQ(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVQ(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVQ(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVQ(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVQ(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVQ(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPRORVQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPRORVQ_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVQ_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVQ_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVQ_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVQ_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVQ_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPRORVQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPRORVQ_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVQ_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVQ_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPRORVQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPRORVQ_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVQ_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVQ_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVQ_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVQ_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPRORVQ_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSADBWValidFormsNoError(t *testing.T) { + if _, err := VPSADBW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSADBW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSADBW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSADBW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSADBW(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSADBW(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSCATTERDDValidFormsNoError(t *testing.T) { + if _, err := VPSCATTERDD(opxmm, opk, opvm32x); err != nil { + t.Fatal(err) + } + if _, err := VPSCATTERDD(opymm, opk, opvm32y); err != nil { + t.Fatal(err) + } + if _, err := VPSCATTERDD(opzmm, opk, opvm32z); err != nil { + t.Fatal(err) + } +} + +func TestVPSCATTERDQValidFormsNoError(t *testing.T) { + if _, err := VPSCATTERDQ(opxmm, opk, opvm32x); err != nil { + t.Fatal(err) + } + if _, err := VPSCATTERDQ(opymm, opk, opvm32x); err != nil { + t.Fatal(err) + } + if _, err := VPSCATTERDQ(opzmm, opk, opvm32y); err != nil { + t.Fatal(err) + } +} + +func TestVPSCATTERQDValidFormsNoError(t *testing.T) { + if _, err := VPSCATTERQD(opxmm, opk, opvm64x); err != nil { + t.Fatal(err) + } + if _, err := VPSCATTERQD(opxmm, opk, opvm64y); err != nil { + t.Fatal(err) + } + if _, err := VPSCATTERQD(opymm, opk, opvm64z); err != nil { + t.Fatal(err) + } +} + +func TestVPSCATTERQQValidFormsNoError(t *testing.T) { + if _, err := VPSCATTERQQ(opxmm, opk, opvm64x); err != nil { + t.Fatal(err) + } + if _, err := VPSCATTERQQ(opymm, opk, opvm64y); err != nil { + t.Fatal(err) + } + if _, err := VPSCATTERQQ(opzmm, opk, opvm64z); err != nil { + t.Fatal(err) + } +} + +func TestVPSHUFBValidFormsNoError(t *testing.T) { + if _, err := VPSHUFB(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFB(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFB(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFB(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFB(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFB(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFB(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFB(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFB(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFB(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFB(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFB(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSHUFB_ZValidFormsNoError(t *testing.T) { + if _, err := VPSHUFB_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFB_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFB_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFB_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFB_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFB_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSHUFDValidFormsNoError(t *testing.T) { + if _, err := VPSHUFD(opimm8, opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFD(opimm8, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFD(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFD(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFD(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFD(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFD(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFD(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFD(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFD(opimm8, opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFD(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFD(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSHUFD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPSHUFD_BCST(opimm8, opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFD_BCST(opimm8, opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFD_BCST(opimm8, opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFD_BCST(opimm8, opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFD_BCST(opimm8, opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFD_BCST(opimm8, opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSHUFD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPSHUFD_BCST_Z(opimm8, opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFD_BCST_Z(opimm8, opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFD_BCST_Z(opimm8, opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSHUFD_ZValidFormsNoError(t *testing.T) { + if _, err := VPSHUFD_Z(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFD_Z(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFD_Z(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFD_Z(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFD_Z(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFD_Z(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSHUFHWValidFormsNoError(t *testing.T) { + if _, err := VPSHUFHW(opimm8, opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFHW(opimm8, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFHW(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFHW(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFHW(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFHW(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFHW(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFHW(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFHW(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFHW(opimm8, opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFHW(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFHW(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSHUFHW_ZValidFormsNoError(t *testing.T) { + if _, err := VPSHUFHW_Z(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFHW_Z(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFHW_Z(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFHW_Z(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFHW_Z(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFHW_Z(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSHUFLWValidFormsNoError(t *testing.T) { + if _, err := VPSHUFLW(opimm8, opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFLW(opimm8, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFLW(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFLW(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFLW(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFLW(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFLW(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFLW(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFLW(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFLW(opimm8, opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFLW(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFLW(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSHUFLW_ZValidFormsNoError(t *testing.T) { + if _, err := VPSHUFLW_Z(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFLW_Z(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFLW_Z(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFLW_Z(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFLW_Z(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFLW_Z(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSIGNBValidFormsNoError(t *testing.T) { + if _, err := VPSIGNB(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSIGNB(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSIGNB(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSIGNB(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSIGNDValidFormsNoError(t *testing.T) { + if _, err := VPSIGND(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSIGND(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSIGND(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSIGND(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSIGNWValidFormsNoError(t *testing.T) { + if _, err := VPSIGNW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSIGNW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSIGNW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSIGNW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSLLDValidFormsNoError(t *testing.T) { + if _, err := VPSLLD(opimm8, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD(opm128, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD(opxmm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD(opimm8, opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD(opm128, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD(opxmm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD(opimm8, opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD(opm128, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD(opm128, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD(opxmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD(opxmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSLLDQValidFormsNoError(t *testing.T) { + if _, err := VPSLLDQ(opimm8, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLDQ(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLDQ(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLDQ(opimm8, opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLDQ(opimm8, opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLDQ(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSLLD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPSLLD_BCST(opimm8, opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD_BCST(opimm8, opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD_BCST(opimm8, opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD_BCST(opimm8, opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD_BCST(opimm8, opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD_BCST(opimm8, opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSLLD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPSLLD_BCST_Z(opimm8, opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD_BCST_Z(opimm8, opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD_BCST_Z(opimm8, opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSLLD_ZValidFormsNoError(t *testing.T) { + if _, err := VPSLLD_Z(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD_Z(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD_Z(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD_Z(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD_Z(opm128, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD_Z(opxmm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD_Z(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD_Z(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD_Z(opm128, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLD_Z(opxmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSLLQValidFormsNoError(t *testing.T) { + if _, err := VPSLLQ(opimm8, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ(opm128, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ(opxmm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ(opimm8, opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ(opm128, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ(opxmm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ(opimm8, opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ(opm128, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ(opm128, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ(opxmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ(opxmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSLLQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPSLLQ_BCST(opimm8, opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ_BCST(opimm8, opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ_BCST(opimm8, opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ_BCST(opimm8, opm64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ_BCST(opimm8, opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ_BCST(opimm8, opm64, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSLLQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPSLLQ_BCST_Z(opimm8, opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ_BCST_Z(opimm8, opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ_BCST_Z(opimm8, opm64, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSLLQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPSLLQ_Z(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ_Z(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ_Z(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ_Z(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ_Z(opm128, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ_Z(opxmm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ_Z(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ_Z(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ_Z(opm128, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLQ_Z(opxmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSLLVDValidFormsNoError(t *testing.T) { + if _, err := VPSLLVD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSLLVD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPSLLVD_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVD_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVD_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVD_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVD_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVD_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSLLVD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPSLLVD_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVD_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVD_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSLLVD_ZValidFormsNoError(t *testing.T) { + if _, err := VPSLLVD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSLLVQValidFormsNoError(t *testing.T) { + if _, err := VPSLLVQ(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVQ(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVQ(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVQ(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVQ(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVQ(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVQ(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVQ(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVQ(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVQ(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVQ(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVQ(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSLLVQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPSLLVQ_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVQ_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVQ_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVQ_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVQ_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVQ_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSLLVQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPSLLVQ_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVQ_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVQ_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSLLVQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPSLLVQ_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVQ_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVQ_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVQ_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVQ_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVQ_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSLLVWValidFormsNoError(t *testing.T) { + if _, err := VPSLLVW(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVW(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVW(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVW(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVW(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVW(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVW(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVW(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSLLVW_ZValidFormsNoError(t *testing.T) { + if _, err := VPSLLVW_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVW_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVW_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVW_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVW_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLVW_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSLLWValidFormsNoError(t *testing.T) { + if _, err := VPSLLW(opimm8, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW(opm128, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW(opxmm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW(opimm8, opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW(opm128, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW(opxmm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW(opimm8, opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW(opm128, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW(opm128, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW(opxmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW(opxmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSLLW_ZValidFormsNoError(t *testing.T) { + if _, err := VPSLLW_Z(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW_Z(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW_Z(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW_Z(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW_Z(opm128, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW_Z(opxmm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW_Z(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW_Z(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW_Z(opm128, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSLLW_Z(opxmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRADValidFormsNoError(t *testing.T) { + if _, err := VPSRAD(opimm8, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD(opm128, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD(opxmm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD(opimm8, opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD(opm128, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD(opxmm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD(opimm8, opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD(opm128, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD(opm128, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD(opxmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD(opxmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRAD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPSRAD_BCST(opimm8, opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD_BCST(opimm8, opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD_BCST(opimm8, opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD_BCST(opimm8, opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD_BCST(opimm8, opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD_BCST(opimm8, opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRAD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPSRAD_BCST_Z(opimm8, opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD_BCST_Z(opimm8, opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD_BCST_Z(opimm8, opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRAD_ZValidFormsNoError(t *testing.T) { + if _, err := VPSRAD_Z(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD_Z(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD_Z(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD_Z(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD_Z(opm128, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD_Z(opxmm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD_Z(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD_Z(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD_Z(opm128, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAD_Z(opxmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRAQValidFormsNoError(t *testing.T) { + if _, err := VPSRAQ(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ(opimm8, opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ(opimm8, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ(opm128, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ(opm128, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ(opxmm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ(opxmm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ(opimm8, opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ(opm128, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ(opm128, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ(opxmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ(opxmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRAQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPSRAQ_BCST(opimm8, opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ_BCST(opimm8, opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ_BCST(opimm8, opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ_BCST(opimm8, opm64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ_BCST(opimm8, opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ_BCST(opimm8, opm64, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRAQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPSRAQ_BCST_Z(opimm8, opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ_BCST_Z(opimm8, opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ_BCST_Z(opimm8, opm64, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRAQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPSRAQ_Z(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ_Z(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ_Z(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ_Z(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ_Z(opm128, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ_Z(opxmm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ_Z(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ_Z(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ_Z(opm128, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAQ_Z(opxmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRAVDValidFormsNoError(t *testing.T) { + if _, err := VPSRAVD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRAVD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPSRAVD_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVD_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVD_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVD_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVD_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVD_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRAVD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPSRAVD_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVD_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVD_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRAVD_ZValidFormsNoError(t *testing.T) { + if _, err := VPSRAVD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRAVQValidFormsNoError(t *testing.T) { + if _, err := VPSRAVQ(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVQ(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVQ(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVQ(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVQ(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVQ(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVQ(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVQ(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVQ(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVQ(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVQ(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVQ(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRAVQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPSRAVQ_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVQ_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVQ_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVQ_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVQ_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVQ_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRAVQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPSRAVQ_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVQ_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVQ_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRAVQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPSRAVQ_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVQ_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVQ_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVQ_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVQ_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVQ_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRAVWValidFormsNoError(t *testing.T) { + if _, err := VPSRAVW(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVW(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVW(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVW(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVW(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVW(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVW(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVW(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRAVW_ZValidFormsNoError(t *testing.T) { + if _, err := VPSRAVW_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVW_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVW_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVW_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVW_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAVW_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRAWValidFormsNoError(t *testing.T) { + if _, err := VPSRAW(opimm8, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW(opm128, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW(opxmm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW(opimm8, opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW(opm128, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW(opxmm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW(opimm8, opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW(opm128, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW(opm128, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW(opxmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW(opxmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRAW_ZValidFormsNoError(t *testing.T) { + if _, err := VPSRAW_Z(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW_Z(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW_Z(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW_Z(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW_Z(opm128, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW_Z(opxmm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW_Z(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW_Z(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW_Z(opm128, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRAW_Z(opxmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRLDValidFormsNoError(t *testing.T) { + if _, err := VPSRLD(opimm8, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD(opm128, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD(opxmm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD(opimm8, opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD(opm128, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD(opxmm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD(opimm8, opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD(opm128, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD(opm128, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD(opxmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD(opxmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRLDQValidFormsNoError(t *testing.T) { + if _, err := VPSRLDQ(opimm8, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLDQ(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLDQ(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLDQ(opimm8, opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLDQ(opimm8, opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLDQ(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRLD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPSRLD_BCST(opimm8, opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD_BCST(opimm8, opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD_BCST(opimm8, opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD_BCST(opimm8, opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD_BCST(opimm8, opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD_BCST(opimm8, opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRLD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPSRLD_BCST_Z(opimm8, opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD_BCST_Z(opimm8, opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD_BCST_Z(opimm8, opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRLD_ZValidFormsNoError(t *testing.T) { + if _, err := VPSRLD_Z(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD_Z(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD_Z(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD_Z(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD_Z(opm128, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD_Z(opxmm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD_Z(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD_Z(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD_Z(opm128, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLD_Z(opxmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRLQValidFormsNoError(t *testing.T) { + if _, err := VPSRLQ(opimm8, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ(opm128, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ(opxmm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ(opimm8, opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ(opm128, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ(opxmm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ(opimm8, opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ(opm128, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ(opm128, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ(opxmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ(opxmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRLQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPSRLQ_BCST(opimm8, opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ_BCST(opimm8, opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ_BCST(opimm8, opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ_BCST(opimm8, opm64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ_BCST(opimm8, opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ_BCST(opimm8, opm64, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRLQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPSRLQ_BCST_Z(opimm8, opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ_BCST_Z(opimm8, opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ_BCST_Z(opimm8, opm64, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRLQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPSRLQ_Z(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ_Z(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ_Z(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ_Z(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ_Z(opm128, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ_Z(opxmm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ_Z(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ_Z(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ_Z(opm128, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLQ_Z(opxmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRLVDValidFormsNoError(t *testing.T) { + if _, err := VPSRLVD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRLVD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPSRLVD_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVD_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVD_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVD_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVD_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVD_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRLVD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPSRLVD_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVD_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVD_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRLVD_ZValidFormsNoError(t *testing.T) { + if _, err := VPSRLVD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRLVQValidFormsNoError(t *testing.T) { + if _, err := VPSRLVQ(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVQ(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVQ(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVQ(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVQ(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVQ(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVQ(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVQ(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVQ(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVQ(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVQ(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVQ(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRLVQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPSRLVQ_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVQ_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVQ_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVQ_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVQ_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVQ_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRLVQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPSRLVQ_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVQ_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVQ_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRLVQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPSRLVQ_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVQ_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVQ_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVQ_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVQ_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVQ_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRLVWValidFormsNoError(t *testing.T) { + if _, err := VPSRLVW(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVW(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVW(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVW(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVW(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVW(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVW(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVW(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRLVW_ZValidFormsNoError(t *testing.T) { + if _, err := VPSRLVW_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVW_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVW_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVW_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVW_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLVW_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRLWValidFormsNoError(t *testing.T) { + if _, err := VPSRLW(opimm8, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW(opm128, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW(opxmm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW(opimm8, opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW(opm128, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW(opxmm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW(opimm8, opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW(opm128, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW(opm128, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW(opxmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW(opxmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSRLW_ZValidFormsNoError(t *testing.T) { + if _, err := VPSRLW_Z(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW_Z(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW_Z(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW_Z(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW_Z(opm128, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW_Z(opxmm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW_Z(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW_Z(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW_Z(opm128, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSRLW_Z(opxmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSUBBValidFormsNoError(t *testing.T) { + if _, err := VPSUBB(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBB(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBB(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBB(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBB(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBB(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBB(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBB(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBB(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBB(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBB(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBB(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSUBB_ZValidFormsNoError(t *testing.T) { + if _, err := VPSUBB_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBB_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBB_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBB_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBB_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBB_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSUBDValidFormsNoError(t *testing.T) { + if _, err := VPSUBD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSUBD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPSUBD_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBD_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBD_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBD_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBD_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBD_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSUBD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPSUBD_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBD_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBD_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSUBD_ZValidFormsNoError(t *testing.T) { + if _, err := VPSUBD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSUBQValidFormsNoError(t *testing.T) { + if _, err := VPSUBQ(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBQ(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBQ(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBQ(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBQ(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBQ(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBQ(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBQ(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBQ(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBQ(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBQ(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBQ(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSUBQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPSUBQ_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBQ_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBQ_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBQ_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBQ_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBQ_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSUBQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPSUBQ_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBQ_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBQ_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSUBQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPSUBQ_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBQ_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBQ_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBQ_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBQ_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBQ_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSUBSBValidFormsNoError(t *testing.T) { + if _, err := VPSUBSB(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSB(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSB(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSB(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSB(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSB(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSB(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSB(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSB(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSB(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSB(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSB(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSUBSB_ZValidFormsNoError(t *testing.T) { + if _, err := VPSUBSB_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSB_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSB_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSB_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSB_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSB_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSUBSWValidFormsNoError(t *testing.T) { + if _, err := VPSUBSW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSW(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSW(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSW(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSW(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSW(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSW(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSW(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSW(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSUBSW_ZValidFormsNoError(t *testing.T) { + if _, err := VPSUBSW_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSW_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSW_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSW_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSW_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBSW_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSUBUSBValidFormsNoError(t *testing.T) { + if _, err := VPSUBUSB(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSB(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSB(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSB(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSB(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSB(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSB(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSB(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSB(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSB(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSB(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSB(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSUBUSB_ZValidFormsNoError(t *testing.T) { + if _, err := VPSUBUSB_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSB_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSB_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSB_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSB_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSB_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSUBUSWValidFormsNoError(t *testing.T) { + if _, err := VPSUBUSW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSW(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSW(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSW(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSW(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSW(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSW(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSW(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSW(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSUBUSW_ZValidFormsNoError(t *testing.T) { + if _, err := VPSUBUSW_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSW_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSW_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSW_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSW_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBUSW_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSUBWValidFormsNoError(t *testing.T) { + if _, err := VPSUBW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBW(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBW(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBW(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBW(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBW(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBW(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBW(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBW(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPSUBW_ZValidFormsNoError(t *testing.T) { + if _, err := VPSUBW_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBW_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBW_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBW_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBW_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPSUBW_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPTERNLOGDValidFormsNoError(t *testing.T) { + if _, err := VPTERNLOGD(opimm8, opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGD(opimm8, opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGD(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGD(opimm8, opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGD(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGD(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGD(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGD(opimm8, opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGD(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGD(opimm8, opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGD(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGD(opimm8, opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPTERNLOGD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPTERNLOGD_BCST(opimm8, opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGD_BCST(opimm8, opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGD_BCST(opimm8, opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGD_BCST(opimm8, opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGD_BCST(opimm8, opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGD_BCST(opimm8, opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPTERNLOGD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPTERNLOGD_BCST_Z(opimm8, opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGD_BCST_Z(opimm8, opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGD_BCST_Z(opimm8, opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPTERNLOGD_ZValidFormsNoError(t *testing.T) { + if _, err := VPTERNLOGD_Z(opimm8, opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGD_Z(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGD_Z(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGD_Z(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGD_Z(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGD_Z(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPTERNLOGQValidFormsNoError(t *testing.T) { + if _, err := VPTERNLOGQ(opimm8, opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGQ(opimm8, opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGQ(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGQ(opimm8, opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGQ(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGQ(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGQ(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGQ(opimm8, opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGQ(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGQ(opimm8, opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGQ(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGQ(opimm8, opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPTERNLOGQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPTERNLOGQ_BCST(opimm8, opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGQ_BCST(opimm8, opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGQ_BCST(opimm8, opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGQ_BCST(opimm8, opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGQ_BCST(opimm8, opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGQ_BCST(opimm8, opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPTERNLOGQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPTERNLOGQ_BCST_Z(opimm8, opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGQ_BCST_Z(opimm8, opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGQ_BCST_Z(opimm8, opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPTERNLOGQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPTERNLOGQ_Z(opimm8, opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGQ_Z(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGQ_Z(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGQ_Z(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGQ_Z(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPTERNLOGQ_Z(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPTESTValidFormsNoError(t *testing.T) { + if _, err := VPTEST(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPTEST(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPTEST(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPTEST(opymm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVPTESTMBValidFormsNoError(t *testing.T) { + if _, err := VPTESTMB(opm128, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMB(opm128, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMB(opm256, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMB(opm256, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMB(opxmm, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMB(opxmm, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMB(opymm, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMB(opymm, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMB(opm512, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMB(opm512, opzmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMB(opzmm, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMB(opzmm, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPTESTMDValidFormsNoError(t *testing.T) { + if _, err := VPTESTMD(opm128, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMD(opm128, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMD(opm256, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMD(opm256, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMD(opxmm, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMD(opxmm, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMD(opymm, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMD(opymm, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMD(opm512, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMD(opm512, opzmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMD(opzmm, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMD(opzmm, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPTESTMD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPTESTMD_BCST(opm32, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMD_BCST(opm32, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMD_BCST(opm32, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMD_BCST(opm32, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMD_BCST(opm32, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMD_BCST(opm32, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPTESTMQValidFormsNoError(t *testing.T) { + if _, err := VPTESTMQ(opm128, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMQ(opm128, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMQ(opm256, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMQ(opm256, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMQ(opxmm, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMQ(opxmm, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMQ(opymm, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMQ(opymm, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMQ(opm512, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMQ(opm512, opzmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMQ(opzmm, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMQ(opzmm, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPTESTMQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPTESTMQ_BCST(opm64, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMQ_BCST(opm64, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMQ_BCST(opm64, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMQ_BCST(opm64, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMQ_BCST(opm64, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMQ_BCST(opm64, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPTESTMWValidFormsNoError(t *testing.T) { + if _, err := VPTESTMW(opm128, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMW(opm128, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMW(opm256, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMW(opm256, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMW(opxmm, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMW(opxmm, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMW(opymm, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMW(opymm, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMW(opm512, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMW(opm512, opzmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMW(opzmm, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTMW(opzmm, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPTESTNMBValidFormsNoError(t *testing.T) { + if _, err := VPTESTNMB(opm512, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMB(opm512, opzmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMB(opzmm, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMB(opzmm, opzmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMB(opm128, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMB(opm128, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMB(opm256, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMB(opm256, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMB(opxmm, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMB(opxmm, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMB(opymm, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMB(opymm, opymm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPTESTNMDValidFormsNoError(t *testing.T) { + if _, err := VPTESTNMD(opm128, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMD(opm128, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMD(opm256, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMD(opm256, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMD(opxmm, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMD(opxmm, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMD(opymm, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMD(opymm, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMD(opm512, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMD(opm512, opzmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMD(opzmm, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMD(opzmm, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPTESTNMD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPTESTNMD_BCST(opm32, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMD_BCST(opm32, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMD_BCST(opm32, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMD_BCST(opm32, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMD_BCST(opm32, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMD_BCST(opm32, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPTESTNMQValidFormsNoError(t *testing.T) { + if _, err := VPTESTNMQ(opm128, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMQ(opm128, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMQ(opm256, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMQ(opm256, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMQ(opxmm, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMQ(opxmm, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMQ(opymm, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMQ(opymm, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMQ(opm512, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMQ(opm512, opzmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMQ(opzmm, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMQ(opzmm, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPTESTNMQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPTESTNMQ_BCST(opm64, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMQ_BCST(opm64, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMQ_BCST(opm64, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMQ_BCST(opm64, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMQ_BCST(opm64, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMQ_BCST(opm64, opzmm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPTESTNMWValidFormsNoError(t *testing.T) { + if _, err := VPTESTNMW(opm512, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMW(opm512, opzmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMW(opzmm, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMW(opzmm, opzmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMW(opm128, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMW(opm128, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMW(opm256, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMW(opm256, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMW(opxmm, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMW(opxmm, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMW(opymm, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPTESTNMW(opymm, opymm, opk); err != nil { + t.Fatal(err) + } +} + +func TestVPUNPCKHBWValidFormsNoError(t *testing.T) { + if _, err := VPUNPCKHBW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHBW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHBW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHBW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHBW(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHBW(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHBW(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHBW(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHBW(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHBW(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHBW(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHBW(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPUNPCKHBW_ZValidFormsNoError(t *testing.T) { + if _, err := VPUNPCKHBW_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHBW_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHBW_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHBW_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHBW_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHBW_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPUNPCKHDQValidFormsNoError(t *testing.T) { + if _, err := VPUNPCKHDQ(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHDQ(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHDQ(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHDQ(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHDQ(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHDQ(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHDQ(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHDQ(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHDQ(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHDQ(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHDQ(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHDQ(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPUNPCKHDQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPUNPCKHDQ_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHDQ_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHDQ_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHDQ_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHDQ_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHDQ_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPUNPCKHDQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPUNPCKHDQ_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHDQ_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHDQ_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPUNPCKHDQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPUNPCKHDQ_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHDQ_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHDQ_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHDQ_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHDQ_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHDQ_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPUNPCKHQDQValidFormsNoError(t *testing.T) { + if _, err := VPUNPCKHQDQ(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHQDQ(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHQDQ(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHQDQ(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHQDQ(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHQDQ(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHQDQ(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHQDQ(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHQDQ(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHQDQ(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHQDQ(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHQDQ(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPUNPCKHQDQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPUNPCKHQDQ_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHQDQ_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHQDQ_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHQDQ_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHQDQ_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHQDQ_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPUNPCKHQDQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPUNPCKHQDQ_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHQDQ_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHQDQ_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPUNPCKHQDQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPUNPCKHQDQ_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHQDQ_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHQDQ_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHQDQ_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHQDQ_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHQDQ_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPUNPCKHWDValidFormsNoError(t *testing.T) { + if _, err := VPUNPCKHWD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHWD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHWD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHWD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHWD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHWD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHWD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHWD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHWD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHWD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHWD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHWD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPUNPCKHWD_ZValidFormsNoError(t *testing.T) { + if _, err := VPUNPCKHWD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHWD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHWD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHWD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHWD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKHWD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPUNPCKLBWValidFormsNoError(t *testing.T) { + if _, err := VPUNPCKLBW(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLBW(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLBW(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLBW(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLBW(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLBW(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLBW(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLBW(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLBW(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLBW(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLBW(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLBW(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPUNPCKLBW_ZValidFormsNoError(t *testing.T) { + if _, err := VPUNPCKLBW_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLBW_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLBW_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLBW_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLBW_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLBW_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPUNPCKLDQValidFormsNoError(t *testing.T) { + if _, err := VPUNPCKLDQ(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLDQ(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLDQ(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLDQ(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLDQ(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLDQ(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLDQ(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLDQ(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLDQ(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLDQ(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLDQ(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLDQ(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPUNPCKLDQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPUNPCKLDQ_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLDQ_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLDQ_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLDQ_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLDQ_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLDQ_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPUNPCKLDQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPUNPCKLDQ_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLDQ_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLDQ_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPUNPCKLDQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPUNPCKLDQ_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLDQ_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLDQ_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLDQ_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLDQ_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLDQ_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPUNPCKLQDQValidFormsNoError(t *testing.T) { + if _, err := VPUNPCKLQDQ(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLQDQ(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLQDQ(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLQDQ(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLQDQ(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLQDQ(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLQDQ(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLQDQ(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLQDQ(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLQDQ(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLQDQ(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLQDQ(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPUNPCKLQDQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPUNPCKLQDQ_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLQDQ_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLQDQ_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLQDQ_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLQDQ_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLQDQ_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPUNPCKLQDQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPUNPCKLQDQ_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLQDQ_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLQDQ_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPUNPCKLQDQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPUNPCKLQDQ_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLQDQ_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLQDQ_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLQDQ_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLQDQ_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLQDQ_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPUNPCKLWDValidFormsNoError(t *testing.T) { + if _, err := VPUNPCKLWD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLWD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLWD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLWD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLWD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLWD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLWD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLWD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLWD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLWD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLWD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLWD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPUNPCKLWD_ZValidFormsNoError(t *testing.T) { + if _, err := VPUNPCKLWD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLWD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLWD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLWD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLWD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPUNPCKLWD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPXORValidFormsNoError(t *testing.T) { + if _, err := VPXOR(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPXOR(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPXOR(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPXOR(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVPXORDValidFormsNoError(t *testing.T) { + if _, err := VPXORD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPXORD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPXORD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPXORD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPXORD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPXORD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPXORD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPXORD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPXORD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPXORD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPXORD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPXORD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPXORD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPXORD_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPXORD_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPXORD_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPXORD_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPXORD_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPXORD_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPXORD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPXORD_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPXORD_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPXORD_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPXORD_ZValidFormsNoError(t *testing.T) { + if _, err := VPXORD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPXORD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPXORD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPXORD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPXORD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPXORD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPXORQValidFormsNoError(t *testing.T) { + if _, err := VPXORQ(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPXORQ(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPXORQ(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPXORQ(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPXORQ(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPXORQ(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPXORQ(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPXORQ(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPXORQ(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPXORQ(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPXORQ(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPXORQ(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPXORQ_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPXORQ_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPXORQ_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPXORQ_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPXORQ_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPXORQ_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPXORQ_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPXORQ_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPXORQ_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPXORQ_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPXORQ_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPXORQ_ZValidFormsNoError(t *testing.T) { + if _, err := VPXORQ_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPXORQ_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPXORQ_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPXORQ_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPXORQ_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPXORQ_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRANGEPDValidFormsNoError(t *testing.T) { + if _, err := VRANGEPD(opimm8, opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPD(opimm8, opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPD(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPD(opimm8, opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPD(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPD(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPD(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPD(opimm8, opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPD(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPD(opimm8, opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPD(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPD(opimm8, opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRANGEPD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VRANGEPD_BCST(opimm8, opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPD_BCST(opimm8, opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPD_BCST(opimm8, opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPD_BCST(opimm8, opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPD_BCST(opimm8, opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPD_BCST(opimm8, opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRANGEPD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VRANGEPD_BCST_Z(opimm8, opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPD_BCST_Z(opimm8, opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPD_BCST_Z(opimm8, opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRANGEPD_SAEValidFormsNoError(t *testing.T) { + if _, err := VRANGEPD_SAE(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPD_SAE(opimm8, opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRANGEPD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VRANGEPD_SAE_Z(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRANGEPD_ZValidFormsNoError(t *testing.T) { + if _, err := VRANGEPD_Z(opimm8, opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPD_Z(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPD_Z(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPD_Z(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPD_Z(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPD_Z(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRANGEPSValidFormsNoError(t *testing.T) { + if _, err := VRANGEPS(opimm8, opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPS(opimm8, opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPS(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPS(opimm8, opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPS(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPS(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPS(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPS(opimm8, opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPS(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPS(opimm8, opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPS(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPS(opimm8, opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRANGEPS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VRANGEPS_BCST(opimm8, opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPS_BCST(opimm8, opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPS_BCST(opimm8, opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPS_BCST(opimm8, opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPS_BCST(opimm8, opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPS_BCST(opimm8, opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRANGEPS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VRANGEPS_BCST_Z(opimm8, opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPS_BCST_Z(opimm8, opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPS_BCST_Z(opimm8, opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRANGEPS_SAEValidFormsNoError(t *testing.T) { + if _, err := VRANGEPS_SAE(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPS_SAE(opimm8, opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRANGEPS_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VRANGEPS_SAE_Z(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRANGEPS_ZValidFormsNoError(t *testing.T) { + if _, err := VRANGEPS_Z(opimm8, opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPS_Z(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPS_Z(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPS_Z(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPS_Z(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGEPS_Z(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRANGESDValidFormsNoError(t *testing.T) { + if _, err := VRANGESD(opimm8, opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGESD(opimm8, opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGESD(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGESD(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRANGESD_SAEValidFormsNoError(t *testing.T) { + if _, err := VRANGESD_SAE(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGESD_SAE(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRANGESD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VRANGESD_SAE_Z(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRANGESD_ZValidFormsNoError(t *testing.T) { + if _, err := VRANGESD_Z(opimm8, opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGESD_Z(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRANGESSValidFormsNoError(t *testing.T) { + if _, err := VRANGESS(opimm8, opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGESS(opimm8, opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGESS(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGESS(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRANGESS_SAEValidFormsNoError(t *testing.T) { + if _, err := VRANGESS_SAE(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGESS_SAE(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRANGESS_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VRANGESS_SAE_Z(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRANGESS_ZValidFormsNoError(t *testing.T) { + if _, err := VRANGESS_Z(opimm8, opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRANGESS_Z(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP14PDValidFormsNoError(t *testing.T) { + if _, err := VRCP14PD(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PD(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PD(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PD(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PD(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PD(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PD(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PD(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PD(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PD(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PD(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP14PD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VRCP14PD_BCST(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PD_BCST(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PD_BCST(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PD_BCST(opm64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PD_BCST(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PD_BCST(opm64, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP14PD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VRCP14PD_BCST_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PD_BCST_Z(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PD_BCST_Z(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP14PD_ZValidFormsNoError(t *testing.T) { + if _, err := VRCP14PD_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PD_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PD_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PD_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PD_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PD_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP14PSValidFormsNoError(t *testing.T) { + if _, err := VRCP14PS(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PS(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PS(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PS(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PS(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PS(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PS(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PS(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PS(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PS(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PS(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP14PS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VRCP14PS_BCST(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PS_BCST(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PS_BCST(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PS_BCST(opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PS_BCST(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PS_BCST(opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP14PS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VRCP14PS_BCST_Z(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PS_BCST_Z(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PS_BCST_Z(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP14PS_ZValidFormsNoError(t *testing.T) { + if _, err := VRCP14PS_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PS_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PS_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PS_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PS_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14PS_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP14SDValidFormsNoError(t *testing.T) { + if _, err := VRCP14SD(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14SD(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14SD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14SD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP14SD_ZValidFormsNoError(t *testing.T) { + if _, err := VRCP14SD_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14SD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP14SSValidFormsNoError(t *testing.T) { + if _, err := VRCP14SS(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14SS(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14SS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14SS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP14SS_ZValidFormsNoError(t *testing.T) { + if _, err := VRCP14SS_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP14SS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP28PDValidFormsNoError(t *testing.T) { + if _, err := VRCP28PD(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP28PD(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP28PD(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP28PD(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP28PD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VRCP28PD_BCST(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP28PD_BCST(opm64, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP28PD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VRCP28PD_BCST_Z(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP28PD_SAEValidFormsNoError(t *testing.T) { + if _, err := VRCP28PD_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP28PD_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP28PD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VRCP28PD_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP28PD_ZValidFormsNoError(t *testing.T) { + if _, err := VRCP28PD_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP28PD_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP28PSValidFormsNoError(t *testing.T) { + if _, err := VRCP28PS(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP28PS(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP28PS(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP28PS(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP28PS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VRCP28PS_BCST(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP28PS_BCST(opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP28PS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VRCP28PS_BCST_Z(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP28PS_SAEValidFormsNoError(t *testing.T) { + if _, err := VRCP28PS_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP28PS_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP28PS_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VRCP28PS_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP28PS_ZValidFormsNoError(t *testing.T) { + if _, err := VRCP28PS_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP28PS_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP28SDValidFormsNoError(t *testing.T) { + if _, err := VRCP28SD(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP28SD(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP28SD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP28SD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP28SD_SAEValidFormsNoError(t *testing.T) { + if _, err := VRCP28SD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP28SD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP28SD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VRCP28SD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP28SD_ZValidFormsNoError(t *testing.T) { + if _, err := VRCP28SD_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP28SD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP28SSValidFormsNoError(t *testing.T) { + if _, err := VRCP28SS(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP28SS(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP28SS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP28SS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP28SS_SAEValidFormsNoError(t *testing.T) { + if _, err := VRCP28SS_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP28SS_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP28SS_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VRCP28SS_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCP28SS_ZValidFormsNoError(t *testing.T) { + if _, err := VRCP28SS_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCP28SS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRCPPSValidFormsNoError(t *testing.T) { + if _, err := VRCPPS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCPPS(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRCPPS(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCPPS(opymm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVRCPSSValidFormsNoError(t *testing.T) { + if _, err := VRCPSS(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRCPSS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVREDUCEPDValidFormsNoError(t *testing.T) { + if _, err := VREDUCEPD(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPD(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPD(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPD(opimm8, opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPD(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPD(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPD(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPD(opimm8, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPD(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPD(opimm8, opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPD(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPD(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVREDUCEPD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VREDUCEPD_BCST(opimm8, opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPD_BCST(opimm8, opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPD_BCST(opimm8, opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPD_BCST(opimm8, opm64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPD_BCST(opimm8, opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPD_BCST(opimm8, opm64, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVREDUCEPD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VREDUCEPD_BCST_Z(opimm8, opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPD_BCST_Z(opimm8, opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPD_BCST_Z(opimm8, opm64, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVREDUCEPD_ZValidFormsNoError(t *testing.T) { + if _, err := VREDUCEPD_Z(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPD_Z(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPD_Z(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPD_Z(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPD_Z(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPD_Z(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVREDUCEPSValidFormsNoError(t *testing.T) { + if _, err := VREDUCEPS(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPS(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPS(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPS(opimm8, opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPS(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPS(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPS(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPS(opimm8, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPS(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPS(opimm8, opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPS(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPS(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVREDUCEPS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VREDUCEPS_BCST(opimm8, opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPS_BCST(opimm8, opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPS_BCST(opimm8, opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPS_BCST(opimm8, opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPS_BCST(opimm8, opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPS_BCST(opimm8, opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVREDUCEPS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VREDUCEPS_BCST_Z(opimm8, opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPS_BCST_Z(opimm8, opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPS_BCST_Z(opimm8, opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVREDUCEPS_ZValidFormsNoError(t *testing.T) { + if _, err := VREDUCEPS_Z(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPS_Z(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPS_Z(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPS_Z(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPS_Z(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCEPS_Z(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVREDUCESDValidFormsNoError(t *testing.T) { + if _, err := VREDUCESD(opimm8, opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCESD(opimm8, opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCESD(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCESD(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVREDUCESD_ZValidFormsNoError(t *testing.T) { + if _, err := VREDUCESD_Z(opimm8, opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCESD_Z(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVREDUCESSValidFormsNoError(t *testing.T) { + if _, err := VREDUCESS(opimm8, opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCESS(opimm8, opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCESS(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCESS(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVREDUCESS_ZValidFormsNoError(t *testing.T) { + if _, err := VREDUCESS_Z(opimm8, opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VREDUCESS_Z(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRNDSCALEPDValidFormsNoError(t *testing.T) { + if _, err := VRNDSCALEPD(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPD(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPD(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPD(opimm8, opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPD(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPD(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPD(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPD(opimm8, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPD(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPD(opimm8, opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPD(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPD(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRNDSCALEPD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VRNDSCALEPD_BCST(opimm8, opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPD_BCST(opimm8, opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPD_BCST(opimm8, opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPD_BCST(opimm8, opm64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPD_BCST(opimm8, opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPD_BCST(opimm8, opm64, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRNDSCALEPD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VRNDSCALEPD_BCST_Z(opimm8, opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPD_BCST_Z(opimm8, opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPD_BCST_Z(opimm8, opm64, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRNDSCALEPD_SAEValidFormsNoError(t *testing.T) { + if _, err := VRNDSCALEPD_SAE(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPD_SAE(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRNDSCALEPD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VRNDSCALEPD_SAE_Z(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRNDSCALEPD_ZValidFormsNoError(t *testing.T) { + if _, err := VRNDSCALEPD_Z(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPD_Z(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPD_Z(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPD_Z(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPD_Z(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPD_Z(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRNDSCALEPSValidFormsNoError(t *testing.T) { + if _, err := VRNDSCALEPS(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPS(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPS(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPS(opimm8, opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPS(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPS(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPS(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPS(opimm8, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPS(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPS(opimm8, opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPS(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPS(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRNDSCALEPS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VRNDSCALEPS_BCST(opimm8, opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPS_BCST(opimm8, opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPS_BCST(opimm8, opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPS_BCST(opimm8, opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPS_BCST(opimm8, opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPS_BCST(opimm8, opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRNDSCALEPS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VRNDSCALEPS_BCST_Z(opimm8, opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPS_BCST_Z(opimm8, opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPS_BCST_Z(opimm8, opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRNDSCALEPS_SAEValidFormsNoError(t *testing.T) { + if _, err := VRNDSCALEPS_SAE(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPS_SAE(opimm8, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRNDSCALEPS_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VRNDSCALEPS_SAE_Z(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRNDSCALEPS_ZValidFormsNoError(t *testing.T) { + if _, err := VRNDSCALEPS_Z(opimm8, opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPS_Z(opimm8, opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPS_Z(opimm8, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPS_Z(opimm8, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPS_Z(opimm8, opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALEPS_Z(opimm8, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRNDSCALESDValidFormsNoError(t *testing.T) { + if _, err := VRNDSCALESD(opimm8, opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALESD(opimm8, opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALESD(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALESD(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRNDSCALESD_SAEValidFormsNoError(t *testing.T) { + if _, err := VRNDSCALESD_SAE(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALESD_SAE(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRNDSCALESD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VRNDSCALESD_SAE_Z(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRNDSCALESD_ZValidFormsNoError(t *testing.T) { + if _, err := VRNDSCALESD_Z(opimm8, opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALESD_Z(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRNDSCALESSValidFormsNoError(t *testing.T) { + if _, err := VRNDSCALESS(opimm8, opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALESS(opimm8, opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALESS(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALESS(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRNDSCALESS_SAEValidFormsNoError(t *testing.T) { + if _, err := VRNDSCALESS_SAE(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALESS_SAE(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRNDSCALESS_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VRNDSCALESS_SAE_Z(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRNDSCALESS_ZValidFormsNoError(t *testing.T) { + if _, err := VRNDSCALESS_Z(opimm8, opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRNDSCALESS_Z(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVROUNDPDValidFormsNoError(t *testing.T) { + if _, err := VROUNDPD(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VROUNDPD(opimm8, opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VROUNDPD(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VROUNDPD(opimm8, opymm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVROUNDPSValidFormsNoError(t *testing.T) { + if _, err := VROUNDPS(opimm8, opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VROUNDPS(opimm8, opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VROUNDPS(opimm8, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VROUNDPS(opimm8, opymm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVROUNDSDValidFormsNoError(t *testing.T) { + if _, err := VROUNDSD(opimm8, opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VROUNDSD(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVROUNDSSValidFormsNoError(t *testing.T) { + if _, err := VROUNDSS(opimm8, opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VROUNDSS(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT14PDValidFormsNoError(t *testing.T) { + if _, err := VRSQRT14PD(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PD(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PD(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PD(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PD(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PD(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PD(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PD(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PD(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PD(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PD(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT14PD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VRSQRT14PD_BCST(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PD_BCST(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PD_BCST(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PD_BCST(opm64, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PD_BCST(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PD_BCST(opm64, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT14PD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VRSQRT14PD_BCST_Z(opm64, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PD_BCST_Z(opm64, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PD_BCST_Z(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT14PD_ZValidFormsNoError(t *testing.T) { + if _, err := VRSQRT14PD_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PD_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PD_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PD_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PD_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PD_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT14PSValidFormsNoError(t *testing.T) { + if _, err := VRSQRT14PS(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PS(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PS(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PS(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PS(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PS(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PS(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PS(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PS(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PS(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PS(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT14PS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VRSQRT14PS_BCST(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PS_BCST(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PS_BCST(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PS_BCST(opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PS_BCST(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PS_BCST(opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT14PS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VRSQRT14PS_BCST_Z(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PS_BCST_Z(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PS_BCST_Z(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT14PS_ZValidFormsNoError(t *testing.T) { + if _, err := VRSQRT14PS_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PS_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PS_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PS_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PS_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14PS_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT14SDValidFormsNoError(t *testing.T) { + if _, err := VRSQRT14SD(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14SD(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14SD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14SD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT14SD_ZValidFormsNoError(t *testing.T) { + if _, err := VRSQRT14SD_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14SD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT14SSValidFormsNoError(t *testing.T) { + if _, err := VRSQRT14SS(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14SS(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14SS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14SS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT14SS_ZValidFormsNoError(t *testing.T) { + if _, err := VRSQRT14SS_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT14SS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT28PDValidFormsNoError(t *testing.T) { + if _, err := VRSQRT28PD(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT28PD(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT28PD(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT28PD(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT28PD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VRSQRT28PD_BCST(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT28PD_BCST(opm64, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT28PD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VRSQRT28PD_BCST_Z(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT28PD_SAEValidFormsNoError(t *testing.T) { + if _, err := VRSQRT28PD_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT28PD_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT28PD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VRSQRT28PD_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT28PD_ZValidFormsNoError(t *testing.T) { + if _, err := VRSQRT28PD_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT28PD_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT28PSValidFormsNoError(t *testing.T) { + if _, err := VRSQRT28PS(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT28PS(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT28PS(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT28PS(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT28PS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VRSQRT28PS_BCST(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT28PS_BCST(opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT28PS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VRSQRT28PS_BCST_Z(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT28PS_SAEValidFormsNoError(t *testing.T) { + if _, err := VRSQRT28PS_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT28PS_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT28PS_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VRSQRT28PS_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT28PS_ZValidFormsNoError(t *testing.T) { + if _, err := VRSQRT28PS_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT28PS_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT28SDValidFormsNoError(t *testing.T) { + if _, err := VRSQRT28SD(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT28SD(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT28SD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT28SD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT28SD_SAEValidFormsNoError(t *testing.T) { + if _, err := VRSQRT28SD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT28SD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT28SD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VRSQRT28SD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT28SD_ZValidFormsNoError(t *testing.T) { + if _, err := VRSQRT28SD_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT28SD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT28SSValidFormsNoError(t *testing.T) { + if _, err := VRSQRT28SS(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT28SS(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT28SS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT28SS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT28SS_SAEValidFormsNoError(t *testing.T) { + if _, err := VRSQRT28SS_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT28SS_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT28SS_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VRSQRT28SS_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRT28SS_ZValidFormsNoError(t *testing.T) { + if _, err := VRSQRT28SS_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRT28SS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRTPSValidFormsNoError(t *testing.T) { + if _, err := VRSQRTPS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRTPS(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRTPS(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRTPS(opymm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVRSQRTSSValidFormsNoError(t *testing.T) { + if _, err := VRSQRTSS(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VRSQRTSS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFPDValidFormsNoError(t *testing.T) { + if _, err := VSCALEFPD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFPD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VSCALEFPD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFPD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VSCALEFPD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFPD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VSCALEFPD_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPD_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFPD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSCALEFPD_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFPD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VSCALEFPD_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPD_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFPD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSCALEFPD_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFPD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VSCALEFPD_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPD_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFPD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSCALEFPD_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFPD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VSCALEFPD_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPD_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFPD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSCALEFPD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFPD_ZValidFormsNoError(t *testing.T) { + if _, err := VSCALEFPD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFPSValidFormsNoError(t *testing.T) { + if _, err := VSCALEFPS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFPS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VSCALEFPS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFPS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VSCALEFPS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFPS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VSCALEFPS_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPS_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFPS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSCALEFPS_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFPS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VSCALEFPS_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPS_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFPS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSCALEFPS_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFPS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VSCALEFPS_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPS_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFPS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSCALEFPS_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFPS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VSCALEFPS_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPS_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFPS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSCALEFPS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFPS_ZValidFormsNoError(t *testing.T) { + if _, err := VSCALEFPS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFPS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFSDValidFormsNoError(t *testing.T) { + if _, err := VSCALEFSD(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFSD(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFSD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFSD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFSD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VSCALEFSD_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFSD_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFSD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSCALEFSD_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFSD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VSCALEFSD_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFSD_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFSD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSCALEFSD_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFSD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VSCALEFSD_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFSD_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFSD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSCALEFSD_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFSD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VSCALEFSD_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFSD_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFSD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSCALEFSD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFSD_ZValidFormsNoError(t *testing.T) { + if _, err := VSCALEFSD_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFSD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFSSValidFormsNoError(t *testing.T) { + if _, err := VSCALEFSS(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFSS(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFSS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFSS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFSS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VSCALEFSS_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFSS_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFSS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSCALEFSS_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFSS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VSCALEFSS_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFSS_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFSS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSCALEFSS_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFSS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VSCALEFSS_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFSS_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFSS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSCALEFSS_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFSS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VSCALEFSS_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFSS_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFSS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSCALEFSS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCALEFSS_ZValidFormsNoError(t *testing.T) { + if _, err := VSCALEFSS_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSCALEFSS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSCATTERDPDValidFormsNoError(t *testing.T) { + if _, err := VSCATTERDPD(opxmm, opk, opvm32x); err != nil { + t.Fatal(err) + } + if _, err := VSCATTERDPD(opymm, opk, opvm32x); err != nil { + t.Fatal(err) + } + if _, err := VSCATTERDPD(opzmm, opk, opvm32y); err != nil { + t.Fatal(err) + } +} + +func TestVSCATTERDPSValidFormsNoError(t *testing.T) { + if _, err := VSCATTERDPS(opxmm, opk, opvm32x); err != nil { + t.Fatal(err) + } + if _, err := VSCATTERDPS(opymm, opk, opvm32y); err != nil { + t.Fatal(err) + } + if _, err := VSCATTERDPS(opzmm, opk, opvm32z); err != nil { + t.Fatal(err) + } +} + +func TestVSCATTERQPDValidFormsNoError(t *testing.T) { + if _, err := VSCATTERQPD(opxmm, opk, opvm64x); err != nil { + t.Fatal(err) + } + if _, err := VSCATTERQPD(opymm, opk, opvm64y); err != nil { + t.Fatal(err) + } + if _, err := VSCATTERQPD(opzmm, opk, opvm64z); err != nil { + t.Fatal(err) + } +} + +func TestVSCATTERQPSValidFormsNoError(t *testing.T) { + if _, err := VSCATTERQPS(opxmm, opk, opvm64x); err != nil { + t.Fatal(err) + } + if _, err := VSCATTERQPS(opxmm, opk, opvm64y); err != nil { + t.Fatal(err) + } + if _, err := VSCATTERQPS(opymm, opk, opvm64z); err != nil { + t.Fatal(err) + } +} + +func TestVSHUFF32X4ValidFormsNoError(t *testing.T) { + if _, err := VSHUFF32X4(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFF32X4(opimm8, opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFF32X4(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFF32X4(opimm8, opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFF32X4(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFF32X4(opimm8, opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFF32X4(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFF32X4(opimm8, opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSHUFF32X4_BCSTValidFormsNoError(t *testing.T) { + if _, err := VSHUFF32X4_BCST(opimm8, opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFF32X4_BCST(opimm8, opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFF32X4_BCST(opimm8, opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFF32X4_BCST(opimm8, opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSHUFF32X4_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VSHUFF32X4_BCST_Z(opimm8, opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFF32X4_BCST_Z(opimm8, opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSHUFF32X4_ZValidFormsNoError(t *testing.T) { + if _, err := VSHUFF32X4_Z(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFF32X4_Z(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFF32X4_Z(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFF32X4_Z(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSHUFF64X2ValidFormsNoError(t *testing.T) { + if _, err := VSHUFF64X2(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFF64X2(opimm8, opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFF64X2(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFF64X2(opimm8, opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFF64X2(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFF64X2(opimm8, opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFF64X2(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFF64X2(opimm8, opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSHUFF64X2_BCSTValidFormsNoError(t *testing.T) { + if _, err := VSHUFF64X2_BCST(opimm8, opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFF64X2_BCST(opimm8, opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFF64X2_BCST(opimm8, opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFF64X2_BCST(opimm8, opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSHUFF64X2_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VSHUFF64X2_BCST_Z(opimm8, opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFF64X2_BCST_Z(opimm8, opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSHUFF64X2_ZValidFormsNoError(t *testing.T) { + if _, err := VSHUFF64X2_Z(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFF64X2_Z(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFF64X2_Z(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFF64X2_Z(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSHUFI32X4ValidFormsNoError(t *testing.T) { + if _, err := VSHUFI32X4(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFI32X4(opimm8, opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFI32X4(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFI32X4(opimm8, opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFI32X4(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFI32X4(opimm8, opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFI32X4(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFI32X4(opimm8, opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSHUFI32X4_BCSTValidFormsNoError(t *testing.T) { + if _, err := VSHUFI32X4_BCST(opimm8, opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFI32X4_BCST(opimm8, opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFI32X4_BCST(opimm8, opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFI32X4_BCST(opimm8, opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSHUFI32X4_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VSHUFI32X4_BCST_Z(opimm8, opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFI32X4_BCST_Z(opimm8, opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSHUFI32X4_ZValidFormsNoError(t *testing.T) { + if _, err := VSHUFI32X4_Z(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFI32X4_Z(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFI32X4_Z(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFI32X4_Z(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSHUFI64X2ValidFormsNoError(t *testing.T) { + if _, err := VSHUFI64X2(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFI64X2(opimm8, opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFI64X2(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFI64X2(opimm8, opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFI64X2(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFI64X2(opimm8, opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFI64X2(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFI64X2(opimm8, opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSHUFI64X2_BCSTValidFormsNoError(t *testing.T) { + if _, err := VSHUFI64X2_BCST(opimm8, opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFI64X2_BCST(opimm8, opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFI64X2_BCST(opimm8, opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFI64X2_BCST(opimm8, opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSHUFI64X2_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VSHUFI64X2_BCST_Z(opimm8, opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFI64X2_BCST_Z(opimm8, opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSHUFI64X2_ZValidFormsNoError(t *testing.T) { + if _, err := VSHUFI64X2_Z(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFI64X2_Z(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFI64X2_Z(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFI64X2_Z(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSHUFPDValidFormsNoError(t *testing.T) { + if _, err := VSHUFPD(opimm8, opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPD(opimm8, opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPD(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPD(opimm8, opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPD(opimm8, opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPD(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPD(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPD(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPD(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPD(opimm8, opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPD(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPD(opimm8, opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSHUFPD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VSHUFPD_BCST(opimm8, opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPD_BCST(opimm8, opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPD_BCST(opimm8, opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPD_BCST(opimm8, opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPD_BCST(opimm8, opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPD_BCST(opimm8, opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSHUFPD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VSHUFPD_BCST_Z(opimm8, opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPD_BCST_Z(opimm8, opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPD_BCST_Z(opimm8, opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSHUFPD_ZValidFormsNoError(t *testing.T) { + if _, err := VSHUFPD_Z(opimm8, opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPD_Z(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPD_Z(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPD_Z(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPD_Z(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPD_Z(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSHUFPSValidFormsNoError(t *testing.T) { + if _, err := VSHUFPS(opimm8, opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPS(opimm8, opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPS(opimm8, opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPS(opimm8, opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPS(opimm8, opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPS(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPS(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPS(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPS(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPS(opimm8, opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPS(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPS(opimm8, opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSHUFPS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VSHUFPS_BCST(opimm8, opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPS_BCST(opimm8, opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPS_BCST(opimm8, opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPS_BCST(opimm8, opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPS_BCST(opimm8, opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPS_BCST(opimm8, opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSHUFPS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VSHUFPS_BCST_Z(opimm8, opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPS_BCST_Z(opimm8, opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPS_BCST_Z(opimm8, opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSHUFPS_ZValidFormsNoError(t *testing.T) { + if _, err := VSHUFPS_Z(opimm8, opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPS_Z(opimm8, opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPS_Z(opimm8, opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPS_Z(opimm8, opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPS_Z(opimm8, opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSHUFPS_Z(opimm8, opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTPDValidFormsNoError(t *testing.T) { + if _, err := VSQRTPD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPD(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPD(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPD(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPD(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPD(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPD(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPD(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPD(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPD(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPD(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPD(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTPD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VSQRTPD_BCST(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPD_BCST(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPD_BCST(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPD_BCST(opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPD_BCST(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPD_BCST(opm64, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTPD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VSQRTPD_BCST_Z(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPD_BCST_Z(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPD_BCST_Z(opm64, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTPD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VSQRTPD_RD_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPD_RD_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTPD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSQRTPD_RD_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTPD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VSQRTPD_RN_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPD_RN_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTPD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSQRTPD_RN_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTPD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VSQRTPD_RU_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPD_RU_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTPD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSQRTPD_RU_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTPD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VSQRTPD_RZ_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPD_RZ_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTPD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSQRTPD_RZ_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTPD_ZValidFormsNoError(t *testing.T) { + if _, err := VSQRTPD_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPD_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPD_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPD_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPD_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPD_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTPSValidFormsNoError(t *testing.T) { + if _, err := VSQRTPS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPS(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPS(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPS(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPS(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPS(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPS(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPS(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPS(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPS(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPS(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPS(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTPS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VSQRTPS_BCST(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPS_BCST(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPS_BCST(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPS_BCST(opm32, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPS_BCST(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPS_BCST(opm32, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTPS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VSQRTPS_BCST_Z(opm32, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPS_BCST_Z(opm32, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPS_BCST_Z(opm32, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTPS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VSQRTPS_RD_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPS_RD_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTPS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSQRTPS_RD_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTPS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VSQRTPS_RN_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPS_RN_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTPS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSQRTPS_RN_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTPS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VSQRTPS_RU_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPS_RU_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTPS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSQRTPS_RU_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTPS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VSQRTPS_RZ_SAE(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPS_RZ_SAE(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTPS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSQRTPS_RZ_SAE_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTPS_ZValidFormsNoError(t *testing.T) { + if _, err := VSQRTPS_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPS_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPS_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPS_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPS_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTPS_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTSDValidFormsNoError(t *testing.T) { + if _, err := VSQRTSD(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTSD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTSD(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTSD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTSD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VSQRTSD_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTSD_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTSD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSQRTSD_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTSD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VSQRTSD_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTSD_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTSD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSQRTSD_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTSD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VSQRTSD_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTSD_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTSD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSQRTSD_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTSD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VSQRTSD_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTSD_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTSD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSQRTSD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTSD_ZValidFormsNoError(t *testing.T) { + if _, err := VSQRTSD_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTSD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTSSValidFormsNoError(t *testing.T) { + if _, err := VSQRTSS(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTSS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTSS(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTSS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTSS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VSQRTSS_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTSS_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTSS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSQRTSS_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTSS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VSQRTSS_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTSS_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTSS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSQRTSS_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTSS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VSQRTSS_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTSS_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTSS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSQRTSS_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTSS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VSQRTSS_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTSS_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTSS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSQRTSS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSQRTSS_ZValidFormsNoError(t *testing.T) { + if _, err := VSQRTSS_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSQRTSS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSTMXCSRValidFormsNoError(t *testing.T) { + if _, err := VSTMXCSR(opm32); err != nil { + t.Fatal(err) + } +} + +func TestVSUBPDValidFormsNoError(t *testing.T) { + if _, err := VSUBPD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBPD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VSUBPD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBPD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VSUBPD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBPD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VSUBPD_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPD_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBPD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSUBPD_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBPD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VSUBPD_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPD_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBPD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSUBPD_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBPD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VSUBPD_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPD_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBPD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSUBPD_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBPD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VSUBPD_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPD_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBPD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSUBPD_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBPD_ZValidFormsNoError(t *testing.T) { + if _, err := VSUBPD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBPSValidFormsNoError(t *testing.T) { + if _, err := VSUBPS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBPS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VSUBPS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBPS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VSUBPS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBPS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VSUBPS_RD_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPS_RD_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBPS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSUBPS_RD_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBPS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VSUBPS_RN_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPS_RN_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBPS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSUBPS_RN_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBPS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VSUBPS_RU_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPS_RU_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBPS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSUBPS_RU_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBPS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VSUBPS_RZ_SAE(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPS_RZ_SAE(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBPS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSUBPS_RZ_SAE_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBPS_ZValidFormsNoError(t *testing.T) { + if _, err := VSUBPS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBPS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBSDValidFormsNoError(t *testing.T) { + if _, err := VSUBSD(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBSD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBSD(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBSD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBSD_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VSUBSD_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBSD_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBSD_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSUBSD_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBSD_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VSUBSD_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBSD_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBSD_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSUBSD_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBSD_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VSUBSD_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBSD_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBSD_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSUBSD_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBSD_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VSUBSD_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBSD_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBSD_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSUBSD_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBSD_ZValidFormsNoError(t *testing.T) { + if _, err := VSUBSD_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBSD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBSSValidFormsNoError(t *testing.T) { + if _, err := VSUBSS(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBSS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBSS(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBSS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBSS_RD_SAEValidFormsNoError(t *testing.T) { + if _, err := VSUBSS_RD_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBSS_RD_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBSS_RD_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSUBSS_RD_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBSS_RN_SAEValidFormsNoError(t *testing.T) { + if _, err := VSUBSS_RN_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBSS_RN_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBSS_RN_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSUBSS_RN_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBSS_RU_SAEValidFormsNoError(t *testing.T) { + if _, err := VSUBSS_RU_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBSS_RU_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBSS_RU_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSUBSS_RU_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBSS_RZ_SAEValidFormsNoError(t *testing.T) { + if _, err := VSUBSS_RZ_SAE(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBSS_RZ_SAE(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBSS_RZ_SAE_ZValidFormsNoError(t *testing.T) { + if _, err := VSUBSS_RZ_SAE_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVSUBSS_ZValidFormsNoError(t *testing.T) { + if _, err := VSUBSS_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VSUBSS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVTESTPDValidFormsNoError(t *testing.T) { + if _, err := VTESTPD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VTESTPD(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VTESTPD(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VTESTPD(opymm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVTESTPSValidFormsNoError(t *testing.T) { + if _, err := VTESTPS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VTESTPS(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VTESTPS(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VTESTPS(opymm, opymm); err != nil { + t.Fatal(err) + } +} + +func TestVUCOMISDValidFormsNoError(t *testing.T) { + if _, err := VUCOMISD(opm64, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUCOMISD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVUCOMISD_SAEValidFormsNoError(t *testing.T) { + if _, err := VUCOMISD_SAE(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVUCOMISSValidFormsNoError(t *testing.T) { + if _, err := VUCOMISS(opm32, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUCOMISS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVUCOMISS_SAEValidFormsNoError(t *testing.T) { + if _, err := VUCOMISS_SAE(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestVUNPCKHPDValidFormsNoError(t *testing.T) { + if _, err := VUNPCKHPD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVUNPCKHPD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VUNPCKHPD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVUNPCKHPD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VUNPCKHPD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVUNPCKHPD_ZValidFormsNoError(t *testing.T) { + if _, err := VUNPCKHPD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVUNPCKHPSValidFormsNoError(t *testing.T) { + if _, err := VUNPCKHPS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVUNPCKHPS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VUNPCKHPS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVUNPCKHPS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VUNPCKHPS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVUNPCKHPS_ZValidFormsNoError(t *testing.T) { + if _, err := VUNPCKHPS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKHPS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVUNPCKLPDValidFormsNoError(t *testing.T) { + if _, err := VUNPCKLPD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVUNPCKLPD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VUNPCKLPD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVUNPCKLPD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VUNPCKLPD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVUNPCKLPD_ZValidFormsNoError(t *testing.T) { + if _, err := VUNPCKLPD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVUNPCKLPSValidFormsNoError(t *testing.T) { + if _, err := VUNPCKLPS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVUNPCKLPS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VUNPCKLPS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVUNPCKLPS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VUNPCKLPS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVUNPCKLPS_ZValidFormsNoError(t *testing.T) { + if _, err := VUNPCKLPS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VUNPCKLPS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVXORPDValidFormsNoError(t *testing.T) { + if _, err := VXORPD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VXORPD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VXORPD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VXORPD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VXORPD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VXORPD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VXORPD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VXORPD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VXORPD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VXORPD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VXORPD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VXORPD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVXORPD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VXORPD_BCST(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VXORPD_BCST(opm64, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VXORPD_BCST(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VXORPD_BCST(opm64, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VXORPD_BCST(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VXORPD_BCST(opm64, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVXORPD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VXORPD_BCST_Z(opm64, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VXORPD_BCST_Z(opm64, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VXORPD_BCST_Z(opm64, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVXORPD_ZValidFormsNoError(t *testing.T) { + if _, err := VXORPD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VXORPD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VXORPD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VXORPD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VXORPD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VXORPD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVXORPSValidFormsNoError(t *testing.T) { + if _, err := VXORPS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VXORPS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VXORPS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VXORPS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VXORPS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VXORPS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VXORPS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VXORPS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VXORPS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VXORPS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VXORPS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VXORPS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVXORPS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VXORPS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VXORPS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VXORPS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VXORPS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VXORPS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VXORPS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVXORPS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VXORPS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VXORPS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VXORPS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVXORPS_ZValidFormsNoError(t *testing.T) { + if _, err := VXORPS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VXORPS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VXORPS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VXORPS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VXORPS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VXORPS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVZEROALLValidFormsNoError(t *testing.T) { + if _, err := VZEROALL(); err != nil { + t.Fatal(err) + } +} + +func TestVZEROUPPERValidFormsNoError(t *testing.T) { + if _, err := VZEROUPPER(); err != nil { + t.Fatal(err) + } +} + +func TestXADDBValidFormsNoError(t *testing.T) { + if _, err := XADDB(opr8, opm8); err != nil { + t.Fatal(err) + } + if _, err := XADDB(opr8, opr8); err != nil { + t.Fatal(err) + } +} + +func TestXADDLValidFormsNoError(t *testing.T) { + if _, err := XADDL(opr32, opm32); err != nil { + t.Fatal(err) + } + if _, err := XADDL(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestXADDQValidFormsNoError(t *testing.T) { + if _, err := XADDQ(opr64, opm64); err != nil { + t.Fatal(err) + } + if _, err := XADDQ(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestXADDWValidFormsNoError(t *testing.T) { + if _, err := XADDW(opr16, opm16); err != nil { + t.Fatal(err) + } + if _, err := XADDW(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestXCHGBValidFormsNoError(t *testing.T) { + if _, err := XCHGB(opm8, opr8); err != nil { + t.Fatal(err) + } + if _, err := XCHGB(opr8, opm8); err != nil { + t.Fatal(err) + } + if _, err := XCHGB(opr8, opr8); err != nil { + t.Fatal(err) + } +} + +func TestXCHGLValidFormsNoError(t *testing.T) { + if _, err := XCHGL(opeax, opr32); err != nil { + t.Fatal(err) + } + if _, err := XCHGL(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := XCHGL(opr32, opeax); err != nil { + t.Fatal(err) + } + if _, err := XCHGL(opr32, opm32); err != nil { + t.Fatal(err) + } + if _, err := XCHGL(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestXCHGQValidFormsNoError(t *testing.T) { + if _, err := XCHGQ(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := XCHGQ(opr64, opm64); err != nil { + t.Fatal(err) + } + if _, err := XCHGQ(opr64, opr64); err != nil { + t.Fatal(err) + } + if _, err := XCHGQ(opr64, oprax); err != nil { + t.Fatal(err) + } + if _, err := XCHGQ(oprax, opr64); err != nil { + t.Fatal(err) + } +} + +func TestXCHGWValidFormsNoError(t *testing.T) { + if _, err := XCHGW(opax, opr16); err != nil { + t.Fatal(err) + } + if _, err := XCHGW(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := XCHGW(opr16, opax); err != nil { + t.Fatal(err) + } + if _, err := XCHGW(opr16, opm16); err != nil { + t.Fatal(err) + } + if _, err := XCHGW(opr16, opr16); err != nil { + t.Fatal(err) + } +} + +func TestXGETBVValidFormsNoError(t *testing.T) { + if _, err := XGETBV(); err != nil { + t.Fatal(err) + } +} + +func TestXLATValidFormsNoError(t *testing.T) { + if _, err := XLAT(); err != nil { + t.Fatal(err) + } +} + +func TestXORBValidFormsNoError(t *testing.T) { + if _, err := XORB(opimm8, opal); err != nil { + t.Fatal(err) + } + if _, err := XORB(opimm8, opm8); err != nil { + t.Fatal(err) + } + if _, err := XORB(opimm8, opr8); err != nil { + t.Fatal(err) + } + if _, err := XORB(opm8, opr8); err != nil { + t.Fatal(err) + } + if _, err := XORB(opr8, opm8); err != nil { + t.Fatal(err) + } + if _, err := XORB(opr8, opr8); err != nil { + t.Fatal(err) + } +} + +func TestXORLValidFormsNoError(t *testing.T) { + if _, err := XORL(opimm32, opeax); err != nil { + t.Fatal(err) + } + if _, err := XORL(opimm32, opm32); err != nil { + t.Fatal(err) + } + if _, err := XORL(opimm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := XORL(opimm8, opm32); err != nil { + t.Fatal(err) + } + if _, err := XORL(opimm8, opr32); err != nil { + t.Fatal(err) + } + if _, err := XORL(opm32, opr32); err != nil { + t.Fatal(err) + } + if _, err := XORL(opr32, opm32); err != nil { + t.Fatal(err) + } + if _, err := XORL(opr32, opr32); err != nil { + t.Fatal(err) + } +} + +func TestXORPDValidFormsNoError(t *testing.T) { + if _, err := XORPD(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := XORPD(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestXORPSValidFormsNoError(t *testing.T) { + if _, err := XORPS(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := XORPS(opxmm, opxmm); err != nil { + t.Fatal(err) + } +} + +func TestXORQValidFormsNoError(t *testing.T) { + if _, err := XORQ(opimm32, opm64); err != nil { + t.Fatal(err) + } + if _, err := XORQ(opimm32, opr64); err != nil { + t.Fatal(err) + } + if _, err := XORQ(opimm32, oprax); err != nil { + t.Fatal(err) + } + if _, err := XORQ(opimm8, opm64); err != nil { + t.Fatal(err) + } + if _, err := XORQ(opimm8, opr64); err != nil { + t.Fatal(err) + } + if _, err := XORQ(opm64, opr64); err != nil { + t.Fatal(err) + } + if _, err := XORQ(opr64, opm64); err != nil { + t.Fatal(err) + } + if _, err := XORQ(opr64, opr64); err != nil { + t.Fatal(err) + } +} + +func TestXORWValidFormsNoError(t *testing.T) { + if _, err := XORW(opimm16, opax); err != nil { + t.Fatal(err) + } + if _, err := XORW(opimm16, opm16); err != nil { + t.Fatal(err) + } + if _, err := XORW(opimm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := XORW(opimm8, opm16); err != nil { + t.Fatal(err) + } + if _, err := XORW(opimm8, opr16); err != nil { + t.Fatal(err) + } + if _, err := XORW(opm16, opr16); err != nil { + t.Fatal(err) + } + if _, err := XORW(opr16, opm16); err != nil { + t.Fatal(err) + } + if _, err := XORW(opr16, opr16); err != nil { + t.Fatal(err) + } } diff --git a/x86/zoptab.go b/x86/zoptab.go new file mode 100644 index 00000000..4479d4ff --- /dev/null +++ b/x86/zoptab.go @@ -0,0 +1,15641 @@ +// Code generated by command: avogen -output zoptab.go optab. DO NOT EDIT. + +package x86 + +import ( + "github.com/mmcloughlin/avo/operand" + "github.com/mmcloughlin/avo/reg" +) + +// maxoperands is the maximum number of operands in an instruction form, including implicit operands. +const maxoperands = 6 + +type oprndtype uint8 + +const ( + oprndtypeNone oprndtype = iota + oprndtype1 + oprndtype3 + oprndtypeAL + oprndtypeAX + oprndtypeCL + oprndtypeEAX + oprndtypeIMM16 + oprndtypeIMM2U + oprndtypeIMM32 + oprndtypeIMM64 + oprndtypeIMM8 + oprndtypeK + oprndtypeM + oprndtypeM128 + oprndtypeM16 + oprndtypeM256 + oprndtypeM32 + oprndtypeM512 + oprndtypeM64 + oprndtypeM8 + oprndtypeR16 + oprndtypeR32 + oprndtypeR64 + oprndtypeR8 + oprndtypeRAX + oprndtypeREL32 + oprndtypeREL8 + oprndtypeVM32X + oprndtypeVM32Y + oprndtypeVM32Z + oprndtypeVM64X + oprndtypeVM64Y + oprndtypeVM64Z + oprndtypeXMM + oprndtypeXMM0 + oprndtypeYMM + oprndtypeZMM + oprndtypemax +) + +func (o oprndtype) Match(op operand.Op) bool { + switch o { + default: + return false + case oprndtype1: + return operand.Is1(op) + case oprndtype3: + return operand.Is3(op) + case oprndtypeAL: + return operand.IsAL(op) + case oprndtypeAX: + return operand.IsAX(op) + case oprndtypeCL: + return operand.IsCL(op) + case oprndtypeEAX: + return operand.IsEAX(op) + case oprndtypeIMM16: + return operand.IsIMM16(op) + case oprndtypeIMM2U: + return operand.IsIMM2U(op) + case oprndtypeIMM32: + return operand.IsIMM32(op) + case oprndtypeIMM64: + return operand.IsIMM64(op) + case oprndtypeIMM8: + return operand.IsIMM8(op) + case oprndtypeK: + return operand.IsK(op) + case oprndtypeM: + return operand.IsM(op) + case oprndtypeM128: + return operand.IsM128(op) + case oprndtypeM16: + return operand.IsM16(op) + case oprndtypeM256: + return operand.IsM256(op) + case oprndtypeM32: + return operand.IsM32(op) + case oprndtypeM512: + return operand.IsM512(op) + case oprndtypeM64: + return operand.IsM64(op) + case oprndtypeM8: + return operand.IsM8(op) + case oprndtypeR16: + return operand.IsR16(op) + case oprndtypeR32: + return operand.IsR32(op) + case oprndtypeR64: + return operand.IsR64(op) + case oprndtypeR8: + return operand.IsR8(op) + case oprndtypeRAX: + return operand.IsRAX(op) + case oprndtypeREL32: + return operand.IsREL32(op) + case oprndtypeREL8: + return operand.IsREL8(op) + case oprndtypeVM32X: + return operand.IsVM32X(op) + case oprndtypeVM32Y: + return operand.IsVM32Y(op) + case oprndtypeVM32Z: + return operand.IsVM32Z(op) + case oprndtypeVM64X: + return operand.IsVM64X(op) + case oprndtypeVM64Y: + return operand.IsVM64Y(op) + case oprndtypeVM64Z: + return operand.IsVM64Z(op) + case oprndtypeXMM: + return operand.IsXMM(op) + case oprndtypeXMM0: + return operand.IsXMM0(op) + case oprndtypeYMM: + return operand.IsYMM(op) + case oprndtypeZMM: + return operand.IsZMM(op) + } +} + +type implreg uint8 + +const ( + implregNone implreg = iota + implregAL + implregAX + implregDX + implregEAX + implregEBX + implregECX + implregEDX + implregR11 + implregRAX + implregRBX + implregRCX + implregRDI + implregRDX + implregX0 + implregmax +) + +func (i implreg) Register() reg.Register { + switch i { + default: + panic("unexpected implicit register type") + case implregAL: + return reg.AL + case implregAX: + return reg.AX + case implregDX: + return reg.DX + case implregEAX: + return reg.EAX + case implregEBX: + return reg.EBX + case implregECX: + return reg.ECX + case implregEDX: + return reg.EDX + case implregR11: + return reg.R11 + case implregRAX: + return reg.RAX + case implregRBX: + return reg.RBX + case implregRCX: + return reg.RCX + case implregRDI: + return reg.RDI + case implregRDX: + return reg.RDX + case implregX0: + return reg.X0 + } +} + +type sffx uint8 + +const ( + sffxNone sffx = iota + sffxBCST + sffxRD_SAE + sffxRN_SAE + sffxRU_SAE + sffxRZ_SAE + sffxSAE + sffxZ + sffxmax +) + +// maxsuffixes is the maximum number of suffixes an instruction can have. +const maxsuffixes = 2 + +type sffxs [maxsuffixes]sffx + +func (s sffxs) Strings() []string { + return sffxsstringsmap[s] +} + +var sffxsstringsmap = map[sffxs][]string{ + sffxs{sffxBCST, sffxZ}: []string{"BCST", "Z"}, + sffxs{sffxBCST}: []string{"BCST"}, + sffxs{sffxRD_SAE, sffxZ}: []string{"RD_SAE", "Z"}, + sffxs{sffxRD_SAE}: []string{"RD_SAE"}, + sffxs{sffxRN_SAE, sffxZ}: []string{"RN_SAE", "Z"}, + sffxs{sffxRN_SAE}: []string{"RN_SAE"}, + sffxs{sffxRU_SAE, sffxZ}: []string{"RU_SAE", "Z"}, + sffxs{sffxRU_SAE}: []string{"RU_SAE"}, + sffxs{sffxRZ_SAE, sffxZ}: []string{"RZ_SAE", "Z"}, + sffxs{sffxRZ_SAE}: []string{"RZ_SAE"}, + sffxs{sffxSAE, sffxZ}: []string{"SAE", "Z"}, + sffxs{sffxSAE}: []string{"SAE"}, + sffxs{sffxZ}: []string{"Z"}, + sffxs{}: []string(nil), +} + +type sffxscls uint8 + +const ( + sffxsclsNone sffxscls = iota + sffxsclsBCST + sffxsclsBCST_Z + sffxsclsER + sffxsclsER_Z + sffxsclsNIL + sffxsclsSAE + sffxsclsSAE_Z + sffxsclsZ + sffxsclsmax +) + +func (s sffxscls) SuffixesSet() map[sffxs]bool { + if sffxsclsNone < s && s < sffxsclsmax { + return sffxsclssuffixessettable[s-1] + } + return nil +} + +var sffxsclssuffixessettable = []map[sffxs]bool{ + {sffxs{sffxBCST}: true}, + {sffxs{sffxBCST, sffxZ}: true}, + {sffxs{sffxRD_SAE}: true, sffxs{sffxRN_SAE}: true, sffxs{sffxRU_SAE}: true, sffxs{sffxRZ_SAE}: true}, + {sffxs{sffxRD_SAE, sffxZ}: true, sffxs{sffxRN_SAE, sffxZ}: true, sffxs{sffxRU_SAE, sffxZ}: true, sffxs{sffxRZ_SAE, sffxZ}: true}, + {sffxs{}: true}, + {sffxs{sffxSAE}: true}, + {sffxs{sffxSAE, sffxZ}: true}, + {sffxs{sffxZ}: true}, +} + +type isas uint8 + +const ( + isasNone isas = iota + isasBase + isasADX + isasSSE2 + isasSSE + isasSSE3 + isasAES + isasBMI + isasSSE41 + isasBMI2 + isasCLFLUSH + isasCLFLUSHOPT + isasCMOV + isasCPUID + isasSSE42 + isasAVX512DQ + isasAVX512BW + isasAVX512F + isasLZCNT + isasMONITOR + isasMOVBE + isasSSSE3 + isasPCLMULQDQ + isasPOPCNT + isasMMX + isasRDRAND + isasRDSEED + isasRDTSC + isasRDTSCP + isasSHA + isasAVX + isasAVX512F_AVX512VL + isasAES_AVX + isasAVX512DQ_AVX512VL + isasAVX2 + isasF16C + isasAVX512VL + isasAVX512BW_AVX512VL + isasAVX512ER + isasFMA3 + isasAVX512CD_AVX512VL + isasAVX512CD + isasAVX_PCLMULQDQ + isasAVX512VBMI_AVX512VL + isasAVX512VBMI + isasAVX512IFMA_AVX512VL + isasAVX512IFMA + isasAVX512VPOPCNTDQ + isasAVX512BW_AVX512F + isasmax +) + +func (i isas) List() []string { + if isasNone < i && i < isasmax { + return isaslisttable[i-1] + } + return nil +} + +var isaslisttable = [][]string{ + []string(nil), + []string{"ADX"}, + []string{"SSE2"}, + []string{"SSE"}, + []string{"SSE3"}, + []string{"AES"}, + []string{"BMI"}, + []string{"SSE4.1"}, + []string{"BMI2"}, + []string{"CLFLUSH"}, + []string{"CLFLUSHOPT"}, + []string{"CMOV"}, + []string{"CPUID"}, + []string{"SSE4.2"}, + []string{"AVX512DQ"}, + []string{"AVX512BW"}, + []string{"AVX512F"}, + []string{"LZCNT"}, + []string{"MONITOR"}, + []string{"MOVBE"}, + []string{"SSSE3"}, + []string{"PCLMULQDQ"}, + []string{"POPCNT"}, + []string{"MMX+"}, + []string{"RDRAND"}, + []string{"RDSEED"}, + []string{"RDTSC"}, + []string{"RDTSCP"}, + []string{"SHA"}, + []string{"AVX"}, + []string{"AVX512F", "AVX512VL"}, + []string{"AES", "AVX"}, + []string{"AVX512DQ", "AVX512VL"}, + []string{"AVX2"}, + []string{"F16C"}, + []string{"AVX512VL"}, + []string{"AVX512BW", "AVX512VL"}, + []string{"AVX512ER"}, + []string{"FMA3"}, + []string{"AVX512CD", "AVX512VL"}, + []string{"AVX512CD"}, + []string{"AVX", "PCLMULQDQ"}, + []string{"AVX512VBMI", "AVX512VL"}, + []string{"AVX512VBMI"}, + []string{"AVX512IFMA", "AVX512VL"}, + []string{"AVX512IFMA"}, + []string{"AVX512VPOPCNTDQ"}, + []string{"AVX512BW", "AVX512F"}, +} + +type opc uint16 + +const ( + opcNone opc = iota + opcADCB + opcADCL + opcADCQ + opcADCW + opcADCXL + opcADCXQ + opcADDB + opcADDL + opcADDPD + opcADDPS + opcADDQ + opcADDSD + opcADDSS + opcADDSUBPD + opcADDSUBPS + opcADDW + opcADOXL + opcADOXQ + opcAESDEC + opcAESDECLAST + opcAESENC + opcAESENCLAST + opcAESIMC + opcAESKEYGENASSIST + opcANDB + opcANDL + opcANDNL + opcANDNPD + opcANDNPS + opcANDNQ + opcANDPD + opcANDPS + opcANDQ + opcANDW + opcBEXTRL + opcBEXTRQ + opcBLENDPD + opcBLENDPS + opcBLENDVPD + opcBLENDVPS + opcBLSIL + opcBLSIQ + opcBLSMSKL + opcBLSMSKQ + opcBLSRL + opcBLSRQ + opcBSFL + opcBSFQ + opcBSFW + opcBSRL + opcBSRQ + opcBSRW + opcBSWAPL + opcBSWAPQ + opcBTCL + opcBTCQ + opcBTCW + opcBTL + opcBTQ + opcBTRL + opcBTRQ + opcBTRW + opcBTSL + opcBTSQ + opcBTSW + opcBTW + opcBZHIL + opcBZHIQ + opcCALL + opcCBW + opcCDQ + opcCDQE + opcCLC + opcCLD + opcCLFLUSH + opcCLFLUSHOPT + opcCMC + opcCMOVLCC + opcCMOVLCS + opcCMOVLEQ + opcCMOVLGE + opcCMOVLGT + opcCMOVLHI + opcCMOVLLE + opcCMOVLLS + opcCMOVLLT + opcCMOVLMI + opcCMOVLNE + opcCMOVLOC + opcCMOVLOS + opcCMOVLPC + opcCMOVLPL + opcCMOVLPS + opcCMOVQCC + opcCMOVQCS + opcCMOVQEQ + opcCMOVQGE + opcCMOVQGT + opcCMOVQHI + opcCMOVQLE + opcCMOVQLS + opcCMOVQLT + opcCMOVQMI + opcCMOVQNE + opcCMOVQOC + opcCMOVQOS + opcCMOVQPC + opcCMOVQPL + opcCMOVQPS + opcCMOVWCC + opcCMOVWCS + opcCMOVWEQ + opcCMOVWGE + opcCMOVWGT + opcCMOVWHI + opcCMOVWLE + opcCMOVWLS + opcCMOVWLT + opcCMOVWMI + opcCMOVWNE + opcCMOVWOC + opcCMOVWOS + opcCMOVWPC + opcCMOVWPL + opcCMOVWPS + opcCMPB + opcCMPL + opcCMPPD + opcCMPPS + opcCMPQ + opcCMPSD + opcCMPSS + opcCMPW + opcCMPXCHG16B + opcCMPXCHG8B + opcCMPXCHGB + opcCMPXCHGL + opcCMPXCHGQ + opcCMPXCHGW + opcCOMISD + opcCOMISS + opcCPUID + opcCQO + opcCRC32B + opcCRC32L + opcCRC32Q + opcCRC32W + opcCVTPD2PL + opcCVTPD2PS + opcCVTPL2PD + opcCVTPL2PS + opcCVTPS2PD + opcCVTPS2PL + opcCVTSD2SL + opcCVTSD2SS + opcCVTSL2SD + opcCVTSL2SS + opcCVTSQ2SD + opcCVTSQ2SS + opcCVTSS2SD + opcCVTSS2SL + opcCVTTPD2PL + opcCVTTPS2PL + opcCVTTSD2SL + opcCVTTSD2SQ + opcCVTTSS2SL + opcCWD + opcCWDE + opcDECB + opcDECL + opcDECQ + opcDECW + opcDIVB + opcDIVL + opcDIVPD + opcDIVPS + opcDIVQ + opcDIVSD + opcDIVSS + opcDIVW + opcDPPD + opcDPPS + opcEXTRACTPS + opcHADDPD + opcHADDPS + opcHSUBPD + opcHSUBPS + opcIDIVB + opcIDIVL + opcIDIVQ + opcIDIVW + opcIMUL3L + opcIMUL3Q + opcIMUL3W + opcIMULB + opcIMULL + opcIMULQ + opcIMULW + opcINCB + opcINCL + opcINCQ + opcINCW + opcINSERTPS + opcINT + opcJA + opcJAE + opcJB + opcJBE + opcJC + opcJCC + opcJCS + opcJCXZL + opcJCXZQ + opcJE + opcJEQ + opcJG + opcJGE + opcJGT + opcJHI + opcJHS + opcJL + opcJLE + opcJLO + opcJLS + opcJLT + opcJMI + opcJMP + opcJNA + opcJNAE + opcJNB + opcJNBE + opcJNC + opcJNE + opcJNG + opcJNGE + opcJNL + opcJNLE + opcJNO + opcJNP + opcJNS + opcJNZ + opcJO + opcJOC + opcJOS + opcJP + opcJPC + opcJPE + opcJPL + opcJPO + opcJPS + opcJS + opcJZ + opcKADDB + opcKADDD + opcKADDQ + opcKADDW + opcKANDB + opcKANDD + opcKANDNB + opcKANDND + opcKANDNQ + opcKANDNW + opcKANDQ + opcKANDW + opcKMOVB + opcKMOVD + opcKMOVQ + opcKMOVW + opcKNOTB + opcKNOTD + opcKNOTQ + opcKNOTW + opcKORB + opcKORD + opcKORQ + opcKORTESTB + opcKORTESTD + opcKORTESTQ + opcKORTESTW + opcKORW + opcKSHIFTLB + opcKSHIFTLD + opcKSHIFTLQ + opcKSHIFTLW + opcKSHIFTRB + opcKSHIFTRD + opcKSHIFTRQ + opcKSHIFTRW + opcKTESTB + opcKTESTD + opcKTESTQ + opcKTESTW + opcKUNPCKBW + opcKUNPCKDQ + opcKUNPCKWD + opcKXNORB + opcKXNORD + opcKXNORQ + opcKXNORW + opcKXORB + opcKXORD + opcKXORQ + opcKXORW + opcLDDQU + opcLDMXCSR + opcLEAL + opcLEAQ + opcLEAW + opcLFENCE + opcLZCNTL + opcLZCNTQ + opcLZCNTW + opcMASKMOVDQU + opcMASKMOVOU + opcMAXPD + opcMAXPS + opcMAXSD + opcMAXSS + opcMFENCE + opcMINPD + opcMINPS + opcMINSD + opcMINSS + opcMONITOR + opcMOVAPD + opcMOVAPS + opcMOVB + opcMOVBELL + opcMOVBEQQ + opcMOVBEWW + opcMOVBLSX + opcMOVBLZX + opcMOVBQSX + opcMOVBQZX + opcMOVBWSX + opcMOVBWZX + opcMOVD + opcMOVDDUP + opcMOVDQ2Q + opcMOVHLPS + opcMOVHPD + opcMOVHPS + opcMOVL + opcMOVLHPS + opcMOVLPD + opcMOVLPS + opcMOVLQSX + opcMOVLQZX + opcMOVMSKPD + opcMOVMSKPS + opcMOVNTDQ + opcMOVNTDQA + opcMOVNTIL + opcMOVNTIQ + opcMOVNTO + opcMOVNTPD + opcMOVNTPS + opcMOVO + opcMOVOA + opcMOVOU + opcMOVQ + opcMOVSD + opcMOVSHDUP + opcMOVSLDUP + opcMOVSS + opcMOVUPD + opcMOVUPS + opcMOVW + opcMOVWLSX + opcMOVWLZX + opcMOVWQSX + opcMOVWQZX + opcMPSADBW + opcMULB + opcMULL + opcMULPD + opcMULPS + opcMULQ + opcMULSD + opcMULSS + opcMULW + opcMULXL + opcMULXQ + opcMWAIT + opcNEGB + opcNEGL + opcNEGQ + opcNEGW + opcNOP + opcNOTB + opcNOTL + opcNOTQ + opcNOTW + opcORB + opcORL + opcORPD + opcORPS + opcORQ + opcORW + opcPABSB + opcPABSD + opcPABSW + opcPACKSSLW + opcPACKSSWB + opcPACKUSDW + opcPACKUSWB + opcPADDB + opcPADDD + opcPADDL + opcPADDQ + opcPADDSB + opcPADDSW + opcPADDUSB + opcPADDUSW + opcPADDW + opcPALIGNR + opcPAND + opcPANDN + opcPAUSE + opcPAVGB + opcPAVGW + opcPBLENDVB + opcPBLENDW + opcPCLMULQDQ + opcPCMPEQB + opcPCMPEQL + opcPCMPEQQ + opcPCMPEQW + opcPCMPESTRI + opcPCMPESTRM + opcPCMPGTB + opcPCMPGTL + opcPCMPGTQ + opcPCMPGTW + opcPCMPISTRI + opcPCMPISTRM + opcPDEPL + opcPDEPQ + opcPEXTL + opcPEXTQ + opcPEXTRB + opcPEXTRD + opcPEXTRQ + opcPEXTRW + opcPHADDD + opcPHADDSW + opcPHADDW + opcPHMINPOSUW + opcPHSUBD + opcPHSUBSW + opcPHSUBW + opcPINSRB + opcPINSRD + opcPINSRQ + opcPINSRW + opcPMADDUBSW + opcPMADDWL + opcPMAXSB + opcPMAXSD + opcPMAXSW + opcPMAXUB + opcPMAXUD + opcPMAXUW + opcPMINSB + opcPMINSD + opcPMINSW + opcPMINUB + opcPMINUD + opcPMINUW + opcPMOVMSKB + opcPMOVSXBD + opcPMOVSXBQ + opcPMOVSXBW + opcPMOVSXDQ + opcPMOVSXWD + opcPMOVSXWQ + opcPMOVZXBD + opcPMOVZXBQ + opcPMOVZXBW + opcPMOVZXDQ + opcPMOVZXWD + opcPMOVZXWQ + opcPMULDQ + opcPMULHRSW + opcPMULHUW + opcPMULHW + opcPMULLD + opcPMULLW + opcPMULULQ + opcPOPCNTL + opcPOPCNTQ + opcPOPCNTW + opcPOPQ + opcPOPW + opcPOR + opcPREFETCHNTA + opcPREFETCHT0 + opcPREFETCHT1 + opcPREFETCHT2 + opcPSADBW + opcPSHUFB + opcPSHUFD + opcPSHUFHW + opcPSHUFL + opcPSHUFLW + opcPSIGNB + opcPSIGND + opcPSIGNW + opcPSLLDQ + opcPSLLL + opcPSLLO + opcPSLLQ + opcPSLLW + opcPSRAL + opcPSRAW + opcPSRLDQ + opcPSRLL + opcPSRLO + opcPSRLQ + opcPSRLW + opcPSUBB + opcPSUBL + opcPSUBQ + opcPSUBSB + opcPSUBSW + opcPSUBUSB + opcPSUBUSW + opcPSUBW + opcPTEST + opcPUNPCKHBW + opcPUNPCKHLQ + opcPUNPCKHQDQ + opcPUNPCKHWL + opcPUNPCKLBW + opcPUNPCKLLQ + opcPUNPCKLQDQ + opcPUNPCKLWL + opcPUSHQ + opcPUSHW + opcPXOR + opcRCLB + opcRCLL + opcRCLQ + opcRCLW + opcRCPPS + opcRCPSS + opcRCRB + opcRCRL + opcRCRQ + opcRCRW + opcRDRANDL + opcRDSEEDL + opcRDTSC + opcRDTSCP + opcRET + opcRETFL + opcRETFQ + opcRETFW + opcROLB + opcROLL + opcROLQ + opcROLW + opcRORB + opcRORL + opcRORQ + opcRORW + opcRORXL + opcRORXQ + opcROUNDPD + opcROUNDPS + opcROUNDSD + opcROUNDSS + opcRSQRTPS + opcRSQRTSS + opcSALB + opcSALL + opcSALQ + opcSALW + opcSARB + opcSARL + opcSARQ + opcSARW + opcSARXL + opcSARXQ + opcSBBB + opcSBBL + opcSBBQ + opcSBBW + opcSETCC + opcSETCS + opcSETEQ + opcSETGE + opcSETGT + opcSETHI + opcSETLE + opcSETLS + opcSETLT + opcSETMI + opcSETNE + opcSETOC + opcSETOS + opcSETPC + opcSETPL + opcSETPS + opcSFENCE + opcSHA1MSG1 + opcSHA1MSG2 + opcSHA1NEXTE + opcSHA1RNDS4 + opcSHA256MSG1 + opcSHA256MSG2 + opcSHA256RNDS2 + opcSHLB + opcSHLL + opcSHLQ + opcSHLW + opcSHLXL + opcSHLXQ + opcSHRB + opcSHRL + opcSHRQ + opcSHRW + opcSHRXL + opcSHRXQ + opcSHUFPD + opcSHUFPS + opcSQRTPD + opcSQRTPS + opcSQRTSD + opcSQRTSS + opcSTC + opcSTD + opcSTMXCSR + opcSUBB + opcSUBL + opcSUBPD + opcSUBPS + opcSUBQ + opcSUBSD + opcSUBSS + opcSUBW + opcSYSCALL + opcTESTB + opcTESTL + opcTESTQ + opcTESTW + opcTZCNTL + opcTZCNTQ + opcTZCNTW + opcUCOMISD + opcUCOMISS + opcUD2 + opcUNPCKHPD + opcUNPCKHPS + opcUNPCKLPD + opcUNPCKLPS + opcVADDPD + opcVADDPS + opcVADDSD + opcVADDSS + opcVADDSUBPD + opcVADDSUBPS + opcVAESDEC + opcVAESDECLAST + opcVAESENC + opcVAESENCLAST + opcVAESIMC + opcVAESKEYGENASSIST + opcVALIGND + opcVALIGNQ + opcVANDNPD + opcVANDNPS + opcVANDPD + opcVANDPS + opcVBLENDMPD + opcVBLENDMPS + opcVBLENDPD + opcVBLENDPS + opcVBLENDVPD + opcVBLENDVPS + opcVBROADCASTF128 + opcVBROADCASTF32X2 + opcVBROADCASTF32X4 + opcVBROADCASTF32X8 + opcVBROADCASTF64X2 + opcVBROADCASTF64X4 + opcVBROADCASTI128 + opcVBROADCASTI32X2 + opcVBROADCASTI32X4 + opcVBROADCASTI32X8 + opcVBROADCASTI64X2 + opcVBROADCASTI64X4 + opcVBROADCASTSD + opcVBROADCASTSS + opcVCMPPD + opcVCMPPS + opcVCMPSD + opcVCMPSS + opcVCOMISD + opcVCOMISS + opcVCOMPRESSPD + opcVCOMPRESSPS + opcVCVTDQ2PD + opcVCVTDQ2PS + opcVCVTPD2DQ + opcVCVTPD2DQX + opcVCVTPD2DQY + opcVCVTPD2PS + opcVCVTPD2PSX + opcVCVTPD2PSY + opcVCVTPD2QQ + opcVCVTPD2UDQ + opcVCVTPD2UDQX + opcVCVTPD2UDQY + opcVCVTPD2UQQ + opcVCVTPH2PS + opcVCVTPS2DQ + opcVCVTPS2PD + opcVCVTPS2PH + opcVCVTPS2QQ + opcVCVTPS2UDQ + opcVCVTPS2UQQ + opcVCVTQQ2PD + opcVCVTQQ2PS + opcVCVTQQ2PSX + opcVCVTQQ2PSY + opcVCVTSD2SI + opcVCVTSD2SIQ + opcVCVTSD2SS + opcVCVTSD2USIL + opcVCVTSD2USIQ + opcVCVTSI2SDL + opcVCVTSI2SDQ + opcVCVTSI2SSL + opcVCVTSI2SSQ + opcVCVTSS2SD + opcVCVTSS2SI + opcVCVTSS2SIQ + opcVCVTSS2USIL + opcVCVTSS2USIQ + opcVCVTTPD2DQ + opcVCVTTPD2DQX + opcVCVTTPD2DQY + opcVCVTTPD2QQ + opcVCVTTPD2UDQ + opcVCVTTPD2UDQX + opcVCVTTPD2UDQY + opcVCVTTPD2UQQ + opcVCVTTPS2DQ + opcVCVTTPS2QQ + opcVCVTTPS2UDQ + opcVCVTTPS2UQQ + opcVCVTTSD2SI + opcVCVTTSD2SIQ + opcVCVTTSD2USIL + opcVCVTTSD2USIQ + opcVCVTTSS2SI + opcVCVTTSS2SIQ + opcVCVTTSS2USIL + opcVCVTTSS2USIQ + opcVCVTUDQ2PD + opcVCVTUDQ2PS + opcVCVTUQQ2PD + opcVCVTUQQ2PS + opcVCVTUQQ2PSX + opcVCVTUQQ2PSY + opcVCVTUSI2SDL + opcVCVTUSI2SDQ + opcVCVTUSI2SSL + opcVCVTUSI2SSQ + opcVDBPSADBW + opcVDIVPD + opcVDIVPS + opcVDIVSD + opcVDIVSS + opcVDPPD + opcVDPPS + opcVEXP2PD + opcVEXP2PS + opcVEXPANDPD + opcVEXPANDPS + opcVEXTRACTF128 + opcVEXTRACTF32X4 + opcVEXTRACTF32X8 + opcVEXTRACTF64X2 + opcVEXTRACTF64X4 + opcVEXTRACTI128 + opcVEXTRACTI32X4 + opcVEXTRACTI32X8 + opcVEXTRACTI64X2 + opcVEXTRACTI64X4 + opcVEXTRACTPS + opcVFIXUPIMMPD + opcVFIXUPIMMPS + opcVFIXUPIMMSD + opcVFIXUPIMMSS + opcVFMADD132PD + opcVFMADD132PS + opcVFMADD132SD + opcVFMADD132SS + opcVFMADD213PD + opcVFMADD213PS + opcVFMADD213SD + opcVFMADD213SS + opcVFMADD231PD + opcVFMADD231PS + opcVFMADD231SD + opcVFMADD231SS + opcVFMADDSUB132PD + opcVFMADDSUB132PS + opcVFMADDSUB213PD + opcVFMADDSUB213PS + opcVFMADDSUB231PD + opcVFMADDSUB231PS + opcVFMSUB132PD + opcVFMSUB132PS + opcVFMSUB132SD + opcVFMSUB132SS + opcVFMSUB213PD + opcVFMSUB213PS + opcVFMSUB213SD + opcVFMSUB213SS + opcVFMSUB231PD + opcVFMSUB231PS + opcVFMSUB231SD + opcVFMSUB231SS + opcVFMSUBADD132PD + opcVFMSUBADD132PS + opcVFMSUBADD213PD + opcVFMSUBADD213PS + opcVFMSUBADD231PD + opcVFMSUBADD231PS + opcVFNMADD132PD + opcVFNMADD132PS + opcVFNMADD132SD + opcVFNMADD132SS + opcVFNMADD213PD + opcVFNMADD213PS + opcVFNMADD213SD + opcVFNMADD213SS + opcVFNMADD231PD + opcVFNMADD231PS + opcVFNMADD231SD + opcVFNMADD231SS + opcVFNMSUB132PD + opcVFNMSUB132PS + opcVFNMSUB132SD + opcVFNMSUB132SS + opcVFNMSUB213PD + opcVFNMSUB213PS + opcVFNMSUB213SD + opcVFNMSUB213SS + opcVFNMSUB231PD + opcVFNMSUB231PS + opcVFNMSUB231SD + opcVFNMSUB231SS + opcVFPCLASSPDX + opcVFPCLASSPDY + opcVFPCLASSPDZ + opcVFPCLASSPSX + opcVFPCLASSPSY + opcVFPCLASSPSZ + opcVFPCLASSSD + opcVFPCLASSSS + opcVGATHERDPD + opcVGATHERDPS + opcVGATHERQPD + opcVGATHERQPS + opcVGETEXPPD + opcVGETEXPPS + opcVGETEXPSD + opcVGETEXPSS + opcVGETMANTPD + opcVGETMANTPS + opcVGETMANTSD + opcVGETMANTSS + opcVHADDPD + opcVHADDPS + opcVHSUBPD + opcVHSUBPS + opcVINSERTF128 + opcVINSERTF32X4 + opcVINSERTF32X8 + opcVINSERTF64X2 + opcVINSERTF64X4 + opcVINSERTI128 + opcVINSERTI32X4 + opcVINSERTI32X8 + opcVINSERTI64X2 + opcVINSERTI64X4 + opcVINSERTPS + opcVLDDQU + opcVLDMXCSR + opcVMASKMOVDQU + opcVMASKMOVPD + opcVMASKMOVPS + opcVMAXPD + opcVMAXPS + opcVMAXSD + opcVMAXSS + opcVMINPD + opcVMINPS + opcVMINSD + opcVMINSS + opcVMOVAPD + opcVMOVAPS + opcVMOVD + opcVMOVDDUP + opcVMOVDQA + opcVMOVDQA32 + opcVMOVDQA64 + opcVMOVDQU + opcVMOVDQU16 + opcVMOVDQU32 + opcVMOVDQU64 + opcVMOVDQU8 + opcVMOVHLPS + opcVMOVHPD + opcVMOVHPS + opcVMOVLHPS + opcVMOVLPD + opcVMOVLPS + opcVMOVMSKPD + opcVMOVMSKPS + opcVMOVNTDQ + opcVMOVNTDQA + opcVMOVNTPD + opcVMOVNTPS + opcVMOVQ + opcVMOVSD + opcVMOVSHDUP + opcVMOVSLDUP + opcVMOVSS + opcVMOVUPD + opcVMOVUPS + opcVMPSADBW + opcVMULPD + opcVMULPS + opcVMULSD + opcVMULSS + opcVORPD + opcVORPS + opcVPABSB + opcVPABSD + opcVPABSQ + opcVPABSW + opcVPACKSSDW + opcVPACKSSWB + opcVPACKUSDW + opcVPACKUSWB + opcVPADDB + opcVPADDD + opcVPADDQ + opcVPADDSB + opcVPADDSW + opcVPADDUSB + opcVPADDUSW + opcVPADDW + opcVPALIGNR + opcVPAND + opcVPANDD + opcVPANDN + opcVPANDND + opcVPANDNQ + opcVPANDQ + opcVPAVGB + opcVPAVGW + opcVPBLENDD + opcVPBLENDMB + opcVPBLENDMD + opcVPBLENDMQ + opcVPBLENDMW + opcVPBLENDVB + opcVPBLENDW + opcVPBROADCASTB + opcVPBROADCASTD + opcVPBROADCASTMB2Q + opcVPBROADCASTMW2D + opcVPBROADCASTQ + opcVPBROADCASTW + opcVPCLMULQDQ + opcVPCMPB + opcVPCMPD + opcVPCMPEQB + opcVPCMPEQD + opcVPCMPEQQ + opcVPCMPEQW + opcVPCMPESTRI + opcVPCMPESTRM + opcVPCMPGTB + opcVPCMPGTD + opcVPCMPGTQ + opcVPCMPGTW + opcVPCMPISTRI + opcVPCMPISTRM + opcVPCMPQ + opcVPCMPUB + opcVPCMPUD + opcVPCMPUQ + opcVPCMPUW + opcVPCMPW + opcVPCOMPRESSD + opcVPCOMPRESSQ + opcVPCONFLICTD + opcVPCONFLICTQ + opcVPERM2F128 + opcVPERM2I128 + opcVPERMB + opcVPERMD + opcVPERMI2B + opcVPERMI2D + opcVPERMI2PD + opcVPERMI2PS + opcVPERMI2Q + opcVPERMI2W + opcVPERMILPD + opcVPERMILPS + opcVPERMPD + opcVPERMPS + opcVPERMQ + opcVPERMT2B + opcVPERMT2D + opcVPERMT2PD + opcVPERMT2PS + opcVPERMT2Q + opcVPERMT2W + opcVPERMW + opcVPEXPANDD + opcVPEXPANDQ + opcVPEXTRB + opcVPEXTRD + opcVPEXTRQ + opcVPEXTRW + opcVPGATHERDD + opcVPGATHERDQ + opcVPGATHERQD + opcVPGATHERQQ + opcVPHADDD + opcVPHADDSW + opcVPHADDW + opcVPHMINPOSUW + opcVPHSUBD + opcVPHSUBSW + opcVPHSUBW + opcVPINSRB + opcVPINSRD + opcVPINSRQ + opcVPINSRW + opcVPLZCNTD + opcVPLZCNTQ + opcVPMADD52HUQ + opcVPMADD52LUQ + opcVPMADDUBSW + opcVPMADDWD + opcVPMASKMOVD + opcVPMASKMOVQ + opcVPMAXSB + opcVPMAXSD + opcVPMAXSQ + opcVPMAXSW + opcVPMAXUB + opcVPMAXUD + opcVPMAXUQ + opcVPMAXUW + opcVPMINSB + opcVPMINSD + opcVPMINSQ + opcVPMINSW + opcVPMINUB + opcVPMINUD + opcVPMINUQ + opcVPMINUW + opcVPMOVB2M + opcVPMOVD2M + opcVPMOVDB + opcVPMOVDW + opcVPMOVM2B + opcVPMOVM2D + opcVPMOVM2Q + opcVPMOVM2W + opcVPMOVMSKB + opcVPMOVQ2M + opcVPMOVQB + opcVPMOVQD + opcVPMOVQW + opcVPMOVSDB + opcVPMOVSDW + opcVPMOVSQB + opcVPMOVSQD + opcVPMOVSQW + opcVPMOVSWB + opcVPMOVSXBD + opcVPMOVSXBQ + opcVPMOVSXBW + opcVPMOVSXDQ + opcVPMOVSXWD + opcVPMOVSXWQ + opcVPMOVUSDB + opcVPMOVUSDW + opcVPMOVUSQB + opcVPMOVUSQD + opcVPMOVUSQW + opcVPMOVUSWB + opcVPMOVW2M + opcVPMOVWB + opcVPMOVZXBD + opcVPMOVZXBQ + opcVPMOVZXBW + opcVPMOVZXDQ + opcVPMOVZXWD + opcVPMOVZXWQ + opcVPMULDQ + opcVPMULHRSW + opcVPMULHUW + opcVPMULHW + opcVPMULLD + opcVPMULLQ + opcVPMULLW + opcVPMULTISHIFTQB + opcVPMULUDQ + opcVPOPCNTD + opcVPOPCNTQ + opcVPOR + opcVPORD + opcVPORQ + opcVPROLD + opcVPROLQ + opcVPROLVD + opcVPROLVQ + opcVPRORD + opcVPRORQ + opcVPRORVD + opcVPRORVQ + opcVPSADBW + opcVPSCATTERDD + opcVPSCATTERDQ + opcVPSCATTERQD + opcVPSCATTERQQ + opcVPSHUFB + opcVPSHUFD + opcVPSHUFHW + opcVPSHUFLW + opcVPSIGNB + opcVPSIGND + opcVPSIGNW + opcVPSLLD + opcVPSLLDQ + opcVPSLLQ + opcVPSLLVD + opcVPSLLVQ + opcVPSLLVW + opcVPSLLW + opcVPSRAD + opcVPSRAQ + opcVPSRAVD + opcVPSRAVQ + opcVPSRAVW + opcVPSRAW + opcVPSRLD + opcVPSRLDQ + opcVPSRLQ + opcVPSRLVD + opcVPSRLVQ + opcVPSRLVW + opcVPSRLW + opcVPSUBB + opcVPSUBD + opcVPSUBQ + opcVPSUBSB + opcVPSUBSW + opcVPSUBUSB + opcVPSUBUSW + opcVPSUBW + opcVPTERNLOGD + opcVPTERNLOGQ + opcVPTEST + opcVPTESTMB + opcVPTESTMD + opcVPTESTMQ + opcVPTESTMW + opcVPTESTNMB + opcVPTESTNMD + opcVPTESTNMQ + opcVPTESTNMW + opcVPUNPCKHBW + opcVPUNPCKHDQ + opcVPUNPCKHQDQ + opcVPUNPCKHWD + opcVPUNPCKLBW + opcVPUNPCKLDQ + opcVPUNPCKLQDQ + opcVPUNPCKLWD + opcVPXOR + opcVPXORD + opcVPXORQ + opcVRANGEPD + opcVRANGEPS + opcVRANGESD + opcVRANGESS + opcVRCP14PD + opcVRCP14PS + opcVRCP14SD + opcVRCP14SS + opcVRCP28PD + opcVRCP28PS + opcVRCP28SD + opcVRCP28SS + opcVRCPPS + opcVRCPSS + opcVREDUCEPD + opcVREDUCEPS + opcVREDUCESD + opcVREDUCESS + opcVRNDSCALEPD + opcVRNDSCALEPS + opcVRNDSCALESD + opcVRNDSCALESS + opcVROUNDPD + opcVROUNDPS + opcVROUNDSD + opcVROUNDSS + opcVRSQRT14PD + opcVRSQRT14PS + opcVRSQRT14SD + opcVRSQRT14SS + opcVRSQRT28PD + opcVRSQRT28PS + opcVRSQRT28SD + opcVRSQRT28SS + opcVRSQRTPS + opcVRSQRTSS + opcVSCALEFPD + opcVSCALEFPS + opcVSCALEFSD + opcVSCALEFSS + opcVSCATTERDPD + opcVSCATTERDPS + opcVSCATTERQPD + opcVSCATTERQPS + opcVSHUFF32X4 + opcVSHUFF64X2 + opcVSHUFI32X4 + opcVSHUFI64X2 + opcVSHUFPD + opcVSHUFPS + opcVSQRTPD + opcVSQRTPS + opcVSQRTSD + opcVSQRTSS + opcVSTMXCSR + opcVSUBPD + opcVSUBPS + opcVSUBSD + opcVSUBSS + opcVTESTPD + opcVTESTPS + opcVUCOMISD + opcVUCOMISS + opcVUNPCKHPD + opcVUNPCKHPS + opcVUNPCKLPD + opcVUNPCKLPS + opcVXORPD + opcVXORPS + opcVZEROALL + opcVZEROUPPER + opcXADDB + opcXADDL + opcXADDQ + opcXADDW + opcXCHGB + opcXCHGL + opcXCHGQ + opcXCHGW + opcXGETBV + opcXLAT + opcXORB + opcXORL + opcXORPD + opcXORPS + opcXORQ + opcXORW + opcmax +) + +func (o opc) String() string { + if opcNone < o && o < opcmax { + return opcstringtable[o-1] + } + return "" +} + +var opcstringtable = []string{ + "ADCB", + "ADCL", + "ADCQ", + "ADCW", + "ADCXL", + "ADCXQ", + "ADDB", + "ADDL", + "ADDPD", + "ADDPS", + "ADDQ", + "ADDSD", + "ADDSS", + "ADDSUBPD", + "ADDSUBPS", + "ADDW", + "ADOXL", + "ADOXQ", + "AESDEC", + "AESDECLAST", + "AESENC", + "AESENCLAST", + "AESIMC", + "AESKEYGENASSIST", + "ANDB", + "ANDL", + "ANDNL", + "ANDNPD", + "ANDNPS", + "ANDNQ", + "ANDPD", + "ANDPS", + "ANDQ", + "ANDW", + "BEXTRL", + "BEXTRQ", + "BLENDPD", + "BLENDPS", + "BLENDVPD", + "BLENDVPS", + "BLSIL", + "BLSIQ", + "BLSMSKL", + "BLSMSKQ", + "BLSRL", + "BLSRQ", + "BSFL", + "BSFQ", + "BSFW", + "BSRL", + "BSRQ", + "BSRW", + "BSWAPL", + "BSWAPQ", + "BTCL", + "BTCQ", + "BTCW", + "BTL", + "BTQ", + "BTRL", + "BTRQ", + "BTRW", + "BTSL", + "BTSQ", + "BTSW", + "BTW", + "BZHIL", + "BZHIQ", + "CALL", + "CBW", + "CDQ", + "CDQE", + "CLC", + "CLD", + "CLFLUSH", + "CLFLUSHOPT", + "CMC", + "CMOVLCC", + "CMOVLCS", + "CMOVLEQ", + "CMOVLGE", + "CMOVLGT", + "CMOVLHI", + "CMOVLLE", + "CMOVLLS", + "CMOVLLT", + "CMOVLMI", + "CMOVLNE", + "CMOVLOC", + "CMOVLOS", + "CMOVLPC", + "CMOVLPL", + "CMOVLPS", + "CMOVQCC", + "CMOVQCS", + "CMOVQEQ", + "CMOVQGE", + "CMOVQGT", + "CMOVQHI", + "CMOVQLE", + "CMOVQLS", + "CMOVQLT", + "CMOVQMI", + "CMOVQNE", + "CMOVQOC", + "CMOVQOS", + "CMOVQPC", + "CMOVQPL", + "CMOVQPS", + "CMOVWCC", + "CMOVWCS", + "CMOVWEQ", + "CMOVWGE", + "CMOVWGT", + "CMOVWHI", + "CMOVWLE", + "CMOVWLS", + "CMOVWLT", + "CMOVWMI", + "CMOVWNE", + "CMOVWOC", + "CMOVWOS", + "CMOVWPC", + "CMOVWPL", + "CMOVWPS", + "CMPB", + "CMPL", + "CMPPD", + "CMPPS", + "CMPQ", + "CMPSD", + "CMPSS", + "CMPW", + "CMPXCHG16B", + "CMPXCHG8B", + "CMPXCHGB", + "CMPXCHGL", + "CMPXCHGQ", + "CMPXCHGW", + "COMISD", + "COMISS", + "CPUID", + "CQO", + "CRC32B", + "CRC32L", + "CRC32Q", + "CRC32W", + "CVTPD2PL", + "CVTPD2PS", + "CVTPL2PD", + "CVTPL2PS", + "CVTPS2PD", + "CVTPS2PL", + "CVTSD2SL", + "CVTSD2SS", + "CVTSL2SD", + "CVTSL2SS", + "CVTSQ2SD", + "CVTSQ2SS", + "CVTSS2SD", + "CVTSS2SL", + "CVTTPD2PL", + "CVTTPS2PL", + "CVTTSD2SL", + "CVTTSD2SQ", + "CVTTSS2SL", + "CWD", + "CWDE", + "DECB", + "DECL", + "DECQ", + "DECW", + "DIVB", + "DIVL", + "DIVPD", + "DIVPS", + "DIVQ", + "DIVSD", + "DIVSS", + "DIVW", + "DPPD", + "DPPS", + "EXTRACTPS", + "HADDPD", + "HADDPS", + "HSUBPD", + "HSUBPS", + "IDIVB", + "IDIVL", + "IDIVQ", + "IDIVW", + "IMUL3L", + "IMUL3Q", + "IMUL3W", + "IMULB", + "IMULL", + "IMULQ", + "IMULW", + "INCB", + "INCL", + "INCQ", + "INCW", + "INSERTPS", + "INT", + "JA", + "JAE", + "JB", + "JBE", + "JC", + "JCC", + "JCS", + "JCXZL", + "JCXZQ", + "JE", + "JEQ", + "JG", + "JGE", + "JGT", + "JHI", + "JHS", + "JL", + "JLE", + "JLO", + "JLS", + "JLT", + "JMI", + "JMP", + "JNA", + "JNAE", + "JNB", + "JNBE", + "JNC", + "JNE", + "JNG", + "JNGE", + "JNL", + "JNLE", + "JNO", + "JNP", + "JNS", + "JNZ", + "JO", + "JOC", + "JOS", + "JP", + "JPC", + "JPE", + "JPL", + "JPO", + "JPS", + "JS", + "JZ", + "KADDB", + "KADDD", + "KADDQ", + "KADDW", + "KANDB", + "KANDD", + "KANDNB", + "KANDND", + "KANDNQ", + "KANDNW", + "KANDQ", + "KANDW", + "KMOVB", + "KMOVD", + "KMOVQ", + "KMOVW", + "KNOTB", + "KNOTD", + "KNOTQ", + "KNOTW", + "KORB", + "KORD", + "KORQ", + "KORTESTB", + "KORTESTD", + "KORTESTQ", + "KORTESTW", + "KORW", + "KSHIFTLB", + "KSHIFTLD", + "KSHIFTLQ", + "KSHIFTLW", + "KSHIFTRB", + "KSHIFTRD", + "KSHIFTRQ", + "KSHIFTRW", + "KTESTB", + "KTESTD", + "KTESTQ", + "KTESTW", + "KUNPCKBW", + "KUNPCKDQ", + "KUNPCKWD", + "KXNORB", + "KXNORD", + "KXNORQ", + "KXNORW", + "KXORB", + "KXORD", + "KXORQ", + "KXORW", + "LDDQU", + "LDMXCSR", + "LEAL", + "LEAQ", + "LEAW", + "LFENCE", + "LZCNTL", + "LZCNTQ", + "LZCNTW", + "MASKMOVDQU", + "MASKMOVOU", + "MAXPD", + "MAXPS", + "MAXSD", + "MAXSS", + "MFENCE", + "MINPD", + "MINPS", + "MINSD", + "MINSS", + "MONITOR", + "MOVAPD", + "MOVAPS", + "MOVB", + "MOVBELL", + "MOVBEQQ", + "MOVBEWW", + "MOVBLSX", + "MOVBLZX", + "MOVBQSX", + "MOVBQZX", + "MOVBWSX", + "MOVBWZX", + "MOVD", + "MOVDDUP", + "MOVDQ2Q", + "MOVHLPS", + "MOVHPD", + "MOVHPS", + "MOVL", + "MOVLHPS", + "MOVLPD", + "MOVLPS", + "MOVLQSX", + "MOVLQZX", + "MOVMSKPD", + "MOVMSKPS", + "MOVNTDQ", + "MOVNTDQA", + "MOVNTIL", + "MOVNTIQ", + "MOVNTO", + "MOVNTPD", + "MOVNTPS", + "MOVO", + "MOVOA", + "MOVOU", + "MOVQ", + "MOVSD", + "MOVSHDUP", + "MOVSLDUP", + "MOVSS", + "MOVUPD", + "MOVUPS", + "MOVW", + "MOVWLSX", + "MOVWLZX", + "MOVWQSX", + "MOVWQZX", + "MPSADBW", + "MULB", + "MULL", + "MULPD", + "MULPS", + "MULQ", + "MULSD", + "MULSS", + "MULW", + "MULXL", + "MULXQ", + "MWAIT", + "NEGB", + "NEGL", + "NEGQ", + "NEGW", + "NOP", + "NOTB", + "NOTL", + "NOTQ", + "NOTW", + "ORB", + "ORL", + "ORPD", + "ORPS", + "ORQ", + "ORW", + "PABSB", + "PABSD", + "PABSW", + "PACKSSLW", + "PACKSSWB", + "PACKUSDW", + "PACKUSWB", + "PADDB", + "PADDD", + "PADDL", + "PADDQ", + "PADDSB", + "PADDSW", + "PADDUSB", + "PADDUSW", + "PADDW", + "PALIGNR", + "PAND", + "PANDN", + "PAUSE", + "PAVGB", + "PAVGW", + "PBLENDVB", + "PBLENDW", + "PCLMULQDQ", + "PCMPEQB", + "PCMPEQL", + "PCMPEQQ", + "PCMPEQW", + "PCMPESTRI", + "PCMPESTRM", + "PCMPGTB", + "PCMPGTL", + "PCMPGTQ", + "PCMPGTW", + "PCMPISTRI", + "PCMPISTRM", + "PDEPL", + "PDEPQ", + "PEXTL", + "PEXTQ", + "PEXTRB", + "PEXTRD", + "PEXTRQ", + "PEXTRW", + "PHADDD", + "PHADDSW", + "PHADDW", + "PHMINPOSUW", + "PHSUBD", + "PHSUBSW", + "PHSUBW", + "PINSRB", + "PINSRD", + "PINSRQ", + "PINSRW", + "PMADDUBSW", + "PMADDWL", + "PMAXSB", + "PMAXSD", + "PMAXSW", + "PMAXUB", + "PMAXUD", + "PMAXUW", + "PMINSB", + "PMINSD", + "PMINSW", + "PMINUB", + "PMINUD", + "PMINUW", + "PMOVMSKB", + "PMOVSXBD", + "PMOVSXBQ", + "PMOVSXBW", + "PMOVSXDQ", + "PMOVSXWD", + "PMOVSXWQ", + "PMOVZXBD", + "PMOVZXBQ", + "PMOVZXBW", + "PMOVZXDQ", + "PMOVZXWD", + "PMOVZXWQ", + "PMULDQ", + "PMULHRSW", + "PMULHUW", + "PMULHW", + "PMULLD", + "PMULLW", + "PMULULQ", + "POPCNTL", + "POPCNTQ", + "POPCNTW", + "POPQ", + "POPW", + "POR", + "PREFETCHNTA", + "PREFETCHT0", + "PREFETCHT1", + "PREFETCHT2", + "PSADBW", + "PSHUFB", + "PSHUFD", + "PSHUFHW", + "PSHUFL", + "PSHUFLW", + "PSIGNB", + "PSIGND", + "PSIGNW", + "PSLLDQ", + "PSLLL", + "PSLLO", + "PSLLQ", + "PSLLW", + "PSRAL", + "PSRAW", + "PSRLDQ", + "PSRLL", + "PSRLO", + "PSRLQ", + "PSRLW", + "PSUBB", + "PSUBL", + "PSUBQ", + "PSUBSB", + "PSUBSW", + "PSUBUSB", + "PSUBUSW", + "PSUBW", + "PTEST", + "PUNPCKHBW", + "PUNPCKHLQ", + "PUNPCKHQDQ", + "PUNPCKHWL", + "PUNPCKLBW", + "PUNPCKLLQ", + "PUNPCKLQDQ", + "PUNPCKLWL", + "PUSHQ", + "PUSHW", + "PXOR", + "RCLB", + "RCLL", + "RCLQ", + "RCLW", + "RCPPS", + "RCPSS", + "RCRB", + "RCRL", + "RCRQ", + "RCRW", + "RDRANDL", + "RDSEEDL", + "RDTSC", + "RDTSCP", + "RET", + "RETFL", + "RETFQ", + "RETFW", + "ROLB", + "ROLL", + "ROLQ", + "ROLW", + "RORB", + "RORL", + "RORQ", + "RORW", + "RORXL", + "RORXQ", + "ROUNDPD", + "ROUNDPS", + "ROUNDSD", + "ROUNDSS", + "RSQRTPS", + "RSQRTSS", + "SALB", + "SALL", + "SALQ", + "SALW", + "SARB", + "SARL", + "SARQ", + "SARW", + "SARXL", + "SARXQ", + "SBBB", + "SBBL", + "SBBQ", + "SBBW", + "SETCC", + "SETCS", + "SETEQ", + "SETGE", + "SETGT", + "SETHI", + "SETLE", + "SETLS", + "SETLT", + "SETMI", + "SETNE", + "SETOC", + "SETOS", + "SETPC", + "SETPL", + "SETPS", + "SFENCE", + "SHA1MSG1", + "SHA1MSG2", + "SHA1NEXTE", + "SHA1RNDS4", + "SHA256MSG1", + "SHA256MSG2", + "SHA256RNDS2", + "SHLB", + "SHLL", + "SHLQ", + "SHLW", + "SHLXL", + "SHLXQ", + "SHRB", + "SHRL", + "SHRQ", + "SHRW", + "SHRXL", + "SHRXQ", + "SHUFPD", + "SHUFPS", + "SQRTPD", + "SQRTPS", + "SQRTSD", + "SQRTSS", + "STC", + "STD", + "STMXCSR", + "SUBB", + "SUBL", + "SUBPD", + "SUBPS", + "SUBQ", + "SUBSD", + "SUBSS", + "SUBW", + "SYSCALL", + "TESTB", + "TESTL", + "TESTQ", + "TESTW", + "TZCNTL", + "TZCNTQ", + "TZCNTW", + "UCOMISD", + "UCOMISS", + "UD2", + "UNPCKHPD", + "UNPCKHPS", + "UNPCKLPD", + "UNPCKLPS", + "VADDPD", + "VADDPS", + "VADDSD", + "VADDSS", + "VADDSUBPD", + "VADDSUBPS", + "VAESDEC", + "VAESDECLAST", + "VAESENC", + "VAESENCLAST", + "VAESIMC", + "VAESKEYGENASSIST", + "VALIGND", + "VALIGNQ", + "VANDNPD", + "VANDNPS", + "VANDPD", + "VANDPS", + "VBLENDMPD", + "VBLENDMPS", + "VBLENDPD", + "VBLENDPS", + "VBLENDVPD", + "VBLENDVPS", + "VBROADCASTF128", + "VBROADCASTF32X2", + "VBROADCASTF32X4", + "VBROADCASTF32X8", + "VBROADCASTF64X2", + "VBROADCASTF64X4", + "VBROADCASTI128", + "VBROADCASTI32X2", + "VBROADCASTI32X4", + "VBROADCASTI32X8", + "VBROADCASTI64X2", + "VBROADCASTI64X4", + "VBROADCASTSD", + "VBROADCASTSS", + "VCMPPD", + "VCMPPS", + "VCMPSD", + "VCMPSS", + "VCOMISD", + "VCOMISS", + "VCOMPRESSPD", + "VCOMPRESSPS", + "VCVTDQ2PD", + "VCVTDQ2PS", + "VCVTPD2DQ", + "VCVTPD2DQX", + "VCVTPD2DQY", + "VCVTPD2PS", + "VCVTPD2PSX", + "VCVTPD2PSY", + "VCVTPD2QQ", + "VCVTPD2UDQ", + "VCVTPD2UDQX", + "VCVTPD2UDQY", + "VCVTPD2UQQ", + "VCVTPH2PS", + "VCVTPS2DQ", + "VCVTPS2PD", + "VCVTPS2PH", + "VCVTPS2QQ", + "VCVTPS2UDQ", + "VCVTPS2UQQ", + "VCVTQQ2PD", + "VCVTQQ2PS", + "VCVTQQ2PSX", + "VCVTQQ2PSY", + "VCVTSD2SI", + "VCVTSD2SIQ", + "VCVTSD2SS", + "VCVTSD2USIL", + "VCVTSD2USIQ", + "VCVTSI2SDL", + "VCVTSI2SDQ", + "VCVTSI2SSL", + "VCVTSI2SSQ", + "VCVTSS2SD", + "VCVTSS2SI", + "VCVTSS2SIQ", + "VCVTSS2USIL", + "VCVTSS2USIQ", + "VCVTTPD2DQ", + "VCVTTPD2DQX", + "VCVTTPD2DQY", + "VCVTTPD2QQ", + "VCVTTPD2UDQ", + "VCVTTPD2UDQX", + "VCVTTPD2UDQY", + "VCVTTPD2UQQ", + "VCVTTPS2DQ", + "VCVTTPS2QQ", + "VCVTTPS2UDQ", + "VCVTTPS2UQQ", + "VCVTTSD2SI", + "VCVTTSD2SIQ", + "VCVTTSD2USIL", + "VCVTTSD2USIQ", + "VCVTTSS2SI", + "VCVTTSS2SIQ", + "VCVTTSS2USIL", + "VCVTTSS2USIQ", + "VCVTUDQ2PD", + "VCVTUDQ2PS", + "VCVTUQQ2PD", + "VCVTUQQ2PS", + "VCVTUQQ2PSX", + "VCVTUQQ2PSY", + "VCVTUSI2SDL", + "VCVTUSI2SDQ", + "VCVTUSI2SSL", + "VCVTUSI2SSQ", + "VDBPSADBW", + "VDIVPD", + "VDIVPS", + "VDIVSD", + "VDIVSS", + "VDPPD", + "VDPPS", + "VEXP2PD", + "VEXP2PS", + "VEXPANDPD", + "VEXPANDPS", + "VEXTRACTF128", + "VEXTRACTF32X4", + "VEXTRACTF32X8", + "VEXTRACTF64X2", + "VEXTRACTF64X4", + "VEXTRACTI128", + "VEXTRACTI32X4", + "VEXTRACTI32X8", + "VEXTRACTI64X2", + "VEXTRACTI64X4", + "VEXTRACTPS", + "VFIXUPIMMPD", + "VFIXUPIMMPS", + "VFIXUPIMMSD", + "VFIXUPIMMSS", + "VFMADD132PD", + "VFMADD132PS", + "VFMADD132SD", + "VFMADD132SS", + "VFMADD213PD", + "VFMADD213PS", + "VFMADD213SD", + "VFMADD213SS", + "VFMADD231PD", + "VFMADD231PS", + "VFMADD231SD", + "VFMADD231SS", + "VFMADDSUB132PD", + "VFMADDSUB132PS", + "VFMADDSUB213PD", + "VFMADDSUB213PS", + "VFMADDSUB231PD", + "VFMADDSUB231PS", + "VFMSUB132PD", + "VFMSUB132PS", + "VFMSUB132SD", + "VFMSUB132SS", + "VFMSUB213PD", + "VFMSUB213PS", + "VFMSUB213SD", + "VFMSUB213SS", + "VFMSUB231PD", + "VFMSUB231PS", + "VFMSUB231SD", + "VFMSUB231SS", + "VFMSUBADD132PD", + "VFMSUBADD132PS", + "VFMSUBADD213PD", + "VFMSUBADD213PS", + "VFMSUBADD231PD", + "VFMSUBADD231PS", + "VFNMADD132PD", + "VFNMADD132PS", + "VFNMADD132SD", + "VFNMADD132SS", + "VFNMADD213PD", + "VFNMADD213PS", + "VFNMADD213SD", + "VFNMADD213SS", + "VFNMADD231PD", + "VFNMADD231PS", + "VFNMADD231SD", + "VFNMADD231SS", + "VFNMSUB132PD", + "VFNMSUB132PS", + "VFNMSUB132SD", + "VFNMSUB132SS", + "VFNMSUB213PD", + "VFNMSUB213PS", + "VFNMSUB213SD", + "VFNMSUB213SS", + "VFNMSUB231PD", + "VFNMSUB231PS", + "VFNMSUB231SD", + "VFNMSUB231SS", + "VFPCLASSPDX", + "VFPCLASSPDY", + "VFPCLASSPDZ", + "VFPCLASSPSX", + "VFPCLASSPSY", + "VFPCLASSPSZ", + "VFPCLASSSD", + "VFPCLASSSS", + "VGATHERDPD", + "VGATHERDPS", + "VGATHERQPD", + "VGATHERQPS", + "VGETEXPPD", + "VGETEXPPS", + "VGETEXPSD", + "VGETEXPSS", + "VGETMANTPD", + "VGETMANTPS", + "VGETMANTSD", + "VGETMANTSS", + "VHADDPD", + "VHADDPS", + "VHSUBPD", + "VHSUBPS", + "VINSERTF128", + "VINSERTF32X4", + "VINSERTF32X8", + "VINSERTF64X2", + "VINSERTF64X4", + "VINSERTI128", + "VINSERTI32X4", + "VINSERTI32X8", + "VINSERTI64X2", + "VINSERTI64X4", + "VINSERTPS", + "VLDDQU", + "VLDMXCSR", + "VMASKMOVDQU", + "VMASKMOVPD", + "VMASKMOVPS", + "VMAXPD", + "VMAXPS", + "VMAXSD", + "VMAXSS", + "VMINPD", + "VMINPS", + "VMINSD", + "VMINSS", + "VMOVAPD", + "VMOVAPS", + "VMOVD", + "VMOVDDUP", + "VMOVDQA", + "VMOVDQA32", + "VMOVDQA64", + "VMOVDQU", + "VMOVDQU16", + "VMOVDQU32", + "VMOVDQU64", + "VMOVDQU8", + "VMOVHLPS", + "VMOVHPD", + "VMOVHPS", + "VMOVLHPS", + "VMOVLPD", + "VMOVLPS", + "VMOVMSKPD", + "VMOVMSKPS", + "VMOVNTDQ", + "VMOVNTDQA", + "VMOVNTPD", + "VMOVNTPS", + "VMOVQ", + "VMOVSD", + "VMOVSHDUP", + "VMOVSLDUP", + "VMOVSS", + "VMOVUPD", + "VMOVUPS", + "VMPSADBW", + "VMULPD", + "VMULPS", + "VMULSD", + "VMULSS", + "VORPD", + "VORPS", + "VPABSB", + "VPABSD", + "VPABSQ", + "VPABSW", + "VPACKSSDW", + "VPACKSSWB", + "VPACKUSDW", + "VPACKUSWB", + "VPADDB", + "VPADDD", + "VPADDQ", + "VPADDSB", + "VPADDSW", + "VPADDUSB", + "VPADDUSW", + "VPADDW", + "VPALIGNR", + "VPAND", + "VPANDD", + "VPANDN", + "VPANDND", + "VPANDNQ", + "VPANDQ", + "VPAVGB", + "VPAVGW", + "VPBLENDD", + "VPBLENDMB", + "VPBLENDMD", + "VPBLENDMQ", + "VPBLENDMW", + "VPBLENDVB", + "VPBLENDW", + "VPBROADCASTB", + "VPBROADCASTD", + "VPBROADCASTMB2Q", + "VPBROADCASTMW2D", + "VPBROADCASTQ", + "VPBROADCASTW", + "VPCLMULQDQ", + "VPCMPB", + "VPCMPD", + "VPCMPEQB", + "VPCMPEQD", + "VPCMPEQQ", + "VPCMPEQW", + "VPCMPESTRI", + "VPCMPESTRM", + "VPCMPGTB", + "VPCMPGTD", + "VPCMPGTQ", + "VPCMPGTW", + "VPCMPISTRI", + "VPCMPISTRM", + "VPCMPQ", + "VPCMPUB", + "VPCMPUD", + "VPCMPUQ", + "VPCMPUW", + "VPCMPW", + "VPCOMPRESSD", + "VPCOMPRESSQ", + "VPCONFLICTD", + "VPCONFLICTQ", + "VPERM2F128", + "VPERM2I128", + "VPERMB", + "VPERMD", + "VPERMI2B", + "VPERMI2D", + "VPERMI2PD", + "VPERMI2PS", + "VPERMI2Q", + "VPERMI2W", + "VPERMILPD", + "VPERMILPS", + "VPERMPD", + "VPERMPS", + "VPERMQ", + "VPERMT2B", + "VPERMT2D", + "VPERMT2PD", + "VPERMT2PS", + "VPERMT2Q", + "VPERMT2W", + "VPERMW", + "VPEXPANDD", + "VPEXPANDQ", + "VPEXTRB", + "VPEXTRD", + "VPEXTRQ", + "VPEXTRW", + "VPGATHERDD", + "VPGATHERDQ", + "VPGATHERQD", + "VPGATHERQQ", + "VPHADDD", + "VPHADDSW", + "VPHADDW", + "VPHMINPOSUW", + "VPHSUBD", + "VPHSUBSW", + "VPHSUBW", + "VPINSRB", + "VPINSRD", + "VPINSRQ", + "VPINSRW", + "VPLZCNTD", + "VPLZCNTQ", + "VPMADD52HUQ", + "VPMADD52LUQ", + "VPMADDUBSW", + "VPMADDWD", + "VPMASKMOVD", + "VPMASKMOVQ", + "VPMAXSB", + "VPMAXSD", + "VPMAXSQ", + "VPMAXSW", + "VPMAXUB", + "VPMAXUD", + "VPMAXUQ", + "VPMAXUW", + "VPMINSB", + "VPMINSD", + "VPMINSQ", + "VPMINSW", + "VPMINUB", + "VPMINUD", + "VPMINUQ", + "VPMINUW", + "VPMOVB2M", + "VPMOVD2M", + "VPMOVDB", + "VPMOVDW", + "VPMOVM2B", + "VPMOVM2D", + "VPMOVM2Q", + "VPMOVM2W", + "VPMOVMSKB", + "VPMOVQ2M", + "VPMOVQB", + "VPMOVQD", + "VPMOVQW", + "VPMOVSDB", + "VPMOVSDW", + "VPMOVSQB", + "VPMOVSQD", + "VPMOVSQW", + "VPMOVSWB", + "VPMOVSXBD", + "VPMOVSXBQ", + "VPMOVSXBW", + "VPMOVSXDQ", + "VPMOVSXWD", + "VPMOVSXWQ", + "VPMOVUSDB", + "VPMOVUSDW", + "VPMOVUSQB", + "VPMOVUSQD", + "VPMOVUSQW", + "VPMOVUSWB", + "VPMOVW2M", + "VPMOVWB", + "VPMOVZXBD", + "VPMOVZXBQ", + "VPMOVZXBW", + "VPMOVZXDQ", + "VPMOVZXWD", + "VPMOVZXWQ", + "VPMULDQ", + "VPMULHRSW", + "VPMULHUW", + "VPMULHW", + "VPMULLD", + "VPMULLQ", + "VPMULLW", + "VPMULTISHIFTQB", + "VPMULUDQ", + "VPOPCNTD", + "VPOPCNTQ", + "VPOR", + "VPORD", + "VPORQ", + "VPROLD", + "VPROLQ", + "VPROLVD", + "VPROLVQ", + "VPRORD", + "VPRORQ", + "VPRORVD", + "VPRORVQ", + "VPSADBW", + "VPSCATTERDD", + "VPSCATTERDQ", + "VPSCATTERQD", + "VPSCATTERQQ", + "VPSHUFB", + "VPSHUFD", + "VPSHUFHW", + "VPSHUFLW", + "VPSIGNB", + "VPSIGND", + "VPSIGNW", + "VPSLLD", + "VPSLLDQ", + "VPSLLQ", + "VPSLLVD", + "VPSLLVQ", + "VPSLLVW", + "VPSLLW", + "VPSRAD", + "VPSRAQ", + "VPSRAVD", + "VPSRAVQ", + "VPSRAVW", + "VPSRAW", + "VPSRLD", + "VPSRLDQ", + "VPSRLQ", + "VPSRLVD", + "VPSRLVQ", + "VPSRLVW", + "VPSRLW", + "VPSUBB", + "VPSUBD", + "VPSUBQ", + "VPSUBSB", + "VPSUBSW", + "VPSUBUSB", + "VPSUBUSW", + "VPSUBW", + "VPTERNLOGD", + "VPTERNLOGQ", + "VPTEST", + "VPTESTMB", + "VPTESTMD", + "VPTESTMQ", + "VPTESTMW", + "VPTESTNMB", + "VPTESTNMD", + "VPTESTNMQ", + "VPTESTNMW", + "VPUNPCKHBW", + "VPUNPCKHDQ", + "VPUNPCKHQDQ", + "VPUNPCKHWD", + "VPUNPCKLBW", + "VPUNPCKLDQ", + "VPUNPCKLQDQ", + "VPUNPCKLWD", + "VPXOR", + "VPXORD", + "VPXORQ", + "VRANGEPD", + "VRANGEPS", + "VRANGESD", + "VRANGESS", + "VRCP14PD", + "VRCP14PS", + "VRCP14SD", + "VRCP14SS", + "VRCP28PD", + "VRCP28PS", + "VRCP28SD", + "VRCP28SS", + "VRCPPS", + "VRCPSS", + "VREDUCEPD", + "VREDUCEPS", + "VREDUCESD", + "VREDUCESS", + "VRNDSCALEPD", + "VRNDSCALEPS", + "VRNDSCALESD", + "VRNDSCALESS", + "VROUNDPD", + "VROUNDPS", + "VROUNDSD", + "VROUNDSS", + "VRSQRT14PD", + "VRSQRT14PS", + "VRSQRT14SD", + "VRSQRT14SS", + "VRSQRT28PD", + "VRSQRT28PS", + "VRSQRT28SD", + "VRSQRT28SS", + "VRSQRTPS", + "VRSQRTSS", + "VSCALEFPD", + "VSCALEFPS", + "VSCALEFSD", + "VSCALEFSS", + "VSCATTERDPD", + "VSCATTERDPS", + "VSCATTERQPD", + "VSCATTERQPS", + "VSHUFF32X4", + "VSHUFF64X2", + "VSHUFI32X4", + "VSHUFI64X2", + "VSHUFPD", + "VSHUFPS", + "VSQRTPD", + "VSQRTPS", + "VSQRTSD", + "VSQRTSS", + "VSTMXCSR", + "VSUBPD", + "VSUBPS", + "VSUBSD", + "VSUBSS", + "VTESTPD", + "VTESTPS", + "VUCOMISD", + "VUCOMISS", + "VUNPCKHPD", + "VUNPCKHPS", + "VUNPCKLPD", + "VUNPCKLPS", + "VXORPD", + "VXORPS", + "VZEROALL", + "VZEROUPPER", + "XADDB", + "XADDL", + "XADDQ", + "XADDW", + "XCHGB", + "XCHGL", + "XCHGQ", + "XCHGW", + "XGETBV", + "XLAT", + "XORB", + "XORL", + "XORPD", + "XORPS", + "XORQ", + "XORW", +} + +var forms = []form{ + {opcADCB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeAL), false, actionRW}}}, + {opcADCB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcADCB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcADCB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcADCB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcADCB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcADCL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeEAX), false, actionRW}}}, + {opcADCL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcADCL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcADCL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcADCL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcADCL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcADCL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcADCL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcADCQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcADCQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcADCQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeRAX), false, actionRW}}}, + {opcADCQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcADCQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcADCQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcADCQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcADCQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcADCW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM16), false, actionN}, {uint8(oprndtypeAX), false, actionRW}}}, + {opcADCW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM16), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcADCW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM16), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcADCW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcADCW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcADCW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcADCW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcADCW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcADCXL, sffxsclsNIL, 0, isasADX, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcADCXL, sffxsclsNIL, 0, isasADX, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcADCXQ, sffxsclsNIL, 0, isasADX, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcADCXQ, sffxsclsNIL, 0, isasADX, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcADDB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeAL), false, actionRW}}}, + {opcADDB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcADDB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcADDB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcADDB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcADDB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcADDL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeEAX), false, actionRW}}}, + {opcADDL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcADDL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcADDL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcADDL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcADDL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcADDL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcADDL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcADDPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcADDPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcADDPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcADDPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcADDQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcADDQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcADDQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeRAX), false, actionRW}}}, + {opcADDQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcADDQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcADDQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcADDQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcADDQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcADDSD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcADDSD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcADDSS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcADDSS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcADDSUBPD, sffxsclsNIL, 0, isasSSE3, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcADDSUBPD, sffxsclsNIL, 0, isasSSE3, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcADDSUBPS, sffxsclsNIL, 0, isasSSE3, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcADDSUBPS, sffxsclsNIL, 0, isasSSE3, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcADDW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM16), false, actionN}, {uint8(oprndtypeAX), false, actionRW}}}, + {opcADDW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM16), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcADDW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM16), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcADDW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcADDW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcADDW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcADDW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcADDW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcADOXL, sffxsclsNIL, 0, isasADX, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcADOXL, sffxsclsNIL, 0, isasADX, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcADOXQ, sffxsclsNIL, 0, isasADX, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcADOXQ, sffxsclsNIL, 0, isasADX, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcAESDEC, sffxsclsNIL, 0, isasAES, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcAESDEC, sffxsclsNIL, 0, isasAES, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcAESDECLAST, sffxsclsNIL, 0, isasAES, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcAESDECLAST, sffxsclsNIL, 0, isasAES, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcAESENC, sffxsclsNIL, 0, isasAES, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcAESENC, sffxsclsNIL, 0, isasAES, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcAESENCLAST, sffxsclsNIL, 0, isasAES, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcAESENCLAST, sffxsclsNIL, 0, isasAES, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcAESIMC, sffxsclsNIL, 0, isasAES, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcAESIMC, sffxsclsNIL, 0, isasAES, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcAESKEYGENASSIST, sffxsclsNIL, 0, isasAES, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcAESKEYGENASSIST, sffxsclsNIL, 0, isasAES, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcANDB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeAL), false, actionRW}}}, + {opcANDB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcANDB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcANDB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcANDB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcANDB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcANDL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeEAX), false, actionRW}}}, + {opcANDL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcANDL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcANDL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcANDL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcANDL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcANDL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcANDL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcANDNL, sffxsclsNIL, 0, isasBMI, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcANDNL, sffxsclsNIL, featureCancellingInputs, isasBMI, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcANDNPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcANDNPD, sffxsclsNIL, featureCancellingInputs, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcANDNPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcANDNPS, sffxsclsNIL, featureCancellingInputs, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcANDNQ, sffxsclsNIL, 0, isasBMI, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcANDNQ, sffxsclsNIL, featureCancellingInputs, isasBMI, 3, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcANDPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcANDPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcANDPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcANDPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcANDQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcANDQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcANDQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeRAX), false, actionRW}}}, + {opcANDQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcANDQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcANDQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcANDQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcANDQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcANDW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM16), false, actionN}, {uint8(oprndtypeAX), false, actionRW}}}, + {opcANDW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM16), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcANDW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM16), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcANDW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcANDW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcANDW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcANDW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcANDW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcBEXTRL, sffxsclsNIL, 0, isasBMI, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcBEXTRL, sffxsclsNIL, 0, isasBMI, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcBEXTRQ, sffxsclsNIL, 0, isasBMI, 3, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcBEXTRQ, sffxsclsNIL, 0, isasBMI, 3, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcBLENDPD, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcBLENDPD, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcBLENDPS, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcBLENDPS, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcBLENDVPD, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeXMM0), false, actionR}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcBLENDVPD, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeXMM0), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcBLENDVPS, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeXMM0), false, actionR}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcBLENDVPS, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeXMM0), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcBLSIL, sffxsclsNIL, 0, isasBMI, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcBLSIL, sffxsclsNIL, 0, isasBMI, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcBLSIQ, sffxsclsNIL, 0, isasBMI, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcBLSIQ, sffxsclsNIL, 0, isasBMI, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcBLSMSKL, sffxsclsNIL, 0, isasBMI, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcBLSMSKL, sffxsclsNIL, 0, isasBMI, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcBLSMSKQ, sffxsclsNIL, 0, isasBMI, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcBLSMSKQ, sffxsclsNIL, 0, isasBMI, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcBLSRL, sffxsclsNIL, 0, isasBMI, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcBLSRL, sffxsclsNIL, 0, isasBMI, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcBLSRQ, sffxsclsNIL, 0, isasBMI, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcBLSRQ, sffxsclsNIL, 0, isasBMI, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcBSFL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcBSFL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcBSFQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcBSFQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcBSFW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcBSFW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcBSRL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcBSRL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcBSRQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcBSRQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcBSRW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcBSRW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcBSWAPL, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR32), false, actionRW}}}, + {opcBSWAPQ, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR64), false, actionRW}}}, + {opcBTCL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcBTCL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcBTCL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcBTCL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcBTCQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcBTCQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcBTCQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcBTCQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcBTCW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcBTCW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcBTCW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcBTCW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcBTL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}}}, + {opcBTL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR32), false, actionR}}}, + {opcBTL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeM32), false, actionR}}}, + {opcBTL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionR}}}, + {opcBTQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}}}, + {opcBTQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR64), false, actionR}}}, + {opcBTQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeM64), false, actionR}}}, + {opcBTQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionR}}}, + {opcBTRL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcBTRL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcBTRL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcBTRL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcBTRQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcBTRQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcBTRQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcBTRQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcBTRW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcBTRW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcBTRW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcBTRW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcBTSL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcBTSL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcBTSL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcBTSL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcBTSQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcBTSQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcBTSQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcBTSQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcBTSW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcBTSW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcBTSW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcBTSW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcBTW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM16), false, actionR}}}, + {opcBTW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR16), false, actionR}}}, + {opcBTW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeM16), false, actionR}}}, + {opcBTW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionR}}}, + {opcBZHIL, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcBZHIL, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcBZHIQ, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcBZHIQ, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcCALL, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcCBW, sffxsclsNIL, 0, isasBase, 0, oprnds{{uint8(implregAX), true, actionW}, {uint8(implregAL), true, actionR}}}, + {opcCDQ, sffxsclsNIL, 0, isasBase, 0, oprnds{{uint8(implregEAX), true, actionR}, {uint8(implregEDX), true, actionW}}}, + {opcCDQE, sffxsclsNIL, 0, isasBase, 0, oprnds{{uint8(implregEAX), true, actionR}, {uint8(implregRAX), true, actionW}}}, + {opcCLC, sffxsclsNIL, 0, isasBase, 0, oprnds{}}, + {opcCLD, sffxsclsNIL, 0, isasBase, 0, oprnds{}}, + {opcCLFLUSH, sffxsclsNIL, 0, isasCLFLUSH, 1, oprnds{{uint8(oprndtypeM8), false, actionR}}}, + {opcCLFLUSHOPT, sffxsclsNIL, 0, isasCLFLUSHOPT, 1, oprnds{{uint8(oprndtypeM8), false, actionR}}}, + {opcCMC, sffxsclsNIL, 0, isasBase, 0, oprnds{}}, + {opcCMOVLCC, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVLCC, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVLCS, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVLCS, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVLEQ, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVLEQ, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVLGE, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVLGE, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVLGT, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVLGT, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVLHI, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVLHI, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVLLE, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVLLE, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVLLS, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVLLS, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVLLT, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVLLT, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVLMI, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVLMI, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVLNE, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVLNE, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVLOC, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVLOC, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVLOS, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVLOS, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVLPC, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVLPC, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVLPL, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVLPL, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVLPS, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVLPS, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMOVQCC, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVQCC, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVQCS, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVQCS, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVQEQ, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVQEQ, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVQGE, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVQGE, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVQGT, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVQGT, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVQHI, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVQHI, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVQLE, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVQLE, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVQLS, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVQLS, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVQLT, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVQLT, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVQMI, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVQMI, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVQNE, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVQNE, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVQOC, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVQOC, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVQOS, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVQOS, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVQPC, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVQPC, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVQPL, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVQPL, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVQPS, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVQPS, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMOVWCC, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMOVWCC, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMOVWCS, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMOVWCS, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMOVWEQ, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMOVWEQ, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMOVWGE, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMOVWGE, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMOVWGT, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMOVWGT, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMOVWHI, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMOVWHI, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMOVWLE, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMOVWLE, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMOVWLS, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMOVWLS, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMOVWLT, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMOVWLT, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMOVWMI, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMOVWMI, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMOVWNE, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMOVWNE, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMOVWOC, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMOVWOC, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMOVWOS, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMOVWOS, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMOVWPC, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMOVWPC, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMOVWPL, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMOVWPL, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMOVWPS, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMOVWPS, sffxsclsNIL, 0, isasCMOV, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCMPB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeAL), false, actionR}, {uint8(oprndtypeIMM8), false, actionN}}}, + {opcCMPB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(oprndtypeIMM8), false, actionN}}}, + {opcCMPB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(oprndtypeR8), false, actionR}}}, + {opcCMPB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(oprndtypeIMM8), false, actionN}}}, + {opcCMPB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(oprndtypeM8), false, actionR}}}, + {opcCMPB, sffxsclsNIL, featureCancellingInputs, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(oprndtypeR8), false, actionR}}}, + {opcCMPL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeEAX), false, actionR}, {uint8(oprndtypeIMM32), false, actionN}}}, + {opcCMPL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeIMM32), false, actionN}}}, + {opcCMPL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeIMM8), false, actionN}}}, + {opcCMPL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionR}}}, + {opcCMPL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeIMM32), false, actionN}}}, + {opcCMPL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeIMM8), false, actionN}}}, + {opcCMPL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeM32), false, actionR}}}, + {opcCMPL, sffxsclsNIL, featureCancellingInputs, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionR}}}, + {opcCMPPD, sffxsclsNIL, 0, isasSSE2, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}, {uint8(oprndtypeIMM8), false, actionN}}}, + {opcCMPPD, sffxsclsNIL, 0, isasSSE2, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}, {uint8(oprndtypeIMM8), false, actionN}}}, + {opcCMPPS, sffxsclsNIL, 0, isasSSE, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}, {uint8(oprndtypeIMM8), false, actionN}}}, + {opcCMPPS, sffxsclsNIL, 0, isasSSE, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}, {uint8(oprndtypeIMM8), false, actionN}}}, + {opcCMPQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeIMM32), false, actionN}}}, + {opcCMPQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeIMM8), false, actionN}}}, + {opcCMPQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionR}}}, + {opcCMPQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeIMM32), false, actionN}}}, + {opcCMPQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeIMM8), false, actionN}}}, + {opcCMPQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeM64), false, actionR}}}, + {opcCMPQ, sffxsclsNIL, featureCancellingInputs, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionR}}}, + {opcCMPQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeRAX), false, actionR}, {uint8(oprndtypeIMM32), false, actionN}}}, + {opcCMPSD, sffxsclsNIL, 0, isasSSE2, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}, {uint8(oprndtypeIMM8), false, actionN}}}, + {opcCMPSD, sffxsclsNIL, 0, isasSSE2, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}, {uint8(oprndtypeIMM8), false, actionN}}}, + {opcCMPSS, sffxsclsNIL, 0, isasSSE, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}, {uint8(oprndtypeIMM8), false, actionN}}}, + {opcCMPSS, sffxsclsNIL, 0, isasSSE, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}, {uint8(oprndtypeIMM8), false, actionN}}}, + {opcCMPW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeAX), false, actionR}, {uint8(oprndtypeIMM16), false, actionN}}}, + {opcCMPW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeIMM16), false, actionN}}}, + {opcCMPW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeIMM8), false, actionN}}}, + {opcCMPW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionR}}}, + {opcCMPW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeIMM16), false, actionN}}}, + {opcCMPW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeIMM8), false, actionN}}}, + {opcCMPW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeM16), false, actionR}}}, + {opcCMPW, sffxsclsNIL, featureCancellingInputs, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionR}}}, + {opcCMPXCHG16B, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(implregRAX), true, actionRW}, {uint8(implregRBX), true, actionR}, {uint8(implregRCX), true, actionR}, {uint8(implregRDX), true, actionRW}}}, + {opcCMPXCHG8B, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(implregEAX), true, actionRW}, {uint8(implregEBX), true, actionR}, {uint8(implregECX), true, actionR}, {uint8(implregEDX), true, actionRW}}}, + {opcCMPXCHGB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcCMPXCHGB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcCMPXCHGL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcCMPXCHGL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCMPXCHGQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcCMPXCHGQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCMPXCHGW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcCMPXCHGW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcCOMISD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}}}, + {opcCOMISD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}}}, + {opcCOMISS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}}}, + {opcCOMISS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}}}, + {opcCPUID, sffxsclsNIL, 0, isasCPUID, 0, oprnds{{uint8(implregEAX), true, actionRW}, {uint8(implregEBX), true, actionW}, {uint8(implregECX), true, actionRW}, {uint8(implregEDX), true, actionW}}}, + {opcCQO, sffxsclsNIL, 0, isasBase, 0, oprnds{{uint8(implregRAX), true, actionR}, {uint8(implregRDX), true, actionW}}}, + {opcCRC32B, sffxsclsNIL, 0, isasSSE42, 2, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCRC32B, sffxsclsNIL, 0, isasSSE42, 2, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCRC32B, sffxsclsNIL, 0, isasSSE42, 2, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCRC32B, sffxsclsNIL, 0, isasSSE42, 2, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCRC32L, sffxsclsNIL, 0, isasSSE42, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCRC32L, sffxsclsNIL, 0, isasSSE42, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCRC32Q, sffxsclsNIL, 0, isasSSE42, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCRC32Q, sffxsclsNIL, 0, isasSSE42, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcCRC32W, sffxsclsNIL, 0, isasSSE42, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCRC32W, sffxsclsNIL, 0, isasSSE42, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcCVTPD2PL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcCVTPD2PL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcCVTPD2PS, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcCVTPD2PS, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcCVTPL2PD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcCVTPL2PD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcCVTPL2PS, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcCVTPL2PS, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcCVTPS2PD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcCVTPS2PD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcCVTPS2PL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcCVTPS2PL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcCVTSD2SL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcCVTSD2SL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcCVTSD2SL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcCVTSD2SL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcCVTSD2SS, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcCVTSD2SS, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcCVTSL2SD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcCVTSL2SD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcCVTSL2SS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcCVTSL2SS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcCVTSQ2SD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcCVTSQ2SD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcCVTSQ2SS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcCVTSQ2SS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcCVTSS2SD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcCVTSS2SD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcCVTSS2SL, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcCVTSS2SL, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcCVTSS2SL, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcCVTSS2SL, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcCVTTPD2PL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcCVTTPD2PL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcCVTTPS2PL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcCVTTPS2PL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcCVTTSD2SL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcCVTTSD2SL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcCVTTSD2SQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcCVTTSD2SQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcCVTTSS2SL, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcCVTTSS2SL, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcCVTTSS2SL, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcCVTTSS2SL, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcCWD, sffxsclsNIL, 0, isasBase, 0, oprnds{{uint8(implregAX), true, actionR}, {uint8(implregDX), true, actionW}}}, + {opcCWDE, sffxsclsNIL, 0, isasBase, 0, oprnds{{uint8(implregAX), true, actionR}, {uint8(implregEAX), true, actionW}}}, + {opcDECB, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM8), false, actionRW}}}, + {opcDECB, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR8), false, actionRW}}}, + {opcDECL, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM32), false, actionRW}}}, + {opcDECL, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR32), false, actionRW}}}, + {opcDECQ, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM64), false, actionRW}}}, + {opcDECQ, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR64), false, actionRW}}}, + {opcDECW, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM16), false, actionRW}}}, + {opcDECW, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR16), false, actionRW}}}, + {opcDIVB, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(implregAX), true, actionRW}}}, + {opcDIVB, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(implregAX), true, actionRW}}}, + {opcDIVL, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(implregEAX), true, actionRW}, {uint8(implregEDX), true, actionRW}}}, + {opcDIVL, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(implregEAX), true, actionRW}, {uint8(implregEDX), true, actionRW}}}, + {opcDIVPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcDIVPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcDIVPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcDIVPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcDIVQ, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(implregRAX), true, actionRW}, {uint8(implregRDX), true, actionRW}}}, + {opcDIVQ, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(implregRAX), true, actionRW}, {uint8(implregRDX), true, actionRW}}}, + {opcDIVSD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcDIVSD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcDIVSS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcDIVSS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcDIVW, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(implregAX), true, actionRW}, {uint8(implregDX), true, actionRW}}}, + {opcDIVW, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(implregAX), true, actionRW}, {uint8(implregDX), true, actionRW}}}, + {opcDPPD, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcDPPD, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcDPPS, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcDPPS, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcEXTRACTPS, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM2U), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcEXTRACTPS, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM2U), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcHADDPD, sffxsclsNIL, 0, isasSSE3, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcHADDPD, sffxsclsNIL, 0, isasSSE3, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcHADDPS, sffxsclsNIL, 0, isasSSE3, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcHADDPS, sffxsclsNIL, 0, isasSSE3, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcHSUBPD, sffxsclsNIL, 0, isasSSE3, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcHSUBPD, sffxsclsNIL, 0, isasSSE3, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcHSUBPS, sffxsclsNIL, 0, isasSSE3, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcHSUBPS, sffxsclsNIL, 0, isasSSE3, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcIDIVB, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(implregAX), true, actionRW}}}, + {opcIDIVB, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(implregAX), true, actionRW}}}, + {opcIDIVL, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(implregEAX), true, actionRW}, {uint8(implregEDX), true, actionRW}}}, + {opcIDIVL, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(implregEAX), true, actionRW}, {uint8(implregEDX), true, actionRW}}}, + {opcIDIVQ, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(implregRAX), true, actionRW}, {uint8(implregRDX), true, actionRW}}}, + {opcIDIVQ, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(implregRAX), true, actionRW}, {uint8(implregRDX), true, actionRW}}}, + {opcIDIVW, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(implregAX), true, actionRW}, {uint8(implregDX), true, actionRW}}}, + {opcIDIVW, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(implregAX), true, actionRW}, {uint8(implregDX), true, actionRW}}}, + {opcIMUL3L, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcIMUL3L, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcIMUL3L, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcIMUL3L, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcIMUL3Q, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcIMUL3Q, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcIMUL3Q, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcIMUL3Q, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcIMUL3W, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeIMM16), false, actionN}, {uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionW}}}, + {opcIMUL3W, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeIMM16), false, actionN}, {uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionW}}}, + {opcIMUL3W, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionW}}}, + {opcIMUL3W, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionW}}}, + {opcIMULB, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(implregAX), true, actionW}, {uint8(implregAL), true, actionR}}}, + {opcIMULB, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(implregAX), true, actionW}, {uint8(implregAL), true, actionR}}}, + {opcIMULL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcIMULL, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(implregEAX), true, actionRW}, {uint8(implregEDX), true, actionW}}}, + {opcIMULL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcIMULL, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(implregEAX), true, actionRW}, {uint8(implregEDX), true, actionW}}}, + {opcIMULQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcIMULQ, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(implregRAX), true, actionRW}, {uint8(implregRDX), true, actionW}}}, + {opcIMULQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcIMULQ, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(implregRAX), true, actionRW}, {uint8(implregRDX), true, actionW}}}, + {opcIMULW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcIMULW, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(implregAX), true, actionRW}, {uint8(implregDX), true, actionW}}}, + {opcIMULW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcIMULW, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(implregAX), true, actionRW}, {uint8(implregDX), true, actionW}}}, + {opcINCB, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM8), false, actionRW}}}, + {opcINCB, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR8), false, actionRW}}}, + {opcINCL, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM32), false, actionRW}}}, + {opcINCL, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR32), false, actionRW}}}, + {opcINCQ, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM64), false, actionRW}}}, + {opcINCQ, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR64), false, actionRW}}}, + {opcINCW, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM16), false, actionRW}}}, + {opcINCW, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR16), false, actionRW}}}, + {opcINSERTPS, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcINSERTPS, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcINT, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtype3), false, actionN}}}, + {opcINT, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeIMM8), false, actionN}}}, + {opcJA, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJA, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJAE, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJAE, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJB, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJB, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJBE, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJBE, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJC, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJC, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJCC, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJCC, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJCS, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJCS, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJCXZL, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}, {uint8(implregECX), true, actionR}}}, + {opcJCXZQ, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}, {uint8(implregRCX), true, actionR}}}, + {opcJE, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJE, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJEQ, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJEQ, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJG, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJG, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJGE, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJGE, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJGT, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJGT, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJHI, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJHI, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJHS, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJHS, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJL, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJL, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJLE, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJLE, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJLO, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJLO, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJLS, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJLS, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJLT, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJLT, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJMI, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJMI, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJMP, sffxsclsNIL, featureBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJMP, sffxsclsNIL, featureBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJMP, sffxsclsNIL, featureBranch, isasBase, 1, oprnds{{uint8(oprndtypeM64), false, actionR}}}, + {opcJMP, sffxsclsNIL, featureBranch, isasBase, 1, oprnds{{uint8(oprndtypeR64), false, actionR}}}, + {opcJNA, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJNA, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJNAE, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJNAE, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJNB, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJNB, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJNBE, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJNBE, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJNC, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJNC, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJNE, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJNE, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJNG, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJNG, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJNGE, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJNGE, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJNL, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJNL, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJNLE, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJNLE, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJNO, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJNO, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJNP, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJNP, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJNS, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJNS, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJNZ, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJNZ, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJO, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJO, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJOC, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJOC, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJOS, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJOS, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJP, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJP, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJPC, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJPC, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJPE, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJPE, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJPL, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJPL, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJPO, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJPO, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJPS, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJPS, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJS, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJS, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcJZ, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL32), false, actionN}}}, + {opcJZ, sffxsclsNIL, featureBranch | featureConditionalBranch, isasBase, 1, oprnds{{uint8(oprndtypeREL8), false, actionN}}}, + {opcKADDB, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKADDD, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKADDQ, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKADDW, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKANDB, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKANDD, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKANDNB, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKANDND, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKANDNQ, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKANDNW, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKANDQ, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKANDW, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKMOVB, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKMOVB, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM8), false, actionW}}}, + {opcKMOVB, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcKMOVB, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKMOVB, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKMOVD, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKMOVD, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcKMOVD, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcKMOVD, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKMOVD, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKMOVQ, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKMOVQ, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcKMOVQ, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcKMOVQ, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKMOVQ, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKMOVW, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKMOVW, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM16), false, actionW}}}, + {opcKMOVW, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcKMOVW, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKMOVW, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKNOTB, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKNOTD, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKNOTQ, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKNOTW, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKORB, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKORD, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKORQ, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKORTESTB, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}}}, + {opcKORTESTD, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}}}, + {opcKORTESTQ, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}}}, + {opcKORTESTW, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}}}, + {opcKORW, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKSHIFTLB, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKSHIFTLD, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKSHIFTLQ, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKSHIFTLW, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKSHIFTRB, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKSHIFTRD, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKSHIFTRQ, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKSHIFTRW, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKTESTB, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}}}, + {opcKTESTD, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}}}, + {opcKTESTQ, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}}}, + {opcKTESTW, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}}}, + {opcKUNPCKBW, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKUNPCKDQ, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKUNPCKWD, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKXNORB, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKXNORD, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKXNORQ, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKXNORW, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKXORB, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKXORD, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKXORQ, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcKXORW, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcLDDQU, sffxsclsNIL, 0, isasSSE3, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcLDMXCSR, sffxsclsNIL, 0, isasSSE, 1, oprnds{{uint8(oprndtypeM32), false, actionR}}}, + {opcLEAL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcLEAQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcLEAW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM), false, actionR}, {uint8(oprndtypeR16), false, actionW}}}, + {opcLFENCE, sffxsclsNIL, 0, isasSSE2, 0, oprnds{}}, + {opcLZCNTL, sffxsclsNIL, 0, isasLZCNT, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcLZCNTL, sffxsclsNIL, 0, isasLZCNT, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcLZCNTQ, sffxsclsNIL, 0, isasLZCNT, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcLZCNTQ, sffxsclsNIL, 0, isasLZCNT, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcLZCNTW, sffxsclsNIL, 0, isasLZCNT, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionW}}}, + {opcLZCNTW, sffxsclsNIL, 0, isasLZCNT, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionW}}}, + {opcMASKMOVDQU, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(implregRDI), true, actionR}}}, + {opcMASKMOVOU, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(implregRDI), true, actionR}}}, + {opcMAXPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMAXPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMAXPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMAXPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMAXSD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMAXSD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMAXSS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMAXSS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMFENCE, sffxsclsNIL, 0, isasSSE2, 0, oprnds{}}, + {opcMINPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMINPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMINPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMINPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMINSD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMINSD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMINSS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMINSS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMONITOR, sffxsclsNIL, 0, isasMONITOR, 0, oprnds{{uint8(implregRAX), true, actionR}, {uint8(implregECX), true, actionR}, {uint8(implregEDX), true, actionR}}}, + {opcMOVAPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVAPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcMOVAPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVAPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVAPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcMOVAPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM8), false, actionW}}}, + {opcMOVB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR8), false, actionW}}}, + {opcMOVB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(oprndtypeR8), false, actionW}}}, + {opcMOVB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(oprndtypeM8), false, actionW}}}, + {opcMOVB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(oprndtypeR8), false, actionW}}}, + {opcMOVBELL, sffxsclsNIL, 0, isasMOVBE, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcMOVBELL, sffxsclsNIL, 0, isasMOVBE, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcMOVBEQQ, sffxsclsNIL, 0, isasMOVBE, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcMOVBEQQ, sffxsclsNIL, 0, isasMOVBE, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcMOVBEWW, sffxsclsNIL, 0, isasMOVBE, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionW}}}, + {opcMOVBEWW, sffxsclsNIL, 0, isasMOVBE, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeM16), false, actionW}}}, + {opcMOVBLSX, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcMOVBLSX, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcMOVBLZX, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcMOVBLZX, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcMOVBQSX, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcMOVBQSX, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcMOVBQZX, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcMOVBQZX, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcMOVBWSX, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(oprndtypeR16), false, actionW}}}, + {opcMOVBWSX, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(oprndtypeR16), false, actionW}}}, + {opcMOVBWZX, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(oprndtypeR16), false, actionW}}}, + {opcMOVBWZX, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(oprndtypeR16), false, actionW}}}, + {opcMOVD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcMOVD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcMOVD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcMOVD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcMOVD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVD, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeM64), false, actionW}}}, + {opcMOVD, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeR64), false, actionW}}}, + {opcMOVD, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM64), false, actionN}, {uint8(oprndtypeR64), false, actionW}}}, + {opcMOVD, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcMOVD, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcMOVD, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcMOVDDUP, sffxsclsNIL, 0, isasSSE3, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVDDUP, sffxsclsNIL, 0, isasSSE3, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVDQ2Q, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVDQ2Q, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVDQ2Q, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVDQ2Q, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVDQ2Q, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcMOVDQ2Q, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcMOVDQ2Q, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcMOVDQ2Q, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcMOVDQ2Q, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVDQ2Q, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeM64), false, actionW}}}, + {opcMOVDQ2Q, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeR64), false, actionW}}}, + {opcMOVDQ2Q, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM64), false, actionN}, {uint8(oprndtypeR64), false, actionW}}}, + {opcMOVDQ2Q, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcMOVDQ2Q, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcMOVDQ2Q, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcMOVHLPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMOVHPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMOVHPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcMOVHPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMOVHPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcMOVL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeM32), false, actionW}}}, + {opcMOVL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeR32), false, actionW}}}, + {opcMOVL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcMOVL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcMOVL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcMOVLHPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMOVLPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMOVLPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcMOVLPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMOVLPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcMOVLQSX, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcMOVLQSX, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcMOVLQZX, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcMOVMSKPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcMOVMSKPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcMOVNTDQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcMOVNTDQA, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVNTIL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcMOVNTIQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcMOVNTO, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcMOVNTPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcMOVNTPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcMOVO, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVO, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcMOVO, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVOA, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVOA, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcMOVOA, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVOU, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVOU, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcMOVOU, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcMOVQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcMOVQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcMOVQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcMOVQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeM64), false, actionW}}}, + {opcMOVQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeR64), false, actionW}}}, + {opcMOVQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM64), false, actionN}, {uint8(oprndtypeR64), false, actionW}}}, + {opcMOVQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcMOVQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcMOVQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcMOVSD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVSD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcMOVSD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMOVSHDUP, sffxsclsNIL, 0, isasSSE3, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVSHDUP, sffxsclsNIL, 0, isasSSE3, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVSLDUP, sffxsclsNIL, 0, isasSSE3, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVSLDUP, sffxsclsNIL, 0, isasSSE3, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVSS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVSS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcMOVSS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMOVUPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVUPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcMOVUPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVUPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVUPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcMOVUPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcMOVW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM16), false, actionN}, {uint8(oprndtypeM16), false, actionW}}}, + {opcMOVW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM16), false, actionN}, {uint8(oprndtypeR16), false, actionW}}}, + {opcMOVW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionW}}}, + {opcMOVW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeM16), false, actionW}}}, + {opcMOVW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionW}}}, + {opcMOVWLSX, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcMOVWLSX, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcMOVWLZX, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcMOVWLZX, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcMOVWQSX, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcMOVWQSX, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcMOVWQZX, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcMOVWQZX, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcMPSADBW, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMPSADBW, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMULB, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(implregAX), true, actionW}, {uint8(implregAL), true, actionR}}}, + {opcMULB, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(implregAX), true, actionW}, {uint8(implregAL), true, actionR}}}, + {opcMULL, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(implregEAX), true, actionRW}, {uint8(implregEDX), true, actionW}}}, + {opcMULL, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(implregEAX), true, actionRW}, {uint8(implregEDX), true, actionW}}}, + {opcMULPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMULPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMULPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMULPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMULQ, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(implregRAX), true, actionRW}, {uint8(implregRDX), true, actionW}}}, + {opcMULQ, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(implregRAX), true, actionRW}, {uint8(implregRDX), true, actionW}}}, + {opcMULSD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMULSD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMULSS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMULSS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcMULW, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(implregAX), true, actionRW}, {uint8(implregDX), true, actionW}}}, + {opcMULW, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(implregAX), true, actionRW}, {uint8(implregDX), true, actionW}}}, + {opcMULXL, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionW}, {uint8(oprndtypeR32), false, actionW}, {uint8(implregEDX), true, actionR}}}, + {opcMULXL, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionW}, {uint8(oprndtypeR32), false, actionW}, {uint8(implregEDX), true, actionR}}}, + {opcMULXQ, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionW}, {uint8(oprndtypeR64), false, actionW}, {uint8(implregRDX), true, actionR}}}, + {opcMULXQ, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionW}, {uint8(oprndtypeR64), false, actionW}, {uint8(implregRDX), true, actionR}}}, + {opcMWAIT, sffxsclsNIL, 0, isasMONITOR, 0, oprnds{{uint8(implregEAX), true, actionR}, {uint8(implregECX), true, actionR}}}, + {opcNEGB, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM8), false, actionRW}}}, + {opcNEGB, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR8), false, actionRW}}}, + {opcNEGL, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM32), false, actionRW}}}, + {opcNEGL, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR32), false, actionRW}}}, + {opcNEGQ, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM64), false, actionRW}}}, + {opcNEGQ, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR64), false, actionRW}}}, + {opcNEGW, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM16), false, actionRW}}}, + {opcNEGW, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR16), false, actionRW}}}, + {opcNOP, sffxsclsNIL, 0, isasBase, 0, oprnds{}}, + {opcNOTB, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM8), false, actionRW}}}, + {opcNOTB, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR8), false, actionRW}}}, + {opcNOTL, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM32), false, actionRW}}}, + {opcNOTL, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR32), false, actionRW}}}, + {opcNOTQ, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM64), false, actionRW}}}, + {opcNOTQ, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR64), false, actionRW}}}, + {opcNOTW, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM16), false, actionRW}}}, + {opcNOTW, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR16), false, actionRW}}}, + {opcORB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeAL), false, actionRW}}}, + {opcORB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcORB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcORB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcORB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcORB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcORL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeEAX), false, actionRW}}}, + {opcORL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcORL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcORL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcORL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcORL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcORL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcORL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcORPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcORPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcORPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcORPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcORQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcORQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcORQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeRAX), false, actionRW}}}, + {opcORQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcORQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcORQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcORQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcORQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcORW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM16), false, actionN}, {uint8(oprndtypeAX), false, actionRW}}}, + {opcORW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM16), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcORW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM16), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcORW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcORW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcORW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcORW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcORW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcPABSB, sffxsclsNIL, 0, isasSSSE3, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPABSB, sffxsclsNIL, 0, isasSSSE3, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPABSD, sffxsclsNIL, 0, isasSSSE3, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPABSD, sffxsclsNIL, 0, isasSSSE3, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPABSW, sffxsclsNIL, 0, isasSSSE3, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPABSW, sffxsclsNIL, 0, isasSSSE3, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPACKSSLW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPACKSSLW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPACKSSWB, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPACKSSWB, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPACKUSDW, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPACKUSDW, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPACKUSWB, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPACKUSWB, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPADDB, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPADDB, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPADDD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPADDD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPADDL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPADDL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPADDQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPADDQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPADDSB, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPADDSB, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPADDSW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPADDSW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPADDUSB, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPADDUSB, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPADDUSW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPADDUSW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPADDW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPADDW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPALIGNR, sffxsclsNIL, 0, isasSSSE3, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPALIGNR, sffxsclsNIL, 0, isasSSSE3, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPAND, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPAND, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPANDN, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPANDN, sffxsclsNIL, featureCancellingInputs, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPAUSE, sffxsclsNIL, 0, isasBase, 0, oprnds{}}, + {opcPAVGB, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPAVGB, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPAVGW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPAVGW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPBLENDVB, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeXMM0), false, actionR}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPBLENDVB, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeXMM0), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPBLENDW, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPBLENDW, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPCLMULQDQ, sffxsclsNIL, 0, isasPCLMULQDQ, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPCLMULQDQ, sffxsclsNIL, 0, isasPCLMULQDQ, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPCMPEQB, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPCMPEQB, sffxsclsNIL, featureCancellingInputs, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPCMPEQL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPCMPEQL, sffxsclsNIL, featureCancellingInputs, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPCMPEQQ, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPCMPEQQ, sffxsclsNIL, featureCancellingInputs, isasSSE41, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPCMPEQW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPCMPEQW, sffxsclsNIL, featureCancellingInputs, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPCMPESTRI, sffxsclsNIL, 0, isasSSE42, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(implregEAX), true, actionR}, {uint8(implregECX), true, actionW}, {uint8(implregEDX), true, actionR}}}, + {opcPCMPESTRI, sffxsclsNIL, 0, isasSSE42, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(implregEAX), true, actionR}, {uint8(implregECX), true, actionW}, {uint8(implregEDX), true, actionR}}}, + {opcPCMPESTRM, sffxsclsNIL, 0, isasSSE42, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(implregEAX), true, actionR}, {uint8(implregEDX), true, actionR}, {uint8(implregX0), true, actionW}}}, + {opcPCMPESTRM, sffxsclsNIL, 0, isasSSE42, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(implregEAX), true, actionR}, {uint8(implregEDX), true, actionR}, {uint8(implregX0), true, actionW}}}, + {opcPCMPGTB, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPCMPGTB, sffxsclsNIL, featureCancellingInputs, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPCMPGTL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPCMPGTL, sffxsclsNIL, featureCancellingInputs, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPCMPGTQ, sffxsclsNIL, 0, isasSSE42, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPCMPGTQ, sffxsclsNIL, featureCancellingInputs, isasSSE42, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPCMPGTW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPCMPGTW, sffxsclsNIL, featureCancellingInputs, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPCMPISTRI, sffxsclsNIL, 0, isasSSE42, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(implregECX), true, actionW}}}, + {opcPCMPISTRI, sffxsclsNIL, 0, isasSSE42, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(implregECX), true, actionW}}}, + {opcPCMPISTRM, sffxsclsNIL, 0, isasSSE42, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(implregX0), true, actionW}}}, + {opcPCMPISTRM, sffxsclsNIL, 0, isasSSE42, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(implregX0), true, actionW}}}, + {opcPDEPL, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcPDEPL, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcPDEPQ, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcPDEPQ, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcPEXTL, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcPEXTL, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcPEXTQ, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcPEXTQ, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcPEXTRB, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM8), false, actionW}}}, + {opcPEXTRB, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcPEXTRD, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcPEXTRD, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcPEXTRQ, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcPEXTRQ, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcPEXTRW, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM16), false, actionW}}}, + {opcPEXTRW, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcPHADDD, sffxsclsNIL, 0, isasSSSE3, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPHADDD, sffxsclsNIL, 0, isasSSSE3, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPHADDSW, sffxsclsNIL, 0, isasSSSE3, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPHADDSW, sffxsclsNIL, 0, isasSSSE3, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPHADDW, sffxsclsNIL, 0, isasSSSE3, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPHADDW, sffxsclsNIL, 0, isasSSSE3, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPHMINPOSUW, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPHMINPOSUW, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPHSUBD, sffxsclsNIL, 0, isasSSSE3, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPHSUBD, sffxsclsNIL, featureCancellingInputs, isasSSSE3, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPHSUBSW, sffxsclsNIL, 0, isasSSSE3, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPHSUBSW, sffxsclsNIL, featureCancellingInputs, isasSSSE3, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPHSUBW, sffxsclsNIL, 0, isasSSSE3, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPHSUBW, sffxsclsNIL, featureCancellingInputs, isasSSSE3, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPINSRB, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM8), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPINSRB, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPINSRD, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPINSRD, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPINSRQ, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPINSRQ, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPINSRW, sffxsclsNIL, 0, isasSSE2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPINSRW, sffxsclsNIL, 0, isasSSE2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMADDUBSW, sffxsclsNIL, 0, isasSSSE3, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMADDUBSW, sffxsclsNIL, 0, isasSSSE3, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMADDWL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMADDWL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMAXSB, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMAXSB, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMAXSD, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMAXSD, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMAXSW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMAXSW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMAXUB, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMAXUB, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMAXUD, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMAXUD, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMAXUW, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMAXUW, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMINSB, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMINSB, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMINSD, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMINSD, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMINSW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMINSW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMINUB, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMINUB, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMINUD, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMINUD, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMINUW, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMINUW, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMOVMSKB, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcPMOVSXBD, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPMOVSXBD, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPMOVSXBQ, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPMOVSXBQ, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPMOVSXBW, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPMOVSXBW, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPMOVSXDQ, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPMOVSXDQ, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPMOVSXWD, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPMOVSXWD, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPMOVSXWQ, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPMOVSXWQ, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPMOVZXBD, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPMOVZXBD, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPMOVZXBQ, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPMOVZXBQ, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPMOVZXBW, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPMOVZXBW, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPMOVZXDQ, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPMOVZXDQ, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPMOVZXWD, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPMOVZXWD, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPMOVZXWQ, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPMOVZXWQ, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPMULDQ, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMULDQ, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMULHRSW, sffxsclsNIL, 0, isasSSSE3, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMULHRSW, sffxsclsNIL, 0, isasSSSE3, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMULHUW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMULHUW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMULHW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMULHW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMULLD, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMULLD, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMULLW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMULLW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMULULQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPMULULQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPOPCNTL, sffxsclsNIL, 0, isasPOPCNT, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcPOPCNTL, sffxsclsNIL, 0, isasPOPCNT, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcPOPCNTQ, sffxsclsNIL, 0, isasPOPCNT, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcPOPCNTQ, sffxsclsNIL, 0, isasPOPCNT, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcPOPCNTW, sffxsclsNIL, 0, isasPOPCNT, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionW}}}, + {opcPOPCNTW, sffxsclsNIL, 0, isasPOPCNT, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionW}}}, + {opcPOPQ, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM64), false, actionW}}}, + {opcPOPQ, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR64), false, actionW}}}, + {opcPOPW, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM16), false, actionW}}}, + {opcPOPW, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR16), false, actionW}}}, + {opcPOR, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPOR, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPREFETCHNTA, sffxsclsNIL, 0, isasMMX, 1, oprnds{{uint8(oprndtypeM8), false, actionR}}}, + {opcPREFETCHT0, sffxsclsNIL, 0, isasMMX, 1, oprnds{{uint8(oprndtypeM8), false, actionR}}}, + {opcPREFETCHT1, sffxsclsNIL, 0, isasMMX, 1, oprnds{{uint8(oprndtypeM8), false, actionR}}}, + {opcPREFETCHT2, sffxsclsNIL, 0, isasMMX, 1, oprnds{{uint8(oprndtypeM8), false, actionR}}}, + {opcPSADBW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSADBW, sffxsclsNIL, featureCancellingInputs, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSHUFB, sffxsclsNIL, 0, isasSSSE3, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSHUFB, sffxsclsNIL, 0, isasSSSE3, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSHUFD, sffxsclsNIL, 0, isasSSE2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPSHUFD, sffxsclsNIL, 0, isasSSE2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPSHUFHW, sffxsclsNIL, 0, isasSSE2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSHUFHW, sffxsclsNIL, 0, isasSSE2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSHUFL, sffxsclsNIL, 0, isasSSE2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPSHUFL, sffxsclsNIL, 0, isasSSE2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPSHUFLW, sffxsclsNIL, 0, isasSSE2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSHUFLW, sffxsclsNIL, 0, isasSSE2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSIGNB, sffxsclsNIL, 0, isasSSSE3, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPSIGNB, sffxsclsNIL, 0, isasSSSE3, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPSIGND, sffxsclsNIL, 0, isasSSSE3, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPSIGND, sffxsclsNIL, 0, isasSSSE3, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPSIGNW, sffxsclsNIL, 0, isasSSSE3, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPSIGNW, sffxsclsNIL, 0, isasSSSE3, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcPSLLDQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSLLL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSLLL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSLLL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSLLO, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSLLQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSLLQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSLLQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSLLW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSLLW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSLLW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSRAL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSRAL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSRAL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSRAW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSRAW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSRAW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSRLDQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSRLL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSRLL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSRLL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSRLO, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSRLQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSRLQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSRLQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSRLW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSRLW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSRLW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSUBB, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSUBB, sffxsclsNIL, featureCancellingInputs, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSUBL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSUBL, sffxsclsNIL, featureCancellingInputs, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSUBQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSUBQ, sffxsclsNIL, featureCancellingInputs, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSUBSB, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSUBSB, sffxsclsNIL, featureCancellingInputs, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSUBSW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSUBSW, sffxsclsNIL, featureCancellingInputs, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSUBUSB, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSUBUSB, sffxsclsNIL, featureCancellingInputs, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSUBUSW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSUBUSW, sffxsclsNIL, featureCancellingInputs, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSUBW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPSUBW, sffxsclsNIL, featureCancellingInputs, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPTEST, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}}}, + {opcPTEST, sffxsclsNIL, 0, isasSSE41, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}}}, + {opcPUNPCKHBW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPUNPCKHBW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPUNPCKHLQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPUNPCKHLQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPUNPCKHQDQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPUNPCKHQDQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPUNPCKHWL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPUNPCKHWL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPUNPCKLBW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPUNPCKLBW, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPUNPCKLLQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPUNPCKLLQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPUNPCKLQDQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPUNPCKLQDQ, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPUNPCKLWL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPUNPCKLWL, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPUSHQ, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeIMM32), false, actionN}}}, + {opcPUSHQ, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeIMM8), false, actionN}}}, + {opcPUSHQ, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM64), false, actionR}}}, + {opcPUSHQ, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR64), false, actionR}}}, + {opcPUSHW, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM16), false, actionR}}}, + {opcPUSHW, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR16), false, actionR}}}, + {opcPXOR, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcPXOR, sffxsclsNIL, featureCancellingInputs, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcRCLB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcRCLB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcRCLB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcRCLB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcRCLB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcRCLB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcRCLL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcRCLL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcRCLL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcRCLL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcRCLL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcRCLL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcRCLQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcRCLQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcRCLQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcRCLQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcRCLQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcRCLQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcRCLW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcRCLW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcRCLW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcRCLW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcRCLW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcRCLW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcRCPPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcRCPPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcRCPSS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcRCPSS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcRCRB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcRCRB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcRCRB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcRCRB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcRCRB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcRCRB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcRCRL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcRCRL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcRCRL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcRCRL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcRCRL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcRCRL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcRCRQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcRCRQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcRCRQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcRCRQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcRCRQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcRCRQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcRCRW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcRCRW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcRCRW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcRCRW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcRCRW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcRCRW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcRDRANDL, sffxsclsNIL, 0, isasRDRAND, 1, oprnds{{uint8(oprndtypeR16), false, actionW}}}, + {opcRDRANDL, sffxsclsNIL, 0, isasRDRAND, 1, oprnds{{uint8(oprndtypeR32), false, actionW}}}, + {opcRDRANDL, sffxsclsNIL, 0, isasRDRAND, 1, oprnds{{uint8(oprndtypeR64), false, actionW}}}, + {opcRDSEEDL, sffxsclsNIL, 0, isasRDSEED, 1, oprnds{{uint8(oprndtypeR16), false, actionW}}}, + {opcRDSEEDL, sffxsclsNIL, 0, isasRDSEED, 1, oprnds{{uint8(oprndtypeR32), false, actionW}}}, + {opcRDSEEDL, sffxsclsNIL, 0, isasRDSEED, 1, oprnds{{uint8(oprndtypeR64), false, actionW}}}, + {opcRDTSC, sffxsclsNIL, 0, isasRDTSC, 0, oprnds{{uint8(implregEAX), true, actionW}, {uint8(implregEDX), true, actionW}}}, + {opcRDTSCP, sffxsclsNIL, 0, isasRDTSCP, 0, oprnds{{uint8(implregEAX), true, actionW}, {uint8(implregECX), true, actionW}, {uint8(implregEDX), true, actionW}}}, + {opcRET, sffxsclsNIL, featureTerminal, isasBase, 0, oprnds{}}, + {opcRETFL, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeIMM16), false, actionN}}}, + {opcRETFQ, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeIMM16), false, actionN}}}, + {opcRETFW, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeIMM16), false, actionN}}}, + {opcROLB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcROLB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcROLB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcROLB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcROLB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcROLB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcROLL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcROLL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcROLL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcROLL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcROLL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcROLL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcROLQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcROLQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcROLQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcROLQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcROLQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcROLQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcROLW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcROLW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcROLW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcROLW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcROLW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcROLW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcRORB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcRORB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcRORB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcRORB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcRORB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcRORB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcRORL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcRORL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcRORL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcRORL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcRORL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcRORL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcRORQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcRORQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcRORQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcRORQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcRORQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcRORQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcRORW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcRORW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcRORW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcRORW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcRORW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcRORW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcRORXL, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcRORXL, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcRORXQ, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcRORXQ, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcROUNDPD, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcROUNDPD, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcROUNDPS, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcROUNDPS, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcROUNDSD, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcROUNDSD, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcROUNDSS, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcROUNDSS, sffxsclsNIL, 0, isasSSE41, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcRSQRTPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcRSQRTPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcRSQRTSS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcRSQRTSS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcSALB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcSALB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcSALB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcSALB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcSALB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcSALB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcSALL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcSALL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcSALL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcSALL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcSALL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcSALL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcSALQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcSALQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcSALQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcSALQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcSALQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcSALQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcSALW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcSALW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcSALW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcSALW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcSALW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcSALW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcSARB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcSARB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcSARB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcSARB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcSARB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcSARB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcSARL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcSARL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcSARL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcSARL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcSARL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcSARL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcSARQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcSARQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcSARQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcSARQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcSARQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcSARQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcSARW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcSARW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcSARW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcSARW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcSARW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcSARW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcSARXL, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcSARXL, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcSARXQ, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcSARXQ, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcSBBB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeAL), false, actionRW}}}, + {opcSBBB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcSBBB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcSBBB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcSBBB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcSBBB, sffxsclsNIL, featureCancellingInputs, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcSBBL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeEAX), false, actionRW}}}, + {opcSBBL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcSBBL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcSBBL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcSBBL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcSBBL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcSBBL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcSBBL, sffxsclsNIL, featureCancellingInputs, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcSBBQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcSBBQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcSBBQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeRAX), false, actionRW}}}, + {opcSBBQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcSBBQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcSBBQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcSBBQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcSBBQ, sffxsclsNIL, featureCancellingInputs, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcSBBW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM16), false, actionN}, {uint8(oprndtypeAX), false, actionRW}}}, + {opcSBBW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM16), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcSBBW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM16), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcSBBW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcSBBW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcSBBW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcSBBW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcSBBW, sffxsclsNIL, featureCancellingInputs, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcSETCC, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM8), false, actionW}}}, + {opcSETCC, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR8), false, actionW}}}, + {opcSETCS, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM8), false, actionW}}}, + {opcSETCS, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR8), false, actionW}}}, + {opcSETEQ, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM8), false, actionW}}}, + {opcSETEQ, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR8), false, actionW}}}, + {opcSETGE, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM8), false, actionW}}}, + {opcSETGE, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR8), false, actionW}}}, + {opcSETGT, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM8), false, actionW}}}, + {opcSETGT, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR8), false, actionW}}}, + {opcSETHI, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM8), false, actionW}}}, + {opcSETHI, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR8), false, actionW}}}, + {opcSETLE, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM8), false, actionW}}}, + {opcSETLE, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR8), false, actionW}}}, + {opcSETLS, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM8), false, actionW}}}, + {opcSETLS, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR8), false, actionW}}}, + {opcSETLT, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM8), false, actionW}}}, + {opcSETLT, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR8), false, actionW}}}, + {opcSETMI, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM8), false, actionW}}}, + {opcSETMI, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR8), false, actionW}}}, + {opcSETNE, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM8), false, actionW}}}, + {opcSETNE, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR8), false, actionW}}}, + {opcSETOC, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM8), false, actionW}}}, + {opcSETOC, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR8), false, actionW}}}, + {opcSETOS, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM8), false, actionW}}}, + {opcSETOS, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR8), false, actionW}}}, + {opcSETPC, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM8), false, actionW}}}, + {opcSETPC, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR8), false, actionW}}}, + {opcSETPL, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM8), false, actionW}}}, + {opcSETPL, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR8), false, actionW}}}, + {opcSETPS, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeM8), false, actionW}}}, + {opcSETPS, sffxsclsNIL, 0, isasBase, 1, oprnds{{uint8(oprndtypeR8), false, actionW}}}, + {opcSFENCE, sffxsclsNIL, 0, isasMMX, 0, oprnds{}}, + {opcSHA1MSG1, sffxsclsNIL, 0, isasSHA, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcSHA1MSG1, sffxsclsNIL, 0, isasSHA, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcSHA1MSG2, sffxsclsNIL, 0, isasSHA, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcSHA1MSG2, sffxsclsNIL, 0, isasSHA, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcSHA1NEXTE, sffxsclsNIL, 0, isasSHA, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcSHA1NEXTE, sffxsclsNIL, 0, isasSHA, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcSHA1RNDS4, sffxsclsNIL, 0, isasSHA, 3, oprnds{{uint8(oprndtypeIMM2U), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcSHA1RNDS4, sffxsclsNIL, 0, isasSHA, 3, oprnds{{uint8(oprndtypeIMM2U), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcSHA256MSG1, sffxsclsNIL, 0, isasSHA, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcSHA256MSG1, sffxsclsNIL, 0, isasSHA, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcSHA256MSG2, sffxsclsNIL, 0, isasSHA, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcSHA256MSG2, sffxsclsNIL, 0, isasSHA, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcSHA256RNDS2, sffxsclsNIL, 0, isasSHA, 3, oprnds{{uint8(oprndtypeXMM0), false, actionR}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcSHA256RNDS2, sffxsclsNIL, 0, isasSHA, 3, oprnds{{uint8(oprndtypeXMM0), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcSHLB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcSHLB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcSHLB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcSHLB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcSHLB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcSHLB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcSHLL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcSHLL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcSHLL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcSHLL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcSHLL, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcSHLL, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcSHLL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcSHLL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcSHLL, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcSHLL, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcSHLQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcSHLQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcSHLQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcSHLQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcSHLQ, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcSHLQ, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcSHLQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcSHLQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcSHLQ, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcSHLQ, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcSHLW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcSHLW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcSHLW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcSHLW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcSHLW, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcSHLW, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcSHLW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcSHLW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcSHLW, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcSHLW, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcSHLXL, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcSHLXL, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcSHLXQ, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcSHLXQ, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcSHRB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcSHRB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcSHRB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcSHRB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcSHRB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcSHRB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcSHRL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcSHRL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcSHRL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcSHRL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcSHRL, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcSHRL, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcSHRL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcSHRL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcSHRL, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcSHRL, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcSHRQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcSHRQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcSHRQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcSHRQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcSHRQ, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcSHRQ, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcSHRQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcSHRQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcSHRQ, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcSHRQ, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcSHRW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcSHRW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtype1), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcSHRW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcSHRW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcSHRW, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcSHRW, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeCL), false, actionR}, {uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcSHRW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcSHRW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcSHRW, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcSHRW, sffxsclsNIL, 0, isasBase, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcSHRXL, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcSHRXL, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcSHRXQ, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcSHRXQ, sffxsclsNIL, 0, isasBMI2, 3, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcSHUFPD, sffxsclsNIL, 0, isasSSE2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcSHUFPD, sffxsclsNIL, 0, isasSSE2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcSHUFPS, sffxsclsNIL, 0, isasSSE, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcSHUFPS, sffxsclsNIL, 0, isasSSE, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcSQRTPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcSQRTPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcSQRTPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcSQRTPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcSQRTSD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcSQRTSD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcSQRTSS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcSQRTSS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcSTC, sffxsclsNIL, 0, isasBase, 0, oprnds{}}, + {opcSTD, sffxsclsNIL, 0, isasBase, 0, oprnds{}}, + {opcSTMXCSR, sffxsclsNIL, 0, isasSSE, 1, oprnds{{uint8(oprndtypeM32), false, actionW}}}, + {opcSUBB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeAL), false, actionRW}}}, + {opcSUBB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcSUBB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcSUBB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcSUBB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcSUBB, sffxsclsNIL, featureCancellingInputs, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcSUBL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeEAX), false, actionRW}}}, + {opcSUBL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcSUBL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcSUBL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcSUBL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcSUBL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcSUBL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcSUBL, sffxsclsNIL, featureCancellingInputs, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcSUBPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcSUBPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcSUBPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcSUBPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcSUBQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcSUBQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcSUBQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeRAX), false, actionRW}}}, + {opcSUBQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcSUBQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcSUBQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcSUBQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcSUBQ, sffxsclsNIL, featureCancellingInputs, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcSUBSD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcSUBSD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcSUBSS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcSUBSS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcSUBW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM16), false, actionN}, {uint8(oprndtypeAX), false, actionRW}}}, + {opcSUBW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM16), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcSUBW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM16), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcSUBW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcSUBW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcSUBW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcSUBW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcSUBW, sffxsclsNIL, featureCancellingInputs, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcSYSCALL, sffxsclsNIL, 0, isasBase, 0, oprnds{{uint8(implregR11), true, actionW}, {uint8(implregRCX), true, actionW}}}, + {opcTESTB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeAL), false, actionR}}}, + {opcTESTB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM8), false, actionR}}}, + {opcTESTB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR8), false, actionR}}}, + {opcTESTB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(oprndtypeM8), false, actionR}}}, + {opcTESTB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(oprndtypeR8), false, actionR}}}, + {opcTESTL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeEAX), false, actionR}}}, + {opcTESTL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeM32), false, actionR}}}, + {opcTESTL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeR32), false, actionR}}}, + {opcTESTL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeM32), false, actionR}}}, + {opcTESTL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionR}}}, + {opcTESTQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeM64), false, actionR}}}, + {opcTESTQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeR64), false, actionR}}}, + {opcTESTQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeRAX), false, actionR}}}, + {opcTESTQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeM64), false, actionR}}}, + {opcTESTQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionR}}}, + {opcTESTW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM16), false, actionN}, {uint8(oprndtypeAX), false, actionR}}}, + {opcTESTW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM16), false, actionN}, {uint8(oprndtypeM16), false, actionR}}}, + {opcTESTW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM16), false, actionN}, {uint8(oprndtypeR16), false, actionR}}}, + {opcTESTW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeM16), false, actionR}}}, + {opcTESTW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionR}}}, + {opcTZCNTL, sffxsclsNIL, 0, isasBMI, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcTZCNTL, sffxsclsNIL, 0, isasBMI, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcTZCNTQ, sffxsclsNIL, 0, isasBMI, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcTZCNTQ, sffxsclsNIL, 0, isasBMI, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcTZCNTW, sffxsclsNIL, 0, isasBMI, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionW}}}, + {opcTZCNTW, sffxsclsNIL, 0, isasBMI, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionW}}}, + {opcUCOMISD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}}}, + {opcUCOMISD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}}}, + {opcUCOMISS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}}}, + {opcUCOMISS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}}}, + {opcUD2, sffxsclsNIL, 0, isasBase, 0, oprnds{}}, + {opcUNPCKHPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcUNPCKHPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcUNPCKHPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcUNPCKHPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcUNPCKLPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcUNPCKLPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcUNPCKLPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcUNPCKLPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVADDPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVADDPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVADDPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVADDPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVADDPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVADDPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVADDPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVADDPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVADDPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVADDPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVADDPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVADDPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVADDPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVADDPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVADDPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVADDPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVADDPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVADDPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVADDPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVADDPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVADDPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVADDPD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVADDPD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVADDPD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVADDPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVADDPD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVADDPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVADDPD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVADDPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVADDPD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVADDPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVADDPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVADDPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVADDPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVADDPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVADDPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVADDPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVADDPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVADDPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVADDPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVADDPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVADDPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVADDPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVADDPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVADDPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVADDPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVADDPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVADDPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVADDPS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVADDPS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVADDPS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVADDPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVADDPS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVADDPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVADDPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVADDPS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVADDPS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVADDPS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVADDPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVADDPS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVADDSD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVADDSD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVADDSD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVADDSD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVADDSD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVADDSD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVADDSD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVADDSD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVADDSD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVADDSS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVADDSS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVADDSS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVADDSS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVADDSS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVADDSS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVADDSS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVADDSS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVADDSS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVADDSUBPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVADDSUBPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVADDSUBPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVADDSUBPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVADDSUBPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVADDSUBPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVADDSUBPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVADDSUBPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVAESDEC, sffxsclsNIL, 0, isasAES_AVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVAESDEC, sffxsclsNIL, 0, isasAES_AVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVAESDECLAST, sffxsclsNIL, 0, isasAES_AVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVAESDECLAST, sffxsclsNIL, 0, isasAES_AVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVAESENC, sffxsclsNIL, 0, isasAES_AVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVAESENC, sffxsclsNIL, 0, isasAES_AVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVAESENCLAST, sffxsclsNIL, 0, isasAES_AVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVAESENCLAST, sffxsclsNIL, 0, isasAES_AVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVAESIMC, sffxsclsNIL, 0, isasAES_AVX, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVAESIMC, sffxsclsNIL, 0, isasAES_AVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVAESKEYGENASSIST, sffxsclsNIL, 0, isasAES_AVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVAESKEYGENASSIST, sffxsclsNIL, 0, isasAES_AVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVALIGND, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVALIGND, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVALIGND, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVALIGND, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVALIGND, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVALIGND, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVALIGND, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVALIGND, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVALIGND, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVALIGND, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVALIGND, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVALIGND, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVALIGND, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVALIGND, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVALIGND, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVALIGND, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVALIGND, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVALIGND, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVALIGND, sffxsclsBCST, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVALIGND, sffxsclsBCST_Z, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVALIGND, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVALIGND, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVALIGND, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVALIGND, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVALIGND, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVALIGND, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVALIGND, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVALIGNQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVALIGNQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVALIGNQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVALIGNQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVALIGNQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVALIGNQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVALIGNQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVALIGNQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVALIGNQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVALIGNQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVALIGNQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVALIGNQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVALIGNQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVALIGNQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVALIGNQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVALIGNQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVALIGNQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVALIGNQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVALIGNQ, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVALIGNQ, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVALIGNQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVALIGNQ, sffxsclsBCST, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVALIGNQ, sffxsclsBCST_Z, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVALIGNQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVALIGNQ, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVALIGNQ, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVALIGNQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVANDNPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVANDNPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVANDNPD, sffxsclsNIL, featureCancellingInputs, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVANDNPD, sffxsclsNIL, featureCancellingInputs, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVANDNPD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVANDNPD, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVANDNPD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVANDNPD, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVANDNPD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVANDNPD, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVANDNPD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVANDNPD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVANDNPD, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVANDNPD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVANDNPD, sffxsclsNIL, featureCancellingInputs, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVANDNPD, sffxsclsZ, featureCancellingInputs, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVANDNPD, sffxsclsNIL, featureCancellingInputs, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVANDNPD, sffxsclsZ, featureCancellingInputs, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVANDNPD, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVANDNPD, sffxsclsZ, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVANDNPD, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVANDNPD, sffxsclsBCST, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVANDNPD, sffxsclsBCST_Z, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVANDNPD, sffxsclsBCST, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVANDNPD, sffxsclsNIL, featureCancellingInputs, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVANDNPD, sffxsclsZ, featureCancellingInputs, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVANDNPD, sffxsclsNIL, featureCancellingInputs, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVANDNPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVANDNPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVANDNPS, sffxsclsNIL, featureCancellingInputs, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVANDNPS, sffxsclsNIL, featureCancellingInputs, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVANDNPS, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVANDNPS, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVANDNPS, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVANDNPS, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVANDNPS, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVANDNPS, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVANDNPS, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVANDNPS, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVANDNPS, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVANDNPS, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVANDNPS, sffxsclsNIL, featureCancellingInputs, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVANDNPS, sffxsclsZ, featureCancellingInputs, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVANDNPS, sffxsclsNIL, featureCancellingInputs, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVANDNPS, sffxsclsZ, featureCancellingInputs, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVANDNPS, sffxsclsBCST, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVANDNPS, sffxsclsBCST_Z, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVANDNPS, sffxsclsBCST, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVANDNPS, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVANDNPS, sffxsclsZ, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVANDNPS, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVANDNPS, sffxsclsNIL, featureCancellingInputs, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVANDNPS, sffxsclsZ, featureCancellingInputs, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVANDNPS, sffxsclsNIL, featureCancellingInputs, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVANDPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVANDPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVANDPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVANDPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVANDPD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVANDPD, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVANDPD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVANDPD, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVANDPD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVANDPD, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVANDPD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVANDPD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVANDPD, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVANDPD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVANDPD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVANDPD, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVANDPD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVANDPD, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVANDPD, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVANDPD, sffxsclsZ, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVANDPD, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVANDPD, sffxsclsBCST, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVANDPD, sffxsclsBCST_Z, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVANDPD, sffxsclsBCST, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVANDPD, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVANDPD, sffxsclsZ, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVANDPD, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVANDPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVANDPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVANDPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVANDPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVANDPS, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVANDPS, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVANDPS, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVANDPS, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVANDPS, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVANDPS, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVANDPS, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVANDPS, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVANDPS, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVANDPS, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVANDPS, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVANDPS, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVANDPS, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVANDPS, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVANDPS, sffxsclsBCST, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVANDPS, sffxsclsBCST_Z, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVANDPS, sffxsclsBCST, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVANDPS, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVANDPS, sffxsclsZ, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVANDPS, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVANDPS, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVANDPS, sffxsclsZ, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVANDPS, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBLENDMPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVBLENDMPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVBLENDMPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVBLENDMPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVBLENDMPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBLENDMPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBLENDMPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVBLENDMPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVBLENDMPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVBLENDMPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVBLENDMPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBLENDMPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBLENDMPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVBLENDMPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVBLENDMPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVBLENDMPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVBLENDMPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBLENDMPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBLENDMPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVBLENDMPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBLENDMPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBLENDMPD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVBLENDMPD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBLENDMPD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBLENDMPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVBLENDMPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBLENDMPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBLENDMPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVBLENDMPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVBLENDMPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVBLENDMPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVBLENDMPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBLENDMPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBLENDMPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVBLENDMPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVBLENDMPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVBLENDMPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVBLENDMPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBLENDMPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBLENDMPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVBLENDMPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVBLENDMPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVBLENDMPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVBLENDMPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBLENDMPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBLENDMPS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVBLENDMPS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBLENDMPS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBLENDMPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVBLENDMPS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBLENDMPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBLENDMPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVBLENDMPS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBLENDMPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBLENDPD, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVBLENDPD, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBLENDPD, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVBLENDPD, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBLENDPS, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVBLENDPS, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBLENDPS, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVBLENDPS, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBLENDVPD, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVBLENDVPD, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVBLENDVPD, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBLENDVPD, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBLENDVPS, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVBLENDVPS, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVBLENDVPS, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBLENDVPS, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBROADCASTF128, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBROADCASTF32X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVBROADCASTF32X2, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBROADCASTF32X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBROADCASTF32X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVBROADCASTF32X2, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBROADCASTF32X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBROADCASTF32X2, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVBROADCASTF32X2, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBROADCASTF32X2, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBROADCASTF32X2, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVBROADCASTF32X2, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBROADCASTF32X2, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBROADCASTF32X4, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVBROADCASTF32X4, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBROADCASTF32X4, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBROADCASTF32X4, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVBROADCASTF32X4, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBROADCASTF32X4, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBROADCASTF32X8, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVBROADCASTF32X8, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBROADCASTF32X8, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBROADCASTF64X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVBROADCASTF64X2, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBROADCASTF64X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBROADCASTF64X2, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVBROADCASTF64X2, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBROADCASTF64X2, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBROADCASTF64X4, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVBROADCASTF64X4, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBROADCASTF64X4, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBROADCASTI128, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBROADCASTI32X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVBROADCASTI32X2, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVBROADCASTI32X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVBROADCASTI32X2, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBROADCASTI32X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVBROADCASTI32X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBROADCASTI32X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVBROADCASTI32X2, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVBROADCASTI32X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVBROADCASTI32X2, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBROADCASTI32X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVBROADCASTI32X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBROADCASTI32X2, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVBROADCASTI32X2, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBROADCASTI32X2, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBROADCASTI32X2, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVBROADCASTI32X2, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBROADCASTI32X2, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBROADCASTI32X4, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVBROADCASTI32X4, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBROADCASTI32X4, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBROADCASTI32X4, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVBROADCASTI32X4, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBROADCASTI32X4, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBROADCASTI32X8, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVBROADCASTI32X8, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBROADCASTI32X8, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBROADCASTI64X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVBROADCASTI64X2, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBROADCASTI64X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBROADCASTI64X2, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVBROADCASTI64X2, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBROADCASTI64X2, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBROADCASTI64X4, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVBROADCASTI64X4, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBROADCASTI64X4, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBROADCASTSD, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBROADCASTSD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBROADCASTSD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVBROADCASTSD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBROADCASTSD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVBROADCASTSD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBROADCASTSD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVBROADCASTSD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBROADCASTSD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBROADCASTSD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVBROADCASTSD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBROADCASTSD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBROADCASTSS, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVBROADCASTSS, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBROADCASTSS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVBROADCASTSS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBROADCASTSS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVBROADCASTSS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBROADCASTSS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVBROADCASTSS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVBROADCASTSS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVBROADCASTSS, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBROADCASTSS, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBROADCASTSS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVBROADCASTSS, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVBROADCASTSS, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCMPPD, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCMPPD, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCMPPD, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCMPPD, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCMPPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPD, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPD, sffxsclsBCST, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPD, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPD, sffxsclsSAE, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPD, sffxsclsSAE, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPS, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCMPPS, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCMPPS, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCMPPS, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCMPPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPS, sffxsclsBCST, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPS, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPS, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPS, sffxsclsSAE, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPPS, sffxsclsSAE, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPSD, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCMPSD, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCMPSD, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPSD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPSD, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPSD, sffxsclsSAE, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPSD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPSD, sffxsclsSAE, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPSS, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCMPSS, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCMPSS, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPSS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPSS, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPSS, sffxsclsSAE, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPSS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCMPSS, sffxsclsSAE, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVCOMISD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}}}, + {opcVCOMISD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}}}, + {opcVCOMISD, sffxsclsSAE, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}}}, + {opcVCOMISS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}}}, + {opcVCOMISS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}}}, + {opcVCOMISS, sffxsclsSAE, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}}}, + {opcVCOMPRESSPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVCOMPRESSPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVCOMPRESSPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCOMPRESSPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCOMPRESSPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVCOMPRESSPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCOMPRESSPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionRW}}}, + {opcVCOMPRESSPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVCOMPRESSPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCOMPRESSPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCOMPRESSPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVCOMPRESSPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCOMPRESSPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM512), false, actionRW}}}, + {opcVCOMPRESSPD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM512), false, actionW}}}, + {opcVCOMPRESSPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCOMPRESSPD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCOMPRESSPD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM512), false, actionW}}}, + {opcVCOMPRESSPD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCOMPRESSPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVCOMPRESSPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVCOMPRESSPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCOMPRESSPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCOMPRESSPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVCOMPRESSPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCOMPRESSPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionRW}}}, + {opcVCOMPRESSPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVCOMPRESSPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCOMPRESSPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCOMPRESSPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVCOMPRESSPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCOMPRESSPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM512), false, actionRW}}}, + {opcVCOMPRESSPS, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM512), false, actionW}}}, + {opcVCOMPRESSPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCOMPRESSPS, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCOMPRESSPS, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM512), false, actionW}}}, + {opcVCOMPRESSPS, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTDQ2PD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTDQ2PD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTDQ2PD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTDQ2PD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTDQ2PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTDQ2PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTDQ2PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTDQ2PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTDQ2PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTDQ2PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTDQ2PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTDQ2PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTDQ2PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTDQ2PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTDQ2PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTDQ2PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTDQ2PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTDQ2PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTDQ2PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTDQ2PD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTDQ2PD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTDQ2PD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTDQ2PD, sffxsclsBCST_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTDQ2PD, sffxsclsBCST, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTDQ2PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTDQ2PD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTDQ2PD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTDQ2PS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTDQ2PS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTDQ2PS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTDQ2PS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTDQ2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTDQ2PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTDQ2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTDQ2PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTDQ2PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTDQ2PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTDQ2PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTDQ2PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTDQ2PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTDQ2PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTDQ2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTDQ2PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTDQ2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTDQ2PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTDQ2PS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTDQ2PS, sffxsclsBCST_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTDQ2PS, sffxsclsBCST, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTDQ2PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTDQ2PS, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTDQ2PS, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTDQ2PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTDQ2PS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTDQ2PS, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTDQ2PS, sffxsclsER_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTDQ2PS, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTDQ2PS, sffxsclsER, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPD2DQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPD2DQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2DQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2DQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPD2DQ, sffxsclsBCST_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2DQ, sffxsclsBCST, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2DQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPD2DQ, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPD2DQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2DQ, sffxsclsER_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2DQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2DQ, sffxsclsER, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2DQX, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2DQX, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2DQX, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPD2DQX, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2DQX, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPD2DQX, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2DQX, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2DQX, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPD2DQX, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2DQY, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2DQY, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2DQY, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPD2DQY, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2DQY, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPD2DQY, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2DQY, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2DQY, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPD2DQY, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPD2PS, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2PS, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2PS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPD2PS, sffxsclsBCST_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2PS, sffxsclsBCST, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPD2PS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPD2PS, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2PS, sffxsclsER_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2PS, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2PS, sffxsclsER, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2PSX, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2PSX, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2PSX, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPD2PSX, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2PSX, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPD2PSX, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2PSX, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2PSX, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPD2PSX, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2PSY, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2PSY, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2PSY, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPD2PSY, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2PSY, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPD2PSY, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2PSY, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2PSY, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPD2PSY, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPD2QQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPD2QQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2QQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPD2QQ, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2QQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPD2QQ, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2QQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2QQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPD2QQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPD2QQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2QQ, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTPD2QQ, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPD2QQ, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPD2QQ, sffxsclsBCST, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTPD2QQ, sffxsclsBCST_Z, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPD2QQ, sffxsclsBCST, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPD2QQ, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTPD2QQ, sffxsclsER, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTPD2QQ, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPD2QQ, sffxsclsER_Z, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPD2QQ, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPD2QQ, sffxsclsER, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPD2UDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPD2UDQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2UDQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2UDQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPD2UDQ, sffxsclsBCST_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2UDQ, sffxsclsBCST, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2UDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPD2UDQ, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPD2UDQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2UDQ, sffxsclsER_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2UDQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2UDQ, sffxsclsER, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2UDQX, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPD2UDQX, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2UDQX, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2UDQX, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPD2UDQX, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2UDQX, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2UDQX, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPD2UDQX, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2UDQX, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2UDQY, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPD2UDQY, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2UDQY, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2UDQY, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPD2UDQY, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2UDQY, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2UDQY, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPD2UDQY, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2UDQY, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPD2UQQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPD2UQQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2UQQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPD2UQQ, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2UQQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPD2UQQ, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2UQQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2UQQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPD2UQQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPD2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPD2UQQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPD2UQQ, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTPD2UQQ, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPD2UQQ, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPD2UQQ, sffxsclsBCST, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTPD2UQQ, sffxsclsBCST_Z, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPD2UQQ, sffxsclsBCST, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPD2UQQ, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTPD2UQQ, sffxsclsER, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTPD2UQQ, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPD2UQQ, sffxsclsER_Z, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPD2UQQ, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPD2UQQ, sffxsclsER, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPH2PS, sffxsclsNIL, 0, isasF16C, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPH2PS, sffxsclsNIL, 0, isasF16C, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPH2PS, sffxsclsNIL, 0, isasF16C, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPH2PS, sffxsclsNIL, 0, isasF16C, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPH2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPH2PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPH2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPH2PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPH2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPH2PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPH2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPH2PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPH2PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTPH2PS, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPH2PS, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPH2PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTPH2PS, sffxsclsSAE, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTPH2PS, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPH2PS, sffxsclsSAE_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPH2PS, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPH2PS, sffxsclsSAE, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2DQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2DQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2DQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2DQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2DQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPS2DQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2DQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPS2DQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2DQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPS2DQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2DQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPS2DQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2DQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2DQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2DQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPS2DQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2DQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPS2DQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2DQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTPS2DQ, sffxsclsBCST_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2DQ, sffxsclsBCST, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2DQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTPS2DQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2DQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2DQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTPS2DQ, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTPS2DQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2DQ, sffxsclsER_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2DQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2DQ, sffxsclsER, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2PD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2PD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2PD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2PD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPS2PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPS2PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPS2PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTPS2PD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2PD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2PD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTPS2PD, sffxsclsBCST_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2PD, sffxsclsBCST, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTPS2PD, sffxsclsSAE, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTPS2PD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2PD, sffxsclsSAE_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2PD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2PD, sffxsclsSAE, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2PD, sffxsclsNIL, 0, isasAVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPS2PD, sffxsclsZ, 0, isasAVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2PD, sffxsclsBCST, 0, isasAVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPS2PD, sffxsclsBCST_Z, 0, isasAVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2PD, sffxsclsBCST, 0, isasAVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2PD, sffxsclsNIL, 0, isasAVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPS2PD, sffxsclsZ, 0, isasAVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2PH, sffxsclsNIL, 0, isasF16C, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVCVTPS2PH, sffxsclsNIL, 0, isasF16C, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2PH, sffxsclsNIL, 0, isasF16C, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVCVTPS2PH, sffxsclsNIL, 0, isasF16C, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2PH, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcVCVTPS2PH, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVCVTPS2PH, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPS2PH, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2PH, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVCVTPS2PH, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVCVTPS2PH, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPS2PH, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2PH, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionRW}}}, + {opcVCVTPS2PH, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVCVTPS2PH, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPS2PH, sffxsclsSAE, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPS2PH, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2PH, sffxsclsSAE_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2PH, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVCVTPS2PH, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2PH, sffxsclsSAE, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPS2QQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2QQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPS2QQ, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2QQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPS2QQ, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2QQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2QQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPS2QQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPS2QQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPS2QQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2QQ, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTPS2QQ, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2QQ, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2QQ, sffxsclsBCST, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTPS2QQ, sffxsclsBCST_Z, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2QQ, sffxsclsBCST, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2QQ, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTPS2QQ, sffxsclsER, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTPS2QQ, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2QQ, sffxsclsER_Z, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2QQ, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2QQ, sffxsclsER, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2UDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPS2UDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2UDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2UDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPS2UDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2UDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2UDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPS2UDQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2UDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPS2UDQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2UDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2UDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2UDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPS2UDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2UDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2UDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPS2UDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2UDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2UDQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTPS2UDQ, sffxsclsBCST_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2UDQ, sffxsclsBCST, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2UDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTPS2UDQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2UDQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2UDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTPS2UDQ, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTPS2UDQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2UDQ, sffxsclsER_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2UDQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2UDQ, sffxsclsER, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPS2UQQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2UQQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPS2UQQ, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2UQQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPS2UQQ, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2UQQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2UQQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPS2UQQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTPS2UQQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTPS2UQQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTPS2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTPS2UQQ, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTPS2UQQ, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2UQQ, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2UQQ, sffxsclsBCST, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTPS2UQQ, sffxsclsBCST_Z, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2UQQ, sffxsclsBCST, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2UQQ, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTPS2UQQ, sffxsclsER, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTPS2UQQ, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2UQQ, sffxsclsER_Z, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2UQQ, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTPS2UQQ, sffxsclsER, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTQQ2PD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTQQ2PD, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTQQ2PD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTQQ2PD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTQQ2PD, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTQQ2PD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTQQ2PD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTQQ2PD, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTQQ2PD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTQQ2PD, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTQQ2PD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTQQ2PD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTQQ2PD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTQQ2PD, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTQQ2PD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTQQ2PD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTQQ2PD, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTQQ2PD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTQQ2PD, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTQQ2PD, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTQQ2PD, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTQQ2PD, sffxsclsBCST, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTQQ2PD, sffxsclsBCST_Z, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTQQ2PD, sffxsclsBCST, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTQQ2PD, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTQQ2PD, sffxsclsER, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTQQ2PD, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTQQ2PD, sffxsclsER_Z, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTQQ2PD, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTQQ2PD, sffxsclsER, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTQQ2PS, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTQQ2PS, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTQQ2PS, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTQQ2PS, sffxsclsBCST, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTQQ2PS, sffxsclsBCST_Z, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTQQ2PS, sffxsclsBCST, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTQQ2PS, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTQQ2PS, sffxsclsER, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTQQ2PS, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTQQ2PS, sffxsclsER_Z, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTQQ2PS, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTQQ2PS, sffxsclsER, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTQQ2PSX, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTQQ2PSX, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTQQ2PSX, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTQQ2PSX, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTQQ2PSX, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTQQ2PSX, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTQQ2PSX, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTQQ2PSX, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTQQ2PSX, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTQQ2PSY, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTQQ2PSY, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTQQ2PSY, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTQQ2PSY, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTQQ2PSY, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTQQ2PSY, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTQQ2PSY, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTQQ2PSY, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTQQ2PSY, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTSD2SI, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVCVTSD2SI, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVCVTSD2SI, sffxsclsER, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVCVTSD2SIQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcVCVTSD2SIQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcVCVTSD2SIQ, sffxsclsER, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcVCVTSD2SS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTSD2SS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTSD2SS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTSD2SS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTSD2SS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTSD2SS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTSD2SS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTSD2SS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTSD2SS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTSD2USIL, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVCVTSD2USIL, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVCVTSD2USIL, sffxsclsER, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVCVTSD2USIQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcVCVTSD2USIQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcVCVTSD2USIQ, sffxsclsER, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcVCVTSI2SDL, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTSI2SDL, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTSI2SDQ, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTSI2SDQ, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTSI2SDQ, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTSI2SSL, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTSI2SSL, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTSI2SSL, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTSI2SSQ, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTSI2SSQ, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTSI2SSQ, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTSS2SD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTSS2SD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTSS2SD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTSS2SD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTSS2SD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTSS2SD, sffxsclsSAE, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTSS2SD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTSS2SD, sffxsclsSAE_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTSS2SD, sffxsclsSAE, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTSS2SI, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVCVTSS2SI, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVCVTSS2SI, sffxsclsER, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVCVTSS2SIQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcVCVTSS2SIQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcVCVTSS2SIQ, sffxsclsER, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcVCVTSS2USIL, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVCVTSS2USIL, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVCVTSS2USIL, sffxsclsER, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVCVTSS2USIQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcVCVTSS2USIQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcVCVTSS2USIQ, sffxsclsER, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcVCVTTPD2DQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTTPD2DQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPD2DQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPD2DQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTTPD2DQ, sffxsclsBCST_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPD2DQ, sffxsclsBCST, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPD2DQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTTPD2DQ, sffxsclsSAE, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTTPD2DQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPD2DQ, sffxsclsSAE_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPD2DQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPD2DQ, sffxsclsSAE, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPD2DQX, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2DQX, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2DQX, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTTPD2DQX, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2DQX, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTTPD2DQX, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2DQX, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2DQX, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTTPD2DQX, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2DQY, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2DQY, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2DQY, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTTPD2DQY, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2DQY, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTTPD2DQY, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2DQY, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2DQY, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTTPD2DQY, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTTPD2QQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTTPD2QQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPD2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPD2QQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTTPD2QQ, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2QQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTTPD2QQ, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPD2QQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2QQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPD2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTTPD2QQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTTPD2QQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPD2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPD2QQ, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTTPD2QQ, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPD2QQ, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPD2QQ, sffxsclsBCST, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTTPD2QQ, sffxsclsBCST_Z, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPD2QQ, sffxsclsBCST, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPD2QQ, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTTPD2QQ, sffxsclsSAE, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTTPD2QQ, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPD2QQ, sffxsclsSAE_Z, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPD2QQ, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPD2QQ, sffxsclsSAE, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPD2UDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTTPD2UDQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPD2UDQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPD2UDQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTTPD2UDQ, sffxsclsBCST_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPD2UDQ, sffxsclsBCST, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPD2UDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTTPD2UDQ, sffxsclsSAE, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTTPD2UDQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPD2UDQ, sffxsclsSAE_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPD2UDQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPD2UDQ, sffxsclsSAE, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPD2UDQX, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTTPD2UDQX, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2UDQX, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2UDQX, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTTPD2UDQX, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2UDQX, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2UDQX, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTTPD2UDQX, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2UDQX, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2UDQY, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTTPD2UDQY, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2UDQY, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2UDQY, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTTPD2UDQY, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2UDQY, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2UDQY, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTTPD2UDQY, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2UDQY, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTTPD2UQQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTTPD2UQQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPD2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPD2UQQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTTPD2UQQ, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2UQQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTTPD2UQQ, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPD2UQQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2UQQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPD2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTTPD2UQQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPD2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTTPD2UQQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPD2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPD2UQQ, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTTPD2UQQ, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPD2UQQ, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPD2UQQ, sffxsclsBCST, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTTPD2UQQ, sffxsclsBCST_Z, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPD2UQQ, sffxsclsBCST, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPD2UQQ, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTTPD2UQQ, sffxsclsSAE, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTTPD2UQQ, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPD2UQQ, sffxsclsSAE_Z, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPD2UQQ, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPD2UQQ, sffxsclsSAE, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2DQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPS2DQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPS2DQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPS2DQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPS2DQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTTPS2DQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPS2DQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTTPS2DQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPS2DQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTTPS2DQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPS2DQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTTPS2DQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPS2DQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPS2DQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPS2DQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTTPS2DQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPS2DQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTTPS2DQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPS2DQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTTPS2DQ, sffxsclsBCST_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2DQ, sffxsclsBCST, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2DQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTTPS2DQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2DQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2DQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTTPS2DQ, sffxsclsSAE, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTTPS2DQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2DQ, sffxsclsSAE_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2DQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2DQ, sffxsclsSAE, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTTPS2QQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPS2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPS2QQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTTPS2QQ, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPS2QQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTTPS2QQ, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPS2QQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPS2QQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPS2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTTPS2QQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPS2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPS2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTTPS2QQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPS2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTTPS2QQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPS2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPS2QQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPS2QQ, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTTPS2QQ, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2QQ, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2QQ, sffxsclsBCST, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTTPS2QQ, sffxsclsBCST_Z, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2QQ, sffxsclsBCST, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2QQ, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTTPS2QQ, sffxsclsSAE, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTTPS2QQ, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2QQ, sffxsclsSAE_Z, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2QQ, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2QQ, sffxsclsSAE, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2UDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTTPS2UDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPS2UDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPS2UDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTTPS2UDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPS2UDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPS2UDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTTPS2UDQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPS2UDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTTPS2UDQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPS2UDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPS2UDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPS2UDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTTPS2UDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPS2UDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPS2UDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTTPS2UDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPS2UDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPS2UDQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTTPS2UDQ, sffxsclsBCST_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2UDQ, sffxsclsBCST, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2UDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTTPS2UDQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2UDQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2UDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTTPS2UDQ, sffxsclsSAE, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTTPS2UDQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2UDQ, sffxsclsSAE_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2UDQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2UDQ, sffxsclsSAE, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTTPS2UQQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPS2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPS2UQQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTTPS2UQQ, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPS2UQQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTTPS2UQQ, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPS2UQQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPS2UQQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPS2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTTPS2UQQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPS2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPS2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTTPS2UQQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPS2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTTPS2UQQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPS2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTTPS2UQQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTTPS2UQQ, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTTPS2UQQ, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2UQQ, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2UQQ, sffxsclsBCST, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTTPS2UQQ, sffxsclsBCST_Z, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2UQQ, sffxsclsBCST, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2UQQ, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTTPS2UQQ, sffxsclsSAE, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTTPS2UQQ, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2UQQ, sffxsclsSAE_Z, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2UQQ, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTPS2UQQ, sffxsclsSAE, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTTSD2SI, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVCVTTSD2SI, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVCVTTSD2SI, sffxsclsSAE, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVCVTTSD2SIQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcVCVTTSD2SIQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcVCVTTSD2SIQ, sffxsclsSAE, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcVCVTTSD2USIL, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVCVTTSD2USIL, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVCVTTSD2USIL, sffxsclsSAE, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVCVTTSD2USIQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcVCVTTSD2USIQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcVCVTTSD2USIQ, sffxsclsSAE, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcVCVTTSS2SI, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVCVTTSS2SI, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVCVTTSS2SI, sffxsclsSAE, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVCVTTSS2SIQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcVCVTTSS2SIQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcVCVTTSS2SIQ, sffxsclsSAE, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcVCVTTSS2USIL, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVCVTTSS2USIL, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVCVTTSS2USIL, sffxsclsSAE, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVCVTTSS2USIQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcVCVTTSS2USIQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcVCVTTSS2USIQ, sffxsclsSAE, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcVCVTUDQ2PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTUDQ2PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTUDQ2PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTUDQ2PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTUDQ2PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUDQ2PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTUDQ2PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTUDQ2PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUDQ2PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTUDQ2PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTUDQ2PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUDQ2PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUDQ2PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTUDQ2PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUDQ2PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTUDQ2PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTUDQ2PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUDQ2PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTUDQ2PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTUDQ2PD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTUDQ2PD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTUDQ2PD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTUDQ2PD, sffxsclsBCST_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTUDQ2PD, sffxsclsBCST, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTUDQ2PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTUDQ2PD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTUDQ2PD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTUDQ2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTUDQ2PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUDQ2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUDQ2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTUDQ2PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTUDQ2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTUDQ2PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTUDQ2PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUDQ2PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTUDQ2PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTUDQ2PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUDQ2PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTUDQ2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTUDQ2PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUDQ2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUDQ2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTUDQ2PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTUDQ2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTUDQ2PS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTUDQ2PS, sffxsclsBCST_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTUDQ2PS, sffxsclsBCST, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTUDQ2PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTUDQ2PS, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTUDQ2PS, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTUDQ2PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTUDQ2PS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTUDQ2PS, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTUDQ2PS, sffxsclsER_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTUDQ2PS, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTUDQ2PS, sffxsclsER, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTUQQ2PD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTUQQ2PD, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUQQ2PD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUQQ2PD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTUQQ2PD, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTUQQ2PD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTUQQ2PD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTUQQ2PD, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUQQ2PD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTUQQ2PD, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTUQQ2PD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUQQ2PD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTUQQ2PD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTUQQ2PD, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUQQ2PD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUQQ2PD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTUQQ2PD, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTUQQ2PD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTUQQ2PD, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTUQQ2PD, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTUQQ2PD, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTUQQ2PD, sffxsclsBCST, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTUQQ2PD, sffxsclsBCST_Z, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTUQQ2PD, sffxsclsBCST, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTUQQ2PD, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTUQQ2PD, sffxsclsER, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVCVTUQQ2PD, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTUQQ2PD, sffxsclsER_Z, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTUQQ2PD, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTUQQ2PD, sffxsclsER, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVCVTUQQ2PS, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTUQQ2PS, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTUQQ2PS, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTUQQ2PS, sffxsclsBCST, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTUQQ2PS, sffxsclsBCST_Z, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTUQQ2PS, sffxsclsBCST, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTUQQ2PS, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTUQQ2PS, sffxsclsER, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVCVTUQQ2PS, sffxsclsZ, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTUQQ2PS, sffxsclsER_Z, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTUQQ2PS, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTUQQ2PS, sffxsclsER, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVCVTUQQ2PSX, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTUQQ2PSX, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUQQ2PSX, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUQQ2PSX, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTUQQ2PSX, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUQQ2PSX, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUQQ2PSX, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTUQQ2PSX, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUQQ2PSX, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUQQ2PSY, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTUQQ2PSY, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUQQ2PSY, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUQQ2PSY, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTUQQ2PSY, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUQQ2PSY, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUQQ2PSY, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVCVTUQQ2PSY, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUQQ2PSY, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUSI2SDL, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUSI2SDL, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUSI2SDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUSI2SDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUSI2SDQ, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUSI2SSL, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUSI2SSL, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUSI2SSL, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUSI2SSQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUSI2SSQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVCVTUSI2SSQ, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDBPSADBW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVDBPSADBW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDBPSADBW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDBPSADBW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVDBPSADBW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVDBPSADBW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVDBPSADBW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVDBPSADBW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDBPSADBW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDBPSADBW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVDBPSADBW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVDBPSADBW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVDBPSADBW, sffxsclsNIL, 0, isasAVX512BW, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVDBPSADBW, sffxsclsZ, 0, isasAVX512BW, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVDBPSADBW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVDBPSADBW, sffxsclsNIL, 0, isasAVX512BW, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVDBPSADBW, sffxsclsZ, 0, isasAVX512BW, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVDBPSADBW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVDIVPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDIVPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVDIVPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDIVPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVDIVPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVDIVPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDIVPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVDIVPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVDIVPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVDIVPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDIVPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDIVPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVDIVPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVDIVPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVDIVPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVDIVPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDIVPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVDIVPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVDIVPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVDIVPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVDIVPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVDIVPD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVDIVPD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVDIVPD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVDIVPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVDIVPD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVDIVPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVDIVPD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVDIVPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVDIVPD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVDIVPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDIVPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVDIVPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDIVPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVDIVPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVDIVPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDIVPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVDIVPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVDIVPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVDIVPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDIVPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDIVPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVDIVPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVDIVPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVDIVPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVDIVPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDIVPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVDIVPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVDIVPS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVDIVPS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVDIVPS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVDIVPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVDIVPS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVDIVPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVDIVPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVDIVPS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVDIVPS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVDIVPS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVDIVPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVDIVPS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVDIVSD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDIVSD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDIVSD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVDIVSD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDIVSD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVDIVSD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVDIVSD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDIVSD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDIVSD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDIVSS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDIVSS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDIVSS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVDIVSS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDIVSS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVDIVSS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVDIVSS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDIVSS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDIVSS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDPPD, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDPPD, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDPPS, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDPPS, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVDPPS, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVDPPS, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVEXP2PD, sffxsclsNIL, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVEXP2PD, sffxsclsZ, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVEXP2PD, sffxsclsNIL, 0, isasAVX512ER, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVEXP2PD, sffxsclsBCST, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVEXP2PD, sffxsclsBCST_Z, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVEXP2PD, sffxsclsBCST, 0, isasAVX512ER, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVEXP2PD, sffxsclsNIL, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVEXP2PD, sffxsclsSAE, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVEXP2PD, sffxsclsZ, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVEXP2PD, sffxsclsSAE_Z, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVEXP2PD, sffxsclsNIL, 0, isasAVX512ER, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVEXP2PD, sffxsclsSAE, 0, isasAVX512ER, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVEXP2PS, sffxsclsBCST, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVEXP2PS, sffxsclsBCST_Z, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVEXP2PS, sffxsclsBCST, 0, isasAVX512ER, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVEXP2PS, sffxsclsNIL, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVEXP2PS, sffxsclsZ, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVEXP2PS, sffxsclsNIL, 0, isasAVX512ER, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVEXP2PS, sffxsclsNIL, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVEXP2PS, sffxsclsSAE, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVEXP2PS, sffxsclsZ, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVEXP2PS, sffxsclsSAE_Z, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVEXP2PS, sffxsclsNIL, 0, isasAVX512ER, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVEXP2PS, sffxsclsSAE, 0, isasAVX512ER, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVEXPANDPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVEXPANDPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVEXPANDPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVEXPANDPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVEXPANDPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVEXPANDPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVEXPANDPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVEXPANDPD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVEXPANDPD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVEXPANDPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVEXPANDPD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVEXPANDPD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVEXPANDPD, sffxsclsNIL, 0, isasAVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVEXPANDPD, sffxsclsZ, 0, isasAVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVEXPANDPD, sffxsclsNIL, 0, isasAVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVEXPANDPD, sffxsclsNIL, 0, isasAVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVEXPANDPD, sffxsclsZ, 0, isasAVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVEXPANDPD, sffxsclsNIL, 0, isasAVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVEXPANDPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVEXPANDPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVEXPANDPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVEXPANDPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVEXPANDPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVEXPANDPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVEXPANDPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVEXPANDPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVEXPANDPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVEXPANDPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVEXPANDPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVEXPANDPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVEXPANDPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVEXPANDPS, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVEXPANDPS, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVEXPANDPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVEXPANDPS, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVEXPANDPS, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVEXTRACTF128, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVEXTRACTF128, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVEXTRACTF32X4, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVEXTRACTF32X4, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVEXTRACTF32X4, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVEXTRACTF32X4, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVEXTRACTF32X4, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVEXTRACTF32X4, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVEXTRACTF32X4, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVEXTRACTF32X4, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVEXTRACTF32X4, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVEXTRACTF32X4, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVEXTRACTF32X4, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVEXTRACTF32X4, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVEXTRACTF32X8, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionRW}}}, + {opcVEXTRACTF32X8, sffxsclsZ, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVEXTRACTF32X8, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVEXTRACTF32X8, sffxsclsZ, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVEXTRACTF32X8, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVEXTRACTF32X8, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVEXTRACTF64X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVEXTRACTF64X2, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVEXTRACTF64X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVEXTRACTF64X2, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVEXTRACTF64X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVEXTRACTF64X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVEXTRACTF64X2, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVEXTRACTF64X2, sffxsclsZ, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVEXTRACTF64X2, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVEXTRACTF64X2, sffxsclsZ, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVEXTRACTF64X2, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVEXTRACTF64X2, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVEXTRACTF64X4, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionRW}}}, + {opcVEXTRACTF64X4, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVEXTRACTF64X4, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVEXTRACTF64X4, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVEXTRACTF64X4, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVEXTRACTF64X4, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVEXTRACTI128, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVEXTRACTI128, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVEXTRACTI32X4, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVEXTRACTI32X4, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVEXTRACTI32X4, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVEXTRACTI32X4, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVEXTRACTI32X4, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVEXTRACTI32X4, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVEXTRACTI32X4, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVEXTRACTI32X4, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVEXTRACTI32X4, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVEXTRACTI32X4, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVEXTRACTI32X4, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVEXTRACTI32X4, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVEXTRACTI32X8, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionRW}}}, + {opcVEXTRACTI32X8, sffxsclsZ, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVEXTRACTI32X8, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVEXTRACTI32X8, sffxsclsZ, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVEXTRACTI32X8, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVEXTRACTI32X8, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVEXTRACTI64X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVEXTRACTI64X2, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVEXTRACTI64X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVEXTRACTI64X2, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVEXTRACTI64X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVEXTRACTI64X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVEXTRACTI64X2, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVEXTRACTI64X2, sffxsclsZ, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVEXTRACTI64X2, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVEXTRACTI64X2, sffxsclsZ, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVEXTRACTI64X2, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVEXTRACTI64X2, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVEXTRACTI64X4, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionRW}}}, + {opcVEXTRACTI64X4, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVEXTRACTI64X4, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVEXTRACTI64X4, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVEXTRACTI64X4, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVEXTRACTI64X4, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVEXTRACTPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcVEXTRACTPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVFIXUPIMMPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFIXUPIMMPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFIXUPIMMPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFIXUPIMMPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFIXUPIMMPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFIXUPIMMPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFIXUPIMMPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFIXUPIMMPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFIXUPIMMPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFIXUPIMMPD, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFIXUPIMMPD, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFIXUPIMMPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFIXUPIMMPD, sffxsclsBCST, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFIXUPIMMPD, sffxsclsBCST_Z, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFIXUPIMMPD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFIXUPIMMPD, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFIXUPIMMPD, sffxsclsSAE, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFIXUPIMMPD, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFIXUPIMMPD, sffxsclsSAE_Z, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFIXUPIMMPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFIXUPIMMPD, sffxsclsSAE, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFIXUPIMMPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFIXUPIMMPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFIXUPIMMPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFIXUPIMMPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFIXUPIMMPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFIXUPIMMPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFIXUPIMMPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFIXUPIMMPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFIXUPIMMPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFIXUPIMMPS, sffxsclsBCST, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFIXUPIMMPS, sffxsclsBCST_Z, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFIXUPIMMPS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFIXUPIMMPS, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFIXUPIMMPS, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFIXUPIMMPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFIXUPIMMPS, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFIXUPIMMPS, sffxsclsSAE, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFIXUPIMMPS, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFIXUPIMMPS, sffxsclsSAE_Z, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFIXUPIMMPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFIXUPIMMPS, sffxsclsSAE, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFIXUPIMMPS, sffxsclsNIL, 0, isasAVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMPS, sffxsclsZ, 0, isasAVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMPS, sffxsclsNIL, 0, isasAVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMPS, sffxsclsBCST, 0, isasAVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMPS, sffxsclsBCST_Z, 0, isasAVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMPS, sffxsclsBCST, 0, isasAVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMPS, sffxsclsNIL, 0, isasAVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMPS, sffxsclsZ, 0, isasAVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMPS, sffxsclsNIL, 0, isasAVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMSD, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMSD, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMSD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMSD, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMSD, sffxsclsSAE, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMSD, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMSD, sffxsclsSAE_Z, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMSD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMSD, sffxsclsSAE, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMSS, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMSS, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMSS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMSS, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMSS, sffxsclsSAE, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMSS, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMSS, sffxsclsSAE_Z, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMSS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFIXUPIMMSS, sffxsclsSAE, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD132PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD132PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD132PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD132PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD132PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD132PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD132PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD132PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD132PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD132PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD132PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD132PD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD132PD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD132PD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD132PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD132PD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD132PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD132PD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD132PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD132PD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD132PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD132PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD132PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD132PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD132PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD132PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD132PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD132PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD132PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD132PS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD132PS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD132PS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD132PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD132PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD132PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD132PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD132PS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD132PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD132PS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD132PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD132PS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD132SD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132SD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132SD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132SD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132SD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132SD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132SD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132SD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132SD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132SS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132SS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132SS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132SS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132SS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132SS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132SS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132SS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD132SS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD213PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD213PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD213PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD213PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD213PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD213PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD213PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD213PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD213PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD213PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD213PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD213PD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD213PD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD213PD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD213PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD213PD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD213PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD213PD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD213PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD213PD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD213PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD213PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD213PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD213PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD213PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD213PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD213PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD213PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD213PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD213PS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD213PS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD213PS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD213PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD213PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD213PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD213PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD213PS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD213PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD213PS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD213PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD213PS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD213SD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213SD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213SD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213SD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213SD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213SD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213SD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213SD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213SD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213SS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213SS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213SS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213SS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213SS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213SS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213SS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213SS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD213SS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD231PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD231PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD231PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD231PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD231PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD231PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD231PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD231PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD231PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD231PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD231PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD231PD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD231PD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD231PD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD231PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD231PD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD231PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD231PD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD231PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD231PD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD231PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD231PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD231PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD231PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD231PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD231PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD231PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD231PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD231PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADD231PS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD231PS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD231PS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD231PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD231PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD231PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD231PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD231PS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD231PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD231PS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD231PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD231PS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADD231SD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231SD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231SD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231SD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231SD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231SD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231SD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231SD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231SD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231SS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231SS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231SS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231SS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231SS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231SS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231SS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231SS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADD231SS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB132PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB132PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB132PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB132PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB132PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB132PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB132PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB132PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB132PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB132PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB132PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB132PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB132PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB132PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB132PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB132PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB132PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB132PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB132PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB132PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB132PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB132PD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB132PD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB132PD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB132PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB132PD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB132PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB132PD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB132PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB132PD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB132PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB132PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB132PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB132PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB132PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB132PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB132PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB132PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB132PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB132PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB132PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB132PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB132PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB132PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB132PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB132PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB132PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB132PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB132PS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB132PS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB132PS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB132PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB132PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB132PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB132PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB132PS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB132PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB132PS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB132PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB132PS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB213PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB213PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB213PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB213PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB213PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB213PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB213PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB213PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB213PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB213PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB213PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB213PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB213PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB213PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB213PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB213PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB213PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB213PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB213PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB213PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB213PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB213PD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB213PD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB213PD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB213PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB213PD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB213PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB213PD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB213PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB213PD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB213PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB213PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB213PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB213PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB213PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB213PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB213PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB213PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB213PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB213PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB213PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB213PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB213PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB213PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB213PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB213PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB213PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB213PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB213PS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB213PS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB213PS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB213PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB213PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB213PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB213PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB213PS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB213PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB213PS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB213PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB213PS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB231PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB231PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB231PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB231PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB231PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB231PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB231PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB231PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB231PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB231PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB231PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB231PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB231PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB231PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB231PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB231PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB231PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB231PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB231PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB231PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB231PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB231PD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB231PD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB231PD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB231PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB231PD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB231PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB231PD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB231PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB231PD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB231PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB231PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB231PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB231PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB231PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB231PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB231PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB231PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB231PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB231PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB231PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB231PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB231PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB231PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB231PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB231PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMADDSUB231PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB231PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMADDSUB231PS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB231PS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB231PS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB231PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB231PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB231PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB231PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB231PS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB231PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB231PS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB231PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMADDSUB231PS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB132PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB132PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB132PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB132PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB132PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB132PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB132PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB132PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB132PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB132PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB132PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB132PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB132PD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB132PD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB132PD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB132PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB132PD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB132PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB132PD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB132PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB132PD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB132PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB132PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB132PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB132PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB132PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB132PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB132PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB132PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB132PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB132PS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB132PS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB132PS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB132PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB132PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB132PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB132PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB132PS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB132PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB132PS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB132PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB132PS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB132SD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132SD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132SD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132SD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132SD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132SD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132SD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132SD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132SD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132SS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132SS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132SS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132SS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132SS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132SS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132SS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132SS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB132SS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB213PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB213PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB213PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB213PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB213PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB213PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB213PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB213PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB213PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB213PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB213PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB213PD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB213PD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB213PD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB213PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB213PD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB213PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB213PD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB213PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB213PD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB213PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB213PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB213PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB213PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB213PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB213PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB213PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB213PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB213PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB213PS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB213PS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB213PS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB213PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB213PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB213PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB213PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB213PS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB213PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB213PS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB213PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB213PS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB213SD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213SD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213SD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213SD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213SD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213SD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213SD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213SD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213SD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213SS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213SS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213SS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213SS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213SS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213SS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213SS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213SS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB213SS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB231PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB231PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB231PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB231PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB231PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB231PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB231PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB231PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB231PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB231PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB231PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB231PD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB231PD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB231PD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB231PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB231PD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB231PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB231PD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB231PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB231PD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB231PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB231PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB231PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB231PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB231PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB231PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB231PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB231PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB231PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUB231PS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB231PS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB231PS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB231PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB231PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB231PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB231PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB231PS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB231PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB231PS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB231PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB231PS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUB231SD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231SD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231SD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231SD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231SD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231SD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231SD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231SD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231SD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231SS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231SS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231SS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231SS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231SS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231SS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231SS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231SS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUB231SS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD132PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD132PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD132PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD132PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD132PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD132PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD132PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD132PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD132PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD132PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD132PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD132PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD132PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD132PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD132PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD132PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD132PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD132PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD132PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD132PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD132PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD132PD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD132PD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD132PD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD132PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD132PD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD132PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD132PD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD132PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD132PD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD132PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD132PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD132PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD132PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD132PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD132PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD132PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD132PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD132PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD132PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD132PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD132PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD132PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD132PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD132PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD132PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD132PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD132PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD132PS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD132PS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD132PS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD132PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD132PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD132PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD132PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD132PS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD132PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD132PS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD132PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD132PS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD213PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD213PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD213PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD213PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD213PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD213PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD213PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD213PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD213PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD213PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD213PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD213PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD213PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD213PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD213PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD213PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD213PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD213PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD213PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD213PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD213PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD213PD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD213PD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD213PD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD213PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD213PD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD213PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD213PD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD213PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD213PD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD213PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD213PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD213PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD213PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD213PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD213PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD213PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD213PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD213PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD213PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD213PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD213PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD213PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD213PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD213PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD213PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD213PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD213PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD213PS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD213PS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD213PS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD213PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD213PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD213PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD213PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD213PS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD213PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD213PS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD213PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD213PS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD231PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD231PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD231PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD231PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD231PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD231PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD231PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD231PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD231PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD231PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD231PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD231PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD231PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD231PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD231PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD231PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD231PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD231PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD231PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD231PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD231PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD231PD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD231PD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD231PD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD231PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD231PD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD231PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD231PD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD231PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD231PD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD231PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD231PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD231PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD231PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD231PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD231PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD231PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD231PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD231PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD231PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD231PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD231PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD231PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD231PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD231PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD231PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFMSUBADD231PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD231PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFMSUBADD231PS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD231PS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD231PS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD231PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD231PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD231PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD231PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD231PS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD231PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD231PS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD231PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFMSUBADD231PS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD132PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD132PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD132PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD132PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD132PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD132PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD132PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD132PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD132PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD132PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD132PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD132PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD132PD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD132PD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD132PD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD132PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD132PD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD132PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD132PD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD132PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD132PD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD132PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD132PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD132PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD132PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD132PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD132PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD132PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD132PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD132PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD132PS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD132PS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD132PS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD132PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD132PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD132PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD132PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD132PS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD132PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD132PS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD132PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD132PS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD132SD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132SD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132SD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132SD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132SD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132SD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132SD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132SD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132SD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132SS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132SS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132SS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132SS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132SS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132SS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132SS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132SS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD132SS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD213PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD213PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD213PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD213PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD213PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD213PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD213PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD213PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD213PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD213PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD213PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD213PD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD213PD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD213PD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD213PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD213PD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD213PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD213PD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD213PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD213PD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD213PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD213PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD213PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD213PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD213PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD213PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD213PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD213PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD213PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD213PS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD213PS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD213PS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD213PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD213PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD213PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD213PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD213PS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD213PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD213PS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD213PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD213PS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD213SD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213SD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213SD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213SD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213SD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213SD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213SD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213SD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213SD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213SS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213SS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213SS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213SS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213SS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213SS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213SS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213SS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD213SS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD231PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD231PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD231PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD231PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD231PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD231PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD231PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD231PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD231PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD231PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD231PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD231PD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD231PD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD231PD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD231PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD231PD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD231PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD231PD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD231PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD231PD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD231PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD231PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD231PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD231PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD231PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD231PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD231PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD231PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD231PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMADD231PS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD231PS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD231PS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD231PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD231PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD231PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD231PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD231PS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD231PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD231PS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD231PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD231PS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMADD231SD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231SD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231SD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231SD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231SD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231SD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231SD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231SD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231SD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231SS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231SS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231SS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231SS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231SS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231SS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231SS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231SS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMADD231SS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB132PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB132PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB132PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB132PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB132PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB132PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB132PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB132PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB132PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB132PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB132PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB132PD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB132PD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB132PD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB132PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB132PD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB132PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB132PD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB132PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB132PD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB132PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB132PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB132PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB132PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB132PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB132PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB132PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB132PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB132PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB132PS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB132PS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB132PS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB132PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB132PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB132PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB132PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB132PS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB132PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB132PS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB132PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB132PS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB132SD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132SD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132SD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132SD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132SD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132SD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132SD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132SD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132SD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132SS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132SS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132SS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132SS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132SS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132SS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132SS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132SS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB132SS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB213PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB213PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB213PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB213PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB213PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB213PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB213PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB213PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB213PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB213PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB213PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB213PD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB213PD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB213PD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB213PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB213PD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB213PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB213PD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB213PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB213PD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB213PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB213PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB213PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB213PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB213PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB213PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB213PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB213PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB213PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB213PS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB213PS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB213PS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB213PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB213PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB213PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB213PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB213PS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB213PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB213PS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB213PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB213PS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB213SD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213SD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213SD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213SD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213SD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213SD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213SD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213SD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213SD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213SS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213SS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213SS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213SS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213SS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213SS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213SS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213SS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB213SS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB231PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231PD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB231PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB231PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB231PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB231PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB231PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB231PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB231PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB231PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB231PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB231PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB231PD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB231PD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB231PD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB231PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB231PD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB231PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB231PD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB231PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB231PD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB231PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB231PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231PS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB231PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB231PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB231PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB231PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB231PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB231PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB231PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVFNMSUB231PS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB231PS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB231PS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB231PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB231PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB231PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB231PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB231PS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB231PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB231PS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB231PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB231PS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVFNMSUB231SD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231SD, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231SD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231SD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231SD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231SD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231SD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231SD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231SD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231SS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231SS, sffxsclsNIL, 0, isasFMA3, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231SS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231SS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231SS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231SS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231SS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231SS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFNMSUB231SS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVFPCLASSPDX, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPDX, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPDX, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPDX, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPDX, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPDX, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPDY, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPDY, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPDY, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPDY, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPDY, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPDY, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPDZ, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPDZ, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPDZ, sffxsclsBCST, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPDZ, sffxsclsBCST, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPDZ, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPDZ, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPSX, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPSX, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPSX, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPSX, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPSX, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPSX, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPSY, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPSY, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPSY, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPSY, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPSY, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPSY, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPSZ, sffxsclsBCST, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPSZ, sffxsclsBCST, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPSZ, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPSZ, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPSZ, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSPSZ, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSSD, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSSD, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSSD, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSSD, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSSS, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSSS, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSSS, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVFPCLASSSS, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVGATHERDPD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeXMM), false, actionRW}, {uint8(oprndtypeVM32X), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGATHERDPD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionRW}, {uint8(oprndtypeVM32X), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVGATHERDPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeVM32X), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGATHERDPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeVM32X), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVGATHERDPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeVM32Y), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVGATHERDPS, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeXMM), false, actionRW}, {uint8(oprndtypeVM32X), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGATHERDPS, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionRW}, {uint8(oprndtypeVM32Y), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVGATHERDPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeVM32X), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGATHERDPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeVM32Y), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVGATHERDPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeVM32Z), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVGATHERQPD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeXMM), false, actionRW}, {uint8(oprndtypeVM64X), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGATHERQPD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionRW}, {uint8(oprndtypeVM64Y), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVGATHERQPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeVM64X), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGATHERQPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeVM64Y), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVGATHERQPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeVM64Z), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVGATHERQPS, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeXMM), false, actionRW}, {uint8(oprndtypeVM64X), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGATHERQPS, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeXMM), false, actionRW}, {uint8(oprndtypeVM64Y), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGATHERQPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeVM64X), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGATHERQPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeVM64Y), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGATHERQPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeVM64Z), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVGETEXPPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGETEXPPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETEXPPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETEXPPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVGETEXPPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVGETEXPPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVGETEXPPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGETEXPPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETEXPPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVGETEXPPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVGETEXPPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETEXPPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVGETEXPPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGETEXPPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETEXPPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETEXPPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVGETEXPPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVGETEXPPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVGETEXPPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVGETEXPPD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETEXPPD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETEXPPD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVGETEXPPD, sffxsclsBCST_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETEXPPD, sffxsclsBCST, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETEXPPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVGETEXPPD, sffxsclsSAE, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVGETEXPPD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETEXPPD, sffxsclsSAE_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETEXPPD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETEXPPD, sffxsclsSAE, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETEXPPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGETEXPPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETEXPPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETEXPPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVGETEXPPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVGETEXPPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVGETEXPPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGETEXPPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETEXPPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVGETEXPPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVGETEXPPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETEXPPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVGETEXPPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGETEXPPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETEXPPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETEXPPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVGETEXPPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVGETEXPPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVGETEXPPS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVGETEXPPS, sffxsclsBCST_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETEXPPS, sffxsclsBCST, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETEXPPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVGETEXPPS, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETEXPPS, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETEXPPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVGETEXPPS, sffxsclsSAE, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVGETEXPPS, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETEXPPS, sffxsclsSAE_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETEXPPS, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETEXPPS, sffxsclsSAE, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETEXPSD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGETEXPSD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETEXPSD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETEXPSD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGETEXPSD, sffxsclsSAE, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGETEXPSD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETEXPSD, sffxsclsSAE_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETEXPSD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETEXPSD, sffxsclsSAE, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETEXPSS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGETEXPSS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETEXPSS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETEXPSS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGETEXPSS, sffxsclsSAE, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGETEXPSS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETEXPSS, sffxsclsSAE_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETEXPSS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETEXPSS, sffxsclsSAE, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETMANTPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGETMANTPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETMANTPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETMANTPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVGETMANTPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVGETMANTPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVGETMANTPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGETMANTPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETMANTPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVGETMANTPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVGETMANTPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETMANTPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVGETMANTPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGETMANTPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETMANTPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETMANTPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVGETMANTPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVGETMANTPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVGETMANTPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVGETMANTPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETMANTPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETMANTPD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVGETMANTPD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETMANTPD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETMANTPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVGETMANTPD, sffxsclsSAE, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVGETMANTPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETMANTPD, sffxsclsSAE_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETMANTPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETMANTPD, sffxsclsSAE, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETMANTPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGETMANTPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETMANTPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETMANTPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVGETMANTPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVGETMANTPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVGETMANTPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGETMANTPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETMANTPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVGETMANTPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVGETMANTPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETMANTPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVGETMANTPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGETMANTPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETMANTPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETMANTPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVGETMANTPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVGETMANTPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVGETMANTPS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVGETMANTPS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETMANTPS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETMANTPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVGETMANTPS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETMANTPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETMANTPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVGETMANTPS, sffxsclsSAE, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVGETMANTPS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETMANTPS, sffxsclsSAE_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETMANTPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETMANTPS, sffxsclsSAE, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVGETMANTSD, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGETMANTSD, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETMANTSD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETMANTSD, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGETMANTSD, sffxsclsSAE, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGETMANTSD, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETMANTSD, sffxsclsSAE_Z, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETMANTSD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETMANTSD, sffxsclsSAE, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETMANTSS, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGETMANTSS, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETMANTSS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETMANTSS, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGETMANTSS, sffxsclsSAE, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVGETMANTSS, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETMANTSS, sffxsclsSAE_Z, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETMANTSS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVGETMANTSS, sffxsclsSAE, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVHADDPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVHADDPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVHADDPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVHADDPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVHADDPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVHADDPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVHADDPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVHADDPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVHSUBPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVHSUBPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVHSUBPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVHSUBPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVHSUBPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVHSUBPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVHSUBPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVHSUBPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVINSERTF128, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVINSERTF128, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVINSERTF32X4, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVINSERTF32X4, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVINSERTF32X4, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVINSERTF32X4, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVINSERTF32X4, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVINSERTF32X4, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVINSERTF32X4, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVINSERTF32X4, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTF32X4, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTF32X4, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVINSERTF32X4, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTF32X4, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTF32X8, sffxsclsNIL, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVINSERTF32X8, sffxsclsZ, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTF32X8, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTF32X8, sffxsclsNIL, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVINSERTF32X8, sffxsclsZ, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTF32X8, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTF64X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVINSERTF64X2, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVINSERTF64X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVINSERTF64X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVINSERTF64X2, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVINSERTF64X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVINSERTF64X2, sffxsclsNIL, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVINSERTF64X2, sffxsclsZ, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTF64X2, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTF64X2, sffxsclsNIL, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVINSERTF64X2, sffxsclsZ, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTF64X2, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTF64X4, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVINSERTF64X4, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTF64X4, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTF64X4, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVINSERTF64X4, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTF64X4, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTI128, sffxsclsNIL, 0, isasAVX2, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVINSERTI128, sffxsclsNIL, 0, isasAVX2, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVINSERTI32X4, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVINSERTI32X4, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVINSERTI32X4, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVINSERTI32X4, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVINSERTI32X4, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVINSERTI32X4, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVINSERTI32X4, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVINSERTI32X4, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTI32X4, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTI32X4, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVINSERTI32X4, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTI32X4, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTI32X8, sffxsclsNIL, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVINSERTI32X8, sffxsclsZ, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTI32X8, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTI32X8, sffxsclsNIL, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVINSERTI32X8, sffxsclsZ, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTI32X8, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTI64X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVINSERTI64X2, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVINSERTI64X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVINSERTI64X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVINSERTI64X2, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVINSERTI64X2, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVINSERTI64X2, sffxsclsNIL, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVINSERTI64X2, sffxsclsZ, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTI64X2, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTI64X2, sffxsclsNIL, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVINSERTI64X2, sffxsclsZ, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTI64X2, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTI64X4, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVINSERTI64X4, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTI64X4, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTI64X4, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVINSERTI64X4, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTI64X4, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVINSERTPS, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVINSERTPS, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVLDDQU, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVLDDQU, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVLDMXCSR, sffxsclsNIL, 0, isasAVX, 1, oprnds{{uint8(oprndtypeM32), false, actionR}}}, + {opcVMASKMOVDQU, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(implregRDI), true, actionR}}}, + {opcVMASKMOVPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMASKMOVPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMASKMOVPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVMASKMOVPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVMASKMOVPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMASKMOVPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMASKMOVPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVMASKMOVPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVMAXPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMAXPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMAXPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMAXPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMAXPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMAXPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMAXPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMAXPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMAXPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMAXPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMAXPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMAXPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMAXPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMAXPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMAXPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMAXPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMAXPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMAXPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMAXPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMAXPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMAXPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMAXPD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMAXPD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMAXPD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMAXPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMAXPD, sffxsclsSAE, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMAXPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMAXPD, sffxsclsSAE_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMAXPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMAXPD, sffxsclsSAE, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMAXPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMAXPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMAXPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMAXPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMAXPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMAXPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMAXPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMAXPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMAXPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMAXPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMAXPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMAXPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMAXPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMAXPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMAXPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMAXPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMAXPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMAXPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMAXPS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMAXPS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMAXPS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMAXPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMAXPS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMAXPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMAXPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMAXPS, sffxsclsSAE, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMAXPS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMAXPS, sffxsclsSAE_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMAXPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMAXPS, sffxsclsSAE, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMAXSD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMAXSD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMAXSD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMAXSD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMAXSD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMAXSD, sffxsclsSAE, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMAXSD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMAXSD, sffxsclsSAE_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMAXSD, sffxsclsSAE, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMAXSS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMAXSS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMAXSS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMAXSS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMAXSS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMAXSS, sffxsclsSAE, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMAXSS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMAXSS, sffxsclsSAE_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMAXSS, sffxsclsSAE, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMINPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMINPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMINPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMINPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMINPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMINPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMINPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMINPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMINPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMINPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMINPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMINPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMINPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMINPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMINPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMINPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMINPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMINPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMINPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMINPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMINPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMINPD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMINPD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMINPD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMINPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMINPD, sffxsclsSAE, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMINPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMINPD, sffxsclsSAE_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMINPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMINPD, sffxsclsSAE, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMINPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMINPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMINPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMINPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMINPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMINPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMINPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMINPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMINPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMINPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMINPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMINPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMINPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMINPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMINPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMINPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMINPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMINPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMINPS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMINPS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMINPS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMINPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMINPS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMINPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMINPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMINPS, sffxsclsSAE, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMINPS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMINPS, sffxsclsSAE_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMINPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMINPS, sffxsclsSAE, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMINSD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMINSD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMINSD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMINSD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMINSD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMINSD, sffxsclsSAE, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMINSD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMINSD, sffxsclsSAE_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMINSD, sffxsclsSAE, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMINSS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMINSS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMINSS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMINSS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMINSS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMINSS, sffxsclsSAE, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMINSS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMINSS, sffxsclsSAE_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMINSS, sffxsclsSAE, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVAPD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVAPD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVAPD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVMOVAPD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVAPD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVMOVAPD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVAPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMOVAPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVAPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMOVAPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVAPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVMOVAPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVMOVAPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMOVAPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVAPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionRW}}}, + {opcVMOVAPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVMOVAPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMOVAPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVAPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMOVAPD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVAPD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVAPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM512), false, actionRW}}}, + {opcVMOVAPD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM512), false, actionW}}}, + {opcVMOVAPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMOVAPD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVAPD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM512), false, actionW}}}, + {opcVMOVAPD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVAPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVAPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVAPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVMOVAPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVAPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVMOVAPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVAPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMOVAPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVAPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMOVAPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVAPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVMOVAPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVMOVAPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMOVAPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVAPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionRW}}}, + {opcVMOVAPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVMOVAPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMOVAPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVAPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMOVAPS, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVAPS, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVAPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM512), false, actionRW}}}, + {opcVMOVAPS, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM512), false, actionW}}}, + {opcVMOVAPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMOVAPS, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVAPS, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM512), false, actionW}}}, + {opcVMOVAPS, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcVMOVD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVMOVDDUP, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDDUP, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDDUP, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDDUP, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDDUP, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMOVDDUP, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDDUP, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMOVDDUP, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDDUP, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMOVDDUP, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDDUP, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMOVDDUP, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDDUP, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMOVDDUP, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVDDUP, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVDDUP, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMOVDDUP, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVDDUP, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVDQA, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDQA, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDQA, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVMOVDQA, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDQA, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVMOVDQA, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDQA32, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMOVDQA32, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDQA32, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDQA32, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMOVDQA32, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDQA32, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDQA32, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVMOVDQA32, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVMOVDQA32, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMOVDQA32, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDQA32, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVMOVDQA32, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDQA32, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionRW}}}, + {opcVMOVDQA32, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVMOVDQA32, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMOVDQA32, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDQA32, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVMOVDQA32, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDQA32, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMOVDQA32, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVDQA32, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVDQA32, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM512), false, actionRW}}}, + {opcVMOVDQA32, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM512), false, actionW}}}, + {opcVMOVDQA32, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMOVDQA32, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVDQA32, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM512), false, actionW}}}, + {opcVMOVDQA32, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVDQA64, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMOVDQA64, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDQA64, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDQA64, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMOVDQA64, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDQA64, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDQA64, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVMOVDQA64, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVMOVDQA64, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMOVDQA64, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDQA64, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVMOVDQA64, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDQA64, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionRW}}}, + {opcVMOVDQA64, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVMOVDQA64, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMOVDQA64, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDQA64, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVMOVDQA64, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDQA64, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMOVDQA64, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVDQA64, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVDQA64, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM512), false, actionRW}}}, + {opcVMOVDQA64, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM512), false, actionW}}}, + {opcVMOVDQA64, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMOVDQA64, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVDQA64, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM512), false, actionW}}}, + {opcVMOVDQA64, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVDQU, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDQU, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDQU, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVMOVDQU, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDQU, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVMOVDQU, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDQU16, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMOVDQU16, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDQU16, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDQU16, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMOVDQU16, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDQU16, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDQU16, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVMOVDQU16, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVMOVDQU16, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMOVDQU16, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDQU16, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVMOVDQU16, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDQU16, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionRW}}}, + {opcVMOVDQU16, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVMOVDQU16, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMOVDQU16, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDQU16, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVMOVDQU16, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDQU16, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMOVDQU16, sffxsclsZ, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVDQU16, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVDQU16, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM512), false, actionRW}}}, + {opcVMOVDQU16, sffxsclsZ, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM512), false, actionW}}}, + {opcVMOVDQU16, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMOVDQU16, sffxsclsZ, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVDQU16, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM512), false, actionW}}}, + {opcVMOVDQU16, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVDQU32, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMOVDQU32, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDQU32, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDQU32, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMOVDQU32, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDQU32, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDQU32, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVMOVDQU32, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVMOVDQU32, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMOVDQU32, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDQU32, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVMOVDQU32, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDQU32, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionRW}}}, + {opcVMOVDQU32, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVMOVDQU32, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMOVDQU32, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDQU32, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVMOVDQU32, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDQU32, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMOVDQU32, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVDQU32, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVDQU32, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM512), false, actionRW}}}, + {opcVMOVDQU32, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM512), false, actionW}}}, + {opcVMOVDQU32, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMOVDQU32, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVDQU32, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM512), false, actionW}}}, + {opcVMOVDQU32, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVDQU64, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMOVDQU64, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDQU64, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDQU64, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMOVDQU64, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDQU64, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDQU64, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVMOVDQU64, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVMOVDQU64, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMOVDQU64, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDQU64, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVMOVDQU64, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDQU64, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionRW}}}, + {opcVMOVDQU64, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVMOVDQU64, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMOVDQU64, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDQU64, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVMOVDQU64, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDQU64, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMOVDQU64, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVDQU64, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVDQU64, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM512), false, actionRW}}}, + {opcVMOVDQU64, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM512), false, actionW}}}, + {opcVMOVDQU64, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMOVDQU64, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVDQU64, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM512), false, actionW}}}, + {opcVMOVDQU64, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVDQU8, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMOVDQU8, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDQU8, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDQU8, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMOVDQU8, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDQU8, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDQU8, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVMOVDQU8, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVMOVDQU8, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMOVDQU8, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDQU8, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVMOVDQU8, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVDQU8, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionRW}}}, + {opcVMOVDQU8, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVMOVDQU8, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMOVDQU8, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDQU8, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVMOVDQU8, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVDQU8, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMOVDQU8, sffxsclsZ, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVDQU8, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVDQU8, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM512), false, actionRW}}}, + {opcVMOVDQU8, sffxsclsZ, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM512), false, actionW}}}, + {opcVMOVDQU8, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMOVDQU8, sffxsclsZ, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVDQU8, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM512), false, actionW}}}, + {opcVMOVDQU8, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVHLPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVHPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVHPD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVMOVHPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVHPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVMOVLHPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVLPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVLPD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVMOVLPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVLPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVMOVMSKPD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVMOVMSKPD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVMOVMSKPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVMOVMSKPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVMOVNTDQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVMOVNTDQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVMOVNTDQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM512), false, actionW}}}, + {opcVMOVNTDQA, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVNTDQA, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVNTDQA, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVNTPD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVMOVNTPD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVMOVNTPD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM512), false, actionW}}}, + {opcVMOVNTPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVMOVNTPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVMOVNTPS, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM512), false, actionW}}}, + {opcVMOVQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVMOVQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcVMOVQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVSD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVSD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVMOVSD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVSD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMOVSD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVSD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVMOVSD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMOVSD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVSHDUP, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVSHDUP, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVSHDUP, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVSHDUP, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVSHDUP, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMOVSHDUP, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVSHDUP, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMOVSHDUP, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVSHDUP, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMOVSHDUP, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVSHDUP, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMOVSHDUP, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVSHDUP, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMOVSHDUP, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVSHDUP, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVSHDUP, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMOVSHDUP, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVSHDUP, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVSLDUP, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVSLDUP, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVSLDUP, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVSLDUP, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVSLDUP, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMOVSLDUP, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVSLDUP, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMOVSLDUP, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVSLDUP, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMOVSLDUP, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVSLDUP, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMOVSLDUP, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVSLDUP, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMOVSLDUP, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVSLDUP, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVSLDUP, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMOVSLDUP, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVSLDUP, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVSS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVSS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcVMOVSS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVSS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMOVSS, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVSS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcVMOVSS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMOVSS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVUPD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVUPD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVUPD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVMOVUPD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVUPD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVMOVUPD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVUPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMOVUPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVUPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMOVUPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVUPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVMOVUPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVMOVUPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMOVUPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVUPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionRW}}}, + {opcVMOVUPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVMOVUPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMOVUPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVUPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMOVUPD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVUPD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVUPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM512), false, actionRW}}}, + {opcVMOVUPD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM512), false, actionW}}}, + {opcVMOVUPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMOVUPD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVUPD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM512), false, actionW}}}, + {opcVMOVUPD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVUPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVUPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVUPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVMOVUPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVUPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVMOVUPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVUPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMOVUPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVUPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMOVUPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVUPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVMOVUPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVMOVUPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMOVUPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMOVUPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionRW}}}, + {opcVMOVUPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVMOVUPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMOVUPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMOVUPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMOVUPS, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVUPS, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVUPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM512), false, actionRW}}}, + {opcVMOVUPS, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM512), false, actionW}}}, + {opcVMOVUPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMOVUPS, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMOVUPS, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM512), false, actionW}}}, + {opcVMOVUPS, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMPSADBW, sffxsclsNIL, 0, isasAVX2, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMPSADBW, sffxsclsNIL, 0, isasAVX2, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMPSADBW, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMPSADBW, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMULPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMULPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMULPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMULPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMULPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMULPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMULPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMULPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMULPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMULPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMULPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMULPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMULPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMULPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMULPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMULPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMULPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMULPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMULPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMULPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMULPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMULPD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMULPD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMULPD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMULPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMULPD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMULPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMULPD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMULPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMULPD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMULPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMULPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMULPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMULPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMULPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMULPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMULPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMULPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMULPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMULPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMULPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMULPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMULPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMULPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMULPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMULPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMULPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVMULPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVMULPS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMULPS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMULPS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMULPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMULPS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMULPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMULPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMULPS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVMULPS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMULPS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMULPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMULPS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVMULSD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMULSD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMULSD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMULSD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMULSD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMULSD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMULSD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMULSD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMULSD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMULSS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMULSS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMULSS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMULSS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMULSS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMULSS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVMULSS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMULSS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVMULSS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVORPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVORPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVORPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVORPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVORPD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVORPD, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVORPD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVORPD, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVORPD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVORPD, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVORPD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVORPD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVORPD, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVORPD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVORPD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVORPD, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVORPD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVORPD, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVORPD, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVORPD, sffxsclsZ, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVORPD, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVORPD, sffxsclsBCST, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVORPD, sffxsclsBCST_Z, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVORPD, sffxsclsBCST, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVORPD, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVORPD, sffxsclsZ, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVORPD, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVORPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVORPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVORPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVORPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVORPS, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVORPS, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVORPS, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVORPS, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVORPS, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVORPS, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVORPS, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVORPS, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVORPS, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVORPS, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVORPS, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVORPS, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVORPS, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVORPS, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVORPS, sffxsclsBCST, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVORPS, sffxsclsBCST_Z, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVORPS, sffxsclsBCST, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVORPS, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVORPS, sffxsclsZ, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVORPS, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVORPS, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVORPS, sffxsclsZ, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVORPS, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPABSB, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPABSB, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPABSB, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPABSB, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPABSB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPABSB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPABSB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPABSB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPABSB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPABSB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPABSB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPABSB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPABSB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPABSB, sffxsclsZ, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPABSB, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPABSB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPABSB, sffxsclsZ, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPABSB, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPABSD, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPABSD, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPABSD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPABSD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPABSD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPABSD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPABSD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPABSD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPABSD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPABSD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPABSD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPABSD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPABSD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPABSD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPABSD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPABSD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPABSD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPABSD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPABSD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPABSD, sffxsclsBCST_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPABSD, sffxsclsBCST, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPABSD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPABSD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPABSD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPABSD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPABSD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPABSD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPABSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPABSQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPABSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPABSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPABSQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPABSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPABSQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPABSQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPABSQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPABSQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPABSQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPABSQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPABSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPABSQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPABSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPABSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPABSQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPABSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPABSQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPABSQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPABSQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPABSQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPABSQ, sffxsclsBCST_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPABSQ, sffxsclsBCST, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPABSQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPABSQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPABSQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPABSW, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPABSW, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPABSW, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPABSW, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPABSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPABSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPABSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPABSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPABSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPABSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPABSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPABSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPABSW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPABSW, sffxsclsZ, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPABSW, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPABSW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPABSW, sffxsclsZ, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPABSW, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPACKSSDW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPACKSSDW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPACKSSDW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPACKSSDW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPACKSSDW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPACKSSDW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPACKSSDW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPACKSSDW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPACKSSDW, sffxsclsBCST, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPACKSSDW, sffxsclsBCST_Z, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPACKSSDW, sffxsclsBCST, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPACKSSDW, sffxsclsBCST, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPACKSSDW, sffxsclsBCST_Z, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPACKSSDW, sffxsclsBCST, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPACKSSDW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPACKSSDW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPACKSSDW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPACKSSDW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPACKSSDW, sffxsclsBCST, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPACKSSDW, sffxsclsBCST_Z, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPACKSSDW, sffxsclsBCST, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPACKSSDW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPACKSSDW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPACKSSDW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPACKSSDW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPACKSSDW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPACKSSDW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPACKSSWB, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPACKSSWB, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPACKSSWB, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPACKSSWB, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPACKSSWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPACKSSWB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPACKSSWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPACKSSWB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPACKSSWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPACKSSWB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPACKSSWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPACKSSWB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPACKSSWB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPACKSSWB, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPACKSSWB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPACKSSWB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPACKSSWB, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPACKSSWB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPACKUSDW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPACKUSDW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPACKUSDW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPACKUSDW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPACKUSDW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPACKUSDW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPACKUSDW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPACKUSDW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPACKUSDW, sffxsclsBCST, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPACKUSDW, sffxsclsBCST_Z, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPACKUSDW, sffxsclsBCST, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPACKUSDW, sffxsclsBCST, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPACKUSDW, sffxsclsBCST_Z, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPACKUSDW, sffxsclsBCST, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPACKUSDW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPACKUSDW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPACKUSDW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPACKUSDW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPACKUSDW, sffxsclsBCST, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPACKUSDW, sffxsclsBCST_Z, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPACKUSDW, sffxsclsBCST, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPACKUSDW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPACKUSDW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPACKUSDW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPACKUSDW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPACKUSDW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPACKUSDW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPACKUSWB, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPACKUSWB, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPACKUSWB, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPACKUSWB, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPACKUSWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPACKUSWB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPACKUSWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPACKUSWB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPACKUSWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPACKUSWB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPACKUSWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPACKUSWB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPACKUSWB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPACKUSWB, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPACKUSWB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPACKUSWB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPACKUSWB, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPACKUSWB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDB, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDB, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDB, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDB, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPADDB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPADDB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPADDB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPADDB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPADDB, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPADDB, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPADDD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPADDD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPADDD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPADDD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPADDD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPADDD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPADDD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPADDD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPADDD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDQ, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDQ, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPADDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPADDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPADDQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPADDQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPADDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPADDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPADDQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPADDQ, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPADDQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDSB, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDSB, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDSB, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDSB, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDSB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPADDSB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDSB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPADDSB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDSB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPADDSB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDSB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPADDSB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDSB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPADDSB, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDSB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDSB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPADDSB, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDSB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDSW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDSW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDSW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDSW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPADDSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPADDSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPADDSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPADDSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDSW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPADDSW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDSW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDSW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPADDSW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDSW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDUSB, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDUSB, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDUSB, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDUSB, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDUSB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPADDUSB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDUSB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPADDUSB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDUSB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPADDUSB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDUSB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPADDUSB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDUSB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPADDUSB, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDUSB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDUSB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPADDUSB, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDUSB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDUSW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDUSW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDUSW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDUSW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDUSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPADDUSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDUSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPADDUSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDUSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPADDUSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDUSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPADDUSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDUSW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPADDUSW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDUSW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDUSW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPADDUSW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDUSW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPADDW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPADDW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPADDW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPADDW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPADDW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPADDW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPADDW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPADDW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPADDW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPALIGNR, sffxsclsNIL, 0, isasAVX2, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPALIGNR, sffxsclsNIL, 0, isasAVX2, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPALIGNR, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPALIGNR, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPALIGNR, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPALIGNR, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPALIGNR, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPALIGNR, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPALIGNR, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPALIGNR, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPALIGNR, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPALIGNR, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPALIGNR, sffxsclsNIL, 0, isasAVX512BW, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPALIGNR, sffxsclsZ, 0, isasAVX512BW, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPALIGNR, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPALIGNR, sffxsclsNIL, 0, isasAVX512BW, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPALIGNR, sffxsclsZ, 0, isasAVX512BW, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPALIGNR, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPAND, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPAND, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPAND, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPAND, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPANDD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPANDD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPANDD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPANDD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPANDD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPANDD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPANDD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPANDD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPANDD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPANDD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPANDD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPANDD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPANDD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPANDD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPANDD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPANDD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPANDD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPANDD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPANDD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPANDD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPANDD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPANDD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPANDD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPANDD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPANDD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPANDD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPANDD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPANDN, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPANDN, sffxsclsNIL, featureCancellingInputs, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPANDN, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPANDN, sffxsclsNIL, featureCancellingInputs, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPANDND, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPANDND, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPANDND, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPANDND, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPANDND, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPANDND, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPANDND, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPANDND, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPANDND, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPANDND, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPANDND, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPANDND, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPANDND, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPANDND, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPANDND, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPANDND, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPANDND, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPANDND, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPANDND, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPANDND, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPANDND, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPANDND, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPANDND, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPANDND, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPANDND, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPANDND, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPANDND, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPANDNQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPANDNQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPANDNQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPANDNQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPANDNQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPANDNQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPANDNQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPANDNQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPANDNQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPANDNQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPANDNQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPANDNQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPANDNQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPANDNQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPANDNQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPANDNQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPANDNQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPANDNQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPANDNQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPANDNQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPANDNQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPANDNQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPANDNQ, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPANDNQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPANDNQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPANDNQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPANDNQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPANDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPANDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPANDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPANDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPANDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPANDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPANDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPANDQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPANDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPANDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPANDQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPANDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPANDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPANDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPANDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPANDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPANDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPANDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPANDQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPANDQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPANDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPANDQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPANDQ, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPANDQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPANDQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPANDQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPANDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPAVGB, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPAVGB, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPAVGB, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPAVGB, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPAVGB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPAVGB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPAVGB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPAVGB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPAVGB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPAVGB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPAVGB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPAVGB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPAVGB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPAVGB, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPAVGB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPAVGB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPAVGB, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPAVGB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPAVGW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPAVGW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPAVGW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPAVGW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPAVGW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPAVGW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPAVGW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPAVGW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPAVGW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPAVGW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPAVGW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPAVGW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPAVGW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPAVGW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPAVGW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPAVGW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPAVGW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPAVGW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBLENDD, sffxsclsNIL, 0, isasAVX2, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBLENDD, sffxsclsNIL, 0, isasAVX2, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBLENDD, sffxsclsNIL, 0, isasAVX2, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBLENDD, sffxsclsNIL, 0, isasAVX2, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBLENDMB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPBLENDMB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBLENDMB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBLENDMB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPBLENDMB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBLENDMB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBLENDMB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPBLENDMB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBLENDMB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBLENDMB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPBLENDMB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBLENDMB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBLENDMB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPBLENDMB, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBLENDMB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBLENDMB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPBLENDMB, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBLENDMB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBLENDMD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPBLENDMD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBLENDMD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBLENDMD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPBLENDMD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBLENDMD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBLENDMD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPBLENDMD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBLENDMD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBLENDMD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPBLENDMD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBLENDMD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBLENDMD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPBLENDMD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBLENDMD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBLENDMD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPBLENDMD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBLENDMD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBLENDMD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPBLENDMD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBLENDMD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBLENDMD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPBLENDMD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBLENDMD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBLENDMD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPBLENDMD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBLENDMD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBLENDMQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPBLENDMQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBLENDMQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBLENDMQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPBLENDMQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBLENDMQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBLENDMQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPBLENDMQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBLENDMQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBLENDMQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPBLENDMQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBLENDMQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBLENDMQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPBLENDMQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBLENDMQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBLENDMQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPBLENDMQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBLENDMQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBLENDMQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPBLENDMQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBLENDMQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBLENDMQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPBLENDMQ, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBLENDMQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBLENDMQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPBLENDMQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBLENDMQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBLENDMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPBLENDMW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBLENDMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBLENDMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPBLENDMW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBLENDMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBLENDMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPBLENDMW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBLENDMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBLENDMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPBLENDMW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBLENDMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBLENDMW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPBLENDMW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBLENDMW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBLENDMW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPBLENDMW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBLENDMW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBLENDVB, sffxsclsNIL, 0, isasAVX2, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBLENDVB, sffxsclsNIL, 0, isasAVX2, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBLENDVB, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBLENDVB, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBLENDW, sffxsclsNIL, 0, isasAVX2, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBLENDW, sffxsclsNIL, 0, isasAVX2, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBLENDW, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBLENDW, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBROADCASTB, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBROADCASTB, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBROADCASTB, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBROADCASTB, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBROADCASTB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPBROADCASTB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBROADCASTB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPBROADCASTB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBROADCASTB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPBROADCASTB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBROADCASTB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPBROADCASTB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBROADCASTB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBROADCASTB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBROADCASTB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPBROADCASTB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBROADCASTB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPBROADCASTB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBROADCASTB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPBROADCASTB, sffxsclsZ, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBROADCASTB, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBROADCASTB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPBROADCASTB, sffxsclsZ, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBROADCASTB, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBROADCASTB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPBROADCASTB, sffxsclsZ, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBROADCASTB, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBROADCASTD, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBROADCASTD, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBROADCASTD, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBROADCASTD, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBROADCASTD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPBROADCASTD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBROADCASTD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPBROADCASTD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBROADCASTD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPBROADCASTD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBROADCASTD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPBROADCASTD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBROADCASTD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBROADCASTD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBROADCASTD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPBROADCASTD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBROADCASTD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPBROADCASTD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBROADCASTD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPBROADCASTD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBROADCASTD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBROADCASTD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPBROADCASTD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBROADCASTD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBROADCASTD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPBROADCASTD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBROADCASTD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBROADCASTMB2Q, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBROADCASTMB2Q, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBROADCASTMB2Q, sffxsclsNIL, 0, isasAVX512CD, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBROADCASTMW2D, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBROADCASTMW2D, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBROADCASTMW2D, sffxsclsNIL, 0, isasAVX512CD, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBROADCASTQ, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBROADCASTQ, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBROADCASTQ, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBROADCASTQ, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBROADCASTQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPBROADCASTQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBROADCASTQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPBROADCASTQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBROADCASTQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPBROADCASTQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBROADCASTQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPBROADCASTQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBROADCASTQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBROADCASTQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBROADCASTQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPBROADCASTQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBROADCASTQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPBROADCASTQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBROADCASTQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPBROADCASTQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBROADCASTQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBROADCASTQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPBROADCASTQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBROADCASTQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBROADCASTQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPBROADCASTQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBROADCASTQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBROADCASTW, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBROADCASTW, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBROADCASTW, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBROADCASTW, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBROADCASTW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPBROADCASTW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBROADCASTW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPBROADCASTW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBROADCASTW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPBROADCASTW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBROADCASTW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPBROADCASTW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBROADCASTW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBROADCASTW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBROADCASTW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPBROADCASTW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPBROADCASTW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPBROADCASTW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPBROADCASTW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPBROADCASTW, sffxsclsZ, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBROADCASTW, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBROADCASTW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPBROADCASTW, sffxsclsZ, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBROADCASTW, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBROADCASTW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPBROADCASTW, sffxsclsZ, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPBROADCASTW, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPCLMULQDQ, sffxsclsNIL, 0, isasAVX_PCLMULQDQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCLMULQDQ, sffxsclsNIL, 0, isasAVX_PCLMULQDQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCMPB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPB, sffxsclsNIL, 0, isasAVX512BW, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPB, sffxsclsNIL, 0, isasAVX512BW, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPD, sffxsclsBCST, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPD, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPD, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQB, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCMPEQB, sffxsclsNIL, featureCancellingInputs, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCMPEQB, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCMPEQB, sffxsclsNIL, featureCancellingInputs, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCMPEQB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQB, sffxsclsNIL, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQB, sffxsclsNIL, featureCancellingInputs, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQB, sffxsclsNIL, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQB, sffxsclsNIL, featureCancellingInputs, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQB, sffxsclsNIL, featureCancellingInputs, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQB, sffxsclsNIL, featureCancellingInputs, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCMPEQD, sffxsclsNIL, featureCancellingInputs, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCMPEQD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCMPEQD, sffxsclsNIL, featureCancellingInputs, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCMPEQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQD, sffxsclsNIL, featureCancellingInputs, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQD, sffxsclsNIL, featureCancellingInputs, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQD, sffxsclsNIL, featureCancellingInputs, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQD, sffxsclsNIL, featureCancellingInputs, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQD, sffxsclsNIL, featureCancellingInputs, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQD, sffxsclsNIL, featureCancellingInputs, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCMPEQQ, sffxsclsNIL, featureCancellingInputs, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCMPEQQ, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCMPEQQ, sffxsclsNIL, featureCancellingInputs, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCMPEQQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQQ, sffxsclsNIL, featureCancellingInputs, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQQ, sffxsclsNIL, featureCancellingInputs, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQQ, sffxsclsNIL, featureCancellingInputs, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQQ, sffxsclsNIL, featureCancellingInputs, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQQ, sffxsclsNIL, featureCancellingInputs, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQQ, sffxsclsNIL, featureCancellingInputs, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCMPEQW, sffxsclsNIL, featureCancellingInputs, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCMPEQW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCMPEQW, sffxsclsNIL, featureCancellingInputs, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCMPEQW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQW, sffxsclsNIL, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQW, sffxsclsNIL, featureCancellingInputs, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQW, sffxsclsNIL, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQW, sffxsclsNIL, featureCancellingInputs, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQW, sffxsclsNIL, featureCancellingInputs, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPEQW, sffxsclsNIL, featureCancellingInputs, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPESTRI, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(implregEAX), true, actionR}, {uint8(implregECX), true, actionW}, {uint8(implregEDX), true, actionR}}}, + {opcVPCMPESTRI, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(implregEAX), true, actionR}, {uint8(implregECX), true, actionW}, {uint8(implregEDX), true, actionR}}}, + {opcVPCMPESTRM, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(implregEAX), true, actionR}, {uint8(implregEDX), true, actionR}, {uint8(implregX0), true, actionW}}}, + {opcVPCMPESTRM, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(implregEAX), true, actionR}, {uint8(implregEDX), true, actionR}, {uint8(implregX0), true, actionW}}}, + {opcVPCMPGTB, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCMPGTB, sffxsclsNIL, featureCancellingInputs, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCMPGTB, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCMPGTB, sffxsclsNIL, featureCancellingInputs, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCMPGTB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTB, sffxsclsNIL, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTB, sffxsclsNIL, featureCancellingInputs, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTB, sffxsclsNIL, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTB, sffxsclsNIL, featureCancellingInputs, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTB, sffxsclsNIL, featureCancellingInputs, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTB, sffxsclsNIL, featureCancellingInputs, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCMPGTD, sffxsclsNIL, featureCancellingInputs, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCMPGTD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCMPGTD, sffxsclsNIL, featureCancellingInputs, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCMPGTD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTD, sffxsclsNIL, featureCancellingInputs, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTD, sffxsclsNIL, featureCancellingInputs, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTD, sffxsclsNIL, featureCancellingInputs, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTD, sffxsclsNIL, featureCancellingInputs, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTD, sffxsclsNIL, featureCancellingInputs, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTD, sffxsclsNIL, featureCancellingInputs, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCMPGTQ, sffxsclsNIL, featureCancellingInputs, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCMPGTQ, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCMPGTQ, sffxsclsNIL, featureCancellingInputs, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCMPGTQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTQ, sffxsclsNIL, featureCancellingInputs, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTQ, sffxsclsNIL, featureCancellingInputs, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTQ, sffxsclsNIL, featureCancellingInputs, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTQ, sffxsclsNIL, featureCancellingInputs, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTQ, sffxsclsNIL, featureCancellingInputs, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTQ, sffxsclsNIL, featureCancellingInputs, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCMPGTW, sffxsclsNIL, featureCancellingInputs, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCMPGTW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCMPGTW, sffxsclsNIL, featureCancellingInputs, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCMPGTW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTW, sffxsclsNIL, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTW, sffxsclsNIL, featureCancellingInputs, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTW, sffxsclsNIL, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTW, sffxsclsNIL, featureCancellingInputs, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTW, sffxsclsNIL, featureCancellingInputs, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPGTW, sffxsclsNIL, featureCancellingInputs, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPISTRI, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(implregECX), true, actionW}}}, + {opcVPCMPISTRI, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(implregECX), true, actionW}}}, + {opcVPCMPISTRM, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(implregX0), true, actionW}}}, + {opcVPCMPISTRM, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(implregX0), true, actionW}}}, + {opcVPCMPQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPQ, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPQ, sffxsclsBCST, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPQ, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUB, sffxsclsNIL, 0, isasAVX512BW, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUB, sffxsclsNIL, 0, isasAVX512BW, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUD, sffxsclsBCST, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUD, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUD, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUQ, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUQ, sffxsclsBCST, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUQ, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUW, sffxsclsNIL, 0, isasAVX512BW, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUW, sffxsclsNIL, 0, isasAVX512BW, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPUW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPW, sffxsclsNIL, 0, isasAVX512BW, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPW, sffxsclsNIL, 0, isasAVX512BW, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCMPW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPCOMPRESSD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVPCOMPRESSD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPCOMPRESSD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPCOMPRESSD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCOMPRESSD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPCOMPRESSD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCOMPRESSD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionRW}}}, + {opcVPCOMPRESSD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVPCOMPRESSD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPCOMPRESSD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCOMPRESSD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVPCOMPRESSD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCOMPRESSD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM512), false, actionRW}}}, + {opcVPCOMPRESSD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM512), false, actionW}}}, + {opcVPCOMPRESSD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPCOMPRESSD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPCOMPRESSD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM512), false, actionW}}}, + {opcVPCOMPRESSD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPCOMPRESSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVPCOMPRESSQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPCOMPRESSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPCOMPRESSQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCOMPRESSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPCOMPRESSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCOMPRESSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionRW}}}, + {opcVPCOMPRESSQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVPCOMPRESSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPCOMPRESSQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCOMPRESSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVPCOMPRESSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCOMPRESSQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM512), false, actionRW}}}, + {opcVPCOMPRESSQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM512), false, actionW}}}, + {opcVPCOMPRESSQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPCOMPRESSQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPCOMPRESSQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM512), false, actionW}}}, + {opcVPCOMPRESSQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPCONFLICTD, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPCONFLICTD, sffxsclsZ, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCONFLICTD, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCONFLICTD, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPCONFLICTD, sffxsclsZ, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCONFLICTD, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCONFLICTD, sffxsclsBCST, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPCONFLICTD, sffxsclsBCST_Z, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCONFLICTD, sffxsclsBCST, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPCONFLICTD, sffxsclsBCST_Z, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCONFLICTD, sffxsclsBCST, 0, isasAVX512CD_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCONFLICTD, sffxsclsBCST, 0, isasAVX512CD_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCONFLICTD, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPCONFLICTD, sffxsclsZ, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCONFLICTD, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCONFLICTD, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPCONFLICTD, sffxsclsZ, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCONFLICTD, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCONFLICTD, sffxsclsBCST, 0, isasAVX512CD, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPCONFLICTD, sffxsclsBCST_Z, 0, isasAVX512CD, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPCONFLICTD, sffxsclsBCST, 0, isasAVX512CD, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPCONFLICTD, sffxsclsNIL, 0, isasAVX512CD, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPCONFLICTD, sffxsclsZ, 0, isasAVX512CD, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPCONFLICTD, sffxsclsNIL, 0, isasAVX512CD, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPCONFLICTD, sffxsclsNIL, 0, isasAVX512CD, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPCONFLICTD, sffxsclsZ, 0, isasAVX512CD, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPCONFLICTD, sffxsclsNIL, 0, isasAVX512CD, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPCONFLICTQ, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPCONFLICTQ, sffxsclsZ, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCONFLICTQ, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCONFLICTQ, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPCONFLICTQ, sffxsclsZ, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCONFLICTQ, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCONFLICTQ, sffxsclsBCST, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPCONFLICTQ, sffxsclsBCST_Z, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCONFLICTQ, sffxsclsBCST, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPCONFLICTQ, sffxsclsBCST_Z, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCONFLICTQ, sffxsclsBCST, 0, isasAVX512CD_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCONFLICTQ, sffxsclsBCST, 0, isasAVX512CD_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCONFLICTQ, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPCONFLICTQ, sffxsclsZ, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCONFLICTQ, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPCONFLICTQ, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPCONFLICTQ, sffxsclsZ, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCONFLICTQ, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPCONFLICTQ, sffxsclsNIL, 0, isasAVX512CD, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPCONFLICTQ, sffxsclsZ, 0, isasAVX512CD, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPCONFLICTQ, sffxsclsNIL, 0, isasAVX512CD, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPCONFLICTQ, sffxsclsBCST, 0, isasAVX512CD, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPCONFLICTQ, sffxsclsBCST_Z, 0, isasAVX512CD, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPCONFLICTQ, sffxsclsBCST, 0, isasAVX512CD, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPCONFLICTQ, sffxsclsNIL, 0, isasAVX512CD, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPCONFLICTQ, sffxsclsZ, 0, isasAVX512CD, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPCONFLICTQ, sffxsclsNIL, 0, isasAVX512CD, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERM2F128, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERM2F128, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERM2I128, sffxsclsNIL, 0, isasAVX2, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERM2I128, sffxsclsNIL, 0, isasAVX2, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMB, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMB, sffxsclsZ, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMB, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMB, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMB, sffxsclsZ, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMB, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMB, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMB, sffxsclsZ, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMB, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMB, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMB, sffxsclsZ, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMB, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMB, sffxsclsNIL, 0, isasAVX512VBMI, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMB, sffxsclsZ, 0, isasAVX512VBMI, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMB, sffxsclsNIL, 0, isasAVX512VBMI, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMB, sffxsclsNIL, 0, isasAVX512VBMI, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMB, sffxsclsZ, 0, isasAVX512VBMI, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMB, sffxsclsNIL, 0, isasAVX512VBMI, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMI2B, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2B, sffxsclsZ, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2B, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2B, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2B, sffxsclsZ, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2B, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2B, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2B, sffxsclsZ, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2B, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2B, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2B, sffxsclsZ, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2B, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2B, sffxsclsNIL, 0, isasAVX512VBMI, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2B, sffxsclsZ, 0, isasAVX512VBMI, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2B, sffxsclsNIL, 0, isasAVX512VBMI, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2B, sffxsclsNIL, 0, isasAVX512VBMI, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2B, sffxsclsZ, 0, isasAVX512VBMI, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2B, sffxsclsNIL, 0, isasAVX512VBMI, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2D, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2D, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2D, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2D, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2D, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2D, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2D, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2D, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2D, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2D, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2D, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2D, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2D, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2D, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2D, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2D, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2D, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2D, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2D, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2D, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2D, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2D, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2D, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2D, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2D, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2D, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2D, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2PD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2PD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2PD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2PS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2PS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2PS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2Q, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2Q, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2Q, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2Q, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2Q, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2Q, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2Q, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2Q, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2Q, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2Q, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2Q, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2Q, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2Q, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2Q, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2Q, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2Q, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2Q, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2Q, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2Q, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2Q, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2Q, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2Q, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2Q, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2Q, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2Q, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2Q, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2Q, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2W, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2W, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2W, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2W, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2W, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2W, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2W, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2W, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2W, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMI2W, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2W, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2W, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMI2W, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2W, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2W, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2W, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2W, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMI2W, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMILPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMILPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMILPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMILPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMILPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMILPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMILPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMILPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMILPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMILPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMILPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMILPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMILPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMILPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMILPD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMILPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMILPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMILPD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMILPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMILPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMILPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMILPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMILPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMILPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMILPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMILPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMILPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMILPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMILPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMILPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMILPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMILPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMILPS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMILPS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMILPS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMILPS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMILPS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMILPS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMILPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMPD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMPD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMPD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMPD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMPD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMPD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMPD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMPD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMPS, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMPS, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMPS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMPS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMPS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMPS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMPS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMQ, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMQ, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMT2B, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2B, sffxsclsZ, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2B, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2B, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2B, sffxsclsZ, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2B, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2B, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2B, sffxsclsZ, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2B, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2B, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2B, sffxsclsZ, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2B, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2B, sffxsclsNIL, 0, isasAVX512VBMI, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2B, sffxsclsZ, 0, isasAVX512VBMI, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2B, sffxsclsNIL, 0, isasAVX512VBMI, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2B, sffxsclsNIL, 0, isasAVX512VBMI, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2B, sffxsclsZ, 0, isasAVX512VBMI, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2B, sffxsclsNIL, 0, isasAVX512VBMI, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2D, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2D, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2D, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2D, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2D, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2D, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2D, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2D, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2D, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2D, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2D, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2D, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2D, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2D, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2D, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2D, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2D, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2D, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2D, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2D, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2D, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2D, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2D, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2D, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2D, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2D, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2D, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2PD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2PD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2PD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2PD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2PD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2PS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2PS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2PS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2PS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2PS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2Q, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2Q, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2Q, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2Q, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2Q, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2Q, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2Q, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2Q, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2Q, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2Q, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2Q, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2Q, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2Q, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2Q, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2Q, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2Q, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2Q, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2Q, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2Q, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2Q, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2Q, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2Q, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2Q, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2Q, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2Q, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2Q, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2Q, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2W, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2W, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2W, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2W, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2W, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2W, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2W, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2W, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2W, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMT2W, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2W, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2W, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMT2W, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2W, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2W, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2W, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2W, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMT2W, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPERMW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPERMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPERMW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPERMW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPERMW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPERMW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPEXPANDD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPEXPANDD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPEXPANDD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPEXPANDD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPEXPANDD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPEXPANDD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPEXPANDD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPEXPANDD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPEXPANDD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPEXPANDD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPEXPANDD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPEXPANDD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPEXPANDD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPEXPANDD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPEXPANDD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPEXPANDD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPEXPANDD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPEXPANDD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPEXPANDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPEXPANDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPEXPANDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPEXPANDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPEXPANDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPEXPANDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPEXPANDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPEXPANDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPEXPANDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPEXPANDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPEXPANDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPEXPANDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPEXPANDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPEXPANDQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPEXPANDQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPEXPANDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPEXPANDQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPEXPANDQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPEXTRB, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM8), false, actionW}}}, + {opcVPEXTRB, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVPEXTRD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcVPEXTRD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVPEXTRQ, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPEXTRQ, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR64), false, actionW}}}, + {opcVPEXTRW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM16), false, actionW}}}, + {opcVPEXTRW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVPGATHERDD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeXMM), false, actionRW}, {uint8(oprndtypeVM32X), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPGATHERDD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionRW}, {uint8(oprndtypeVM32Y), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPGATHERDD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeVM32X), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPGATHERDD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeVM32Y), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPGATHERDD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeVM32Z), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPGATHERDQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeXMM), false, actionRW}, {uint8(oprndtypeVM32X), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPGATHERDQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionRW}, {uint8(oprndtypeVM32X), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPGATHERDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeVM32X), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPGATHERDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeVM32X), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPGATHERDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeVM32Y), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPGATHERQD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeXMM), false, actionRW}, {uint8(oprndtypeVM64X), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPGATHERQD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeXMM), false, actionRW}, {uint8(oprndtypeVM64Y), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPGATHERQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeVM64X), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPGATHERQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeVM64Y), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPGATHERQD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeVM64Z), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPGATHERQQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeXMM), false, actionRW}, {uint8(oprndtypeVM64X), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPGATHERQQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionRW}, {uint8(oprndtypeVM64Y), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPGATHERQQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeVM64X), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPGATHERQQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeVM64Y), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPGATHERQQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeVM64Z), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPHADDD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPHADDD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPHADDD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPHADDD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPHADDSW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPHADDSW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPHADDSW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPHADDSW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPHADDW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPHADDW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPHADDW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPHADDW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPHMINPOSUW, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPHMINPOSUW, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPHSUBD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPHSUBD, sffxsclsNIL, featureCancellingInputs, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPHSUBD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPHSUBD, sffxsclsNIL, featureCancellingInputs, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPHSUBSW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPHSUBSW, sffxsclsNIL, featureCancellingInputs, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPHSUBSW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPHSUBSW, sffxsclsNIL, featureCancellingInputs, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPHSUBW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPHSUBW, sffxsclsNIL, featureCancellingInputs, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPHSUBW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPHSUBW, sffxsclsNIL, featureCancellingInputs, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPINSRB, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM8), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPINSRB, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPINSRD, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPINSRD, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPINSRQ, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPINSRQ, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPINSRW, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPINSRW, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPLZCNTD, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPLZCNTD, sffxsclsZ, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPLZCNTD, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPLZCNTD, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPLZCNTD, sffxsclsZ, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPLZCNTD, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPLZCNTD, sffxsclsBCST, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPLZCNTD, sffxsclsBCST_Z, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPLZCNTD, sffxsclsBCST, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPLZCNTD, sffxsclsBCST_Z, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPLZCNTD, sffxsclsBCST, 0, isasAVX512CD_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPLZCNTD, sffxsclsBCST, 0, isasAVX512CD_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPLZCNTD, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPLZCNTD, sffxsclsZ, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPLZCNTD, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPLZCNTD, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPLZCNTD, sffxsclsZ, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPLZCNTD, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPLZCNTD, sffxsclsBCST, 0, isasAVX512CD, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPLZCNTD, sffxsclsBCST_Z, 0, isasAVX512CD, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPLZCNTD, sffxsclsBCST, 0, isasAVX512CD, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPLZCNTD, sffxsclsNIL, 0, isasAVX512CD, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPLZCNTD, sffxsclsZ, 0, isasAVX512CD, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPLZCNTD, sffxsclsNIL, 0, isasAVX512CD, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPLZCNTD, sffxsclsNIL, 0, isasAVX512CD, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPLZCNTD, sffxsclsZ, 0, isasAVX512CD, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPLZCNTD, sffxsclsNIL, 0, isasAVX512CD, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPLZCNTQ, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPLZCNTQ, sffxsclsZ, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPLZCNTQ, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPLZCNTQ, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPLZCNTQ, sffxsclsZ, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPLZCNTQ, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPLZCNTQ, sffxsclsBCST, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPLZCNTQ, sffxsclsBCST_Z, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPLZCNTQ, sffxsclsBCST, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPLZCNTQ, sffxsclsBCST_Z, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPLZCNTQ, sffxsclsBCST, 0, isasAVX512CD_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPLZCNTQ, sffxsclsBCST, 0, isasAVX512CD_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPLZCNTQ, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPLZCNTQ, sffxsclsZ, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPLZCNTQ, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPLZCNTQ, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPLZCNTQ, sffxsclsZ, 0, isasAVX512CD_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPLZCNTQ, sffxsclsNIL, 0, isasAVX512CD_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPLZCNTQ, sffxsclsNIL, 0, isasAVX512CD, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPLZCNTQ, sffxsclsZ, 0, isasAVX512CD, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPLZCNTQ, sffxsclsNIL, 0, isasAVX512CD, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPLZCNTQ, sffxsclsBCST, 0, isasAVX512CD, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPLZCNTQ, sffxsclsBCST_Z, 0, isasAVX512CD, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPLZCNTQ, sffxsclsBCST, 0, isasAVX512CD, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPLZCNTQ, sffxsclsNIL, 0, isasAVX512CD, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPLZCNTQ, sffxsclsZ, 0, isasAVX512CD, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPLZCNTQ, sffxsclsNIL, 0, isasAVX512CD, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMADD52HUQ, sffxsclsNIL, 0, isasAVX512IFMA_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMADD52HUQ, sffxsclsZ, 0, isasAVX512IFMA_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMADD52HUQ, sffxsclsNIL, 0, isasAVX512IFMA_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMADD52HUQ, sffxsclsNIL, 0, isasAVX512IFMA_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMADD52HUQ, sffxsclsZ, 0, isasAVX512IFMA_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMADD52HUQ, sffxsclsNIL, 0, isasAVX512IFMA_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMADD52HUQ, sffxsclsBCST, 0, isasAVX512IFMA_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMADD52HUQ, sffxsclsBCST_Z, 0, isasAVX512IFMA_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMADD52HUQ, sffxsclsBCST, 0, isasAVX512IFMA_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMADD52HUQ, sffxsclsBCST, 0, isasAVX512IFMA_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMADD52HUQ, sffxsclsBCST_Z, 0, isasAVX512IFMA_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMADD52HUQ, sffxsclsBCST, 0, isasAVX512IFMA_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMADD52HUQ, sffxsclsNIL, 0, isasAVX512IFMA_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMADD52HUQ, sffxsclsZ, 0, isasAVX512IFMA_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMADD52HUQ, sffxsclsNIL, 0, isasAVX512IFMA_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMADD52HUQ, sffxsclsNIL, 0, isasAVX512IFMA_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMADD52HUQ, sffxsclsZ, 0, isasAVX512IFMA_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMADD52HUQ, sffxsclsNIL, 0, isasAVX512IFMA_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMADD52HUQ, sffxsclsNIL, 0, isasAVX512IFMA, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMADD52HUQ, sffxsclsZ, 0, isasAVX512IFMA, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMADD52HUQ, sffxsclsNIL, 0, isasAVX512IFMA, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMADD52HUQ, sffxsclsBCST, 0, isasAVX512IFMA, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMADD52HUQ, sffxsclsBCST_Z, 0, isasAVX512IFMA, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMADD52HUQ, sffxsclsBCST, 0, isasAVX512IFMA, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMADD52HUQ, sffxsclsNIL, 0, isasAVX512IFMA, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMADD52HUQ, sffxsclsZ, 0, isasAVX512IFMA, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMADD52HUQ, sffxsclsNIL, 0, isasAVX512IFMA, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMADD52LUQ, sffxsclsNIL, 0, isasAVX512IFMA_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMADD52LUQ, sffxsclsZ, 0, isasAVX512IFMA_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMADD52LUQ, sffxsclsNIL, 0, isasAVX512IFMA_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMADD52LUQ, sffxsclsNIL, 0, isasAVX512IFMA_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMADD52LUQ, sffxsclsZ, 0, isasAVX512IFMA_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMADD52LUQ, sffxsclsNIL, 0, isasAVX512IFMA_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMADD52LUQ, sffxsclsBCST, 0, isasAVX512IFMA_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMADD52LUQ, sffxsclsBCST_Z, 0, isasAVX512IFMA_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMADD52LUQ, sffxsclsBCST, 0, isasAVX512IFMA_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMADD52LUQ, sffxsclsBCST, 0, isasAVX512IFMA_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMADD52LUQ, sffxsclsBCST_Z, 0, isasAVX512IFMA_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMADD52LUQ, sffxsclsBCST, 0, isasAVX512IFMA_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMADD52LUQ, sffxsclsNIL, 0, isasAVX512IFMA_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMADD52LUQ, sffxsclsZ, 0, isasAVX512IFMA_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMADD52LUQ, sffxsclsNIL, 0, isasAVX512IFMA_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMADD52LUQ, sffxsclsNIL, 0, isasAVX512IFMA_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMADD52LUQ, sffxsclsZ, 0, isasAVX512IFMA_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMADD52LUQ, sffxsclsNIL, 0, isasAVX512IFMA_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMADD52LUQ, sffxsclsNIL, 0, isasAVX512IFMA, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMADD52LUQ, sffxsclsZ, 0, isasAVX512IFMA, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMADD52LUQ, sffxsclsNIL, 0, isasAVX512IFMA, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMADD52LUQ, sffxsclsBCST, 0, isasAVX512IFMA, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMADD52LUQ, sffxsclsBCST_Z, 0, isasAVX512IFMA, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMADD52LUQ, sffxsclsBCST, 0, isasAVX512IFMA, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMADD52LUQ, sffxsclsNIL, 0, isasAVX512IFMA, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMADD52LUQ, sffxsclsZ, 0, isasAVX512IFMA, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMADD52LUQ, sffxsclsNIL, 0, isasAVX512IFMA, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMADDUBSW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMADDUBSW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMADDUBSW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMADDUBSW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMADDUBSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMADDUBSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMADDUBSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMADDUBSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMADDUBSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMADDUBSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMADDUBSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMADDUBSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMADDUBSW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMADDUBSW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMADDUBSW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMADDUBSW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMADDUBSW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMADDUBSW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMADDWD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMADDWD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMADDWD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMADDWD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMADDWD, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMADDWD, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMADDWD, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMADDWD, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMADDWD, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMADDWD, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMADDWD, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMADDWD, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMADDWD, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMADDWD, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMADDWD, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMADDWD, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMADDWD, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMADDWD, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMASKMOVD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMASKMOVD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMASKMOVD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMASKMOVD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVPMASKMOVQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMASKMOVQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMASKMOVQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMASKMOVQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVPMAXSB, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXSB, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXSB, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXSB, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXSB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMAXSB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXSB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMAXSB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXSB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMAXSB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXSB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMAXSB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXSB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMAXSB, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXSB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXSB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMAXSB, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXSB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXSD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXSD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXSD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXSD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXSD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMAXSD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXSD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMAXSD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXSD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMAXSD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXSD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXSD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMAXSD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXSD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXSD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMAXSD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXSD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMAXSD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXSD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMAXSD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXSD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXSD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMAXSD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXSD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXSD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMAXSD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXSD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMAXSQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMAXSQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXSQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMAXSQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXSQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXSQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMAXSQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXSQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMAXSQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMAXSQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXSQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMAXSQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXSQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXSQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMAXSQ, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXSQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXSQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMAXSQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXSQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXSW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXSW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXSW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXSW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMAXSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMAXSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMAXSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMAXSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXSW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMAXSW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXSW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXSW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMAXSW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXSW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXUB, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXUB, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXUB, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXUB, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXUB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMAXUB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXUB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMAXUB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXUB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMAXUB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXUB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMAXUB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXUB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMAXUB, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXUB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXUB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMAXUB, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXUB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXUD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXUD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXUD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXUD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXUD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMAXUD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXUD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMAXUD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXUD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMAXUD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXUD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXUD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMAXUD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXUD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXUD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMAXUD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXUD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMAXUD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXUD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMAXUD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXUD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXUD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMAXUD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXUD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXUD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMAXUD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXUD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXUQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMAXUQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXUQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXUQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMAXUQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXUQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXUQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMAXUQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXUQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXUQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMAXUQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXUQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXUQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMAXUQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXUQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXUQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMAXUQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXUQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXUQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMAXUQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXUQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXUQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMAXUQ, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXUQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXUQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMAXUQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXUQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXUW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXUW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXUW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXUW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXUW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMAXUW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXUW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMAXUW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXUW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMAXUW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMAXUW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMAXUW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMAXUW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMAXUW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXUW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXUW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMAXUW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMAXUW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINSB, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINSB, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINSB, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINSB, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINSB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMINSB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINSB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMINSB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINSB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMINSB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINSB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMINSB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINSB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMINSB, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINSB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINSB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMINSB, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINSB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINSD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINSD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINSD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINSD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINSD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMINSD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINSD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMINSD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINSD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMINSD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINSD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINSD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMINSD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINSD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINSD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMINSD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINSD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMINSD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINSD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMINSD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINSD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINSD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMINSD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINSD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINSD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMINSD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINSD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMINSQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMINSQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINSQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMINSQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINSQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINSQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMINSQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINSQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMINSQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMINSQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINSQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINSQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMINSQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINSQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINSQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMINSQ, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINSQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINSQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMINSQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINSQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINSW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINSW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINSW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINSW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMINSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMINSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMINSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMINSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINSW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMINSW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINSW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINSW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMINSW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINSW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINUB, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINUB, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINUB, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINUB, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINUB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMINUB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINUB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMINUB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINUB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMINUB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINUB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMINUB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINUB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMINUB, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINUB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINUB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMINUB, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINUB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINUD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINUD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINUD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINUD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINUD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMINUD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINUD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMINUD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINUD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMINUD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINUD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINUD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMINUD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINUD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINUD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMINUD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINUD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMINUD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINUD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMINUD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINUD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINUD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMINUD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINUD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINUD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMINUD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINUD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINUQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMINUQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINUQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINUQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMINUQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINUQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINUQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMINUQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINUQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINUQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMINUQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINUQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINUQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMINUQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINUQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINUQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMINUQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINUQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINUQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMINUQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINUQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINUQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMINUQ, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINUQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINUQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMINUQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINUQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINUW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINUW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINUW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINUW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINUW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMINUW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINUW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMINUW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINUW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMINUW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMINUW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMINUW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMINUW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMINUW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINUW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINUW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMINUW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMINUW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVB2M, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPMOVB2M, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPMOVB2M, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPMOVD2M, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPMOVD2M, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPMOVD2M, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPMOVDB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcVPMOVDB, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcVPMOVDB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVDB, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVDB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcVPMOVDB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVDB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcVPMOVDB, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVDB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVDB, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVDB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVDB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVDB, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVPMOVDB, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMOVDB, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVDB, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVDB, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMOVDB, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVDW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcVPMOVDW, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVDW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVDW, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVDW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVDW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVDW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVPMOVDW, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMOVDW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVDW, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVDW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMOVDW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVDW, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionRW}}}, + {opcVPMOVDW, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVPMOVDW, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVDW, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVDW, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVPMOVDW, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVM2B, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVM2B, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVM2B, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVM2D, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVM2D, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVM2D, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVM2Q, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVM2Q, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVM2Q, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVM2W, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVM2W, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVM2W, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVMSKB, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVPMOVMSKB, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeR32), false, actionW}}}, + {opcVPMOVQ2M, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPMOVQ2M, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPMOVQ2M, sffxsclsNIL, 0, isasAVX512DQ, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPMOVQB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcVPMOVQB, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM16), false, actionW}}}, + {opcVPMOVQB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVQB, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVQB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM16), false, actionW}}}, + {opcVPMOVQB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVQB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcVPMOVQB, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcVPMOVQB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVQB, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVQB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcVPMOVQB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVQB, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcVPMOVQB, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVQB, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVQB, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVQB, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVQB, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcVPMOVQD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVQD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVPMOVQD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMOVQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVQD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMOVQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVQD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionRW}}}, + {opcVPMOVQD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVPMOVQD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVQD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVQD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVPMOVQD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVQW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcVPMOVQW, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcVPMOVQW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVQW, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVQW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcVPMOVQW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVQW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcVPMOVQW, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVQW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVQW, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVQW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVQW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVQW, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVPMOVQW, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMOVQW, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVQW, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVQW, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMOVQW, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSDB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcVPMOVSDB, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcVPMOVSDB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVSDB, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSDB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcVPMOVSDB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSDB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcVPMOVSDB, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVSDB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVSDB, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSDB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVSDB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSDB, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVPMOVSDB, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMOVSDB, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVSDB, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSDB, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMOVSDB, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSDW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcVPMOVSDW, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVSDW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVSDW, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSDW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVSDW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSDW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVPMOVSDW, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMOVSDW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVSDW, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSDW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMOVSDW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSDW, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionRW}}}, + {opcVPMOVSDW, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVPMOVSDW, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVSDW, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVSDW, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVPMOVSDW, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVSQB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcVPMOVSQB, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM16), false, actionW}}}, + {opcVPMOVSQB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVSQB, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSQB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM16), false, actionW}}}, + {opcVPMOVSQB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSQB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcVPMOVSQB, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcVPMOVSQB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVSQB, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSQB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcVPMOVSQB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSQB, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcVPMOVSQB, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVSQB, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVSQB, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSQB, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVSQB, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcVPMOVSQD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVSQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVSQD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVSQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVPMOVSQD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMOVSQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVSQD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMOVSQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSQD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionRW}}}, + {opcVPMOVSQD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVPMOVSQD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVSQD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVSQD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVPMOVSQD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVSQW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcVPMOVSQW, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcVPMOVSQW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVSQW, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSQW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcVPMOVSQW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSQW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcVPMOVSQW, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVSQW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVSQW, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSQW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVSQW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSQW, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVPMOVSQW, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMOVSQW, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVSQW, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSQW, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMOVSQW, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcVPMOVSWB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVSWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVSWB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVSWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVPMOVSWB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMOVSWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVSWB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMOVSWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSWB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionRW}}}, + {opcVPMOVSWB, sffxsclsZ, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVPMOVSWB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVSWB, sffxsclsZ, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVSWB, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVPMOVSWB, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVSXBD, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVSXBD, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVSXBD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSXBD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSXBD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVSXBD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSXBD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVSXBD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVSXBD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVSXBD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSXBD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVSXBD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVSXBD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMOVSXBD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVSXBD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVSXBD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMOVSXBD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVSXBD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVSXBQ, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVSXBQ, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVSXBQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSXBQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSXBQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVSXBQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSXBQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVSXBQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVSXBQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVSXBQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSXBQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVSXBQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVSXBQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMOVSXBQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVSXBQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVSXBQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMOVSXBQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVSXBQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVSXBW, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVSXBW, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVSXBW, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSXBW, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSXBW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVSXBW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVSXBW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVSXBW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSXBW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVSXBW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSXBW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVSXBW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVSXBW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMOVSXBW, sffxsclsZ, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVSXBW, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVSXBW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMOVSXBW, sffxsclsZ, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVSXBW, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVSXDQ, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVSXDQ, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVSXDQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSXDQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSXDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVSXDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVSXDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVSXDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSXDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVSXDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSXDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVSXDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVSXDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMOVSXDQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVSXDQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVSXDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMOVSXDQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVSXDQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVSXWD, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVSXWD, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVSXWD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSXWD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSXWD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVSXWD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVSXWD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVSXWD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSXWD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVSXWD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSXWD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVSXWD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVSXWD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMOVSXWD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVSXWD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVSXWD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMOVSXWD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVSXWD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVSXWQ, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVSXWQ, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVSXWQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSXWQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSXWQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVSXWQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSXWQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVSXWQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVSXWQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVSXWQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVSXWQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVSXWQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVSXWQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMOVSXWQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVSXWQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVSXWQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMOVSXWQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVSXWQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVUSDB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcVPMOVUSDB, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcVPMOVUSDB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVUSDB, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVUSDB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcVPMOVUSDB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVUSDB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcVPMOVUSDB, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVUSDB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVUSDB, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVUSDB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVUSDB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVUSDB, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVPMOVUSDB, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMOVUSDB, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVUSDB, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVUSDB, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMOVUSDB, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVUSDW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcVPMOVUSDW, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVUSDW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVUSDW, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVUSDW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVUSDW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVUSDW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVPMOVUSDW, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMOVUSDW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVUSDW, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVUSDW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMOVUSDW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVUSDW, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionRW}}}, + {opcVPMOVUSDW, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVPMOVUSDW, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVUSDW, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVUSDW, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVPMOVUSDW, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVUSQB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcVPMOVUSQB, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM16), false, actionW}}}, + {opcVPMOVUSQB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVUSQB, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVUSQB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM16), false, actionW}}}, + {opcVPMOVUSQB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVUSQB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcVPMOVUSQB, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcVPMOVUSQB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVUSQB, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVUSQB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcVPMOVUSQB, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVUSQB, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcVPMOVUSQB, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVUSQB, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVUSQB, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVUSQB, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVUSQB, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVUSQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcVPMOVUSQD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVUSQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVUSQD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVUSQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVUSQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVUSQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVPMOVUSQD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMOVUSQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVUSQD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVUSQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMOVUSQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVUSQD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionRW}}}, + {opcVPMOVUSQD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVPMOVUSQD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVUSQD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVUSQD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVPMOVUSQD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVUSQW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcVPMOVUSQW, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcVPMOVUSQW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVUSQW, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVUSQW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM32), false, actionW}}}, + {opcVPMOVUSQW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVUSQW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcVPMOVUSQW, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVUSQW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVUSQW, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVUSQW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVUSQW, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVUSQW, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVPMOVUSQW, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMOVUSQW, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVUSQW, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVUSQW, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMOVUSQW, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVUSWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcVPMOVUSWB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVUSWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVUSWB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVUSWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVUSWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVUSWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVPMOVUSWB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMOVUSWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVUSWB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVUSWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMOVUSWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVUSWB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionRW}}}, + {opcVPMOVUSWB, sffxsclsZ, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVPMOVUSWB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVUSWB, sffxsclsZ, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVUSWB, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVPMOVUSWB, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVW2M, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPMOVW2M, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPMOVW2M, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPMOVWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcVPMOVWB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVWB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeM64), false, actionW}}}, + {opcVPMOVWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionRW}}}, + {opcVPMOVWB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMOVWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVWB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeM128), false, actionW}}}, + {opcVPMOVWB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVWB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionRW}}}, + {opcVPMOVWB, sffxsclsZ, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVPMOVWB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVWB, sffxsclsZ, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVWB, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeM256), false, actionW}}}, + {opcVPMOVWB, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVZXBD, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVZXBD, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVZXBD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVZXBD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVZXBD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVZXBD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVZXBD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVZXBD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVZXBD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVZXBD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVZXBD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVZXBD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVZXBD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMOVZXBD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVZXBD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVZXBD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMOVZXBD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVZXBD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVZXBQ, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVZXBQ, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVZXBQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVZXBQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVZXBQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVZXBQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVZXBQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVZXBQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVZXBQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVZXBQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVZXBQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVZXBQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVZXBQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMOVZXBQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVZXBQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVZXBQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMOVZXBQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVZXBQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVZXBW, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVZXBW, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVZXBW, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVZXBW, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVZXBW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVZXBW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVZXBW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVZXBW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVZXBW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVZXBW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVZXBW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVZXBW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVZXBW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMOVZXBW, sffxsclsZ, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVZXBW, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVZXBW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMOVZXBW, sffxsclsZ, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVZXBW, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVZXDQ, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVZXDQ, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVZXDQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVZXDQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVZXDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVZXDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVZXDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVZXDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVZXDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVZXDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVZXDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVZXDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVZXDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMOVZXDQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVZXDQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVZXDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMOVZXDQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVZXDQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVZXWD, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVZXWD, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVZXWD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVZXWD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVZXWD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVZXWD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVZXWD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVZXWD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVZXWD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVZXWD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVZXWD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVZXWD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVZXWD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMOVZXWD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVZXWD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVZXWD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMOVZXWD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVZXWD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVZXWQ, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVZXWQ, sffxsclsNIL, 0, isasAVX2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVZXWQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVZXWQ, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVZXWQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVZXWQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVZXWQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVZXWQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVZXWQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMOVZXWQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMOVZXWQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMOVZXWQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMOVZXWQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMOVZXWQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVZXWQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVZXWQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMOVZXWQ, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMOVZXWQ, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULDQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULDQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULDQ, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULDQ, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMULDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMULDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMULDQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMULDQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMULDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMULDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULDQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMULDQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULDQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMULDQ, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULDQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULDQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMULDQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULHRSW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULHRSW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULHRSW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULHRSW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULHRSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMULHRSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULHRSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMULHRSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULHRSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMULHRSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULHRSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMULHRSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULHRSW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMULHRSW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULHRSW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULHRSW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMULHRSW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULHRSW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULHUW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULHUW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULHUW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULHUW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULHUW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMULHUW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULHUW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMULHUW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULHUW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMULHUW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULHUW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMULHUW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULHUW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMULHUW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULHUW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULHUW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMULHUW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULHUW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULHW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULHW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULHW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULHW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULHW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMULHW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULHW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMULHW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULHW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMULHW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULHW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMULHW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULHW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMULHW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULHW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULHW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMULHW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULHW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULLD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULLD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULLD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULLD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMULLD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMULLD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULLD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMULLD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULLD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULLD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMULLD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULLD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMULLD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMULLD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULLD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMULLD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULLD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULLD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMULLD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULLD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULLD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMULLD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULLD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULLQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMULLQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULLQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULLQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMULLQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULLQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULLQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMULLQ, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULLQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULLQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMULLQ, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULLQ, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULLQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMULLQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULLQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULLQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMULLQ, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULLQ, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULLQ, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMULLQ, sffxsclsZ, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULLQ, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULLQ, sffxsclsBCST, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMULLQ, sffxsclsBCST_Z, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULLQ, sffxsclsBCST, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULLQ, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMULLQ, sffxsclsZ, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULLQ, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULLW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULLW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULLW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULLW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULLW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMULLW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULLW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMULLW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULLW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMULLW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULLW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMULLW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULLW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMULLW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULLW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULLW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMULLW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULLW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULTISHIFTQB, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMULTISHIFTQB, sffxsclsZ, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULTISHIFTQB, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULTISHIFTQB, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMULTISHIFTQB, sffxsclsZ, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULTISHIFTQB, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULTISHIFTQB, sffxsclsBCST, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMULTISHIFTQB, sffxsclsBCST_Z, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULTISHIFTQB, sffxsclsBCST, 0, isasAVX512VBMI_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULTISHIFTQB, sffxsclsBCST, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMULTISHIFTQB, sffxsclsBCST_Z, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULTISHIFTQB, sffxsclsBCST, 0, isasAVX512VBMI_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULTISHIFTQB, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMULTISHIFTQB, sffxsclsZ, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULTISHIFTQB, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULTISHIFTQB, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMULTISHIFTQB, sffxsclsZ, 0, isasAVX512VBMI_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULTISHIFTQB, sffxsclsNIL, 0, isasAVX512VBMI_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULTISHIFTQB, sffxsclsNIL, 0, isasAVX512VBMI, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMULTISHIFTQB, sffxsclsZ, 0, isasAVX512VBMI, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULTISHIFTQB, sffxsclsNIL, 0, isasAVX512VBMI, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULTISHIFTQB, sffxsclsBCST, 0, isasAVX512VBMI, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMULTISHIFTQB, sffxsclsBCST_Z, 0, isasAVX512VBMI, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULTISHIFTQB, sffxsclsBCST, 0, isasAVX512VBMI, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULTISHIFTQB, sffxsclsNIL, 0, isasAVX512VBMI, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMULTISHIFTQB, sffxsclsZ, 0, isasAVX512VBMI, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULTISHIFTQB, sffxsclsNIL, 0, isasAVX512VBMI, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULUDQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULUDQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULUDQ, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULUDQ, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULUDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMULUDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULUDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMULUDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULUDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMULUDQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULUDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULUDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMULUDQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULUDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULUDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPMULUDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPMULUDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPMULUDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPMULUDQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMULUDQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULUDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULUDQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMULUDQ, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULUDQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULUDQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPMULUDQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPMULUDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPOPCNTD, sffxsclsBCST, 0, isasAVX512VPOPCNTDQ, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPOPCNTD, sffxsclsBCST_Z, 0, isasAVX512VPOPCNTDQ, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPOPCNTD, sffxsclsBCST, 0, isasAVX512VPOPCNTDQ, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPOPCNTD, sffxsclsNIL, 0, isasAVX512VPOPCNTDQ, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPOPCNTD, sffxsclsZ, 0, isasAVX512VPOPCNTDQ, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPOPCNTD, sffxsclsNIL, 0, isasAVX512VPOPCNTDQ, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPOPCNTD, sffxsclsNIL, 0, isasAVX512VPOPCNTDQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPOPCNTD, sffxsclsZ, 0, isasAVX512VPOPCNTDQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPOPCNTD, sffxsclsNIL, 0, isasAVX512VPOPCNTDQ, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPOPCNTQ, sffxsclsNIL, 0, isasAVX512VPOPCNTDQ, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPOPCNTQ, sffxsclsZ, 0, isasAVX512VPOPCNTDQ, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPOPCNTQ, sffxsclsNIL, 0, isasAVX512VPOPCNTDQ, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPOPCNTQ, sffxsclsBCST, 0, isasAVX512VPOPCNTDQ, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPOPCNTQ, sffxsclsBCST_Z, 0, isasAVX512VPOPCNTDQ, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPOPCNTQ, sffxsclsBCST, 0, isasAVX512VPOPCNTDQ, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPOPCNTQ, sffxsclsNIL, 0, isasAVX512VPOPCNTDQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPOPCNTQ, sffxsclsZ, 0, isasAVX512VPOPCNTDQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPOPCNTQ, sffxsclsNIL, 0, isasAVX512VPOPCNTDQ, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPOR, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPOR, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPOR, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPOR, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPORD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPORD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPORD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPORD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPORD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPORD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPORD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPORD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPORD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPORD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPORD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPORD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPORD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPORD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPORD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPORD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPORD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPORD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPORD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPORD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPORD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPORD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPORD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPORD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPORD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPORD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPORD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPORQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPORQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPORQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPORQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPORQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPORQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPORQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPORQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPORQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPORQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPORQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPORQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPORQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPORQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPORQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPORQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPORQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPORQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPORQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPORQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPORQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPORQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPORQ, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPORQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPORQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPORQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPORQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPROLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPROLD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPROLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPROLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPROLD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPROLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPROLD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPROLD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPROLD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPROLD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPROLD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPROLD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPROLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPROLD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPROLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPROLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPROLD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPROLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPROLD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPROLD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPROLD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPROLD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPROLD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPROLD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPROLD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPROLD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPROLD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPROLQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPROLQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPROLQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPROLQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPROLQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPROLQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPROLQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPROLQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPROLQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPROLQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPROLQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPROLQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPROLQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPROLQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPROLQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPROLQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPROLQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPROLQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPROLQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPROLQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPROLQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPROLQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPROLQ, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPROLQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPROLQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPROLQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPROLQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPROLVD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPROLVD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPROLVD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPROLVD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPROLVD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPROLVD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPROLVD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPROLVD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPROLVD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPROLVD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPROLVD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPROLVD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPROLVD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPROLVD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPROLVD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPROLVD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPROLVD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPROLVD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPROLVD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPROLVD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPROLVD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPROLVD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPROLVD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPROLVD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPROLVD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPROLVD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPROLVD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPROLVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPROLVQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPROLVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPROLVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPROLVQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPROLVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPROLVQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPROLVQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPROLVQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPROLVQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPROLVQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPROLVQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPROLVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPROLVQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPROLVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPROLVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPROLVQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPROLVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPROLVQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPROLVQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPROLVQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPROLVQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPROLVQ, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPROLVQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPROLVQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPROLVQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPROLVQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPRORD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPRORD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPRORD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPRORD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPRORD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPRORD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPRORD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPRORD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPRORD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPRORD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPRORD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPRORD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPRORD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPRORD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPRORD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPRORD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPRORD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPRORD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPRORD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPRORD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPRORD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPRORD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPRORD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPRORD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPRORD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPRORD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPRORD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPRORQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPRORQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPRORQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPRORQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPRORQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPRORQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPRORQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPRORQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPRORQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPRORQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPRORQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPRORQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPRORQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPRORQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPRORQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPRORQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPRORQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPRORQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPRORQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPRORQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPRORQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPRORQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPRORQ, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPRORQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPRORQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPRORQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPRORQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPRORVD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPRORVD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPRORVD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPRORVD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPRORVD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPRORVD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPRORVD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPRORVD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPRORVD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPRORVD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPRORVD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPRORVD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPRORVD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPRORVD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPRORVD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPRORVD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPRORVD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPRORVD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPRORVD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPRORVD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPRORVD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPRORVD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPRORVD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPRORVD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPRORVD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPRORVD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPRORVD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPRORVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPRORVQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPRORVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPRORVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPRORVQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPRORVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPRORVQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPRORVQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPRORVQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPRORVQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPRORVQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPRORVQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPRORVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPRORVQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPRORVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPRORVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPRORVQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPRORVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPRORVQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPRORVQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPRORVQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPRORVQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPRORVQ, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPRORVQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPRORVQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPRORVQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPRORVQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSADBW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSADBW, sffxsclsNIL, featureCancellingInputs, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSADBW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSADBW, sffxsclsNIL, featureCancellingInputs, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSADBW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSADBW, sffxsclsNIL, featureCancellingInputs, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSCATTERDD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeVM32X), false, actionW}}}, + {opcVPSCATTERDD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeVM32Y), false, actionW}}}, + {opcVPSCATTERDD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeVM32Z), false, actionW}}}, + {opcVPSCATTERDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeVM32X), false, actionW}}}, + {opcVPSCATTERDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeVM32X), false, actionW}}}, + {opcVPSCATTERDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeVM32Y), false, actionW}}}, + {opcVPSCATTERQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeVM64X), false, actionW}}}, + {opcVPSCATTERQD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeVM64Y), false, actionW}}}, + {opcVPSCATTERQD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeVM64Z), false, actionW}}}, + {opcVPSCATTERQQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeVM64X), false, actionW}}}, + {opcVPSCATTERQQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeVM64Y), false, actionW}}}, + {opcVPSCATTERQQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeVM64Z), false, actionW}}}, + {opcVPSHUFB, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSHUFB, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSHUFB, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSHUFB, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSHUFB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSHUFB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSHUFB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSHUFB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSHUFB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSHUFB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSHUFB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSHUFB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSHUFB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSHUFB, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSHUFB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSHUFB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSHUFB, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSHUFB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSHUFD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSHUFD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSHUFD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSHUFD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSHUFD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSHUFD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSHUFD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSHUFD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSHUFD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSHUFD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSHUFD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSHUFD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSHUFD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSHUFD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSHUFD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSHUFD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSHUFD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSHUFD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSHUFD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSHUFD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSHUFD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSHUFD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSHUFD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSHUFD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSHUFD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSHUFD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSHUFD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSHUFHW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSHUFHW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSHUFHW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSHUFHW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSHUFHW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSHUFHW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSHUFHW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSHUFHW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSHUFHW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSHUFHW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSHUFHW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSHUFHW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSHUFHW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSHUFHW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSHUFHW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSHUFHW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSHUFHW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSHUFHW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSHUFLW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSHUFLW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSHUFLW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSHUFLW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSHUFLW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSHUFLW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSHUFLW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSHUFLW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSHUFLW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSHUFLW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSHUFLW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSHUFLW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSHUFLW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSHUFLW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSHUFLW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSHUFLW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSHUFLW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSHUFLW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSIGNB, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSIGNB, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSIGNB, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSIGNB, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSIGND, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSIGND, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSIGND, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSIGND, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSIGNW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSIGNW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSIGNW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSIGNW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSLLD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSLLD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSLLD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSLLD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSLLD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSLLD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSLLD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSLLD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSLLD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSLLD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSLLD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSLLD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSLLD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSLLD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSLLD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLDQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLDQ, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLDQ, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLDQ, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLDQ, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLDQ, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLQ, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLQ, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLQ, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSLLQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSLLQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSLLQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSLLQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSLLQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSLLQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSLLQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSLLQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSLLQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSLLQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSLLQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSLLQ, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSLLQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSLLQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSLLQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLVD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLVD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLVD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLVD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLVD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSLLVD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLVD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSLLVD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLVD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSLLVD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLVD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLVD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSLLVD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLVD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLVD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSLLVD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLVD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSLLVD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLVD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSLLVD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLVD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLVD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSLLVD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLVD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLVD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSLLVD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLVD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLVQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLVQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLVQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLVQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSLLVQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSLLVQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLVQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSLLVQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLVQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLVQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSLLVQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLVQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSLLVQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSLLVQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLVQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSLLVQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLVQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLVQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSLLVQ, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLVQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLVQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSLLVQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLVQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLVW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSLLVW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLVW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLVW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSLLVW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLVW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLVW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSLLVW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLVW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLVW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSLLVW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLVW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLVW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSLLVW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLVW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLVW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSLLVW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLVW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSLLW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSLLW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSLLW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSLLW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSLLW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSLLW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSLLW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSLLW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSLLW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSLLW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSLLW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSLLW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSLLW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSLLW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSLLW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRAD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRAD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRAD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRAD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRAD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRAD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRAD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRAD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRAD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRAD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRAD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRAD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRAD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRAD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRAD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRAQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRAQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRAQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRAQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRAQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRAQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRAQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRAQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRAQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRAQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRAQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRAQ, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRAQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRAQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRAQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAVD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAVD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAVD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAVD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAVD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRAVD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAVD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRAVD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAVD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRAVD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAVD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAVD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRAVD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAVD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAVD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRAVD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAVD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRAVD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAVD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRAVD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAVD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAVD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRAVD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAVD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAVD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRAVD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAVD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRAVQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRAVQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAVQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRAVQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAVQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAVQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRAVQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAVQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRAVQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRAVQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAVQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRAVQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAVQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAVQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRAVQ, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAVQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAVQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRAVQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAVQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAVW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRAVW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAVW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAVW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRAVW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAVW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAVW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRAVW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAVW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAVW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRAVW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAVW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAVW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRAVW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAVW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAVW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRAVW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAVW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRAW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRAW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRAW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRAW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRAW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRAW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRAW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRAW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRAW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRAW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRAW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRAW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRAW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRAW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRAW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRLD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRLD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRLD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRLD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRLD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRLD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRLD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRLD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRLD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRLD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRLD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRLD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRLD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRLD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRLD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLDQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLDQ, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLDQ, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLDQ, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLDQ, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLDQ, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLQ, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLQ, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLQ, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRLQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRLQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRLQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRLQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRLQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRLQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRLQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRLQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRLQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRLQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRLQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRLQ, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRLQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRLQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRLQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLVD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLVD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLVD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLVD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLVD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRLVD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLVD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRLVD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLVD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRLVD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLVD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLVD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRLVD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLVD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLVD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRLVD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLVD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRLVD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLVD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRLVD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLVD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLVD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRLVD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLVD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLVD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRLVD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLVD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLVQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLVQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLVQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLVQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRLVQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRLVQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLVQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRLVQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLVQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLVQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRLVQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLVQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRLVQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLVQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRLVQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLVQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRLVQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLVQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLVQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRLVQ, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLVQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLVQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRLVQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLVQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLVW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRLVW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLVW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLVW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRLVW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLVW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLVW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRLVW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLVW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLVW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRLVW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLVW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLVW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRLVW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLVW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLVW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRLVW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLVW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRLW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRLW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRLW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRLW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRLW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRLW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSRLW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSRLW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSRLW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSRLW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRLW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRLW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRLW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSRLW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSRLW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBB, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBB, sffxsclsNIL, featureCancellingInputs, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBB, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBB, sffxsclsNIL, featureCancellingInputs, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSUBB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSUBB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBB, sffxsclsNIL, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSUBB, sffxsclsZ, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBB, sffxsclsNIL, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSUBB, sffxsclsZ, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSUBB, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBB, sffxsclsNIL, featureCancellingInputs, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSUBB, sffxsclsZ, featureCancellingInputs, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBB, sffxsclsNIL, featureCancellingInputs, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBD, sffxsclsNIL, featureCancellingInputs, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBD, sffxsclsNIL, featureCancellingInputs, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSUBD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSUBD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSUBD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSUBD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBD, sffxsclsNIL, featureCancellingInputs, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSUBD, sffxsclsZ, featureCancellingInputs, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBD, sffxsclsNIL, featureCancellingInputs, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSUBD, sffxsclsZ, featureCancellingInputs, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSUBD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSUBD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBD, sffxsclsNIL, featureCancellingInputs, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSUBD, sffxsclsZ, featureCancellingInputs, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBD, sffxsclsNIL, featureCancellingInputs, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBQ, sffxsclsNIL, featureCancellingInputs, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBQ, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBQ, sffxsclsNIL, featureCancellingInputs, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSUBQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSUBQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSUBQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSUBQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBQ, sffxsclsNIL, featureCancellingInputs, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSUBQ, sffxsclsZ, featureCancellingInputs, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBQ, sffxsclsNIL, featureCancellingInputs, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSUBQ, sffxsclsZ, featureCancellingInputs, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSUBQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSUBQ, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBQ, sffxsclsNIL, featureCancellingInputs, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSUBQ, sffxsclsZ, featureCancellingInputs, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBQ, sffxsclsNIL, featureCancellingInputs, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBSB, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBSB, sffxsclsNIL, featureCancellingInputs, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBSB, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBSB, sffxsclsNIL, featureCancellingInputs, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBSB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSUBSB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBSB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSUBSB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBSB, sffxsclsNIL, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSUBSB, sffxsclsZ, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBSB, sffxsclsNIL, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSUBSB, sffxsclsZ, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBSB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSUBSB, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBSB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBSB, sffxsclsNIL, featureCancellingInputs, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSUBSB, sffxsclsZ, featureCancellingInputs, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBSB, sffxsclsNIL, featureCancellingInputs, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBSW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBSW, sffxsclsNIL, featureCancellingInputs, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBSW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBSW, sffxsclsNIL, featureCancellingInputs, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSUBSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSUBSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBSW, sffxsclsNIL, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSUBSW, sffxsclsZ, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBSW, sffxsclsNIL, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSUBSW, sffxsclsZ, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBSW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSUBSW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBSW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBSW, sffxsclsNIL, featureCancellingInputs, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSUBSW, sffxsclsZ, featureCancellingInputs, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBSW, sffxsclsNIL, featureCancellingInputs, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBUSB, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBUSB, sffxsclsNIL, featureCancellingInputs, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBUSB, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBUSB, sffxsclsNIL, featureCancellingInputs, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBUSB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSUBUSB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBUSB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSUBUSB, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBUSB, sffxsclsNIL, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSUBUSB, sffxsclsZ, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBUSB, sffxsclsNIL, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSUBUSB, sffxsclsZ, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBUSB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSUBUSB, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBUSB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBUSB, sffxsclsNIL, featureCancellingInputs, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSUBUSB, sffxsclsZ, featureCancellingInputs, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBUSB, sffxsclsNIL, featureCancellingInputs, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBUSW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBUSW, sffxsclsNIL, featureCancellingInputs, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBUSW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBUSW, sffxsclsNIL, featureCancellingInputs, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBUSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSUBUSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBUSW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSUBUSW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBUSW, sffxsclsNIL, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSUBUSW, sffxsclsZ, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBUSW, sffxsclsNIL, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSUBUSW, sffxsclsZ, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBUSW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSUBUSW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBUSW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBUSW, sffxsclsNIL, featureCancellingInputs, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSUBUSW, sffxsclsZ, featureCancellingInputs, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBUSW, sffxsclsNIL, featureCancellingInputs, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBW, sffxsclsNIL, featureCancellingInputs, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBW, sffxsclsNIL, featureCancellingInputs, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSUBW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSUBW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBW, sffxsclsNIL, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPSUBW, sffxsclsZ, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPSUBW, sffxsclsNIL, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPSUBW, sffxsclsZ, featureCancellingInputs, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPSUBW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSUBW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBW, sffxsclsNIL, featureCancellingInputs, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPSUBW, sffxsclsZ, featureCancellingInputs, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSUBW, sffxsclsNIL, featureCancellingInputs, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPTERNLOGD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPTERNLOGD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPTERNLOGD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPTERNLOGD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPTERNLOGD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPTERNLOGD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPTERNLOGD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPTERNLOGD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPTERNLOGD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPTERNLOGD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPTERNLOGD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPTERNLOGD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPTERNLOGD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPTERNLOGD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPTERNLOGD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPTERNLOGD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPTERNLOGD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPTERNLOGD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPTERNLOGD, sffxsclsBCST, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPTERNLOGD, sffxsclsBCST_Z, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPTERNLOGD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPTERNLOGD, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPTERNLOGD, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPTERNLOGD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPTERNLOGD, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPTERNLOGD, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPTERNLOGD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPTERNLOGQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPTERNLOGQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPTERNLOGQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPTERNLOGQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPTERNLOGQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPTERNLOGQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPTERNLOGQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPTERNLOGQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPTERNLOGQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPTERNLOGQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPTERNLOGQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPTERNLOGQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPTERNLOGQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPTERNLOGQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPTERNLOGQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPTERNLOGQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPTERNLOGQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPTERNLOGQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPTERNLOGQ, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPTERNLOGQ, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPTERNLOGQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPTERNLOGQ, sffxsclsBCST, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPTERNLOGQ, sffxsclsBCST_Z, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPTERNLOGQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPTERNLOGQ, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPTERNLOGQ, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPTERNLOGQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPTEST, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}}}, + {opcVPTEST, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}}}, + {opcVPTEST, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}}}, + {opcVPTEST, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}}}, + {opcVPTESTMB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTMW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMB, sffxsclsNIL, 0, isasAVX512BW_AVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMB, sffxsclsNIL, 0, isasAVX512BW_AVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMB, sffxsclsNIL, 0, isasAVX512BW_AVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMB, sffxsclsNIL, 0, isasAVX512BW_AVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMW, sffxsclsNIL, 0, isasAVX512BW_AVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMW, sffxsclsNIL, 0, isasAVX512BW_AVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMW, sffxsclsNIL, 0, isasAVX512BW_AVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMW, sffxsclsNIL, 0, isasAVX512BW_AVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPTESTNMW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPUNPCKHBW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKHBW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKHBW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKHBW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKHBW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPUNPCKHBW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKHBW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPUNPCKHBW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKHBW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPUNPCKHBW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKHBW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPUNPCKHBW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKHBW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPUNPCKHBW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKHBW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKHBW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPUNPCKHBW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKHBW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKHDQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKHDQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKHDQ, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKHDQ, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKHDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPUNPCKHDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKHDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPUNPCKHDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKHDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPUNPCKHDQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKHDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKHDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPUNPCKHDQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKHDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKHDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPUNPCKHDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKHDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPUNPCKHDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKHDQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPUNPCKHDQ, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKHDQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKHDQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPUNPCKHDQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKHDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKHDQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPUNPCKHDQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKHDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKHQDQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKHQDQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKHQDQ, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKHQDQ, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKHQDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPUNPCKHQDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKHQDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPUNPCKHQDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKHQDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPUNPCKHQDQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKHQDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKHQDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPUNPCKHQDQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKHQDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKHQDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPUNPCKHQDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKHQDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPUNPCKHQDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKHQDQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPUNPCKHQDQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKHQDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKHQDQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPUNPCKHQDQ, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKHQDQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKHQDQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPUNPCKHQDQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKHQDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKHWD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKHWD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKHWD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKHWD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKHWD, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPUNPCKHWD, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKHWD, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPUNPCKHWD, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKHWD, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPUNPCKHWD, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKHWD, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPUNPCKHWD, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKHWD, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPUNPCKHWD, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKHWD, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKHWD, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPUNPCKHWD, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKHWD, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKLBW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKLBW, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKLBW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKLBW, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKLBW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPUNPCKLBW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKLBW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPUNPCKLBW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKLBW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPUNPCKLBW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKLBW, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPUNPCKLBW, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKLBW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPUNPCKLBW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKLBW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKLBW, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPUNPCKLBW, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKLBW, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKLDQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKLDQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKLDQ, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKLDQ, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKLDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPUNPCKLDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKLDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPUNPCKLDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKLDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPUNPCKLDQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKLDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKLDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPUNPCKLDQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKLDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKLDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPUNPCKLDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKLDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPUNPCKLDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKLDQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPUNPCKLDQ, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKLDQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKLDQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPUNPCKLDQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKLDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKLDQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPUNPCKLDQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKLDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKLQDQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKLQDQ, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKLQDQ, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKLQDQ, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKLQDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPUNPCKLQDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKLQDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPUNPCKLQDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKLQDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPUNPCKLQDQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKLQDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKLQDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPUNPCKLQDQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKLQDQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKLQDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPUNPCKLQDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKLQDQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPUNPCKLQDQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKLQDQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPUNPCKLQDQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKLQDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKLQDQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPUNPCKLQDQ, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKLQDQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKLQDQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPUNPCKLQDQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKLQDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKLWD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKLWD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKLWD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKLWD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKLWD, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPUNPCKLWD, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKLWD, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPUNPCKLWD, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKLWD, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPUNPCKLWD, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPUNPCKLWD, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPUNPCKLWD, sffxsclsZ, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPUNPCKLWD, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPUNPCKLWD, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKLWD, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKLWD, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPUNPCKLWD, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPUNPCKLWD, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPXOR, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPXOR, sffxsclsNIL, featureCancellingInputs, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPXOR, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPXOR, sffxsclsNIL, featureCancellingInputs, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPXORD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPXORD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPXORD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPXORD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPXORD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPXORD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPXORD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPXORD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPXORD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPXORD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPXORD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPXORD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPXORD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPXORD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPXORD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPXORD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPXORD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPXORD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPXORD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPXORD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPXORD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPXORD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPXORD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPXORD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPXORD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPXORD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPXORD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPXORQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPXORQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPXORQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPXORQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPXORQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPXORQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPXORQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPXORQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPXORQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPXORQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPXORQ, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPXORQ, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPXORQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPXORQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPXORQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPXORQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPXORQ, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPXORQ, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPXORQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPXORQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPXORQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPXORQ, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPXORQ, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPXORQ, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPXORQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPXORQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPXORQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRANGEPD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRANGEPD, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRANGEPD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRANGEPD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVRANGEPD, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRANGEPD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRANGEPD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRANGEPD, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRANGEPD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRANGEPD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVRANGEPD, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRANGEPD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRANGEPD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRANGEPD, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRANGEPD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRANGEPD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVRANGEPD, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRANGEPD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRANGEPD, sffxsclsNIL, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRANGEPD, sffxsclsZ, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRANGEPD, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRANGEPD, sffxsclsBCST, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRANGEPD, sffxsclsBCST_Z, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRANGEPD, sffxsclsBCST, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRANGEPD, sffxsclsNIL, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRANGEPD, sffxsclsSAE, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRANGEPD, sffxsclsZ, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRANGEPD, sffxsclsSAE_Z, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRANGEPD, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRANGEPD, sffxsclsSAE, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRANGEPS, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRANGEPS, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRANGEPS, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRANGEPS, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVRANGEPS, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRANGEPS, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRANGEPS, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRANGEPS, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRANGEPS, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRANGEPS, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVRANGEPS, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRANGEPS, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRANGEPS, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRANGEPS, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRANGEPS, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRANGEPS, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVRANGEPS, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRANGEPS, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRANGEPS, sffxsclsBCST, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRANGEPS, sffxsclsBCST_Z, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRANGEPS, sffxsclsBCST, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRANGEPS, sffxsclsNIL, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRANGEPS, sffxsclsZ, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRANGEPS, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRANGEPS, sffxsclsNIL, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRANGEPS, sffxsclsSAE, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRANGEPS, sffxsclsZ, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRANGEPS, sffxsclsSAE_Z, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRANGEPS, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRANGEPS, sffxsclsSAE, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRANGESD, sffxsclsNIL, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRANGESD, sffxsclsZ, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRANGESD, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRANGESD, sffxsclsNIL, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRANGESD, sffxsclsSAE, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRANGESD, sffxsclsZ, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRANGESD, sffxsclsSAE_Z, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRANGESD, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRANGESD, sffxsclsSAE, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRANGESS, sffxsclsNIL, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRANGESS, sffxsclsZ, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRANGESS, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRANGESS, sffxsclsNIL, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRANGESS, sffxsclsSAE, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRANGESS, sffxsclsZ, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRANGESS, sffxsclsSAE_Z, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRANGESS, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRANGESS, sffxsclsSAE, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP14PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRCP14PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP14PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP14PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVRCP14PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRCP14PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRCP14PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRCP14PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP14PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVRCP14PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRCP14PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP14PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRCP14PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRCP14PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP14PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP14PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVRCP14PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRCP14PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRCP14PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRCP14PD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRCP14PD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRCP14PD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRCP14PD, sffxsclsBCST_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRCP14PD, sffxsclsBCST, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRCP14PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRCP14PD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRCP14PD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRCP14PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRCP14PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP14PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP14PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVRCP14PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRCP14PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRCP14PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRCP14PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP14PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVRCP14PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRCP14PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP14PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRCP14PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRCP14PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP14PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP14PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVRCP14PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRCP14PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRCP14PS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRCP14PS, sffxsclsBCST_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRCP14PS, sffxsclsBCST, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRCP14PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRCP14PS, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRCP14PS, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRCP14PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRCP14PS, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRCP14PS, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRCP14SD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRCP14SD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP14SD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP14SD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRCP14SD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP14SD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP14SS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRCP14SS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP14SS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP14SS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRCP14SS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP14SS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP28PD, sffxsclsNIL, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRCP28PD, sffxsclsZ, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRCP28PD, sffxsclsNIL, 0, isasAVX512ER, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRCP28PD, sffxsclsBCST, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRCP28PD, sffxsclsBCST_Z, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRCP28PD, sffxsclsBCST, 0, isasAVX512ER, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRCP28PD, sffxsclsNIL, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRCP28PD, sffxsclsSAE, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRCP28PD, sffxsclsZ, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRCP28PD, sffxsclsSAE_Z, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRCP28PD, sffxsclsNIL, 0, isasAVX512ER, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRCP28PD, sffxsclsSAE, 0, isasAVX512ER, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRCP28PS, sffxsclsBCST, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRCP28PS, sffxsclsBCST_Z, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRCP28PS, sffxsclsBCST, 0, isasAVX512ER, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRCP28PS, sffxsclsNIL, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRCP28PS, sffxsclsZ, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRCP28PS, sffxsclsNIL, 0, isasAVX512ER, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRCP28PS, sffxsclsNIL, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRCP28PS, sffxsclsSAE, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRCP28PS, sffxsclsZ, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRCP28PS, sffxsclsSAE_Z, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRCP28PS, sffxsclsNIL, 0, isasAVX512ER, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRCP28PS, sffxsclsSAE, 0, isasAVX512ER, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRCP28SD, sffxsclsNIL, 0, isasAVX512ER, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRCP28SD, sffxsclsZ, 0, isasAVX512ER, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP28SD, sffxsclsNIL, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP28SD, sffxsclsNIL, 0, isasAVX512ER, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRCP28SD, sffxsclsSAE, 0, isasAVX512ER, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRCP28SD, sffxsclsZ, 0, isasAVX512ER, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP28SD, sffxsclsSAE_Z, 0, isasAVX512ER, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP28SD, sffxsclsNIL, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP28SD, sffxsclsSAE, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP28SS, sffxsclsNIL, 0, isasAVX512ER, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRCP28SS, sffxsclsZ, 0, isasAVX512ER, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP28SS, sffxsclsNIL, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP28SS, sffxsclsNIL, 0, isasAVX512ER, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRCP28SS, sffxsclsSAE, 0, isasAVX512ER, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRCP28SS, sffxsclsZ, 0, isasAVX512ER, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP28SS, sffxsclsSAE_Z, 0, isasAVX512ER, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP28SS, sffxsclsNIL, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCP28SS, sffxsclsSAE, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCPPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCPPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRCPPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCPPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRCPSS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRCPSS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVREDUCEPD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVREDUCEPD, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVREDUCEPD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVREDUCEPD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVREDUCEPD, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVREDUCEPD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVREDUCEPD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVREDUCEPD, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVREDUCEPD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVREDUCEPD, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVREDUCEPD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVREDUCEPD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVREDUCEPD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVREDUCEPD, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVREDUCEPD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVREDUCEPD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVREDUCEPD, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVREDUCEPD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVREDUCEPD, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVREDUCEPD, sffxsclsZ, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVREDUCEPD, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVREDUCEPD, sffxsclsBCST, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVREDUCEPD, sffxsclsBCST_Z, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVREDUCEPD, sffxsclsBCST, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVREDUCEPD, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVREDUCEPD, sffxsclsZ, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVREDUCEPD, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVREDUCEPS, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVREDUCEPS, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVREDUCEPS, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVREDUCEPS, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVREDUCEPS, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVREDUCEPS, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVREDUCEPS, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVREDUCEPS, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVREDUCEPS, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVREDUCEPS, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVREDUCEPS, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVREDUCEPS, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVREDUCEPS, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVREDUCEPS, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVREDUCEPS, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVREDUCEPS, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVREDUCEPS, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVREDUCEPS, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVREDUCEPS, sffxsclsBCST, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVREDUCEPS, sffxsclsBCST_Z, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVREDUCEPS, sffxsclsBCST, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVREDUCEPS, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVREDUCEPS, sffxsclsZ, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVREDUCEPS, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVREDUCEPS, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVREDUCEPS, sffxsclsZ, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVREDUCEPS, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVREDUCESD, sffxsclsNIL, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVREDUCESD, sffxsclsZ, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVREDUCESD, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVREDUCESD, sffxsclsNIL, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVREDUCESD, sffxsclsZ, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVREDUCESD, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVREDUCESS, sffxsclsNIL, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVREDUCESS, sffxsclsZ, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVREDUCESS, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVREDUCESS, sffxsclsNIL, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVREDUCESS, sffxsclsZ, 0, isasAVX512DQ, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVREDUCESS, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRNDSCALEPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRNDSCALEPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRNDSCALEPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRNDSCALEPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVRNDSCALEPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRNDSCALEPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRNDSCALEPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRNDSCALEPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRNDSCALEPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVRNDSCALEPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRNDSCALEPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRNDSCALEPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRNDSCALEPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRNDSCALEPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRNDSCALEPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRNDSCALEPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVRNDSCALEPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRNDSCALEPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRNDSCALEPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRNDSCALEPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRNDSCALEPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRNDSCALEPD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRNDSCALEPD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRNDSCALEPD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRNDSCALEPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRNDSCALEPD, sffxsclsSAE, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRNDSCALEPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRNDSCALEPD, sffxsclsSAE_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRNDSCALEPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRNDSCALEPD, sffxsclsSAE, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRNDSCALEPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRNDSCALEPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRNDSCALEPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRNDSCALEPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVRNDSCALEPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRNDSCALEPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRNDSCALEPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRNDSCALEPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRNDSCALEPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVRNDSCALEPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRNDSCALEPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRNDSCALEPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRNDSCALEPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRNDSCALEPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRNDSCALEPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRNDSCALEPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVRNDSCALEPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRNDSCALEPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRNDSCALEPS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRNDSCALEPS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRNDSCALEPS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRNDSCALEPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRNDSCALEPS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRNDSCALEPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRNDSCALEPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRNDSCALEPS, sffxsclsSAE, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRNDSCALEPS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRNDSCALEPS, sffxsclsSAE_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRNDSCALEPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRNDSCALEPS, sffxsclsSAE, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRNDSCALESD, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRNDSCALESD, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRNDSCALESD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRNDSCALESD, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRNDSCALESD, sffxsclsSAE, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRNDSCALESD, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRNDSCALESD, sffxsclsSAE_Z, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRNDSCALESD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRNDSCALESD, sffxsclsSAE, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRNDSCALESS, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRNDSCALESS, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRNDSCALESS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRNDSCALESS, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRNDSCALESS, sffxsclsSAE, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRNDSCALESS, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRNDSCALESS, sffxsclsSAE_Z, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRNDSCALESS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRNDSCALESS, sffxsclsSAE, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVROUNDPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVROUNDPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVROUNDPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVROUNDPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVROUNDPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVROUNDPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVROUNDPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVROUNDPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVROUNDSD, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVROUNDSD, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVROUNDSS, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVROUNDSS, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT14PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRSQRT14PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT14PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT14PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVRSQRT14PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRSQRT14PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRSQRT14PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRSQRT14PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT14PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVRSQRT14PD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRSQRT14PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT14PD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRSQRT14PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRSQRT14PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT14PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT14PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVRSQRT14PD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRSQRT14PD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRSQRT14PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRSQRT14PD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRSQRT14PD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRSQRT14PD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRSQRT14PD, sffxsclsBCST_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRSQRT14PD, sffxsclsBCST, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRSQRT14PD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRSQRT14PD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRSQRT14PD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRSQRT14PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRSQRT14PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT14PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT14PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVRSQRT14PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRSQRT14PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRSQRT14PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRSQRT14PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT14PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVRSQRT14PS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRSQRT14PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT14PS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRSQRT14PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRSQRT14PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT14PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT14PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVRSQRT14PS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRSQRT14PS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRSQRT14PS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRSQRT14PS, sffxsclsBCST_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRSQRT14PS, sffxsclsBCST, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRSQRT14PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRSQRT14PS, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRSQRT14PS, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRSQRT14PS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRSQRT14PS, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRSQRT14PS, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRSQRT14SD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRSQRT14SD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT14SD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT14SD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRSQRT14SD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT14SD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT14SS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRSQRT14SS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT14SS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT14SS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRSQRT14SS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT14SS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT28PD, sffxsclsNIL, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRSQRT28PD, sffxsclsZ, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRSQRT28PD, sffxsclsNIL, 0, isasAVX512ER, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRSQRT28PD, sffxsclsBCST, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRSQRT28PD, sffxsclsBCST_Z, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRSQRT28PD, sffxsclsBCST, 0, isasAVX512ER, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRSQRT28PD, sffxsclsNIL, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRSQRT28PD, sffxsclsSAE, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRSQRT28PD, sffxsclsZ, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRSQRT28PD, sffxsclsSAE_Z, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRSQRT28PD, sffxsclsNIL, 0, isasAVX512ER, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRSQRT28PD, sffxsclsSAE, 0, isasAVX512ER, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRSQRT28PS, sffxsclsBCST, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRSQRT28PS, sffxsclsBCST_Z, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRSQRT28PS, sffxsclsBCST, 0, isasAVX512ER, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRSQRT28PS, sffxsclsNIL, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRSQRT28PS, sffxsclsZ, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRSQRT28PS, sffxsclsNIL, 0, isasAVX512ER, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRSQRT28PS, sffxsclsNIL, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRSQRT28PS, sffxsclsSAE, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVRSQRT28PS, sffxsclsZ, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRSQRT28PS, sffxsclsSAE_Z, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRSQRT28PS, sffxsclsNIL, 0, isasAVX512ER, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRSQRT28PS, sffxsclsSAE, 0, isasAVX512ER, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVRSQRT28SD, sffxsclsNIL, 0, isasAVX512ER, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRSQRT28SD, sffxsclsZ, 0, isasAVX512ER, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT28SD, sffxsclsNIL, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT28SD, sffxsclsNIL, 0, isasAVX512ER, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRSQRT28SD, sffxsclsSAE, 0, isasAVX512ER, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRSQRT28SD, sffxsclsZ, 0, isasAVX512ER, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT28SD, sffxsclsSAE_Z, 0, isasAVX512ER, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT28SD, sffxsclsNIL, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT28SD, sffxsclsSAE, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT28SS, sffxsclsNIL, 0, isasAVX512ER, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRSQRT28SS, sffxsclsZ, 0, isasAVX512ER, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT28SS, sffxsclsNIL, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT28SS, sffxsclsNIL, 0, isasAVX512ER, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRSQRT28SS, sffxsclsSAE, 0, isasAVX512ER, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVRSQRT28SS, sffxsclsZ, 0, isasAVX512ER, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT28SS, sffxsclsSAE_Z, 0, isasAVX512ER, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT28SS, sffxsclsNIL, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRT28SS, sffxsclsSAE, 0, isasAVX512ER, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRTPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRTPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRSQRTPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRTPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVRSQRTSS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVRSQRTSS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSCALEFPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSCALEFPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSCALEFPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSCALEFPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSCALEFPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSCALEFPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSCALEFPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSCALEFPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSCALEFPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSCALEFPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSCALEFPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSCALEFPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSCALEFPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSCALEFPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSCALEFPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSCALEFPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSCALEFPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSCALEFPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSCALEFPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSCALEFPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSCALEFPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSCALEFPD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSCALEFPD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSCALEFPD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSCALEFPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSCALEFPD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSCALEFPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSCALEFPD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSCALEFPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSCALEFPD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSCALEFPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSCALEFPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSCALEFPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSCALEFPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSCALEFPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSCALEFPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSCALEFPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSCALEFPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSCALEFPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSCALEFPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSCALEFPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSCALEFPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSCALEFPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSCALEFPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSCALEFPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSCALEFPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSCALEFPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSCALEFPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSCALEFPS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSCALEFPS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSCALEFPS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSCALEFPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSCALEFPS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSCALEFPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSCALEFPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSCALEFPS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSCALEFPS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSCALEFPS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSCALEFPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSCALEFPS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSCALEFSD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSCALEFSD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSCALEFSD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSCALEFSD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSCALEFSD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSCALEFSD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSCALEFSD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSCALEFSD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSCALEFSD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSCALEFSS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSCALEFSS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSCALEFSS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSCALEFSS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSCALEFSS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSCALEFSS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSCALEFSS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSCALEFSS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSCALEFSS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSCATTERDPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeVM32X), false, actionW}}}, + {opcVSCATTERDPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeVM32X), false, actionW}}}, + {opcVSCATTERDPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeVM32Y), false, actionW}}}, + {opcVSCATTERDPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeVM32X), false, actionW}}}, + {opcVSCATTERDPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeVM32Y), false, actionW}}}, + {opcVSCATTERDPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeVM32Z), false, actionW}}}, + {opcVSCATTERQPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeVM64X), false, actionW}}}, + {opcVSCATTERQPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeVM64Y), false, actionW}}}, + {opcVSCATTERQPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeVM64Z), false, actionW}}}, + {opcVSCATTERQPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeVM64X), false, actionW}}}, + {opcVSCATTERQPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeVM64Y), false, actionW}}}, + {opcVSCATTERQPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeVM64Z), false, actionW}}}, + {opcVSHUFF32X4, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSHUFF32X4, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFF32X4, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFF32X4, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSHUFF32X4, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFF32X4, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFF32X4, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSHUFF32X4, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFF32X4, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFF32X4, sffxsclsBCST, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSHUFF32X4, sffxsclsBCST_Z, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFF32X4, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFF32X4, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSHUFF32X4, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFF32X4, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFF32X4, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSHUFF32X4, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFF32X4, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFF64X2, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSHUFF64X2, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFF64X2, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFF64X2, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSHUFF64X2, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFF64X2, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFF64X2, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSHUFF64X2, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFF64X2, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFF64X2, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSHUFF64X2, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFF64X2, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFF64X2, sffxsclsBCST, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSHUFF64X2, sffxsclsBCST_Z, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFF64X2, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFF64X2, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSHUFF64X2, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFF64X2, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFI32X4, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSHUFI32X4, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFI32X4, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFI32X4, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSHUFI32X4, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFI32X4, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFI32X4, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSHUFI32X4, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFI32X4, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFI32X4, sffxsclsBCST, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSHUFI32X4, sffxsclsBCST_Z, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFI32X4, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFI32X4, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSHUFI32X4, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFI32X4, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFI32X4, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSHUFI32X4, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFI32X4, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFI64X2, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSHUFI64X2, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFI64X2, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFI64X2, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSHUFI64X2, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFI64X2, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFI64X2, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSHUFI64X2, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFI64X2, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFI64X2, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSHUFI64X2, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFI64X2, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFI64X2, sffxsclsBCST, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSHUFI64X2, sffxsclsBCST_Z, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFI64X2, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFI64X2, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSHUFI64X2, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFI64X2, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFPD, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSHUFPD, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFPD, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSHUFPD, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSHUFPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSHUFPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSHUFPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSHUFPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSHUFPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSHUFPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSHUFPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSHUFPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSHUFPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSHUFPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFPD, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSHUFPD, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFPD, sffxsclsBCST, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSHUFPD, sffxsclsBCST_Z, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFPD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFPD, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSHUFPD, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFPS, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSHUFPS, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFPS, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSHUFPS, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSHUFPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSHUFPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSHUFPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSHUFPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSHUFPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSHUFPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSHUFPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSHUFPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSHUFPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSHUFPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSHUFPS, sffxsclsBCST, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSHUFPS, sffxsclsBCST_Z, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFPS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFPS, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSHUFPS, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFPS, sffxsclsNIL, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSHUFPS, sffxsclsZ, 0, isasAVX512F, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSHUFPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSQRTPD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSQRTPD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSQRTPD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSQRTPD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSQRTPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSQRTPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSQRTPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSQRTPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSQRTPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSQRTPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSQRTPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSQRTPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSQRTPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSQRTPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSQRTPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSQRTPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSQRTPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSQRTPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSQRTPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSQRTPD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSQRTPD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSQRTPD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSQRTPD, sffxsclsBCST_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSQRTPD, sffxsclsBCST, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSQRTPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSQRTPD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSQRTPD, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSQRTPD, sffxsclsER_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSQRTPD, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSQRTPD, sffxsclsER, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSQRTPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSQRTPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSQRTPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSQRTPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSQRTPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSQRTPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSQRTPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSQRTPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSQRTPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSQRTPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSQRTPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSQRTPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSQRTPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSQRTPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSQRTPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSQRTPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSQRTPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSQRTPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSQRTPS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSQRTPS, sffxsclsBCST_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSQRTPS, sffxsclsBCST, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSQRTPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSQRTPS, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSQRTPS, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSQRTPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSQRTPS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSQRTPS, sffxsclsZ, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSQRTPS, sffxsclsER_Z, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSQRTPS, sffxsclsNIL, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSQRTPS, sffxsclsER, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSQRTSD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSQRTSD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSQRTSD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSQRTSD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSQRTSD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSQRTSD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSQRTSD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSQRTSD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSQRTSD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSQRTSS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSQRTSS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSQRTSS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSQRTSS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSQRTSS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSQRTSS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSQRTSS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSQRTSS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSQRTSS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSTMXCSR, sffxsclsNIL, 0, isasAVX, 1, oprnds{{uint8(oprndtypeM32), false, actionW}}}, + {opcVSUBPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSUBPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSUBPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSUBPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSUBPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSUBPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSUBPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSUBPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSUBPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSUBPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSUBPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSUBPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSUBPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSUBPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSUBPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSUBPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSUBPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSUBPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSUBPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSUBPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSUBPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSUBPD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSUBPD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSUBPD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSUBPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSUBPD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSUBPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSUBPD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSUBPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSUBPD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSUBPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSUBPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSUBPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSUBPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSUBPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSUBPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSUBPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSUBPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSUBPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSUBPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSUBPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSUBPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSUBPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSUBPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSUBPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSUBPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSUBPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVSUBPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVSUBPS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSUBPS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSUBPS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSUBPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSUBPS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSUBPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSUBPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSUBPS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVSUBPS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSUBPS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSUBPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSUBPS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVSUBSD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSUBSD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSUBSD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSUBSD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSUBSD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSUBSD, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSUBSD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSUBSD, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSUBSD, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSUBSS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSUBSS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSUBSS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSUBSS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSUBSS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSUBSS, sffxsclsER, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVSUBSS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSUBSS, sffxsclsER_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVSUBSS, sffxsclsER, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVTESTPD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}}}, + {opcVTESTPD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}}}, + {opcVTESTPD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}}}, + {opcVTESTPD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}}}, + {opcVTESTPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}}}, + {opcVTESTPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}}}, + {opcVTESTPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}}}, + {opcVTESTPS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}}}, + {opcVUCOMISD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}}}, + {opcVUCOMISD, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}}}, + {opcVUCOMISD, sffxsclsSAE, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}}}, + {opcVUCOMISS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}}}, + {opcVUCOMISS, sffxsclsNIL, 0, isasAVX, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}}}, + {opcVUCOMISS, sffxsclsSAE, 0, isasAVX512F, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}}}, + {opcVUNPCKHPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVUNPCKHPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVUNPCKHPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVUNPCKHPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVUNPCKHPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVUNPCKHPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVUNPCKHPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVUNPCKHPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVUNPCKHPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVUNPCKHPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVUNPCKHPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVUNPCKHPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVUNPCKHPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVUNPCKHPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVUNPCKHPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVUNPCKHPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVUNPCKHPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVUNPCKHPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVUNPCKHPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVUNPCKHPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVUNPCKHPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVUNPCKHPD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVUNPCKHPD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVUNPCKHPD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVUNPCKHPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVUNPCKHPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVUNPCKHPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVUNPCKHPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVUNPCKHPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVUNPCKHPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVUNPCKHPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVUNPCKHPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVUNPCKHPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVUNPCKHPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVUNPCKHPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVUNPCKHPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVUNPCKHPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVUNPCKHPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVUNPCKHPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVUNPCKHPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVUNPCKHPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVUNPCKHPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVUNPCKHPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVUNPCKHPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVUNPCKHPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVUNPCKHPS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVUNPCKHPS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVUNPCKHPS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVUNPCKHPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVUNPCKHPS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVUNPCKHPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVUNPCKHPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVUNPCKHPS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVUNPCKHPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVUNPCKLPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVUNPCKLPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVUNPCKLPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVUNPCKLPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVUNPCKLPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVUNPCKLPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVUNPCKLPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVUNPCKLPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVUNPCKLPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVUNPCKLPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVUNPCKLPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVUNPCKLPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVUNPCKLPD, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVUNPCKLPD, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVUNPCKLPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVUNPCKLPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVUNPCKLPD, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVUNPCKLPD, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVUNPCKLPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVUNPCKLPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVUNPCKLPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVUNPCKLPD, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVUNPCKLPD, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVUNPCKLPD, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVUNPCKLPD, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVUNPCKLPD, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVUNPCKLPD, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVUNPCKLPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVUNPCKLPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVUNPCKLPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVUNPCKLPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVUNPCKLPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVUNPCKLPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVUNPCKLPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVUNPCKLPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVUNPCKLPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVUNPCKLPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVUNPCKLPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVUNPCKLPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVUNPCKLPS, sffxsclsBCST_Z, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVUNPCKLPS, sffxsclsBCST, 0, isasAVX512F_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVUNPCKLPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVUNPCKLPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVUNPCKLPS, sffxsclsNIL, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVUNPCKLPS, sffxsclsZ, 0, isasAVX512F_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVUNPCKLPS, sffxsclsBCST, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVUNPCKLPS, sffxsclsBCST_Z, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVUNPCKLPS, sffxsclsBCST, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVUNPCKLPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVUNPCKLPS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVUNPCKLPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVUNPCKLPS, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVUNPCKLPS, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVUNPCKLPS, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVXORPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVXORPD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVXORPD, sffxsclsNIL, featureCancellingInputs, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVXORPD, sffxsclsNIL, featureCancellingInputs, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVXORPD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVXORPD, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVXORPD, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVXORPD, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVXORPD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVXORPD, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVXORPD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVXORPD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVXORPD, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVXORPD, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVXORPD, sffxsclsNIL, featureCancellingInputs, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVXORPD, sffxsclsZ, featureCancellingInputs, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVXORPD, sffxsclsNIL, featureCancellingInputs, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVXORPD, sffxsclsZ, featureCancellingInputs, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVXORPD, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVXORPD, sffxsclsZ, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVXORPD, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVXORPD, sffxsclsBCST, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVXORPD, sffxsclsBCST_Z, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVXORPD, sffxsclsBCST, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVXORPD, sffxsclsNIL, featureCancellingInputs, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVXORPD, sffxsclsZ, featureCancellingInputs, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVXORPD, sffxsclsNIL, featureCancellingInputs, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVXORPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVXORPS, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVXORPS, sffxsclsNIL, featureCancellingInputs, isasAVX, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVXORPS, sffxsclsNIL, featureCancellingInputs, isasAVX, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVXORPS, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVXORPS, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVXORPS, sffxsclsNIL, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVXORPS, sffxsclsZ, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVXORPS, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVXORPS, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVXORPS, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVXORPS, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVXORPS, sffxsclsBCST_Z, 0, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVXORPS, sffxsclsBCST, 0, isasAVX512DQ_AVX512VL, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVXORPS, sffxsclsNIL, featureCancellingInputs, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVXORPS, sffxsclsZ, featureCancellingInputs, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVXORPS, sffxsclsNIL, featureCancellingInputs, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVXORPS, sffxsclsZ, featureCancellingInputs, isasAVX512DQ_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVXORPS, sffxsclsBCST, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVXORPS, sffxsclsBCST_Z, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVXORPS, sffxsclsBCST, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVXORPS, sffxsclsNIL, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVXORPS, sffxsclsZ, 0, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVXORPS, sffxsclsNIL, 0, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVXORPS, sffxsclsNIL, featureCancellingInputs, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVXORPS, sffxsclsZ, featureCancellingInputs, isasAVX512DQ, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVXORPS, sffxsclsNIL, featureCancellingInputs, isasAVX512DQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVZEROALL, sffxsclsNIL, 0, isasAVX, 0, oprnds{}}, + {opcVZEROUPPER, sffxsclsNIL, 0, isasAVX, 0, oprnds{}}, + {opcXADDB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionRW}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcXADDB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionRW}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcXADDL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionRW}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcXADDL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionRW}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcXADDQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionRW}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcXADDQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionRW}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcXADDW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionRW}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcXADDW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionRW}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcXCHGB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM8), false, actionRW}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcXCHGB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionRW}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcXCHGB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionRW}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcXCHGL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeEAX), false, actionRW}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcXCHGL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM32), false, actionRW}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcXCHGL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionRW}, {uint8(oprndtypeEAX), false, actionRW}}}, + {opcXCHGL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionRW}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcXCHGL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionRW}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcXCHGQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM64), false, actionRW}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcXCHGQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionRW}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcXCHGQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionRW}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcXCHGQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionRW}, {uint8(oprndtypeRAX), false, actionRW}}}, + {opcXCHGQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeRAX), false, actionRW}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcXCHGW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeAX), false, actionRW}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcXCHGW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM16), false, actionRW}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcXCHGW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionRW}, {uint8(oprndtypeAX), false, actionRW}}}, + {opcXCHGW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionRW}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcXCHGW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionRW}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcXGETBV, sffxsclsNIL, 0, isasBase, 0, oprnds{{uint8(implregEAX), true, actionW}, {uint8(implregECX), true, actionR}, {uint8(implregEDX), true, actionW}}}, + {opcXLAT, sffxsclsNIL, 0, isasBase, 0, oprnds{{uint8(implregAL), true, actionRW}, {uint8(implregEBX), true, actionR}}}, + {opcXORB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeAL), false, actionRW}}}, + {opcXORB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcXORB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcXORB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM8), false, actionR}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcXORB, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(oprndtypeM8), false, actionRW}}}, + {opcXORB, sffxsclsNIL, featureCancellingInputs, isasBase, 2, oprnds{{uint8(oprndtypeR8), false, actionR}, {uint8(oprndtypeR8), false, actionRW}}}, + {opcXORL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeEAX), false, actionRW}}}, + {opcXORL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcXORL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcXORL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcXORL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcXORL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcXORL, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeM32), false, actionRW}}}, + {opcXORL, sffxsclsNIL, featureCancellingInputs, isasBase, 2, oprnds{{uint8(oprndtypeR32), false, actionR}, {uint8(oprndtypeR32), false, actionRW}}}, + {opcXORPD, sffxsclsNIL, 0, isasSSE2, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcXORPD, sffxsclsNIL, featureCancellingInputs, isasSSE2, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcXORPS, sffxsclsNIL, 0, isasSSE, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcXORPS, sffxsclsNIL, featureCancellingInputs, isasSSE, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcXORQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcXORQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcXORQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM32), false, actionN}, {uint8(oprndtypeRAX), false, actionRW}}}, + {opcXORQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcXORQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcXORQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcXORQ, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeM64), false, actionRW}}}, + {opcXORQ, sffxsclsNIL, featureCancellingInputs, isasBase, 2, oprnds{{uint8(oprndtypeR64), false, actionR}, {uint8(oprndtypeR64), false, actionRW}}}, + {opcXORW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM16), false, actionN}, {uint8(oprndtypeAX), false, actionRW}}}, + {opcXORW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM16), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcXORW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM16), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcXORW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcXORW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcXORW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeM16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, + {opcXORW, sffxsclsNIL, 0, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeM16), false, actionRW}}}, + {opcXORW, sffxsclsNIL, featureCancellingInputs, isasBase, 2, oprnds{{uint8(oprndtypeR16), false, actionR}, {uint8(oprndtypeR16), false, actionRW}}}, +} + +func (o opc) Forms() []form { + if opcNone < o && o < opcmax { + return opcformstable[o-1] + } + return nil +} + +var opcformstable = [][]form{ + forms[0:6], + forms[6:14], + forms[14:22], + forms[22:30], + forms[30:32], + forms[32:34], + forms[34:40], + forms[40:48], + forms[48:50], + forms[50:52], + forms[52:60], + forms[60:62], + forms[62:64], + forms[64:66], + forms[66:68], + forms[68:76], + forms[76:78], + forms[78:80], + forms[80:82], + forms[82:84], + forms[84:86], + forms[86:88], + forms[88:90], + forms[90:92], + forms[92:98], + forms[98:106], + forms[106:108], + forms[108:110], + forms[110:112], + forms[112:114], + forms[114:116], + forms[116:118], + forms[118:126], + forms[126:134], + forms[134:136], + forms[136:138], + forms[138:140], + forms[140:142], + forms[142:144], + forms[144:146], + forms[146:148], + forms[148:150], + forms[150:152], + forms[152:154], + forms[154:156], + forms[156:158], + forms[158:160], + forms[160:162], + forms[162:164], + forms[164:166], + forms[166:168], + forms[168:170], + forms[170:171], + forms[171:172], + forms[172:176], + forms[176:180], + forms[180:184], + forms[184:188], + forms[188:192], + forms[192:196], + forms[196:200], + forms[200:204], + forms[204:208], + forms[208:212], + forms[212:216], + forms[216:220], + forms[220:222], + forms[222:224], + forms[224:225], + forms[225:226], + forms[226:227], + forms[227:228], + forms[228:229], + forms[229:230], + forms[230:231], + forms[231:232], + forms[232:233], + forms[233:235], + forms[235:237], + forms[237:239], + forms[239:241], + forms[241:243], + forms[243:245], + forms[245:247], + forms[247:249], + forms[249:251], + forms[251:253], + forms[253:255], + forms[255:257], + forms[257:259], + forms[259:261], + forms[261:263], + forms[263:265], + forms[265:267], + forms[267:269], + forms[269:271], + forms[271:273], + forms[273:275], + forms[275:277], + forms[277:279], + forms[279:281], + forms[281:283], + forms[283:285], + forms[285:287], + forms[287:289], + forms[289:291], + forms[291:293], + forms[293:295], + forms[295:297], + forms[297:299], + forms[299:301], + forms[301:303], + forms[303:305], + forms[305:307], + forms[307:309], + forms[309:311], + forms[311:313], + forms[313:315], + forms[315:317], + forms[317:319], + forms[319:321], + forms[321:323], + forms[323:325], + forms[325:327], + forms[327:329], + forms[329:335], + forms[335:343], + forms[343:345], + forms[345:347], + forms[347:355], + forms[355:357], + forms[357:359], + forms[359:367], + forms[367:368], + forms[368:369], + forms[369:371], + forms[371:373], + forms[373:375], + forms[375:377], + forms[377:379], + forms[379:381], + forms[381:382], + forms[382:383], + forms[383:387], + forms[387:389], + forms[389:391], + forms[391:393], + forms[393:395], + forms[395:397], + forms[397:399], + forms[399:401], + forms[401:403], + forms[403:405], + forms[405:409], + forms[409:411], + forms[411:413], + forms[413:415], + forms[415:417], + forms[417:419], + forms[419:421], + forms[421:425], + forms[425:427], + forms[427:429], + forms[429:431], + forms[431:433], + forms[433:437], + forms[437:438], + forms[438:439], + forms[439:441], + forms[441:443], + forms[443:445], + forms[445:447], + forms[447:449], + forms[449:451], + forms[451:453], + forms[453:455], + forms[455:457], + forms[457:459], + forms[459:461], + forms[461:463], + forms[463:465], + forms[465:467], + forms[467:469], + forms[469:471], + forms[471:473], + forms[473:475], + forms[475:477], + forms[477:479], + forms[479:481], + forms[481:483], + forms[483:485], + forms[485:489], + forms[489:493], + forms[493:497], + forms[497:499], + forms[499:503], + forms[503:507], + forms[507:511], + forms[511:513], + forms[513:515], + forms[515:517], + forms[517:519], + forms[519:521], + forms[521:523], + forms[523:525], + forms[525:527], + forms[527:529], + forms[529:531], + forms[531:533], + forms[533:535], + forms[535:537], + forms[537:538], + forms[538:539], + forms[539:541], + forms[541:543], + forms[543:545], + forms[545:547], + forms[547:549], + forms[549:551], + forms[551:553], + forms[553:555], + forms[555:557], + forms[557:559], + forms[559:561], + forms[561:563], + forms[563:565], + forms[565:569], + forms[569:571], + forms[571:573], + forms[573:575], + forms[575:577], + forms[577:579], + forms[579:581], + forms[581:583], + forms[583:585], + forms[585:587], + forms[587:589], + forms[589:591], + forms[591:593], + forms[593:595], + forms[595:597], + forms[597:599], + forms[599:601], + forms[601:603], + forms[603:605], + forms[605:607], + forms[607:609], + forms[609:611], + forms[611:613], + forms[613:615], + forms[615:617], + forms[617:619], + forms[619:620], + forms[620:621], + forms[621:622], + forms[622:623], + forms[623:624], + forms[624:625], + forms[625:626], + forms[626:627], + forms[627:628], + forms[628:629], + forms[629:630], + forms[630:631], + forms[631:636], + forms[636:641], + forms[641:646], + forms[646:651], + forms[651:652], + forms[652:653], + forms[653:654], + forms[654:655], + forms[655:656], + forms[656:657], + forms[657:658], + forms[658:659], + forms[659:660], + forms[660:661], + forms[661:662], + forms[662:663], + forms[663:664], + forms[664:665], + forms[665:666], + forms[666:667], + forms[667:668], + forms[668:669], + forms[669:670], + forms[670:671], + forms[671:672], + forms[672:673], + forms[673:674], + forms[674:675], + forms[675:676], + forms[676:677], + forms[677:678], + forms[678:679], + forms[679:680], + forms[680:681], + forms[681:682], + forms[682:683], + forms[683:684], + forms[684:685], + forms[685:686], + forms[686:687], + forms[687:688], + forms[688:689], + forms[689:690], + forms[690:691], + forms[691:692], + forms[692:694], + forms[694:696], + forms[696:698], + forms[698:699], + forms[699:700], + forms[700:702], + forms[702:704], + forms[704:706], + forms[706:708], + forms[708:709], + forms[709:711], + forms[711:713], + forms[713:715], + forms[715:717], + forms[717:718], + forms[718:721], + forms[721:724], + forms[724:729], + forms[729:731], + forms[731:733], + forms[733:735], + forms[735:737], + forms[737:739], + forms[739:741], + forms[741:743], + forms[743:745], + forms[745:747], + forms[747:762], + forms[762:764], + forms[764:779], + forms[779:780], + forms[780:782], + forms[782:784], + forms[784:789], + forms[789:790], + forms[790:792], + forms[792:794], + forms[794:796], + forms[796:797], + forms[797:798], + forms[798:799], + forms[799:800], + forms[800:801], + forms[801:802], + forms[802:803], + forms[803:804], + forms[804:805], + forms[805:806], + forms[806:809], + forms[809:812], + forms[812:815], + forms[815:830], + forms[830:833], + forms[833:835], + forms[835:837], + forms[837:840], + forms[840:843], + forms[843:846], + forms[846:851], + forms[851:853], + forms[853:855], + forms[855:857], + forms[857:859], + forms[859:861], + forms[861:863], + forms[863:865], + forms[865:867], + forms[867:869], + forms[869:871], + forms[871:873], + forms[873:875], + forms[875:877], + forms[877:879], + forms[879:881], + forms[881:882], + forms[882:884], + forms[884:886], + forms[886:888], + forms[888:890], + forms[890:891], + forms[891:893], + forms[893:895], + forms[895:897], + forms[897:899], + forms[899:905], + forms[905:913], + forms[913:915], + forms[915:917], + forms[917:925], + forms[925:933], + forms[933:935], + forms[935:937], + forms[937:939], + forms[939:941], + forms[941:943], + forms[943:945], + forms[945:947], + forms[947:949], + forms[949:951], + forms[951:953], + forms[953:955], + forms[955:957], + forms[957:959], + forms[959:961], + forms[961:963], + forms[963:965], + forms[965:967], + forms[967:969], + forms[969:971], + forms[971:972], + forms[972:974], + forms[974:976], + forms[976:978], + forms[978:980], + forms[980:982], + forms[982:984], + forms[984:986], + forms[986:988], + forms[988:990], + forms[990:992], + forms[992:994], + forms[994:996], + forms[996:998], + forms[998:1000], + forms[1000:1002], + forms[1002:1004], + forms[1004:1006], + forms[1006:1008], + forms[1008:1010], + forms[1010:1012], + forms[1012:1014], + forms[1014:1016], + forms[1016:1018], + forms[1018:1020], + forms[1020:1022], + forms[1022:1024], + forms[1024:1026], + forms[1026:1028], + forms[1028:1030], + forms[1030:1032], + forms[1032:1034], + forms[1034:1036], + forms[1036:1038], + forms[1038:1040], + forms[1040:1042], + forms[1042:1044], + forms[1044:1046], + forms[1046:1048], + forms[1048:1050], + forms[1050:1052], + forms[1052:1054], + forms[1054:1056], + forms[1056:1058], + forms[1058:1060], + forms[1060:1062], + forms[1062:1064], + forms[1064:1066], + forms[1066:1068], + forms[1068:1070], + forms[1070:1072], + forms[1072:1073], + forms[1073:1075], + forms[1075:1077], + forms[1077:1079], + forms[1079:1081], + forms[1081:1083], + forms[1083:1085], + forms[1085:1087], + forms[1087:1089], + forms[1089:1091], + forms[1091:1093], + forms[1093:1095], + forms[1095:1097], + forms[1097:1099], + forms[1099:1101], + forms[1101:1103], + forms[1103:1105], + forms[1105:1107], + forms[1107:1109], + forms[1109:1111], + forms[1111:1113], + forms[1113:1115], + forms[1115:1117], + forms[1117:1119], + forms[1119:1121], + forms[1121:1123], + forms[1123:1124], + forms[1124:1125], + forms[1125:1126], + forms[1126:1127], + forms[1127:1129], + forms[1129:1131], + forms[1131:1133], + forms[1133:1135], + forms[1135:1137], + forms[1137:1139], + forms[1139:1141], + forms[1141:1143], + forms[1143:1145], + forms[1145:1146], + forms[1146:1149], + forms[1149:1150], + forms[1150:1153], + forms[1153:1156], + forms[1156:1159], + forms[1159:1162], + forms[1162:1163], + forms[1163:1166], + forms[1166:1167], + forms[1167:1170], + forms[1170:1173], + forms[1173:1175], + forms[1175:1177], + forms[1177:1179], + forms[1179:1181], + forms[1181:1183], + forms[1183:1185], + forms[1185:1187], + forms[1187:1189], + forms[1189:1191], + forms[1191:1193], + forms[1193:1195], + forms[1195:1197], + forms[1197:1199], + forms[1199:1201], + forms[1201:1203], + forms[1203:1205], + forms[1205:1207], + forms[1207:1211], + forms[1211:1213], + forms[1213:1215], + forms[1215:1221], + forms[1221:1227], + forms[1227:1233], + forms[1233:1239], + forms[1239:1241], + forms[1241:1243], + forms[1243:1249], + forms[1249:1255], + forms[1255:1261], + forms[1261:1267], + forms[1267:1270], + forms[1270:1273], + forms[1273:1274], + forms[1274:1275], + forms[1275:1276], + forms[1276:1277], + forms[1277:1278], + forms[1278:1279], + forms[1279:1285], + forms[1285:1291], + forms[1291:1297], + forms[1297:1303], + forms[1303:1309], + forms[1309:1315], + forms[1315:1321], + forms[1321:1327], + forms[1327:1329], + forms[1329:1331], + forms[1331:1333], + forms[1333:1335], + forms[1335:1337], + forms[1337:1339], + forms[1339:1341], + forms[1341:1343], + forms[1343:1349], + forms[1349:1355], + forms[1355:1361], + forms[1361:1367], + forms[1367:1373], + forms[1373:1379], + forms[1379:1385], + forms[1385:1391], + forms[1391:1393], + forms[1393:1395], + forms[1395:1401], + forms[1401:1409], + forms[1409:1417], + forms[1417:1425], + forms[1425:1427], + forms[1427:1429], + forms[1429:1431], + forms[1431:1433], + forms[1433:1435], + forms[1435:1437], + forms[1437:1439], + forms[1439:1441], + forms[1441:1443], + forms[1443:1445], + forms[1445:1447], + forms[1447:1449], + forms[1449:1451], + forms[1451:1453], + forms[1453:1455], + forms[1455:1457], + forms[1457:1458], + forms[1458:1460], + forms[1460:1462], + forms[1462:1464], + forms[1464:1466], + forms[1466:1468], + forms[1468:1470], + forms[1470:1472], + forms[1472:1478], + forms[1478:1488], + forms[1488:1498], + forms[1498:1508], + forms[1508:1510], + forms[1510:1512], + forms[1512:1518], + forms[1518:1528], + forms[1528:1538], + forms[1538:1548], + forms[1548:1550], + forms[1550:1552], + forms[1552:1554], + forms[1554:1556], + forms[1556:1558], + forms[1558:1560], + forms[1560:1562], + forms[1562:1564], + forms[1564:1565], + forms[1565:1566], + forms[1566:1567], + forms[1567:1573], + forms[1573:1581], + forms[1581:1583], + forms[1583:1585], + forms[1585:1593], + forms[1593:1595], + forms[1595:1597], + forms[1597:1605], + forms[1605:1606], + forms[1606:1611], + forms[1611:1616], + forms[1616:1621], + forms[1621:1626], + forms[1626:1628], + forms[1628:1630], + forms[1630:1632], + forms[1632:1634], + forms[1634:1636], + forms[1636:1637], + forms[1637:1639], + forms[1639:1641], + forms[1641:1643], + forms[1643:1645], + forms[1645:1675], + forms[1675:1705], + forms[1705:1714], + forms[1714:1723], + forms[1723:1727], + forms[1727:1731], + forms[1731:1733], + forms[1733:1735], + forms[1735:1737], + forms[1737:1739], + forms[1739:1741], + forms[1741:1743], + forms[1743:1770], + forms[1770:1797], + forms[1797:1824], + forms[1824:1851], + forms[1851:1878], + forms[1878:1905], + forms[1905:1932], + forms[1932:1959], + forms[1959:1963], + forms[1963:1967], + forms[1967:1971], + forms[1971:1975], + forms[1975:1976], + forms[1976:1988], + forms[1988:1994], + forms[1994:1997], + forms[1997:2003], + forms[2003:2006], + forms[2006:2007], + forms[2007:2025], + forms[2025:2031], + forms[2031:2034], + forms[2034:2040], + forms[2040:2043], + forms[2043:2055], + forms[2055:2069], + forms[2069:2093], + forms[2093:2117], + forms[2117:2125], + forms[2125:2133], + forms[2133:2136], + forms[2136:2139], + forms[2139:2157], + forms[2157:2175], + forms[2175:2202], + forms[2202:2232], + forms[2232:2244], + forms[2244:2253], + forms[2253:2262], + forms[2262:2274], + forms[2274:2283], + forms[2283:2292], + forms[2292:2322], + forms[2322:2334], + forms[2334:2343], + forms[2343:2352], + forms[2352:2382], + forms[2382:2403], + forms[2403:2433], + forms[2433:2463], + forms[2463:2484], + forms[2484:2514], + forms[2514:2544], + forms[2544:2574], + forms[2574:2604], + forms[2604:2616], + forms[2616:2625], + forms[2625:2634], + forms[2634:2637], + forms[2637:2640], + forms[2640:2649], + forms[2649:2652], + forms[2652:2655], + forms[2655:2657], + forms[2657:2660], + forms[2660:2663], + forms[2663:2666], + forms[2666:2675], + forms[2675:2678], + forms[2678:2681], + forms[2681:2684], + forms[2684:2687], + forms[2687:2699], + forms[2699:2708], + forms[2708:2717], + forms[2717:2747], + forms[2747:2759], + forms[2759:2768], + forms[2768:2777], + forms[2777:2807], + forms[2807:2837], + forms[2837:2867], + forms[2867:2897], + forms[2897:2927], + forms[2927:2930], + forms[2930:2933], + forms[2933:2936], + forms[2936:2939], + forms[2939:2942], + forms[2942:2945], + forms[2945:2948], + forms[2948:2951], + forms[2951:2978], + forms[2978:3008], + forms[3008:3038], + forms[3038:3050], + forms[3050:3059], + forms[3059:3068], + forms[3068:3070], + forms[3070:3073], + forms[3073:3076], + forms[3076:3079], + forms[3079:3097], + forms[3097:3127], + forms[3127:3157], + forms[3157:3166], + forms[3166:3175], + forms[3175:3177], + forms[3177:3181], + forms[3181:3193], + forms[3193:3205], + forms[3205:3223], + forms[3223:3241], + forms[3241:3243], + forms[3243:3255], + forms[3255:3261], + forms[3261:3273], + forms[3273:3279], + forms[3279:3281], + forms[3281:3293], + forms[3293:3299], + forms[3299:3311], + forms[3311:3317], + forms[3317:3319], + forms[3319:3349], + forms[3349:3379], + forms[3379:3388], + forms[3388:3397], + forms[3397:3427], + forms[3427:3457], + forms[3457:3466], + forms[3466:3475], + forms[3475:3505], + forms[3505:3535], + forms[3535:3544], + forms[3544:3553], + forms[3553:3583], + forms[3583:3613], + forms[3613:3622], + forms[3622:3631], + forms[3631:3661], + forms[3661:3691], + forms[3691:3721], + forms[3721:3751], + forms[3751:3781], + forms[3781:3811], + forms[3811:3841], + forms[3841:3871], + forms[3871:3880], + forms[3880:3889], + forms[3889:3919], + forms[3919:3949], + forms[3949:3958], + forms[3958:3967], + forms[3967:3997], + forms[3997:4027], + forms[4027:4036], + forms[4036:4045], + forms[4045:4075], + forms[4075:4105], + forms[4105:4135], + forms[4135:4165], + forms[4165:4195], + forms[4195:4225], + forms[4225:4255], + forms[4255:4285], + forms[4285:4294], + forms[4294:4303], + forms[4303:4333], + forms[4333:4363], + forms[4363:4372], + forms[4372:4381], + forms[4381:4411], + forms[4411:4441], + forms[4441:4450], + forms[4450:4459], + forms[4459:4489], + forms[4489:4519], + forms[4519:4528], + forms[4528:4537], + forms[4537:4567], + forms[4567:4597], + forms[4597:4606], + forms[4606:4615], + forms[4615:4645], + forms[4645:4675], + forms[4675:4684], + forms[4684:4693], + forms[4693:4699], + forms[4699:4705], + forms[4705:4711], + forms[4711:4717], + forms[4717:4723], + forms[4723:4729], + forms[4729:4733], + forms[4733:4737], + forms[4737:4742], + forms[4742:4747], + forms[4747:4752], + forms[4752:4757], + forms[4757:4787], + forms[4787:4817], + forms[4817:4826], + forms[4826:4835], + forms[4835:4865], + forms[4865:4895], + forms[4895:4904], + forms[4904:4913], + forms[4913:4917], + forms[4917:4921], + forms[4921:4925], + forms[4925:4929], + forms[4929:4931], + forms[4931:4943], + forms[4943:4949], + forms[4949:4961], + forms[4961:4967], + forms[4967:4969], + forms[4969:4981], + forms[4981:4987], + forms[4987:4999], + forms[4999:5005], + forms[5005:5007], + forms[5007:5009], + forms[5009:5010], + forms[5010:5011], + forms[5011:5015], + forms[5015:5019], + forms[5019:5049], + forms[5049:5079], + forms[5079:5088], + forms[5088:5097], + forms[5097:5127], + forms[5127:5157], + forms[5157:5166], + forms[5166:5175], + forms[5175:5202], + forms[5202:5229], + forms[5229:5233], + forms[5233:5251], + forms[5251:5257], + forms[5257:5284], + forms[5284:5311], + forms[5311:5317], + forms[5317:5344], + forms[5344:5371], + forms[5371:5398], + forms[5398:5425], + forms[5425:5426], + forms[5426:5428], + forms[5428:5430], + forms[5430:5431], + forms[5431:5433], + forms[5433:5435], + forms[5435:5437], + forms[5437:5439], + forms[5439:5442], + forms[5442:5445], + forms[5445:5448], + forms[5448:5451], + forms[5451:5456], + forms[5456:5464], + forms[5464:5482], + forms[5482:5500], + forms[5500:5508], + forms[5508:5535], + forms[5535:5562], + forms[5562:5566], + forms[5566:5596], + forms[5596:5626], + forms[5626:5635], + forms[5635:5644], + forms[5644:5671], + forms[5671:5698], + forms[5698:5716], + forms[5716:5743], + forms[5743:5770], + forms[5770:5788], + forms[5788:5815], + forms[5815:5833], + forms[5833:5860], + forms[5860:5878], + forms[5878:5896], + forms[5896:5923], + forms[5923:5950], + forms[5950:5968], + forms[5968:5986], + forms[5986:6004], + forms[6004:6022], + forms[6022:6040], + forms[6040:6058], + forms[6058:6062], + forms[6062:6089], + forms[6089:6093], + forms[6093:6120], + forms[6120:6147], + forms[6147:6174], + forms[6174:6192], + forms[6192:6210], + forms[6210:6214], + forms[6214:6232], + forms[6232:6259], + forms[6259:6286], + forms[6286:6304], + forms[6304:6308], + forms[6308:6312], + forms[6312:6339], + forms[6339:6366], + forms[6366:6369], + forms[6369:6372], + forms[6372:6399], + forms[6399:6426], + forms[6426:6428], + forms[6428:6440], + forms[6440:6458], + forms[6458:6474], + forms[6474:6496], + forms[6496:6518], + forms[6518:6534], + forms[6534:6536], + forms[6536:6538], + forms[6538:6554], + forms[6554:6576], + forms[6576:6598], + forms[6598:6614], + forms[6614:6616], + forms[6616:6618], + forms[6618:6636], + forms[6636:6648], + forms[6648:6666], + forms[6666:6684], + forms[6684:6696], + forms[6696:6708], + forms[6708:6726], + forms[6726:6744], + forms[6744:6771], + forms[6771:6798], + forms[6798:6800], + forms[6800:6802], + forms[6802:6820], + forms[6820:6838], + forms[6838:6856], + forms[6856:6883], + forms[6883:6910], + forms[6910:6937], + forms[6937:6964], + forms[6964:6982], + forms[6982:7036], + forms[7036:7090], + forms[7090:7126], + forms[7126:7144], + forms[7144:7180], + forms[7180:7198], + forms[7198:7225], + forms[7225:7252], + forms[7252:7279], + forms[7279:7306], + forms[7306:7324], + forms[7324:7342], + forms[7342:7360], + forms[7360:7378], + forms[7378:7380], + forms[7380:7382], + forms[7382:7384], + forms[7384:7386], + forms[7386:7391], + forms[7391:7396], + forms[7396:7401], + forms[7401:7406], + forms[7406:7410], + forms[7410:7414], + forms[7414:7418], + forms[7418:7420], + forms[7420:7424], + forms[7424:7428], + forms[7428:7432], + forms[7432:7434], + forms[7434:7436], + forms[7436:7438], + forms[7438:7440], + forms[7440:7467], + forms[7467:7494], + forms[7494:7521], + forms[7521:7548], + forms[7548:7566], + forms[7566:7584], + forms[7584:7588], + forms[7588:7592], + forms[7592:7610], + forms[7610:7637], + forms[7637:7664], + forms[7664:7682], + forms[7682:7700], + forms[7700:7727], + forms[7727:7754], + forms[7754:7772], + forms[7772:7790], + forms[7790:7817], + forms[7817:7844], + forms[7844:7862], + forms[7862:7880], + forms[7880:7907], + forms[7907:7934], + forms[7934:7952], + forms[7952:7955], + forms[7955:7958], + forms[7958:7976], + forms[7976:7994], + forms[7994:7997], + forms[7997:8000], + forms[8000:8003], + forms[8003:8006], + forms[8006:8008], + forms[8008:8011], + forms[8011:8029], + forms[8029:8047], + forms[8047:8065], + forms[8065:8083], + forms[8083:8101], + forms[8101:8119], + forms[8119:8137], + forms[8137:8155], + forms[8155:8173], + forms[8173:8191], + forms[8191:8209], + forms[8209:8227], + forms[8227:8245], + forms[8245:8263], + forms[8263:8281], + forms[8281:8299], + forms[8299:8317], + forms[8317:8335], + forms[8335:8353], + forms[8353:8371], + forms[8371:8389], + forms[8389:8392], + forms[8392:8410], + forms[8410:8428], + forms[8428:8446], + forms[8446:8464], + forms[8464:8482], + forms[8482:8500], + forms[8500:8518], + forms[8518:8545], + forms[8545:8563], + forms[8563:8581], + forms[8581:8599], + forms[8599:8626], + forms[8626:8653], + forms[8653:8671], + forms[8671:8698], + forms[8698:8725], + forms[8725:8734], + forms[8734:8743], + forms[8743:8747], + forms[8747:8774], + forms[8774:8801], + forms[8801:8828], + forms[8828:8855], + forms[8855:8882], + forms[8882:8909], + forms[8909:8936], + forms[8936:8963], + forms[8963:8990], + forms[8990:9017], + forms[9017:9023], + forms[9023:9026], + forms[9026:9029], + forms[9029:9032], + forms[9032:9035], + forms[9035:9053], + forms[9053:9080], + forms[9080:9098], + forms[9098:9116], + forms[9116:9120], + forms[9120:9124], + forms[9124:9128], + forms[9128:9173], + forms[9173:9179], + forms[9179:9224], + forms[9224:9251], + forms[9251:9278], + forms[9278:9296], + forms[9296:9332], + forms[9332:9377], + forms[9377:9422], + forms[9422:9449], + forms[9449:9476], + forms[9476:9494], + forms[9494:9530], + forms[9530:9575], + forms[9575:9581], + forms[9581:9626], + forms[9626:9653], + forms[9653:9680], + forms[9680:9698], + forms[9698:9734], + forms[9734:9752], + forms[9752:9779], + forms[9779:9806], + forms[9806:9824], + forms[9824:9842], + forms[9842:9860], + forms[9860:9878], + forms[9878:9896], + forms[9896:9923], + forms[9923:9950], + forms[9950:9954], + forms[9954:9966], + forms[9966:9984], + forms[9984:10002], + forms[10002:10014], + forms[10014:10026], + forms[10026:10044], + forms[10044:10062], + forms[10062:10074], + forms[10074:10092], + forms[10092:10119], + forms[10119:10146], + forms[10146:10164], + forms[10164:10182], + forms[10182:10209], + forms[10209:10236], + forms[10236:10254], + forms[10254:10258], + forms[10258:10285], + forms[10285:10312], + forms[10312:10342], + forms[10342:10372], + forms[10372:10381], + forms[10381:10390], + forms[10390:10417], + forms[10417:10444], + forms[10444:10450], + forms[10450:10456], + forms[10456:10468], + forms[10468:10480], + forms[10480:10489], + forms[10489:10498], + forms[10498:10502], + forms[10502:10504], + forms[10504:10531], + forms[10531:10558], + forms[10558:10564], + forms[10564:10570], + forms[10570:10600], + forms[10600:10630], + forms[10630:10639], + forms[10639:10648], + forms[10648:10652], + forms[10652:10656], + forms[10656:10658], + forms[10658:10660], + forms[10660:10687], + forms[10687:10714], + forms[10714:10720], + forms[10720:10726], + forms[10726:10738], + forms[10738:10750], + forms[10750:10759], + forms[10759:10768], + forms[10768:10772], + forms[10772:10774], + forms[10774:10804], + forms[10804:10834], + forms[10834:10843], + forms[10843:10852], + forms[10852:10855], + forms[10855:10858], + forms[10858:10861], + forms[10861:10864], + forms[10864:10882], + forms[10882:10900], + forms[10900:10918], + forms[10918:10936], + forms[10936:10963], + forms[10963:10990], + forms[10990:11020], + forms[11020:11050], + forms[11050:11059], + forms[11059:11068], + forms[11068:11069], + forms[11069:11099], + forms[11099:11129], + forms[11129:11138], + forms[11138:11147], + forms[11147:11151], + forms[11151:11155], + forms[11155:11158], + forms[11158:11161], + forms[11161:11188], + forms[11188:11215], + forms[11215:11242], + forms[11242:11269], + forms[11269:11296], + forms[11296:11323], + forms[11323:11324], + forms[11324:11325], + forms[11325:11327], + forms[11327:11329], + forms[11329:11331], + forms[11331:11333], + forms[11333:11336], + forms[11336:11341], + forms[11341:11346], + forms[11346:11351], + forms[11351:11352], + forms[11352:11353], + forms[11353:11359], + forms[11359:11367], + forms[11367:11369], + forms[11369:11371], + forms[11371:11379], + forms[11379:11387], +}